STRUCTURE Architecture Reference

Signals
gt0_rxpmaresetdone_i	STD_LOGIC
\^gt0_rxsyncout_i\	STD_LOGIC
\^gt0_txphinitdone_out\	STD_LOGIC
gthe2_i_n_50	STD_LOGIC
NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_CPLLLOCK_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_PHYSTATUS_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RSOSINTDONE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXCDRLOCK_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXCOMINITDET_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXCOMSASDET_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXELECIDLE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXPRBSERR_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXQPISENN_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXQPISENP_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXRATEDONE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_RXVALID_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_TXCOMFINISH_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_TXQPISENN_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_TXQPISENP_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_TXRATEDONE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_TXSYNCDONE_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_TXSYNCOUT_UNCONNECTED	STD_LOGIC
NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED	STD_LOGIC_VECTOR ( 15 downto 0 )
NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED	STD_LOGIC_VECTOR ( 2 downto 0 )
NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED	STD_LOGIC_VECTOR ( 7 downto 0 )
NLW_gthe2_i_RXCHARISK_UNCONNECTED	STD_LOGIC_VECTOR ( 7 downto 4 )
NLW_gthe2_i_RXCHBONDO_UNCONNECTED	STD_LOGIC_VECTOR ( 4 downto 0 )
NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED	STD_LOGIC_VECTOR ( 1 downto 0 )
NLW_gthe2_i_RXDATA_UNCONNECTED	STD_LOGIC_VECTOR ( 63 downto 32 )
NLW_gthe2_i_RXDATAVALID_UNCONNECTED	STD_LOGIC_VECTOR ( 1 downto 0 )
NLW_gthe2_i_RXDISPERR_UNCONNECTED	STD_LOGIC_VECTOR ( 7 downto 4 )
NLW_gthe2_i_RXHEADER_UNCONNECTED	STD_LOGIC_VECTOR ( 5 downto 0 )
NLW_gthe2_i_RXHEADERVALID_UNCONNECTED	STD_LOGIC_VECTOR ( 1 downto 0 )
NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED	STD_LOGIC_VECTOR ( 7 downto 4 )
NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED	STD_LOGIC_VECTOR ( 1 downto 0 )
NLW_gthe2_i_RXSTATUS_UNCONNECTED	STD_LOGIC_VECTOR ( 2 downto 0 )
NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED	STD_LOGIC_VECTOR ( 1 downto 0 )

Attributes
box_type	string
box_type	gthe2_i : label is " PRIMITIVE "

Member Data Documentation

\^gt0_rxsyncout_i\

\^gt0_rxsyncout_i\ STD_LOGIC

Signal

\^gt0_txphinitdone_out\

\^gt0_txphinitdone_out\ STD_LOGIC

Signal

box_type [1/2]

box_type string

Attribute

box_type [2/2]

box_type gthe2_i : label is " PRIMITIVE "

Attribute

gt0_rxpmaresetdone_i

gt0_rxpmaresetdone_i STD_LOGIC

Signal

gthe2_i_n_50

gthe2_i_n_50 STD_LOGIC

Signal

NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED

NLW_gthe2_i_CPLLFBCLKLOST_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_CPLLLOCK_UNCONNECTED

NLW_gthe2_i_CPLLLOCK_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED

NLW_gthe2_i_CPLLREFCLKLOST_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED

NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED

NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED STD_LOGIC_VECTOR ( 15 downto 0 )

Signal

NLW_gthe2_i_PHYSTATUS_UNCONNECTED

NLW_gthe2_i_PHYSTATUS_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RSOSINTDONE_UNCONNECTED

NLW_gthe2_i_RSOSINTDONE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED

NLW_gthe2_i_RXBUFSTATUS_UNCONNECTED STD_LOGIC_VECTOR ( 2 downto 0 )

Signal

NLW_gthe2_i_RXCDRLOCK_UNCONNECTED

NLW_gthe2_i_RXCDRLOCK_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED

NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED

NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED

NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED

NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED STD_LOGIC_VECTOR ( 7 downto 0 )

Signal

NLW_gthe2_i_RXCHARISK_UNCONNECTED

NLW_gthe2_i_RXCHARISK_UNCONNECTED STD_LOGIC_VECTOR ( 7 downto 4 )

Signal

NLW_gthe2_i_RXCHBONDO_UNCONNECTED

NLW_gthe2_i_RXCHBONDO_UNCONNECTED STD_LOGIC_VECTOR ( 4 downto 0 )

Signal

NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED

NLW_gthe2_i_RXCLKCORCNT_UNCONNECTED STD_LOGIC_VECTOR ( 1 downto 0 )

Signal

NLW_gthe2_i_RXCOMINITDET_UNCONNECTED

NLW_gthe2_i_RXCOMINITDET_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXCOMSASDET_UNCONNECTED

NLW_gthe2_i_RXCOMSASDET_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED

NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXDATA_UNCONNECTED

NLW_gthe2_i_RXDATA_UNCONNECTED STD_LOGIC_VECTOR ( 63 downto 32 )

Signal

NLW_gthe2_i_RXDATAVALID_UNCONNECTED

NLW_gthe2_i_RXDATAVALID_UNCONNECTED STD_LOGIC_VECTOR ( 1 downto 0 )

Signal

NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED

NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED

NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED

NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED

NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXDISPERR_UNCONNECTED

NLW_gthe2_i_RXDISPERR_UNCONNECTED STD_LOGIC_VECTOR ( 7 downto 4 )

Signal

NLW_gthe2_i_RXELECIDLE_UNCONNECTED

NLW_gthe2_i_RXELECIDLE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXHEADER_UNCONNECTED

NLW_gthe2_i_RXHEADER_UNCONNECTED STD_LOGIC_VECTOR ( 5 downto 0 )

Signal

NLW_gthe2_i_RXHEADERVALID_UNCONNECTED

NLW_gthe2_i_RXHEADERVALID_UNCONNECTED STD_LOGIC_VECTOR ( 1 downto 0 )

Signal

NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED

NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED STD_LOGIC_VECTOR ( 7 downto 4 )

Signal

NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED

NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED

NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED

NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED

NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXPRBSERR_UNCONNECTED

NLW_gthe2_i_RXPRBSERR_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXQPISENN_UNCONNECTED

NLW_gthe2_i_RXQPISENN_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXQPISENP_UNCONNECTED

NLW_gthe2_i_RXQPISENP_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXRATEDONE_UNCONNECTED

NLW_gthe2_i_RXRATEDONE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED

NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED STD_LOGIC_VECTOR ( 1 downto 0 )

Signal

NLW_gthe2_i_RXSTATUS_UNCONNECTED

NLW_gthe2_i_RXSTATUS_UNCONNECTED STD_LOGIC_VECTOR ( 2 downto 0 )

Signal

NLW_gthe2_i_RXVALID_UNCONNECTED

NLW_gthe2_i_RXVALID_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED

NLW_gthe2_i_TXBUFSTATUS_UNCONNECTED STD_LOGIC_VECTOR ( 1 downto 0 )

Signal

NLW_gthe2_i_TXCOMFINISH_UNCONNECTED

NLW_gthe2_i_TXCOMFINISH_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED

NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_TXQPISENN_UNCONNECTED

NLW_gthe2_i_TXQPISENN_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_TXQPISENP_UNCONNECTED

NLW_gthe2_i_TXQPISENP_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_TXRATEDONE_UNCONNECTED

NLW_gthe2_i_TXRATEDONE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_TXSYNCDONE_UNCONNECTED

NLW_gthe2_i_TXSYNCDONE_UNCONNECTED STD_LOGIC

Signal

NLW_gthe2_i_TXSYNCOUT_UNCONNECTED

NLW_gthe2_i_TXSYNCOUT_UNCONNECTED STD_LOGIC

Signal

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The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2_sim_netlist.vhdl