<!-- Address table for FTM DSS FPGA firmware -->

<node id="TOP">
	<node id="Common_IdVersion" module="file://ftm_common_IdVersion.xml" address="0x0" description="ID register" fwinfo = "endpoint;width=3">
	</node>

	<node id="FPGA_Control" module="file://ftm_dss_control.xml" address="0x8" description="Control Status" fwinfo = "endpoint;width=3">
	</node>

	<node id="XADC" module="file://ftm_xadc.xml" address="0x10" description="XADC conversions" fwinfo = "endpoint;width=4">
	</node>

	<node id="Reconfigure" module="file://ftm_reconfigure.xml" address="0x20" description="Reconfigure this FPGA" fwinfo = "endpoint;width=1">
	</node>

	<node id="FLASH_SPI_Ram" module="file://ftm_flash_spi_ram.xml" address="0x200" description="SPI_RAM"  fwinfo = "endpoint;width=9">
	</node>

	<node id="MGT_XCVR_Control"  module="file://ftm_dss_mgt_registers.xml" address="0x800" description="MGT Transceiver Control" fwinfo = "endpoint;width=5">
	</node>

	<node id="DSS_Buffer_Control" module="file://ftm_dss_buf_control.xml" address="0x1100" description="DSS Playback Control"  fwinfo = "endpoint;width=3">
	</node>

   <node id="MGT_Error_Counters" module="file://ftm_dss_error_counters.xml" address="0x200000" description="Rx Error counters" fwinfo = "endpoint;width=4">
   </node>

   <node id="MGT_Source_Ram" module="file://ftm_dss_source_ram.xml" address="0x400000" description="Source RAM 48" fwinfo = "endpoint;width=22"> 
   </node>

   <node id="MGT_Sink_Ram" module="file://ftm_dss_sink_ram.xml" address="0x800000" description="Sink RAM" fwinfo = "endpoint;width=22">
   </node>

</node>

