*** Running vivado with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_Control.tcl -notrace Command: link_design -top top_FTM_Control -part xc7k325tffg900-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.dcp' for cell 'mgts_115_116/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i' Netlist sorting complete. Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1970.777 ; gain = 0.000 ; free physical = 3281 ; free virtual = 19570 INFO: [Netlist 29-17] Analyzing 1399 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_115_116/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_115_116/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_117_118/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_117_118/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4] get_clocks: Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 2680.055 ; gain = 555.051 ; free physical = 2676 ; free virtual = 18966 INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:42] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_117_118_6g4_mgts.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_117_118_6g4_mgts.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_115_116_6g4_mgts.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_115_116_6g4_mgts.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2781.332 ; gain = 0.000 ; free physical = 2644 ; free virtual = 18934 INFO: [Project 1-111] Unisim Transformation Summary: A total of 60 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 4 instances OBUFDS => OBUFDS: 26 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances 15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:41 ; elapsed = 00:01:10 . Memory (MB): peak = 2781.332 ; gain = 1143.051 ; free physical = 2644 ; free virtual = 18934 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xci Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7k325t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.99 . Memory (MB): peak = 2789.336 ; gain = 8.000 ; free physical = 2642 ; free virtual = 18931 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: de38a041 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2789.336 ; gain = 0.000 ; free physical = 2600 ; free virtual = 18889 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0 INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV. INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_1 INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_1_CV. Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2970.211 ; gain = 0.000 ; free physical = 2330 ; free virtual = 18648 Phase 1 Generate And Synthesize Debug Cores | Checksum: 18b392f87 Time (s): cpu = 00:08:06 ; elapsed = 00:15:20 . Memory (MB): peak = 2970.211 ; gain = 68.879 ; free physical = 2330 ; free virtual = 18648 Phase 2 Retarget INFO: [Opt 31-138] Pushed 8 inverter(s) to 14 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1bdf1473d Time (s): cpu = 00:08:10 ; elapsed = 00:15:24 . Memory (MB): peak = 2971.211 ; gain = 69.879 ; free physical = 2359 ; free virtual = 18677 INFO: [Opt 31-389] Phase Retarget created 27 cells and removed 93 cells INFO: [Opt 31-1021] In phase Retarget, 108 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 1 inverter(s) to 11 load pin(s). Phase 3 Constant propagation | Checksum: 1a0d1a78f Time (s): cpu = 00:08:10 ; elapsed = 00:15:24 . Memory (MB): peak = 2971.211 ; gain = 69.879 ; free physical = 2359 ; free virtual = 18677 INFO: [Opt 31-389] Phase Constant propagation created 117 cells and removed 163 cells INFO: [Opt 31-1021] In phase Constant propagation, 56 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 1a54d3485 Time (s): cpu = 00:08:12 ; elapsed = 00:15:26 . Memory (MB): peak = 2971.211 ; gain = 69.879 ; free physical = 2359 ; free virtual = 18677 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 303 cells INFO: [Opt 31-1021] In phase Sweep, 1436 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 5 BUFG optimization | Checksum: 1a54d3485 Time (s): cpu = 00:08:13 ; elapsed = 00:15:27 . Memory (MB): peak = 2971.211 ; gain = 69.879 ; free physical = 2359 ; free virtual = 18676 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1a37332fa Time (s): cpu = 00:08:14 ; elapsed = 00:15:27 . Memory (MB): peak = 2971.211 ; gain = 69.879 ; free physical = 2359 ; free virtual = 18677 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 1b79ff0c3 Time (s): cpu = 00:08:14 ; elapsed = 00:15:28 . Memory (MB): peak = 2971.211 ; gain = 69.879 ; free physical = 2359 ; free virtual = 18677 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 70 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 27 | 93 | 108 | | Constant propagation | 117 | 163 | 56 | | Sweep | 6 | 303 | 1436 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 70 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2971.211 ; gain = 0.000 ; free physical = 2359 ; free virtual = 18677 Ending Logic Optimization Task | Checksum: f47519fa Time (s): cpu = 00:08:15 ; elapsed = 00:15:29 . Memory (MB): peak = 2971.211 ; gain = 69.879 ; free physical = 2359 ; free virtual = 18677 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.045 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 2 BRAM(s) out of a total of 297 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 19 newly gated: 152 Total Ports: 594 Ending PowerOpt Patch Enables Task | Checksum: 1726399ca Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3705.227 ; gain = 0.000 ; free physical = 2239 ; free virtual = 18557 Ending Power Optimization Task | Checksum: 1726399ca Time (s): cpu = 00:01:51 ; elapsed = 00:01:54 . Memory (MB): peak = 3705.227 ; gain = 734.016 ; free physical = 2290 ; free virtual = 18608 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 59bc7ae8 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3705.227 ; gain = 0.000 ; free physical = 2276 ; free virtual = 18594 Ending Final Cleanup Task | Checksum: 59bc7ae8 Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 3705.227 ; gain = 0.000 ; free physical = 2276 ; free virtual = 18594 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3705.227 ; gain = 0.000 ; free physical = 2276 ; free virtual = 18594 Ending Netlist Obfuscation Task | Checksum: 59bc7ae8 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3705.227 ; gain = 0.000 ; free physical = 2276 ; free virtual = 18594 INFO: [Common 17-83] Releasing license: Implementation 65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:10:29 ; elapsed = 00:17:50 . Memory (MB): peak = 3705.227 ; gain = 923.895 ; free physical = 2277 ; free virtual = 18594 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3705.227 ; gain = 0.000 ; free physical = 2227 ; free virtual = 18545 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3705.227 ; gain = 0.000 ; free physical = 2191 ; free virtual = 18535 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 3705.230 ; gain = 0.004 ; free physical = 2207 ; free virtual = 18534 INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx Command: report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2203 ; free virtual = 18530 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2201 ; free virtual = 18528 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 57fdf396 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2201 ; free virtual = 18528 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2201 ; free virtual = 18528 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17fcc9bf1 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2187 ; free virtual = 18514 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 22ac5fa69 Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2133 ; free virtual = 18460 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 22ac5fa69 Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2134 ; free virtual = 18460 Phase 1 Placer Initialization | Checksum: 22ac5fa69 Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2131 ; free virtual = 18458 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 18b175b29 Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2115 ; free virtual = 18442 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 580 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 233 nets or cells. Created 0 new cell, deleted 233 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2104 ; free virtual = 18431 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 233 | 233 | 0 | 1 | 00:00:01 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 233 | 233 | 0 | 7 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 11fe81353 Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2103 ; free virtual = 18430 Phase 2.2 Global Placement Core | Checksum: 15d89e441 Time (s): cpu = 00:01:20 ; elapsed = 00:01:22 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2098 ; free virtual = 18424 Phase 2 Global Placement | Checksum: 15d89e441 Time (s): cpu = 00:01:20 ; elapsed = 00:01:22 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2111 ; free virtual = 18438 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1179d113c Time (s): cpu = 00:01:25 ; elapsed = 00:01:27 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2106 ; free virtual = 18433 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: ccdb57fb Time (s): cpu = 00:01:34 ; elapsed = 00:01:37 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2103 ; free virtual = 18429 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: dfdaacae Time (s): cpu = 00:01:35 ; elapsed = 00:01:37 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2103 ; free virtual = 18429 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 14d5bed21 Time (s): cpu = 00:01:36 ; elapsed = 00:01:38 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2104 ; free virtual = 18431 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 139aa16e5 Time (s): cpu = 00:01:44 ; elapsed = 00:01:46 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2104 ; free virtual = 18431 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: ca8e4e0c Time (s): cpu = 00:01:55 ; elapsed = 00:01:58 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2079 ; free virtual = 18406 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 189007f47 Time (s): cpu = 00:01:57 ; elapsed = 00:02:00 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2080 ; free virtual = 18406 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1e425c047 Time (s): cpu = 00:01:58 ; elapsed = 00:02:00 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2080 ; free virtual = 18406 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1cc87631b Time (s): cpu = 00:02:10 ; elapsed = 00:02:13 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2076 ; free virtual = 18403 Phase 3 Detail Placement | Checksum: 1cc87631b Time (s): cpu = 00:02:10 ; elapsed = 00:02:13 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2076 ; free virtual = 18403 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1bfcc244c Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 1bfcc244c Time (s): cpu = 00:02:27 ; elapsed = 00:02:30 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2063 ; free virtual = 18390 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.327. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 10c0d1e57 Time (s): cpu = 00:03:08 ; elapsed = 00:03:12 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2066 ; free virtual = 18393 Phase 4.1 Post Commit Optimization | Checksum: 10c0d1e57 Time (s): cpu = 00:03:09 ; elapsed = 00:03:12 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2066 ; free virtual = 18393 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 10c0d1e57 Time (s): cpu = 00:03:09 ; elapsed = 00:03:13 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2073 ; free virtual = 18400 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 10c0d1e57 Time (s): cpu = 00:03:10 ; elapsed = 00:03:13 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2073 ; free virtual = 18400 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2073 ; free virtual = 18400 Phase 4.4 Final Placement Cleanup | Checksum: 1d8b57a82 Time (s): cpu = 00:03:10 ; elapsed = 00:03:13 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2074 ; free virtual = 18401 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d8b57a82 Time (s): cpu = 00:03:10 ; elapsed = 00:03:14 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2074 ; free virtual = 18401 Ending Placer Task | Checksum: 134e99951 Time (s): cpu = 00:03:10 ; elapsed = 00:03:14 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2074 ; free virtual = 18401 INFO: [Common 17-83] Releasing license: Implementation 97 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:03:14 ; elapsed = 00:03:18 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2109 ; free virtual = 18436 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2109 ; free virtual = 18436 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2049 ; free virtual = 18433 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2094 ; free virtual = 18433 INFO: [runtcl-4] Executing : report_io -file top_FTM_Control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2070 ; free virtual = 18409 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed.rpt -pb top_FTM_Control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_Control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.25 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 2089 ; free virtual = 18428 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed_1.rpt -pb top_FTM_Control_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 4d93272a ConstDB: 0 ShapeSum: e7567227 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: d1797bbd Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1814 ; free virtual = 18154 Post Restoration Checksum: NetGraph: cd67f69a NumContArr: 4118523 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: d1797bbd Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1790 ; free virtual = 18130 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: d1797bbd Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1781 ; free virtual = 18121 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: d1797bbd Time (s): cpu = 00:01:01 ; elapsed = 00:01:03 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1781 ; free virtual = 18121 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 2357c391c Time (s): cpu = 00:01:30 ; elapsed = 00:01:32 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1749 ; free virtual = 18089 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.365 | TNS=0.000 | WHS=-0.380 | THS=-847.184| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1ffcb9f5e Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1747 ; free virtual = 18087 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.365 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1e92a5096 Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1746 ; free virtual = 18086 Phase 2 Router Initialization | Checksum: 250b9f630 Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1746 ; free virtual = 18086 Router Utilization Summary Global Vertical Routing Utilization = 0.000794495 % Global Horizontal Routing Utilization = 0.00122742 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 27243 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 27241 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 152cc3cfb Time (s): cpu = 00:03:06 ; elapsed = 00:03:09 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1735 ; free virtual = 18075 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 2229 Number of Nodes with overlaps = 192 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.455 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1f1ae97e1 Time (s): cpu = 00:04:14 ; elapsed = 00:04:18 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 Phase 4 Rip-up And Reroute | Checksum: 1f1ae97e1 Time (s): cpu = 00:04:14 ; elapsed = 00:04:18 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1f1ae97e1 Time (s): cpu = 00:04:15 ; elapsed = 00:04:18 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1f1ae97e1 Time (s): cpu = 00:04:15 ; elapsed = 00:04:18 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 Phase 5 Delay and Skew Optimization | Checksum: 1f1ae97e1 Time (s): cpu = 00:04:15 ; elapsed = 00:04:19 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1df426832 Time (s): cpu = 00:04:20 ; elapsed = 00:04:23 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.148 | TNS=0.000 | WHS=0.052 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 2a56b5401 Time (s): cpu = 00:04:20 ; elapsed = 00:04:24 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 Phase 6 Post Hold Fix | Checksum: 2a56b5401 Time (s): cpu = 00:04:20 ; elapsed = 00:04:24 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1736 ; free virtual = 18076 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 3.53933 % Global Horizontal Routing Utilization = 3.90058 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1b0574b0a Time (s): cpu = 00:04:21 ; elapsed = 00:04:24 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1735 ; free virtual = 18075 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b0574b0a Time (s): cpu = 00:04:21 ; elapsed = 00:04:25 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1734 ; free virtual = 18074 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1e01e4725 Time (s): cpu = 00:04:24 ; elapsed = 00:04:28 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1732 ; free virtual = 18072 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.148 | TNS=0.000 | WHS=0.052 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 1e01e4725 Time (s): cpu = 00:04:25 ; elapsed = 00:04:28 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1737 ; free virtual = 18077 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:04:25 ; elapsed = 00:04:28 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1768 ; free virtual = 18108 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 116 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:04:30 ; elapsed = 00:04:34 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1768 ; free virtual = 18108 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_Control was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean. INFO: [Hog:ReadListFile-0] 114 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains 1C48B1F, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:ReadListFile-0] 7 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 19 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains 1c48b1f, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:Msg-0] Found last SHA for FTM_Control: 1c48b1f INFO: [Hog:Msg-0] The git SHA value 1c48b1f will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1768 ; free virtual = 18108 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1697 ; free virtual = 18105 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1750 ; free virtual = 18106 INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx Command: report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1739 ; free virtual = 18094 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1717 ; free virtual = 18072 INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx Command: report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 141 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 3705.230 ; gain = 0.000 ; free physical = 1650 ; free virtual = 18015 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_Control_route_status.rpt -pb top_FTM_Control_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_Control_timing_summary_routed.rpt -pb top_FTM_Control_timing_summary_routed.pb -rpx top_FTM_Control_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_Control_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_Control_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_Control_bus_skew_routed.rpt -pb top_FTM_Control_bus_skew_routed.pb -rpx top_FTM_Control_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx Command: report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 3716.227 ; gain = 10.996 ; free physical = 1622 ; free virtual = 17993 INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx Command: report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 153 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 3724.234 ; gain = 8.008 ; free physical = 1610 ; free virtual = 17991 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_Control_timing_summary_routed_1.rpt -pb top_FTM_Control_timing_summary_routed_1.pb -rpx top_FTM_Control_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Sun Nov 15 16:16:01 2020... *** Running vivado with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_Control.tcl -notrace Command: open_checkpoint top_FTM_Control_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1595.270 ; gain = 0.000 ; free physical = 3660 ; free virtual = 20027 INFO: [Device 21-403] Loading part xc7k325tffg900-2 Netlist sorting complete. Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1943.539 ; gain = 0.000 ; free physical = 3187 ; free virtual = 19553 INFO: [Netlist 29-17] Analyzing 1558 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2707.395 ; gain = 34.270 ; free physical = 2472 ; free virtual = 18839 Restored from archive | CPU: 3.440000 secs | Memory: 39.382362 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2707.395 ; gain = 34.270 ; free physical = 2472 ; free virtual = 18839 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2707.395 ; gain = 0.000 ; free physical = 2473 ; free virtual = 18840 INFO: [Project 1-111] Unisim Transformation Summary: A total of 138 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 96 instances IOBUF => IOBUF (IBUF, OBUFT): 4 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 8 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:00:42 ; elapsed = 00:01:19 . Memory (MB): peak = 2707.395 ; gain = 1112.129 ; free physical = 2473 ; free virtual = 18839 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_Control.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'temac_gbe_v9_0_gmii' (temac_gbe_v9_0_gmii_block) was generated with multiple features: IP feature 'eth_avb_endpoint@2015.04' was enabled using a design_linking license. IP feature 'tri_mode_eth_mac@2015.04' was enabled using a bought license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. WARNING: [DRC RTSTAT-10] No routable loads: 89 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rd_rst_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0]... and (the first 15 of 41 listed). INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 44652864 bits. Writing bitstream ./top_FTM_Control.bit... Writing bitstream ./top_FTM_Control.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Nov 15 16:20:02 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:02:07 ; elapsed = 00:02:18 . Memory (MB): peak = 3279.004 ; gain = 571.609 ; free physical = 2382 ; free virtual = 18760 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_Control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean. INFO: [Hog:ReadListFile-0] 114 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains 1C48B1F, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:ReadListFile-0] 7 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 19 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains 1c48b1f, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:Msg-0] Git describe set to: v1.0.9-4-g1c48b1f INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v1.0.9-4-g1c48b1f... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v1.0.9-4-g1c48b1f/FTM_Control-v1.0.9-4-g1c48b1f.bit...