*** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Netlist sorting complete. Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2068.508 ; gain = 1.996 ; free physical = 8331 ; free virtual = 27547 INFO: [Netlist 29-17] Analyzing 3217 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] get_clocks: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 3155.207 ; gain = 825.551 ; free physical = 7437 ; free virtual = 26653 Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3326.102 ; gain = 0.000 ; free physical = 7489 ; free virtual = 26706 INFO: [Project 1-111] Unisim Transformation Summary: A total of 10 instances were transformed. OBUFDS => OBUFDS: 10 instances 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:02 ; elapsed = 00:01:53 . Memory (MB): peak = 3326.102 ; gain = 1703.031 ; free physical = 7489 ; free virtual = 26706 source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci Sourcing Tcl File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx415t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:01 . Memory (MB): peak = 3342.109 ; gain = 8.004 ; free physical = 7486 ; free virtual = 26702 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1a4df2e1c Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3351.109 ; gain = 9.000 ; free physical = 7254 ; free virtual = 26470 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1face7bda Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3546.859 ; gain = 16.004 ; free physical = 7242 ; free virtual = 26458 INFO: [Opt 31-389] Phase Retarget created 59 cells and removed 118 cells INFO: [Opt 31-1021] In phase Retarget, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 1face7bda Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3546.859 ; gain = 16.004 ; free physical = 7242 ; free virtual = 26458 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 1a73c69b2 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3546.859 ; gain = 16.004 ; free physical = 7243 ; free virtual = 26459 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 508 cells INFO: [Opt 31-1021] In phase Sweep, 524 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 4 BUFG optimization | Checksum: 213a3e127 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3546.859 ; gain = 16.004 ; free physical = 7243 ; free virtual = 26459 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 213a3e127 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3546.859 ; gain = 16.004 ; free physical = 7243 ; free virtual = 26459 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1cb35151e Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3546.859 ; gain = 16.004 ; free physical = 7243 ; free virtual = 26459 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 59 | 118 | 49 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 508 | 524 | | BUFG optimization | 0 | 4 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3546.859 ; gain = 0.000 ; free physical = 7243 ; free virtual = 26460 Ending Logic Optimization Task | Checksum: 209239c19 Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3546.859 ; gain = 16.004 ; free physical = 7243 ; free virtual = 26460 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.483 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 643 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 16 newly gated: 8 Total Ports: 1286 Ending PowerOpt Patch Enables Task | Checksum: 157e45ea9 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4654.016 ; gain = 0.000 ; free physical = 6900 ; free virtual = 26116 Ending Power Optimization Task | Checksum: 157e45ea9 Time (s): cpu = 00:01:28 ; elapsed = 00:01:32 . Memory (MB): peak = 4654.016 ; gain = 1107.156 ; free physical = 7007 ; free virtual = 26223 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1856ff395 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4654.016 ; gain = 0.000 ; free physical = 6855 ; free virtual = 26072 Ending Final Cleanup Task | Checksum: 1856ff395 Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 4654.016 ; gain = 0.000 ; free physical = 6853 ; free virtual = 26070 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.016 ; gain = 0.000 ; free physical = 6853 ; free virtual = 26070 Ending Netlist Obfuscation Task | Checksum: 1856ff395 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.016 ; gain = 0.000 ; free physical = 6853 ; free virtual = 26070 INFO: [Common 17-83] Releasing license: Implementation 45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:13 ; elapsed = 00:02:23 . Memory (MB): peak = 4654.016 ; gain = 1327.914 ; free physical = 6857 ; free virtual = 26073 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4654.016 ; gain = 0.000 ; free physical = 6589 ; free virtual = 25805 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 4654.016 ; gain = 0.000 ; free physical = 6392 ; free virtual = 25791 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 4654.020 ; gain = 0.004 ; free physical = 6557 ; free virtual = 25792 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6553 ; free virtual = 25787 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6551 ; free virtual = 25786 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e7cba4fd Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6551 ; free virtual = 25786 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6551 ; free virtual = 25786 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cddd8c7f Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6533 ; free virtual = 25768 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: f576fb8a Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6487 ; free virtual = 25722 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: f576fb8a Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6487 ; free virtual = 25722 Phase 1 Placer Initialization | Checksum: f576fb8a Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6484 ; free virtual = 25718 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 18a7f721d Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6463 ; free virtual = 25698 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 985 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 416 nets or cells. Created 17 new cells, deleted 399 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6445 ; free virtual = 25680 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 17 | 399 | 416 | 0 | 1 | 00:00:02 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 17 | 399 | 416 | 0 | 7 | 00:00:02 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 22116f8e2 Time (s): cpu = 00:02:20 ; elapsed = 00:02:25 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6450 ; free virtual = 25685 Phase 2.2 Global Placement Core | Checksum: 158621f1c Time (s): cpu = 00:02:26 ; elapsed = 00:02:31 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6440 ; free virtual = 25675 Phase 2 Global Placement | Checksum: 158621f1c Time (s): cpu = 00:02:26 ; elapsed = 00:02:31 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6462 ; free virtual = 25697 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: c6ce51a1 Time (s): cpu = 00:02:35 ; elapsed = 00:02:40 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6454 ; free virtual = 25689 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 11344eccf Time (s): cpu = 00:02:50 ; elapsed = 00:02:56 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6449 ; free virtual = 25684 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: bd68aec6 Time (s): cpu = 00:02:51 ; elapsed = 00:02:57 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6449 ; free virtual = 25684 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: d9228b56 Time (s): cpu = 00:02:52 ; elapsed = 00:02:58 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6449 ; free virtual = 25685 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1b01f408e Time (s): cpu = 00:03:06 ; elapsed = 00:03:12 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6452 ; free virtual = 25687 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: ea8829af Time (s): cpu = 00:03:25 ; elapsed = 00:03:31 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6405 ; free virtual = 25641 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 157ce6da7 Time (s): cpu = 00:03:28 ; elapsed = 00:03:35 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6407 ; free virtual = 25643 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1804d0298 Time (s): cpu = 00:03:29 ; elapsed = 00:03:36 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6407 ; free virtual = 25643 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: ad499fa4 Time (s): cpu = 00:03:50 ; elapsed = 00:03:57 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6404 ; free virtual = 25639 Phase 3 Detail Placement | Checksum: ad499fa4 Time (s): cpu = 00:03:50 ; elapsed = 00:03:58 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6404 ; free virtual = 25639 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 11ba8a007 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 11ba8a007 Time (s): cpu = 00:04:20 ; elapsed = 00:04:28 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6207 ; free virtual = 25443 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.051. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 1e0eb4877 Time (s): cpu = 00:05:17 ; elapsed = 00:05:25 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6219 ; free virtual = 25455 Phase 4.1 Post Commit Optimization | Checksum: 1e0eb4877 Time (s): cpu = 00:05:17 ; elapsed = 00:05:25 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6220 ; free virtual = 25455 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1e0eb4877 Time (s): cpu = 00:05:18 ; elapsed = 00:05:26 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6229 ; free virtual = 25464 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1e0eb4877 Time (s): cpu = 00:05:19 ; elapsed = 00:05:27 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6229 ; free virtual = 25465 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6229 ; free virtual = 25465 Phase 4.4 Final Placement Cleanup | Checksum: 1cc4ae027 Time (s): cpu = 00:05:19 ; elapsed = 00:05:28 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6229 ; free virtual = 25465 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1cc4ae027 Time (s): cpu = 00:05:20 ; elapsed = 00:05:28 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6229 ; free virtual = 25465 Ending Placer Task | Checksum: 1817d1935 Time (s): cpu = 00:05:20 ; elapsed = 00:05:28 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6229 ; free virtual = 25465 INFO: [Common 17-83] Releasing license: Implementation 76 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:05:25 ; elapsed = 00:05:34 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6283 ; free virtual = 25519 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6283 ; free virtual = 25519 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6032 ; free virtual = 25508 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6253 ; free virtual = 25512 INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt report_io: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.45 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6226 ; free virtual = 25486 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.37 . Memory (MB): peak = 4654.020 ; gain = 0.000 ; free physical = 6250 ; free virtual = 25510 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: bd0a03b8 ConstDB: 0 ShapeSum: c473157d RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: e5b6dcd3 Time (s): cpu = 00:01:20 ; elapsed = 00:01:20 . Memory (MB): peak = 4691.406 ; gain = 37.387 ; free physical = 5908 ; free virtual = 25168 Post Restoration Checksum: NetGraph: 5f5a4062 NumContArr: 865c9c71 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: e5b6dcd3 Time (s): cpu = 00:01:21 ; elapsed = 00:01:21 . Memory (MB): peak = 4720.605 ; gain = 66.586 ; free physical = 5884 ; free virtual = 25144 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: e5b6dcd3 Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 4727.809 ; gain = 73.789 ; free physical = 5872 ; free virtual = 25133 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: e5b6dcd3 Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 4727.812 ; gain = 73.793 ; free physical = 5872 ; free virtual = 25133 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 18a5c0306 Time (s): cpu = 00:02:05 ; elapsed = 00:02:07 . Memory (MB): peak = 4831.367 ; gain = 177.348 ; free physical = 5815 ; free virtual = 25075 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.038 | TNS=0.000 | WHS=-1.008 | THS=-1821.089| Phase 2 Router Initialization | Checksum: 1414e25e8 Time (s): cpu = 00:02:15 ; elapsed = 00:02:17 . Memory (MB): peak = 4831.367 ; gain = 177.348 ; free physical = 5808 ; free virtual = 25068 Router Utilization Summary Global Vertical Routing Utilization = 0.00269664 % Global Horizontal Routing Utilization = 0.00110459 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 47165 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 47164 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: fde3d594 Time (s): cpu = 00:05:53 ; elapsed = 00:05:59 . Memory (MB): peak = 4848.070 ; gain = 194.051 ; free physical = 5790 ; free virtual = 25050 INFO: [Route 35-580] Design has 200 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][21]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][10]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[39].mgt_source_data_regd_reg[39][data][31]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[42].mgt_source_data_regd_reg[42][data][7]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[12].mgt_source_data_regd_reg[12][data][27]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 4790 Number of Nodes with overlaps = 677 Number of Nodes with overlaps = 190 Number of Nodes with overlaps = 47 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.082 | TNS=-0.082 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 14d6788f9 Time (s): cpu = 00:07:53 ; elapsed = 00:08:02 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5768 ; free virtual = 25028 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 264 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.107 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1f70fa91b Time (s): cpu = 00:08:09 ; elapsed = 00:08:18 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5777 ; free virtual = 25037 Phase 4 Rip-up And Reroute | Checksum: 1f70fa91b Time (s): cpu = 00:08:09 ; elapsed = 00:08:18 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5777 ; free virtual = 25037 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1f70fa91b Time (s): cpu = 00:08:10 ; elapsed = 00:08:19 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5777 ; free virtual = 25037 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1f70fa91b Time (s): cpu = 00:08:10 ; elapsed = 00:08:19 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5777 ; free virtual = 25037 Phase 5 Delay and Skew Optimization | Checksum: 1f70fa91b Time (s): cpu = 00:08:10 ; elapsed = 00:08:19 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5777 ; free virtual = 25037 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1bcb3a385 Time (s): cpu = 00:08:18 ; elapsed = 00:08:27 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5779 ; free virtual = 25039 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.218 | TNS=0.000 | WHS=-0.492 | THS=-0.492 | Phase 6.1 Hold Fix Iter | Checksum: 1d193169d Time (s): cpu = 00:08:18 ; elapsed = 00:08:27 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5779 ; free virtual = 25039 Phase 6 Post Hold Fix | Checksum: 17ff1f3d6 Time (s): cpu = 00:08:18 ; elapsed = 00:08:27 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5778 ; free virtual = 25038 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.52574 % Global Horizontal Routing Utilization = 7.43504 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: f847ecd2 Time (s): cpu = 00:08:19 ; elapsed = 00:08:28 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5776 ; free virtual = 25037 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f847ecd2 Time (s): cpu = 00:08:20 ; elapsed = 00:08:29 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5775 ; free virtual = 25035 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 Phase 9 Depositing Routes | Checksum: b22949d8 Time (s): cpu = 00:08:25 ; elapsed = 00:08:34 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5772 ; free virtual = 25032 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: 17ecc3be2 Time (s): cpu = 00:08:33 ; elapsed = 00:08:42 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5781 ; free virtual = 25041 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.218 | TNS=0.000 | WHS=0.057 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 17ecc3be2 Time (s): cpu = 00:08:33 ; elapsed = 00:08:42 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5781 ; free virtual = 25041 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:08:33 ; elapsed = 00:08:42 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5848 ; free virtual = 25108 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 97 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:08:43 ; elapsed = 00:08:52 . Memory (MB): peak = 4988.070 ; gain = 334.051 ; free physical = 5848 ; free virtual = 25108 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains C7D9D02, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains EAB8DF6, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:GetVerFromSHA-0] No tag contains c7d9d02, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: c7d9d02 INFO: [Hog:Msg-0] The git SHA value c7d9d02 will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4988.070 ; gain = 0.000 ; free physical = 5851 ; free virtual = 25111 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4988.070 ; gain = 0.000 ; free physical = 5572 ; free virtual = 25094 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 4988.074 ; gain = 0.004 ; free physical = 5810 ; free virtual = 25100 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 4988.074 ; gain = 0.000 ; free physical = 5789 ; free virtual = 25079 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 5083.070 ; gain = 94.996 ; free physical = 5637 ; free virtual = 24928 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 123 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:34 ; elapsed = 00:00:31 . Memory (MB): peak = 5133.086 ; gain = 50.016 ; free physical = 5425 ; free virtual = 24728 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5149.086 ; gain = 16.000 ; free physical = 5395 ; free virtual = 24706 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 5249.812 ; gain = 100.727 ; free physical = 5379 ; free virtual = 24690 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 135 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 5249.812 ; gain = 0.000 ; free physical = 5368 ; free virtual = 24692 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Sun Nov 15 16:09:35 2020... *** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: open_checkpoint top_FTM_DSS_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1595.273 ; gain = 0.000 ; free physical = 8814 ; free virtual = 28139 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 Netlist sorting complete. Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2053.270 ; gain = 0.000 ; free physical = 8234 ; free virtual = 27559 INFO: [Netlist 29-17] Analyzing 3215 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3137.684 ; gain = 63.133 ; free physical = 7228 ; free virtual = 26553 Restored from archive | CPU: 6.000000 secs | Memory: 74.705086 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3137.684 ; gain = 63.133 ; free physical = 7228 ; free virtual = 26553 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3137.684 ; gain = 0.000 ; free physical = 7232 ; free virtual = 26557 INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:01:14 ; elapsed = 00:02:15 . Memory (MB): peak = 3137.684 ; gain = 1542.414 ; free physical = 7232 ; free virtual = 26557 source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_DSS.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. INFO: [Vivado 12-3199] DRC finished with 0 Errors INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 61361792 bits. Writing bitstream ./top_FTM_DSS.bit... Writing bitstream ./top_FTM_DSS.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Nov 15 16:15:47 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:03:25 ; elapsed = 00:03:35 . Memory (MB): peak = 3832.844 ; gain = 695.160 ; free physical = 7115 ; free virtual = 26459 source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains C7D9D02, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains EAB8DF6, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:GetVerFromSHA-0] No tag contains c7d9d02, will use most recent tag v1.0.9. As this is an official tag, patch will be incremented to 10. INFO: [Hog:Msg-0] Git describe set to: v1.0.9-5-gc7d9d02 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.9-5-gc7d9d02... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.9-5-gc7d9d02/FTM_DSS-v1.0.9-5-gc7d9d02.bit...