*** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Netlist sorting complete. Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2063.684 ; gain = 0.996 ; free physical = 1378 ; free virtual = 19308 INFO: [Netlist 29-17] Analyzing 3217 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] get_clocks: Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 3086.977 ; gain = 793.160 ; free physical = 483 ; free virtual = 18413 Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3257.871 ; gain = 0.000 ; free physical = 534 ; free virtual = 18464 INFO: [Project 1-111] Unisim Transformation Summary: A total of 10 instances were transformed. OBUFDS => OBUFDS: 10 instances 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:07 ; elapsed = 00:02:04 . Memory (MB): peak = 3257.871 ; gain = 1634.805 ; free physical = 534 ; free virtual = 18464 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx415t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:01 . Memory (MB): peak = 3273.879 ; gain = 8.004 ; free physical = 533 ; free virtual = 18463 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 11fa93c52 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3281.879 ; gain = 8.000 ; free physical = 301 ; free virtual = 18231 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1b9402651 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3477.660 ; gain = 16.004 ; free physical = 287 ; free virtual = 18217 INFO: [Opt 31-389] Phase Retarget created 59 cells and removed 118 cells INFO: [Opt 31-1021] In phase Retarget, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 1b9402651 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3477.660 ; gain = 16.004 ; free physical = 287 ; free virtual = 18217 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 1e3c4c99e Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3477.660 ; gain = 16.004 ; free physical = 288 ; free virtual = 18218 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 508 cells INFO: [Opt 31-1021] In phase Sweep, 524 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 4 BUFG optimization | Checksum: 129c8cc87 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3477.660 ; gain = 16.004 ; free physical = 288 ; free virtual = 18218 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 129c8cc87 Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3477.660 ; gain = 16.004 ; free physical = 288 ; free virtual = 18218 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 2013e6d75 Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3477.660 ; gain = 16.004 ; free physical = 288 ; free virtual = 18218 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 59 | 118 | 49 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 508 | 524 | | BUFG optimization | 0 | 4 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3477.660 ; gain = 0.000 ; free physical = 289 ; free virtual = 18219 Ending Logic Optimization Task | Checksum: 15c8c0021 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 3477.660 ; gain = 16.004 ; free physical = 289 ; free virtual = 18219 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.483 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 643 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 16 newly gated: 8 Total Ports: 1286 Ending PowerOpt Patch Enables Task | Checksum: 1a25bd9f8 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4581.293 ; gain = 0.000 ; free physical = 1026 ; free virtual = 17941 Ending Power Optimization Task | Checksum: 1a25bd9f8 Time (s): cpu = 00:01:38 ; elapsed = 00:01:46 . Memory (MB): peak = 4581.293 ; gain = 1103.633 ; free physical = 1135 ; free virtual = 18050 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 111755f3e Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 4581.293 ; gain = 0.000 ; free physical = 983 ; free virtual = 17898 Ending Final Cleanup Task | Checksum: 111755f3e Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 4581.293 ; gain = 0.000 ; free physical = 981 ; free virtual = 17896 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.293 ; gain = 0.000 ; free physical = 981 ; free virtual = 17896 Ending Netlist Obfuscation Task | Checksum: 111755f3e Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.293 ; gain = 0.000 ; free physical = 981 ; free virtual = 17896 INFO: [Common 17-83] Releasing license: Implementation 45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:30 ; elapsed = 00:02:43 . Memory (MB): peak = 4581.293 ; gain = 1323.422 ; free physical = 981 ; free virtual = 17896 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4581.293 ; gain = 0.000 ; free physical = 716 ; free virtual = 17631 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.23 . Memory (MB): peak = 4581.293 ; gain = 0.000 ; free physical = 523 ; free virtual = 17620 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 4581.297 ; gain = 0.004 ; free physical = 685 ; free virtual = 17618 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 677 ; free virtual = 17612 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 676 ; free virtual = 17611 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e7cba4fd Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 676 ; free virtual = 17611 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 676 ; free virtual = 17611 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8b7be33e Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 655 ; free virtual = 17593 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 12ba1ba86 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 610 ; free virtual = 17548 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 12ba1ba86 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 609 ; free virtual = 17548 Phase 1 Placer Initialization | Checksum: 12ba1ba86 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 605 ; free virtual = 17544 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: a2f9a348 Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 585 ; free virtual = 17524 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 940 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 380 nets or cells. Created 9 new cells, deleted 371 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-46] Identified 1 candidate net for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 561 ; free virtual = 17507 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 9 | 371 | 380 | 0 | 1 | 00:00:02 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 9 | 371 | 380 | 0 | 8 | 00:00:03 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: a8edff0e Time (s): cpu = 00:02:37 ; elapsed = 00:02:43 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 564 ; free virtual = 17510 Phase 2.2 Global Placement Core | Checksum: 112a30739 Time (s): cpu = 00:02:44 ; elapsed = 00:02:50 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 553 ; free virtual = 17499 Phase 2 Global Placement | Checksum: 112a30739 Time (s): cpu = 00:02:44 ; elapsed = 00:02:50 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 575 ; free virtual = 17521 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 13d0cb2f7 Time (s): cpu = 00:02:54 ; elapsed = 00:03:00 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 567 ; free virtual = 17513 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10adcd730 Time (s): cpu = 00:03:10 ; elapsed = 00:03:17 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 563 ; free virtual = 17509 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: cb479560 Time (s): cpu = 00:03:12 ; elapsed = 00:03:18 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 562 ; free virtual = 17509 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 4bdfd81d Time (s): cpu = 00:03:13 ; elapsed = 00:03:20 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 562 ; free virtual = 17508 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 111b56ec3 Time (s): cpu = 00:03:28 ; elapsed = 00:03:35 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 564 ; free virtual = 17510 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1b19995e8 Time (s): cpu = 00:03:49 ; elapsed = 00:03:56 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 519 ; free virtual = 17465 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 15ca7f169 Time (s): cpu = 00:03:52 ; elapsed = 00:04:00 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 521 ; free virtual = 17467 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 14badb55c Time (s): cpu = 00:03:54 ; elapsed = 00:04:01 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 521 ; free virtual = 17467 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 166d3078f Time (s): cpu = 00:04:16 ; elapsed = 00:04:24 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 518 ; free virtual = 17464 Phase 3 Detail Placement | Checksum: 166d3078f Time (s): cpu = 00:04:17 ; elapsed = 00:04:25 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 518 ; free virtual = 17464 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: df3a85ea Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: df3a85ea Time (s): cpu = 00:04:50 ; elapsed = 00:04:59 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 322 ; free virtual = 17268 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.229. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 3d34f92e Time (s): cpu = 00:06:05 ; elapsed = 00:06:15 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 333 ; free virtual = 17279 Phase 4.1 Post Commit Optimization | Checksum: 3d34f92e Time (s): cpu = 00:06:06 ; elapsed = 00:06:16 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 333 ; free virtual = 17279 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 3d34f92e Time (s): cpu = 00:06:07 ; elapsed = 00:06:17 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 342 ; free virtual = 17288 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 3d34f92e Time (s): cpu = 00:06:08 ; elapsed = 00:06:18 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 342 ; free virtual = 17289 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 342 ; free virtual = 17289 Phase 4.4 Final Placement Cleanup | Checksum: c7c315a0 Time (s): cpu = 00:06:08 ; elapsed = 00:06:19 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 342 ; free virtual = 17289 Phase 4 Post Placement Optimization and Clean-Up | Checksum: c7c315a0 Time (s): cpu = 00:06:09 ; elapsed = 00:06:19 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 342 ; free virtual = 17289 Ending Placer Task | Checksum: c6a7d472 Time (s): cpu = 00:06:09 ; elapsed = 00:06:19 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 342 ; free virtual = 17289 INFO: [Common 17-83] Releasing license: Implementation 79 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:06:15 ; elapsed = 00:06:26 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 398 ; free virtual = 17344 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 398 ; free virtual = 17344 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 146 ; free virtual = 17334 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 364 ; free virtual = 17334 INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt report_io: Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.50 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 337 ; free virtual = 17308 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.42 . Memory (MB): peak = 4581.297 ; gain = 0.000 ; free physical = 363 ; free virtual = 17334 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 161cb425 ConstDB: 0 ShapeSum: b08b204d RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 48b600e7 Time (s): cpu = 00:01:31 ; elapsed = 00:01:32 . Memory (MB): peak = 4618.684 ; gain = 37.387 ; free physical = 153 ; free virtual = 17002 Post Restoration Checksum: NetGraph: 3d7027e0 NumContArr: b45d907 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 48b600e7 Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 4647.883 ; gain = 66.586 ; free physical = 128 ; free virtual = 16977 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 48b600e7 Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 4654.887 ; gain = 73.590 ; free physical = 117 ; free virtual = 16965 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 48b600e7 Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 4654.887 ; gain = 73.590 ; free physical = 117 ; free virtual = 16965 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 16ec0fdfb Time (s): cpu = 00:02:23 ; elapsed = 00:02:26 . Memory (MB): peak = 4760.441 ; gain = 179.145 ; free physical = 214 ; free virtual = 16917 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.117 | TNS=0.000 | WHS=-1.008 | THS=-1860.432| Phase 2 Router Initialization | Checksum: 16c3475e3 Time (s): cpu = 00:02:33 ; elapsed = 00:02:36 . Memory (MB): peak = 4760.441 ; gain = 179.145 ; free physical = 204 ; free virtual = 16910 Router Utilization Summary Global Vertical Routing Utilization = 0.000282794 % Global Horizontal Routing Utilization = 0.00313242 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 47271 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 47270 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 1254f2364 Time (s): cpu = 00:08:31 ; elapsed = 00:08:40 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 258 ; free virtual = 16888 INFO: [Route 35-580] Design has 153 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][2]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[18].mgt_source_data_regd_reg[18][data][28]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][3]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[19].mgt_source_data_regd_reg[19][data][18]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[20].mgt_source_data_regd_reg[20][data][11]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 3946 Number of Nodes with overlaps = 390 Number of Nodes with overlaps = 161 Number of Nodes with overlaps = 71 Number of Nodes with overlaps = 38 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.097 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1dce2323a Time (s): cpu = 00:10:56 ; elapsed = 00:11:09 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 251 ; free virtual = 16884 Phase 4 Rip-up And Reroute | Checksum: 1dce2323a Time (s): cpu = 00:10:56 ; elapsed = 00:11:09 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 251 ; free virtual = 16884 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1dce2323a Time (s): cpu = 00:10:56 ; elapsed = 00:11:10 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 251 ; free virtual = 16884 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1dce2323a Time (s): cpu = 00:10:57 ; elapsed = 00:11:10 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 251 ; free virtual = 16884 Phase 5 Delay and Skew Optimization | Checksum: 1dce2323a Time (s): cpu = 00:10:57 ; elapsed = 00:11:10 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 251 ; free virtual = 16884 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 16e1dc510 Time (s): cpu = 00:11:06 ; elapsed = 00:11:19 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 253 ; free virtual = 16886 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.141 | TNS=0.000 | WHS=-0.492 | THS=-0.672 | Phase 6.1 Hold Fix Iter | Checksum: 26f484955 Time (s): cpu = 00:11:07 ; elapsed = 00:11:21 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 247 ; free virtual = 16885 Phase 6 Post Hold Fix | Checksum: 26a7df16b Time (s): cpu = 00:11:07 ; elapsed = 00:11:21 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 248 ; free virtual = 16885 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.3227 % Global Horizontal Routing Utilization = 7.85792 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 2b6190e3c Time (s): cpu = 00:11:09 ; elapsed = 00:11:22 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 246 ; free virtual = 16883 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 2b6190e3c Time (s): cpu = 00:11:09 ; elapsed = 00:11:23 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 245 ; free virtual = 16883 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 Phase 9 Depositing Routes | Checksum: 282ff4ffc Time (s): cpu = 00:11:15 ; elapsed = 00:11:29 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 241 ; free virtual = 16878 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: 2263df0ef Time (s): cpu = 00:11:25 ; elapsed = 00:11:39 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 250 ; free virtual = 16887 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.141 | TNS=0.000 | WHS=0.057 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 2263df0ef Time (s): cpu = 00:11:25 ; elapsed = 00:11:39 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 250 ; free virtual = 16887 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:11:25 ; elapsed = 00:11:39 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 311 ; free virtual = 16949 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 99 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:11:36 ; elapsed = 00:11:51 . Memory (MB): peak = 4876.293 ; gain = 294.996 ; free physical = 310 ; free virtual = 16950 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains F0E7603, will use most recent tag v1.0.10. As this is an official tag, patch will be incremented to 11. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains f0e7603, will use most recent tag v1.0.10. As this is an official tag, patch will be incremented to 11. INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: f0e7603 INFO: [Hog:Msg-0] The git SHA value f0e7603 will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4876.293 ; gain = 0.000 ; free physical = 309 ; free virtual = 16950 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 4876.293 ; gain = 0.000 ; free physical = 136 ; free virtual = 16943 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 4876.297 ; gain = 0.004 ; free physical = 390 ; free virtual = 16946 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 4876.297 ; gain = 0.000 ; free physical = 374 ; free virtual = 16930 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:58 ; elapsed = 00:01:02 . Memory (MB): peak = 5015.293 ; gain = 138.996 ; free physical = 316 ; free virtual = 16778 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 124 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 5061.301 ; gain = 46.008 ; free physical = 155 ; free virtual = 16586 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5077.301 ; gain = 16.000 ; free physical = 156 ; free virtual = 16566 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 5179.105 ; gain = 101.805 ; free physical = 244 ; free virtual = 16551 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 136 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 5179.105 ; gain = 0.000 ; free physical = 236 ; free virtual = 16556 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5179.105 ; gain = 0.000 ; free physical = 232 ; free virtual = 16553 INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Thu Nov 19 14:06:02 2020... *** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: open_checkpoint top_FTM_DSS_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.39 . Memory (MB): peak = 1594.270 ; gain = 0.000 ; free physical = 3402 ; free virtual = 20002 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 Netlist sorting complete. Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2048.992 ; gain = 0.000 ; free physical = 2811 ; free virtual = 19422 INFO: [Netlist 29-17] Analyzing 3215 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3100.945 ; gain = 62.133 ; free physical = 1803 ; free virtual = 18416 Restored from archive | CPU: 6.390000 secs | Memory: 74.849274 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3100.945 ; gain = 62.133 ; free physical = 1803 ; free virtual = 18416 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3100.945 ; gain = 0.000 ; free physical = 1808 ; free virtual = 18421 INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:01:17 ; elapsed = 00:02:34 . Memory (MB): peak = 3100.945 ; gain = 1506.680 ; free physical = 1808 ; free virtual = 18420 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_DSS.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. INFO: [Vivado 12-3199] DRC finished with 0 Errors INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 60008608 bits. Writing bitstream ./top_FTM_DSS.bit... Writing bitstream ./top_FTM_DSS.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Nov 19 14:13:58 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:03:51 ; elapsed = 00:04:04 . Memory (MB): peak = 3779.285 ; gain = 678.340 ; free physical = 1680 ; free virtual = 18323 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains F0E7603, will use most recent tag v1.0.10. As this is an official tag, patch will be incremented to 11. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains f0e7603, will use most recent tag v1.0.10. As this is an official tag, patch will be incremented to 11. INFO: [Hog:Msg-0] Git describe set to: v1.0.10-2-gf0e7603 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.10-2-gf0e7603... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.10-2-gf0e7603/FTM_DSS-v1.0.10-2-gf0e7603.bit...