*** Running vivado with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_Control.tcl -notrace Command: link_design -top top_FTM_Control -part xc7k325tffg900-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.dcp' for cell 'mgts_115_116/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i' Netlist sorting complete. Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1972.191 ; gain = 0.000 ; free physical = 2840 ; free virtual = 19571 INFO: [Netlist 29-17] Analyzing 1463 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_115_116/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_115_116/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_117_118/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xdc] for cell 'mgts_117_118/CON_2Quads_6g4_support_i/CON_2Quads_6g4_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4] get_clocks: Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 2682.461 ; gain = 556.043 ; free physical = 2235 ; free virtual = 18966 INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:42] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_117_118_6g4_mgts.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_117_118_6g4_mgts.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_115_116_6g4_mgts.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/CON_115_116_6g4_mgts.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:41] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2783.738 ; gain = 0.000 ; free physical = 2202 ; free virtual = 18934 INFO: [Project 1-111] Unisim Transformation Summary: A total of 60 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 4 instances OBUFDS => OBUFDS: 26 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances 15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:41 ; elapsed = 00:01:10 . Memory (MB): peak = 2783.738 ; gain = 1145.012 ; free physical = 2202 ; free virtual = 18934 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/CON_2Quads_6g4.xci Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7k325t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/CON_2Quads_6g4/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:01 . Memory (MB): peak = 2791.742 ; gain = 8.000 ; free physical = 2200 ; free virtual = 18932 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1394c3d7f Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2791.742 ; gain = 0.000 ; free physical = 2159 ; free virtual = 18890 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0 INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV. Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2983.617 ; gain = 0.000 ; free physical = 1897 ; free virtual = 18639 Phase 1 Generate And Synthesize Debug Cores | Checksum: d7e3c86b Time (s): cpu = 00:05:49 ; elapsed = 00:10:21 . Memory (MB): peak = 2983.617 ; gain = 80.879 ; free physical = 1897 ; free virtual = 18639 Phase 2 Retarget INFO: [Opt 31-138] Pushed 8 inverter(s) to 14 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1c263cc1f Time (s): cpu = 00:05:53 ; elapsed = 00:10:25 . Memory (MB): peak = 2987.617 ; gain = 84.879 ; free physical = 1931 ; free virtual = 18672 INFO: [Opt 31-389] Phase Retarget created 23 cells and removed 103 cells INFO: [Opt 31-1021] In phase Retarget, 89 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 1 inverter(s) to 11 load pin(s). Phase 3 Constant propagation | Checksum: 118b2f015 Time (s): cpu = 00:05:53 ; elapsed = 00:10:25 . Memory (MB): peak = 2987.617 ; gain = 84.879 ; free physical = 1930 ; free virtual = 18672 INFO: [Opt 31-389] Phase Constant propagation created 117 cells and removed 147 cells INFO: [Opt 31-1021] In phase Constant propagation, 53 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 16d766075 Time (s): cpu = 00:05:55 ; elapsed = 00:10:27 . Memory (MB): peak = 2987.617 ; gain = 84.879 ; free physical = 1929 ; free virtual = 18671 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 233 cells INFO: [Opt 31-1021] In phase Sweep, 1082 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 5 BUFG optimization | Checksum: 16d766075 Time (s): cpu = 00:05:56 ; elapsed = 00:10:28 . Memory (MB): peak = 2987.617 ; gain = 84.879 ; free physical = 1930 ; free virtual = 18671 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 114a077bf Time (s): cpu = 00:05:57 ; elapsed = 00:10:29 . Memory (MB): peak = 2987.617 ; gain = 84.879 ; free physical = 1930 ; free virtual = 18671 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 16942bd45 Time (s): cpu = 00:05:57 ; elapsed = 00:10:29 . Memory (MB): peak = 2987.617 ; gain = 84.879 ; free physical = 1930 ; free virtual = 18671 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 67 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 23 | 103 | 89 | | Constant propagation | 117 | 147 | 53 | | Sweep | 6 | 233 | 1082 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 67 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2987.617 ; gain = 0.000 ; free physical = 1930 ; free virtual = 18671 Ending Logic Optimization Task | Checksum: ff519151 Time (s): cpu = 00:05:58 ; elapsed = 00:10:30 . Memory (MB): peak = 2987.617 ; gain = 84.879 ; free physical = 1930 ; free virtual = 18671 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.045 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 296 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 18 newly gated: 152 Total Ports: 592 Ending PowerOpt Patch Enables Task | Checksum: 1fc6a4410 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3725.695 ; gain = 0.000 ; free physical = 1806 ; free virtual = 18548 Ending Power Optimization Task | Checksum: 1fc6a4410 Time (s): cpu = 00:01:52 ; elapsed = 00:01:55 . Memory (MB): peak = 3725.695 ; gain = 738.078 ; free physical = 1858 ; free virtual = 18600 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 181c62da7 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3725.695 ; gain = 0.000 ; free physical = 1843 ; free virtual = 18585 Ending Final Cleanup Task | Checksum: 181c62da7 Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3725.695 ; gain = 0.000 ; free physical = 1843 ; free virtual = 18585 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.695 ; gain = 0.000 ; free physical = 1843 ; free virtual = 18585 Ending Netlist Obfuscation Task | Checksum: 181c62da7 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.695 ; gain = 0.000 ; free physical = 1843 ; free virtual = 18585 INFO: [Common 17-83] Releasing license: Implementation 60 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:08:14 ; elapsed = 00:12:53 . Memory (MB): peak = 3725.695 ; gain = 941.957 ; free physical = 1845 ; free virtual = 18587 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.695 ; gain = 0.000 ; free physical = 1791 ; free virtual = 18532 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3725.695 ; gain = 0.000 ; free physical = 1750 ; free virtual = 18520 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 3725.699 ; gain = 0.004 ; free physical = 1768 ; free virtual = 18520 INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx Command: report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1762 ; free virtual = 18514 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1760 ; free virtual = 18512 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ae605e22 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1760 ; free virtual = 18512 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1760 ; free virtual = 18512 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c076fa49 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1746 ; free virtual = 18498 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1a133ee4c Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1681 ; free virtual = 18433 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1a133ee4c Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1681 ; free virtual = 18433 Phase 1 Placer Initialization | Checksum: 1a133ee4c Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1678 ; free virtual = 18430 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1f9c5c81a Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1661 ; free virtual = 18413 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 662 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 244 nets or cells. Created 0 new cell, deleted 244 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1652 ; free virtual = 18404 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 244 | 244 | 0 | 1 | 00:00:01 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 244 | 244 | 0 | 7 | 00:00:02 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 17ca75b62 Time (s): cpu = 00:01:27 ; elapsed = 00:01:30 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1649 ; free virtual = 18401 Phase 2.2 Global Placement Core | Checksum: 16591c62f Time (s): cpu = 00:01:30 ; elapsed = 00:01:33 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1643 ; free virtual = 18395 Phase 2 Global Placement | Checksum: 16591c62f Time (s): cpu = 00:01:30 ; elapsed = 00:01:33 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1657 ; free virtual = 18409 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 15937e60d Time (s): cpu = 00:01:36 ; elapsed = 00:01:39 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1652 ; free virtual = 18404 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18dc53c16 Time (s): cpu = 00:01:46 ; elapsed = 00:01:50 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1647 ; free virtual = 18399 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 191bb5777 Time (s): cpu = 00:01:47 ; elapsed = 00:01:51 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1647 ; free virtual = 18399 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1c4017211 Time (s): cpu = 00:01:48 ; elapsed = 00:01:51 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1649 ; free virtual = 18401 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1a22c1cc4 Time (s): cpu = 00:01:57 ; elapsed = 00:02:01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1649 ; free virtual = 18401 Phase 3.6 Small Shape Detail Placement Phase 3.6.1 Place Remaining Phase 3.6.1 Place Remaining | Checksum: fa2484b8 Time (s): cpu = 00:02:10 ; elapsed = 00:02:14 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1611 ; free virtual = 18363 Phase 3.6 Small Shape Detail Placement | Checksum: fa2484b8 Time (s): cpu = 00:02:10 ; elapsed = 00:02:14 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1622 ; free virtual = 18375 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: fb2a0e84 Time (s): cpu = 00:02:12 ; elapsed = 00:02:16 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1624 ; free virtual = 18376 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1c4e747ef Time (s): cpu = 00:02:13 ; elapsed = 00:02:17 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1624 ; free virtual = 18376 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1e2f99d39 Time (s): cpu = 00:02:27 ; elapsed = 00:02:31 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1623 ; free virtual = 18375 Phase 3 Detail Placement | Checksum: 1e2f99d39 Time (s): cpu = 00:02:27 ; elapsed = 00:02:32 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1623 ; free virtual = 18375 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 2854a0037 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 2854a0037 Time (s): cpu = 00:02:46 ; elapsed = 00:02:51 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1607 ; free virtual = 18359 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.219. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 22f11ef4c Time (s): cpu = 00:03:27 ; elapsed = 00:03:32 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1610 ; free virtual = 18362 Phase 4.1 Post Commit Optimization | Checksum: 22f11ef4c Time (s): cpu = 00:03:27 ; elapsed = 00:03:33 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1610 ; free virtual = 18362 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 22f11ef4c Time (s): cpu = 00:03:28 ; elapsed = 00:03:33 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1617 ; free virtual = 18369 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 22f11ef4c Time (s): cpu = 00:03:28 ; elapsed = 00:03:34 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1617 ; free virtual = 18370 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1619 ; free virtual = 18371 Phase 4.4 Final Placement Cleanup | Checksum: 20d4c72ba Time (s): cpu = 00:03:29 ; elapsed = 00:03:34 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1619 ; free virtual = 18371 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20d4c72ba Time (s): cpu = 00:03:29 ; elapsed = 00:03:34 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1619 ; free virtual = 18371 Ending Placer Task | Checksum: 141fa443c Time (s): cpu = 00:03:29 ; elapsed = 00:03:34 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1619 ; free virtual = 18371 INFO: [Common 17-83] Releasing license: Implementation 92 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:03:33 ; elapsed = 00:03:39 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1658 ; free virtual = 18410 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1658 ; free virtual = 18410 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1588 ; free virtual = 18406 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1640 ; free virtual = 18405 INFO: [runtcl-4] Executing : report_io -file top_FTM_Control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.50 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1616 ; free virtual = 18383 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed.rpt -pb top_FTM_Control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_Control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1635 ; free virtual = 18402 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed_1.rpt -pb top_FTM_Control_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 930772f0 ConstDB: 0 ShapeSum: aef2d14c RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: d830cbf8 Time (s): cpu = 00:01:01 ; elapsed = 00:01:01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1357 ; free virtual = 18124 Post Restoration Checksum: NetGraph: 3e94144f NumContArr: 999cb7a9 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: d830cbf8 Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1333 ; free virtual = 18100 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: d830cbf8 Time (s): cpu = 00:01:02 ; elapsed = 00:01:02 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1324 ; free virtual = 18091 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: d830cbf8 Time (s): cpu = 00:01:02 ; elapsed = 00:01:03 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1324 ; free virtual = 18091 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1a542538a Time (s): cpu = 00:01:32 ; elapsed = 00:01:34 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1291 ; free virtual = 18058 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.251 | TNS=0.000 | WHS=-0.385 | THS=-1207.470| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 190267563 Time (s): cpu = 00:01:44 ; elapsed = 00:01:46 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1286 ; free virtual = 18053 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.251 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 19542c7ec Time (s): cpu = 00:01:44 ; elapsed = 00:01:46 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1285 ; free virtual = 18052 Phase 2 Router Initialization | Checksum: 1341ab4f5 Time (s): cpu = 00:01:44 ; elapsed = 00:01:46 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1285 ; free virtual = 18052 Router Utilization Summary Global Vertical Routing Utilization = 0.00219905 % Global Horizontal Routing Utilization = 0.00356647 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 30183 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 30181 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 18b161fda Time (s): cpu = 00:03:37 ; elapsed = 00:03:40 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1271 ; free virtual = 18038 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 2846 Number of Nodes with overlaps = 234 Number of Nodes with overlaps = 38 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.455 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 20efcbefb Time (s): cpu = 00:04:26 ; elapsed = 00:04:30 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 Phase 4 Rip-up And Reroute | Checksum: 20efcbefb Time (s): cpu = 00:04:26 ; elapsed = 00:04:31 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 20efcbefb Time (s): cpu = 00:04:26 ; elapsed = 00:04:31 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 20efcbefb Time (s): cpu = 00:04:26 ; elapsed = 00:04:31 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 Phase 5 Delay and Skew Optimization | Checksum: 20efcbefb Time (s): cpu = 00:04:26 ; elapsed = 00:04:31 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 245405220 Time (s): cpu = 00:04:32 ; elapsed = 00:04:37 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.148 | TNS=0.000 | WHS=0.055 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 19a9bfd74 Time (s): cpu = 00:04:32 ; elapsed = 00:04:37 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 Phase 6 Post Hold Fix | Checksum: 19a9bfd74 Time (s): cpu = 00:04:32 ; elapsed = 00:04:37 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 3.7169 % Global Horizontal Routing Utilization = 4.07251 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1a8de85d8 Time (s): cpu = 00:04:33 ; elapsed = 00:04:38 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1273 ; free virtual = 18040 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a8de85d8 Time (s): cpu = 00:04:33 ; elapsed = 00:04:38 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1272 ; free virtual = 18039 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 19b5db7d3 Time (s): cpu = 00:04:37 ; elapsed = 00:04:41 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1269 ; free virtual = 18036 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.148 | TNS=0.000 | WHS=0.055 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 19b5db7d3 Time (s): cpu = 00:04:37 ; elapsed = 00:04:42 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1274 ; free virtual = 18041 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:04:37 ; elapsed = 00:04:42 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1306 ; free virtual = 18073 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 111 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:04:43 ; elapsed = 00:04:48 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1307 ; free virtual = 18073 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_Control was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean. INFO: [Hog:ReadListFile-0] 114 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains 1B6E0E2, will use most recent tag v1.0.12. As this is an official tag, patch will be incremented to 13. INFO: [Hog:ReadListFile-0] 7 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 19 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains 1b6e0e2, will use most recent tag v1.0.12. As this is an official tag, patch will be incremented to 13. INFO: [Hog:Msg-0] Found last SHA for FTM_Control: 1b6e0e2 INFO: [Hog:Msg-0] The git SHA value 1b6e0e2 will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1307 ; free virtual = 18074 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1227 ; free virtual = 18071 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1289 ; free virtual = 18073 INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx Command: report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 3725.699 ; gain = 0.000 ; free physical = 1278 ; free virtual = 18062 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 3750.695 ; gain = 24.996 ; free physical = 1250 ; free virtual = 18034 INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx Command: report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 136 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3750.695 ; gain = 0.000 ; free physical = 1181 ; free virtual = 17976 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_Control_route_status.rpt -pb top_FTM_Control_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_Control_timing_summary_routed.rpt -pb top_FTM_Control_timing_summary_routed.pb -rpx top_FTM_Control_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_Control_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_Control_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_Control_bus_skew_routed.rpt -pb top_FTM_Control_bus_skew_routed.pb -rpx top_FTM_Control_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx Command: report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 3769.094 ; gain = 18.398 ; free physical = 1149 ; free virtual = 17950 INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx Command: report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 148 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 3769.094 ; gain = 0.000 ; free physical = 1137 ; free virtual = 17948 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_Control_timing_summary_routed_1.rpt -pb top_FTM_Control_timing_summary_routed_1.pb -rpx top_FTM_Control_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Thu Nov 26 22:19:48 2020... *** Running vivado with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_Control.tcl -notrace Command: open_checkpoint top_FTM_Control_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1552.031 ; gain = 0.000 ; free physical = 3239 ; free virtual = 20031 INFO: [Device 21-403] Loading part xc7k325tffg900-2 Netlist sorting complete. Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1947.203 ; gain = 0.000 ; free physical = 2761 ; free virtual = 19553 INFO: [Netlist 29-17] Analyzing 2434 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2726.934 ; gain = 41.238 ; free physical = 2030 ; free virtual = 18822 Restored from archive | CPU: 3.980000 secs | Memory: 44.406685 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2726.934 ; gain = 41.238 ; free physical = 2030 ; free virtual = 18822 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2726.934 ; gain = 0.000 ; free physical = 2033 ; free virtual = 18825 INFO: [Project 1-111] Unisim Transformation Summary: A total of 638 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 564 instances IOBUF => IOBUF (IBUF, OBUFT): 4 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 8 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances RAM64M => RAM64M (RAMD64E(x4)): 32 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:00:44 ; elapsed = 00:01:22 . Memory (MB): peak = 2726.934 ; gain = 1174.906 ; free physical = 2033 ; free virtual = 18825 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_Control.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems. Evaluation cores found in this design: IP core 'temac_gbe_v9_0_gmii' (temac_gbe_v9_0_gmii_block) was generated with multiple features: IP feature 'eth_avb_endpoint@2015.04' was enabled using a design_linking license. IP feature 'tri_mode_eth_mac@2015.04' was enabled using a bought license. Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. WARNING: [DRC RTSTAT-10] No routable loads: 79 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rd_rst_reg[2:0]... and (the first 15 of 31 listed). INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 44261024 bits. Writing bitstream ./top_FTM_Control.bit... Writing bitstream ./top_FTM_Control.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Nov 26 22:23:55 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:02:09 ; elapsed = 00:02:19 . Memory (MB): peak = 3301.574 ; gain = 574.641 ; free physical = 1936 ; free virtual = 18739 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_Control... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean. INFO: [Hog:ReadListFile-0] 114 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains 1B6E0E2, will use most recent tag v1.0.12. As this is an official tag, patch will be incremented to 13. INFO: [Hog:ReadListFile-0] 7 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 19 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains 1b6e0e2, will use most recent tag v1.0.12. As this is an official tag, patch will be incremented to 13. INFO: [Hog:Msg-0] Git describe set to: v1.0.12-1-g1b6e0e2 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v1.0.12-1-g1b6e0e2... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v1.0.12-1-g1b6e0e2/FTM_Control-v1.0.12-1-g1b6e0e2.bit...