*** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Netlist sorting complete. Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2063.688 ; gain = 0.996 ; free physical = 3362 ; free virtual = 19587 INFO: [Netlist 29-17] Analyzing 3217 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] get_clocks: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 3086.355 ; gain = 792.535 ; free physical = 2446 ; free virtual = 18693 Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3257.250 ; gain = 0.000 ; free physical = 2487 ; free virtual = 18745 INFO: [Project 1-111] Unisim Transformation Summary: A total of 10 instances were transformed. OBUFDS => OBUFDS: 10 instances 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:05 ; elapsed = 00:02:05 . Memory (MB): peak = 3257.250 ; gain = 1634.180 ; free physical = 2487 ; free virtual = 18745 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx415t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:01 . Memory (MB): peak = 3273.258 ; gain = 8.004 ; free physical = 2481 ; free virtual = 18743 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: fd062c48 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3282.258 ; gain = 9.000 ; free physical = 2243 ; free virtual = 18510 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1330e86f1 Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3478.008 ; gain = 16.004 ; free physical = 2222 ; free virtual = 18496 INFO: [Opt 31-389] Phase Retarget created 59 cells and removed 118 cells INFO: [Opt 31-1021] In phase Retarget, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 1330e86f1 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3478.008 ; gain = 16.004 ; free physical = 2222 ; free virtual = 18496 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 12be78bb2 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3478.008 ; gain = 16.004 ; free physical = 2224 ; free virtual = 18497 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 508 cells INFO: [Opt 31-1021] In phase Sweep, 524 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 4 BUFG optimization | Checksum: 1a0835d57 Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3478.008 ; gain = 16.004 ; free physical = 2224 ; free virtual = 18497 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 1a0835d57 Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3478.008 ; gain = 16.004 ; free physical = 2224 ; free virtual = 18497 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1e8a27ab8 Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3478.008 ; gain = 16.004 ; free physical = 2224 ; free virtual = 18498 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 59 | 118 | 49 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 508 | 524 | | BUFG optimization | 0 | 4 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3478.008 ; gain = 0.000 ; free physical = 2224 ; free virtual = 18498 Ending Logic Optimization Task | Checksum: 1311afa52 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3478.008 ; gain = 16.004 ; free physical = 2224 ; free virtual = 18498 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.475 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 643 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 16 newly gated: 8 Total Ports: 1286 Ending PowerOpt Patch Enables Task | Checksum: 13ff96724 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4580.648 ; gain = 0.000 ; free physical = 1878 ; free virtual = 18159 Ending Power Optimization Task | Checksum: 13ff96724 Time (s): cpu = 00:01:36 ; elapsed = 00:01:44 . Memory (MB): peak = 4580.648 ; gain = 1102.641 ; free physical = 1985 ; free virtual = 18266 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 11d02c767 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4580.648 ; gain = 0.000 ; free physical = 1825 ; free virtual = 18113 Ending Final Cleanup Task | Checksum: 11d02c767 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 4580.648 ; gain = 0.000 ; free physical = 1823 ; free virtual = 18111 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4580.648 ; gain = 0.000 ; free physical = 1823 ; free virtual = 18111 Ending Netlist Obfuscation Task | Checksum: 11d02c767 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4580.648 ; gain = 0.000 ; free physical = 1823 ; free virtual = 18111 INFO: [Common 17-83] Releasing license: Implementation 45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:27 ; elapsed = 00:02:40 . Memory (MB): peak = 4580.648 ; gain = 1323.398 ; free physical = 1823 ; free virtual = 18111 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4580.648 ; gain = 0.000 ; free physical = 1560 ; free virtual = 17848 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 4580.648 ; gain = 0.000 ; free physical = 1362 ; free virtual = 17834 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 4580.652 ; gain = 0.004 ; free physical = 1528 ; free virtual = 17836 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1515 ; free virtual = 17829 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1512 ; free virtual = 17827 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e7cba4fd Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1512 ; free virtual = 17827 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1512 ; free virtual = 17827 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8b7be33e Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1488 ; free virtual = 17809 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 10deae519 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1442 ; free virtual = 17764 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 10deae519 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1445 ; free virtual = 17766 Phase 1 Placer Initialization | Checksum: 10deae519 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1442 ; free virtual = 17763 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: e7b9a78c Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1419 ; free virtual = 17741 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 1013 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 415 nets or cells. Created 15 new cells, deleted 400 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-46] Identified 6 candidate nets for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-665] Processed cell slaves/rx_bufs/bufgen[5].rxbuf/rx_check/dssram/ram_reg_0. 4 registers were pushed out. INFO: [Physopt 32-665] Processed cell slaves/rx_bufs/bufgen[1].rxbuf/rx_check/dssram/ram_reg_4. 4 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 8 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1397 ; free virtual = 17722 INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1397 ; free virtual = 17723 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 15 | 400 | 415 | 0 | 1 | 00:00:02 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 8 | 0 | 2 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 23 | 400 | 417 | 0 | 8 | 00:00:03 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 1a01c5c01 Time (s): cpu = 00:02:20 ; elapsed = 00:02:25 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1401 ; free virtual = 17726 Phase 2.2 Global Placement Core | Checksum: 1630b6d0b Time (s): cpu = 00:02:25 ; elapsed = 00:02:31 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1391 ; free virtual = 17716 Phase 2 Global Placement | Checksum: 1630b6d0b Time (s): cpu = 00:02:26 ; elapsed = 00:02:31 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1413 ; free virtual = 17738 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 12db57bef Time (s): cpu = 00:02:36 ; elapsed = 00:02:42 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1406 ; free virtual = 17732 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: f49c4656 Time (s): cpu = 00:02:52 ; elapsed = 00:02:58 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1401 ; free virtual = 17727 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 8cb6d3f5 Time (s): cpu = 00:02:53 ; elapsed = 00:02:59 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1401 ; free virtual = 17726 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 101d9b6ec Time (s): cpu = 00:02:54 ; elapsed = 00:03:01 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1400 ; free virtual = 17725 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 14f61f927 Time (s): cpu = 00:03:09 ; elapsed = 00:03:17 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1402 ; free virtual = 17731 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 13397e90a Time (s): cpu = 00:03:31 ; elapsed = 00:03:38 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1357 ; free virtual = 17685 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 105af1b86 Time (s): cpu = 00:03:34 ; elapsed = 00:03:42 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1359 ; free virtual = 17687 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 93f3d88e Time (s): cpu = 00:03:36 ; elapsed = 00:03:43 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1359 ; free virtual = 17687 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 9b95085e Time (s): cpu = 00:03:57 ; elapsed = 00:04:05 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1356 ; free virtual = 17684 Phase 3 Detail Placement | Checksum: 9b95085e Time (s): cpu = 00:03:58 ; elapsed = 00:04:06 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1356 ; free virtual = 17684 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 224306929 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 224306929 Time (s): cpu = 00:04:31 ; elapsed = 00:04:40 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1157 ; free virtual = 17485 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.182. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 13c3d007e Time (s): cpu = 00:05:36 ; elapsed = 00:05:45 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1169 ; free virtual = 17498 Phase 4.1 Post Commit Optimization | Checksum: 13c3d007e Time (s): cpu = 00:05:37 ; elapsed = 00:05:46 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1169 ; free virtual = 17498 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 13c3d007e Time (s): cpu = 00:05:38 ; elapsed = 00:05:47 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1178 ; free virtual = 17507 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 13c3d007e Time (s): cpu = 00:05:39 ; elapsed = 00:05:48 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1179 ; free virtual = 17508 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1179 ; free virtual = 17508 Phase 4.4 Final Placement Cleanup | Checksum: 12795d74b Time (s): cpu = 00:05:39 ; elapsed = 00:05:49 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1179 ; free virtual = 17508 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 12795d74b Time (s): cpu = 00:05:40 ; elapsed = 00:05:49 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1179 ; free virtual = 17508 Ending Placer Task | Checksum: c9fa44e6 Time (s): cpu = 00:05:40 ; elapsed = 00:05:49 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1179 ; free virtual = 17507 INFO: [Common 17-83] Releasing license: Implementation 80 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:05:46 ; elapsed = 00:05:56 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1234 ; free virtual = 17562 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1234 ; free virtual = 17562 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 979 ; free virtual = 17549 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1201 ; free virtual = 17554 INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt report_io: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.51 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1175 ; free virtual = 17528 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.38 . Memory (MB): peak = 4580.652 ; gain = 0.000 ; free physical = 1199 ; free virtual = 17553 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 196f2499 ConstDB: 0 ShapeSum: b08b204d RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: afb570d2 Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 4617.039 ; gain = 36.387 ; free physical = 852 ; free virtual = 17211 Post Restoration Checksum: NetGraph: 199a37a5 NumContArr: 961b392d Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: afb570d2 Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4646.238 ; gain = 65.586 ; free physical = 825 ; free virtual = 17186 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: afb570d2 Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4653.441 ; gain = 72.789 ; free physical = 812 ; free virtual = 17174 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: afb570d2 Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 4653.445 ; gain = 72.793 ; free physical = 812 ; free virtual = 17174 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 70751f7e Time (s): cpu = 00:02:19 ; elapsed = 00:02:22 . Memory (MB): peak = 4806.000 ; gain = 225.348 ; free physical = 752 ; free virtual = 17114 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.057 | TNS=0.000 | WHS=-1.008 | THS=-1859.112| Phase 2 Router Initialization | Checksum: 1e22ff424 Time (s): cpu = 00:02:29 ; elapsed = 00:02:32 . Memory (MB): peak = 4806.000 ; gain = 225.348 ; free physical = 744 ; free virtual = 17106 Router Utilization Summary Global Vertical Routing Utilization = 0.00333293 % Global Horizontal Routing Utilization = 0.000989185 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 47264 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 47263 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 10cb46f94 Time (s): cpu = 00:08:10 ; elapsed = 00:08:18 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 725 ; free virtual = 17087 INFO: [Route 35-580] Design has 196 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[40].mgt_source_data_regd_reg[40][ctrl][0]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[17].mgt_source_data_regd_reg[17][data][27]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[44].mgt_source_data_regd_reg[44][data][26]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[14].mgt_source_data_regd_reg[14][data][8]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[18].mgt_source_data_regd_reg[18][data][24]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 4947 Number of Nodes with overlaps = 839 Number of Nodes with overlaps = 210 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.043 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1e8c7c900 Time (s): cpu = 00:10:46 ; elapsed = 00:10:59 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 709 ; free virtual = 17071 Phase 4 Rip-up And Reroute | Checksum: 1e8c7c900 Time (s): cpu = 00:10:46 ; elapsed = 00:11:00 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 709 ; free virtual = 17071 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 16f8a2292 Time (s): cpu = 00:10:53 ; elapsed = 00:11:06 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 711 ; free virtual = 17073 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.131 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 16f8a2292 Time (s): cpu = 00:10:53 ; elapsed = 00:11:07 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 711 ; free virtual = 17074 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 16f8a2292 Time (s): cpu = 00:10:54 ; elapsed = 00:11:07 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 711 ; free virtual = 17074 Phase 5 Delay and Skew Optimization | Checksum: 16f8a2292 Time (s): cpu = 00:10:54 ; elapsed = 00:11:07 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 711 ; free virtual = 17074 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1ba2365fd Time (s): cpu = 00:11:02 ; elapsed = 00:11:16 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 719 ; free virtual = 17082 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.131 | TNS=0.000 | WHS=-0.492 | THS=-0.492 | Phase 6.1 Hold Fix Iter | Checksum: 1fcba4f42 Time (s): cpu = 00:11:03 ; elapsed = 00:11:16 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 719 ; free virtual = 17082 Phase 6 Post Hold Fix | Checksum: 20114e865 Time (s): cpu = 00:11:03 ; elapsed = 00:11:16 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 719 ; free virtual = 17081 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.27114 % Global Horizontal Routing Utilization = 7.69784 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 15cf94634 Time (s): cpu = 00:11:04 ; elapsed = 00:11:18 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 717 ; free virtual = 17080 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15cf94634 Time (s): cpu = 00:11:05 ; elapsed = 00:11:18 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 716 ; free virtual = 17079 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 Phase 9 Depositing Routes | Checksum: a7b7c710 Time (s): cpu = 00:11:11 ; elapsed = 00:11:24 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 712 ; free virtual = 17074 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: c63f7f10 Time (s): cpu = 00:11:19 ; elapsed = 00:11:33 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 720 ; free virtual = 17082 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.131 | TNS=0.000 | WHS=0.058 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: c63f7f10 Time (s): cpu = 00:11:20 ; elapsed = 00:11:33 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 720 ; free virtual = 17082 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:11:20 ; elapsed = 00:11:33 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 784 ; free virtual = 17147 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 101 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:11:30 ; elapsed = 00:11:45 . Memory (MB): peak = 4895.000 ; gain = 314.348 ; free physical = 784 ; free virtual = 17147 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains 3E2D36C, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:GetVerFromSHA-0] No tag contains 3E2D36C, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:GetVerFromSHA-0] No tag contains 3E2D36C, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains 3e2d36c, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: 3e2d36c INFO: [Hog:Msg-0] The git SHA value 3e2d36c will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4895.000 ; gain = 0.000 ; free physical = 786 ; free virtual = 17149 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4895.000 ; gain = 0.000 ; free physical = 508 ; free virtual = 17133 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 4895.004 ; gain = 0.004 ; free physical = 746 ; free virtual = 17138 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 4895.004 ; gain = 0.000 ; free physical = 728 ; free virtual = 17120 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:55 ; elapsed = 00:00:57 . Memory (MB): peak = 5015.000 ; gain = 119.996 ; free physical = 573 ; free virtual = 16965 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 128 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 5061.008 ; gain = 46.008 ; free physical = 363 ; free virtual = 16768 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5078.008 ; gain = 17.000 ; free physical = 332 ; free virtual = 16747 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 5178.734 ; gain = 100.727 ; free physical = 315 ; free virtual = 16730 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 140 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 5178.734 ; gain = 0.000 ; free physical = 306 ; free virtual = 16734 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5178.734 ; gain = 0.000 ; free physical = 302 ; free virtual = 16731 INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Fri Dec 4 16:18:00 2020... *** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: open_checkpoint top_FTM_DSS_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1554.156 ; gain = 0.000 ; free physical = 3750 ; free virtual = 20179 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 Netlist sorting complete. Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2049.199 ; gain = 0.000 ; free physical = 3170 ; free virtual = 19599 INFO: [Netlist 29-17] Analyzing 3215 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3101.535 ; gain = 63.133 ; free physical = 2164 ; free virtual = 18593 Restored from archive | CPU: 6.200000 secs | Memory: 74.862617 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3101.535 ; gain = 63.133 ; free physical = 2164 ; free virtual = 18593 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3101.535 ; gain = 0.000 ; free physical = 2170 ; free virtual = 18598 INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:01:16 ; elapsed = 00:02:24 . Memory (MB): peak = 3101.535 ; gain = 1547.383 ; free physical = 2169 ; free virtual = 18598 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_DSS.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. INFO: [Vivado 12-3199] DRC finished with 0 Errors INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 60407456 bits. Writing bitstream ./top_FTM_DSS.bit... Writing bitstream ./top_FTM_DSS.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Dec 4 16:24:52 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:03:50 ; elapsed = 00:04:02 . Memory (MB): peak = 3779.844 ; gain = 678.309 ; free physical = 2044 ; free virtual = 18499 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:GetVerFromSHA-0] No tag contains 3E2D36C, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:GetVerFromSHA-0] No tag contains 3E2D36C, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:GetVerFromSHA-0] No tag contains 3E2D36C, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:GetVerFromSHA-0] No tag contains 3e2d36c, will use most recent tag v1.0.13. As this is an official tag, patch will be incremented to 14. INFO: [Hog:Msg-0] Git describe set to: v1.0.13-1-g3e2d36c INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.13-1-g3e2d36c... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.13-1-g3e2d36c/FTM_DSS-v1.0.13-1-g3e2d36c.bit...