*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i'
Netlist sorting complete. Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2067.492 ; gain = 0.996 ; free physical = 7571 ; free virtual = 28040
INFO: [Netlist 29-17] Analyzing 3217 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
get_clocks: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 3156.160 ; gain = 826.551 ; free physical = 6677 ; free virtual = 27146
WARNING: [Vivado 12-180] No cells matched '*ttc_synch_reg'. [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:33]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_cells -hierarchical *ttc_synch_reg]'. [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:33]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3327.055 ; gain = 0.000 ; free physical = 6728 ; free virtual = 27197
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 10 instances were transformed.
  OBUFDS => OBUFDS: 10 instances

10 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:55 . Memory (MB): peak = 3327.055 ; gain = 1704.133 ; free physical = 6729 ; free virtual = 27197
source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Parsing TCL File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci
Sourcing Tcl File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx415t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:01 . Memory (MB): peak = 3343.062 ; gain = 8.004 ; free physical = 6725 ; free virtual = 27194

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1bdc5f4ab

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3352.062 ; gain = 9.000 ; free physical = 6494 ; free virtual = 26963

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 60427fb1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3546.812 ; gain = 16.004 ; free physical = 6481 ; free virtual = 26950
INFO: [Opt 31-389] Phase Retarget created 59 cells and removed 166 cells
INFO: [Opt 31-1021] In phase Retarget, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 60427fb1

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3546.812 ; gain = 16.004 ; free physical = 6481 ; free virtual = 26950
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 101cff0a1

Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3546.812 ; gain = 16.004 ; free physical = 6483 ; free virtual = 26952
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 508 cells
INFO: [Opt 31-1021] In phase Sweep, 524 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 BUFG optimization
INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
Phase 4 BUFG optimization | Checksum: 155379ede

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3546.812 ; gain = 16.004 ; free physical = 6483 ; free virtual = 26952
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 155379ede

Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3546.812 ; gain = 16.004 ; free physical = 6483 ; free virtual = 26952
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: e43a8db8

Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3546.812 ; gain = 16.004 ; free physical = 6483 ; free virtual = 26952
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              59  |             166  |                                             49  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |             508  |                                            524  |
|  BUFG optimization            |               0  |               4  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              1  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3546.812 ; gain = 0.000 ; free physical = 6483 ; free virtual = 26952
Ending Logic Optimization Task | Checksum: 16735471f

Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 3546.812 ; gain = 16.004 ; free physical = 6483 ; free virtual = 26952

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.475 | TNS=0.000 |
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 643 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 16 newly gated: 8 Total Ports: 1286
Ending PowerOpt Patch Enables Task | Checksum: 1176f6082

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4654.461 ; gain = 0.000 ; free physical = 6140 ; free virtual = 26609
Ending Power Optimization Task | Checksum: 1176f6082

Time (s): cpu = 00:01:29 ; elapsed = 00:01:34 . Memory (MB): peak = 4654.461 ; gain = 1107.648 ; free physical = 6248 ; free virtual = 26717

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 19459ad37

Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4654.461 ; gain = 0.000 ; free physical = 6096 ; free virtual = 26565
Ending Final Cleanup Task | Checksum: 19459ad37

Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 4654.461 ; gain = 0.000 ; free physical = 6094 ; free virtual = 26563

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.461 ; gain = 0.000 ; free physical = 6094 ; free virtual = 26563
Ending Netlist Obfuscation Task | Checksum: 19459ad37

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.461 ; gain = 0.000 ; free physical = 6094 ; free virtual = 26563
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:02:17 ; elapsed = 00:02:26 . Memory (MB): peak = 4654.461 ; gain = 1327.406 ; free physical = 6099 ; free virtual = 26567
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-35] Done setting XDC timing constraints.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.461 ; gain = 0.000 ; free physical = 5829 ; free virtual = 26298
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.15 . Memory (MB): peak = 4654.461 ; gain = 0.000 ; free physical = 5633 ; free virtual = 26284
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 4654.465 ; gain = 0.004 ; free physical = 5798 ; free virtual = 26285
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5792 ; free virtual = 26280
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5789 ; free virtual = 26277
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a105874f

Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5789 ; free virtual = 26277
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5789 ; free virtual = 26277

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b2d8aa2f

Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5772 ; free virtual = 26259

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1001feef0

Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5727 ; free virtual = 26215

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1001feef0

Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5729 ; free virtual = 26216
Phase 1 Placer Initialization | Checksum: 1001feef0

Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5726 ; free virtual = 26213

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 17881e74f

Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5705 ; free virtual = 26192

Phase 2.2 Global Placement Core

Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-1018] Found 1009 candidate LUT instances to create LUTNM shape
INFO: [Physopt 32-775] End 1 Pass. Optimized 396 nets or cells. Created 5 new cells, deleted 391 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5686 ; free virtual = 26173

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            5  |            391  |                   396  |           0  |           1  |  00:00:02  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            5  |            391  |                   396  |           0  |           7  |  00:00:03  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2.1 Physical Synthesis In Placer | Checksum: 17c224440

Time (s): cpu = 00:02:26 ; elapsed = 00:02:31 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5689 ; free virtual = 26176
Phase 2.2 Global Placement Core | Checksum: 226aee334

Time (s): cpu = 00:02:31 ; elapsed = 00:02:36 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5679 ; free virtual = 26167
Phase 2 Global Placement | Checksum: 226aee334

Time (s): cpu = 00:02:31 ; elapsed = 00:02:36 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5701 ; free virtual = 26188

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1a0863045

Time (s): cpu = 00:02:40 ; elapsed = 00:02:46 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5694 ; free virtual = 26181

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13e3224f3

Time (s): cpu = 00:02:56 ; elapsed = 00:03:02 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5689 ; free virtual = 26176

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 10c81cb63

Time (s): cpu = 00:02:57 ; elapsed = 00:03:03 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5689 ; free virtual = 26176

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 95acf125

Time (s): cpu = 00:02:58 ; elapsed = 00:03:04 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5689 ; free virtual = 26177

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: e048f47e

Time (s): cpu = 00:03:13 ; elapsed = 00:03:20 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5691 ; free virtual = 26179

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1a0f03a21

Time (s): cpu = 00:03:32 ; elapsed = 00:03:39 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5646 ; free virtual = 26133

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 182bdd741

Time (s): cpu = 00:03:36 ; elapsed = 00:03:43 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5648 ; free virtual = 26136

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 188383420

Time (s): cpu = 00:03:37 ; elapsed = 00:03:44 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5648 ; free virtual = 26136

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 1d7d1bb7f

Time (s): cpu = 00:03:57 ; elapsed = 00:04:05 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5645 ; free virtual = 26132
Phase 3 Detail Placement | Checksum: 1d7d1bb7f

Time (s): cpu = 00:03:58 ; elapsed = 00:04:06 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5645 ; free virtual = 26132

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1e9ad03fd

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1e9ad03fd

Time (s): cpu = 00:04:29 ; elapsed = 00:04:37 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5445 ; free virtual = 25933
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.218. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 2248e4bf5

Time (s): cpu = 00:05:33 ; elapsed = 00:05:41 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5458 ; free virtual = 25945
Phase 4.1 Post Commit Optimization | Checksum: 2248e4bf5

Time (s): cpu = 00:05:33 ; elapsed = 00:05:42 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5458 ; free virtual = 25945

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 2248e4bf5

Time (s): cpu = 00:05:35 ; elapsed = 00:05:43 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5467 ; free virtual = 25954

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 2248e4bf5

Time (s): cpu = 00:05:35 ; elapsed = 00:05:44 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5467 ; free virtual = 25955

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5467 ; free virtual = 25955
Phase 4.4 Final Placement Cleanup | Checksum: 1ec6b778b

Time (s): cpu = 00:05:36 ; elapsed = 00:05:44 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5468 ; free virtual = 25955
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ec6b778b

Time (s): cpu = 00:05:36 ; elapsed = 00:05:45 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5467 ; free virtual = 25955
Ending Placer Task | Checksum: 13a3bd879

Time (s): cpu = 00:05:36 ; elapsed = 00:05:45 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5467 ; free virtual = 25955
INFO: [Common 17-83] Releasing license: Implementation
76 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:05:42 ; elapsed = 00:05:51 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5522 ; free virtual = 26009
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5522 ; free virtual = 26009
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5268 ; free virtual = 25996
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5489 ; free virtual = 26001
INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.45 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5463 ; free virtual = 25975
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.36 . Memory (MB): peak = 4654.465 ; gain = 0.000 ; free physical = 5487 ; free virtual = 25999
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: 7cd50f40 ConstDB: 0 ShapeSum: bd66c939 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 9d230c30

Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 4691.852 ; gain = 37.387 ; free physical = 5147 ; free virtual = 25659
Post Restoration Checksum: NetGraph: 265d6052 NumContArr: 76c5abde Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 9d230c30

Time (s): cpu = 00:01:22 ; elapsed = 00:01:22 . Memory (MB): peak = 4721.051 ; gain = 66.586 ; free physical = 5123 ; free virtual = 25635

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 9d230c30

Time (s): cpu = 00:01:23 ; elapsed = 00:01:23 . Memory (MB): peak = 4728.254 ; gain = 73.789 ; free physical = 5111 ; free virtual = 25623

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 9d230c30

Time (s): cpu = 00:01:23 ; elapsed = 00:01:23 . Memory (MB): peak = 4728.258 ; gain = 73.793 ; free physical = 5111 ; free virtual = 25623
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 16b5f1469

Time (s): cpu = 00:02:10 ; elapsed = 00:02:12 . Memory (MB): peak = 4830.812 ; gain = 176.348 ; free physical = 5053 ; free virtual = 25565
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.097  | TNS=0.000  | WHS=-0.618 | THS=-1983.133|

Phase 2 Router Initialization | Checksum: 1367c075e

Time (s): cpu = 00:02:19 ; elapsed = 00:02:21 . Memory (MB): peak = 4830.812 ; gain = 176.348 ; free physical = 5046 ; free virtual = 25558

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00166646 %
  Global Horizontal Routing Utilization  = 0.00397323 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 47225
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 47224
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 12918432b

Time (s): cpu = 00:07:54 ; elapsed = 00:08:00 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5028 ; free virtual = 25540
INFO: [Route 35-580] Design has 181 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
|       Launch Clock       |      Capture Clock       |                                                 Pin                                                      |
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[46].mgt_source_data_regd_reg[46][data][16]/D|
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[19].mgt_source_data_regd_reg[19][data][12]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[43].mgt_source_data_regd_reg[43][data][28]/D|
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[20].mgt_source_data_regd_reg[20][data][21]/D|
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[18].mgt_source_data_regd_reg[18][data][22]/D|
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 5138
 Number of Nodes with overlaps = 761
 Number of Nodes with overlaps = 188
 Number of Nodes with overlaps = 73
 Number of Nodes with overlaps = 24
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.144  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1ce9a290f

Time (s): cpu = 00:09:48 ; elapsed = 00:09:56 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5012 ; free virtual = 25524
Phase 4 Rip-up And Reroute | Checksum: 1ce9a290f

Time (s): cpu = 00:09:48 ; elapsed = 00:09:56 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5012 ; free virtual = 25524

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1ce9a290f

Time (s): cpu = 00:09:48 ; elapsed = 00:09:57 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5012 ; free virtual = 25524

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1ce9a290f

Time (s): cpu = 00:09:49 ; elapsed = 00:09:57 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5012 ; free virtual = 25524
Phase 5 Delay and Skew Optimization | Checksum: 1ce9a290f

Time (s): cpu = 00:09:49 ; elapsed = 00:09:57 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5012 ; free virtual = 25524

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 157124c4f

Time (s): cpu = 00:09:58 ; elapsed = 00:10:06 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5014 ; free virtual = 25526
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.144  | TNS=0.000  | WHS=0.051  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 157124c4f

Time (s): cpu = 00:09:58 ; elapsed = 00:10:06 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5014 ; free virtual = 25526
Phase 6 Post Hold Fix | Checksum: 157124c4f

Time (s): cpu = 00:09:58 ; elapsed = 00:10:07 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5014 ; free virtual = 25526

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 5.10466 %
  Global Horizontal Routing Utilization  = 7.50823 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 204575420

Time (s): cpu = 00:09:59 ; elapsed = 00:10:08 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5012 ; free virtual = 25524

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 204575420

Time (s): cpu = 00:09:59 ; elapsed = 00:10:08 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5010 ; free virtual = 25523

Phase 9 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1
Phase 9 Depositing Routes | Checksum: 22e7a22f0

Time (s): cpu = 00:10:06 ; elapsed = 00:10:14 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5007 ; free virtual = 25519

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.144  | TNS=0.000  | WHS=0.051  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 22e7a22f0

Time (s): cpu = 00:10:06 ; elapsed = 00:10:15 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5019 ; free virtual = 25531
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:10:06 ; elapsed = 00:10:15 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5084 ; free virtual = 25597

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
96 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:10:16 ; elapsed = 00:10:25 . Memory (MB): peak = 5027.516 ; gain = 373.051 ; free physical = 5085 ; free virtual = 25597
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1
INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified...
INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware clean.
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src.
INFO: [Hog:GetVerFromSHA-0] No tag contains 4BCAC42, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con.
INFO: [Hog:GetVerFromSHA-0] No tag contains FC9CCE2, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:GetVerFromSHA-0] No tag contains FC9CCE2, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst.
INFO: [Hog:GetVerFromSHA-0] No tag contains 4bcac42, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: 4bcac42
INFO: [Hog:Msg-0] The git SHA value 4bcac42 will be set as bitstream USERID.
INFO: [Hog:Msg-0] All done.
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5027.516 ; gain = 0.000 ; free physical = 5087 ; free virtual = 25599
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5027.516 ; gain = 0.000 ; free physical = 4814 ; free virtual = 25589
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 5027.520 ; gain = 0.004 ; free physical = 5051 ; free virtual = 25594
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 5027.520 ; gain = 0.000 ; free physical = 5034 ; free virtual = 25577
INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 5086.516 ; gain = 58.996 ; free physical = 4875 ; free virtual = 25417
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
123 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 5135.531 ; gain = 49.016 ; free physical = 4664 ; free virtual = 25220
INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5152.531 ; gain = 17.000 ; free physical = 4634 ; free virtual = 25197
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 5254.258 ; gain = 101.727 ; free physical = 4617 ; free virtual = 25180
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
135 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 5254.258 ; gain = 0.000 ; free physical = 4609 ; free virtual = 25185
INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5254.258 ; gain = 0.000 ; free physical = 4605 ; free virtual = 25182
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
INFO: [Common 17-206] Exiting Vivado at Wed Dec 30 19:21:54 2020...

*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: open_checkpoint top_FTM_DSS_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1554.156 ; gain = 0.000 ; free physical = 8056 ; free virtual = 28633
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
Netlist sorting complete. Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2052.805 ; gain = 0.000 ; free physical = 7477 ; free virtual = 28054
INFO: [Netlist 29-17] Analyzing 3215 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3137.199 ; gain = 63.133 ; free physical = 6470 ; free virtual = 27047
Restored from archive | CPU: 5.790000 secs | Memory: 74.958801 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3137.199 ; gain = 63.133 ; free physical = 6470 ; free virtual = 27047
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3137.199 ; gain = 0.000 ; free physical = 6474 ; free virtual = 27051
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 2 instances were transformed.
  SRLC32E => SRL16E: 2 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876
open_checkpoint: Time (s): cpu = 00:01:14 ; elapsed = 00:02:17 . Memory (MB): peak = 3137.199 ; gain = 1583.047 ; free physical = 6474 ; free virtual = 27051
source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: write_bitstream -force top_FTM_DSS.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 60373920 bits.
Writing bitstream ./top_FTM_DSS.bit...
Writing bitstream ./top_FTM_DSS.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Dec 30 19:28:08 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:03:24 ; elapsed = 00:03:34 . Memory (MB): peak = 3832.359 ; gain = 695.160 ; free physical = 6356 ; free virtual = 26952
source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1
INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src.
INFO: [Hog:GetVerFromSHA-0] No tag contains 4BCAC42, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con.
INFO: [Hog:GetVerFromSHA-0] No tag contains FC9CCE2, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:GetVerFromSHA-0] No tag contains FC9CCE2, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst.
INFO: [Hog:GetVerFromSHA-0] No tag contains 4bcac42, will use most recent tag v1.0.16. As this is an official tag, patch will be incremented to 17.
INFO: [Hog:Msg-0] Git describe set to: v1.0.16-5-g4bcac42
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.16-5-g4bcac42...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.16-5-g4bcac42/FTM_DSS-v1.0.16-5-g4bcac42.bit...