<!-- FPGA_Control -->
	<node fwinfo = "endpoint;width=3">
		<node id="control_reg" address="0x0" permission="rw" >
            <node id="monitor_channel"  mask="0x3F0000" />
        </node>
		<node id="pulse_reg"   address="0x1" permission="rw" />
		<node id="status"      address="0x2" permission="r" >
            <node id="run_signal"  mask="0x01" />
        </node>
	</node>


