<!-- FTM Control FPGA MGT source RAM -->
<node  fwinfo = "endpoint;width=20"> 
   <node id="source_ram_00" address="0x000000" mode="block" size="0x2000" description="Quad117 Ch0"  />
   <node id="contrl_ram_00" address="0x002000" mode="block" size="0x2000" description="Quad117 Ch0"  />
   <node id="source_ram_01" address="0x010000" mode="block" size="0x2000" description="Quad117 Ch1"  />
   <node id="contrl_ram_01" address="0x012000" mode="block" size="0x2000" description="Quad117 Ch1"  />
   <node id="source_ram_02" address="0x020000" mode="block" size="0x2000" description="Quad117 Ch2"  />
   <node id="contrl_ram_02" address="0x022000" mode="block" size="0x2000" description="Quad117 Ch2"  />
   <node id="source_ram_03" address="0x030000" mode="block" size="0x2000" description="Quad117 Ch3"  />
   <node id="contrl_ram_03" address="0x032000" mode="block" size="0x2000" description="Quad117 Ch3"  />
   <node id="source_ram_04" address="0x040000" mode="block" size="0x2000" description="Quad118 Ch0"  />
   <node id="contrl_ram_04" address="0x042000" mode="block" size="0x2000" description="Quad118 Ch0"  />
   <node id="source_ram_05" address="0x050000" mode="block" size="0x2000" description="Quad118 Ch1"  />
   <node id="contrl_ram_05" address="0x052000" mode="block" size="0x2000" description="Quad118 Ch1"  />
   <node id="source_ram_06" address="0x060000" mode="block" size="0x2000" description="Quad118 Ch2"  />
   <node id="contrl_ram_06" address="0x062000" mode="block" size="0x2000" description="Quad118 Ch2"  />
   <node id="source_ram_07" address="0x070000" mode="block" size="0x2000" description="Quad118 Ch3"  />
   <node id="contrl_ram_07" address="0x072000" mode="block" size="0x2000" description="Quad118 Ch3"  />
   <node id="source_ram_08" address="0x080000" mode="block" size="0x2000" description="Quad115 Ch0"  />
   <node id="contrl_ram_08" address="0x082000" mode="block" size="0x2000" description="Quad115 Ch0"  />
   <node id="source_ram_09" address="0x090000" mode="block" size="0x2000" description="Quad115 Ch1"  />
   <node id="contrl_ram_09" address="0x092000" mode="block" size="0x2000" description="Quad115 Ch1"  />
   <node id="source_ram_10" address="0x0A0000" mode="block" size="0x2000" description="Quad115 Ch2"  />
   <node id="contrl_ram_10" address="0x0A2000" mode="block" size="0x2000" description="Quad115 Ch2"  />
   <node id="source_ram_11" address="0x0B0000" mode="block" size="0x2000" description="Quad115 Ch3"  />
   <node id="contrl_ram_11" address="0x0B2000" mode="block" size="0x2000" description="Quad115 Ch3"  />
   <node id="source_ram_12" address="0x0C0000" mode="block" size="0x2000" description="Quad116 Ch0"  />
   <node id="contrl_ram_12" address="0x0C2000" mode="block" size="0x2000" description="Quad116 Ch0"  />
   <node id="source_ram_13" address="0x0D0000" mode="block" size="0x2000" description="Quad116 Ch1"  />
   <node id="contrl_ram_13" address="0x0D2000" mode="block" size="0x2000" description="Quad116 Ch1"  />
   <node id="source_ram_14" address="0x0E0000" mode="block" size="0x2000" description="Quad116 Ch2"  />
   <node id="contrl_ram_14" address="0x0E2000" mode="block" size="0x2000" description="Quad116 Ch2"  />
   <node id="source_ram_15" address="0x0F0000" mode="block" size="0x2000" description="Quad116 Ch3"  />
   <node id="contrl_ram_15" address="0x0F2000" mode="block" size="0x2000" description="Quad116 Ch3"  />
</node>

