<!-- Control FPGA Module Control -->
<node fwinfo = "endpoint;width=2">
	<node id="control" permission="rw" address="0x0">
            <node id="pll_pd"   mask="0x0100" description="Power down PLLs"/>
            <node id="vadj_on"  mask="0x800000" description="Power up FMC Vadj"/>
        </node>
	<node id="pulse"  permission="rw"  address="0x1">
            <node id="modreset" mask="0x01" description="Reset Module"/>
            <node id="dss_1_rst" mask="0x02" description="Reset DSS1 logic"/>
            <node id="dss_2_rst" mask="0x04" description="Reset DSS2 logic"/>
            <node id="pll_sync" mask="0x040" description="PLL Sync signal"/>
            <node id="dss_1_cfg" mask="0x0100" description="ReConfigure DSS1"/>
            <node id="dss_2_cfg" mask="0x0200" description="ReConfigure DSS2"/>
        </node>
	<node id="status" permission="r"  address="0x2">
            <node id="ctrl_done" mask="0x01" />
            <node id="dss_1_done" mask="0x02" />
            <node id="dss_2_done" mask="0x04" />
            <node id="pll_0_lock" mask="0x040" />
            <node id="pll_1_lock" mask="0x080" />
            <node id="pll_2_lock" mask="0x0100" />
            <node id="pll_3_lock" mask="0x0200" />
            <node id="dss_1_init" mask="0x0400" />
            <node id="dss_2_init" mask="0x0800" />
            <node id="crate" mask="0x0F000" />
            <node id="debug" mask="0x10000" />
            <node id="fmc_active"   mask="0x20000000" />
            <node id="fmc_selected" mask="0x40000000" />
            <node id="fmc_present"  mask="0x80000000" />
        </node>
</node>

