*** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Netlist sorting complete. Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2069.504 ; gain = 1.996 ; free physical = 8623 ; free virtual = 27778 INFO: [Netlist 29-17] Analyzing 3256 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] get_clocks: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 3158.234 ; gain = 825.582 ; free physical = 7728 ; free virtual = 26883 Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3330.129 ; gain = 0.000 ; free physical = 7780 ; free virtual = 26935 INFO: [Project 1-111] Unisim Transformation Summary: A total of 10 instances were transformed. OBUFDS => OBUFDS: 10 instances 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:03 ; elapsed = 00:01:54 . Memory (MB): peak = 3330.129 ; gain = 1707.062 ; free physical = 7780 ; free virtual = 26935 source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci Sourcing Tcl File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx415t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:01 . Memory (MB): peak = 3346.137 ; gain = 8.004 ; free physical = 7777 ; free virtual = 26932 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 11ab33630 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3354.137 ; gain = 8.000 ; free physical = 7545 ; free virtual = 26700 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 114f33d06 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3549.887 ; gain = 16.004 ; free physical = 7528 ; free virtual = 26684 INFO: [Opt 31-389] Phase Retarget created 59 cells and removed 122 cells INFO: [Opt 31-1021] In phase Retarget, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 114f33d06 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3549.887 ; gain = 16.004 ; free physical = 7528 ; free virtual = 26684 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 100f6867c Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3549.887 ; gain = 16.004 ; free physical = 7530 ; free virtual = 26685 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 508 cells INFO: [Opt 31-1021] In phase Sweep, 524 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 4 BUFG optimization | Checksum: fe69c317 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3549.887 ; gain = 16.004 ; free physical = 7530 ; free virtual = 26685 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: fe69c317 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3549.887 ; gain = 16.004 ; free physical = 7530 ; free virtual = 26685 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 115a42334 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3549.887 ; gain = 16.004 ; free physical = 7530 ; free virtual = 26685 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 59 | 122 | 49 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 508 | 524 | | BUFG optimization | 0 | 4 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3549.887 ; gain = 0.000 ; free physical = 7530 ; free virtual = 26686 Ending Logic Optimization Task | Checksum: 17bf73e4e Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 3549.887 ; gain = 16.004 ; free physical = 7530 ; free virtual = 26686 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.483 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 643 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 16 newly gated: 440 Total Ports: 1286 Ending PowerOpt Patch Enables Task | Checksum: b72a3410 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4645.504 ; gain = 0.000 ; free physical = 7200 ; free virtual = 26356 Ending Power Optimization Task | Checksum: b72a3410 Time (s): cpu = 00:01:22 ; elapsed = 00:01:26 . Memory (MB): peak = 4645.504 ; gain = 1095.617 ; free physical = 7307 ; free virtual = 26462 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 16c028f9a Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 4645.504 ; gain = 0.000 ; free physical = 7155 ; free virtual = 26310 Ending Final Cleanup Task | Checksum: 16c028f9a Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 4645.504 ; gain = 0.000 ; free physical = 7153 ; free virtual = 26308 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4645.504 ; gain = 0.000 ; free physical = 7153 ; free virtual = 26308 Ending Netlist Obfuscation Task | Checksum: 16c028f9a Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4645.504 ; gain = 0.000 ; free physical = 7153 ; free virtual = 26308 INFO: [Common 17-83] Releasing license: Implementation 45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:09 ; elapsed = 00:02:18 . Memory (MB): peak = 4645.504 ; gain = 1315.375 ; free physical = 7153 ; free virtual = 26309 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4645.504 ; gain = 0.000 ; free physical = 6887 ; free virtual = 26042 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 4645.504 ; gain = 0.000 ; free physical = 6686 ; free virtual = 26025 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 4645.508 ; gain = 0.004 ; free physical = 6853 ; free virtual = 26027 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6846 ; free virtual = 26020 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6843 ; free virtual = 26017 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11261e1c7 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6843 ; free virtual = 26017 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6843 ; free virtual = 26017 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d0408e7b Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6825 ; free virtual = 25998 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1f8089f76 Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6784 ; free virtual = 25958 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1f8089f76 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6784 ; free virtual = 25958 Phase 1 Placer Initialization | Checksum: 1f8089f76 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6780 ; free virtual = 25954 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 19612801a Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6755 ; free virtual = 25929 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 986 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 396 nets or cells. Created 12 new cells, deleted 384 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-46] Identified 29 candidate nets for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-665] Processed cell slaves/rx_bufs/bufgen[2].rxbuf/rx_check/dssram/ram_reg_1. 4 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 4 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6740 ; free virtual = 25914 INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6741 ; free virtual = 25914 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 12 | 384 | 396 | 0 | 1 | 00:00:02 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 4 | 0 | 1 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 16 | 384 | 397 | 0 | 8 | 00:00:03 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 23ca9a51c Time (s): cpu = 00:02:09 ; elapsed = 00:02:14 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6742 ; free virtual = 25916 Phase 2.2 Global Placement Core | Checksum: 1a90c12c9 Time (s): cpu = 00:02:15 ; elapsed = 00:02:20 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6733 ; free virtual = 25907 Phase 2 Global Placement | Checksum: 1a90c12c9 Time (s): cpu = 00:02:15 ; elapsed = 00:02:20 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6755 ; free virtual = 25929 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e5801c4c Time (s): cpu = 00:02:26 ; elapsed = 00:02:31 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6747 ; free virtual = 25920 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 267623113 Time (s): cpu = 00:02:41 ; elapsed = 00:02:47 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6743 ; free virtual = 25916 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 20a89845e Time (s): cpu = 00:02:43 ; elapsed = 00:02:49 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6742 ; free virtual = 25916 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 244a0d7e3 Time (s): cpu = 00:02:43 ; elapsed = 00:02:49 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6742 ; free virtual = 25915 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1b918f3ba Time (s): cpu = 00:02:59 ; elapsed = 00:03:05 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6744 ; free virtual = 25918 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 280064c05 Time (s): cpu = 00:03:18 ; elapsed = 00:03:25 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6698 ; free virtual = 25872 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1eea11631 Time (s): cpu = 00:03:21 ; elapsed = 00:03:28 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6700 ; free virtual = 25874 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1e000ac66 Time (s): cpu = 00:03:22 ; elapsed = 00:03:29 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6700 ; free virtual = 25874 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 25b5d17cb Time (s): cpu = 00:03:45 ; elapsed = 00:03:53 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6700 ; free virtual = 25874 Phase 3 Detail Placement | Checksum: 25b5d17cb Time (s): cpu = 00:03:46 ; elapsed = 00:03:54 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6700 ; free virtual = 25874 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 19739eeb7 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 19739eeb7 Time (s): cpu = 00:04:18 ; elapsed = 00:04:26 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6500 ; free virtual = 25673 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.118. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: e4ee086f Time (s): cpu = 00:05:12 ; elapsed = 00:05:20 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6512 ; free virtual = 25686 Phase 4.1 Post Commit Optimization | Checksum: e4ee086f Time (s): cpu = 00:05:12 ; elapsed = 00:05:20 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6512 ; free virtual = 25686 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: e4ee086f Time (s): cpu = 00:05:13 ; elapsed = 00:05:22 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6521 ; free virtual = 25695 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: e4ee086f Time (s): cpu = 00:05:14 ; elapsed = 00:05:22 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6522 ; free virtual = 25696 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6522 ; free virtual = 25696 Phase 4.4 Final Placement Cleanup | Checksum: 15a68446a Time (s): cpu = 00:05:15 ; elapsed = 00:05:23 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6522 ; free virtual = 25696 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15a68446a Time (s): cpu = 00:05:15 ; elapsed = 00:05:23 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6522 ; free virtual = 25696 Ending Placer Task | Checksum: d1a4e3fc Time (s): cpu = 00:05:15 ; elapsed = 00:05:23 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6522 ; free virtual = 25696 INFO: [Common 17-83] Releasing license: Implementation 79 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:05:21 ; elapsed = 00:05:30 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6577 ; free virtual = 25751 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6577 ; free virtual = 25751 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6323 ; free virtual = 25739 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6545 ; free virtual = 25743 INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.45 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6517 ; free virtual = 25716 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.35 . Memory (MB): peak = 4645.508 ; gain = 0.000 ; free physical = 6542 ; free virtual = 25741 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 9316dd6 ConstDB: 0 ShapeSum: c8737626 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 4b516147 Time (s): cpu = 00:01:20 ; elapsed = 00:01:21 . Memory (MB): peak = 4691.895 ; gain = 46.387 ; free physical = 6198 ; free virtual = 25397 Post Restoration Checksum: NetGraph: 2db49f50 NumContArr: 1d9cc1f7 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 4b516147 Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 4721.094 ; gain = 75.586 ; free physical = 6174 ; free virtual = 25373 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 4b516147 Time (s): cpu = 00:01:22 ; elapsed = 00:01:22 . Memory (MB): peak = 4728.297 ; gain = 82.789 ; free physical = 6162 ; free virtual = 25361 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 4b516147 Time (s): cpu = 00:01:22 ; elapsed = 00:01:22 . Memory (MB): peak = 4728.301 ; gain = 82.793 ; free physical = 6162 ; free virtual = 25361 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 13c2a696d Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6103 ; free virtual = 25302 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.162 | TNS=-0.548 | WHS=-0.979 | THS=-1866.344| Phase 2 Router Initialization | Checksum: 112ddac24 Time (s): cpu = 00:02:17 ; elapsed = 00:02:20 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6096 ; free virtual = 25295 Router Utilization Summary Global Vertical Routing Utilization = 0.00241385 % Global Horizontal Routing Utilization = 0.00161567 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 47680 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 47679 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 2455af192 Time (s): cpu = 00:07:17 ; elapsed = 00:07:23 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6072 ; free virtual = 25271 INFO: [Route 35-580] Design has 207 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[21].mgt_source_data_regd_reg[21][data][8]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[44].mgt_source_data_regd_reg[44][data][30]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[17].mgt_source_data_regd_reg[17][data][27]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[36].mgt_source_data_regd_reg[36][data][26]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[36].mgt_source_data_regd_reg[36][data][24]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 4712 Number of Nodes with overlaps = 596 Number of Nodes with overlaps = 123 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.116 | TNS=-0.258 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 99e2395e Time (s): cpu = 00:09:06 ; elapsed = 00:09:14 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6059 ; free virtual = 25258 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 348 Number of Nodes with overlaps = 70 Number of Nodes with overlaps = 54 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.116 | TNS=-0.182 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 149eab9bf Time (s): cpu = 00:09:30 ; elapsed = 00:09:39 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6060 ; free virtual = 25259 Phase 4 Rip-up And Reroute | Checksum: 149eab9bf Time (s): cpu = 00:09:30 ; elapsed = 00:09:39 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6060 ; free virtual = 25259 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 14aa4ad41 Time (s): cpu = 00:09:37 ; elapsed = 00:09:45 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6062 ; free virtual = 25261 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.116 | TNS=-0.182 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 1f820307f Time (s): cpu = 00:09:38 ; elapsed = 00:09:46 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6060 ; free virtual = 25259 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1f820307f Time (s): cpu = 00:09:38 ; elapsed = 00:09:47 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6060 ; free virtual = 25259 Phase 5 Delay and Skew Optimization | Checksum: 1f820307f Time (s): cpu = 00:09:38 ; elapsed = 00:09:47 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6060 ; free virtual = 25259 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1ea6d49aa Time (s): cpu = 00:09:46 ; elapsed = 00:09:55 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6073 ; free virtual = 25272 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.116 | TNS=-0.182 | WHS=-0.524 | THS=-0.524 | Phase 6.1 Hold Fix Iter | Checksum: 1bf2d82da Time (s): cpu = 00:09:47 ; elapsed = 00:09:56 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6072 ; free virtual = 25271 Phase 6 Post Hold Fix | Checksum: 1bb9e5485 Time (s): cpu = 00:09:47 ; elapsed = 00:09:56 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6072 ; free virtual = 25271 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.65926 % Global Horizontal Routing Utilization = 7.82435 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 70.2703%, No Congested Regions. South Dir 1x1 Area, Max Cong = 63.964%, No Congested Regions. East Dir 1x1 Area, Max Cong = 66.1765%, No Congested Regions. West Dir 1x1 Area, Max Cong = 75%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 174a9ef12 Time (s): cpu = 00:09:48 ; elapsed = 00:09:57 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6070 ; free virtual = 25269 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 174a9ef12 Time (s): cpu = 00:09:49 ; elapsed = 00:09:57 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6069 ; free virtual = 25268 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 Phase 9 Depositing Routes | Checksum: 114b2f23f Time (s): cpu = 00:09:55 ; elapsed = 00:10:04 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6064 ; free virtual = 25263 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: 14e25d591 Time (s): cpu = 00:10:03 ; elapsed = 00:10:12 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6067 ; free virtual = 25266 INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.116 | TNS=-0.182 | WHS=0.059 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 14e25d591 Time (s): cpu = 00:10:03 ; elapsed = 00:10:12 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6067 ; free virtual = 25266 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:10:04 ; elapsed = 00:10:12 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6132 ; free virtual = 25331 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 100 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:10:13 ; elapsed = 00:10:23 . Memory (MB): peak = 4879.855 ; gain = 234.348 ; free physical = 6133 ; free virtual = 25332 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: df94d40 INFO: [Hog:Msg-0] The git SHA value df94d40 will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4879.855 ; gain = 0.000 ; free physical = 6137 ; free virtual = 25336 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4879.855 ; gain = 0.000 ; free physical = 5860 ; free virtual = 25323 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 4879.859 ; gain = 0.004 ; free physical = 6099 ; free virtual = 25329 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 4879.859 ; gain = 0.000 ; free physical = 6077 ; free virtual = 25306 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 5092.855 ; gain = 212.996 ; free physical = 5925 ; free virtual = 25154 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 123 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 5139.863 ; gain = 47.008 ; free physical = 5712 ; free virtual = 24954 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5155.863 ; gain = 16.000 ; free physical = 5682 ; free virtual = 24931 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 5258.621 ; gain = 102.758 ; free physical = 5664 ; free virtual = 24914 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 135 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 5258.621 ; gain = 0.000 ; free physical = 5655 ; free virtual = 24917 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5258.621 ; gain = 0.000 ; free physical = 5652 ; free virtual = 24916 INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Sun Oct 4 14:01:58 2020... *** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: open_checkpoint top_FTM_DSS_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1554.152 ; gain = 0.000 ; free physical = 9109 ; free virtual = 28373 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 Netlist sorting complete. Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2053.801 ; gain = 0.000 ; free physical = 8529 ; free virtual = 27793 INFO: [Netlist 29-17] Analyzing 3254 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3140.109 ; gain = 63.133 ; free physical = 7521 ; free virtual = 26784 Restored from archive | CPU: 5.700000 secs | Memory: 75.340050 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3140.109 ; gain = 63.133 ; free physical = 7521 ; free virtual = 26784 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3140.109 ; gain = 0.000 ; free physical = 7526 ; free virtual = 26789 INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:01:14 ; elapsed = 00:02:16 . Memory (MB): peak = 3140.109 ; gain = 1585.961 ; free physical = 7526 ; free virtual = 26789 source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_DSS.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. INFO: [Vivado 12-3199] DRC finished with 0 Errors INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 59800352 bits. Writing bitstream ./top_FTM_DSS.bit... Writing bitstream ./top_FTM_DSS.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Oct 4 14:08:16 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:03:30 ; elapsed = 00:03:39 . Memory (MB): peak = 3819.480 ; gain = 679.371 ; free physical = 7406 ; free virtual = 26688 source /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.14.1 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:ReadListFile-0] 92 lines read from ./list/ftm.src. INFO: [Hog:ReadListFile-0] 8 lines read from ./list/XDC.con. INFO: [Hog:ReadListFile-0] 15 lines read from ./list/xml.lst. INFO: [Hog:Msg-0] Git describe set to: v1.0.4-0-gdf94d40 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.4-0-gdf94d40... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/VivadoProject/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v1.0.4-0-gdf94d40/FTM_DSS-v1.0.4-0-gdf94d40.bit...