*** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Netlist sorting complete. Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2063.582 ; gain = 0.996 ; free physical = 3166 ; free virtual = 21578 INFO: [Netlist 29-17] Analyzing 3217 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] get_clocks: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 3087.258 ; gain = 794.574 ; free physical = 2270 ; free virtual = 20682 Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3258.152 ; gain = 0.000 ; free physical = 2322 ; free virtual = 20734 INFO: [Project 1-111] Unisim Transformation Summary: A total of 10 instances were transformed. OBUFDS => OBUFDS: 10 instances 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:04 ; elapsed = 00:02:02 . Memory (MB): peak = 3258.152 ; gain = 1635.086 ; free physical = 2322 ; free virtual = 20734 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx415t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:01 . Memory (MB): peak = 3274.160 ; gain = 8.004 ; free physical = 2320 ; free virtual = 20733 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1aa24c8e4 Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3284.156 ; gain = 9.000 ; free physical = 2087 ; free virtual = 20499 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 115f1cf3d Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3462.941 ; gain = 0.004 ; free physical = 2075 ; free virtual = 20487 INFO: [Opt 31-389] Phase Retarget created 59 cells and removed 118 cells INFO: [Opt 31-1021] In phase Retarget, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 115f1cf3d Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3462.941 ; gain = 0.004 ; free physical = 2075 ; free virtual = 20487 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: fb3bab82 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.941 ; gain = 0.004 ; free physical = 2076 ; free virtual = 20488 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 508 cells INFO: [Opt 31-1021] In phase Sweep, 524 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 4 BUFG optimization | Checksum: 11a5e7e07 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3462.941 ; gain = 0.004 ; free physical = 2076 ; free virtual = 20488 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 11a5e7e07 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3462.941 ; gain = 0.004 ; free physical = 2076 ; free virtual = 20488 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: d64251c0 Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3462.941 ; gain = 0.004 ; free physical = 2076 ; free virtual = 20489 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 59 | 118 | 49 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 508 | 524 | | BUFG optimization | 0 | 4 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3462.941 ; gain = 0.000 ; free physical = 2076 ; free virtual = 20489 Ending Logic Optimization Task | Checksum: 166db3ff6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.941 ; gain = 0.004 ; free physical = 2076 ; free virtual = 20489 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.475 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 643 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 16 newly gated: 8 Total Ports: 1286 Ending PowerOpt Patch Enables Task | Checksum: eae62343 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4581.566 ; gain = 0.000 ; free physical = 1736 ; free virtual = 20149 Ending Power Optimization Task | Checksum: eae62343 Time (s): cpu = 00:01:34 ; elapsed = 00:01:41 . Memory (MB): peak = 4581.566 ; gain = 1118.625 ; free physical = 1844 ; free virtual = 20256 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1089a7766 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4581.566 ; gain = 0.000 ; free physical = 1692 ; free virtual = 20105 Ending Final Cleanup Task | Checksum: 1089a7766 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 4581.566 ; gain = 0.000 ; free physical = 1691 ; free virtual = 20103 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.566 ; gain = 0.000 ; free physical = 1691 ; free virtual = 20103 Ending Netlist Obfuscation Task | Checksum: 1089a7766 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.566 ; gain = 0.000 ; free physical = 1691 ; free virtual = 20103 INFO: [Common 17-83] Releasing license: Implementation 45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:25 ; elapsed = 00:02:36 . Memory (MB): peak = 4581.566 ; gain = 1323.414 ; free physical = 1695 ; free virtual = 20107 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.566 ; gain = 0.000 ; free physical = 1428 ; free virtual = 19840 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 4581.566 ; gain = 0.000 ; free physical = 1232 ; free virtual = 19826 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 4581.570 ; gain = 0.004 ; free physical = 1396 ; free virtual = 19827 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1390 ; free virtual = 19820 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1387 ; free virtual = 19818 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a105874f Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1387 ; free virtual = 19818 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1387 ; free virtual = 19818 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 107b2a202 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1370 ; free virtual = 19801 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 154b089e0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1328 ; free virtual = 19759 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 154b089e0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1330 ; free virtual = 19761 Phase 1 Placer Initialization | Checksum: 154b089e0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1327 ; free virtual = 19757 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1572bdfd0 Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1301 ; free virtual = 19732 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 966 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 407 nets or cells. Created 14 new cells, deleted 393 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-46] Identified 15 candidate nets for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1286 ; free virtual = 19717 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 14 | 393 | 407 | 0 | 1 | 00:00:02 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 14 | 393 | 407 | 0 | 8 | 00:00:03 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 2208d5d5f Time (s): cpu = 00:02:13 ; elapsed = 00:02:18 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1286 ; free virtual = 19717 Phase 2.2 Global Placement Core | Checksum: 2133521ea Time (s): cpu = 00:02:19 ; elapsed = 00:02:24 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1278 ; free virtual = 19708 Phase 2 Global Placement | Checksum: 2133521ea Time (s): cpu = 00:02:19 ; elapsed = 00:02:24 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1299 ; free virtual = 19730 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 15992df3f Time (s): cpu = 00:02:28 ; elapsed = 00:02:34 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1292 ; free virtual = 19723 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13740d8b1 Time (s): cpu = 00:02:45 ; elapsed = 00:02:51 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1288 ; free virtual = 19718 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18733f1ee Time (s): cpu = 00:02:46 ; elapsed = 00:02:52 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1288 ; free virtual = 19718 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1ab3ba2da Time (s): cpu = 00:02:47 ; elapsed = 00:02:53 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1286 ; free virtual = 19717 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 20218d27a Time (s): cpu = 00:03:02 ; elapsed = 00:03:09 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1290 ; free virtual = 19720 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1e6fb2da1 Time (s): cpu = 00:03:23 ; elapsed = 00:03:30 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1242 ; free virtual = 19674 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 2171885e8 Time (s): cpu = 00:03:26 ; elapsed = 00:03:33 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1244 ; free virtual = 19676 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 2298d2343 Time (s): cpu = 00:03:27 ; elapsed = 00:03:35 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1244 ; free virtual = 19676 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 21b5c74dd Time (s): cpu = 00:03:50 ; elapsed = 00:03:57 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1240 ; free virtual = 19672 Phase 3 Detail Placement | Checksum: 21b5c74dd Time (s): cpu = 00:03:50 ; elapsed = 00:03:58 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1240 ; free virtual = 19672 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 128efa4f7 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: 128efa4f7 Time (s): cpu = 00:04:22 ; elapsed = 00:04:30 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1043 ; free virtual = 19475 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.120. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: c08753db Time (s): cpu = 00:05:21 ; elapsed = 00:05:30 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1055 ; free virtual = 19487 Phase 4.1 Post Commit Optimization | Checksum: c08753db Time (s): cpu = 00:05:22 ; elapsed = 00:05:30 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1055 ; free virtual = 19487 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: c08753db Time (s): cpu = 00:05:23 ; elapsed = 00:05:32 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1064 ; free virtual = 19496 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: c08753db Time (s): cpu = 00:05:24 ; elapsed = 00:05:32 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1064 ; free virtual = 19496 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1064 ; free virtual = 19496 Phase 4.4 Final Placement Cleanup | Checksum: de6aa404 Time (s): cpu = 00:05:24 ; elapsed = 00:05:33 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1064 ; free virtual = 19496 Phase 4 Post Placement Optimization and Clean-Up | Checksum: de6aa404 Time (s): cpu = 00:05:25 ; elapsed = 00:05:34 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1064 ; free virtual = 19496 Ending Placer Task | Checksum: c30e4b2c Time (s): cpu = 00:05:25 ; elapsed = 00:05:34 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1064 ; free virtual = 19496 INFO: [Common 17-83] Releasing license: Implementation 79 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:05:31 ; elapsed = 00:05:40 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1119 ; free virtual = 19551 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1120 ; free virtual = 19552 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 867 ; free virtual = 19539 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1087 ; free virtual = 19543 INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt report_io: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.47 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1059 ; free virtual = 19515 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.36 . Memory (MB): peak = 4581.570 ; gain = 0.000 ; free physical = 1085 ; free virtual = 19542 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 9cd7c13e ConstDB: 0 ShapeSum: 263689ee RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: efdab2c0 Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 4618.957 ; gain = 37.387 ; free physical = 743 ; free virtual = 19200 Post Restoration Checksum: NetGraph: b1b13c39 NumContArr: 3e297687 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: efdab2c0 Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4648.156 ; gain = 66.586 ; free physical = 719 ; free virtual = 19175 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: efdab2c0 Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4655.359 ; gain = 73.789 ; free physical = 707 ; free virtual = 19164 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: efdab2c0 Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 4655.363 ; gain = 73.793 ; free physical = 707 ; free virtual = 19164 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: f92cc307 Time (s): cpu = 00:02:19 ; elapsed = 00:02:21 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 650 ; free virtual = 19107 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.025 | TNS=-0.049 | WHS=-0.446 | THS=-1831.161| Phase 2 Router Initialization | Checksum: 1fdbf2b56 Time (s): cpu = 00:02:29 ; elapsed = 00:02:32 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 642 ; free virtual = 19099 Router Utilization Summary Global Vertical Routing Utilization = 0.00309053 % Global Horizontal Routing Utilization = 0.00275323 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 47313 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 47312 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: abb09190 Time (s): cpu = 00:07:22 ; elapsed = 00:07:29 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 625 ; free virtual = 19082 INFO: [Route 35-580] Design has 197 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[46].mgt_source_data_regd_reg[46][data][4]/D| | mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[32].mgt_source_data_regd_reg[32][data][16]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[46].mgt_source_data_regd_reg[46][data][7]/D| | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[40].mgt_source_data_regd_reg[40][data][8]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[12].mgt_source_data_regd_reg[12][data][18]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 5108 Number of Nodes with overlaps = 903 Number of Nodes with overlaps = 232 Number of Nodes with overlaps = 70 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.015 | TNS=-0.015 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 152863b49 Time (s): cpu = 00:09:42 ; elapsed = 00:09:52 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 609 ; free virtual = 19069 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 290 Number of Nodes with overlaps = 48 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.028 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: b13eef51 Time (s): cpu = 00:10:01 ; elapsed = 00:10:12 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 611 ; free virtual = 19070 Phase 4 Rip-up And Reroute | Checksum: b13eef51 Time (s): cpu = 00:10:01 ; elapsed = 00:10:13 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 611 ; free virtual = 19070 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: b13eef51 Time (s): cpu = 00:10:02 ; elapsed = 00:10:13 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 611 ; free virtual = 19070 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: b13eef51 Time (s): cpu = 00:10:02 ; elapsed = 00:10:13 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 611 ; free virtual = 19070 Phase 5 Delay and Skew Optimization | Checksum: b13eef51 Time (s): cpu = 00:10:02 ; elapsed = 00:10:13 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 611 ; free virtual = 19070 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 99d4cb33 Time (s): cpu = 00:10:11 ; elapsed = 00:10:22 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 612 ; free virtual = 19072 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.136 | TNS=0.000 | WHS=0.032 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: c2ff1d3e Time (s): cpu = 00:10:11 ; elapsed = 00:10:22 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 612 ; free virtual = 19072 Phase 6 Post Hold Fix | Checksum: c2ff1d3e Time (s): cpu = 00:10:11 ; elapsed = 00:10:22 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 612 ; free virtual = 19072 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.68829 % Global Horizontal Routing Utilization = 7.50772 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 6ee8f70f Time (s): cpu = 00:10:12 ; elapsed = 00:10:24 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 611 ; free virtual = 19070 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6ee8f70f Time (s): cpu = 00:10:13 ; elapsed = 00:10:24 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 609 ; free virtual = 19069 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 Phase 9 Depositing Routes | Checksum: b738096c Time (s): cpu = 00:10:19 ; elapsed = 00:10:30 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 606 ; free virtual = 19065 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.136 | TNS=0.000 | WHS=0.032 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: b738096c Time (s): cpu = 00:10:20 ; elapsed = 00:10:31 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 619 ; free virtual = 19079 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:10:20 ; elapsed = 00:10:31 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 677 ; free virtual = 19136 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:10:30 ; elapsed = 00:10:42 . Memory (MB): peak = 4803.918 ; gain = 222.348 ; free physical = 677 ; free virtual = 19136 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 01B2D3C, will use most recent tag v2.0.0. As this is an official tag, patch will be incremented to 1. INFO: [Hog:GetVerFromSHA-0] No tag contains 63135BC, will use most recent tag v2.0.0. As this is an official tag, patch will be incremented to 1. INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: 63135bc INFO: [Hog:Msg-0] The git SHA value 63135bc will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4803.918 ; gain = 0.000 ; free physical = 678 ; free virtual = 19138 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4803.918 ; gain = 0.000 ; free physical = 406 ; free virtual = 19128 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 4803.922 ; gain = 0.004 ; free physical = 643 ; free virtual = 19133 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 4803.922 ; gain = 0.000 ; free physical = 627 ; free virtual = 19116 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:54 ; elapsed = 00:00:56 . Memory (MB): peak = 5008.918 ; gain = 204.996 ; free physical = 469 ; free virtual = 18959 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 122 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:38 ; elapsed = 00:00:34 . Memory (MB): peak = 5061.934 ; gain = 53.016 ; free physical = 255 ; free virtual = 18758 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5078.934 ; gain = 17.000 ; free physical = 226 ; free virtual = 18737 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 5180.660 ; gain = 101.727 ; free physical = 249 ; free virtual = 18722 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 134 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 5180.660 ; gain = 0.000 ; free physical = 241 ; free virtual = 18726 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5180.660 ; gain = 0.000 ; free physical = 237 ; free virtual = 18723 INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Wed Apr 7 17:47:36 2021... *** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: open_checkpoint top_FTM_DSS_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1595.270 ; gain = 0.000 ; free physical = 3685 ; free virtual = 22171 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 Netlist sorting complete. Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2048.996 ; gain = 0.000 ; free physical = 3105 ; free virtual = 21591 INFO: [Netlist 29-17] Analyzing 3215 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3101.344 ; gain = 63.133 ; free physical = 2099 ; free virtual = 20586 Restored from archive | CPU: 6.140000 secs | Memory: 74.674515 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3101.344 ; gain = 63.133 ; free physical = 2099 ; free virtual = 20586 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3101.344 ; gain = 0.000 ; free physical = 2104 ; free virtual = 20591 INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:01:15 ; elapsed = 00:02:24 . Memory (MB): peak = 3101.344 ; gain = 1506.078 ; free physical = 2104 ; free virtual = 20590 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_DSS.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. INFO: [Vivado 12-3199] DRC finished with 0 Errors INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 61304800 bits. Writing bitstream ./top_FTM_DSS.bit... Writing bitstream ./top_FTM_DSS.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Apr 7 17:54:20 2021. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:03:44 ; elapsed = 00:03:56 . Memory (MB): peak = 3776.684 ; gain = 675.340 ; free physical = 1988 ; free virtual = 20492 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 01B2D3C, will use most recent tag v2.0.0. As this is an official tag, patch will be incremented to 1. INFO: [Hog:GetVerFromSHA-0] No tag contains 63135BC, will use most recent tag v2.0.0. As this is an official tag, patch will be incremented to 1. INFO: [Hog:Msg-0] Git describe set to: v2.0.0-2-g63135bc INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.0.0-2-g63135bc... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.0.0-2-g63135bc/FTM_DSS-v2.0.0-2-g63135bc.bit...