*** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_bcr.dcp' for cell 'slaves/buffer_control/bcr_delays' Netlist sorting complete. Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.88 . Memory (MB): peak = 2100.035 ; gain = 3.000 ; free physical = 3000 ; free virtual = 21462 INFO: [Netlist 29-17] Analyzing 3265 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: slaves/buffer_control/bcr_delays UUID: b6fbd4f1-3519-5b57-8709-90667c26e79c Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] get_clocks: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 3126.672 ; gain = 795.535 ; free physical = 2103 ; free virtual = 20564 Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3299.566 ; gain = 0.000 ; free physical = 2151 ; free virtual = 20613 INFO: [Project 1-111] Unisim Transformation Summary: A total of 42 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances OBUFDS => OBUFDS: 10 instances 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:06 ; elapsed = 00:02:02 . Memory (MB): peak = 3299.566 ; gain = 1660.488 ; free physical = 2151 ; free virtual = 20613 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx415t. * **************************************************************************************** Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:01 . Memory (MB): peak = 3315.574 ; gain = 8.004 ; free physical = 2151 ; free virtual = 20613 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 169c6b9a3 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3323.570 ; gain = 7.000 ; free physical = 1919 ; free virtual = 20381 Starting Logic Optimization Task Phase 1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3575.156 ; gain = 40.965 ; free physical = 1722 ; free virtual = 20134 Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3575.156 ; gain = 0.000 ; free physical = 1722 ; free virtual = 20135 Phase 1 Generate And Synthesize Debug Cores | Checksum: 17db34c2a Time (s): cpu = 00:02:27 ; elapsed = 00:05:02 . Memory (MB): peak = 3575.160 ; gain = 72.840 ; free physical = 1722 ; free virtual = 20134 Phase 2 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 2 Retarget | Checksum: 1620c3b24 Time (s): cpu = 00:02:32 ; elapsed = 00:05:08 . Memory (MB): peak = 3591.160 ; gain = 88.840 ; free physical = 1851 ; free virtual = 20266 INFO: [Opt 31-389] Phase Retarget created 63 cells and removed 129 cells INFO: [Opt 31-1021] In phase Retarget, 112 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Constant propagation | Checksum: ee789d29 Time (s): cpu = 00:02:33 ; elapsed = 00:05:09 . Memory (MB): peak = 3591.160 ; gain = 88.840 ; free physical = 1851 ; free virtual = 20266 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells INFO: [Opt 31-1021] In phase Constant propagation, 47 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Sweep Phase 4 Sweep | Checksum: 1ad6ed3d6 Time (s): cpu = 00:02:39 ; elapsed = 00:05:15 . Memory (MB): peak = 3591.160 ; gain = 88.840 ; free physical = 1849 ; free virtual = 20264 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 580 cells INFO: [Opt 31-1021] In phase Sweep, 1386 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). Phase 5 BUFG optimization | Checksum: 1ce93392d Time (s): cpu = 00:02:40 ; elapsed = 00:05:16 . Memory (MB): peak = 3591.160 ; gain = 88.840 ; free physical = 1852 ; free virtual = 20267 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells. Phase 6 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 6 Shift Register Optimization | Checksum: 1ce93392d Time (s): cpu = 00:02:42 ; elapsed = 00:05:17 . Memory (MB): peak = 3591.160 ; gain = 88.840 ; free physical = 1852 ; free virtual = 20267 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 7 Post Processing Netlist Phase 7 Post Processing Netlist | Checksum: 170c887fe Time (s): cpu = 00:02:42 ; elapsed = 00:05:18 . Memory (MB): peak = 3591.160 ; gain = 88.840 ; free physical = 1853 ; free virtual = 20267 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 58 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 63 | 129 | 112 | | Constant propagation | 0 | 16 | 47 | | Sweep | 0 | 580 | 1386 | | BUFG optimization | 0 | 4 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 58 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3591.160 ; gain = 0.000 ; free physical = 1852 ; free virtual = 20267 Ending Logic Optimization Task | Checksum: 194c138cf Time (s): cpu = 00:02:45 ; elapsed = 00:05:21 . Memory (MB): peak = 3591.160 ; gain = 88.840 ; free physical = 1852 ; free virtual = 20267 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.475 | TNS=0.000 | INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 644 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 1288 Ending PowerOpt Patch Enables Task | Checksum: 16d5bfc62 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4701.387 ; gain = 0.000 ; free physical = 1563 ; free virtual = 19980 Ending Power Optimization Task | Checksum: 16d5bfc62 Time (s): cpu = 00:01:36 ; elapsed = 00:01:41 . Memory (MB): peak = 4701.387 ; gain = 1110.227 ; free physical = 1668 ; free virtual = 20085 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: f5c1bcda Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4701.387 ; gain = 0.000 ; free physical = 1527 ; free virtual = 19944 Ending Final Cleanup Task | Checksum: f5c1bcda Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 4701.387 ; gain = 0.000 ; free physical = 1525 ; free virtual = 19942 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.387 ; gain = 0.000 ; free physical = 1525 ; free virtual = 19942 Ending Netlist Obfuscation Task | Checksum: f5c1bcda Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.387 ; gain = 0.000 ; free physical = 1525 ; free virtual = 19942 INFO: [Common 17-83] Releasing license: Implementation 53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:55 ; elapsed = 00:07:41 . Memory (MB): peak = 4701.387 ; gain = 1401.820 ; free physical = 1525 ; free virtual = 19942 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4701.387 ; gain = 0.000 ; free physical = 1246 ; free virtual = 19663 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 4701.387 ; gain = 0.000 ; free physical = 1040 ; free virtual = 19647 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 4701.391 ; gain = 0.004 ; free physical = 1211 ; free virtual = 19648 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1204 ; free virtual = 19642 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1202 ; free virtual = 19639 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7e0a097a Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1202 ; free virtual = 19639 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1202 ; free virtual = 19639 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1002cef9 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1182 ; free virtual = 19622 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 77aa8530 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1136 ; free virtual = 19577 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 77aa8530 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1136 ; free virtual = 19577 Phase 1 Placer Initialization | Checksum: 77aa8530 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1132 ; free virtual = 19573 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: c8770726 Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1112 ; free virtual = 19553 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1018] Found 1104 candidate LUT instances to create LUTNM shape INFO: [Physopt 32-775] End 1 Pass. Optimized 453 nets or cells. Created 17 new cells, deleted 436 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-665] Processed cell slaves/rx_bufs/bufgen[3].rxbuf/rx_check/dssram/ram_reg_0. 4 registers were pushed out. INFO: [Physopt 32-665] Processed cell slaves/rx_bufs/bufgen[2].rxbuf/rx_check/dssram/ram_reg_0. 4 registers were pushed out. INFO: [Physopt 32-665] Processed cell slaves/rx_bufs/bufgen[3].rxbuf/rx_check/dssram/ram_reg_3. 4 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 3 nets or cells. Created 12 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1081 ; free virtual = 19526 INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1082 ; free virtual = 19527 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 17 | 436 | 453 | 0 | 1 | 00:00:02 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 12 | 0 | 3 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 29 | 436 | 456 | 0 | 7 | 00:00:03 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 1156593f9 Time (s): cpu = 00:02:38 ; elapsed = 00:02:45 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1085 ; free virtual = 19531 Phase 2.2 Global Placement Core | Checksum: 11797df4a Time (s): cpu = 00:02:44 ; elapsed = 00:02:51 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1078 ; free virtual = 19523 Phase 2 Global Placement | Checksum: 11797df4a Time (s): cpu = 00:02:44 ; elapsed = 00:02:51 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1101 ; free virtual = 19546 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e3b89a68 Time (s): cpu = 00:02:55 ; elapsed = 00:03:02 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1092 ; free virtual = 19538 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 11b5fb055 Time (s): cpu = 00:03:11 ; elapsed = 00:03:19 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1087 ; free virtual = 19532 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 19d93bc2f Time (s): cpu = 00:03:13 ; elapsed = 00:03:21 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1087 ; free virtual = 19532 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 132a1c86c Time (s): cpu = 00:03:14 ; elapsed = 00:03:22 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1086 ; free virtual = 19531 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1a10124bc Time (s): cpu = 00:03:30 ; elapsed = 00:03:39 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1091 ; free virtual = 19536 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 10bc87289 Time (s): cpu = 00:03:55 ; elapsed = 00:04:04 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1046 ; free virtual = 19491 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 8f564f43 Time (s): cpu = 00:03:59 ; elapsed = 00:04:08 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1048 ; free virtual = 19493 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 13c5e8558 Time (s): cpu = 00:04:01 ; elapsed = 00:04:10 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1048 ; free virtual = 19493 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: e3829648 Time (s): cpu = 00:04:25 ; elapsed = 00:04:35 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1043 ; free virtual = 19488 Phase 3 Detail Placement | Checksum: e3829648 Time (s): cpu = 00:04:26 ; elapsed = 00:04:35 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 1043 ; free virtual = 19488 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: e287a4bf Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Phase 4.1.1.1 BUFG Insertion | Checksum: e287a4bf Time (s): cpu = 00:05:00 ; elapsed = 00:05:10 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 842 ; free virtual = 19287 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.276. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 1a717d5ca Time (s): cpu = 00:06:10 ; elapsed = 00:06:21 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 855 ; free virtual = 19300 Phase 4.1 Post Commit Optimization | Checksum: 1a717d5ca Time (s): cpu = 00:06:11 ; elapsed = 00:06:22 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 855 ; free virtual = 19300 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1a717d5ca Time (s): cpu = 00:06:12 ; elapsed = 00:06:23 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 864 ; free virtual = 19310 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1a717d5ca Time (s): cpu = 00:06:13 ; elapsed = 00:06:24 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 865 ; free virtual = 19310 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 865 ; free virtual = 19310 Phase 4.4 Final Placement Cleanup | Checksum: 1e2637f96 Time (s): cpu = 00:06:14 ; elapsed = 00:06:25 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 865 ; free virtual = 19310 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e2637f96 Time (s): cpu = 00:06:14 ; elapsed = 00:06:25 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 865 ; free virtual = 19310 Ending Placer Task | Checksum: 101d64eb9 Time (s): cpu = 00:06:14 ; elapsed = 00:06:25 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 865 ; free virtual = 19310 INFO: [Common 17-83] Releasing license: Implementation 87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:06:21 ; elapsed = 00:06:32 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 920 ; free virtual = 19366 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 920 ; free virtual = 19366 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 653 ; free virtual = 19350 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 884 ; free virtual = 19354 INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.54 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 857 ; free virtual = 19328 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.43 . Memory (MB): peak = 4701.391 ; gain = 0.000 ; free physical = 881 ; free virtual = 19353 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: b53313bc ConstDB: 0 ShapeSum: 4ca33afd RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 9e35bf1d Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 4735.387 ; gain = 33.996 ; free physical = 541 ; free virtual = 19013 Post Restoration Checksum: NetGraph: 20116e3d NumContArr: 7e2450e0 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 9e35bf1d Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 4764.586 ; gain = 63.195 ; free physical = 518 ; free virtual = 18990 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 9e35bf1d Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 4771.789 ; gain = 70.398 ; free physical = 506 ; free virtual = 18978 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 9e35bf1d Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4771.793 ; gain = 70.402 ; free physical = 506 ; free virtual = 18978 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: dc7ea7f2 Time (s): cpu = 00:02:20 ; elapsed = 00:02:22 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 452 ; free virtual = 18924 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.117 | TNS=0.000 | WHS=-0.628 | THS=-2006.734| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: db613146 Time (s): cpu = 00:02:37 ; elapsed = 00:02:40 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 440 ; free virtual = 18911 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.117 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1437198d6 Time (s): cpu = 00:02:38 ; elapsed = 00:02:41 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 433 ; free virtual = 18911 Phase 2 Router Initialization | Checksum: 28b2e09cd Time (s): cpu = 00:02:38 ; elapsed = 00:02:41 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 433 ; free virtual = 18911 Router Utilization Summary Global Vertical Routing Utilization = 0.00134327 % Global Horizontal Routing Utilization = 0.00367647 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 49581 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 49580 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 18edad074 Time (s): cpu = 00:06:36 ; elapsed = 00:06:43 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 416 ; free virtual = 18893 INFO: [Route 35-580] Design has 15 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][25]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[12].mgt_source_data_regd_reg[12][data][19]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][5]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][4]/D| | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | regtxdata[22].mgt_source_data_regd_reg[22][data][7]/D| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 5180 Number of Nodes with overlaps = 757 Number of Nodes with overlaps = 194 Number of Nodes with overlaps = 67 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.103 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1a93290e4 Time (s): cpu = 00:08:43 ; elapsed = 00:08:53 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 416 ; free virtual = 18893 Phase 4 Rip-up And Reroute | Checksum: 1a93290e4 Time (s): cpu = 00:08:43 ; elapsed = 00:08:53 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 416 ; free virtual = 18893 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1bf388d39 Time (s): cpu = 00:08:51 ; elapsed = 00:09:01 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 415 ; free virtual = 18892 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.174 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Delay CleanUp | Checksum: 1efd9bc1a Time (s): cpu = 00:08:51 ; elapsed = 00:09:01 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 415 ; free virtual = 18892 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1efd9bc1a Time (s): cpu = 00:08:52 ; elapsed = 00:09:02 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 415 ; free virtual = 18892 Phase 5 Delay and Skew Optimization | Checksum: 1efd9bc1a Time (s): cpu = 00:08:52 ; elapsed = 00:09:02 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 415 ; free virtual = 18892 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1fb8d31c5 Time (s): cpu = 00:09:00 ; elapsed = 00:09:11 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 416 ; free virtual = 18893 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.174 | TNS=0.000 | WHS=-0.203 | THS=-0.203 | Phase 6.1 Hold Fix Iter | Checksum: 23dff9895 Time (s): cpu = 00:09:01 ; elapsed = 00:09:11 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 415 ; free virtual = 18892 Phase 6 Post Hold Fix | Checksum: 27cb532c3 Time (s): cpu = 00:09:01 ; elapsed = 00:09:11 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 414 ; free virtual = 18891 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 5.08953 % Global Horizontal Routing Utilization = 7.87604 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 2c4b433dd Time (s): cpu = 00:09:03 ; elapsed = 00:09:13 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 413 ; free virtual = 18890 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 2c4b433dd Time (s): cpu = 00:09:03 ; elapsed = 00:09:13 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 411 ; free virtual = 18888 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1 Phase 9 Depositing Routes | Checksum: 2a623a347 Time (s): cpu = 00:09:09 ; elapsed = 00:09:19 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 407 ; free virtual = 18885 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: 1d9710abf Time (s): cpu = 00:09:18 ; elapsed = 00:09:28 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 410 ; free virtual = 18888 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.174 | TNS=0.000 | WHS=0.056 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 1d9710abf Time (s): cpu = 00:09:18 ; elapsed = 00:09:29 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 410 ; free virtual = 18888 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:09:19 ; elapsed = 00:09:29 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 474 ; free virtual = 18951 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 109 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:09:29 ; elapsed = 00:09:40 . Memory (MB): peak = 4913.348 ; gain = 211.957 ; free physical = 474 ; free virtual = 18951 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified... INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 2173AF4, will use most recent tag v2.0.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: 2173af4 INFO: [Hog:Msg-0] The git SHA value 2173af4 will be set as bitstream USERID. INFO: [Hog:Msg-0] All done. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4913.348 ; gain = 0.000 ; free physical = 475 ; free virtual = 18953 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4913.348 ; gain = 0.000 ; free physical = 186 ; free virtual = 18937 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 4913.352 ; gain = 0.004 ; free physical = 432 ; free virtual = 18941 INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 4913.352 ; gain = 0.000 ; free physical = 413 ; free virtual = 18922 INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 5130.348 ; gain = 216.996 ; free physical = 326 ; free virtual = 18765 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 130 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 5180.363 ; gain = 50.016 ; free physical = 163 ; free virtual = 18562 INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5200.363 ; gain = 20.000 ; free physical = 155 ; free virtual = 18540 INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 5304.121 ; gain = 103.758 ; free physical = 247 ; free virtual = 18522 INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 142 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 5304.121 ; gain = 0.000 ; free physical = 240 ; free virtual = 18528 INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5304.121 ; gain = 0.000 ; free physical = 236 ; free virtual = 18525 INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Common 17-206] Exiting Vivado at Fri Apr 9 21:25:34 2021... *** Running vivado with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace Command: open_checkpoint top_FTM_DSS_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1595.273 ; gain = 0.000 ; free physical = 3792 ; free virtual = 22091 INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 Netlist sorting complete. Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2072.992 ; gain = 0.000 ; free physical = 3187 ; free virtual = 21486 INFO: [Netlist 29-17] Analyzing 3281 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3138.105 ; gain = 67.133 ; free physical = 2172 ; free virtual = 20470 Restored from archive | CPU: 6.540000 secs | Memory: 77.628105 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3138.105 ; gain = 67.133 ; free physical = 2172 ; free virtual = 20470 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3138.105 ; gain = 0.000 ; free physical = 2177 ; free virtual = 20476 INFO: [Project 1-111] Unisim Transformation Summary: A total of 40 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 6 instances SRLC32E => SRL16E: 2 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876 open_checkpoint: Time (s): cpu = 00:01:16 ; elapsed = 00:02:25 . Memory (MB): peak = 3138.105 ; gain = 1542.836 ; free physical = 2177 ; free virtual = 20475 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:Msg-0] All done Command: write_bitstream -force top_FTM_DSS.bit -bin_file Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. WARNING: [DRC RTSTAT-10] No routable loads: 25 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/s_bscan_tms, slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[13], slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[14]... and (the first 15 of 23 listed). INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 59691488 bits. Writing bitstream ./top_FTM_DSS.bit... Writing bitstream ./top_FTM_DSS.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Apr 9 21:32:16 2021. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 26 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:03:40 ; elapsed = 00:03:52 . Memory (MB): peak = 3817.445 ; gain = 679.340 ; free physical = 2058 ; free virtual = 20376 source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:GetVerFromSHA-0] No tag contains 2173AF4, will use most recent tag v2.0.1. As this is an official tag, patch will be incremented to 2. INFO: [Hog:Msg-0] Git describe set to: v2.0.1-2-g2173af4 INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.0.1-2-g2173af4... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.0.1-2-g2173af4/FTM_DSS-v2.0.1-2-g2173af4.bit...