*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_bcr.dcp' for cell 'slaves/buffer_control/bcr_delays'
Netlist sorting complete. Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.88 . Memory (MB): peak = 2100.492 ; gain = 4.000 ; free physical = 3082 ; free virtual = 21423
INFO: [Netlist 29-17] Analyzing 3265 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: slaves/buffer_control/bcr_delays UUID: b6fbd4f1-3519-5b57-8709-90667c26e79c 
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
get_clocks: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 3126.129 ; gain = 794.535 ; free physical = 2183 ; free virtual = 20524
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3299.023 ; gain = 0.000 ; free physical = 2234 ; free virtual = 20575
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 42 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances
  OBUFDS => OBUFDS: 10 instances

12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:01:05 ; elapsed = 00:02:03 . Memory (MB): peak = 3299.023 ; gain = 1660.121 ; free physical = 2234 ; free virtual = 20575
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci
Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx415t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:01 . Memory (MB): peak = 3315.031 ; gain = 8.004 ; free physical = 2233 ; free virtual = 20574

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 16e958fcc

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3323.031 ; gain = 8.000 ; free physical = 2002 ; free virtual = 20343

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3575.613 ; gain = 40.965 ; free physical = 1748 ; free virtual = 20095
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3575.613 ; gain = 0.000 ; free physical = 1749 ; free virtual = 20095
Phase 1 Generate And Synthesize Debug Cores | Checksum: d59bf91c

Time (s): cpu = 00:02:29 ; elapsed = 00:05:03 . Memory (MB): peak = 3575.617 ; gain = 72.840 ; free physical = 1748 ; free virtual = 20095

Phase 2 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 2 Retarget | Checksum: f753e5c3

Time (s): cpu = 00:02:34 ; elapsed = 00:05:09 . Memory (MB): peak = 3591.617 ; gain = 88.840 ; free physical = 1880 ; free virtual = 20227
INFO: [Opt 31-389] Phase Retarget created 63 cells and removed 129 cells
INFO: [Opt 31-1021] In phase Retarget, 112 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 3 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 3 Constant propagation | Checksum: 13f3cde53

Time (s): cpu = 00:02:35 ; elapsed = 00:05:09 . Memory (MB): peak = 3591.617 ; gain = 88.840 ; free physical = 1880 ; free virtual = 20226
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells
INFO: [Opt 31-1021] In phase Constant propagation, 47 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Sweep
Phase 4 Sweep | Checksum: 1ccda2763

Time (s): cpu = 00:02:40 ; elapsed = 00:05:14 . Memory (MB): peak = 3591.617 ; gain = 88.840 ; free physical = 1878 ; free virtual = 20224
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 580 cells
INFO: [Opt 31-1021] In phase Sweep, 1386 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 BUFG optimization
INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
Phase 5 BUFG optimization | Checksum: 123e47a25

Time (s): cpu = 00:02:41 ; elapsed = 00:05:16 . Memory (MB): peak = 3591.617 ; gain = 88.840 ; free physical = 1880 ; free virtual = 20227
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells.

Phase 6 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 6 Shift Register Optimization | Checksum: 123e47a25

Time (s): cpu = 00:02:42 ; elapsed = 00:05:17 . Memory (MB): peak = 3591.617 ; gain = 88.840 ; free physical = 1880 ; free virtual = 20227
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 7 Post Processing Netlist
Phase 7 Post Processing Netlist | Checksum: 1b594bbfa

Time (s): cpu = 00:02:43 ; elapsed = 00:05:17 . Memory (MB): peak = 3591.617 ; gain = 88.840 ; free physical = 1881 ; free virtual = 20227
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 58 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              63  |             129  |                                            112  |
|  Constant propagation         |               0  |              16  |                                             47  |
|  Sweep                        |               0  |             580  |                                           1386  |
|  BUFG optimization            |               0  |               4  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                             58  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3591.617 ; gain = 0.000 ; free physical = 1880 ; free virtual = 20227
Ending Logic Optimization Task | Checksum: 1b147c9c8

Time (s): cpu = 00:02:46 ; elapsed = 00:05:20 . Memory (MB): peak = 3591.617 ; gain = 88.840 ; free physical = 1880 ; free virtual = 20227

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.475 | TNS=0.000 |
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 644 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 1288
Ending PowerOpt Patch Enables Task | Checksum: f8ded796

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4701.836 ; gain = 0.000 ; free physical = 1591 ; free virtual = 19937
Ending Power Optimization Task | Checksum: f8ded796

Time (s): cpu = 00:01:36 ; elapsed = 00:01:41 . Memory (MB): peak = 4701.836 ; gain = 1110.219 ; free physical = 1698 ; free virtual = 20044

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 945686ef

Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4701.836 ; gain = 0.000 ; free physical = 1556 ; free virtual = 19903
Ending Final Cleanup Task | Checksum: 945686ef

Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 4701.836 ; gain = 0.000 ; free physical = 1554 ; free virtual = 19901

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.836 ; gain = 0.000 ; free physical = 1554 ; free virtual = 19901
Ending Netlist Obfuscation Task | Checksum: 945686ef

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.836 ; gain = 0.000 ; free physical = 1554 ; free virtual = 19901
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:04:56 ; elapsed = 00:07:40 . Memory (MB): peak = 4701.836 ; gain = 1402.812 ; free physical = 1554 ; free virtual = 19901
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-35] Done setting XDC timing constraints.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4701.836 ; gain = 0.000 ; free physical = 1278 ; free virtual = 19624
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 4701.836 ; gain = 0.000 ; free physical = 1072 ; free virtual = 19608
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 4701.840 ; gain = 0.004 ; free physical = 1244 ; free virtual = 19610
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1236 ; free virtual = 19602
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1234 ; free virtual = 19600
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7e0a097a

Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1234 ; free virtual = 19600
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1234 ; free virtual = 19600

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1002cef9

Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1217 ; free virtual = 19583

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 157f9effd

Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1171 ; free virtual = 19536

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 157f9effd

Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1170 ; free virtual = 19536
Phase 1 Placer Initialization | Checksum: 157f9effd

Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1165 ; free virtual = 19531

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 7b83844c

Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1144 ; free virtual = 19510

Phase 2.2 Global Placement Core

Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-1018] Found 1083 candidate LUT instances to create LUTNM shape
INFO: [Physopt 32-775] End 1 Pass. Optimized 450 nets or cells. Created 20 new cells, deleted 430 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-665] Processed cell slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_0. 4 registers were pushed out.
INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 4 new cells, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1128 ; free virtual = 19494
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1128 ; free virtual = 19494

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |           20  |            430  |                   450  |           0  |           1  |  00:00:02  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            4  |              0  |                     1  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |           24  |            430  |                   451  |           0  |           7  |  00:00:03  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2.1 Physical Synthesis In Placer | Checksum: cda8ebe0

Time (s): cpu = 00:02:13 ; elapsed = 00:02:20 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1129 ; free virtual = 19495
Phase 2.2 Global Placement Core | Checksum: d4ac2862

Time (s): cpu = 00:02:19 ; elapsed = 00:02:26 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1120 ; free virtual = 19486
Phase 2 Global Placement | Checksum: d4ac2862

Time (s): cpu = 00:02:20 ; elapsed = 00:02:26 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1143 ; free virtual = 19509

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 91c45032

Time (s): cpu = 00:02:29 ; elapsed = 00:02:36 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1135 ; free virtual = 19501

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 14f501ac1

Time (s): cpu = 00:02:45 ; elapsed = 00:02:53 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1130 ; free virtual = 19496

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 194aa45eb

Time (s): cpu = 00:02:47 ; elapsed = 00:02:54 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1130 ; free virtual = 19496

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1a8e8a3aa

Time (s): cpu = 00:02:47 ; elapsed = 00:02:55 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1129 ; free virtual = 19495

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 104004069

Time (s): cpu = 00:03:02 ; elapsed = 00:03:10 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1133 ; free virtual = 19499

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1449a7db5

Time (s): cpu = 00:03:24 ; elapsed = 00:03:32 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1085 ; free virtual = 19451

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: ab8db6f2

Time (s): cpu = 00:03:27 ; elapsed = 00:03:35 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1088 ; free virtual = 19454

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 8cd3c038

Time (s): cpu = 00:03:28 ; elapsed = 00:03:37 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1088 ; free virtual = 19454

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 1be7634d1

Time (s): cpu = 00:03:50 ; elapsed = 00:03:59 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1085 ; free virtual = 19451
Phase 3 Detail Placement | Checksum: 1be7634d1

Time (s): cpu = 00:03:51 ; elapsed = 00:04:00 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 1085 ; free virtual = 19451

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 15416b503

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 15416b503

Time (s): cpu = 00:04:24 ; elapsed = 00:04:33 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 885 ; free virtual = 19251
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.246. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1451de692

Time (s): cpu = 00:05:25 ; elapsed = 00:05:35 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 899 ; free virtual = 19265
Phase 4.1 Post Commit Optimization | Checksum: 1451de692

Time (s): cpu = 00:05:25 ; elapsed = 00:05:35 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 899 ; free virtual = 19265

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1451de692

Time (s): cpu = 00:05:27 ; elapsed = 00:05:37 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 908 ; free virtual = 19274

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1451de692

Time (s): cpu = 00:05:27 ; elapsed = 00:05:37 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 908 ; free virtual = 19275

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 908 ; free virtual = 19275
Phase 4.4 Final Placement Cleanup | Checksum: 18e32bb4a

Time (s): cpu = 00:05:28 ; elapsed = 00:05:38 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 908 ; free virtual = 19275
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18e32bb4a

Time (s): cpu = 00:05:29 ; elapsed = 00:05:39 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 908 ; free virtual = 19274
Ending Placer Task | Checksum: e1223dd9

Time (s): cpu = 00:05:29 ; elapsed = 00:05:39 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 908 ; free virtual = 19274
INFO: [Common 17-83] Releasing license: Implementation
85 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:05:35 ; elapsed = 00:05:45 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 965 ; free virtual = 19331
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 965 ; free virtual = 19331
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 699 ; free virtual = 19316
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 929 ; free virtual = 19320
INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.50 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 901 ; free virtual = 19292
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.40 . Memory (MB): peak = 4701.840 ; gain = 0.000 ; free physical = 925 ; free virtual = 19318
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: 947f02dc ConstDB: 0 ShapeSum: 4ca33afd RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 17affb3dc

Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 4731.836 ; gain = 29.996 ; free physical = 586 ; free virtual = 18978
Post Restoration Checksum: NetGraph: c2a31681 NumContArr: b85c9d5b Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 17affb3dc

Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 4761.035 ; gain = 59.195 ; free physical = 562 ; free virtual = 18955

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 17affb3dc

Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 4768.238 ; gain = 66.398 ; free physical = 551 ; free virtual = 18943

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 17affb3dc

Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 4768.242 ; gain = 66.402 ; free physical = 551 ; free virtual = 18943
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: a147d568

Time (s): cpu = 00:02:20 ; elapsed = 00:02:22 . Memory (MB): peak = 4868.797 ; gain = 166.957 ; free physical = 497 ; free virtual = 18890
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.111  | TNS=0.000  | WHS=-0.657 | THS=-2148.349|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 1739c0290

Time (s): cpu = 00:02:38 ; elapsed = 00:02:40 . Memory (MB): peak = 4868.797 ; gain = 166.957 ; free physical = 484 ; free virtual = 18877
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.111  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 123ee316c

Time (s): cpu = 00:02:38 ; elapsed = 00:02:40 . Memory (MB): peak = 4884.797 ; gain = 182.957 ; free physical = 484 ; free virtual = 18876
Phase 2 Router Initialization | Checksum: 1512e01cd

Time (s): cpu = 00:02:38 ; elapsed = 00:02:40 . Memory (MB): peak = 4884.797 ; gain = 182.957 ; free physical = 483 ; free virtual = 18876

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00304004 %
  Global Horizontal Routing Utilization  = 0.0029181 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 49614
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 49613
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 20803c596

Time (s): cpu = 00:06:55 ; elapsed = 00:07:01 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 465 ; free virtual = 18857
INFO: [Route 35-580] Design has 4 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
|       Launch Clock       |      Capture Clock       |                                                 Pin                                                      |
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                      regtxdata[8].mgt_source_data_regd_reg[8][data][17]/D|
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                      regtxdata[8].mgt_source_data_regd_reg[8][data][19]/D|
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[12].mgt_source_data_regd_reg[12][data][30]/D|
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[12].mgt_source_data_regd_reg[12][data][31]/D|
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 5171
 Number of Nodes with overlaps = 792
 Number of Nodes with overlaps = 162
 Number of Nodes with overlaps = 44
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.061  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 191eaedef

Time (s): cpu = 00:08:48 ; elapsed = 00:08:57 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 472 ; free virtual = 18865
Phase 4 Rip-up And Reroute | Checksum: 191eaedef

Time (s): cpu = 00:08:48 ; elapsed = 00:08:57 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 472 ; free virtual = 18865

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 191eaedef

Time (s): cpu = 00:08:49 ; elapsed = 00:08:58 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 472 ; free virtual = 18865

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 191eaedef

Time (s): cpu = 00:08:49 ; elapsed = 00:08:58 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 472 ; free virtual = 18865
Phase 5 Delay and Skew Optimization | Checksum: 191eaedef

Time (s): cpu = 00:08:49 ; elapsed = 00:08:58 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 472 ; free virtual = 18865

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1b4c2a3d2

Time (s): cpu = 00:08:58 ; elapsed = 00:09:07 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 473 ; free virtual = 18865
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.154  | TNS=0.000  | WHS=0.032  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1f8a514ce

Time (s): cpu = 00:08:59 ; elapsed = 00:09:08 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 473 ; free virtual = 18865
Phase 6 Post Hold Fix | Checksum: 1f8a514ce

Time (s): cpu = 00:08:59 ; elapsed = 00:09:08 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 473 ; free virtual = 18865

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 5.17705 %
  Global Horizontal Routing Utilization  = 7.42479 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 20057d3b5

Time (s): cpu = 00:09:00 ; elapsed = 00:09:09 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 471 ; free virtual = 18864

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 20057d3b5

Time (s): cpu = 00:09:00 ; elapsed = 00:09:09 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 469 ; free virtual = 18862

Phase 9 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1
Phase 9 Depositing Routes | Checksum: 20455070e

Time (s): cpu = 00:09:07 ; elapsed = 00:09:16 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 466 ; free virtual = 18859

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.154  | TNS=0.000  | WHS=0.032  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 20455070e

Time (s): cpu = 00:09:07 ; elapsed = 00:09:16 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 471 ; free virtual = 18863
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:09:07 ; elapsed = 00:09:17 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 526 ; free virtual = 18919

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
106 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:09:18 ; elapsed = 00:09:28 . Memory (MB): peak = 4893.797 ; gain = 191.957 ; free physical = 526 ; free virtual = 18919
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified...
INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean.
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains 8F3C8C6, will use most recent tag v2.0.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:GetVerFromSHA-0] No tag contains 51AD2FB, will use most recent tag v2.0.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: 51ad2fb
INFO: [Hog:Msg-0] The git SHA value 51ad2fb will be set as bitstream USERID.
INFO: [Hog:Msg-0] All done.
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4893.797 ; gain = 0.000 ; free physical = 527 ; free virtual = 18919
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 4893.797 ; gain = 0.000 ; free physical = 240 ; free virtual = 18905
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 4893.801 ; gain = 0.004 ; free physical = 490 ; free virtual = 18914
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 4893.801 ; gain = 0.000 ; free physical = 471 ; free virtual = 18895
INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:55 ; elapsed = 00:00:56 . Memory (MB): peak = 5126.797 ; gain = 232.996 ; free physical = 308 ; free virtual = 18733
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
128 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 5176.805 ; gain = 50.008 ; free physical = 152 ; free virtual = 18527
INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5196.805 ; gain = 20.000 ; free physical = 154 ; free virtual = 18505
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 5300.562 ; gain = 103.758 ; free physical = 257 ; free virtual = 18494
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
140 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 5300.562 ; gain = 0.000 ; free physical = 250 ; free virtual = 18499
INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5300.562 ; gain = 0.000 ; free physical = 245 ; free virtual = 18495
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
INFO: [Common 17-206] Exiting Vivado at Mon May 17 19:25:18 2021...

*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: open_checkpoint top_FTM_DSS_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1595.277 ; gain = 0.000 ; free physical = 3813 ; free virtual = 22060
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
Netlist sorting complete. Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2073.027 ; gain = 0.000 ; free physical = 3208 ; free virtual = 21455
INFO: [Netlist 29-17] Analyzing 3281 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3138.148 ; gain = 67.133 ; free physical = 2193 ; free virtual = 20440
Restored from archive | CPU: 6.320000 secs | Memory: 77.129211 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3138.148 ; gain = 67.133 ; free physical = 2193 ; free virtual = 20440
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3138.148 ; gain = 0.000 ; free physical = 2198 ; free virtual = 20445
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 40 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 6 instances
  SRLC32E => SRL16E: 2 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876
open_checkpoint: Time (s): cpu = 00:01:17 ; elapsed = 00:02:26 . Memory (MB): peak = 3138.148 ; gain = 1542.875 ; free physical = 2198 ; free virtual = 20445
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: write_bitstream -force top_FTM_DSS.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [DRC RTSTAT-10] No routable loads: 25 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/s_bscan_tms, slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[13], slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[14]... and (the first 15 of 23 listed).
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 60952320 bits.
Writing bitstream ./top_FTM_DSS.bit...
Writing bitstream ./top_FTM_DSS.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Mon May 17 19:32:04 2021. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
26 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:03:42 ; elapsed = 00:03:55 . Memory (MB): peak = 3815.457 ; gain = 677.309 ; free physical = 2083 ; free virtual = 20349
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains 8F3C8C6, will use most recent tag v2.0.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:GetVerFromSHA-0] No tag contains 51AD2FB, will use most recent tag v2.0.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Git describe set to: v2.0.2-4-g51ad2fb
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.0.2-4-g51ad2fb...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.0.2-4-g51ad2fb/FTM_DSS-v2.0.2-4-g51ad2fb.bit...