*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_bcr.dcp' for cell 'slaves/buffer_control/bcr_delays'
Netlist sorting complete. Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2101.043 ; gain = 4.000 ; free physical = 2882 ; free virtual = 21493
INFO: [Netlist 29-17] Analyzing 3273 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: slaves/buffer_control/bcr_delays UUID: b6fbd4f1-3519-5b57-8709-90667c26e79c 
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
get_clocks: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 3126.344 ; gain = 795.168 ; free physical = 1984 ; free virtual = 20596
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3300.238 ; gain = 0.000 ; free physical = 2037 ; free virtual = 20648
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 42 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances
  OBUFDS => OBUFDS: 10 instances

12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:01:04 ; elapsed = 00:02:01 . Memory (MB): peak = 3300.238 ; gain = 1661.152 ; free physical = 2037 ; free virtual = 20648
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci
Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx415t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:01 . Memory (MB): peak = 3316.246 ; gain = 8.004 ; free physical = 2036 ; free virtual = 20647

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1f041576b

Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3323.246 ; gain = 7.000 ; free physical = 1802 ; free virtual = 20413

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3576.828 ; gain = 41.965 ; free physical = 1732 ; free virtual = 20170
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3576.828 ; gain = 0.000 ; free physical = 1732 ; free virtual = 20171
Phase 1 Generate And Synthesize Debug Cores | Checksum: 1577fef18

Time (s): cpu = 00:02:30 ; elapsed = 00:05:07 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1732 ; free virtual = 20170

Phase 2 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 2 Retarget | Checksum: 19502fd86

Time (s): cpu = 00:02:36 ; elapsed = 00:05:13 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1865 ; free virtual = 20303
INFO: [Opt 31-389] Phase Retarget created 63 cells and removed 129 cells
INFO: [Opt 31-1021] In phase Retarget, 112 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 3 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 3 Constant propagation | Checksum: 12f330d9d

Time (s): cpu = 00:02:36 ; elapsed = 00:05:14 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1865 ; free virtual = 20303
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells
INFO: [Opt 31-1021] In phase Constant propagation, 47 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Sweep
Phase 4 Sweep | Checksum: 1dec56a78

Time (s): cpu = 00:02:41 ; elapsed = 00:05:19 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1860 ; free virtual = 20301
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 700 cells
INFO: [Opt 31-1021] In phase Sweep, 1386 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 BUFG optimization
INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
Phase 5 BUFG optimization | Checksum: 1eb998c68

Time (s): cpu = 00:02:43 ; elapsed = 00:05:21 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1862 ; free virtual = 20303
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells.

Phase 6 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 6 Shift Register Optimization | Checksum: 1eb998c68

Time (s): cpu = 00:02:44 ; elapsed = 00:05:22 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1862 ; free virtual = 20303
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 7 Post Processing Netlist
Phase 7 Post Processing Netlist | Checksum: 13d789cab

Time (s): cpu = 00:02:44 ; elapsed = 00:05:22 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1859 ; free virtual = 20304
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 58 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              63  |             129  |                                            112  |
|  Constant propagation         |               0  |              16  |                                             47  |
|  Sweep                        |               0  |             700  |                                           1386  |
|  BUFG optimization            |               0  |               4  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                             58  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3576.832 ; gain = 0.000 ; free physical = 1859 ; free virtual = 20304
Ending Logic Optimization Task | Checksum: 197fee11e

Time (s): cpu = 00:02:47 ; elapsed = 00:05:26 . Memory (MB): peak = 3576.832 ; gain = 73.840 ; free physical = 1859 ; free virtual = 20303

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.475 | TNS=0.000 |
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 644 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 1288
Ending PowerOpt Patch Enables Task | Checksum: 22e0224d1

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4702.105 ; gain = 0.000 ; free physical = 1558 ; free virtual = 20014
Ending Power Optimization Task | Checksum: 22e0224d1

Time (s): cpu = 00:01:36 ; elapsed = 00:01:42 . Memory (MB): peak = 4702.105 ; gain = 1125.273 ; free physical = 1668 ; free virtual = 20125

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: f35a146a

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 4702.105 ; gain = 0.000 ; free physical = 1525 ; free virtual = 19983
Ending Final Cleanup Task | Checksum: f35a146a

Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 4702.105 ; gain = 0.000 ; free physical = 1523 ; free virtual = 19981

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4702.105 ; gain = 0.000 ; free physical = 1523 ; free virtual = 19981
Ending Netlist Obfuscation Task | Checksum: f35a146a

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4702.105 ; gain = 0.000 ; free physical = 1523 ; free virtual = 19981
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:04:58 ; elapsed = 00:07:46 . Memory (MB): peak = 4702.105 ; gain = 1401.867 ; free physical = 1523 ; free virtual = 19981
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-35] Done setting XDC timing constraints.
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4702.105 ; gain = 0.000 ; free physical = 1243 ; free virtual = 19701
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.19 . Memory (MB): peak = 4702.105 ; gain = 0.000 ; free physical = 1038 ; free virtual = 19686
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 4702.109 ; gain = 0.004 ; free physical = 1210 ; free virtual = 19688
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1202 ; free virtual = 19680
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1200 ; free virtual = 19678
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 92e0832a

Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1200 ; free virtual = 19678
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1200 ; free virtual = 19678

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15359707

Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1179 ; free virtual = 19659

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 18dbb532e

Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1131 ; free virtual = 19614

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 18dbb532e

Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1131 ; free virtual = 19614
Phase 1 Placer Initialization | Checksum: 18dbb532e

Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1127 ; free virtual = 19610

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 18c5b7378

Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1105 ; free virtual = 19588

Phase 2.2 Global Placement Core

Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-1018] Found 1079 candidate LUT instances to create LUTNM shape
INFO: [Physopt 32-775] End 1 Pass. Optimized 451 nets or cells. Created 6 new cells, deleted 445 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-46] Identified 10 candidate nets for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1084 ; free virtual = 19568

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            6  |            445  |                   451  |           0  |           1  |  00:00:02  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  Critical Cell                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            6  |            445  |                   451  |           0  |           8  |  00:00:03  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2.1 Physical Synthesis In Placer | Checksum: 11965ffc7

Time (s): cpu = 00:02:24 ; elapsed = 00:02:31 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1083 ; free virtual = 19568
Phase 2.2 Global Placement Core | Checksum: 29561bc37

Time (s): cpu = 00:02:30 ; elapsed = 00:02:38 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1075 ; free virtual = 19559
Phase 2 Global Placement | Checksum: 29561bc37

Time (s): cpu = 00:02:30 ; elapsed = 00:02:38 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1098 ; free virtual = 19582

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 214ea8f0e

Time (s): cpu = 00:02:40 ; elapsed = 00:02:48 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1090 ; free virtual = 19574

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c8a53b50

Time (s): cpu = 00:02:57 ; elapsed = 00:03:05 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1086 ; free virtual = 19570

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 28d7ed671

Time (s): cpu = 00:02:58 ; elapsed = 00:03:06 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1086 ; free virtual = 19570

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 24abfed82

Time (s): cpu = 00:03:00 ; elapsed = 00:03:08 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1085 ; free virtual = 19569

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 2612602e1

Time (s): cpu = 00:03:15 ; elapsed = 00:03:24 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1088 ; free virtual = 19572

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1bb9d6001

Time (s): cpu = 00:03:37 ; elapsed = 00:03:47 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1038 ; free virtual = 19522

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 15950e022

Time (s): cpu = 00:03:41 ; elapsed = 00:03:50 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1041 ; free virtual = 19525

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 2d5d6cb74

Time (s): cpu = 00:03:43 ; elapsed = 00:03:52 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1041 ; free virtual = 19525

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 1c07a36a1

Time (s): cpu = 00:04:06 ; elapsed = 00:04:16 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1038 ; free virtual = 19522
Phase 3 Detail Placement | Checksum: 1c07a36a1

Time (s): cpu = 00:04:06 ; elapsed = 00:04:16 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 1038 ; free virtual = 19522

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1afa99188

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1afa99188

Time (s): cpu = 00:04:41 ; elapsed = 00:04:51 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 835 ; free virtual = 19319
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.109. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1a67f6061

Time (s): cpu = 00:05:40 ; elapsed = 00:05:51 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 849 ; free virtual = 19333
Phase 4.1 Post Commit Optimization | Checksum: 1a67f6061

Time (s): cpu = 00:05:41 ; elapsed = 00:05:52 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 849 ; free virtual = 19333

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1a67f6061

Time (s): cpu = 00:05:42 ; elapsed = 00:05:53 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 858 ; free virtual = 19342

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1a67f6061

Time (s): cpu = 00:05:43 ; elapsed = 00:05:54 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 859 ; free virtual = 19343

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 859 ; free virtual = 19343
Phase 4.4 Final Placement Cleanup | Checksum: 1a74f5b37

Time (s): cpu = 00:05:43 ; elapsed = 00:05:54 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 859 ; free virtual = 19343
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a74f5b37

Time (s): cpu = 00:05:44 ; elapsed = 00:05:55 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 859 ; free virtual = 19343
Ending Placer Task | Checksum: 10d22ae1a

Time (s): cpu = 00:05:44 ; elapsed = 00:05:55 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 859 ; free virtual = 19343
INFO: [Common 17-83] Releasing license: Implementation
88 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:05:50 ; elapsed = 00:06:02 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 914 ; free virtual = 19398
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 914 ; free virtual = 19398
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 646 ; free virtual = 19382
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 876 ; free virtual = 19386
INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.48 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 849 ; free virtual = 19359
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.39 . Memory (MB): peak = 4702.109 ; gain = 0.000 ; free physical = 873 ; free virtual = 19384
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: 43335f0d ConstDB: 0 ShapeSum: c9ef4f0d RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: f51f2f79

Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 4740.105 ; gain = 37.996 ; free physical = 535 ; free virtual = 19046
Post Restoration Checksum: NetGraph: 7da47ef2 NumContArr: 777ab087 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: f51f2f79

Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 4769.305 ; gain = 67.195 ; free physical = 512 ; free virtual = 19023

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: f51f2f79

Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 4776.508 ; gain = 74.398 ; free physical = 500 ; free virtual = 19011

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: f51f2f79

Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 4776.512 ; gain = 74.402 ; free physical = 500 ; free virtual = 19011
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 187de6fd5

Time (s): cpu = 00:02:21 ; elapsed = 00:02:24 . Memory (MB): peak = 4915.066 ; gain = 212.957 ; free physical = 448 ; free virtual = 18959
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.017 | TNS=-0.017 | WHS=-0.358 | THS=-2070.530|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 1b00af603

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 4915.066 ; gain = 212.957 ; free physical = 436 ; free virtual = 18947
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.017 | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 16e0d1f6e

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 4915.066 ; gain = 212.957 ; free physical = 436 ; free virtual = 18947
Phase 2 Router Initialization | Checksum: 1c9682612

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 4915.066 ; gain = 212.957 ; free physical = 436 ; free virtual = 18947

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00206036 %
  Global Horizontal Routing Utilization  = 0.00146729 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 49750
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 49749
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 905704ff

Time (s): cpu = 00:08:19 ; elapsed = 00:08:28 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 408 ; free virtual = 18919
INFO: [Route 35-580] Design has 14 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
|       Launch Clock       |      Capture Clock       |                                                 Pin                                                      |
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[18].mgt_source_data_regd_reg[18][data][24]/D|
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[18].mgt_source_data_regd_reg[18][data][25]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[43].mgt_source_data_regd_reg[43][data][27]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[43].mgt_source_data_regd_reg[43][data][16]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[45].mgt_source_data_regd_reg[45][data][12]/D|
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 5237
 Number of Nodes with overlaps = 801
 Number of Nodes with overlaps = 177
 Number of Nodes with overlaps = 25
 Number of Nodes with overlaps = 14
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.010 | TNS=-0.010 | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 10f54d434

Time (s): cpu = 00:10:48 ; elapsed = 00:11:00 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 413 ; free virtual = 18923

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 258
 Number of Nodes with overlaps = 74
 Number of Nodes with overlaps = 32
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.010  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 1a31b1f5d

Time (s): cpu = 00:11:24 ; elapsed = 00:11:36 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 412 ; free virtual = 18923
Phase 4 Rip-up And Reroute | Checksum: 1a31b1f5d

Time (s): cpu = 00:11:24 ; elapsed = 00:11:36 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 412 ; free virtual = 18923

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1a31b1f5d

Time (s): cpu = 00:11:25 ; elapsed = 00:11:37 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 412 ; free virtual = 18923

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1a31b1f5d

Time (s): cpu = 00:11:25 ; elapsed = 00:11:37 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 412 ; free virtual = 18923
Phase 5 Delay and Skew Optimization | Checksum: 1a31b1f5d

Time (s): cpu = 00:11:25 ; elapsed = 00:11:37 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 412 ; free virtual = 18923

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 18ea9eece

Time (s): cpu = 00:11:34 ; elapsed = 00:11:46 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 415 ; free virtual = 18926
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.114  | TNS=0.000  | WHS=-0.127 | THS=-0.127 |

Phase 6.1 Hold Fix Iter | Checksum: a30690a2

Time (s): cpu = 00:11:35 ; elapsed = 00:11:47 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 415 ; free virtual = 18926
Phase 6 Post Hold Fix | Checksum: b5f384ad

Time (s): cpu = 00:11:35 ; elapsed = 00:11:47 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 414 ; free virtual = 18925

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 5.28571 %
  Global Horizontal Routing Utilization  = 7.65522 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 11c5e9395

Time (s): cpu = 00:11:36 ; elapsed = 00:11:48 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 413 ; free virtual = 18924

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 11c5e9395

Time (s): cpu = 00:11:36 ; elapsed = 00:11:49 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 412 ; free virtual = 18923

Phase 9 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1
Phase 9 Depositing Routes | Checksum: 162de7820

Time (s): cpu = 00:11:43 ; elapsed = 00:11:55 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 408 ; free virtual = 18919

Phase 10 Post Router Timing

Phase 10.1 Update Timing
Phase 10.1 Update Timing | Checksum: 131792c68

Time (s): cpu = 00:11:52 ; elapsed = 00:12:04 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 411 ; free virtual = 18922
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.114  | TNS=0.000  | WHS=0.056  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 131792c68

Time (s): cpu = 00:11:52 ; elapsed = 00:12:04 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 411 ; free virtual = 18922
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:11:52 ; elapsed = 00:12:05 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 468 ; free virtual = 18981

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
110 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:12:03 ; elapsed = 00:12:16 . Memory (MB): peak = 4991.066 ; gain = 288.957 ; free physical = 468 ; free virtual = 18981
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified...
INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean.
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains C6E5DAF, will use most recent tag v2.1.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:GetVerFromSHA-0] No tag contains 3947DEB, will use most recent tag v2.1.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: c6e5daf
INFO: [Hog:Msg-0] The git SHA value c6e5daf will be set as bitstream USERID.
INFO: [Hog:Msg-0] All done.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4991.066 ; gain = 0.000 ; free physical = 469 ; free virtual = 18982
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4991.066 ; gain = 0.000 ; free physical = 180 ; free virtual = 18967
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 4991.070 ; gain = 0.004 ; free physical = 427 ; free virtual = 18971
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 4991.070 ; gain = 0.000 ; free physical = 410 ; free virtual = 18954
INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:01:00 ; elapsed = 00:01:05 . Memory (MB): peak = 5130.066 ; gain = 138.996 ; free physical = 344 ; free virtual = 18800
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
132 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 5177.082 ; gain = 47.016 ; free physical = 183 ; free virtual = 18601
INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5197.082 ; gain = 20.000 ; free physical = 146 ; free virtual = 18579
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 5302.840 ; gain = 105.758 ; free physical = 266 ; free virtual = 18562
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
144 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 5302.840 ; gain = 0.000 ; free physical = 258 ; free virtual = 18567
INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5302.840 ; gain = 0.000 ; free physical = 254 ; free virtual = 18564
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
INFO: [Common 17-206] Exiting Vivado at Thu Aug 12 17:11:50 2021...

*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: open_checkpoint top_FTM_DSS_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1594.309 ; gain = 0.000 ; free physical = 3720 ; free virtual = 22128
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
Netlist sorting complete. Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2073.492 ; gain = 0.000 ; free physical = 3115 ; free virtual = 21522
INFO: [Netlist 29-17] Analyzing 3289 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3139.023 ; gain = 67.133 ; free physical = 2091 ; free virtual = 20507
Restored from archive | CPU: 6.780000 secs | Memory: 77.938606 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3139.023 ; gain = 67.133 ; free physical = 2091 ; free virtual = 20507
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3139.023 ; gain = 0.000 ; free physical = 2097 ; free virtual = 20512
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 40 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 6 instances
  SRLC32E => SRL16E: 2 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876
open_checkpoint: Time (s): cpu = 00:01:18 ; elapsed = 00:02:28 . Memory (MB): peak = 3139.023 ; gain = 1544.719 ; free physical = 2097 ; free virtual = 20512
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: write_bitstream -force top_FTM_DSS.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [DRC RTSTAT-10] No routable loads: 25 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/s_bscan_tms, slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[13], slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[14]... and (the first 15 of 23 listed).
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 61483232 bits.
Writing bitstream ./top_FTM_DSS.bit...
Writing bitstream ./top_FTM_DSS.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Aug 12 17:18:42 2021. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
26 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:03:44 ; elapsed = 00:03:57 . Memory (MB): peak = 3835.184 ; gain = 696.160 ; free physical = 1970 ; free virtual = 20413
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains C6E5DAF, will use most recent tag v2.1.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:GetVerFromSHA-0] No tag contains 3947DEB, will use most recent tag v2.1.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Git describe set to: v2.1.2-7-gc6e5daf
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.1.2-7-gc6e5daf...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.1.2-7-gc6e5daf/FTM_DSS-v2.1.2-7-gc6e5daf.bit...