Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
| Date             : Tue Aug 17 18:27:43 2021
| Host             : hog-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
| Command          : report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx
| Design           : top_ftm_control
| Device           : xc7k325tffg900-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 1.647        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 1.443        |
| Device Static (W)        | 0.203        |
| Effective TJA (C/W)      | 1.8          |
| Max Ambient (C)          | 82.1         |
| Junction Temperature (C) | 27.9         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.092 |       23 |       --- |             --- |
| Slice Logic              |     0.019 |    28369 |       --- |             --- |
|   LUT as Logic           |     0.016 |     9835 |    203800 |            4.83 |
|   Register               |     0.002 |    13972 |    407600 |            3.43 |
|   CARRY4                 |    <0.001 |      453 |     50950 |            0.89 |
|   LUT as Shift Register  |    <0.001 |      474 |     64000 |            0.74 |
|   LUT as Distributed RAM |    <0.001 |       68 |     64000 |            0.11 |
|   F7/F8 Muxes            |    <0.001 |      280 |    203800 |            0.14 |
|   BUFG                   |    <0.001 |        1 |        32 |            3.13 |
|   Others                 |     0.000 |     1211 |       --- |             --- |
| Signals                  |     0.032 |    22622 |       --- |             --- |
| Block RAM                |     0.210 |      320 |       445 |           71.91 |
| MMCM                     |     0.229 |        2 |        10 |           20.00 |
| I/O                      |     0.572 |      198 |       500 |           39.60 |
| GTX                      |     0.288 |        1 |        16 |            6.25 |
| XADC                     |    <0.001 |        1 |       --- |             --- |
| Static Power             |     0.203 |          |           |                 |
| Total                    |     1.647 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.464 |       0.380 |      0.085 |
| Vccaux    |       1.800 |     0.200 |       0.172 |      0.029 |
| Vcco33    |       3.300 |     0.002 |       0.001 |      0.001 |
| Vcco25    |       2.500 |     0.009 |       0.008 |      0.001 |
| Vcco18    |       1.800 |     0.251 |       0.250 |      0.001 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.030 |       0.017 |      0.013 |
| MGTAVcc   |       1.000 |     0.151 |       0.147 |      0.005 |
| MGTAVtt   |       1.200 |     0.090 |       0.084 |      0.005 |
| MGTVccaux |       1.800 |     0.009 |       0.009 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 1.8                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 3.3                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+-----------------+
| Clock                                                                                                | Domain                                                                                               | Constraint (ns) |
+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+-----------------+
| I                                                                                                    | clocks/I                                                                                             |             5.0 |
| cdrclk                                                                                               | cdrclk_p                                                                                             |             6.2 |
| clk200                                                                                               | clocks/clk200                                                                                        |             5.0 |
| clk40M_in                                                                                            | clk40M_p                                                                                             |            24.9 |
| clk_125_i                                                                                            | clocks/clk_125_i                                                                                     |             8.0 |
| clk_ipb_i                                                                                            | clocks/clk_ipb_i                                                                                     |            32.0 |
| clkfbout                                                                                             | clocks/clkfbout                                                                                      |             8.0 |
| clkfbout_1                                                                                           | ttc/pll/clkfbout                                                                                     |            25.0 |
| clkout0                                                                                              | ttc/pll/clkout0                                                                                      |             6.2 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK           | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/tck_bs                                 |            33.0 |
| flash_spi_clk                                                                                        | slaves/spi_flash/spi_clk                                                                             |            16.0 |
| gmii_rx_clk                                                                                          | gmii_rx_clk                                                                                          |             8.0 |
| mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/RXOUTCLK | mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0/gtwizard_0_i/gt0_gtwizard_0_i/gt0_rxoutclk_out |             6.2 |
| mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK | mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0/gtwizard_0_i/gt0_gtwizard_0_i/gt0_txoutclk_out |             6.2 |
| mgtrefclk160                                                                                         | Q0_CLK0_GTREFCLK_PAD_P_IN                                                                            |             6.2 |
| onehz                                                                                                | clocks/clkdiv/in0                                                                                    |          1000.0 |
| pll_spi_clk                                                                                          | slaves/spi_pll/spi_clk                                                                               |            16.0 |
| sysclk                                                                                               | sysclk_p                                                                                             |             8.0 |
+------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+-------------------------------+-----------+
| Name                          | Power (W) |
+-------------------------------+-----------+
| top_ftm_control               |     1.443 |
|   clocks                      |     0.115 |
|     clkdiv                    |     0.002 |
|   dbg_hub                     |     0.004 |
|     inst                      |     0.004 |
|       BSCANID.u_xsdbm_id      |     0.004 |
|   eth                         |     0.036 |
|     emac0                     |     0.035 |
|       U0                      |     0.035 |
|     fifo                      |     0.001 |
|       U0                      |     0.001 |
|   ipbus                       |     0.054 |
|     trans                     |     0.011 |
|       iface                   |     0.003 |
|       sm                      |     0.008 |
|     udp_if                    |     0.043 |
|       IPADDR                  |     0.002 |
|       internal_ram            |     0.003 |
|       ipbus_rx_ram            |     0.008 |
|       ipbus_tx_ram            |     0.006 |
|       payload                 |     0.002 |
|       primary_mode.ARP        |     0.001 |
|       primary_mode.RARP_block |     0.002 |
|       primary_mode.ping       |     0.001 |
|       rx_packet_parser        |     0.004 |
|       status                  |     0.001 |
|       status_buffer           |     0.004 |
|       tx_main                 |     0.002 |
|       tx_transactor           |     0.002 |
|   mgt_ttcinfo                 |     0.326 |
|     gtwizard_0_support_i      |     0.293 |
|       gtwizard_0_init_i       |     0.292 |
|     rx_data                   |     0.020 |
|       U0                      |     0.020 |
|     tx_data                   |     0.012 |
|       U0                      |     0.012 |
|   pll_sync_reset              |     0.009 |
|     U0                        |     0.009 |
|       ila_core_inst           |     0.009 |
|   slaves                      |     0.223 |
|     l1a_generator             |     0.003 |
|       delay_memory            |     0.002 |
|     monitoring                |     0.001 |
|       adc_inst                |     0.001 |
|     rx_bufs                   |     0.084 |
|       bufgen[0].rxbuf         |     0.005 |
|       bufgen[10].rxbuf        |     0.005 |
|       bufgen[11].rxbuf        |     0.005 |
|       bufgen[12].rxbuf        |     0.005 |
|       bufgen[13].rxbuf        |     0.005 |
|       bufgen[14].rxbuf        |     0.005 |
|       bufgen[15].rxbuf        |     0.005 |
|       bufgen[1].rxbuf         |     0.005 |
|       bufgen[2].rxbuf         |     0.005 |
|       bufgen[3].rxbuf         |     0.005 |
|       bufgen[4].rxbuf         |     0.005 |
|       bufgen[5].rxbuf         |     0.005 |
|       bufgen[6].rxbuf         |     0.005 |
|       bufgen[7].rxbuf         |     0.005 |
|       bufgen[8].rxbuf         |     0.005 |
|       bufgen[9].rxbuf         |     0.005 |
|     spi_flash                 |     0.005 |
|       spi_dpram_in            |     0.001 |
|       spi_dpram_out           |     0.002 |
|       spi_engine              |     0.001 |
|     spi_pll                   |     0.005 |
|       spi_dpram_out           |     0.002 |
|     ttc_info                  |     0.023 |
|       ttcin                   |     0.017 |
|       ttcout                  |     0.005 |
|     tx_bufs                   |     0.096 |
|       bufgen[0].txbuf         |     0.006 |
|       bufgen[10].txbuf        |     0.006 |
|       bufgen[11].txbuf        |     0.006 |
|       bufgen[12].txbuf        |     0.006 |
|       bufgen[13].txbuf        |     0.006 |
|       bufgen[14].txbuf        |     0.006 |
|       bufgen[15].txbuf        |     0.006 |
|       bufgen[1].txbuf         |     0.006 |
|       bufgen[2].txbuf         |     0.006 |
|       bufgen[3].txbuf         |     0.006 |
|       bufgen[4].txbuf         |     0.006 |
|       bufgen[5].txbuf         |     0.006 |
|       bufgen[6].txbuf         |     0.006 |
|       bufgen[7].txbuf         |     0.006 |
|       bufgen[8].txbuf         |     0.006 |
|       bufgen[9].txbuf         |     0.006 |
|   ttc                         |     0.129 |
|     pll                       |     0.123 |
|     ttc_dec                   |     0.007 |
|       from_cdr_to_AandB       |     0.002 |
|       serialb_com0            |     0.003 |
+-------------------------------+-----------+


