*** Running vivado with args -log top_FTM_DSS.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_FTM_DSS.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source top_FTM_DSS.tcl -notrace source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-synthesis.tcl INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Found Projects/hog_reset_files, opening it... INFO: [Hog:Msg-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:Msg-0] No modified *.bd files found. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean. INFO: [Hog:Msg-0] Git describe for 875f4f8 is: v2.1.5-3-g875f4f8 INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: 875f4f8 INFO: [Hog:Msg-0] The commit in which project FTM_DSS was last modified is 875f4f8, that is 4 commits older than current commit 424fd65. INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml and replacing placeholders with xml version 02010005... INFO: [Hog:CopyXMLsFromListFile-0] 15 lines read from ./Top/FTM_DSS/list/xml.lst INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/L1CaloFtmDSS.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_common_IdVersion.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_control.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_xadc.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_reconfigure.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_flash_spi_ram.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_mgt_registers.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_3quad_registers.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_buf_control.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_mgt_rx_monitor.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_error_counters.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_source_ram.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_sink_ram.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_dss_mgt_sink.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] 14 file/s copied INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of L1CaloFtmDSS.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_common_IdVersion.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_control.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_xadc.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_reconfigure.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_flash_spi_ram.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_mgt_registers.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_3quad_registers.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_buf_control.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_mgt_rx_monitor.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_error_counters.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_source_ram.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_sink_ram.xml as no VHDL file was specified. INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_dss_mgt_sink.xml as no VHDL file was specified. INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/versions.txt... INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v2.1.5-3-g875f4f8... INFO: [Hog:Msg-0] Evaluating non committed changes... INFO: [Hog:Msg-0] No uncommitted changes found. ------------------------- PRE SYNTHESIS ------------------------- 04/01/2022 at 17:24:51 Firmware date and time: '21092021', '00151245' Global SHA: 875f4f8, VER: 2.1.6 Constraints SHA: 875F4F8, VER: 2.1.6 IPbus XML SHA: EB4F800, VER: 2.1.5 Top SHA: AB7034F, VER: 0.0.21 Hog SHA: 6C02797, VER: 3.0.0 --- Libraries --- ftm SHA: 875F4F8, VER: 2.1.6 --- External Libraries --- ----------------------------------------------------------------- INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with v3.0.0 in .gitlab-ci.yml. INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0 INFO: [Hog:Msg-0] Opening project FTM_DSS... Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'. INFO: [Hog:Msg-0] Checking FTM_DSS list files... INFO: [Hog:Msg-0] List Files matches project. All ok! INFO: [Hog:Msg-0] All done. Command: synth_design -top top_FTM_DSS -part xc7vx415tffg1158-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx415t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11409 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 2223.035 ; gain = 200.715 ; free physical = 3199 ; free virtual = 21315 --------------------------------------------------------------------------------- WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_tob_init.vhd:40] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:38] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_frame_init.vhd:40] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_ctrl_init.vhd:35] INFO: [Synth 8-638] synthesizing module 'top_FTM_DSS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:111] Parameter FLAVOUR bound to: 0 - type: integer Parameter GLOBAL_DATE bound to: 32'b00100001000010010010000000100001 Parameter GLOBAL_TIME bound to: 32'b00000000000101010001001001000101 Parameter GLOBAL_SHA bound to: 32'b00001000011101011111010011111000 Parameter GLOBAL_VER bound to: 32'b00000010000000010000000000000110 Parameter TOP_SHA bound to: 32'b00001010101101110000001101001111 Parameter TOP_VER bound to: 32'b00000000000000000000000000010101 Parameter CON_SHA bound to: 32'b00001000011101011111010011111000 Parameter CON_VER bound to: 32'b00000010000000010000000000000110 Parameter XML_SHA bound to: 32'b00001110101101001111100000000000 Parameter XML_VER bound to: 32'b00000010000000010000000000000101 Parameter HOG_SHA bound to: 32'b00000110110000000010011110010111 Parameter HOG_VER bound to: 32'b00000011000000000000000000000000 Parameter FTM_SHA bound to: 32'b00001000011101011111010011111000 Parameter FTM_VER bound to: 32'b00000010000000010000000000000110 INFO: [Synth 8-5534] Detected attribute (* mark_debug = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:147] INFO: [Synth 8-638] synthesizing module 'DSS_3quads_11g2_mgts' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer Parameter Q2_REFCLK1_Q1 bound to: 1 - type: bool INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:101] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:102] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:107] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:108] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:111] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:112] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:115] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:116] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:117] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:125] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:126] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:129] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:130] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:133] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:134] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:135] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:143] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:144] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:147] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:148] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:151] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:152] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:153] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:161] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:162] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:165] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:166] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:169] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:170] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:171] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:179] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:180] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:183] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:184] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:187] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:188] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:189] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:197] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:198] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:201] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:202] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:205] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:206] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:207] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:215] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:216] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:219] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:220] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:223] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:224] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:225] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:233] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:234] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:237] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:238] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:241] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:242] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:243] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:251] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:252] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:255] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:256] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:259] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:260] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:261] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:269] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:270] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:273] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:274] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:277] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:278] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:279] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:287] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:288] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:291] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:292] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:295] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:296] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:297] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:305] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:306] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:309] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:310] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:313] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:314] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:315] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:1029] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter Q2_REFCLK1_Q1 bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT_USRCLK_SOURCE' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:72' bound to instance 'gt_usrclk_source' of component 'DSS_3Quads_11g2_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3704] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:173] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'ibufds_instq0_clk1' to cell 'IBUFDS_GTE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:294] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'ibufds_instq1_clk1' to cell 'IBUFDS_GTE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:304] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-113] binding component instance 'ibufds_instq2_clk1' to cell 'IBUFDS_GTE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:314] INFO: [Synth 8-113] binding component instance 'txoutclk_bufg0_i' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:328] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg1_i' to cell 'BUFH' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:336] INFO: [Synth 8-113] binding component instance 'txoutclk_bufg2_i' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:344] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg3_i' to cell 'BUFH' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:352] INFO: [Synth 8-113] binding component instance 'txoutclk_bufg4_i' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:360] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg5_i' to cell 'BUFH' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:368] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_GT_USRCLK_SOURCE' (1#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:173] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:70' bound to instance 'common0_i' of component 'DSS_3Quads_11g2_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3806] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:92] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000001011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-113] binding component instance 'gthe2_common_i' to cell 'GTHE2_COMMON' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:164] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_common' (2#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:92] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:70' bound to instance 'common1_i' of component 'DSS_3Quads_11g2_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3826] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:70' bound to instance 'common2_i' of component 'DSS_3Quads_11g2_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3855] Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common_reset' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common_reset.vhd:78' bound to instance 'common_reset_i' of component 'DSS_3Quads_11g2_common_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3876] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_common_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common_reset.vhd:91] Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common_reset.vhd:133] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_common_reset' (3#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common_reset.vhd:91] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/synth_1/.Xil/Vivado-11348-hog-vm0.cern.ch/realtime/DSS_3Quads_11g2_stub.vhdl:5' bound to instance 'DSS_3Quads_11g2_init_i' of component 'DSS_3Quads_11g2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3890] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/synth_1/.Xil/Vivado-11348-hog-vm0.cern.ch/realtime/DSS_3Quads_11g2_stub.vhdl:630] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_support' (4#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:1029] INFO: [Synth 8-113] binding component instance 'DRP_CLK_BUFG' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:3298] WARNING: [Synth 8-5858] RAM mgt_link_errors_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'DSS_3quads_11g2_mgts' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] INFO: [Synth 8-638] synthesizing module 'DSS_3quads_11g2_mgts__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer Parameter Q2_REFCLK1_Q1 bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_support__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:1029] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter Q2_REFCLK1_Q1 bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT_USRCLK_SOURCE' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd:72' bound to instance 'gt_usrclk_source' of component 'DSS_3Quads_11g2_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3704] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:70' bound to instance 'common0_i' of component 'DSS_3Quads_11g2_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3806] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:70' bound to instance 'common1_i' of component 'DSS_3Quads_11g2_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3826] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common.vhd:70' bound to instance 'common2_i' of component 'DSS_3Quads_11g2_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3855] Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_common_reset' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_common_reset.vhd:78' bound to instance 'common_reset_i' of component 'DSS_3Quads_11g2_common_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3876] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/synth_1/.Xil/Vivado-11348-hog-vm0.cern.ch/realtime/DSS_3Quads_11g2_stub.vhdl:5' bound to instance 'DSS_3Quads_11g2_init_i' of component 'DSS_3Quads_11g2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:3890] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_support__parameterized0' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_support.vhd:1029] INFO: [Synth 8-113] binding component instance 'DRP_CLK_BUFG' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:3298] WARNING: [Synth 8-5858] RAM mgt_link_errors_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'DSS_3quads_11g2_mgts__parameterized0' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] INFO: [Synth 8-638] synthesizing module 'DSS_3quads_11g2_mgts__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer Parameter Q2_REFCLK1_Q1 bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'DRP_CLK_BUFG' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:3298] WARNING: [Synth 8-5858] RAM mgt_link_errors_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'DSS_3quads_11g2_mgts__parameterized1' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] INFO: [Synth 8-638] synthesizing module 'DSS_3quads_11g2_mgts__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer Parameter Q2_REFCLK1_Q1 bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'DRP_CLK_BUFG' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:3298] WARNING: [Synth 8-5858] RAM mgt_link_errors_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'DSS_3quads_11g2_mgts__parameterized2' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd:53] INFO: [Synth 8-638] synthesizing module 'comma_monitor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/comma_monitor.vhd:23] INFO: [Synth 8-256] done synthesizing module 'comma_monitor' (6#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/comma_monitor.vhd:23] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'ibuf_40M' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:303] INFO: [Synth 8-113] binding component instance 'bufg_ttc' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:309] INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:29] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'ibufgds0' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:40] INFO: [Synth 8-113] binding component instance 'bufg200' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:47] INFO: [Synth 8-113] binding component instance 'bufg125' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:54] INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:61] INFO: [Synth 8-113] binding component instance 'bufgfb' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:68] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 1.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 292.500000 - type: double Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 73.125000 - type: double Parameter CLKOUT3_DIVIDE bound to: 5 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm' to cell 'MMCME2_BASE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:75] INFO: [Synth 8-638] synthesizing module 'clock_div' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clock_div.vhd:27] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clock_div.vhd:33] INFO: [Synth 8-256] done synthesizing module 'clock_div' (7#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clock_div.vhd:27] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (8#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/clocks_7s_ftm.vhd:29] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2m' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:346] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 's2mp' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:354] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:363] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s_err' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:371] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'm2s_pause' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:378] INFO: [Synth 8-638] synthesizing module 'UDP_slave_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:35] WARNING: [Synth 8-6014] Unused sequential element next_valid_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:66] WARNING: [Synth 8-6014] Unused sequential element next_data_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:67] WARNING: [Synth 8-6014] Unused sequential element last_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:68] WARNING: [Synth 8-6014] Unused sequential element error_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:69] WARNING: [Synth 8-6014] Unused sequential element next_last_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:120] WARNING: [Synth 8-6014] Unused sequential element next_error_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:121] WARNING: [Synth 8-6014] Unused sequential element ready_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:122] WARNING: [Synth 8-6014] Unused sequential element valid_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:123] WARNING: [Synth 8-6014] Unused sequential element data_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:125] INFO: [Synth 8-4471] merging register 'last_ready_reg' into 'mac_tx_ready_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:127] WARNING: [Synth 8-6014] Unused sequential element last_ready_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:127] INFO: [Synth 8-256] done synthesizing module 'UDP_slave_if' (9#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_slave_if.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:70] Parameter MAC_CFG bound to: 1'b0 Parameter IP_CFG bound to: 1'b0 Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b1 Parameter N_OOB bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:64] WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:65] INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:66] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:30] INFO: [Synth 8-4471] merging register 'MAC_IP_addr_rx_reg[79:0]' into 'MAC_IP_addr_rx_int_reg[79:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:76] WARNING: [Synth 8-6014] Unused sequential element MAC_IP_addr_rx_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:76] INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_block' (10#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:30] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:33] WARNING: [Synth 8-6014] Unused sequential element state_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:60] WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:63] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:115] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:116] WARNING: [Synth 8-6014] Unused sequential element next_low_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:409] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:486] INFO: [Synth 8-4471] merging register 'send_pending_reg' into 'send_pending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:46] INFO: [Synth 8-4471] merging register 'payload_we_sig_reg' into 'payload_we_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:43] INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:268] INFO: [Synth 8-4471] merging register 'buf_to_load_reg[15:0]' into 'buf_to_load_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:273] INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:278] INFO: [Synth 8-4471] merging register 'do_sum_payload_reg' into 'do_sum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:362] INFO: [Synth 8-4471] merging register 'clr_sum_payload_reg' into 'clr_sum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:367] INFO: [Synth 8-4471] merging register 'int_data_payload_reg[7:0]' into 'int_data_int_reg[7:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:372] INFO: [Synth 8-4471] merging register 'int_valid_payload_reg' into 'int_valid_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:377] INFO: [Synth 8-4471] merging register 'cksum_reg' into 'cksum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:382] INFO: [Synth 8-4471] merging register 'next_addr_reg[12:0]' into 'next_addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:408] INFO: [Synth 8-4471] merging register 'address_reg[12:0]' into 'addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:126] INFO: [Synth 8-4471] merging register 'low_addr_reg' into 'low_addr_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:123] INFO: [Synth 8-4471] merging register 'byteswap_reg' into 'byteswap_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:473] INFO: [Synth 8-4471] merging register 'ipbus_in_hdr_reg[31:0]' into 'ipbus_hdr_int_reg[31:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:515] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:46] WARNING: [Synth 8-6014] Unused sequential element payload_we_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:43] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:268] WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:273] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:278] WARNING: [Synth 8-6014] Unused sequential element do_sum_payload_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:362] WARNING: [Synth 8-6014] Unused sequential element clr_sum_payload_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:367] WARNING: [Synth 8-6014] Unused sequential element int_data_payload_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:372] WARNING: [Synth 8-6014] Unused sequential element int_valid_payload_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:377] WARNING: [Synth 8-6014] Unused sequential element cksum_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:382] WARNING: [Synth 8-6014] Unused sequential element next_addr_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:408] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:126] WARNING: [Synth 8-6014] Unused sequential element low_addr_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:123] WARNING: [Synth 8-6014] Unused sequential element byteswap_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:473] WARNING: [Synth 8-6014] Unused sequential element ipbus_in_hdr_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:515] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (11#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:33] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:23] INFO: [Synth 8-4471] merging register 'resend_pkt_id_reg[15:0]' into 'resend_pkt_id_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:65] WARNING: [Synth 8-6014] Unused sequential element resend_pkt_id_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:65] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (12#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:23] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:28] WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:43] WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:97] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:98] WARNING: [Synth 8-6014] Unused sequential element request_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:183] WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:247] INFO: [Synth 8-4471] merging register 'address_reg[6:0]' into 'addr_int_reg[6:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:36] INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:219] INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:224] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:36] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:219] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:224] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (13#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_build_status.vhd:28] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:49] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer WARNING: [Synth 8-6014] Unused sequential element bufsize_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:101] WARNING: [Synth 8-6014] Unused sequential element nbuf_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:102] WARNING: [Synth 8-6014] Unused sequential element new_event_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:149] WARNING: [Synth 8-6014] Unused sequential element async_ready_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:150] WARNING: [Synth 8-6014] Unused sequential element rarp_arp_ping_ipbus_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:156] WARNING: [Synth 8-6014] Unused sequential element payload_status_resend_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:158] WARNING: [Synth 8-6014] Unused sequential element got_event_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:242] WARNING: [Synth 8-6014] Unused sequential element event_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:243] INFO: [Synth 8-4471] merging register 'next_pkt_id_reg[15:0]' into 'next_pkt_id_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:123] WARNING: [Synth 8-6014] Unused sequential element next_pkt_id_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:123] INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (14#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:25] INFO: [Synth 8-4471] merging register 'carry_bit_reg' into 'carry_bit_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:88] INFO: [Synth 8-4471] merging register 'hi_byte_reg[8:0]' into 'hi_byte_int_reg[8:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:32] WARNING: [Synth 8-6014] Unused sequential element carry_bit_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:88] WARNING: [Synth 8-6014] Unused sequential element hi_byte_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:32] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (15#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:25] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:20] INFO: [Synth 8-4471] merging register 'rx_reset_sig_reg' into 'reset_latch_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:26] WARNING: [Synth 8-6014] Unused sequential element rx_reset_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:26] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (16#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:20] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:37] Parameter SECONDARYPORT bound to: 1'b1 INFO: [Synth 8-4471] merging register 'pkt_drop_rarp_sig_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:47] INFO: [Synth 8-4471] merging register 'pkt_drop_ip_sig_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:230] INFO: [Synth 8-4471] merging register 'pkt_drop_ipbus_sig_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:48] INFO: [Synth 8-4471] merging register 'ipbus_status_mask_reg' into 'last_mask_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:303] INFO: [Synth 8-4471] merging register 'pkt_runt_reg' into 'header_sel_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:313] INFO: [Synth 8-4471] merging register 'pkt_drop_reliable_sig_reg' into 'pkt_drop_reliable_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:353] INFO: [Synth 8-4471] merging register 'pkt_reliable_drop_sig_reg' into 'pkt_drop_reliable_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:399] INFO: [Synth 8-4471] merging register 'reliable_packet_reg' into 'IsReliable_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:422] INFO: [Synth 8-4471] merging register 'pkt_drop_status_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:453] INFO: [Synth 8-4471] merging register 'pkt_drop_resend_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:488] INFO: [Synth 8-4471] merging register 'pkt_broadcast_reg' into 'broadcast_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:510] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_rarp_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:47] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ip_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:230] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ipbus_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:48] WARNING: [Synth 8-6014] Unused sequential element ipbus_status_mask_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:303] WARNING: [Synth 8-6014] Unused sequential element pkt_runt_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:313] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_reliable_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:353] WARNING: [Synth 8-6014] Unused sequential element pkt_reliable_drop_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:399] WARNING: [Synth 8-6014] Unused sequential element reliable_packet_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:422] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_status_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:453] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_resend_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:488] WARNING: [Synth 8-6014] Unused sequential element pkt_broadcast_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:510] INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (17#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:37] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:56] WARNING: [Synth 8-6014] Unused sequential element rxram_dropped_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:74] WARNING: [Synth 8-6014] Unused sequential element rxram_end_addr_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:97] WARNING: [Synth 8-6014] Unused sequential element rxram_send_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:98] WARNING: [Synth 8-6014] Unused sequential element dia_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:154] WARNING: [Synth 8-6014] Unused sequential element addra_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:155] WARNING: [Synth 8-6014] Unused sequential element wea_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:156] INFO: [Synth 8-4471] merging register 'ram_ready_reg' into 'ram_ready_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:62] WARNING: [Synth 8-6014] Unused sequential element ram_ready_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:62] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (18#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:22] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (19#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:22] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32] Parameter BUFWIDTH bound to: 1 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:154] INFO: [Synth 8-4471] merging register 'free_reg[1:0]' into 'free_i_reg[1:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75] INFO: [Synth 8-4471] merging register 'clean_reg[1:0]' into 'clean_i_reg[1:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44] INFO: [Synth 8-4471] merging register 'send_pending_reg[1:0]' into 'send_pending_i_reg[1:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121] INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43] INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158] INFO: [Synth 8-4471] merging register 'write_sig_reg[0:0]' into 'write_i_reg[0:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41] INFO: [Synth 8-4471] merging register 'send_sig_reg[0:0]' into 'send_i_reg[0:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42] WARNING: [Synth 8-6014] Unused sequential element free_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75] WARNING: [Synth 8-6014] Unused sequential element clean_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121] WARNING: [Synth 8-6014] Unused sequential element busy_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43] WARNING: [Synth 8-6014] Unused sequential element sending_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158] WARNING: [Synth 8-6014] Unused sequential element write_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41] WARNING: [Synth 8-6014] Unused sequential element send_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42] INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (20#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:30] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (21#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:30] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:22] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:36] WARNING: [Synth 8-6014] Unused sequential element byte4_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:56] WARNING: [Synth 8-6014] Unused sequential element byte3_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:57] WARNING: [Synth 8-6014] Unused sequential element byte2_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:58] WARNING: [Synth 8-6014] Unused sequential element byte1_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:59] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (22#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:22] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32] Parameter BUFWIDTH bound to: 4 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:154] INFO: [Synth 8-4471] merging register 'free_reg[15:0]' into 'free_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75] INFO: [Synth 8-4471] merging register 'clean_reg[15:0]' into 'clean_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44] INFO: [Synth 8-4471] merging register 'send_pending_reg[15:0]' into 'send_pending_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121] INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43] INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158] INFO: [Synth 8-4471] merging register 'write_sig_reg[3:0]' into 'write_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41] INFO: [Synth 8-4471] merging register 'send_sig_reg[3:0]' into 'send_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42] WARNING: [Synth 8-6014] Unused sequential element free_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75] WARNING: [Synth 8-6014] Unused sequential element clean_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121] WARNING: [Synth 8-6014] Unused sequential element busy_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43] WARNING: [Synth 8-6014] Unused sequential element sending_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158] WARNING: [Synth 8-6014] Unused sequential element write_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41] WARNING: [Synth 8-6014] Unused sequential element send_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42] INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (22#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:23] WARNING: [Synth 8-6014] Unused sequential element rxpayload_dropped_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:35] WARNING: [Synth 8-6014] Unused sequential element pkt_rcvd_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:36] INFO: [Synth 8-4471] merging register 'ram_ok_reg' into 'ram_ok_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:29] WARNING: [Synth 8-6014] Unused sequential element ram_ok_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:29] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (23#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:23] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:22] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:57] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (24#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:22] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32] Parameter BUFWIDTH bound to: 4 - type: integer WARNING: [Synth 8-6014] Unused sequential element req_send_i_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:154] INFO: [Synth 8-4471] merging register 'free_reg[15:0]' into 'free_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75] INFO: [Synth 8-4471] merging register 'clean_reg[15:0]' into 'clean_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44] INFO: [Synth 8-4471] merging register 'send_pending_reg[15:0]' into 'send_pending_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121] INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43] INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158] INFO: [Synth 8-4471] merging register 'write_sig_reg[3:0]' into 'write_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41] INFO: [Synth 8-4471] merging register 'send_sig_reg[3:0]' into 'send_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42] WARNING: [Synth 8-6014] Unused sequential element free_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75] WARNING: [Synth 8-6014] Unused sequential element clean_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121] WARNING: [Synth 8-6014] Unused sequential element busy_sig_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43] WARNING: [Synth 8-6014] Unused sequential element sending_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158] INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (24#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:52] Parameter INTERNAL_ONLY bound to: 1'b0 INFO: [Synth 8-4471] merging register 'rxram_busy_sig_reg' into 'rxram_busy_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:72] INFO: [Synth 8-4471] merging register 'rxram_end_addr_sig_reg[12:0]' into 'rxram_end_addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:114] INFO: [Synth 8-4471] merging register 'addr_sig_reg[12:0]' into 'addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:74] INFO: [Synth 8-4471] merging register 'byteswapping_reg' into 'byteswapping_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:151] INFO: [Synth 8-4471] merging register 'mac_tx_data_sig_reg[7:0]' into 'mac_tx_data_int_reg[7:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:75] INFO: [Synth 8-4471] merging register 'next_state_reg[2:0]' into 'state_reg[2:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:219] INFO: [Synth 8-4471] merging register 'rxram_active_reg' into 'rxram_active_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:104] INFO: [Synth 8-4471] merging register 'udpram_active_reg' into 'udpram_active_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:174] INFO: [Synth 8-4471] merging register 'counting_reg' into 'counting_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:130] INFO: [Synth 8-4471] merging register 'prefetch_reg' into 'prefetch_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:184] INFO: [Synth 8-4471] merging register 'mac_tx_last_sig_reg' into 'mac_tx_last_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:76] INFO: [Synth 8-4471] merging register 'mac_tx_valid_sig_reg' into 'mac_tx_valid_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:77] INFO: [Synth 8-4471] merging register 'set_addr_reg' into 'set_addr_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:127] INFO: [Synth 8-4471] merging register 'addr_to_set_reg[12:0]' into 'addr_to_set_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:128] INFO: [Synth 8-4471] merging register 'default_mode.udpram_busy_sig_reg' into 'default_mode.udpram_busy_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:73] INFO: [Synth 8-4471] merging register 'default_mode.udp_short_sig_reg' into 'default_mode.short_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:79] INFO: [Synth 8-4471] merging register 'default_mode.send_special_reg' into 'default_mode.send_special_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:170] INFO: [Synth 8-4471] merging register 'default_mode.special_reg[7:0]' into 'default_mode.special_int_reg[7:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:171] INFO: [Synth 8-4471] merging register 'default_mode.last_udpram_active_reg' into 'default_mode.last_udpram_active_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:472] INFO: [Synth 8-4471] merging register 'default_mode.udp_counting_reg' into 'default_mode.counting_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:477] INFO: [Synth 8-4471] merging register 'default_mode.udp_counter_reg[4:0]' into 'default_mode.counter_reg[4:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:482] INFO: [Synth 8-4471] merging register 'default_mode.cksum_reg' into 'default_mode.cksum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:551] INFO: [Synth 8-4471] merging register 'default_mode.clr_sum_reg' into 'default_mode.clr_sum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:556] INFO: [Synth 8-4471] merging register 'default_mode.do_sum_reg' into 'default_mode.do_sum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:561] INFO: [Synth 8-4471] merging register 'default_mode.int_valid_reg' into 'default_mode.int_valid_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:566] INFO: [Synth 8-4471] merging register 'default_mode.udpram_end_addr_sig_reg[12:0]' into 'default_mode.udpram_end_addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:248] INFO: [Synth 8-4471] merging register 'default_mode.int_data_reg[7:0]' into 'default_mode.int_data_int_reg[7:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:645] INFO: [Synth 8-4471] merging register 'default_mode.ip_len_reg[15:0]' into 'default_mode.ip_len_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:404] INFO: [Synth 8-4471] merging register 'default_mode.ip_cksum_reg[15:0]' into 'default_mode.ip_cksum_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:409] INFO: [Synth 8-4471] merging register 'default_mode.udp_len_reg[15:0]' into 'default_mode.udp_len_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:434] INFO: [Synth 8-4471] merging register 'default_mode.ipbus_out_hdr_reg[31:0]' into 'default_mode.ipbus_hdr_int_reg[31:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:707] INFO: [Synth 8-4471] merging register 'default_mode.byteswap_sig_reg' into 'default_mode.byteswap_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:141] INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (25#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:52] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:35] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (26#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:35] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:43] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:48] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:49] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (27#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:43] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (28#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:66] INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor.vhd:34] INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor_if.vhd:31] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (29#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor_if.vhd:31] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor_sm.vhd:39] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (30#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor_sm.vhd:39] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:27] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (31#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:27] INFO: [Synth 8-256] done synthesizing module 'transactor' (32#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/transactor.vhd:34] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (33#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:70] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'ttc_info_spin' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:440] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'ttc_info_sync' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:449] INFO: [Synth 8-638] synthesizing module 'slaves' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/slaves_dss.vhd:58] Parameter N_TXS bound to: 48 - type: integer Parameter N_RXS bound to: 12 - type: integer Parameter XML_VERSION bound to: 33619973 - type: integer Parameter XML_HASH bound to: 246740992 - type: integer Parameter GLOBAL_FWVERSION bound to: 33619974 - type: integer Parameter GLOBAL_FWHASH bound to: 141948152 - type: integer Parameter GLOBAL_FWDATE bound to: 554246177 - type: integer Parameter GLOBAL_FWTIME bound to: 1380933 - type: integer Parameter FTM_FWHASH bound to: 141948152 - type: integer Parameter FTM_FWVERSION bound to: 33619974 - type: integer Parameter IPBUS_LIB_FWHASH bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:29] Parameter NSLV bound to: 10 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (34#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:29] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/slaves_dss.vhd:128] INFO: [Synth 8-638] synthesizing module 'ipbus_ftm_fpga_id_version' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_ftm_fpga_id_version.vhd:34] Parameter XML_VERSION bound to: 33619973 - type: integer Parameter XML_HASH bound to: 246740992 - type: integer Parameter GLOBAL_FWVERSION bound to: 33619974 - type: integer Parameter GLOBAL_FWHASH bound to: 141948152 - type: integer Parameter GLOBAL_FWDATE bound to: 554246177 - type: integer Parameter GLOBAL_FWTIME bound to: 1380933 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ftm_fpga_id_version' (35#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_ftm_fpga_id_version.vhd:34] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:36] Parameter N_CTRL bound to: 2 - type: integer Parameter N_STAT bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (36#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:36] INFO: [Synth 8-638] synthesizing module 'ipbus_spi32' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/ipbus_spi32.vhd:39] Parameter BYTE_SPI bound to: 1 - type: bool Parameter ADDR_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 7 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch' (37#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:36] Parameter N_CTRL bound to: 4 - type: integer Parameter N_STAT bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (37#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:36] INFO: [Synth 8-638] synthesizing module 'ipbus_watchdog' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_watchdog.vhd:33] Parameter TIMER_WIDTH bound to: 20 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_watchdog' (38#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_watchdog.vhd:33] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:35] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram' (39#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:35] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized0' (39#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:35] INFO: [Synth 8-638] synthesizing module 'command_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/command_sync.vhd:20] INFO: [Synth 8-256] done synthesizing module 'command_sync' (40#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/command_sync.vhd:20] INFO: [Synth 8-638] synthesizing module 'spi32_8_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:39] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter BYTE_SPI bound to: 1 - type: bool INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:57] INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:59] INFO: [Common 17-14] Message 'Synth 8-5534' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'spi32_8_control' (41#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:39] INFO: [Synth 8-638] synthesizing module 'clock_pulse' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/clock_pulse.vhd:18] INFO: [Synth 8-256] done synthesizing module 'clock_pulse' (42#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/clock_pulse.vhd:18] INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32' (43#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/ipbus_spi32.vhd:39] INFO: [Synth 8-638] synthesizing module 'ipbus_self_configure' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/ipbus_self_configure.vhd:21] INFO: [Synth 8-638] synthesizing module 'reconfigure_fsm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:16] Parameter DEVICE_ID bound to: 32'b00000011011001010001000010010011 Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-113] binding component instance 'ICAPE2_inst' to cell 'ICAPE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:64] INFO: [Synth 8-256] done synthesizing module 'reconfigure_fsm' (44#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:16] INFO: [Synth 8-256] done synthesizing module 'ipbus_self_configure' (45#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/ipbus_self_configure.vhd:21] INFO: [Synth 8-638] synthesizing module 'ipbus_xadc_array' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/ipbus_xadc_array.vhd:24] INFO: [Synth 8-638] synthesizing module 'xadc_ftm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/xadc_ftm.vhd:45] Parameter INIT_40 bound to: 16'b1001000000000000 Parameter INIT_41 bound to: 16'b0010111011110000 Parameter INIT_42 bound to: 16'b0000001100000000 Parameter INIT_43 bound to: 16'b0010111011110000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000001 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0100011100000001 Parameter INIT_49 bound to: 16'b0000000000001111 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101100110011001 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1101110111011101 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101000100010001 Parameter INIT_56 bound to: 16'b1001000111101011 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/xadc_ftm.vhd:98] INFO: [Synth 8-256] done synthesizing module 'xadc_ftm' (46#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/xadc_ftm.vhd:45] INFO: [Synth 8-256] done synthesizing module 'ipbus_xadc_array' (47#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/ipbus_xadc_array.vhd:24] INFO: [Synth 8-638] synthesizing module 'ipbus_dss_xcvr_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_dss_xcvr_control.vhd:30] Parameter N_3QUADS bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:29] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (47#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:29] INFO: [Synth 8-638] synthesizing module 'ipbus_xcvr_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_xcvr_control.vhd:27] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:36] Parameter N_CTRL bound to: 2 - type: integer Parameter N_STAT bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (47#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:36] INFO: [Synth 8-256] done synthesizing module 'ipbus_xcvr_control' (48#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_xcvr_control.vhd:27] INFO: [Synth 8-256] done synthesizing module 'ipbus_dss_xcvr_control' (49#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_dss_xcvr_control.vhd:30] INFO: [Synth 8-638] synthesizing module 'ipbus_dss_buffer_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dss_buffer_control.vhd:40] Parameter ADDR_WIDTH bound to: 13 - type: integer Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'playout_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dss_buffer_control.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'extra_sink_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dss_buffer_control.vhd:145] INFO: [Synth 8-3491] module 'ila_bcr' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/synth_1/.Xil/Vivado-11348-hog-vm0.cern.ch/realtime/ila_bcr_stub.vhdl:5' bound to instance 'bcr_delays' of component 'ila_bcr' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dss_buffer_control.vhd:160] INFO: [Synth 8-638] synthesizing module 'ila_bcr' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/synth_1/.Xil/Vivado-11348-hog-vm0.cern.ch/realtime/ila_bcr_stub.vhdl:13] INFO: [Synth 8-256] done synthesizing module 'ipbus_dss_buffer_control' (50#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dss_buffer_control.vhd:40] INFO: [Synth 8-638] synthesizing module 'ipbus_mgt_source' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_source.vhd:35] Parameter NSLV bound to: 48 - type: integer Parameter DPRAM_ADDR_WIDTH bound to: 14 - type: integer Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] Parameter NSLV bound to: 48 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 16 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized0' (50#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_data_source' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_source.vhd:41] Parameter DPRAM_ADDR_WIDTH bound to: 14 - type: integer Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'framing_sync_logic' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:22] Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'framing_sync_logic' (51#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:22] INFO: [Synth 8-638] synthesizing module 'tx_ram_pointer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/tx_ram_pointer.vhd:21] Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer INFO: [Synth 8-256] done synthesizing module 'tx_ram_pointer' (52#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/tx_ram_pointer.vhd:21] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_merge' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_fabric_merge.vhd:29] Parameter STROBE_GAP bound to: 0 - type: bool Parameter INTERLEAVE bound to: 0 - type: bool Parameter DPRAM_ADDR_WIDTH bound to: 14 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_merge' (53#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_fabric_merge.vhd:29] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_frame_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_frame_init.vhd:34] Parameter ADDR_WIDTH bound to: 13 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_frame_init' (54#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_frame_init.vhd:34] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_ctrl_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_ctrl_init.vhd:30] Parameter ADDR_WIDTH bound to: 13 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_ctrl_init' (55#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_ctrl_init.vhd:30] INFO: [Synth 8-638] synthesizing module 'dummy_frame_generator' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/dummy_frame_generator.vhd:30] Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d32.vhd:20] Parameter REVERSE_BIT_ORDER bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (56#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d32.vhd:20] INFO: [Synth 8-638] synthesizing module 'osum_crc9d23' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d23.vhd:20] Parameter REVERSE_BIT_ORDER bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'osum_crc9d23' (57#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d23.vhd:20] INFO: [Synth 8-256] done synthesizing module 'dummy_frame_generator' (58#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/dummy_frame_generator.vhd:30] INFO: [Synth 8-256] done synthesizing module 'ipbus_data_source' (59#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_source.vhd:41] INFO: [Synth 8-256] done synthesizing module 'ipbus_mgt_source' (60#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_source.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_mgt_sink_ref' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_sink_ref.vhd:35] Parameter NSLV bound to: 12 - type: integer Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] Parameter NSLV bound to: 12 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 16 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized1' (60#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_mgt_ref' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_ref.vhd:34] Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] Parameter NSLV bound to: 3 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 13 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized2' (60#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_data_sink' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_sink.vhd:34] Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'rx_framing_sync_logic' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_framing_sync_logic.vhd:30] Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'rx_framing_sync_logic' (61#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_framing_sync_logic.vhd:30] INFO: [Synth 8-638] synthesizing module 'rx_ram_pointer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_ram_pointer.vhd:27] Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer INFO: [Synth 8-256] done synthesizing module 'rx_ram_pointer' (62#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_ram_pointer.vhd:27] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:35] Parameter ADDR_WIDTH bound to: 13 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized1' (62#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:35] INFO: [Synth 8-256] done synthesizing module 'ipbus_data_sink' (63#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_sink.vhd:34] INFO: [Synth 8-638] synthesizing module 'ipbus_data_check' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_check.vhd:33] Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer Parameter FRAME_SIZE bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_tob_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_tob_init.vhd:34] Parameter ADDR_WIDTH bound to: 13 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_tob_init' (64#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_tob_init.vhd:34] INFO: [Synth 8-256] done synthesizing module 'ipbus_data_check' (65#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_check.vhd:33] INFO: [Synth 8-638] synthesizing module 'ipbus_counter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_counter.vhd:28] INFO: [Synth 8-256] done synthesizing module 'ipbus_counter' (66#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_counter.vhd:28] INFO: [Synth 8-256] done synthesizing module 'ipbus_mgt_ref' (67#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_ref.vhd:34] INFO: [Synth 8-256] done synthesizing module 'ipbus_mgt_sink_ref' (68#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_sink_ref.vhd:35] INFO: [Synth 8-638] synthesizing module 'ipbus_mgt_rx_monitor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_mgt_rx_monitor.vhd:31] Parameter N_CHANNELS bound to: 12 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] Parameter NSLV bound to: 12 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 2 - type: integer WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized3' (68#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35] INFO: [Synth 8-638] synthesizing module 'mgt_data_check' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/mgt_data_check.vhd:19] INFO: [Synth 8-638] synthesizing module 'osum_crc9d32__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d32.vhd:20] Parameter REVERSE_BIT_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32__parameterized0' (68#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d32.vhd:20] INFO: [Synth 8-256] done synthesizing module 'mgt_data_check' (69#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/mgt_data_check.vhd:19] INFO: [Synth 8-638] synthesizing module 'ipbus_counter_array' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_counter_array.vhd:28] Parameter N_BITS bound to: 16 - type: integer Parameter N_COUNTERS bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_counter_array' (70#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_counter_array.vhd:28] INFO: [Synth 8-256] done synthesizing module 'ipbus_mgt_rx_monitor' (71#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_mgt_rx_monitor.vhd:31] INFO: [Synth 8-256] done synthesizing module 'slaves' (72#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/slaves_dss.vhd:58] INFO: [Synth 8-638] synthesizing module 'startup' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/startup.vhd:15] Parameter PROG_USR bound to: FALSE - type: string Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double INFO: [Synth 8-113] binding component instance 'STARTUPE2_inst' to cell 'STARTUPE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/startup.vhd:27] INFO: [Synth 8-256] done synthesizing module 'startup' (73#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/startup.vhd:15] WARNING: [Synth 8-5858] RAM mgt_source_data_regd_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers WARNING: [Synth 8-5858] RAM mgt_sink_data_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'mgts_114_116'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:242] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'detect_rxcomma0'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:293] INFO: [Synth 8-256] done synthesizing module 'top_FTM_DSS' (74#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/top_FTM_DSS.vhd:111] WARNING: [Synth 8-3917] design top_FTM_DSS has port test_pin3 driven by constant 0 WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][31] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][30] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][29] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][28] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][27] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][26] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][25] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][24] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][23] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][22] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][21] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][20] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][19] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][18] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][17] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][16] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][15] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][14] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][13] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][12] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][11] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][10] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][9] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][8] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][7] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][6] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][5] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][4] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][3] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_addr][2] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][31] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][30] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][29] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][28] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][27] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][26] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][25] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][24] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][23] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][22] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][21] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][20] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][19] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][18] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][17] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][16] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][15] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][14] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][13] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][12] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][11] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][10] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][9] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][8] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][7] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][6] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][5] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][4] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][3] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][2] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][1] WARNING: [Synth 8-3331] design ipbus_counter_array has unconnected port ipbus_in[ipb_wdata][0] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port reset WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][31] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][30] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][29] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][28] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][27] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][26] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][25] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][24] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][23] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][22] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][21] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][20] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][19] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][18] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][17] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][16] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][15] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][14] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][13] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][12] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][11] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][10] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][9] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][8] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][7] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][6] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][5] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][4] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][3] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][2] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][1] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_addr][0] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_wdata][31] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_wdata][30] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_wdata][29] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_wdata][28] WARNING: [Synth 8-3331] design ipbus_counter has unconnected port ipbus_in[ipb_wdata][27] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:22 . Memory (MB): peak = 2383.758 ; gain = 361.438 ; free physical = 3137 ; free virtual = 21256 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2398.598 ; gain = 376.277 ; free physical = 3160 ; free virtual = 21279 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 2398.598 ; gain = 376.277 ; free physical = 3160 ; free virtual = 21279 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2404.535 ; gain = 0.000 ; free physical = 3098 ; free virtual = 21216 INFO: [Netlist 29-17] Analyzing 29 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/DSS_3Quads_11g2_in_context.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_bcr/ila_bcr_in_context.xdc] for cell 'slaves/buffer_control/bcr_delays' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_bcr/ila_bcr_in_context.xdc] for cell 'slaves/buffer_control/bcr_delays' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_FTM_DSS_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_FTM_DSS_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_FTM_DSS_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_FTM_DSS_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_FTM_DSS_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_FTM_DSS_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc:3] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_FTM_DSS_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_FTM_DSS_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_FTM_DSS_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_FTM_DSS_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2562.004 ; gain = 0.000 ; free physical = 2932 ; free virtual = 21051 INFO: [Project 1-111] Unisim Transformation Summary: A total of 14 instances were transformed. IBUFGDS => IBUFDS: 2 instances MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS: 10 instances SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2562.004 ; gain = 0.000 ; free physical = 2932 ; free virtual = 21050 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:40 ; elapsed = 00:00:56 . Memory (MB): peak = 2562.004 ; gain = 539.684 ; free physical = 3128 ; free virtual = 21247 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx415tffg1158-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:40 ; elapsed = 00:00:56 . Memory (MB): peak = 2562.004 ; gain = 539.684 ; free physical = 3128 ; free virtual = 21247 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for slaves/buffer_control/bcr_delays. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:57 . Memory (MB): peak = 2562.004 ; gain = 539.684 ; free physical = 3127 ; free virtual = 21246 --------------------------------------------------------------------------------- INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "send_buf_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "do_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "clr_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "int_valid_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "int_data_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "send_buf_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "do_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "clr_sum_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "int_valid_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5587] ROM size for "int_data_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ipbus_hdr_int" won't be mapped to RAM because it is too sparse WARNING: [Synth 8-3936] Found unconnected internal register 'pkt_rdy_buf_reg' and it is trimmed from '3' to '2' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:128] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'command_sync' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control' INFO: [Synth 8-802] inferred FSM for state register 'NEXT_STATE_reg' in module 'reconfigure_fsm' INFO: [Synth 8-5544] ROM "NEXT_STATE" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'xadc_ftm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' INFO: [Synth 8-3971] The signal "ipbus_dpram:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized0:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0001 | 00 request | 0010 | 01 done | 0100 | 10 iSTATE | 1000 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'one-hot' in module 'command_sync' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start_frame | 001 | 001 read_mem | 010 | 010 shift_io | 011 | 011 write_mem | 100 | 100 end_frame | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 data_00 | 0001 | 0001 data_01 | 0010 | 0010 data_02 | 0011 | 0011 data_03 | 0100 | 0100 data_04 | 0101 | 0101 data_05 | 0110 | 0110 data_06 | 0111 | 0111 data_07 | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'NEXT_STATE_reg' using encoding 'sequential' in module 'reconfigure_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init_read | 00000 | 00000 read_waitdrdy | 00001 | 00001 write_waitdrdy | 00010 | 00010 read_reg00 | 00011 | 00011 reg00_waitdrdy | 00100 | 00100 read_reg01 | 00101 | 00101 reg01_waitdrdy | 00110 | 00110 read_reg02 | 00111 | 00111 reg02_waitdrdy | 01000 | 01000 read_reg06 | 01001 | 01001 reg06_waitdrdy | 01010 | 01010 read_reg20 | 01011 | 01011 reg20_waitdrdy | 01100 | 01100 read_reg21 | 01101 | 01101 reg21_waitdrdy | 01110 | 01110 read_reg22 | 01111 | 01111 reg22_waitdrdy | 10000 | 10000 read_reg23 | 10001 | 10001 reg23_waitdrdy | 10010 | 10010 read_reg24 | 10011 | 10011 reg24_waitdrdy | 10100 | 10100 read_reg25 | 10101 | 10101 reg25_waitdrdy | 10110 | 10110 read_reg26 | 10111 | 10111 reg26_waitdrdy | 11000 | 11000 read_reg27 | 11001 | 11001 reg27_waitdrdy | 11010 | 11010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'xadc_ftm' INFO: [Synth 8-3971] The signal "ipbus_dpram_frame_init:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_ctrl_init:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized1:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_tob_init:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:51 ; elapsed = 00:01:09 . Memory (MB): peak = 2562.008 ; gain = 539.688 ; free physical = 3105 ; free virtual = 21235 --------------------------------------------------------------------------------- Report RTL Partitions: +------+----------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+----------------------+------------+----------+ |1 |clocks_7s_extphy__GC0 | 1| 132| |2 |ipbus_mgt_source__GB0 | 1| 42471| |3 |ipbus_mgt_source__GB1 | 1| 12034| |4 |slaves__GC0 | 1| 28790| |5 |top_FTM_DSS__GC0 | 1| 24404| +------+----------------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 31 Bit Adders := 1 2 Input 16 Bit Adders := 1 2 Input 13 Bit Adders := 2 2 Input 9 Bit Adders := 5 2 Input 8 Bit Adders := 9 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 4 2 Input 3 Bit Adders := 132 2 Input 2 Bit Adders := 2 +---XORs : 3 Input 1 Bit XORs := 276 9 Input 1 Bit XORs := 169 2 Input 1 Bit XORs := 959 4 Input 1 Bit XORs := 276 21 Input 1 Bit XORs := 60 15 Input 1 Bit XORs := 108 10 Input 1 Bit XORs := 217 19 Input 1 Bit XORs := 60 14 Input 1 Bit XORs := 60 12 Input 1 Bit XORs := 60 7 Input 1 Bit XORs := 60 13 Input 1 Bit XORs := 48 11 Input 1 Bit XORs := 144 18 Input 1 Bit XORs := 48 +---Registers : 128 Bit Registers := 7 120 Bit Registers := 1 80 Bit Registers := 2 48 Bit Registers := 2 45 Bit Registers := 2 42 Bit Registers := 1 38 Bit Registers := 1 34 Bit Registers := 1 32 Bit Registers := 360 31 Bit Registers := 1 24 Bit Registers := 1 22 Bit Registers := 1 20 Bit Registers := 1 16 Bit Registers := 84 13 Bit Registers := 18 12 Bit Registers := 6 10 Bit Registers := 1 9 Bit Registers := 132 8 Bit Registers := 27 7 Bit Registers := 6 6 Bit Registers := 2 5 Bit Registers := 5 4 Bit Registers := 184 3 Bit Registers := 190 2 Bit Registers := 103 1 Bit Registers := 1600 +---RAMs : 256K Bit RAMs := 73 64K Bit RAMs := 4 32K Bit RAMs := 49 4K Bit RAMs := 2 +---Muxes : 2 Input 128 Bit Muxes := 8 4 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 80 Bit Muxes := 4 2 Input 48 Bit Muxes := 1 5 Input 48 Bit Muxes := 1 3 Input 38 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 2 Input 32 Bit Muxes := 216 3 Input 32 Bit Muxes := 158 8 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 15 9 Input 32 Bit Muxes := 1 6 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 2 2 Input 24 Bit Muxes := 1 3 Input 22 Bit Muxes := 1 2 Input 16 Bit Muxes := 37 3 Input 16 Bit Muxes := 12 4 Input 16 Bit Muxes := 2 14 Input 16 Bit Muxes := 3 11 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 18 Input 16 Bit Muxes := 4 3 Input 13 Bit Muxes := 49 2 Input 13 Bit Muxes := 23 8 Input 13 Bit Muxes := 1 4 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 4 5 Input 11 Bit Muxes := 1 4 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 73 2 Input 8 Bit Muxes := 135 6 Input 8 Bit Muxes := 2 13 Input 8 Bit Muxes := 1 5 Input 8 Bit Muxes := 3 4 Input 8 Bit Muxes := 1 17 Input 8 Bit Muxes := 1 3 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 13 7 Input 7 Bit Muxes := 1 6 Input 6 Bit Muxes := 2 27 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 9 4 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 1 7 Input 6 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 27 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 20 5 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 62 4 Input 4 Bit Muxes := 2 9 Input 4 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 6 Input 4 Bit Muxes := 2 5 Input 4 Bit Muxes := 3 3 Input 4 Bit Muxes := 1 3 Input 3 Bit Muxes := 48 6 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 5 5 Input 3 Bit Muxes := 3 8 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 160 27 Input 2 Bit Muxes := 2 17 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 762 4 Input 1 Bit Muxes := 11 6 Input 1 Bit Muxes := 8 3 Input 1 Bit Muxes := 8 9 Input 1 Bit Muxes := 7 27 Input 1 Bit Muxes := 16 11 Input 1 Bit Muxes := 2 12 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 9 8 Input 1 Bit Muxes := 9 5 Input 1 Bit Muxes := 4 7 Input 1 Bit Muxes := 8 16 Input 1 Bit Muxes := 9 17 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top_FTM_DSS Detailed RTL Component Info : +---XORs : 9 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 1 +---Registers : 32 Bit Registers := 60 9 Bit Registers := 2 4 Bit Registers := 60 1 Bit Registers := 2 Module clock_div Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 Module clocks_7s_extphy Detailed RTL Component Info : +---Registers : 1 Bit Registers := 7 Module ipbus_fabric_branch__parameterized0 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 48 Module framing_sync_logic__1 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__1 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__1 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__1 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__1 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__2 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__2 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__2 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__2 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__2 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__3 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__3 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__3 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__3 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__3 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__3 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__4 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__4 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__4 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__4 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__4 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__4 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__5 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__5 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__5 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__5 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__5 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__5 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__6 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__6 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__6 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__6 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__6 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__6 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__7 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__7 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__7 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__7 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__7 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__7 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__8 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__8 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__8 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__8 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__8 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__8 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__9 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__9 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__9 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__9 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__9 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__9 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__10 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__10 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__10 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__10 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__10 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__10 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__11 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__11 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__11 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__11 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__11 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__11 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__12 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__12 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__12 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__12 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__12 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__12 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__12 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__12 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__13 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__13 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__13 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__13 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__13 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__13 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__13 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__13 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__14 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__14 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__14 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__14 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__14 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__14 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__14 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__14 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__15 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__15 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__15 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__15 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__15 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__15 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__15 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__15 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__16 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__16 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__16 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__16 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__16 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__16 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__16 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__16 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__17 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__17 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__17 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__17 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__17 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__17 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__17 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__17 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__18 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__18 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__18 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__18 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__18 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__18 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__18 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__18 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__19 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__19 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__19 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__19 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__19 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__19 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__19 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__19 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__20 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__20 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__20 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__20 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__20 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__20 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__20 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__20 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__21 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__21 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__21 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__21 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__21 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__21 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__21 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__21 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__22 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__22 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__22 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__22 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__22 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__22 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__22 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__22 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__23 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__23 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__23 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__23 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__23 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__23 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__23 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__23 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__24 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__24 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__24 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__24 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__24 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__24 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__24 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__24 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__25 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__25 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__25 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__25 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__25 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__25 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__25 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__25 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__26 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__26 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__26 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__26 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__26 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__26 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__26 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__26 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__27 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__27 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__27 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__27 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__27 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__27 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__27 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__27 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__28 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__28 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__28 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__28 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__28 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__28 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__28 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__28 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__29 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__29 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__29 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__29 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__29 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__29 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__29 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__29 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__30 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__30 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__30 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__30 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__30 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__30 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__30 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__30 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__31 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__31 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__31 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__31 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__31 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__31 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__31 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__31 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__32 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__32 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__32 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__32 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__32 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__32 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__32 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__32 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__33 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__33 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__33 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__33 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__33 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__33 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__33 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__33 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__34 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__34 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__34 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__34 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__34 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__34 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__34 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__34 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__35 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__35 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__35 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__35 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__35 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__35 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__35 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__35 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__36 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__36 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__36 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__36 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__36 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__36 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__36 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__36 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__37 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__37 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__37 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__37 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__37 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__37 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__37 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__37 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__38 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__38 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__38 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__38 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__38 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__38 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__38 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__38 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__39 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__39 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__39 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__39 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__39 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__39 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__39 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__39 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__40 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__40 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__40 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__40 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__40 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__40 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__40 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__40 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__41 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__41 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__41 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__41 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__41 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__41 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__41 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__41 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__42 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__42 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__42 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__42 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__42 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__42 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__42 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__42 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__43 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__43 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__43 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__43 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__43 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__43 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__43 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__43 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__44 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__44 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__44 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__44 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__44 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__44 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__44 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__44 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__45 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__45 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__45 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__45 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__45 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__45 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__45 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__45 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__46 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__46 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__46 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__46 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__46 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__46 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__46 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__46 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic__47 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge__47 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init__47 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init__47 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32__47 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23__47 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator__47 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source__47 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module framing_sync_logic Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ipbus_fabric_merge Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module ipbus_dpram_frame_init Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_dpram_ctrl_init Detailed RTL Component Info : +---Registers : 4 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module osum_crc9d32 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module osum_crc9d23 Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 6 3 Input 1 Bit XORs := 2 4 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 11 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 1 9 Input 1 Bit XORs := 1 18 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 Module dummy_frame_generator Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 3 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 3 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module ipbus_data_source Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 Module ipbus_fabric_sel Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 10 Module ipbus_ftm_fpga_id_version Detailed RTL Component Info : +---Muxes : 8 Input 32 Bit Muxes := 1 Module ipbus_ctrlreg_v Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 2 Input 1 Bit Muxes := 2 Module ipbus_fabric_branch Detailed RTL Component Info : +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module ipbus_ctrlreg_v__parameterized0 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 4 4 Bit Registers := 1 +---Muxes : 4 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 8 Module ipbus_watchdog Detailed RTL Component Info : +---Adders : 2 Input 31 Bit Adders := 1 +---Registers : 31 Bit Registers := 1 20 Bit Registers := 1 1 Bit Registers := 12 +---Muxes : 2 Input 32 Bit Muxes := 2 2 Input 31 Bit Muxes := 2 2 Input 1 Bit Muxes := 5 Module ipbus_dpram Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 4K Bit RAMs := 1 Module ipbus_dpram__parameterized0 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 4K Bit RAMs := 1 Module command_sync Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 4 Input 1 Bit Muxes := 1 Module spi32_8_control Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 6 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 1 6 Bit Registers := 1 1 Bit Registers := 7 +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 1 6 Input 6 Bit Muxes := 1 6 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 6 6 Input 1 Bit Muxes := 4 3 Input 1 Bit Muxes := 4 Module clock_pulse Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 1 Bit Registers := 2 Module ipbus_spi32 Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 1 Module ipbus_ctrlreg_v__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 4 2 Input 1 Bit Muxes := 2 Module reconfigure_fsm Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 9 Input 32 Bit Muxes := 1 2 Input 9 Bit Muxes := 1 9 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 9 Input 1 Bit Muxes := 3 Module xadc_ftm Detailed RTL Component Info : +---Registers : 16 Bit Registers := 13 7 Bit Registers := 1 2 Bit Registers := 2 +---Muxes : 27 Input 6 Bit Muxes := 1 27 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 14 2 Input 2 Bit Muxes := 2 27 Input 2 Bit Muxes := 2 27 Input 1 Bit Muxes := 16 Module ipbus_xadc_array Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 2 Input 16 Bit Muxes := 1 Module ipbus_fabric_sel__parameterized0 Detailed RTL Component Info : +---Muxes : 4 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module ipbus_ctrlreg_v__parameterized1__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module ipbus_xcvr_control__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 12 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 Module ipbus_ctrlreg_v__parameterized1__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module ipbus_xcvr_control__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 12 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 Module ipbus_ctrlreg_v__parameterized1__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module ipbus_xcvr_control__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 12 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 Module ipbus_ctrlreg_v__parameterized1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 2 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 2 4 Input 32 Bit Muxes := 2 2 Input 1 Bit Muxes := 4 Module ipbus_xcvr_control Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 12 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 2 Bit Muxes := 1 Module ipbus_dss_xcvr_control Detailed RTL Component Info : +---Muxes : 5 Input 3 Bit Muxes := 1 Module ipbus_dss_buffer_control Detailed RTL Component Info : +---Registers : 7 Bit Registers := 1 5 Bit Registers := 2 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 5 Input 11 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 2 Module ipbus_fabric_branch__parameterized1 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 12 Module ipbus_fabric_branch__parameterized2__1 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__3 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__3 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__2 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__2 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__2 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__5 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__5 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__4 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__4 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__2 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__3 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__7 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__7 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__3 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__6 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__6 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__3 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__4 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__9 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__9 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__4 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__8 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__8 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__4 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__5 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__11 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__11 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__5 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__10 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__10 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__5 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__6 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__13 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__13 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__6 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__12 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__12 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__6 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__7 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__15 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__15 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__7 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__14 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__14 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__7 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__8 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__17 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__17 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__8 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__16 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__16 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__8 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__9 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__19 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__19 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__9 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__18 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__18 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__9 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__10 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__21 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__21 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__10 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__20 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__20 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__10 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2__11 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic__23 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__23 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink__11 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__22 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__22 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter__11 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized2 Detailed RTL Component Info : +---Muxes : 3 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 Module rx_framing_sync_logic Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram__parameterized1 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_sink Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module rx_framing_sync_logic__1 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 3 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 2 Module rx_ram_pointer__1 Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 1 Bit Muxes := 1 Module ipbus_dpram_tob_init Detailed RTL Component Info : +---Registers : 32 Bit Registers := 2 1 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 Module ipbus_data_check Detailed RTL Component Info : +---Registers : 32 Bit Registers := 3 1 Bit Registers := 2 Module ipbus_counter Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_fabric_branch__parameterized3 Detailed RTL Component Info : +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 1 Bit Muxes := 12 Module osum_crc9d32__parameterized0__1 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__1 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__1 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__2 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__2 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__2 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__3 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__3 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__3 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__4 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__4 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__4 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__5 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__5 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__5 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__6 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__6 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__6 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__7 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__7 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__7 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__8 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__8 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__8 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__9 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__9 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__9 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__10 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__10 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__10 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0__11 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check__11 Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array__11 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module osum_crc9d32__parameterized0 Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 3 9 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 11 4 Input 1 Bit XORs := 3 21 Input 1 Bit XORs := 1 15 Input 1 Bit XORs := 1 10 Input 1 Bit XORs := 2 19 Input 1 Bit XORs := 1 14 Input 1 Bit XORs := 1 12 Input 1 Bit XORs := 1 7 Input 1 Bit XORs := 1 +---Registers : 9 Bit Registers := 1 +---Muxes : 2 Input 9 Bit Muxes := 1 Module mgt_data_check Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 9 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 Module ipbus_counter_array Detailed RTL Component Info : +---Registers : 16 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 3 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 Module slaves Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 +---Muxes : 11 Input 4 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 Module DSS_3Quads_11g2_common_reset Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module DSS_3quads_11g2_mgts Detailed RTL Component Info : +---Registers : 1 Bit Registers := 84 +---Muxes : 2 Input 1 Bit Muxes := 24 Module DSS_3Quads_11g2_common_reset__5 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module DSS_3quads_11g2_mgts__parameterized0 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 84 +---Muxes : 2 Input 1 Bit Muxes := 24 Module DSS_3Quads_11g2_common_reset__4 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module DSS_3quads_11g2_mgts__parameterized1 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 84 +---Muxes : 2 Input 1 Bit Muxes := 24 Module DSS_3Quads_11g2_common_reset__3 Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 1 Bit Muxes := 2 Module DSS_3quads_11g2_mgts__parameterized2 Detailed RTL Component Info : +---Registers : 1 Bit Registers := 84 +---Muxes : 2 Input 1 Bit Muxes := 24 Module comma_monitor__1 Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module comma_monitor Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 1 Bit Registers := 1 Module UDP_slave_if Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 8 Bit Registers := 2 1 Bit Registers := 9 +---Muxes : 2 Input 8 Bit Muxes := 4 2 Input 1 Bit Muxes := 6 Module udp_ipaddr_block Detailed RTL Component Info : +---Registers : 80 Bit Registers := 2 48 Bit Registers := 1 42 Bit Registers := 1 32 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 80 Bit Muxes := 4 2 Input 1 Bit Muxes := 2 Module udp_build_payload Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 4 13 Bit Registers := 6 8 Bit Registers := 2 1 Bit Registers := 20 +---Muxes : 2 Input 16 Bit Muxes := 6 4 Input 16 Bit Muxes := 2 14 Input 16 Bit Muxes := 3 11 Input 16 Bit Muxes := 1 2 Input 13 Bit Muxes := 12 2 Input 8 Bit Muxes := 2 13 Input 8 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 4 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 23 9 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 2 11 Input 1 Bit Muxes := 2 12 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 9 Module udp_build_resend Detailed RTL Component Info : +---Registers : 45 Bit Registers := 1 16 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module udp_build_status Detailed RTL Component Info : +---Adders : 2 Input 7 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 13 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 4 1 Bit Registers := 9 +---Muxes : 2 Input 128 Bit Muxes := 2 2 Input 8 Bit Muxes := 2 2 Input 7 Bit Muxes := 9 2 Input 6 Bit Muxes := 2 7 Input 6 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 6 8 Input 1 Bit Muxes := 1 6 Input 1 Bit Muxes := 3 Module udp_status_buffer Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : 128 Bit Registers := 4 16 Bit Registers := 1 8 Bit Registers := 1 5 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 13 +---Muxes : 2 Input 128 Bit Muxes := 4 4 Input 128 Bit Muxes := 1 2 Input 32 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 2 Input 5 Bit Muxes := 3 5 Input 5 Bit Muxes := 1 6 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 4 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 25 5 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 2 Module udp_byte_sum__1 Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 2 +---Registers : 9 Bit Registers := 4 8 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 9 Bit Muxes := 6 2 Input 8 Bit Muxes := 7 2 Input 1 Bit Muxes := 9 Module udp_do_rx_reset Detailed RTL Component Info : +---Registers : 12 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 12 Bit Muxes := 1 Module udp_packet_parser Detailed RTL Component Info : +---Registers : 128 Bit Registers := 1 120 Bit Registers := 1 48 Bit Registers := 1 45 Bit Registers := 1 38 Bit Registers := 1 34 Bit Registers := 1 32 Bit Registers := 4 24 Bit Registers := 1 22 Bit Registers := 1 16 Bit Registers := 1 10 Bit Registers := 1 6 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 16 +---Muxes : 2 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 48 Bit Muxes := 1 5 Input 48 Bit Muxes := 1 3 Input 38 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 2 Input 32 Bit Muxes := 4 4 Input 32 Bit Muxes := 1 2 Input 24 Bit Muxes := 1 3 Input 22 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 4 Input 10 Bit Muxes := 1 5 Input 8 Bit Muxes := 3 6 Input 8 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 5 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 41 4 Input 1 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 Module udp_rxram_mux Detailed RTL Component Info : +---Registers : 13 Bit Registers := 2 8 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 3 Bit Muxes := 2 5 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 5 Module udp_DualPortRAM Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 +---RAMs : 32K Bit RAMs := 1 Module udp_buffer_selector Detailed RTL Component Info : +---Registers : 2 Bit Registers := 3 1 Bit Registers := 6 +---Muxes : 2 Input 2 Bit Muxes := 8 2 Input 1 Bit Muxes := 2 Module udp_rxram_shim Detailed RTL Component Info : +---Registers : 13 Bit Registers := 3 1 Bit Registers := 3 +---Muxes : 2 Input 13 Bit Muxes := 1 Module udp_DualPortRAM_rx Detailed RTL Component Info : +---Registers : 8 Bit Registers := 4 +---RAMs : 64K Bit RAMs := 4 +---Muxes : 4 Input 1 Bit Muxes := 4 Module udp_buffer_selector__parameterized0 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---Registers : 16 Bit Registers := 3 4 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 2 Input 16 Bit Muxes := 8 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module udp_rxtransactor_if Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 2 Module udp_DualPortRAM_tx Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 2 Bit Registers := 1 +---RAMs : 256K Bit RAMs := 1 +---Muxes : 4 Input 8 Bit Muxes := 1 Module udp_buffer_selector__parameterized1 Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---Registers : 16 Bit Registers := 3 4 Bit Registers := 2 1 Bit Registers := 4 +---Muxes : 2 Input 16 Bit Muxes := 8 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 Module udp_byte_sum Detailed RTL Component Info : +---Adders : 2 Input 9 Bit Adders := 2 +---Registers : 9 Bit Registers := 4 8 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 9 Bit Muxes := 6 2 Input 8 Bit Muxes := 7 2 Input 1 Bit Muxes := 9 Module udp_tx_mux Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 1 2 Input 5 Bit Adders := 1 +---Registers : 32 Bit Registers := 1 16 Bit Registers := 4 13 Bit Registers := 6 8 Bit Registers := 4 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 25 +---Muxes : 6 Input 32 Bit Muxes := 1 18 Input 16 Bit Muxes := 4 2 Input 13 Bit Muxes := 10 8 Input 13 Bit Muxes := 1 4 Input 13 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 8 Bit Muxes := 13 17 Input 8 Bit Muxes := 1 2 Input 5 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 17 Input 2 Bit Muxes := 2 2 Input 2 Bit Muxes := 1 8 Input 1 Bit Muxes := 8 7 Input 1 Bit Muxes := 7 2 Input 1 Bit Muxes := 27 5 Input 1 Bit Muxes := 2 9 Input 1 Bit Muxes := 3 16 Input 1 Bit Muxes := 8 17 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 2 Module udp_txtransactor_if Detailed RTL Component Info : +---Registers : 16 Bit Registers := 16 4 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 16 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 2 Input 1 Bit Muxes := 16 16 Input 1 Bit Muxes := 1 Module udp_clock_crossing_if Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 10 +---Registers : 4 Bit Registers := 5 3 Bit Registers := 7 2 Bit Registers := 5 1 Bit Registers := 8 +---Muxes : 2 Input 4 Bit Muxes := 2 2 Input 3 Bit Muxes := 2 Module UDP_if Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 1 Bit Registers := 5 Module transactor_if Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 16 Bit Registers := 2 12 Bit Registers := 1 1 Bit Registers := 5 +---Muxes : 2 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 7 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 3 7 Input 1 Bit Muxes := 1 Module transactor_sm Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 8 Bit Adders := 3 +---Registers : 32 Bit Registers := 5 8 Bit Registers := 3 4 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 5 3 Input 8 Bit Muxes := 1 6 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 6 2 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 1 6 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 3 Input 1 Bit Muxes := 2 6 Input 1 Bit Muxes := 1 Module transactor_cfg Detailed RTL Component Info : +---Registers : 128 Bit Registers := 1 +---Muxes : 2 Input 128 Bit Muxes := 1 4 Input 32 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2160 (col length:120) BRAMs: 1760 (col length: RAMB18 120 RAMB36 60) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met INFO: [Synth 8-4471] merging register 'reggen[2].xcvr_regs/xcvr_status_reg[3][31:0]' into 'reggen[3].xcvr_regs/xcvr_status_reg[3][31:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_xcvr_control.vhd:47] INFO: [Synth 8-4471] merging register 'reggen[1].xcvr_regs/xcvr_status_reg[3][31:0]' into 'reggen[3].xcvr_regs/xcvr_status_reg[3][31:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_xcvr_control.vhd:47] INFO: [Synth 8-4471] merging register 'reggen[0].xcvr_regs/xcvr_status_reg[3][31:0]' into 'reggen[3].xcvr_regs/xcvr_status_reg[3][31:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/DSS/hdl/ipbus_xcvr_control.vhd:47] INFO: [Synth 8-5544] ROM "buf_to_load_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse WARNING: [Synth 8-3917] design top_FTM_DSS has port test_pin3 driven by constant 0 INFO: [Synth 8-3971] The signal "slavesi_4/spi_flash/spi_dpram_in/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[11].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[10].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[9].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[8].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[7].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[6].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[5].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[4].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[3].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[2].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[1].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-3971] The signal "slavesi_4/rx_bufs/\bufgen[0].rxbuf /rx_spy/dssram/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM rx_spy/dssram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[0].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[0].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[12].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[12].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[13].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[13].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[14].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[14].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[15].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[15].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[16].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[16].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[17].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[17].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[18].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[18].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[19].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[19].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[20].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[20].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][14]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][14]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][15]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][15]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][23]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][23]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][24]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][24]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][25]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][25]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][26]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][26]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][27]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][27]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][28]' INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][28]' (FD) to 'tx_bufsi_2/bufgen[21].txbuf/dummy/data_int_reg[data][29]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[21].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3886] merging instance 'tx_bufsi_2/bufgen[22].txbuf/dummy/data_int_reg[data][13]' (FD) to 'tx_bufsi_2/bufgen[22].txbuf/dummy/data_int_reg[data][14]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[22].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[23].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[24].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[25].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[26].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[27].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[28].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[29].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[30].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[31].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[32].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[33].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[34].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[35].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[36].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[37].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[38].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[39].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[40].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[41].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[42].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[43].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[44].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[45].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[46].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_2/\bufgen[47].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[11].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[1].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[2].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[3].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[4].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[5].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[6].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[7].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[8].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[9].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (tx_bufsi_3/\bufgen[10].txbuf /\dummy/data_int_reg[data][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (slavesi_4/monitoring/\adc_inst/daddr_reg[4] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (slavesi_4/xcvr_control/\reggen[3].xcvr_regs/xcvr_status_reg[3][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (slavesi_4/xcvr_control/\reggen[0].xcvr_regs/xcvr_status_reg[0][31] ) WARNING: [Synth 8-3332] Sequential element (synch/FSM_onehot_sequencer_reg[3]) is unused and will be removed from module ipbus_spi32. INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /rx_packet_parser/\pkt_data_reg[5]__1 ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[32] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[33] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[34] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[35] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[36] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[37] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[38] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[39] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[40] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[41] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[42] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[43] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[44] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[45] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[46] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[47] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[48] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[49] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[50] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[51] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[52] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[53] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[54] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[55] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[56] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[57] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[58] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[59] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[60] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[61] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[62] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[63] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[64] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[65] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[66] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[67] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[68] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[69] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[70] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[71] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[72] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[73] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[74] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[75] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[76] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[77] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ipbus/udp_if /status_buffer/\header_reg[78] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:36 ; elapsed = 00:03:10 . Memory (MB): peak = 2930.688 ; gain = 908.367 ; free physical = 2625 ; free virtual = 20895 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +-------------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-------------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |tx_bufsi_2/\bufgen[47].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[47].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[46].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[46].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[45].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[45].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[44].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[44].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[43].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[43].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[42].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[42].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[41].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[41].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[40].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[40].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[39].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[39].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[38].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[38].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[37].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[37].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[36].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[36].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[35].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[35].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[34].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[34].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[33].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[33].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[32].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[32].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[31].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[31].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[30].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[30].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[29].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[29].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[28].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[28].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[27].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[27].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[26].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[26].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[25].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[25].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[24].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[24].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[23].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[23].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[22].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[22].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[21].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[21].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[20].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[20].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[19].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[19].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[18].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[18].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[17].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[17].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[16].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[16].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[15].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[15].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[14].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[14].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[13].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[13].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[12].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[12].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[0].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[0].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[10].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[10].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[9].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[9].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[8].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[8].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[7].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[7].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[6].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[6].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[5].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[5].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[4].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[4].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[3].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[3].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[2].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[2].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[1].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[1].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[11].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[11].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |slavesi_4/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |slavesi_4/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |slavesi_4/rx_bufs/\bufgen[11].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[11].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[10].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[10].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[9].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[9].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[8].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[8].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[7].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[7].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[6].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[6].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[5].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[5].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[4].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[4].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[3].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[3].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[2].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[2].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[1].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[1].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[0].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[0].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |i_0/\ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | +-------------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +------+----------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+----------------------+------------+----------+ |1 |clocks_7s_extphy__GC0 | 1| 35| |2 |ipbus_mgt_source__GB0 | 1| 19535| |3 |ipbus_mgt_source__GB1 | 1| 5973| |4 |slaves__GC0 | 1| 20794| |5 |top_FTM_DSS__GC0 | 1| 17419| +------+----------------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:49 ; elapsed = 00:03:31 . Memory (MB): peak = 2933.660 ; gain = 911.340 ; free physical = 2503 ; free virtual = 20774 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:03:33 ; elapsed = 00:04:16 . Memory (MB): peak = 2971.660 ; gain = 949.340 ; free physical = 2439 ; free virtual = 20710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +-------------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-------------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |slavesi_4/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |slavesi_4/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |slavesi_4/rx_bufs/\bufgen[11].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[11].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[10].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[10].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[9].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[9].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[8].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[8].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[7].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[7].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[6].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[6].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[5].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[5].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[4].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[4].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[3].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[3].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[2].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[2].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[1].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[1].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[0].rxbuf | rx_spy/dssram/ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 8 | |slavesi_4/rx_bufs/\bufgen[0].rxbuf | rx_check/dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[47].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[47].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[46].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[46].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[45].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[45].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[44].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[44].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[43].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[43].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[42].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[42].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[41].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[41].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[40].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[40].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[39].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[39].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[38].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[38].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[37].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[37].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[36].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[36].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[35].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[35].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[34].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[34].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[33].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[33].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[32].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[32].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[31].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[31].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[30].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[30].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[29].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[29].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[28].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[28].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[27].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[27].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[26].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[26].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[25].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[25].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[24].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[24].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[23].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[23].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[22].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[22].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[21].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[21].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[20].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[20].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[19].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[19].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[18].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[18].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[17].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[17].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[16].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[16].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[15].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[15].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[14].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[14].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[13].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[13].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[12].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[12].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_2/\bufgen[0].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_2/\bufgen[0].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[10].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[10].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[9].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[9].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[8].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[8].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[7].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[7].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[6].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[6].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[5].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[5].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[4].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[4].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[3].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[3].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[2].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[2].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[1].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[1].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |tx_bufsi_3/\bufgen[11].txbuf | dssram/ram_reg | 8 K x 32(READ_FIRST) | W | R | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |tx_bufsi_3/\bufgen[11].txbuf | ctrlram/ram_reg | 8 K x 4(READ_FIRST) | W | R | 8 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_0/\ipbus/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |i_0/\ipbus/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | +-------------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +------+----------------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+----------------------+------------+----------+ |1 |clocks_7s_extphy__GC0 | 1| 35| |2 |slaves__GC0 | 1| 20794| |3 |top_FTM_DSS_GT0 | 1| 38970| +------+----------------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7053] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_spy/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[11].rxbuf/rx_check/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_spy/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[10].rxbuf/rx_check/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_spy/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[9].rxbuf/rx_check/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_spy/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[8].rxbuf/rx_check/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_spy/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[7].rxbuf/rx_check/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_spy/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[6].rxbuf/rx_check/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7053] The timing for the instance slaves/rx_bufs/bufgen[5].rxbuf/rx_spy/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Common 17-14] Message 'Synth 8-7053' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:04:01 ; elapsed = 00:04:44 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2624 ; free virtual = 20894 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-5365] Flop spi_engine/gen_enable_bytes.le_int_reg is being inverted and renamed to spi_engine/gen_enable_bytes.le_int_reg_inv. INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [6] is driving 624 big block pins (URAM, BRAM and DSP loads). Created 64 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_addr] [6] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [7] is driving 624 big block pins (URAM, BRAM and DSP loads). Created 64 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_addr] [7] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [10] is driving 624 big block pins (URAM, BRAM and DSP loads). Created 64 replicas of its driver. INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [7] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [7] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [8] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [8] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [9] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [9] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [10] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [10] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [11] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [11] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [12] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [12] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [13] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [13] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [14] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [14] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [15] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [15] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [16] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [16] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [17] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [17] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [18] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [18] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [19] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [19] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [20] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [20] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [21] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [21] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [22] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [22] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [23] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [23] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [24] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [24] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [25] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [25] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [26] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [26] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [27] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [27] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [28] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [28] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [29] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [29] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [30] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [30] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_wdata] [31] is driving 72 big block pins (URAM, BRAM and DSP loads). Created 9 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_wdata] [31] is sub-optimal because some of its loads are not in same hierarchy as its driver INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [11] is driving 624 big block pins (URAM, BRAM and DSP loads). Created 64 replicas of its driver. INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [4] is driving 624 big block pins (URAM, BRAM and DSP loads). Created 64 replicas of its driver. INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_addr] [4] is sub-optimal because some of its loads are not in same hierarchy as its driver --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin gt_txfsmresetdone_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin gt_txfsmresetdone_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin mgts_217_219/gt_txfsmresetdone_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin mgts_217_219/gt_txfsmresetdone_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin mgts_214_216/gt_txfsmresetdone_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin mgts_214_216/gt_txfsmresetdone_r2_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin mgts_117_119/gt_txfsmresetdone_r_inferred:in0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin mgts_117_119/gt_txfsmresetdone_r2_inferred:in0 to constant 0 INFO: [Synth 8-4560] design has 17 instantiated BUFGs while the limit set by the -bufg synthesis option is 12 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:04:09 ; elapsed = 00:04:53 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2619 ; free virtual = 20890 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:04:09 ; elapsed = 00:04:53 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2619 ; free virtual = 20890 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:04:16 ; elapsed = 00:05:00 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2616 ; free virtual = 20886 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:04:17 ; elapsed = 00:05:01 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2616 ; free virtual = 20886 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:04:18 ; elapsed = 00:05:02 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2612 ; free virtual = 20883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:04:18 ; elapsed = 00:05:02 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2612 ; free virtual = 20883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +--------------+---------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +--------------+---------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |comma_monitor | pulse_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | |top_FTM_DSS | detect_txcomma0/pulse_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | |top_FTM_DSS | ipbus/udp_if/IPADDR/pkt_mask_reg[41] | 32 | 1 | YES | NO | YES | 0 | 1 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |top_FTM_DSS | ipbus/udp_if/resend/pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[33]__0 | 6 | 5 | YES | NO | YES | 5 | 0 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[18]__0 | 5 | 1 | YES | NO | YES | 1 | 0 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[11]__0 | 8 | 1 | YES | NO | YES | 1 | 0 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[37]__0 | 23 | 1 | YES | NO | YES | 0 | 1 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[13]__1 | 12 | 1 | YES | NO | YES | 1 | 0 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_data_reg[71] | 5 | 4 | YES | NO | YES | 4 | 0 | |top_FTM_DSS | ipbus/udp_if/rx_packet_parser/pkt_data_reg[59] | 4 | 1 | YES | NO | YES | 1 | 0 | +--------------+---------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+----------------+----------+ | |BlackBox name |Instances | +------+----------------+----------+ |1 |DSS_3Quads_11g2 | 4| |2 |ila_bcr | 1| +------+----------------+----------+ Report Cell Usage: +------+--------------------------+------+ | |Cell |Count | +------+--------------------------+------+ |1 |DSS_3Quads_11g2_bbox_1 | 1| |2 |DSS_3Quads_11g2_bbox_2 | 1| |3 |DSS_3Quads_11g2_bbox_2__3 | 1| |4 |DSS_3Quads_11g2_bbox_2__4 | 1| |5 |ila_bcr_bbox_3 | 1| |6 |BUFG | 21| |7 |BUFH | 12| |8 |CARRY4 | 828| |9 |GTHE2_COMMON | 12| |10 |IBUFDS_GTE2 | 12| |11 |ICAPE2 | 1| |12 |LUT1 | 487| |13 |LUT2 | 925| |14 |LUT3 | 2191| |15 |LUT4 | 2289| |16 |LUT5 | 3412| |17 |LUT6 | 4981| |18 |MMCME2_BASE | 1| |19 |MUXF7 | 633| |20 |MUXF8 | 37| |21 |RAMB36E1 | 48| |22 |RAMB36E1_1 | 48| |23 |RAMB36E1_11 | 1| |24 |RAMB36E1_12 | 16| |25 |RAMB36E1_13 | 12| |26 |RAMB36E1_14 | 48| |27 |RAMB36E1_15 | 12| |28 |RAMB36E1_16 | 12| |29 |RAMB36E1_17 | 12| |30 |RAMB36E1_2 | 288| |31 |RAMB36E1_3 | 48| |32 |RAMB36E1_4 | 1| |33 |RAMB36E1_5 | 1| |34 |RAMB36E1_6 | 96| |35 |SRL16 | 1| |36 |SRL16E | 15| |37 |SRLC32E | 8| |38 |STARTUPE2 | 1| |39 |XADC | 1| |40 |FDCE | 359| |41 |FDRE | 13915| |42 |FDSE | 542| |43 |IBUF | 124| |44 |IBUFDS | 13| |45 |IBUFGDS | 2| |46 |OBUF | 103| |47 |OBUFDS | 10| +------+--------------------------+------+ Report Instance Areas: +------+-----------------------------------+---------------------------------------------------+------+ | |Instance |Module |Cells | +------+-----------------------------------+---------------------------------------------------+------+ |1 |top | | 36775| |2 | mgts_114_116 |DSS_3quads_11g2_mgts__parameterized2 | 1488| |3 | DSS_3Quads_11g2_support_i |DSS_3Quads_11g2_support__parameterized0 | 1401| |4 | common0_i |DSS_3Quads_11g2_common_541 | 1| |5 | common1_i |DSS_3Quads_11g2_common_542 | 1| |6 | common2_i |DSS_3Quads_11g2_common_543 | 1| |7 | common_reset_i |DSS_3Quads_11g2_common_reset_544 | 30| |8 | gt_usrclk_source |DSS_3Quads_11g2_GT_USRCLK_SOURCE_545 | 9| |9 | detect_rxcomma0 |comma_monitor | 6| |10 | cclk_o |startup | 1| |11 | clocks |clocks_7s_extphy | 41| |12 | clkdiv |clock_div | 26| |13 | detect_txcomma0 |comma_monitor__2 | 6| |14 | interconnect_slave |UDP_slave_if | 49| |15 | ipbus |ipbus_ctrl | 7647| |16 | trans |transactor | 3672| |17 | iface |transactor_if | 949| |18 | sm |transactor_sm | 2709| |19 | udp_if |UDP_if | 3973| |20 | ipbus_rx_ram |udp_DualPortRAM_rx | 8| |21 | IPADDR |udp_ipaddr_block | 303| |22 | clock_crossing_if |udp_clock_crossing_if | 86| |23 | internal_ram |udp_DualPortRAM | 1| |24 | internal_ram_selector |udp_buffer_selector | 19| |25 | internal_ram_shim |udp_rxram_shim | 8| |26 | ipbus_tx_ram |udp_DualPortRAM_tx | 18| |27 | payload |udp_build_payload | 412| |28 | resend |udp_build_resend | 82| |29 | rx_byte_sum |udp_byte_sum | 81| |30 | rx_packet_parser |udp_packet_parser | 486| |31 | rx_ram_mux |udp_rxram_mux | 43| |32 | rx_ram_selector |udp_buffer_selector__parameterized0 | 130| |33 | rx_reset_block |udp_do_rx_reset | 22| |34 | rx_transactor |udp_rxtransactor_if | 6| |35 | status |udp_build_status | 328| |36 | status_buffer |udp_status_buffer | 691| |37 | tx_byte_sum |udp_byte_sum_540 | 76| |38 | tx_main |udp_tx_mux | 516| |39 | tx_ram_selector |udp_buffer_selector__parameterized1 | 202| |40 | tx_transactor |udp_txtransactor_if | 442| |41 | mgts_117_119 |DSS_3quads_11g2_mgts__parameterized1 | 1464| |42 | DSS_3Quads_11g2_support_i |DSS_3Quads_11g2_support__parameterized0__xdcDup__2 | 1341| |43 | common0_i |DSS_3Quads_11g2_common_535 | 1| |44 | common1_i |DSS_3Quads_11g2_common_536 | 1| |45 | common2_i |DSS_3Quads_11g2_common_537 | 1| |46 | common_reset_i |DSS_3Quads_11g2_common_reset_538 | 30| |47 | gt_usrclk_source |DSS_3Quads_11g2_GT_USRCLK_SOURCE_539 | 9| |48 | mgts_214_216 |DSS_3quads_11g2_mgts__parameterized0 | 1464| |49 | DSS_3Quads_11g2_support_i |DSS_3Quads_11g2_support__parameterized0__xdcDup__1 | 1341| |50 | common0_i |DSS_3Quads_11g2_common_530 | 1| |51 | common1_i |DSS_3Quads_11g2_common_531 | 1| |52 | common2_i |DSS_3Quads_11g2_common_532 | 1| |53 | common_reset_i |DSS_3Quads_11g2_common_reset_533 | 30| |54 | gt_usrclk_source |DSS_3Quads_11g2_GT_USRCLK_SOURCE_534 | 9| |55 | mgts_217_219 |DSS_3quads_11g2_mgts | 1464| |56 | DSS_3Quads_11g2_support_i |DSS_3Quads_11g2_support | 1341| |57 | common0_i |DSS_3Quads_11g2_common | 1| |58 | common1_i |DSS_3Quads_11g2_common_528 | 1| |59 | common2_i |DSS_3Quads_11g2_common_529 | 1| |60 | common_reset_i |DSS_3Quads_11g2_common_reset | 30| |61 | gt_usrclk_source |DSS_3Quads_11g2_GT_USRCLK_SOURCE | 9| |62 | slaves |slaves | 20689| |63 | spi_flash |ipbus_spi32 | 622| |64 | arbitration |ipbus_watchdog | 250| |65 | gen_clock |clock_pulse | 4| |66 | spi_control |ipbus_ctrlreg_v__parameterized0 | 195| |67 | spi_dpram_in |ipbus_dpram__parameterized0 | 17| |68 | spi_dpram_out |ipbus_dpram | 5| |69 | spi_engine |spi32_8_control | 132| |70 | synch |command_sync | 9| |71 | buffer_control |ipbus_dss_buffer_control | 63| |72 | configure |ipbus_self_configure | 167| |73 | \config |reconfigure_fsm | 102| |74 | wbstart_reg |ipbus_ctrlreg_v_527 | 65| |75 | fpga_control |ipbus_ctrlreg_v | 64| |76 | monitoring |ipbus_xadc_array | 310| |77 | adc_inst |xadc_ftm | 309| |78 | rx_bufs |ipbus_mgt_sink_ref | 3490| |79 | \bufgen[0].rxbuf |ipbus_mgt_ref | 258| |80 | rx_check |ipbus_data_check_518 | 120| |81 | dssram |ipbus_dpram_tob_init_524 | 9| |82 | frame_sync |rx_framing_sync_logic_525 | 11| |83 | ram_pointer |rx_ram_pointer_526 | 28| |84 | rx_errors |ipbus_counter_519 | 87| |85 | rx_spy |ipbus_data_sink_520 | 51| |86 | dssram |ipbus_dpram__parameterized1_521 | 9| |87 | frame_sync |rx_framing_sync_logic_522 | 11| |88 | ram_pointer |rx_ram_pointer_523 | 30| |89 | \bufgen[10].rxbuf |ipbus_mgt_ref_415 | 258| |90 | rx_check |ipbus_data_check_509 | 120| |91 | dssram |ipbus_dpram_tob_init_515 | 9| |92 | frame_sync |rx_framing_sync_logic_516 | 11| |93 | ram_pointer |rx_ram_pointer_517 | 28| |94 | rx_errors |ipbus_counter_510 | 87| |95 | rx_spy |ipbus_data_sink_511 | 51| |96 | dssram |ipbus_dpram__parameterized1_512 | 9| |97 | frame_sync |rx_framing_sync_logic_513 | 11| |98 | ram_pointer |rx_ram_pointer_514 | 30| |99 | \bufgen[11].rxbuf |ipbus_mgt_ref_416 | 258| |100 | rx_check |ipbus_data_check_500 | 120| |101 | dssram |ipbus_dpram_tob_init_506 | 9| |102 | frame_sync |rx_framing_sync_logic_507 | 11| |103 | ram_pointer |rx_ram_pointer_508 | 28| |104 | rx_errors |ipbus_counter_501 | 87| |105 | rx_spy |ipbus_data_sink_502 | 51| |106 | dssram |ipbus_dpram__parameterized1_503 | 9| |107 | frame_sync |rx_framing_sync_logic_504 | 11| |108 | ram_pointer |rx_ram_pointer_505 | 30| |109 | \bufgen[1].rxbuf |ipbus_mgt_ref_417 | 259| |110 | rx_check |ipbus_data_check_491 | 120| |111 | dssram |ipbus_dpram_tob_init_497 | 9| |112 | frame_sync |rx_framing_sync_logic_498 | 11| |113 | ram_pointer |rx_ram_pointer_499 | 28| |114 | rx_errors |ipbus_counter_492 | 87| |115 | rx_spy |ipbus_data_sink_493 | 52| |116 | dssram |ipbus_dpram__parameterized1_494 | 9| |117 | frame_sync |rx_framing_sync_logic_495 | 11| |118 | ram_pointer |rx_ram_pointer_496 | 31| |119 | \bufgen[2].rxbuf |ipbus_mgt_ref_418 | 258| |120 | rx_check |ipbus_data_check_482 | 120| |121 | dssram |ipbus_dpram_tob_init_488 | 9| |122 | frame_sync |rx_framing_sync_logic_489 | 11| |123 | ram_pointer |rx_ram_pointer_490 | 28| |124 | rx_errors |ipbus_counter_483 | 87| |125 | rx_spy |ipbus_data_sink_484 | 51| |126 | dssram |ipbus_dpram__parameterized1_485 | 9| |127 | frame_sync |rx_framing_sync_logic_486 | 11| |128 | ram_pointer |rx_ram_pointer_487 | 30| |129 | \bufgen[3].rxbuf |ipbus_mgt_ref_419 | 258| |130 | rx_check |ipbus_data_check_473 | 120| |131 | dssram |ipbus_dpram_tob_init_479 | 9| |132 | frame_sync |rx_framing_sync_logic_480 | 11| |133 | ram_pointer |rx_ram_pointer_481 | 28| |134 | rx_errors |ipbus_counter_474 | 87| |135 | rx_spy |ipbus_data_sink_475 | 51| |136 | dssram |ipbus_dpram__parameterized1_476 | 9| |137 | frame_sync |rx_framing_sync_logic_477 | 11| |138 | ram_pointer |rx_ram_pointer_478 | 30| |139 | \bufgen[4].rxbuf |ipbus_mgt_ref_420 | 258| |140 | rx_check |ipbus_data_check_464 | 120| |141 | dssram |ipbus_dpram_tob_init_470 | 9| |142 | frame_sync |rx_framing_sync_logic_471 | 11| |143 | ram_pointer |rx_ram_pointer_472 | 28| |144 | rx_errors |ipbus_counter_465 | 87| |145 | rx_spy |ipbus_data_sink_466 | 51| |146 | dssram |ipbus_dpram__parameterized1_467 | 9| |147 | frame_sync |rx_framing_sync_logic_468 | 11| |148 | ram_pointer |rx_ram_pointer_469 | 30| |149 | \bufgen[5].rxbuf |ipbus_mgt_ref_421 | 259| |150 | rx_check |ipbus_data_check_455 | 120| |151 | dssram |ipbus_dpram_tob_init_461 | 9| |152 | frame_sync |rx_framing_sync_logic_462 | 11| |153 | ram_pointer |rx_ram_pointer_463 | 28| |154 | rx_errors |ipbus_counter_456 | 87| |155 | rx_spy |ipbus_data_sink_457 | 52| |156 | dssram |ipbus_dpram__parameterized1_458 | 9| |157 | frame_sync |rx_framing_sync_logic_459 | 11| |158 | ram_pointer |rx_ram_pointer_460 | 31| |159 | \bufgen[6].rxbuf |ipbus_mgt_ref_422 | 258| |160 | rx_check |ipbus_data_check_446 | 120| |161 | dssram |ipbus_dpram_tob_init_452 | 9| |162 | frame_sync |rx_framing_sync_logic_453 | 11| |163 | ram_pointer |rx_ram_pointer_454 | 28| |164 | rx_errors |ipbus_counter_447 | 87| |165 | rx_spy |ipbus_data_sink_448 | 51| |166 | dssram |ipbus_dpram__parameterized1_449 | 9| |167 | frame_sync |rx_framing_sync_logic_450 | 11| |168 | ram_pointer |rx_ram_pointer_451 | 30| |169 | \bufgen[7].rxbuf |ipbus_mgt_ref_423 | 258| |170 | rx_check |ipbus_data_check_437 | 120| |171 | dssram |ipbus_dpram_tob_init_443 | 9| |172 | frame_sync |rx_framing_sync_logic_444 | 11| |173 | ram_pointer |rx_ram_pointer_445 | 28| |174 | rx_errors |ipbus_counter_438 | 87| |175 | rx_spy |ipbus_data_sink_439 | 51| |176 | dssram |ipbus_dpram__parameterized1_440 | 9| |177 | frame_sync |rx_framing_sync_logic_441 | 11| |178 | ram_pointer |rx_ram_pointer_442 | 30| |179 | \bufgen[8].rxbuf |ipbus_mgt_ref_424 | 258| |180 | rx_check |ipbus_data_check_428 | 120| |181 | dssram |ipbus_dpram_tob_init_434 | 9| |182 | frame_sync |rx_framing_sync_logic_435 | 11| |183 | ram_pointer |rx_ram_pointer_436 | 28| |184 | rx_errors |ipbus_counter_429 | 87| |185 | rx_spy |ipbus_data_sink_430 | 51| |186 | dssram |ipbus_dpram__parameterized1_431 | 9| |187 | frame_sync |rx_framing_sync_logic_432 | 11| |188 | ram_pointer |rx_ram_pointer_433 | 30| |189 | \bufgen[9].rxbuf |ipbus_mgt_ref_425 | 259| |190 | rx_check |ipbus_data_check | 120| |191 | dssram |ipbus_dpram_tob_init | 9| |192 | frame_sync |rx_framing_sync_logic_426 | 11| |193 | ram_pointer |rx_ram_pointer_427 | 28| |194 | rx_errors |ipbus_counter | 87| |195 | rx_spy |ipbus_data_sink | 52| |196 | dssram |ipbus_dpram__parameterized1 | 9| |197 | frame_sync |rx_framing_sync_logic | 11| |198 | ram_pointer |rx_ram_pointer | 31| |199 | fabric_decode |ipbus_fabric_branch__parameterized1 | 391| |200 | rx_error_monitors |ipbus_mgt_rx_monitor | 2844| |201 | \channel_gen[0].counters |ipbus_counter_array | 142| |202 | \channel_gen[0].data_check |mgt_data_check | 86| |203 | crc32 |osum_crc9d32__parameterized0_414 | 49| |204 | \channel_gen[10].counters |ipbus_counter_array_382 | 174| |205 | \channel_gen[10].data_check |mgt_data_check_383 | 86| |206 | crc32 |osum_crc9d32__parameterized0_413 | 49| |207 | \channel_gen[11].counters |ipbus_counter_array_384 | 158| |208 | \channel_gen[11].data_check |mgt_data_check_385 | 86| |209 | crc32 |osum_crc9d32__parameterized0_412 | 49| |210 | \channel_gen[1].counters |ipbus_counter_array_386 | 142| |211 | \channel_gen[1].data_check |mgt_data_check_387 | 86| |212 | crc32 |osum_crc9d32__parameterized0_411 | 49| |213 | \channel_gen[2].counters |ipbus_counter_array_388 | 142| |214 | \channel_gen[2].data_check |mgt_data_check_389 | 86| |215 | crc32 |osum_crc9d32__parameterized0_410 | 49| |216 | \channel_gen[3].counters |ipbus_counter_array_390 | 143| |217 | \channel_gen[3].data_check |mgt_data_check_391 | 86| |218 | crc32 |osum_crc9d32__parameterized0_409 | 49| |219 | \channel_gen[4].counters |ipbus_counter_array_392 | 142| |220 | \channel_gen[4].data_check |mgt_data_check_393 | 86| |221 | crc32 |osum_crc9d32__parameterized0_408 | 49| |222 | \channel_gen[5].counters |ipbus_counter_array_394 | 142| |223 | \channel_gen[5].data_check |mgt_data_check_395 | 86| |224 | crc32 |osum_crc9d32__parameterized0_407 | 49| |225 | \channel_gen[6].counters |ipbus_counter_array_396 | 142| |226 | \channel_gen[6].data_check |mgt_data_check_397 | 86| |227 | crc32 |osum_crc9d32__parameterized0_406 | 49| |228 | \channel_gen[7].counters |ipbus_counter_array_398 | 142| |229 | \channel_gen[7].data_check |mgt_data_check_399 | 86| |230 | crc32 |osum_crc9d32__parameterized0_405 | 49| |231 | \channel_gen[8].counters |ipbus_counter_array_400 | 185| |232 | \channel_gen[8].data_check |mgt_data_check_401 | 86| |233 | crc32 |osum_crc9d32__parameterized0_404 | 49| |234 | \channel_gen[9].counters |ipbus_counter_array_402 | 158| |235 | \channel_gen[9].data_check |mgt_data_check_403 | 86| |236 | crc32 |osum_crc9d32__parameterized0 | 49| |237 | tx_bufs |ipbus_mgt_source | 12467| |238 | \bufgen[0].txbuf |ipbus_data_source | 275| |239 | ctrlram |ipbus_dpram_ctrl_init_375 | 4| |240 | dssram |ipbus_dpram_frame_init_376 | 29| |241 | dummy |dummy_frame_generator_377 | 200| |242 | crc32_i |osum_crc9d32_380 | 76| |243 | crc9d23_i |osum_crc9d23_381 | 37| |244 | framer |framing_sync_logic_378 | 18| |245 | ram_pointer |tx_ram_pointer_379 | 21| |246 | \bufgen[10].txbuf |ipbus_data_source_6 | 223| |247 | ctrlram |ipbus_dpram_ctrl_init_368 | 4| |248 | dssram |ipbus_dpram_frame_init_369 | 29| |249 | dummy |dummy_frame_generator_370 | 148| |250 | crc32_i |osum_crc9d32_373 | 64| |251 | crc9d23_i |osum_crc9d23_374 | 25| |252 | framer |framing_sync_logic_371 | 18| |253 | ram_pointer |tx_ram_pointer_372 | 21| |254 | \bufgen[11].txbuf |ipbus_data_source_7 | 250| |255 | ctrlram |ipbus_dpram_ctrl_init_361 | 8| |256 | dssram |ipbus_dpram_frame_init_362 | 57| |257 | dummy |dummy_frame_generator_363 | 143| |258 | crc32_i |osum_crc9d32_366 | 64| |259 | crc9d23_i |osum_crc9d23_367 | 26| |260 | framer |framing_sync_logic_364 | 18| |261 | ram_pointer |tx_ram_pointer_365 | 21| |262 | \bufgen[12].txbuf |ipbus_data_source_8 | 254| |263 | ctrlram |ipbus_dpram_ctrl_init_354 | 4| |264 | dssram |ipbus_dpram_frame_init_355 | 29| |265 | dummy |dummy_frame_generator_356 | 179| |266 | crc32_i |osum_crc9d32_359 | 76| |267 | crc9d23_i |osum_crc9d23_360 | 37| |268 | framer |framing_sync_logic_357 | 18| |269 | ram_pointer |tx_ram_pointer_358 | 21| |270 | \bufgen[13].txbuf |ipbus_data_source_9 | 319| |271 | ctrlram |ipbus_dpram_ctrl_init_347 | 16| |272 | dssram |ipbus_dpram_frame_init_348 | 113| |273 | dummy |dummy_frame_generator_349 | 148| |274 | crc32_i |osum_crc9d32_352 | 64| |275 | crc9d23_i |osum_crc9d23_353 | 25| |276 | framer |framing_sync_logic_350 | 18| |277 | ram_pointer |tx_ram_pointer_351 | 21| |278 | \bufgen[14].txbuf |ipbus_data_source_10 | 223| |279 | ctrlram |ipbus_dpram_ctrl_init_340 | 4| |280 | dssram |ipbus_dpram_frame_init_341 | 29| |281 | dummy |dummy_frame_generator_342 | 148| |282 | crc32_i |osum_crc9d32_345 | 64| |283 | crc9d23_i |osum_crc9d23_346 | 25| |284 | framer |framing_sync_logic_343 | 18| |285 | ram_pointer |tx_ram_pointer_344 | 21| |286 | \bufgen[15].txbuf |ipbus_data_source_11 | 255| |287 | ctrlram |ipbus_dpram_ctrl_init_333 | 8| |288 | dssram |ipbus_dpram_frame_init_334 | 57| |289 | dummy |dummy_frame_generator_335 | 148| |290 | crc32_i |osum_crc9d32_338 | 64| |291 | crc9d23_i |osum_crc9d23_339 | 25| |292 | framer |framing_sync_logic_336 | 18| |293 | ram_pointer |tx_ram_pointer_337 | 21| |294 | \bufgen[16].txbuf |ipbus_data_source_12 | 254| |295 | ctrlram |ipbus_dpram_ctrl_init_326 | 4| |296 | dssram |ipbus_dpram_frame_init_327 | 29| |297 | dummy |dummy_frame_generator_328 | 179| |298 | crc32_i |osum_crc9d32_331 | 76| |299 | crc9d23_i |osum_crc9d23_332 | 37| |300 | framer |framing_sync_logic_329 | 18| |301 | ram_pointer |tx_ram_pointer_330 | 21| |302 | \bufgen[17].txbuf |ipbus_data_source_13 | 287| |303 | ctrlram |ipbus_dpram_ctrl_init_319 | 12| |304 | dssram |ipbus_dpram_frame_init_320 | 85| |305 | dummy |dummy_frame_generator_321 | 148| |306 | crc32_i |osum_crc9d32_324 | 64| |307 | crc9d23_i |osum_crc9d23_325 | 25| |308 | framer |framing_sync_logic_322 | 18| |309 | ram_pointer |tx_ram_pointer_323 | 21| |310 | \bufgen[18].txbuf |ipbus_data_source_14 | 223| |311 | ctrlram |ipbus_dpram_ctrl_init_312 | 4| |312 | dssram |ipbus_dpram_frame_init_313 | 29| |313 | dummy |dummy_frame_generator_314 | 148| |314 | crc32_i |osum_crc9d32_317 | 64| |315 | crc9d23_i |osum_crc9d23_318 | 25| |316 | framer |framing_sync_logic_315 | 18| |317 | ram_pointer |tx_ram_pointer_316 | 21| |318 | \bufgen[19].txbuf |ipbus_data_source_15 | 255| |319 | ctrlram |ipbus_dpram_ctrl_init_305 | 8| |320 | dssram |ipbus_dpram_frame_init_306 | 57| |321 | dummy |dummy_frame_generator_307 | 148| |322 | crc32_i |osum_crc9d32_310 | 64| |323 | crc9d23_i |osum_crc9d23_311 | 25| |324 | framer |framing_sync_logic_308 | 18| |325 | ram_pointer |tx_ram_pointer_309 | 21| |326 | \bufgen[1].txbuf |ipbus_data_source_16 | 282| |327 | ctrlram |ipbus_dpram_ctrl_init_298 | 12| |328 | dssram |ipbus_dpram_frame_init_299 | 85| |329 | dummy |dummy_frame_generator_300 | 143| |330 | crc32_i |osum_crc9d32_303 | 64| |331 | crc9d23_i |osum_crc9d23_304 | 26| |332 | framer |framing_sync_logic_301 | 18| |333 | ram_pointer |tx_ram_pointer_302 | 21| |334 | \bufgen[20].txbuf |ipbus_data_source_17 | 254| |335 | ctrlram |ipbus_dpram_ctrl_init_291 | 4| |336 | dssram |ipbus_dpram_frame_init_292 | 29| |337 | dummy |dummy_frame_generator_293 | 179| |338 | crc32_i |osum_crc9d32_296 | 76| |339 | crc9d23_i |osum_crc9d23_297 | 37| |340 | framer |framing_sync_logic_294 | 18| |341 | ram_pointer |tx_ram_pointer_295 | 21| |342 | \bufgen[21].txbuf |ipbus_data_source_18 | 287| |343 | ctrlram |ipbus_dpram_ctrl_init_284 | 12| |344 | dssram |ipbus_dpram_frame_init_285 | 85| |345 | dummy |dummy_frame_generator_286 | 148| |346 | crc32_i |osum_crc9d32_289 | 64| |347 | crc9d23_i |osum_crc9d23_290 | 25| |348 | framer |framing_sync_logic_287 | 18| |349 | ram_pointer |tx_ram_pointer_288 | 21| |350 | \bufgen[22].txbuf |ipbus_data_source_19 | 223| |351 | ctrlram |ipbus_dpram_ctrl_init_277 | 4| |352 | dssram |ipbus_dpram_frame_init_278 | 29| |353 | dummy |dummy_frame_generator_279 | 148| |354 | crc32_i |osum_crc9d32_282 | 64| |355 | crc9d23_i |osum_crc9d23_283 | 25| |356 | framer |framing_sync_logic_280 | 18| |357 | ram_pointer |tx_ram_pointer_281 | 21| |358 | \bufgen[23].txbuf |ipbus_data_source_20 | 255| |359 | ctrlram |ipbus_dpram_ctrl_init_270 | 8| |360 | dssram |ipbus_dpram_frame_init_271 | 57| |361 | dummy |dummy_frame_generator_272 | 148| |362 | crc32_i |osum_crc9d32_275 | 64| |363 | crc9d23_i |osum_crc9d23_276 | 25| |364 | framer |framing_sync_logic_273 | 18| |365 | ram_pointer |tx_ram_pointer_274 | 21| |366 | \bufgen[24].txbuf |ipbus_data_source_21 | 254| |367 | ctrlram |ipbus_dpram_ctrl_init_263 | 4| |368 | dssram |ipbus_dpram_frame_init_264 | 29| |369 | dummy |dummy_frame_generator_265 | 179| |370 | crc32_i |osum_crc9d32_268 | 76| |371 | crc9d23_i |osum_crc9d23_269 | 37| |372 | framer |framing_sync_logic_266 | 18| |373 | ram_pointer |tx_ram_pointer_267 | 21| |374 | \bufgen[25].txbuf |ipbus_data_source_22 | 287| |375 | ctrlram |ipbus_dpram_ctrl_init_256 | 12| |376 | dssram |ipbus_dpram_frame_init_257 | 85| |377 | dummy |dummy_frame_generator_258 | 148| |378 | crc32_i |osum_crc9d32_261 | 64| |379 | crc9d23_i |osum_crc9d23_262 | 25| |380 | framer |framing_sync_logic_259 | 18| |381 | ram_pointer |tx_ram_pointer_260 | 21| |382 | \bufgen[26].txbuf |ipbus_data_source_23 | 223| |383 | ctrlram |ipbus_dpram_ctrl_init_249 | 4| |384 | dssram |ipbus_dpram_frame_init_250 | 29| |385 | dummy |dummy_frame_generator_251 | 148| |386 | crc32_i |osum_crc9d32_254 | 64| |387 | crc9d23_i |osum_crc9d23_255 | 25| |388 | framer |framing_sync_logic_252 | 18| |389 | ram_pointer |tx_ram_pointer_253 | 21| |390 | \bufgen[27].txbuf |ipbus_data_source_24 | 255| |391 | ctrlram |ipbus_dpram_ctrl_init_242 | 8| |392 | dssram |ipbus_dpram_frame_init_243 | 57| |393 | dummy |dummy_frame_generator_244 | 148| |394 | crc32_i |osum_crc9d32_247 | 64| |395 | crc9d23_i |osum_crc9d23_248 | 25| |396 | framer |framing_sync_logic_245 | 18| |397 | ram_pointer |tx_ram_pointer_246 | 21| |398 | \bufgen[28].txbuf |ipbus_data_source_25 | 254| |399 | ctrlram |ipbus_dpram_ctrl_init_235 | 4| |400 | dssram |ipbus_dpram_frame_init_236 | 29| |401 | dummy |dummy_frame_generator_237 | 179| |402 | crc32_i |osum_crc9d32_240 | 76| |403 | crc9d23_i |osum_crc9d23_241 | 37| |404 | framer |framing_sync_logic_238 | 18| |405 | ram_pointer |tx_ram_pointer_239 | 21| |406 | \bufgen[29].txbuf |ipbus_data_source_26 | 319| |407 | ctrlram |ipbus_dpram_ctrl_init_228 | 16| |408 | dssram |ipbus_dpram_frame_init_229 | 113| |409 | dummy |dummy_frame_generator_230 | 148| |410 | crc32_i |osum_crc9d32_233 | 64| |411 | crc9d23_i |osum_crc9d23_234 | 25| |412 | framer |framing_sync_logic_231 | 18| |413 | ram_pointer |tx_ram_pointer_232 | 21| |414 | \bufgen[2].txbuf |ipbus_data_source_27 | 218| |415 | ctrlram |ipbus_dpram_ctrl_init_221 | 4| |416 | dssram |ipbus_dpram_frame_init_222 | 29| |417 | dummy |dummy_frame_generator_223 | 143| |418 | crc32_i |osum_crc9d32_226 | 64| |419 | crc9d23_i |osum_crc9d23_227 | 26| |420 | framer |framing_sync_logic_224 | 18| |421 | ram_pointer |tx_ram_pointer_225 | 21| |422 | \bufgen[30].txbuf |ipbus_data_source_28 | 223| |423 | ctrlram |ipbus_dpram_ctrl_init_214 | 4| |424 | dssram |ipbus_dpram_frame_init_215 | 29| |425 | dummy |dummy_frame_generator_216 | 148| |426 | crc32_i |osum_crc9d32_219 | 64| |427 | crc9d23_i |osum_crc9d23_220 | 25| |428 | framer |framing_sync_logic_217 | 18| |429 | ram_pointer |tx_ram_pointer_218 | 21| |430 | \bufgen[31].txbuf |ipbus_data_source_29 | 255| |431 | ctrlram |ipbus_dpram_ctrl_init_207 | 8| |432 | dssram |ipbus_dpram_frame_init_208 | 57| |433 | dummy |dummy_frame_generator_209 | 148| |434 | crc32_i |osum_crc9d32_212 | 64| |435 | crc9d23_i |osum_crc9d23_213 | 25| |436 | framer |framing_sync_logic_210 | 18| |437 | ram_pointer |tx_ram_pointer_211 | 21| |438 | \bufgen[32].txbuf |ipbus_data_source_30 | 254| |439 | ctrlram |ipbus_dpram_ctrl_init_200 | 4| |440 | dssram |ipbus_dpram_frame_init_201 | 29| |441 | dummy |dummy_frame_generator_202 | 179| |442 | crc32_i |osum_crc9d32_205 | 76| |443 | crc9d23_i |osum_crc9d23_206 | 37| |444 | framer |framing_sync_logic_203 | 18| |445 | ram_pointer |tx_ram_pointer_204 | 21| |446 | \bufgen[33].txbuf |ipbus_data_source_31 | 287| |447 | ctrlram |ipbus_dpram_ctrl_init_193 | 12| |448 | dssram |ipbus_dpram_frame_init_194 | 85| |449 | dummy |dummy_frame_generator_195 | 148| |450 | crc32_i |osum_crc9d32_198 | 64| |451 | crc9d23_i |osum_crc9d23_199 | 25| |452 | framer |framing_sync_logic_196 | 18| |453 | ram_pointer |tx_ram_pointer_197 | 21| |454 | \bufgen[34].txbuf |ipbus_data_source_32 | 223| |455 | ctrlram |ipbus_dpram_ctrl_init_186 | 4| |456 | dssram |ipbus_dpram_frame_init_187 | 29| |457 | dummy |dummy_frame_generator_188 | 148| |458 | crc32_i |osum_crc9d32_191 | 64| |459 | crc9d23_i |osum_crc9d23_192 | 25| |460 | framer |framing_sync_logic_189 | 18| |461 | ram_pointer |tx_ram_pointer_190 | 21| |462 | \bufgen[35].txbuf |ipbus_data_source_33 | 255| |463 | ctrlram |ipbus_dpram_ctrl_init_179 | 8| |464 | dssram |ipbus_dpram_frame_init_180 | 57| |465 | dummy |dummy_frame_generator_181 | 148| |466 | crc32_i |osum_crc9d32_184 | 64| |467 | crc9d23_i |osum_crc9d23_185 | 25| |468 | framer |framing_sync_logic_182 | 18| |469 | ram_pointer |tx_ram_pointer_183 | 21| |470 | \bufgen[36].txbuf |ipbus_data_source_34 | 256| |471 | ctrlram |ipbus_dpram_ctrl_init_172 | 4| |472 | dssram |ipbus_dpram_frame_init_173 | 29| |473 | dummy |dummy_frame_generator_174 | 179| |474 | crc32_i |osum_crc9d32_177 | 76| |475 | crc9d23_i |osum_crc9d23_178 | 37| |476 | framer |framing_sync_logic_175 | 20| |477 | ram_pointer |tx_ram_pointer_176 | 21| |478 | \bufgen[37].txbuf |ipbus_data_source_35 | 287| |479 | ctrlram |ipbus_dpram_ctrl_init_165 | 12| |480 | dssram |ipbus_dpram_frame_init_166 | 85| |481 | dummy |dummy_frame_generator_167 | 148| |482 | crc32_i |osum_crc9d32_170 | 64| |483 | crc9d23_i |osum_crc9d23_171 | 25| |484 | framer |framing_sync_logic_168 | 18| |485 | ram_pointer |tx_ram_pointer_169 | 21| |486 | \bufgen[38].txbuf |ipbus_data_source_36 | 223| |487 | ctrlram |ipbus_dpram_ctrl_init_158 | 4| |488 | dssram |ipbus_dpram_frame_init_159 | 29| |489 | dummy |dummy_frame_generator_160 | 148| |490 | crc32_i |osum_crc9d32_163 | 64| |491 | crc9d23_i |osum_crc9d23_164 | 25| |492 | framer |framing_sync_logic_161 | 18| |493 | ram_pointer |tx_ram_pointer_162 | 21| |494 | \bufgen[39].txbuf |ipbus_data_source_37 | 255| |495 | ctrlram |ipbus_dpram_ctrl_init_151 | 8| |496 | dssram |ipbus_dpram_frame_init_152 | 57| |497 | dummy |dummy_frame_generator_153 | 148| |498 | crc32_i |osum_crc9d32_156 | 64| |499 | crc9d23_i |osum_crc9d23_157 | 25| |500 | framer |framing_sync_logic_154 | 18| |501 | ram_pointer |tx_ram_pointer_155 | 21| |502 | \bufgen[3].txbuf |ipbus_data_source_38 | 250| |503 | ctrlram |ipbus_dpram_ctrl_init_144 | 8| |504 | dssram |ipbus_dpram_frame_init_145 | 57| |505 | dummy |dummy_frame_generator_146 | 143| |506 | crc32_i |osum_crc9d32_149 | 64| |507 | crc9d23_i |osum_crc9d23_150 | 26| |508 | framer |framing_sync_logic_147 | 18| |509 | ram_pointer |tx_ram_pointer_148 | 21| |510 | \bufgen[40].txbuf |ipbus_data_source_39 | 254| |511 | ctrlram |ipbus_dpram_ctrl_init_137 | 4| |512 | dssram |ipbus_dpram_frame_init_138 | 29| |513 | dummy |dummy_frame_generator_139 | 179| |514 | crc32_i |osum_crc9d32_142 | 76| |515 | crc9d23_i |osum_crc9d23_143 | 37| |516 | framer |framing_sync_logic_140 | 18| |517 | ram_pointer |tx_ram_pointer_141 | 21| |518 | \bufgen[41].txbuf |ipbus_data_source_40 | 287| |519 | ctrlram |ipbus_dpram_ctrl_init_130 | 12| |520 | dssram |ipbus_dpram_frame_init_131 | 85| |521 | dummy |dummy_frame_generator_132 | 148| |522 | crc32_i |osum_crc9d32_135 | 64| |523 | crc9d23_i |osum_crc9d23_136 | 25| |524 | framer |framing_sync_logic_133 | 18| |525 | ram_pointer |tx_ram_pointer_134 | 21| |526 | \bufgen[42].txbuf |ipbus_data_source_41 | 223| |527 | ctrlram |ipbus_dpram_ctrl_init_123 | 4| |528 | dssram |ipbus_dpram_frame_init_124 | 29| |529 | dummy |dummy_frame_generator_125 | 148| |530 | crc32_i |osum_crc9d32_128 | 64| |531 | crc9d23_i |osum_crc9d23_129 | 25| |532 | framer |framing_sync_logic_126 | 18| |533 | ram_pointer |tx_ram_pointer_127 | 21| |534 | \bufgen[43].txbuf |ipbus_data_source_42 | 255| |535 | ctrlram |ipbus_dpram_ctrl_init_116 | 8| |536 | dssram |ipbus_dpram_frame_init_117 | 57| |537 | dummy |dummy_frame_generator_118 | 148| |538 | crc32_i |osum_crc9d32_121 | 64| |539 | crc9d23_i |osum_crc9d23_122 | 25| |540 | framer |framing_sync_logic_119 | 18| |541 | ram_pointer |tx_ram_pointer_120 | 21| |542 | \bufgen[44].txbuf |ipbus_data_source_43 | 254| |543 | ctrlram |ipbus_dpram_ctrl_init_109 | 4| |544 | dssram |ipbus_dpram_frame_init_110 | 29| |545 | dummy |dummy_frame_generator_111 | 179| |546 | crc32_i |osum_crc9d32_114 | 76| |547 | crc9d23_i |osum_crc9d23_115 | 37| |548 | framer |framing_sync_logic_112 | 18| |549 | ram_pointer |tx_ram_pointer_113 | 21| |550 | \bufgen[45].txbuf |ipbus_data_source_44 | 319| |551 | ctrlram |ipbus_dpram_ctrl_init_102 | 16| |552 | dssram |ipbus_dpram_frame_init_103 | 113| |553 | dummy |dummy_frame_generator_104 | 148| |554 | crc32_i |osum_crc9d32_107 | 64| |555 | crc9d23_i |osum_crc9d23_108 | 25| |556 | framer |framing_sync_logic_105 | 18| |557 | ram_pointer |tx_ram_pointer_106 | 21| |558 | \bufgen[46].txbuf |ipbus_data_source_45 | 223| |559 | ctrlram |ipbus_dpram_ctrl_init_95 | 4| |560 | dssram |ipbus_dpram_frame_init_96 | 29| |561 | dummy |dummy_frame_generator_97 | 148| |562 | crc32_i |osum_crc9d32_100 | 64| |563 | crc9d23_i |osum_crc9d23_101 | 25| |564 | framer |framing_sync_logic_98 | 18| |565 | ram_pointer |tx_ram_pointer_99 | 21| |566 | \bufgen[47].txbuf |ipbus_data_source_46 | 255| |567 | ctrlram |ipbus_dpram_ctrl_init_88 | 8| |568 | dssram |ipbus_dpram_frame_init_89 | 57| |569 | dummy |dummy_frame_generator_90 | 148| |570 | crc32_i |osum_crc9d32_93 | 64| |571 | crc9d23_i |osum_crc9d23_94 | 25| |572 | framer |framing_sync_logic_91 | 18| |573 | ram_pointer |tx_ram_pointer_92 | 21| |574 | \bufgen[4].txbuf |ipbus_data_source_47 | 277| |575 | ctrlram |ipbus_dpram_ctrl_init_81 | 4| |576 | dssram |ipbus_dpram_frame_init_82 | 29| |577 | dummy |dummy_frame_generator_83 | 202| |578 | crc32_i |osum_crc9d32_86 | 76| |579 | crc9d23_i |osum_crc9d23_87 | 38| |580 | framer |framing_sync_logic_84 | 18| |581 | ram_pointer |tx_ram_pointer_85 | 21| |582 | \bufgen[5].txbuf |ipbus_data_source_48 | 282| |583 | ctrlram |ipbus_dpram_ctrl_init_74 | 12| |584 | dssram |ipbus_dpram_frame_init_75 | 85| |585 | dummy |dummy_frame_generator_76 | 143| |586 | crc32_i |osum_crc9d32_79 | 64| |587 | crc9d23_i |osum_crc9d23_80 | 26| |588 | framer |framing_sync_logic_77 | 18| |589 | ram_pointer |tx_ram_pointer_78 | 21| |590 | \bufgen[6].txbuf |ipbus_data_source_49 | 218| |591 | ctrlram |ipbus_dpram_ctrl_init_67 | 4| |592 | dssram |ipbus_dpram_frame_init_68 | 29| |593 | dummy |dummy_frame_generator_69 | 143| |594 | crc32_i |osum_crc9d32_72 | 64| |595 | crc9d23_i |osum_crc9d23_73 | 26| |596 | framer |framing_sync_logic_70 | 18| |597 | ram_pointer |tx_ram_pointer_71 | 21| |598 | \bufgen[7].txbuf |ipbus_data_source_50 | 250| |599 | ctrlram |ipbus_dpram_ctrl_init_60 | 8| |600 | dssram |ipbus_dpram_frame_init_61 | 57| |601 | dummy |dummy_frame_generator_62 | 143| |602 | crc32_i |osum_crc9d32_65 | 64| |603 | crc9d23_i |osum_crc9d23_66 | 26| |604 | framer |framing_sync_logic_63 | 18| |605 | ram_pointer |tx_ram_pointer_64 | 21| |606 | \bufgen[8].txbuf |ipbus_data_source_51 | 270| |607 | ctrlram |ipbus_dpram_ctrl_init_53 | 4| |608 | dssram |ipbus_dpram_frame_init_54 | 29| |609 | dummy |dummy_frame_generator_55 | 195| |610 | crc32_i |osum_crc9d32_58 | 76| |611 | crc9d23_i |osum_crc9d23_59 | 38| |612 | framer |framing_sync_logic_56 | 18| |613 | ram_pointer |tx_ram_pointer_57 | 21| |614 | \bufgen[9].txbuf |ipbus_data_source_52 | 282| |615 | ctrlram |ipbus_dpram_ctrl_init | 12| |616 | dssram |ipbus_dpram_frame_init | 85| |617 | dummy |dummy_frame_generator | 143| |618 | crc32_i |osum_crc9d32 | 64| |619 | crc9d23_i |osum_crc9d23 | 26| |620 | framer |framing_sync_logic | 18| |621 | ram_pointer |tx_ram_pointer | 21| |622 | fabric_decode |ipbus_fabric_branch__parameterized0 | 25| |623 | xcvr_control |ipbus_dss_xcvr_control | 660| |624 | \reggen[0].xcvr_regs |ipbus_xcvr_control | 183| |625 | xcvr_control |ipbus_ctrlreg_v__parameterized1_5 | 131| |626 | \reggen[1].xcvr_regs |ipbus_xcvr_control_0 | 147| |627 | xcvr_control |ipbus_ctrlreg_v__parameterized1_4 | 95| |628 | \reggen[2].xcvr_regs |ipbus_xcvr_control_1 | 183| |629 | xcvr_control |ipbus_ctrlreg_v__parameterized1_3 | 131| |630 | \reggen[3].xcvr_regs |ipbus_xcvr_control_2 | 147| |631 | xcvr_control |ipbus_ctrlreg_v__parameterized1 | 95| +------+-----------------------------------+---------------------------------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:04:18 ; elapsed = 00:05:02 . Memory (MB): peak = 3010.988 ; gain = 988.668 ; free physical = 2612 ; free virtual = 20883 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 120 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:04:01 ; elapsed = 00:04:43 . Memory (MB): peak = 3010.988 ; gain = 825.262 ; free physical = 2662 ; free virtual = 20933 Synthesis Optimization Complete : Time (s): cpu = 00:04:18 ; elapsed = 00:05:02 . Memory (MB): peak = 3010.992 ; gain = 988.668 ; free physical = 2662 ; free virtual = 20933 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3010.992 ; gain = 0.000 ; free physical = 2707 ; free virtual = 20978 INFO: [Netlist 29-17] Analyzing 2170 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3022.613 ; gain = 0.000 ; free physical = 2640 ; free virtual = 20916 INFO: [Project 1-111] Unisim Transformation Summary: A total of 14 instances were transformed. IBUFGDS => IBUFDS: 2 instances MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 10 instances SRL16 => SRL16E: 1 instance INFO: [Common 17-83] Releasing license: Synthesis 980 Infos, 233 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:04:55 ; elapsed = 00:06:09 . Memory (MB): peak = 3022.613 ; gain = 1353.547 ; free physical = 2848 ; free virtual = 21124 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3022.613 ; gain = 0.000 ; free physical = 2848 ; free virtual = 21124 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/synth_1/top_FTM_DSS.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 3022.617 ; gain = 0.004 ; free physical = 2849 ; free virtual = 21133 INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_synth.rpt -pb top_FTM_DSS_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 17:31:25 2022...