*** Running vivado with args -log mac_fifo_axi4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mac_fifo_axi4.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source mac_fifo_axi4.tcl -notrace Command: synth_design -top mac_fifo_axi4 -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24053 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:01:02 . Memory (MB): peak = 2106.211 ; gain = 200.684 ; free physical = 523 ; free virtual = 18686 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'mac_fifo_axi4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/synth/mac_fifo_axi4.vhd:77] Parameter C_COMMON_CLOCK bound to: 0 - type: integer Parameter C_SELECT_XPM bound to: 0 - type: integer Parameter C_COUNT_TYPE bound to: 0 - type: integer Parameter C_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_DEFAULT_VALUE bound to: BlankString - type: string Parameter C_DIN_WIDTH bound to: 18 - type: integer Parameter C_DOUT_RST_VAL bound to: 0 - type: string Parameter C_DOUT_WIDTH bound to: 18 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer Parameter C_HAS_BACKUP bound to: 0 - type: integer Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_INT_CLK bound to: 0 - type: integer Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer Parameter C_HAS_OVERFLOW bound to: 0 - type: integer Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_RD_RST bound to: 0 - type: integer Parameter C_HAS_RST bound to: 1 - type: integer Parameter C_HAS_SRST bound to: 0 - type: integer Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer Parameter C_HAS_VALID bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 0 - type: integer Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_WR_RST bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer Parameter C_MEMORY_TYPE bound to: 1 - type: integer Parameter C_MIF_FILE_NAME bound to: BlankString - type: string Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer Parameter C_OVERFLOW_LOW bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer Parameter C_PRELOAD_REGS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE bound to: 4kx4 - type: string Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 1022 - type: integer Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 1021 - type: integer Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer Parameter C_RD_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_RD_DEPTH bound to: 1024 - type: integer Parameter C_RD_FREQ bound to: 1 - type: integer Parameter C_RD_PNTR_WIDTH bound to: 10 - type: integer Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer Parameter C_USE_DOUT_RST bound to: 1 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer Parameter C_VALID_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_WR_DEPTH bound to: 1024 - type: integer Parameter C_WR_FREQ bound to: 1 - type: integer Parameter C_WR_PNTR_WIDTH bound to: 10 - type: integer Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer Parameter C_MSGON_VAL bound to: 0 - type: integer Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_INTERFACE_TYPE bound to: 1 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer Parameter C_HAS_MASTER_CE bound to: 0 - type: integer Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer Parameter C_HAS_AXIS_TID bound to: 0 - type: integer Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer Parameter C_HAS_AXIS_TLAST bound to: 1 - type: integer Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer Parameter C_WACH_TYPE bound to: 0 - type: integer Parameter C_WDCH_TYPE bound to: 0 - type: integer Parameter C_WRCH_TYPE bound to: 0 - type: integer Parameter C_RACH_TYPE bound to: 0 - type: integer Parameter C_RDCH_TYPE bound to: 0 - type: integer Parameter C_AXIS_TYPE bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 12 - type: integer Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 11 - type: integer Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 12 - type: integer Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 12 - type: integer Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 11 - type: integer Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 12 - type: integer Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 512x36 - type: string Parameter C_USE_ECC_WACH bound to: 0 - type: integer Parameter C_USE_ECC_WDCH bound to: 0 - type: integer Parameter C_USE_ECC_WRCH bound to: 0 - type: integer Parameter C_USE_ECC_RACH bound to: 0 - type: integer Parameter C_USE_ECC_RDCH bound to: 0 - type: integer Parameter C_USE_ECC_AXIS bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_AXIS bound to: 10 - type: integer Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_AXIS bound to: 16 - type: integer Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_AXIS bound to: 4 - type: integer Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 15 - type: integer Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 13 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1021 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 13 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 13 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1021 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 13 - type: integer Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer INFO: [Synth 8-3491] module 'fifo_generator_v13_2_5' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38604' bound to instance 'U0' of component 'fifo_generator_v13_2_5' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/synth/mac_fifo_axi4.vhd:555] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1226] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (1#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (2#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (7#1) [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-256] done synthesizing module 'mac_fifo_axi4' (22#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/synth/mac_fifo_axi4.vhd:77] WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_FULL_I WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_FULL_I WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_EMPTY_I WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_EMPTY_I WARNING: [Synth 8-3331] design output_blk has unconnected port WR_ACK_I WARNING: [Synth 8-3331] design output_blk has unconnected port VALID_I WARNING: [Synth 8-3331] design output_blk has unconnected port OVERFLOW_I WARNING: [Synth 8-3331] design output_blk has unconnected port UNDERFLOW_I WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[4] WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[3] WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[2] WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[1] WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[0] WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[4] WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[3] WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[2] WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[1] WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[0] WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[4] WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[3] WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[2] WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[1] WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[0] WARNING: [Synth 8-3331] design output_blk has unconnected port SBITERR_I WARNING: [Synth 8-3331] design output_blk has unconnected port DBITERR_I WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_RST WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SRST WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SAFETY_CKT_WR_RST WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[3] WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[2] WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[1] WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[0] WARNING: [Synth 8-3331] design wr_bin_cntr has unconnected port SRST WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_EN_INTO_LOGIC WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_INTO_LOGIC WARNING: [Synth 8-3331] design wr_logic has unconnected port RD_EN WARNING: [Synth 8-3331] design wr_logic has unconnected port SRST_FULL_FF WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_BUSY WARNING: [Synth 8-3331] design wr_logic has unconnected port EMPTY WARNING: [Synth 8-3331] design wr_logic has unconnected port RAM_RD_EN WARNING: [Synth 8-3331] design wr_logic has unconnected port ALMOST_EMPTY WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[3] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[2] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[1] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[0] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[3] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[2] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[1] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[0] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[3] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[2] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[1] WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[0] WARNING: [Synth 8-3331] design rd_fwft has unconnected port SRST WARNING: [Synth 8-3331] design rd_fwft has unconnected port SAFETY_CKT_RD_RST WARNING: [Synth 8-3331] design rd_fwft has unconnected port RAM_ALMOST_EMPTY WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SRST WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SAFETY_CKT_RD_RST WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[3] WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[2] WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[1] WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[0] WARNING: [Synth 8-3331] design rd_bin_cntr has unconnected port SRST WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_EN_INTO_LOGIC WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_INTO_LOGIC WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_BUSY WARNING: [Synth 8-3331] design rd_logic has unconnected port RAM_WR_EN WARNING: [Synth 8-3331] design rd_logic has unconnected port RST_FULL_FF WARNING: [Synth 8-3331] design rd_logic has unconnected port ALMOST_FULL_FB WARNING: [Synth 8-3331] design rd_logic has unconnected port FULL WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[3] WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[2] WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[1] WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[0] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[3] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[2] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[1] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[0] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[3] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[2] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[1] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[0] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[3] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[2] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[1] WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[0] WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port WR_RST WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port RD_RST WARNING: [Synth 8-3331] design dmem has unconnected port SRST WARNING: [Synth 8-3331] design memory has unconnected port FAB_REGOUT_EN WARNING: [Synth 8-3331] design memory has unconnected port SFT_RST WARNING: [Synth 8-3331] design memory has unconnected port SRST WARNING: [Synth 8-3331] design memory has unconnected port SAFETY_CKT_RD_RST WARNING: [Synth 8-3331] design memory has unconnected port SLEEP WARNING: [Synth 8-3331] design memory has unconnected port INJECTDBITERR WARNING: [Synth 8-3331] design memory has unconnected port INJECTSBITERR WARNING: [Synth 8-3331] design input_blk has unconnected port CLK WARNING: [Synth 8-3331] design input_blk has unconnected port INT_CLK WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[3] WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[2] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:26 ; elapsed = 00:01:53 . Memory (MB): peak = 2260.934 ; gain = 355.406 ; free physical = 959 ; free virtual = 19120 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:01:55 . Memory (MB): peak = 2260.934 ; gain = 355.406 ; free physical = 923 ; free virtual = 19084 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:01:55 . Memory (MB): peak = 2260.934 ; gain = 355.406 ; free physical = 923 ; free virtual = 19084 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2260.934 ; gain = 0.000 ; free physical = 909 ; free virtual = 19069 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_ooc.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/mac_fifo_axi4_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/mac_fifo_axi4_synth_1/dont_touch.xdc] Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'U0' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mac_fifo_axi4_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/mac_fifo_axi4_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mac_fifo_axi4_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/mac_fifo_axi4_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mac_fifo_axi4_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/mac_fifo_axi4_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2365.758 ; gain = 0.000 ; free physical = 703 ; free virtual = 18864 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2365.758 ; gain = 0.000 ; free physical = 701 ; free virtual = 18861 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:36 ; elapsed = 00:02:16 . Memory (MB): peak = 2365.758 ; gain = 460.230 ; free physical = 432 ; free virtual = 18593 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:36 ; elapsed = 00:02:16 . Memory (MB): peak = 2365.758 ; gain = 460.230 ; free physical = 432 ; free virtual = 18593 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/mac_fifo_axi4_synth_1/dont_touch.xdc, line 9). Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:02:16 . Memory (MB): peak = 2365.758 ; gain = 460.230 ; free physical = 431 ; free virtual = 18592 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:37 ; elapsed = 00:02:16 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 412 ; free virtual = 18573 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 2 +---XORs : 2 Input 4 Bit XORs := 2 2 Input 1 Bit XORs := 22 +---Registers : 10 Bit Registers := 2 4 Bit Registers := 16 2 Bit Registers := 4 1 Bit Registers := 17 +---Muxes : 2 Input 2 Bit Muxes := 4 5 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module xpm_cdc_async_rst Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 Module xpm_cdc_single Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 Module reset_blk_ramfifo Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 7 Module dmem Detailed RTL Component Info : +---Registers : 10 Bit Registers := 1 Module memory Detailed RTL Component Info : +---Registers : 10 Bit Registers := 1 Module xpm_cdc_gray Detailed RTL Component Info : +---XORs : 2 Input 4 Bit XORs := 1 2 Input 1 Bit XORs := 3 +---Registers : 4 Bit Registers := 4 Module rd_bin_cntr Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 2 Module compare Detailed RTL Component Info : +---XORs : 2 Input 1 Bit XORs := 4 Module rd_status_flags_as Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 Module rd_fwft Detailed RTL Component Info : +---Registers : 2 Bit Registers := 1 1 Bit Registers := 6 +---Muxes : 2 Input 2 Bit Muxes := 4 5 Input 2 Bit Muxes := 1 3 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 2 Module wr_bin_cntr Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 4 Bit Registers := 3 Module wr_status_flags_as Detailed RTL Component Info : +---Registers : 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:02:18 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 390 ; free virtual = 18554 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------+------------------------------------------------------------------------------------------+----------------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+------------------------------------------------------------------------------------------+----------------+----------------------+-------------+ |U0 | inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 10 | RAM32M x 2 | +------------+------------------------------------------------------------------------------------------+----------------+----------------------+-------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:47 ; elapsed = 00:02:37 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 115 ; free virtual = 18280 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:48 ; elapsed = 00:02:37 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 150 ; free virtual = 18276 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+------------------------------------------------------------------------------------------+----------------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+------------------------------------------------------------------------------------------+----------------+----------------------+-------------+ |U0 | inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 10 | RAM32M x 2 | +------------+------------------------------------------------------------------------------------------+----------------+----------------------+-------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:48 ; elapsed = 00:02:37 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 148 ; free virtual = 18274 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 223 ; free virtual = 18350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 223 ; free virtual = 18350 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 223 ; free virtual = 18350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 222 ; free virtual = 18350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 222 ; free virtual = 18350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 222 ; free virtual = 18350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |LUT1 | 16| |2 |LUT2 | 13| |3 |LUT3 | 6| |4 |LUT4 | 13| |5 |LUT5 | 2| |6 |LUT6 | 5| |7 |RAM32M | 2| |8 |FDCE | 26| |9 |FDPE | 23| |10 |FDRE | 60| +------+-------+------+ Report Instance Areas: +------+-------------------------------------------------------------------------------------+-----------------------------+------+ | |Instance |Module |Cells | +------+-------------------------------------------------------------------------------------+-----------------------------+------+ |1 |top | | 166| |2 | U0 |fifo_generator_v13_2_5 | 166| |3 | inst_fifo_gen |fifo_generator_v13_2_5_synth | 166| |4 | \gaxis_fifo.gaxisf.axisf |fifo_generator_top | 166| |5 | \grf.rf |fifo_generator_ramfifo | 166| |6 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 46| |7 | wr_pntr_cdc_inst |xpm_cdc_gray__2 | 22| |8 | rd_pntr_cdc_inst |xpm_cdc_gray | 22| |9 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 34| |10 | \gr1.gr1_int.rfwft |rd_fwft | 17| |11 | \gras.rsts |rd_status_flags_as | 2| |12 | rpntr |rd_bin_cntr | 15| |13 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 23| |14 | \gwas.wsts |wr_status_flags_as | 5| |15 | wpntr |wr_bin_cntr | 18| |16 | \gntv_or_sync_fifo.mem |memory | 22| |17 | \gdm.dm_gen.dm |dmem | 12| |18 | rstblk |reset_blk_ramfifo | 41| |19 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst |xpm_cdc_async_rst__1 | 2| |20 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst |xpm_cdc_async_rst | 2| |21 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd |xpm_cdc_single__2 | 4| |22 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr |xpm_cdc_single | 4| +------+-------------------------------------------------------------------------------------+-----------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 222 ; free virtual = 18349 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 468 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:48 ; elapsed = 00:02:35 . Memory (MB): peak = 2365.762 ; gain = 355.410 ; free physical = 274 ; free virtual = 18401 Synthesis Optimization Complete : Time (s): cpu = 00:00:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2365.762 ; gain = 460.234 ; free physical = 274 ; free virtual = 18401 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2365.762 ; gain = 0.000 ; free physical = 268 ; free virtual = 18395 INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 5 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2365.762 ; gain = 0.000 ; free physical = 266 ; free virtual = 18393 INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances INFO: [Common 17-83] Releasing license: Synthesis 28 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:05 ; elapsed = 00:03:06 . Memory (MB): peak = 2365.762 ; gain = 745.246 ; free physical = 393 ; free virtual = 18520 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2365.762 ; gain = 0.000 ; free physical = 393 ; free virtual = 18520 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/mac_fifo_axi4_synth_1/mac_fifo_axi4.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP mac_fifo_axi4, cache-ID = 23ba5a8dba672343 INFO: [Coretcl 2-1174] Renamed 21 cell refs. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2389.773 ; gain = 0.000 ; free physical = 357 ; free virtual = 18484 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/mac_fifo_axi4_synth_1/mac_fifo_axi4.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file mac_fifo_axi4_utilization_synth.rpt -pb mac_fifo_axi4_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Thu Jan 6 01:31:03 2022...