Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
| Date             : Thu Jan  6 02:45:46 2022
| Host             : hog-vm0.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
| Command          : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
| Design           : top_FTM_DSS
| Device           : xc7vx415tffg1158-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------------------------------

Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 19.787       |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 19.060       |
| Device Static (W)        | 0.727        |
| Effective TJA (C/W)      | 1.4          |
| Max Ambient (C)          | 57.2         |
| Junction Temperature (C) | 52.8         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.566 |      213 |       --- |             --- |
| Slice Logic              |     0.250 |    60681 |       --- |             --- |
|   LUT as Logic           |     0.227 |    21264 |    257600 |            8.25 |
|   Register               |     0.015 |    29542 |    515200 |            5.73 |
|   CARRY4                 |     0.008 |     1907 |     64400 |            2.96 |
|   F7/F8 Muxes            |    <0.001 |      672 |    257600 |            0.26 |
|   LUT as Shift Register  |    <0.001 |       87 |    104400 |            0.08 |
|   LUT as Distributed RAM |    <0.001 |       24 |    104400 |            0.02 |
|   Others                 |     0.000 |     3725 |       --- |             --- |
| Signals                  |     0.535 |    49428 |       --- |             --- |
| Block RAM                |     3.460 |    643.5 |       880 |           73.13 |
| MMCM                     |     0.106 |        1 |        12 |            8.33 |
| I/O                      |     0.242 |       61 |       350 |           17.43 |
| GTH                      |    13.900 |       48 |       --- |             --- |
| XADC                     |    <0.001 |        1 |       --- |             --- |
| Static Power             |     0.727 |          |           |                 |
| Total                    |    19.787 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     6.883 |       6.490 |      0.393 |
| Vccaux    |       1.800 |     0.125 |       0.083 |      0.042 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.105 |       0.104 |      0.001 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.331 |       0.278 |      0.052 |
| MGTAVcc   |       1.000 |     9.186 |       9.056 |      0.130 |
| MGTAVtt   |       1.200 |     2.257 |       2.225 |      0.032 |
| MGTVccaux |       1.800 |     0.127 |       0.127 |      0.000 |
| MGTZVccl  |       1.075 |     0.000 |       0.000 |      0.000 |
| MGTZAVcc  |       1.075 |     0.000 |       0.000 |      0.000 |
| MGTZVcch  |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 1.4                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 2.4                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+---------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+-----------------+
| Clock                                                                                                                     | Domain                                                                                                                    | Constraint (ns) |
+---------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+-----------------+
| Q114_REFCLK1_P                                                                                                            | Q114_REFCLK1_P                                                                                                            |             3.6 |
| Q115_REFCLK1_P                                                                                                            | Q115_REFCLK1_P                                                                                                            |             3.6 |
| Q116_REFCLK1_P                                                                                                            | Q116_REFCLK1_P                                                                                                            |             3.6 |
| Q117_REFCLK1_P                                                                                                            | Q117_REFCLK1_P                                                                                                            |             3.6 |
| Q118_REFCLK1_P                                                                                                            | Q118_REFCLK1_P                                                                                                            |             3.6 |
| Q119_REFCLK1_P                                                                                                            | Q119_REFCLK1_P                                                                                                            |             3.6 |
| Q214_REFCLK1_P                                                                                                            | Q214_REFCLK1_P                                                                                                            |             3.6 |
| Q215_REFCLK1_P                                                                                                            | Q215_REFCLK1_P                                                                                                            |             3.6 |
| Q216_REFCLK1_P                                                                                                            | Q216_REFCLK1_P                                                                                                            |             3.6 |
| Q217_REFCLK1_P                                                                                                            | Q217_REFCLK1_P                                                                                                            |             3.6 |
| Q218_REFCLK1_P                                                                                                            | Q218_REFCLK1_P                                                                                                            |             3.6 |
| clk_125_i                                                                                                                 | clocks/clk_125_i                                                                                                          |             8.0 |
| clk_ipb_i                                                                                                                 | clocks/clk_ipb_i                                                                                                          |            32.0 |
| clkfbout                                                                                                                  | clocks/clkfbout                                                                                                           |             8.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK                                | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/tck_bs                                                      |            33.0 |
| flash_spi_clk                                                                                                             | slaves/spi_flash/spi_clk                                                                                                  |            64.0 |
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_rxoutclk_out |             3.6 |
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_txoutclk_out |             3.6 |
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_rxoutclk_out |             3.6 |
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_txoutclk_out |             3.6 |
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_rxoutclk_out |             3.6 |
| mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_txoutclk_out |             3.6 |
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_rxoutclk_out |             3.6 |
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_txoutclk_out |             3.6 |
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_rxoutclk_out |             3.6 |
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_txoutclk_out |             3.6 |
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_rxoutclk_out |             3.6 |
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_txoutclk_out |             3.6 |
| mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_rxoutclk_out |             3.6 |
| mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_txoutclk_out |             3.6 |
| mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_rxoutclk_out |             3.6 |
| mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_txoutclk_out |             3.6 |
| mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_rxoutclk_out |             3.6 |
| mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_txoutclk_out |             3.6 |
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_rxoutclk_out |             3.6 |
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt0_DSS_3Quads_11g2_i/gt0_txoutclk_out |             3.6 |
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_rxoutclk_out |             3.6 |
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gt4_txoutclk_out |             3.6 |
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/RXOUTCLK | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_rxoutclk_out |             3.6 |
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK | mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gt8_txoutclk_out |             3.6 |
| sysclk                                                                                                                    | sysclk_p                                                                                                                  |             8.0 |
| ttc_clk                                                                                                                   | ttc_clk_p                                                                                                                 |            24.9 |
+---------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+----------------------------------+-----------+
| Name                             | Power (W) |
+----------------------------------+-----------+
| top_FTM_DSS                      |    19.060 |
|   clocks                         |     0.112 |
|   dbg_hub                        |     0.003 |
|     inst                         |     0.003 |
|       BSCANID.u_xsdbm_id         |     0.003 |
|   ipbus                          |     0.066 |
|     trans                        |     0.027 |
|       iface                      |     0.004 |
|       sm                         |     0.023 |
|     udp_if                       |     0.040 |
|       IPADDR                     |     0.001 |
|       internal_ram               |     0.002 |
|       ipbus_rx_ram               |     0.006 |
|       ipbus_tx_ram               |     0.008 |
|       payload                    |     0.002 |
|       rx_byte_sum                |     0.001 |
|       rx_packet_parser           |     0.003 |
|       status                     |     0.001 |
|       status_buffer              |     0.004 |
|       tx_main                    |     0.004 |
|       tx_ram_selector            |     0.001 |
|       tx_transactor              |     0.002 |
|   mgts_114_116                   |     3.551 |
|     DSS_3Quads_11g2_support_i    |     3.551 |
|       DSS_3Quads_11g2_init_i     |     3.548 |
|       gt_usrclk_source           |     0.002 |
|   mgts_117_119                   |     3.546 |
|     DSS_3Quads_11g2_support_i    |     3.546 |
|       DSS_3Quads_11g2_init_i     |     3.542 |
|       gt_usrclk_source           |     0.004 |
|   mgts_214_216                   |     3.539 |
|     DSS_3Quads_11g2_support_i    |     3.539 |
|       DSS_3Quads_11g2_init_i     |     3.536 |
|       gt_usrclk_source           |     0.002 |
|   mgts_217_219                   |     3.542 |
|     DSS_3Quads_11g2_support_i    |     3.542 |
|       DSS_3Quads_11g2_init_i     |     3.538 |
|       gt_usrclk_source           |     0.003 |
|   slaves                         |     4.270 |
|     buffer_control               |     0.006 |
|       bcr_delays                 |     0.006 |
|     monitoring                   |     0.002 |
|       adc_inst                   |     0.002 |
|     rx_bufs                      |     0.806 |
|       bufgen[0].rxbuf            |     0.067 |
|       bufgen[10].rxbuf           |     0.066 |
|       bufgen[11].rxbuf           |     0.067 |
|       bufgen[1].rxbuf            |     0.067 |
|       bufgen[2].rxbuf            |     0.066 |
|       bufgen[3].rxbuf            |     0.067 |
|       bufgen[4].rxbuf            |     0.068 |
|       bufgen[5].rxbuf            |     0.068 |
|       bufgen[6].rxbuf            |     0.067 |
|       bufgen[7].rxbuf            |     0.067 |
|       bufgen[8].rxbuf            |     0.068 |
|       bufgen[9].rxbuf            |     0.068 |
|     rx_error_monitors            |     0.078 |
|       channel_gen[0].counters    |     0.002 |
|       channel_gen[0].data_check  |     0.004 |
|       channel_gen[10].counters   |     0.002 |
|       channel_gen[10].data_check |     0.004 |
|       channel_gen[11].counters   |     0.002 |
|       channel_gen[11].data_check |     0.004 |
|       channel_gen[1].counters    |     0.002 |
|       channel_gen[1].data_check  |     0.004 |
|       channel_gen[2].counters    |     0.002 |
|       channel_gen[2].data_check  |     0.005 |
|       channel_gen[3].counters    |     0.002 |
|       channel_gen[3].data_check  |     0.004 |
|       channel_gen[4].counters    |     0.002 |
|       channel_gen[4].data_check  |     0.005 |
|       channel_gen[5].counters    |     0.002 |
|       channel_gen[5].data_check  |     0.004 |
|       channel_gen[6].counters    |     0.002 |
|       channel_gen[6].data_check  |     0.004 |
|       channel_gen[7].counters    |     0.002 |
|       channel_gen[7].data_check  |     0.004 |
|       channel_gen[8].counters    |     0.002 |
|       channel_gen[8].data_check  |     0.005 |
|       channel_gen[9].counters    |     0.002 |
|       channel_gen[9].data_check  |     0.005 |
|     spi_flash                    |     0.003 |
|       spi_dpram_out              |     0.001 |
|     tx_bufs                      |     3.373 |
|       bufgen[0].txbuf            |     0.073 |
|       bufgen[10].txbuf           |     0.074 |
|       bufgen[11].txbuf           |     0.074 |
|       bufgen[12].txbuf           |     0.074 |
|       bufgen[13].txbuf           |     0.071 |
|       bufgen[14].txbuf           |     0.073 |
|       bufgen[15].txbuf           |     0.073 |
|       bufgen[16].txbuf           |     0.070 |
|       bufgen[17].txbuf           |     0.070 |
|       bufgen[18].txbuf           |     0.070 |
|       bufgen[19].txbuf           |     0.070 |
|       bufgen[1].txbuf            |     0.073 |
|       bufgen[20].txbuf           |     0.069 |
|       bufgen[21].txbuf           |     0.071 |
|       bufgen[22].txbuf           |     0.070 |
|       bufgen[23].txbuf           |     0.070 |
|       bufgen[24].txbuf           |     0.068 |
|       bufgen[25].txbuf           |     0.068 |
|       bufgen[26].txbuf           |     0.068 |
|       bufgen[27].txbuf           |     0.068 |
|       bufgen[28].txbuf           |     0.069 |
|       bufgen[29].txbuf           |     0.068 |
|       bufgen[2].txbuf            |     0.073 |
|       bufgen[30].txbuf           |     0.068 |
|       bufgen[31].txbuf           |     0.067 |
|       bufgen[32].txbuf           |     0.068 |
|       bufgen[33].txbuf           |     0.067 |
|       bufgen[34].txbuf           |     0.068 |
|       bufgen[35].txbuf           |     0.068 |
|       bufgen[36].txbuf           |     0.069 |
|       bufgen[37].txbuf           |     0.067 |
|       bufgen[38].txbuf           |     0.068 |
|       bufgen[39].txbuf           |     0.068 |
|       bufgen[3].txbuf            |     0.073 |
|       bufgen[40].txbuf           |     0.070 |
|       bufgen[41].txbuf           |     0.068 |
|       bufgen[42].txbuf           |     0.068 |
|       bufgen[43].txbuf           |     0.068 |
|       bufgen[44].txbuf           |     0.069 |
|       bufgen[45].txbuf           |     0.069 |
|       bufgen[46].txbuf           |     0.070 |
|       bufgen[47].txbuf           |     0.069 |
|       bufgen[4].txbuf            |     0.075 |
|       bufgen[5].txbuf            |     0.075 |
|       bufgen[6].txbuf            |     0.072 |
|       bufgen[7].txbuf            |     0.074 |
|       bufgen[8].txbuf            |     0.075 |
|       bufgen[9].txbuf            |     0.075 |
|     xcvr_control                 |     0.002 |
+----------------------------------+-----------+