*** Running vivado
    with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_Control.tcl -notrace
Command: link_design -top top_FTM_Control -part xc7k325tffg900-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx.dcp' for cell 'pll_sync_reset'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii.dcp' for cell 'eth/emac0'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_rx.dcp' for cell 'mgt_ttcinfo/rx_data'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.dcp' for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i'
Netlist sorting complete. Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2020.551 ; gain = 0.000 ; free physical = 3364 ; free virtual = 21625
INFO: [Netlist 29-17] Analyzing 1472 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: mgt_ttcinfo/rx_data UUID: 2e216d50-fdcc-5e22-b690-e434f5351049 
INFO: [Chipscope 16-324] Core: mgt_ttcinfo/tx_data UUID: 5b89df68-5880-5164-8735-ef82a233b4c0 
INFO: [Chipscope 16-324] Core: pll_sync_reset UUID: 93b37abd-9bf1-5b91-b254-f9275f803806 
INFO: [Chipscope 16-324] Core: slaves/ttc_info/ttcin/ttc_sink UUID: 40ec53cc-f74b-5d06-9bbf-5235d0ce3e6b 
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'pll_sync_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'pll_sync_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'pll_sync_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'pll_sync_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xdc] for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xdc] for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4]
get_clocks: Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 2733.801 ; gain = 554.055 ; free physical = 2773 ; free virtual = 21041
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:48]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/ttcinfo_mgt.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/ttcinfo_mgt.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0'
INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:40]
INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:41]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2767.871 ; gain = 0.000 ; free physical = 2785 ; free virtual = 21052
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 272 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 212 instances
  IOBUF => IOBUF (IBUF, OBUFT): 4 instances
  OBUFDS => OBUFDS: 26 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances

21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:42 ; elapsed = 00:01:11 . Memory (MB): peak = 2767.871 ; gain = 1107.098 ; free physical = 2785 ; free virtual = 21052
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xci
Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7k325t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:01 . Memory (MB): peak = 2775.875 ; gain = 8.000 ; free physical = 2771 ; free virtual = 21050

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 205bbd122

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2775.875 ; gain = 0.000 ; free physical = 2742 ; free virtual = 21023

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2902.742 ; gain = 0.000 ; free physical = 2547 ; free virtual = 20851
Phase 1 Generate And Synthesize Debug Cores | Checksum: 204ddac6e

Time (s): cpu = 00:02:03 ; elapsed = 00:03:58 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2547 ; free virtual = 20851

Phase 2 Retarget
INFO: [Opt 31-138] Pushed 3 inverter(s) to 6 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 2 Retarget | Checksum: 22f1404c4

Time (s): cpu = 00:02:06 ; elapsed = 00:04:01 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2573 ; free virtual = 20877
INFO: [Opt 31-389] Phase Retarget created 19 cells and removed 57 cells
INFO: [Opt 31-1021] In phase Retarget, 170 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 3 Constant propagation
INFO: [Opt 31-138] Pushed 1 inverter(s) to 11 load pin(s).
Phase 3 Constant propagation | Checksum: 263879e51

Time (s): cpu = 00:02:07 ; elapsed = 00:04:02 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2573 ; free virtual = 20877
INFO: [Opt 31-389] Phase Constant propagation created 121 cells and removed 1128 cells
INFO: [Opt 31-1021] In phase Constant propagation, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Sweep
Phase 4 Sweep | Checksum: 195df4114

Time (s): cpu = 00:02:09 ; elapsed = 00:04:03 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2571 ; free virtual = 20875
INFO: [Opt 31-389] Phase Sweep created 5 cells and removed 388 cells
INFO: [Opt 31-1021] In phase Sweep, 2233 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 BUFG optimization
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
Phase 5 BUFG optimization | Checksum: 195df4114

Time (s): cpu = 00:02:09 ; elapsed = 00:04:04 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2572 ; free virtual = 20876
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 6 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 6 Shift Register Optimization | Checksum: 1fd44cbd7

Time (s): cpu = 00:02:10 ; elapsed = 00:04:05 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2572 ; free virtual = 20876
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 7 Post Processing Netlist
Phase 7 Post Processing Netlist | Checksum: 1228a95fe

Time (s): cpu = 00:02:10 ; elapsed = 00:04:05 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2572 ; free virtual = 20876
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 112 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              19  |              57  |                                            170  |
|  Constant propagation         |             121  |            1128  |                                             99  |
|  Sweep                        |               5  |             388  |                                           2233  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                            112  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2902.742 ; gain = 0.000 ; free physical = 2572 ; free virtual = 20876
Ending Logic Optimization Task | Checksum: 1a7f7df19

Time (s): cpu = 00:02:11 ; elapsed = 00:04:05 . Memory (MB): peak = 2902.742 ; gain = 33.871 ; free physical = 2572 ; free virtual = 20876

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.045 | TNS=0.000 |
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 26 BRAM(s) out of a total of 325 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 144 WE to EN ports
Number of BRAM Ports augmented: 52 newly gated: 152 Total Ports: 650
Ending PowerOpt Patch Enables Task | Checksum: 13364790e

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3605.203 ; gain = 0.000 ; free physical = 2478 ; free virtual = 20787
Ending Power Optimization Task | Checksum: 13364790e

Time (s): cpu = 00:01:46 ; elapsed = 00:01:50 . Memory (MB): peak = 3605.203 ; gain = 702.461 ; free physical = 2519 ; free virtual = 20829

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 1d431d4a2

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3605.203 ; gain = 0.000 ; free physical = 2519 ; free virtual = 20829
Ending Final Cleanup Task | Checksum: 1d431d4a2

Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 3605.203 ; gain = 0.000 ; free physical = 2519 ; free virtual = 20829

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.203 ; gain = 0.000 ; free physical = 2519 ; free virtual = 20829
Ending Netlist Obfuscation Task | Checksum: 1d431d4a2

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.203 ; gain = 0.000 ; free physical = 2519 ; free virtual = 20829
INFO: [Common 17-83] Releasing license: Implementation
61 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:04:19 ; elapsed = 00:06:22 . Memory (MB): peak = 3605.203 ; gain = 837.332 ; free physical = 2519 ; free virtual = 20829
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-35] Done setting XDC timing constraints.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.203 ; gain = 0.000 ; free physical = 2495 ; free virtual = 20805
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3605.203 ; gain = 0.000 ; free physical = 2477 ; free virtual = 20802
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 3605.207 ; gain = 0.004 ; free physical = 2481 ; free virtual = 20801
INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx
Command: report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2475 ; free virtual = 20799
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2472 ; free virtual = 20796
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 118662acc

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2472 ; free virtual = 20796
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2472 ; free virtual = 20796

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3fb209d2

Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2455 ; free virtual = 20785

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 51e4f791

Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2410 ; free virtual = 20739

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 51e4f791

Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2410 ; free virtual = 20739
Phase 1 Placer Initialization | Checksum: 51e4f791

Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2407 ; free virtual = 20737

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 11ecbd86e

Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2393 ; free virtual = 20723

Phase 2.2 Global Placement Core

Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-1018] Found 559 candidate LUT instances to create LUTNM shape
INFO: [Physopt 32-775] End 1 Pass. Optimized 202 nets or cells. Created 1 new cell, deleted 201 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2375 ; free virtual = 20710

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            1  |            201  |                   202  |           0  |           1  |  00:00:01  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            1  |            201  |                   202  |           0  |           7  |  00:00:01  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2.1 Physical Synthesis In Placer | Checksum: 18ae93456

Time (s): cpu = 00:01:05 ; elapsed = 00:01:08 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2376 ; free virtual = 20711
Phase 2.2 Global Placement Core | Checksum: 2233f9964

Time (s): cpu = 00:01:08 ; elapsed = 00:01:11 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2370 ; free virtual = 20704
Phase 2 Global Placement | Checksum: 2233f9964

Time (s): cpu = 00:01:08 ; elapsed = 00:01:11 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2381 ; free virtual = 20715

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 252576002

Time (s): cpu = 00:01:13 ; elapsed = 00:01:16 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2380 ; free virtual = 20715

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1fef0cb99

Time (s): cpu = 00:01:22 ; elapsed = 00:01:25 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2377 ; free virtual = 20711

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 20c2f3b9c

Time (s): cpu = 00:01:22 ; elapsed = 00:01:25 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2377 ; free virtual = 20711

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 15b612f2d

Time (s): cpu = 00:01:22 ; elapsed = 00:01:25 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2377 ; free virtual = 20711

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 17f4e1925

Time (s): cpu = 00:01:29 ; elapsed = 00:01:32 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2377 ; free virtual = 20711

Phase 3.6 Small Shape Detail Placement

Phase 3.6.1 Place Remaining
Phase 3.6.1 Place Remaining | Checksum: 190ece995

Time (s): cpu = 00:01:40 ; elapsed = 00:01:43 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2347 ; free virtual = 20681
Phase 3.6 Small Shape Detail Placement | Checksum: 190ece995

Time (s): cpu = 00:01:40 ; elapsed = 00:01:44 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20691

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 13bc05216

Time (s): cpu = 00:01:42 ; elapsed = 00:01:45 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20692

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 120a2b8dd

Time (s): cpu = 00:01:42 ; elapsed = 00:01:46 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20692

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 1734cad5c

Time (s): cpu = 00:01:54 ; elapsed = 00:01:57 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2354 ; free virtual = 20688
Phase 3 Detail Placement | Checksum: 1734cad5c

Time (s): cpu = 00:01:54 ; elapsed = 00:01:58 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2354 ; free virtual = 20688

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1ce305f38

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1ce305f38

Time (s): cpu = 00:02:08 ; elapsed = 00:02:12 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20691
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.052. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 211dbbea0

Time (s): cpu = 00:02:12 ; elapsed = 00:02:17 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2361 ; free virtual = 20695
Phase 4.1 Post Commit Optimization | Checksum: 211dbbea0

Time (s): cpu = 00:02:13 ; elapsed = 00:02:17 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2361 ; free virtual = 20695

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 211dbbea0

Time (s): cpu = 00:02:13 ; elapsed = 00:02:17 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2369 ; free virtual = 20703

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 211dbbea0

Time (s): cpu = 00:02:14 ; elapsed = 00:02:18 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2371 ; free virtual = 20705

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2372 ; free virtual = 20706
Phase 4.4 Final Placement Cleanup | Checksum: 179f88550

Time (s): cpu = 00:02:14 ; elapsed = 00:02:18 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2372 ; free virtual = 20706
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 179f88550

Time (s): cpu = 00:02:14 ; elapsed = 00:02:18 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2372 ; free virtual = 20707
Ending Placer Task | Checksum: ed43d453

Time (s): cpu = 00:02:14 ; elapsed = 00:02:18 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2372 ; free virtual = 20707
INFO: [Common 17-83] Releasing license: Implementation
93 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:02:17 ; elapsed = 00:02:22 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2404 ; free virtual = 20738
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2404 ; free virtual = 20738
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2363 ; free virtual = 20737
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2393 ; free virtual = 20738
INFO: [runtcl-4] Executing : report_io -file top_FTM_Control_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2371 ; free virtual = 20717
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed.rpt -pb top_FTM_Control_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_Control_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2389 ; free virtual = 20735
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed_1.rpt -pb top_FTM_Control_utilization_placed_1.pb
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: a7334199 ConstDB: 0 ShapeSum: 461092ba RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 18ceddc8b

Time (s): cpu = 00:01:01 ; elapsed = 00:01:02 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2123 ; free virtual = 20468
Post Restoration Checksum: NetGraph: d869feea NumContArr: b483dda1 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 18ceddc8b

Time (s): cpu = 00:01:02 ; elapsed = 00:01:02 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2092 ; free virtual = 20437

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 18ceddc8b

Time (s): cpu = 00:01:02 ; elapsed = 00:01:03 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2083 ; free virtual = 20429

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 18ceddc8b

Time (s): cpu = 00:01:02 ; elapsed = 00:01:03 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2083 ; free virtual = 20429
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 288ff0fc5

Time (s): cpu = 00:01:25 ; elapsed = 00:01:27 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2047 ; free virtual = 20393
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.106  | TNS=0.000  | WHS=-0.390 | THS=-668.369|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 219f7096a

Time (s): cpu = 00:01:34 ; elapsed = 00:01:36 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2045 ; free virtual = 20390
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.106  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 1b2e9645e

Time (s): cpu = 00:01:34 ; elapsed = 00:01:36 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2044 ; free virtual = 20389
Phase 2 Router Initialization | Checksum: 105f43731

Time (s): cpu = 00:01:34 ; elapsed = 00:01:36 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2044 ; free virtual = 20389

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.000922182 %
  Global Horizontal Routing Utilization  = 0.000138953 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 22560
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 22558
  Number of Partially Routed Nets     = 2
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 165c7bbf7

Time (s): cpu = 00:02:25 ; elapsed = 00:02:28 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2034 ; free virtual = 20380

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 2090
 Number of Nodes with overlaps = 161
 Number of Nodes with overlaps = 20
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.422  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: efbe3c60

Time (s): cpu = 00:02:54 ; elapsed = 00:02:57 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384
Phase 4 Rip-up And Reroute | Checksum: efbe3c60

Time (s): cpu = 00:02:54 ; elapsed = 00:02:57 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: efbe3c60

Time (s): cpu = 00:02:54 ; elapsed = 00:02:58 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: efbe3c60

Time (s): cpu = 00:02:54 ; elapsed = 00:02:58 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384
Phase 5 Delay and Skew Optimization | Checksum: efbe3c60

Time (s): cpu = 00:02:54 ; elapsed = 00:02:58 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 14d160739

Time (s): cpu = 00:02:59 ; elapsed = 00:03:02 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.148  | TNS=0.000  | WHS=0.056  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: c7a85396

Time (s): cpu = 00:02:59 ; elapsed = 00:03:02 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384
Phase 6 Post Hold Fix | Checksum: c7a85396

Time (s): cpu = 00:02:59 ; elapsed = 00:03:03 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20384

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 2.31034 %
  Global Horizontal Routing Utilization  = 2.61505 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 187a00ebe

Time (s): cpu = 00:03:00 ; elapsed = 00:03:03 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2038 ; free virtual = 20383

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 187a00ebe

Time (s): cpu = 00:03:00 ; elapsed = 00:03:03 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2037 ; free virtual = 20382

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1e4d8e9c3

Time (s): cpu = 00:03:03 ; elapsed = 00:03:06 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2033 ; free virtual = 20379

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.148  | TNS=0.000  | WHS=0.056  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1e4d8e9c3

Time (s): cpu = 00:03:03 ; elapsed = 00:03:07 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2037 ; free virtual = 20383
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:03:03 ; elapsed = 00:03:07 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2065 ; free virtual = 20414

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
112 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:03:08 ; elapsed = 00:03:12 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2065 ; free virtual = 20414
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_Control was modified...
INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean.
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains D65CA14, will use most recent tag v3.1.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Found last SHA for FTM_Control: d65ca14
INFO: [Hog:Msg-0] The git SHA value d65ca14 will be set as bitstream USERID.
INFO: [Hog:Msg-0] All done.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2066 ; free virtual = 20415
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2019 ; free virtual = 20417
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2054 ; free virtual = 20416
INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx
Command: report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2043 ; free virtual = 20405
INFO: [runtcl-4] Executing : report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx
Command: report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 2033 ; free virtual = 20395
INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx
Command: report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
133 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 1985 ; free virtual = 20356
INFO: [runtcl-4] Executing : report_route_status -file top_FTM_Control_route_status.rpt -pb top_FTM_Control_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_Control_timing_summary_routed.rpt -pb top_FTM_Control_timing_summary_routed.pb -rpx top_FTM_Control_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_Control_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_Control_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_Control_bus_skew_routed.rpt -pb top_FTM_Control_bus_skew_routed.pb -rpx top_FTM_Control_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx
Command: report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed_1.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 1960 ; free virtual = 20337
INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx
Command: report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
145 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 3605.207 ; gain = 0.000 ; free physical = 1950 ; free virtual = 20336
INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_Control_timing_summary_routed_1.rpt -pb top_FTM_Control_timing_summary_routed_1.pb -rpx top_FTM_Control_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
INFO: [Common 17-206] Exiting Vivado at Fri Mar 11 16:15:22 2022...

*** Running vivado
    with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_Control.tcl -notrace
Command: open_checkpoint top_FTM_Control_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1593.148 ; gain = 0.000 ; free physical = 3752 ; free virtual = 22135
INFO: [Device 21-403] Loading part xc7k325tffg900-2
Netlist sorting complete. Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1944.664 ; gain = 0.000 ; free physical = 3278 ; free virtual = 21661
INFO: [Netlist 29-17] Analyzing 1359 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2673.609 ; gain = 21.332 ; free physical = 2600 ; free virtual = 20984
Restored from archive | CPU: 2.860000 secs | Memory: 34.446480 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2673.609 ; gain = 21.332 ; free physical = 2600 ; free virtual = 20984
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2673.609 ; gain = 0.000 ; free physical = 2603 ; free virtual = 20986
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 254 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 212 instances
  IOBUF => IOBUF (IBUF, OBUFT): 4 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 8 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances
  SRLC32E => SRL16E: 2 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876
open_checkpoint: Time (s): cpu = 00:00:37 ; elapsed = 00:01:12 . Memory (MB): peak = 2673.609 ; gain = 1080.465 ; free physical = 2602 ; free virtual = 20985
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: write_bitstream -force top_FTM_Control.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.

Evaluation cores found in this design:
    IP core 'temac_gbe_v9_0_gmii' (temac_gbe_v9_0_gmii_block) was generated with multiple features:
        IP feature 'eth_avb_endpoint@2015.04' was enabled using a design_linking license.
        IP feature 'tri_mode_eth_mac@2015.04' was enabled using a bought license.

Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [DRC RTSTAT-10] No routable loads: 101 net(s) have no routable loads. The problem bus(es) and/or net(s) are eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rd_rst_reg[2:0]... and (the first 15 of 53 listed).
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 49408096 bits.
Writing bitstream ./top_FTM_Control.bit...
Writing bitstream ./top_FTM_Control.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Mar 11 16:19:04 2022. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
26 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:01:53 ; elapsed = 00:02:05 . Memory (MB): peak = 3232.156 ; gain = 558.547 ; free physical = 2503 ; free virtual = 20907
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating Git sha for FTM_Control...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains D65CA14, will use most recent tag v3.1.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Git describe set to: v3.1.2-2-gd65ca14
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v3.1.2-2-gd65ca14...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v3.1.2-2-gd65ca14/FTM_Control-v3.1.2-2-gd65ca14.bit...