*** Running vivado
    with args -log top_FTM_Control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_FTM_Control.tcl


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_Control.tcl -notrace
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-synthesis.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Found Projects/hog_reset_files, opening it...
INFO: [Hog:Msg-0] Found the following files/wild cards to restore if modified: *.bd...
INFO: [Hog:Msg-0] No modified *.bd files found.
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
CRITICAL WARNING: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control not clean, commit hash, and version will be set to 0.
INFO: [Hog:GetVerFromSHA-0] No tag contains F48C96E, will use most recent tag v3.3.0. As this is an official tag, patch will be incremented to 1.
INFO: [Hog:GetVerFromSHA-0] No tag contains F48C96E, will use most recent tag v3.3.0. As this is an official tag, patch will be incremented to 1.
INFO: [Hog:GetVerFromSHA-0] No tag contains D6CD94A, will use most recent tag v3.3.0. As this is an official tag, patch will be incremented to 1.
INFO: [Hog:Msg-0] Git describe for 0000000 is: v3.3.0-9-g2936948-dirty
CRITICAL WARNING: [Hog:Msg-0] Repository is not clean, will use current SHA (2936948) and create a dirty bitfile...
INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml and replacing placeholders with xml version 03010004...
INFO: [Hog:CopyXMLsFromListFile-0] 19 lines read from ./Top/FTM_Control/list/xml.lst
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/L1CaloFtm.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_common_IdVersion.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_module_control.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_xadc.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_reconfigure.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_pll_spi_ram.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_flash_spi_ram.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_module_control.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_l1a_generator.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_playback_control.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_con_mgt_registers.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_con_2quad_registers.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_ttc_fmc.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_i2c.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_mgt_buf_control.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_ttcinfo.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_con_source_ram.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Infrastructure/xml/ftm_con_sink_ram.xml to /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml...
INFO: [Hog:CopyXMLsFromListFile-0] 18 file/s copied
INFO: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml/L1CaloFtm.xml and /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_decode_L1CaloFtm.vhd match.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_common_IdVersion.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_module_control.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_xadc.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_reconfigure.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_pll_spi_ram.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_flash_spi_ram.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_module_control.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_l1a_generator.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_playback_control.xml as no VHDL file was specified.
CRITICAL WARNING: [Hog:CopyXMLsFromListFile-0] /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_decode_ftm_con_mgt_registers.vhd does not correspond to its XML /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/xml/ftm_con_mgt_registers.xml, 6 line/s differ:
> constant IPBUS_SEL_WIDTH: positive := 2;
< constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?


> constant N_SLV_QUADS_115_116: integer := 0;
< constant N_SLV_QUADS115_116: integer := 0;


> constant N_SLV_QUADS_117_118: integer := 1;
< constant N_SLV_QUADS117_118: integer := 1;


> sel := ipbus_sel_t(to_unsigned(N_SLV_QUADS_115_116, IPBUS_SEL_WIDTH)); -- quads_115_116 / base 0x00000000 / mask 0x00000008
< sel := ipbus_sel_t(to_unsigned(N_SLV_QUADS115_116, IPBUS_SEL_WIDTH)); -- Quads115_116 / base 0x00000000 / mask 0x00000008


> sel := ipbus_sel_t(to_unsigned(N_SLV_QUADS_117_118, IPBUS_SEL_WIDTH)); -- quads_117_118 / base 0x00000008 / mask 0x00000008
< sel := ipbus_sel_t(to_unsigned(N_SLV_QUADS117_118, IPBUS_SEL_WIDTH)); -- Quads117_118 / base 0x00000008 / mask 0x00000008

INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_con_2quad_registers.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_ttc_fmc.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_i2c.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_mgt_buf_control.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_ttcinfo.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_con_source_ram.xml as no VHDL file was specified.
INFO: [Hog:CopyXMLsFromListFile-0] Skipped verification of ftm_con_sink_ram.xml as no VHDL file was specified.
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/versions.txt...
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v3.3.0-9-g2936948-dirty...
INFO: [Hog:Msg-0] Evaluating non committed changes...
WARNING: [Hog:Msg-0] Found non committed changes:...
diff --git a/IP/ila_rx/ila_rx.xci b/IP/ila_rx/ila_rx.xci
index 42a30a2..465e846 100644
--- a/IP/ila_rx/ila_rx.xci
+++ b/IP/ila_rx/ila_rx.xci
@@ -78,7 +78,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MONITOR_SLOTS">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_PROBES">7</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL">AXI4</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TIME_TAG_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TIME_TAG_WIDTH">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGIN_EN">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGOUT_EN">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
diff --git a/IP/ila_tx/ila_tx.xci b/IP/ila_tx/ila_tx.xci
index 692ed9d..3f2fba9 100644
--- a/IP/ila_tx/ila_tx.xci
+++ b/IP/ila_tx/ila_tx.xci
@@ -78,7 +78,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MONITOR_SLOTS">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_PROBES">2</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SLOT_0_AXI_PROTOCOL">AXI4</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TIME_TAG_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TIME_TAG_WIDTH">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGIN_EN">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGOUT_EN">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
 ------------------------- PRE SYNTHESIS -------------------------
 11/05/2022 at 17:43:44
 Firmware date and time: '10052022', '00221042'
 Global SHA: 2936948, VER: 0.0.0
 Constraints SHA: 1C0E44B, VER: 3.0.2
 IPbus XML SHA: B4F6D12, VER: 3.1.4
 Top SHA: AB7034F, VER: 0.0.21
 Hog SHA: 6C02797, VER: 3.0.0
 --- Libraries ---
 Default SHA: F48C96E, VER: 3.3.1
 ftm SHA: F48C96E, VER: 3.3.1
 ipbus_lib SHA: D6CD94A, VER: 3.3.1
 --- External Libraries ---
 -----------------------------------------------------------------
INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml
INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with v3.0.0 in .gitlab-ci.yml.
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Opening project FTM_Control...
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
INFO: [Hog:Msg-0] Checking FTM_Control list files...
INFO: [Hog:Msg-0] List Files matches project. All ok!
INFO: [Hog:Msg-0] All done.
Command: synth_design -top top_FTM_Control -part xc7k325tffg900-2
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 10204 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 2186.785 ; gain = 200.715 ; free physical = 3230 ; free virtual = 21318
---------------------------------------------------------------------------------
WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:65]
WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_frame_init.vhd:41]
WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_ctrl_init.vhd:36]
INFO: [Synth 8-638] synthesizing module 'top_ftm_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:182]
	Parameter FLAVOUR bound to: 0 - type: integer 
	Parameter GLOBAL_DATE bound to: 32'b00010000000001010010000000100010 
	Parameter GLOBAL_TIME bound to: 32'b00000000001000100001000001000010 
	Parameter GLOBAL_SHA bound to: 32'b00000010100100110110100101001000 
	Parameter GLOBAL_VER bound to: 32'b00000000000000000000000000000000 
	Parameter TOP_SHA bound to: 32'b00001010101101110000001101001111 
	Parameter TOP_VER bound to: 32'b00000000000000000000000000010101 
	Parameter CON_SHA bound to: 32'b00000001110000001110010001001011 
	Parameter CON_VER bound to: 32'b00000011000000000000000000000010 
	Parameter XML_SHA bound to: 32'b00001011010011110110110100010010 
	Parameter XML_VER bound to: 32'b00000011000000010000000000000100 
	Parameter HOG_SHA bound to: 32'b00000110110000000010011110010111 
	Parameter HOG_VER bound to: 32'b00000011000000000000000000000000 
	Parameter FTM_SHA bound to: 32'b00001111010010001100100101101110 
	Parameter FTM_VER bound to: 32'b00000011000000110000000000000001 
	Parameter NSRC bound to: 3 - type: integer 
WARNING: [Synth 8-3819] Generic 'DEFAULT_VER' not present in instantiated entity will be ignored
WARNING: [Synth 8-3819] Generic 'DEFAULT_SHA' not present in instantiated entity will be ignored
WARNING: [Synth 8-3819] Generic 'IPBUS_LIB_VER' not present in instantiated entity will be ignored
WARNING: [Synth 8-3819] Generic 'IPBUS_LIB_SHA' not present in instantiated entity will be ignored
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:196]
INFO: [Synth 8-638] synthesizing module 'gtwizard_0_exdes' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:117]
	Parameter EXAMPLE_CONFIG_INDEPENDENT_LANES bound to: 1 - type: integer 
	Parameter EXAMPLE_LANE_WITH_START_CHAR bound to: 0 - type: integer 
	Parameter EXAMPLE_WORDS_IN_BRAM bound to: 512 - type: integer 
	Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer 
	Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:306]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:307]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:313]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:314]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:317]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:318]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:321]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:322]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:323]
	Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer 
INFO: [Synth 8-3491] module 'gtwizard_0_support' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_support.vhd:74' bound to instance 'gtwizard_0_support_i' of component 'gtwizard_0_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:621]
INFO: [Synth 8-638] synthesizing module 'gtwizard_0_support' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_support.vhd:180]
	Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer 
INFO: [Synth 8-3491] module 'gtwizard_0_GT_USRCLK_SOURCE' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_gt_usrclk_source.vhd:72' bound to instance 'gt_usrclk_source' of component 'gtwizard_0_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_support.vhd:505]
INFO: [Synth 8-638] synthesizing module 'gtwizard_0_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_gt_usrclk_source.vhd:90]
	Parameter CLKCM_CFG bound to: 1 - type: bool 
	Parameter CLKRCV_TRST bound to: 1 - type: bool 
	Parameter CLKSWING_CFG bound to: 2'b11 
INFO: [Synth 8-113] binding component instance 'ibufds_instq0_clk0' to cell 'IBUFDS_GTE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_gt_usrclk_source.vhd:146]
INFO: [Synth 8-113] binding component instance 'txoutclk_bufg0_i' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_gt_usrclk_source.vhd:160]
INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg1_i' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_gt_usrclk_source.vhd:168]
INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_GT_USRCLK_SOURCE' (1#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_gt_usrclk_source.vhd:90]
	Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 
INFO: [Synth 8-3491] module 'gtwizard_0_common' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common.vhd:72' bound to instance 'common0_i' of component 'gtwizard_0_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_support.vhd:523]
INFO: [Synth 8-638] synthesizing module 'gtwizard_0_common' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common.vhd:94]
	Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 
	Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 
	Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000000000000 
	Parameter COMMON_CFG bound to: 32'b00000000000000000000000000000000 
	Parameter IS_DRPCLK_INVERTED bound to: 1'b0 
	Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 
	Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 
	Parameter QPLL_CFG bound to: 28'b0000011010000000000111000001 
	Parameter QPLL_CLKOUT_CFG bound to: 4'b0000 
	Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 
	Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 
	Parameter QPLL_CP bound to: 10'b0000011111 
	Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 
	Parameter QPLL_DMONITOR_SEL bound to: 1'b0 
	Parameter QPLL_FBDIV bound to: 10'b0010000000 
	Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 
	Parameter QPLL_FBDIV_RATIO bound to: 1'b1 
	Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 
	Parameter QPLL_LOCK_CFG bound to: 16'b0010000111101000 
	Parameter QPLL_LPF bound to: 4'b1111 
	Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer 
	Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 
	Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string 
	Parameter SIM_VERSION bound to: 4.0 - type: string 
INFO: [Synth 8-113] binding component instance 'gtxe2_common_i' to cell 'GTXE2_COMMON' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common.vhd:172]
INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_common' (2#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common.vhd:94]
	Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer 
INFO: [Synth 8-3491] module 'gtwizard_0_common_reset' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common_reset.vhd:78' bound to instance 'common_reset_i' of component 'gtwizard_0_common_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_support.vhd:543]
INFO: [Synth 8-638] synthesizing module 'gtwizard_0_common_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common_reset.vhd:91]
	Parameter STABLE_CLOCK_PERIOD bound to: 24 - type: integer 
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common_reset.vhd:133]
INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_common_reset' (3#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_common_reset.vhd:91]
INFO: [Synth 8-3491] module 'gtwizard_0' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/gtwizard_0_stub.vhdl:5' bound to instance 'gtwizard_0_init_i' of component 'gtwizard_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_support.vhd:557]
INFO: [Synth 8-638] synthesizing module 'gtwizard_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/gtwizard_0_stub.vhdl:72]
INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_support' (4#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/support/gtwizard_0_support.vhd:180]
INFO: [Synth 8-3491] module 'ila_tx' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/ila_tx_stub.vhdl:5' bound to instance 'tx_data' of component 'ila_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:870]
INFO: [Synth 8-638] synthesizing module 'ila_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/ila_tx_stub.vhdl:14]
INFO: [Synth 8-3491] module 'ila_rx' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/ila_rx_stub.vhdl:5' bound to instance 'rx_data' of component 'ila_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:884]
INFO: [Synth 8-638] synthesizing module 'ila_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/ila_rx_stub.vhdl:19]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'gtwizard_0_support_i'. This will prevent further optimization [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:621]
WARNING: [Synth 8-3848] Net PLL_POWERDOWN_vio_o in module/entity gtwizard_0_exdes does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:547]
INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_exdes' (5#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/ttcinfo_mgt/gtwizard_0_exdes.vhd:117]
INFO: [Synth 8-638] synthesizing module 'pll_synch' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/pll_synch.vhd:21]
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/pll_synch.vhd:16]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/pll_synch.vhd:16]
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/pll_synch.vhd:28]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/pll_synch.vhd:28]
INFO: [Synth 8-256] done synthesizing module 'pll_synch' (6#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/pll_synch.vhd:21]
INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:30]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 'ibufgds0' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:44]
INFO: [Synth 8-113] binding component instance 'bufg200' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:50]
INFO: [Synth 8-113] binding component instance 'bufg125' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:57]
INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:64]
INFO: [Synth 8-113] binding component instance 'bufgfb' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:71]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double 
	Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double 
	Parameter CLKOUT0_DIVIDE_F bound to: 1.000000 - type: double 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT1_PHASE bound to: 292.500000 - type: double 
	Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT2_PHASE bound to: 73.125000 - type: double 
	Parameter CLKOUT3_DIVIDE bound to: 5 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
INFO: [Synth 8-113] binding component instance 'mmcm' to cell 'MMCME2_BASE' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:77]
INFO: [Synth 8-638] synthesizing module 'clock_div' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clock_div.vhd:25]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clock_div.vhd:31]
INFO: [Synth 8-256] done synthesizing module 'clock_div' (7#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clock_div.vhd:25]
INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (8#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/clocks_7s_ftm.vhd:30]
INFO: [Synth 8-638] synthesizing module 'mac_arbiter' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_eth/firmware/hdl/mac_arbiter.vhd:35]
	Parameter NSRC bound to: 3 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'mac_arbiter' (9#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_eth/firmware/hdl/mac_arbiter.vhd:35]
INFO: [Synth 8-638] synthesizing module 'udp_master_rarp' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:24]
WARNING: [Synth 8-6014] Unused sequential element pkt_data_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:88]
WARNING: [Synth 8-6014] Unused sequential element addr_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element rarp_req_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:135]
INFO: [Synth 8-4471] merging register 'rarp_rx_valid_reg' into 'valid_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:95]
INFO: [Synth 8-4471] merging register 'rarp_rx_last_reg' into 'last_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:100]
WARNING: [Synth 8-6014] Unused sequential element rarp_rx_valid_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:95]
WARNING: [Synth 8-6014] Unused sequential element rarp_rx_last_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:100]
INFO: [Synth 8-256] done synthesizing module 'udp_master_rarp' (10#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_rarp.vhd:24]
INFO: [Synth 8-638] synthesizing module 'UDP_master_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:36]
WARNING: [Synth 8-6014] Unused sequential element next_last_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:92]
WARNING: [Synth 8-6014] Unused sequential element next_error_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element valid_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element data_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:96]
WARNING: [Synth 8-6014] Unused sequential element next_valid_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:124]
WARNING: [Synth 8-6014] Unused sequential element next_data_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:125]
WARNING: [Synth 8-6014] Unused sequential element last_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:126]
WARNING: [Synth 8-6014] Unused sequential element error_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:127]
INFO: [Synth 8-4471] merging register 'Got_IP_addr_sig_reg' into 'Got_IP_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:85]
WARNING: [Synth 8-6014] Unused sequential element Got_IP_addr_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:85]
INFO: [Synth 8-256] done synthesizing module 'UDP_master_if' (11#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_if.vhd:36]
INFO: [Synth 8-638] synthesizing module 'UDP_master_fifo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_fifo.vhd:35]
	Parameter BUFWIDTH bound to: 5 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element FillLevel_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_fifo.vhd:102]
INFO: [Synth 8-4471] merging register 'mac_tx_valid_reg' into 'Running_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_fifo.vhd:138]
WARNING: [Synth 8-6014] Unused sequential element mac_tx_valid_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_fifo.vhd:138]
INFO: [Synth 8-256] done synthesizing module 'UDP_master_fifo' (12#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_fifo.vhd:35]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:664]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1p' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:672]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:680]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2p' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:688]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_1pause' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:695]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'm2s_2pause' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:702]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:711]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:720]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_1txe' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:728]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 's2m_2txe' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:735]
INFO: [Synth 8-638] synthesizing module 'eth_7s_gmii' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_eth/firmware/hdl/eth_7s_gmii.vhd:45]
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
INFO: [Synth 8-113] binding component instance 'idelayctrl0' to cell 'IDELAYCTRL' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_eth/firmware/hdl/eth_7s_gmii.vhd:112]
INFO: [Synth 8-3491] module 'temac_gbe_v9_0_gmii' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/temac_gbe_v9_0_gmii_stub.vhdl:5' bound to instance 'emac0' of component 'temac_gbe_v9_0_gmii' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_eth/firmware/hdl/eth_7s_gmii.vhd:119]
INFO: [Synth 8-638] synthesizing module 'temac_gbe_v9_0_gmii' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/temac_gbe_v9_0_gmii_stub.vhdl:47]
INFO: [Synth 8-3491] module 'mac_fifo_axi4' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/mac_fifo_axi4_stub.vhdl:5' bound to instance 'fifo' of component 'mac_fifo_axi4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_eth/firmware/hdl/eth_7s_gmii.vhd:163]
INFO: [Synth 8-638] synthesizing module 'mac_fifo_axi4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/mac_fifo_axi4_stub.vhdl:24]
INFO: [Synth 8-256] done synthesizing module 'eth_7s_gmii' (13#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/components/ipbus_eth/firmware/hdl/eth_7s_gmii.vhd:45]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:67]
	Parameter MAC_CFG bound to: 1'b0 
	Parameter IP_CFG bound to: 1'b0 
	Parameter BUFWIDTH bound to: 4 - type: integer 
	Parameter INTERNALWIDTH bound to: 1 - type: integer 
	Parameter ADDRWIDTH bound to: 11 - type: integer 
	Parameter IPBUSPORT bound to: 16'b1100001101010001 
	Parameter SECONDARYPORT bound to: 1'b0 
	Parameter N_OOB bound to: 0 - type: integer 
WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:61]
WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:62]
INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:67]
	Parameter BUFWIDTH bound to: 4 - type: integer 
	Parameter INTERNALWIDTH bound to: 1 - type: integer 
	Parameter ADDRWIDTH bound to: 11 - type: integer 
	Parameter IPBUSPORT bound to: 16'b1100001101010001 
	Parameter SECONDARYPORT bound to: 1'b0 
INFO: [Synth 8-638] synthesizing module 'udp_rarp_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:24]
WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:55]
WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:56]
WARNING: [Synth 8-6014] Unused sequential element pkt_data_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:112]
WARNING: [Synth 8-6014] Unused sequential element addr_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:145]
WARNING: [Synth 8-6014] Unused sequential element tick_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:164]
WARNING: [Synth 8-6014] Unused sequential element t_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:195]
WARNING: [Synth 8-6014] Unused sequential element rarp_req_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:220]
INFO: [Synth 8-4471] merging register 'rarp_we_sig_reg' into 'we_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:34]
WARNING: [Synth 8-6014] Unused sequential element rarp_we_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:34]
INFO: [Synth 8-256] done synthesizing module 'udp_rarp_block' (14#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rarp_block.vhd:24]
INFO: [Synth 8-638] synthesizing module 'udp_build_arp' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:28]
WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:45]
WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:47]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:81]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:82]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:225]
INFO: [Synth 8-4471] merging register 'arp_we_sig_reg' into 'arp_we_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:37]
INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:176]
INFO: [Synth 8-4471] merging register 'buf_to_load_reg[47:0]' into 'buf_to_load_int_reg[47:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:181]
INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:186]
INFO: [Synth 8-4471] merging register 'address_reg[5:0]' into 'addr_int_reg[5:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:38]
WARNING: [Synth 8-6014] Unused sequential element arp_we_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:37]
WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:176]
WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:181]
WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:186]
WARNING: [Synth 8-6014] Unused sequential element address_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'udp_build_arp' (15#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:28]
INFO: [Synth 8-638] synthesizing module 'udp_build_ping' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:31]
WARNING: [Synth 8-6014] Unused sequential element state_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:54]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:114]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element ping_we_i_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:179]
WARNING: [Synth 8-6014] Unused sequential element clr_sum_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:251]
WARNING: [Synth 8-6014] Unused sequential element int_valid_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:252]
WARNING: [Synth 8-6014] Unused sequential element int_data_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:253]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:351]
INFO: [Synth 8-4471] merging register 'ping_end_addr_reg[12:0]' into 'end_addr_i_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:77]
INFO: [Synth 8-4471] merging register 'ping_send_reg' into 'send_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:82]
INFO: [Synth 8-4471] merging register 'send_pending_reg' into 'send_pending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:43]
INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:226]
INFO: [Synth 8-4471] merging register 'buf_to_load_reg[15:0]' into 'buf_to_load_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:231]
INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:236]
INFO: [Synth 8-4471] merging register 'do_sum_ping_reg' into 'do_sum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:285]
INFO: [Synth 8-4471] merging register 'address_reg[12:0]' into 'addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:41]
INFO: [Synth 8-4471] merging register 'low_addr_reg' into 'low_addr_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:121]
WARNING: [Synth 8-6014] Unused sequential element ping_end_addr_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:77]
WARNING: [Synth 8-6014] Unused sequential element ping_send_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:82]
WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:43]
WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:226]
WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:231]
WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:236]
WARNING: [Synth 8-6014] Unused sequential element do_sum_ping_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:285]
WARNING: [Synth 8-6014] Unused sequential element address_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:41]
WARNING: [Synth 8-6014] Unused sequential element low_addr_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:121]
INFO: [Synth 8-256] done synthesizing module 'udp_build_ping' (16#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:31]
INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:30]
INFO: [Synth 8-4471] merging register 'MAC_IP_addr_rx_reg[79:0]' into 'MAC_IP_addr_rx_int_reg[79:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:76]
WARNING: [Synth 8-6014] Unused sequential element MAC_IP_addr_rx_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:76]
INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_block' (17#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_block.vhd:30]
INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:33]
WARNING: [Synth 8-6014] Unused sequential element state_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:60]
WARNING: [Synth 8-6014] Unused sequential element send_i_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:63]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element next_low_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:409]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:486]
INFO: [Synth 8-4471] merging register 'send_pending_reg' into 'send_pending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:46]
INFO: [Synth 8-4471] merging register 'payload_we_sig_reg' into 'payload_we_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:43]
INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:268]
INFO: [Synth 8-4471] merging register 'buf_to_load_reg[15:0]' into 'buf_to_load_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:273]
INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:278]
INFO: [Synth 8-4471] merging register 'do_sum_payload_reg' into 'do_sum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:362]
INFO: [Synth 8-4471] merging register 'clr_sum_payload_reg' into 'clr_sum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:367]
INFO: [Synth 8-4471] merging register 'int_data_payload_reg[7:0]' into 'int_data_int_reg[7:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:372]
INFO: [Synth 8-4471] merging register 'int_valid_payload_reg' into 'int_valid_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:377]
INFO: [Synth 8-4471] merging register 'cksum_reg' into 'cksum_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:382]
INFO: [Synth 8-4471] merging register 'next_addr_reg[12:0]' into 'next_addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:408]
INFO: [Synth 8-4471] merging register 'address_reg[12:0]' into 'addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:126]
INFO: [Synth 8-4471] merging register 'low_addr_reg' into 'low_addr_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:123]
INFO: [Synth 8-4471] merging register 'byteswap_reg' into 'byteswap_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:473]
INFO: [Synth 8-4471] merging register 'ipbus_in_hdr_reg[31:0]' into 'ipbus_hdr_int_reg[31:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:515]
WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:46]
WARNING: [Synth 8-6014] Unused sequential element payload_we_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:43]
WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:268]
WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:273]
WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:278]
WARNING: [Synth 8-6014] Unused sequential element do_sum_payload_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:362]
WARNING: [Synth 8-6014] Unused sequential element clr_sum_payload_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:367]
WARNING: [Synth 8-6014] Unused sequential element int_data_payload_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:372]
WARNING: [Synth 8-6014] Unused sequential element int_valid_payload_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:377]
WARNING: [Synth 8-6014] Unused sequential element cksum_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:382]
WARNING: [Synth 8-6014] Unused sequential element next_addr_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:408]
WARNING: [Synth 8-6014] Unused sequential element address_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:126]
WARNING: [Synth 8-6014] Unused sequential element low_addr_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:123]
WARNING: [Synth 8-6014] Unused sequential element byteswap_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:473]
WARNING: [Synth 8-6014] Unused sequential element ipbus_in_hdr_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:515]
INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (18#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:33]
INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:23]
INFO: [Synth 8-4471] merging register 'resend_pkt_id_reg[15:0]' into 'resend_pkt_id_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:65]
WARNING: [Synth 8-6014] Unused sequential element resend_pkt_id_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:65]
INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (19#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:23]
INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:28]
WARNING: [Synth 8-6014] Unused sequential element end_addr_i_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:43]
WARNING: [Synth 8-6014] Unused sequential element set_addr_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:97]
WARNING: [Synth 8-6014] Unused sequential element addr_to_set_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:98]
WARNING: [Synth 8-6014] Unused sequential element request_int_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:183]
WARNING: [Synth 8-6014] Unused sequential element data_to_send_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:247]
INFO: [Synth 8-4471] merging register 'address_reg[6:0]' into 'addr_int_reg[6:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:36]
INFO: [Synth 8-4471] merging register 'load_buf_reg' into 'load_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:219]
INFO: [Synth 8-4471] merging register 'send_buf_reg' into 'send_buf_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:224]
WARNING: [Synth 8-6014] Unused sequential element address_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:36]
WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:219]
WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:224]
INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (20#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:28]
INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:49]
	Parameter BUFWIDTH bound to: 4 - type: integer 
	Parameter ADDRWIDTH bound to: 11 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element bufsize_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:101]
WARNING: [Synth 8-6014] Unused sequential element nbuf_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:102]
WARNING: [Synth 8-6014] Unused sequential element new_event_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:149]
WARNING: [Synth 8-6014] Unused sequential element async_ready_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:150]
WARNING: [Synth 8-6014] Unused sequential element rarp_arp_ping_ipbus_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:156]
WARNING: [Synth 8-6014] Unused sequential element payload_status_resend_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:158]
WARNING: [Synth 8-6014] Unused sequential element got_event_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:239]
WARNING: [Synth 8-6014] Unused sequential element event_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:240]
INFO: [Synth 8-4471] merging register 'next_pkt_id_reg[15:0]' into 'next_pkt_id_int_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:123]
WARNING: [Synth 8-6014] Unused sequential element next_pkt_id_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:123]
INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (21#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:49]
INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:25]
INFO: [Synth 8-4471] merging register 'carry_bit_reg' into 'carry_bit_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:88]
INFO: [Synth 8-4471] merging register 'hi_byte_reg[8:0]' into 'hi_byte_int_reg[8:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:32]
WARNING: [Synth 8-6014] Unused sequential element carry_bit_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:88]
WARNING: [Synth 8-6014] Unused sequential element hi_byte_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:32]
INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (22#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:25]
INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:20]
INFO: [Synth 8-4471] merging register 'rx_reset_sig_reg' into 'reset_latch_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:26]
WARNING: [Synth 8-6014] Unused sequential element rx_reset_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:26]
INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (23#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:20]
INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:37]
	Parameter IPBUSPORT bound to: 16'b1100001101010001 
	Parameter SECONDARYPORT bound to: 1'b0 
INFO: [Synth 8-4471] merging register 'primary_mode.pkt_drop_arp_sig_reg' into 'primary_mode.pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:59]
INFO: [Synth 8-4471] merging register 'primary_mode.pkt_drop_ping_sig_reg' into 'primary_mode.pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:60]
INFO: [Synth 8-4471] merging register 'pkt_drop_rarp_sig_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:47]
INFO: [Synth 8-4471] merging register 'pkt_drop_ip_sig_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:131]
INFO: [Synth 8-4471] merging register 'pkt_drop_ipbus_sig_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:48]
INFO: [Synth 8-4471] merging register 'ipbus_status_mask_reg' into 'last_mask_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:303]
INFO: [Synth 8-4471] merging register 'pkt_runt_reg' into 'header_sel_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:313]
INFO: [Synth 8-4471] merging register 'pkt_drop_reliable_sig_reg' into 'pkt_drop_reliable_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:353]
INFO: [Synth 8-4471] merging register 'pkt_reliable_drop_sig_reg' into 'pkt_drop_reliable_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:399]
INFO: [Synth 8-4471] merging register 'reliable_packet_reg' into 'IsReliable_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:422]
INFO: [Synth 8-4471] merging register 'pkt_drop_status_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:453]
INFO: [Synth 8-4471] merging register 'pkt_drop_resend_reg' into 'pkt_drop_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:488]
INFO: [Synth 8-4471] merging register 'pkt_broadcast_reg' into 'broadcast_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:510]
WARNING: [Synth 8-6014] Unused sequential element primary_mode.pkt_drop_arp_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:59]
WARNING: [Synth 8-6014] Unused sequential element primary_mode.pkt_drop_ping_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:60]
WARNING: [Synth 8-6014] Unused sequential element pkt_drop_rarp_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:47]
WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ip_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:131]
WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ipbus_sig_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:48]
WARNING: [Synth 8-6014] Unused sequential element ipbus_status_mask_reg was removed.  [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:303]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (24#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:37]
INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:56]
INFO: [Synth 8-4471] merging register 'ram_ready_reg' into 'ram_ready_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:62]
INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (25#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:56]
INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:22]
	Parameter BUFWIDTH bound to: 1 - type: integer 
	Parameter ADDRWIDTH bound to: 11 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (26#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:22]
INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32]
	Parameter BUFWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-4471] merging register 'free_reg[1:0]' into 'free_i_reg[1:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75]
INFO: [Synth 8-4471] merging register 'clean_reg[1:0]' into 'clean_i_reg[1:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44]
INFO: [Synth 8-4471] merging register 'send_pending_reg[1:0]' into 'send_pending_i_reg[1:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121]
INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43]
INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158]
INFO: [Synth 8-4471] merging register 'write_sig_reg[0:0]' into 'write_i_reg[0:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41]
INFO: [Synth 8-4471] merging register 'send_sig_reg[0:0]' into 'send_i_reg[0:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (27#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32]
INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:30]
	Parameter BUFWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (28#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:30]
INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:22]
	Parameter BUFWIDTH bound to: 4 - type: integer 
	Parameter ADDRWIDTH bound to: 11 - type: integer 
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:36]
INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (29#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:22]
INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32]
	Parameter BUFWIDTH bound to: 4 - type: integer 
INFO: [Synth 8-4471] merging register 'free_reg[15:0]' into 'free_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75]
INFO: [Synth 8-4471] merging register 'clean_reg[15:0]' into 'clean_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44]
INFO: [Synth 8-4471] merging register 'send_pending_reg[15:0]' into 'send_pending_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121]
INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43]
INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158]
INFO: [Synth 8-4471] merging register 'write_sig_reg[3:0]' into 'write_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41]
INFO: [Synth 8-4471] merging register 'send_sig_reg[3:0]' into 'send_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (29#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32]
INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:23]
INFO: [Synth 8-4471] merging register 'ram_ok_reg' into 'ram_ok_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:29]
INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (30#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:23]
INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:22]
	Parameter BUFWIDTH bound to: 4 - type: integer 
	Parameter ADDRWIDTH bound to: 11 - type: integer 
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (31#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:22]
INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32]
	Parameter BUFWIDTH bound to: 4 - type: integer 
INFO: [Synth 8-4471] merging register 'free_reg[15:0]' into 'free_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:75]
INFO: [Synth 8-4471] merging register 'clean_reg[15:0]' into 'clean_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:44]
INFO: [Synth 8-4471] merging register 'send_pending_reg[15:0]' into 'send_pending_i_reg[15:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:121]
INFO: [Synth 8-4471] merging register 'busy_sig_reg' into 'busy_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:43]
INFO: [Synth 8-4471] merging register 'sending_reg' into 'sending_i_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:158]
INFO: [Synth 8-4471] merging register 'write_sig_reg[3:0]' into 'write_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:41]
INFO: [Synth 8-4471] merging register 'send_sig_reg[3:0]' into 'send_i_reg[3:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (31#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:32]
INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:52]
	Parameter INTERNAL_ONLY bound to: 1'b0 
INFO: [Synth 8-4471] merging register 'rxram_busy_sig_reg' into 'rxram_busy_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:72]
INFO: [Synth 8-4471] merging register 'rxram_end_addr_sig_reg[12:0]' into 'rxram_end_addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:114]
INFO: [Synth 8-4471] merging register 'addr_sig_reg[12:0]' into 'addr_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:74]
INFO: [Synth 8-4471] merging register 'byteswapping_reg' into 'byteswapping_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:151]
INFO: [Synth 8-4471] merging register 'mac_tx_data_sig_reg[7:0]' into 'mac_tx_data_int_reg[7:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:75]
INFO: [Synth 8-4471] merging register 'next_state_reg[2:0]' into 'state_reg[2:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:219]
INFO: [Synth 8-4471] merging register 'rxram_active_reg' into 'rxram_active_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:104]
INFO: [Synth 8-4471] merging register 'udpram_active_reg' into 'udpram_active_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:174]
INFO: [Synth 8-4471] merging register 'counting_reg' into 'counting_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:130]
INFO: [Synth 8-4471] merging register 'prefetch_reg' into 'prefetch_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:184]
INFO: [Synth 8-4471] merging register 'mac_tx_last_sig_reg' into 'mac_tx_last_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:76]
INFO: [Synth 8-4471] merging register 'mac_tx_valid_sig_reg' into 'mac_tx_valid_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:77]
INFO: [Synth 8-4471] merging register 'set_addr_reg' into 'set_addr_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:127]
INFO: [Synth 8-4471] merging register 'addr_to_set_reg[12:0]' into 'addr_to_set_int_reg[12:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:128]
INFO: [Synth 8-4471] merging register 'default_mode.udpram_busy_sig_reg' into 'default_mode.udpram_busy_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:73]
INFO: [Synth 8-4471] merging register 'default_mode.udp_short_sig_reg' into 'default_mode.short_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:79]
INFO: [Synth 8-4471] merging register 'default_mode.send_special_reg' into 'default_mode.send_special_int_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:170]
INFO: [Synth 8-4471] merging register 'default_mode.special_reg[7:0]' into 'default_mode.special_int_reg[7:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:171]
INFO: [Synth 8-4471] merging register 'default_mode.last_udpram_active_reg' into 'default_mode.last_udpram_active_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:472]
INFO: [Synth 8-4471] merging register 'default_mode.udp_counting_reg' into 'default_mode.counting_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:477]
INFO: [Synth 8-4471] merging register 'default_mode.udp_counter_reg[4:0]' into 'default_mode.counter_reg[4:0]' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:482]
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (32#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:52]
INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:35]
	Parameter BUFWIDTH bound to: 4 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (33#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:35]
INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:43]
	Parameter BUFWIDTH bound to: 4 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:46]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:48]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:49]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (34#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:43]
INFO: [Synth 8-256] done synthesizing module 'UDP_if' (35#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:67]
INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60]
INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'transactor_if' (36#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57]
INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65]
INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (37#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65]
INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53]
INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (38#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53]
INFO: [Synth 8-256] done synthesizing module 'transactor' (39#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60]
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (40#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:67]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 'ibufd40Mclk' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:849]
INFO: [Synth 8-113] binding component instance 'bufg40M' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:855]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 'ibufdraw40Mclk' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:860]
INFO: [Synth 8-113] binding component instance 'bufgraw40M' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:866]
INFO: [Synth 8-638] synthesizing module 'slaves' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/slaves_FTM_control.vhd:120]
	Parameter N_TXS bound to: 16 - type: integer 
	Parameter N_RXS bound to: 16 - type: integer 
	Parameter XML_VERSION bound to: 50397188 - type: integer 
	Parameter XML_HASH bound to: 189754642 - type: integer 
	Parameter GLOBAL_FWVERSION bound to: 0 - type: integer 
	Parameter GLOBAL_FWHASH bound to: 43215176 - type: integer 
	Parameter GLOBAL_FWDATE bound to: 268771362 - type: integer 
	Parameter GLOBAL_FWTIME bound to: 2232386 - type: integer 
	Parameter FTM_FWHASH bound to: 256428398 - type: integer 
	Parameter FTM_FWVERSION bound to: 50528257 - type: integer 
	Parameter IPBUS_LIB_FWHASH bound to: 0 - type: integer 
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:31]
	Parameter NSLV bound to: 18 - type: integer 
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter SEL_WIDTH bound to: 5 - type: integer 
	Parameter GENERATE_ILA bound to: 0 - type: bool 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (41#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:31]
INFO: [Synth 8-638] synthesizing module 'ipbus_ftm_fpga_id_version' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_ftm_fpga_id_version.vhd:35]
	Parameter XML_VERSION bound to: 50397188 - type: integer 
	Parameter XML_HASH bound to: 189754642 - type: integer 
	Parameter GLOBAL_FWVERSION bound to: 0 - type: integer 
	Parameter GLOBAL_FWHASH bound to: 43215176 - type: integer 
	Parameter GLOBAL_FWDATE bound to: 268771362 - type: integer 
	Parameter GLOBAL_FWTIME bound to: 2232386 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_ftm_fpga_id_version' (42#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_ftm_fpga_id_version.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
	Parameter N_CTRL bound to: 2 - type: integer 
	Parameter N_STAT bound to: 1 - type: integer 
	Parameter SWAP_ORDER bound to: 0 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (43#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
INFO: [Synth 8-638] synthesizing module 'ipbus_spi32' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/ipbus_spi32.vhd:43]
	Parameter BYTE_SPI bound to: 0 - type: bool 
	Parameter ADDR_WIDTH bound to: 6 - type: integer 
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
	Parameter NSLV bound to: 4 - type: integer 
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter DECODE_BASE bound to: 4 - type: integer 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch' (44#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
	Parameter N_CTRL bound to: 4 - type: integer 
	Parameter N_STAT bound to: 1 - type: integer 
	Parameter SWAP_ORDER bound to: 0 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (44#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
INFO: [Synth 8-638] synthesizing module 'ipbus_watchdog' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_watchdog.vhd:34]
	Parameter TIMER_WIDTH bound to: 20 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_watchdog' (45#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_watchdog.vhd:34]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
	Parameter ADDR_WIDTH bound to: 4 - type: integer 
	Parameter DATA_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram' (46#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
	Parameter ADDR_WIDTH bound to: 4 - type: integer 
	Parameter DATA_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized0' (46#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
INFO: [Synth 8-638] synthesizing module 'command_sync' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/command_sync.vhd:20]
INFO: [Synth 8-256] done synthesizing module 'command_sync' (47#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/command_sync.vhd:20]
INFO: [Synth 8-638] synthesizing module 'spi32_8_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:39]
	Parameter ADDR_WIDTH bound to: 5 - type: integer 
	Parameter BYTE_SPI bound to: 0 - type: bool 
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:57]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:59]
INFO: [Synth 8-256] done synthesizing module 'spi32_8_control' (48#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:39]
INFO: [Synth 8-638] synthesizing module 'clock_pulse' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/clock_pulse.vhd:18]
INFO: [Synth 8-256] done synthesizing module 'clock_pulse' (49#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/clock_pulse.vhd:18]
INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/ipbus_spi32.vhd:43]
INFO: [Synth 8-638] synthesizing module 'ipbus_spi32__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/ipbus_spi32.vhd:43]
	Parameter BYTE_SPI bound to: 1 - type: bool 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
	Parameter NSLV bound to: 4 - type: integer 
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter DECODE_BASE bound to: 7 - type: integer 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized0' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
	Parameter ADDR_WIDTH bound to: 7 - type: integer 
	Parameter DATA_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized1' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
	Parameter ADDR_WIDTH bound to: 7 - type: integer 
	Parameter DATA_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized2' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
INFO: [Synth 8-638] synthesizing module 'spi32_8_control__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:39]
	Parameter ADDR_WIDTH bound to: 8 - type: integer 
	Parameter BYTE_SPI bound to: 1 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'spi32_8_control__parameterized0' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/spi32_8_control.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32__parameterized0' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/IPbus_SPI/hdl/ipbus_spi32.vhd:43]
INFO: [Synth 8-638] synthesizing module 'ipbus_con_xcvr_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_con_xcvr_control.vhd:35]
	Parameter N_2QUADS bound to: 2 - type: integer 
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:31]
	Parameter NSLV bound to: 2 - type: integer 
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter SEL_WIDTH bound to: 5 - type: integer 
	Parameter GENERATE_ILA bound to: 0 - type: bool 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:31]
INFO: [Synth 8-638] synthesizing module 'ipbus_con_2quad_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_con_2quad_control.vhd:31]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
	Parameter N_CTRL bound to: 2 - type: integer 
	Parameter N_STAT bound to: 4 - type: integer 
	Parameter SWAP_ORDER bound to: 0 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (50#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
INFO: [Synth 8-256] done synthesizing module 'ipbus_con_2quad_control' (51#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_con_2quad_control.vhd:31]
INFO: [Synth 8-256] done synthesizing module 'ipbus_con_xcvr_control' (52#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_con_xcvr_control.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_ftm_buffer_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_ftm_buffer_control.vhd:39]
	Parameter ADDR_WIDTH bound to: 13 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_ftm_buffer_control.vhd:58]
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_ftm_buffer_control.vhd:59]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'Sink_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_ftm_buffer_control.vhd:165]
INFO: [Synth 8-256] done synthesizing module 'ipbus_ftm_buffer_control' (53#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_ftm_buffer_control.vhd:39]
INFO: [Synth 8-638] synthesizing module 'ipbus_ttcinfo' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_ttcinfo.vhd:50]
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
	Parameter NSLV bound to: 2 - type: integer 
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter DECODE_BASE bound to: 3 - type: integer 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized1' (53#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_ttcinfo_control' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_ttcinfo_control.vhd:41]
INFO: [Synth 8-256] done synthesizing module 'ipbus_ttcinfo_control' (54#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_ttcinfo_control.vhd:41]
INFO: [Synth 8-638] synthesizing module 'delay_128' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/delay_128.vhd:24]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'LSB_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/delay_128.vhd:37]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'add32_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/delay_128.vhd:49]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'add32a_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/delay_128.vhd:67]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'add32b_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/delay_128.vhd:79]
INFO: [Synth 8-256] done synthesizing module 'delay_128' (55#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/delay_128.vhd:24]
INFO: [Synth 8-638] synthesizing module 'ttcinfo_source' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_source.vhd:34]
	Parameter CRC_REVERSE_BIT_ORDER bound to: 0 - type: bool 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_source.vhd:43]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_source.vhd:44]
INFO: [Synth 8-638] synthesizing module 'frame_sync_ttc_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/frame_sync_ttc_tx.vhd:20]
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/frame_sync_ttc_tx.vhd:24]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/frame_sync_ttc_tx.vhd:25]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/frame_sync_ttc_tx.vhd:26]
INFO: [Synth 8-256] done synthesizing module 'frame_sync_ttc_tx' (56#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/frame_sync_ttc_tx.vhd:20]
INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d32.vhd:20]
	Parameter REVERSE_BIT_ORDER bound to: 0 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (57#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/LatomeCRC/hdl/osum_crc9d32.vhd:20]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_source.vhd:223]
WARNING: [Synth 8-5858] RAM ttcinfo_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-5858] RAM ttcreg_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ttcinfo_source' (58#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_source.vhd:34]
INFO: [Synth 8-638] synthesizing module 'ttcinfo_sink' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:35]
	Parameter CRC_REVERSE_BIT_ORDER bound to: 0 - type: bool 
WARNING: [Synth 8-614] signal 'data_int' is read in the process but is not in the sensitivity list [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:120]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'then_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:182]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'then_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:182]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'then_delay' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:182]
INFO: [Synth 8-3491] module 'ila_tx' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/ila_tx_stub.vhdl:5' bound to instance 'ttc_sink' of component 'ila_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:240]
WARNING: [Synth 8-3936] Found unconnected internal register 'data_int_reg[ctrl]' and it is trimmed from '4' to '1' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:85]
INFO: [Synth 8-256] done synthesizing module 'ttcinfo_sink' (59#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ttcinfo_sink.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_counter_array' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_counter_array.vhd:29]
	Parameter N_BITS bound to: 16 - type: integer 
	Parameter N_COUNTERS bound to: 2 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_counter_array' (60#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_counter_array.vhd:29]
INFO: [Synth 8-256] done synthesizing module 'ipbus_ttcinfo' (61#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_ttcinfo.vhd:50]
INFO: [Synth 8-638] synthesizing module 'ipbus_mgt_source' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_source.vhd:36]
	Parameter NSLV bound to: 16 - type: integer 
	Parameter DPRAM_ADDR_WIDTH bound to: 14 - type: integer 
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
	Parameter NSLV bound to: 16 - type: integer 
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter DECODE_BASE bound to: 16 - type: integer 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized2' (61#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_data_source' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_source.vhd:43]
	Parameter DPRAM_ADDR_WIDTH bound to: 14 - type: integer 
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-638] synthesizing module 'framing_sync_logic' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:22]
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:26]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:27]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:28]
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:30]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:32]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:33]
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:35]
INFO: [Synth 8-256] done synthesizing module 'framing_sync_logic' (62#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/framing_sync_logic.vhd:22]
INFO: [Synth 8-638] synthesizing module 'tx_ram_pointer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/tx_ram_pointer.vhd:21]
	Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'tx_ram_pointer' (63#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/tx_ram_pointer.vhd:21]
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_merge' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_fabric_merge.vhd:29]
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter INTERLEAVE bound to: 0 - type: bool 
	Parameter DPRAM_ADDR_WIDTH bound to: 14 - type: integer 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_merge' (64#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_fabric_merge.vhd:29]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_frame_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_frame_init.vhd:35]
	Parameter ADDR_WIDTH bound to: 13 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_frame_init' (65#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_frame_init.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_ctrl_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_ctrl_init.vhd:31]
	Parameter ADDR_WIDTH bound to: 13 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_ctrl_init' (66#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_dpram_ctrl_init.vhd:31]
INFO: [Synth 8-638] synthesizing module 'dummy_frame_generator' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/dummy_frame_generator_c.vhd:32]
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'dummy_frame_generator' (67#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/dummy_frame_generator_c.vhd:32]
INFO: [Synth 8-256] done synthesizing module 'ipbus_data_source' (68#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_source.vhd:43]
INFO: [Synth 8-256] done synthesizing module 'ipbus_mgt_source' (69#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_source.vhd:36]
INFO: [Synth 8-638] synthesizing module 'ipbus_mgt_sink' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_sink.vhd:35]
	Parameter NSLV bound to: 16 - type: integer 
	Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer 
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-638] synthesizing module 'ipbus_data_sink' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_sink.vhd:35]
	Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer 
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_sink.vhd:40]
INFO: [Synth 8-638] synthesizing module 'rx_framing_sync_logic' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_framing_sync_logic.vhd:30]
	Parameter FRAME_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rx_framing_sync_logic' (70#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_framing_sync_logic.vhd:30]
INFO: [Synth 8-638] synthesizing module 'rx_ram_pointer' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_ram_pointer.vhd:27]
	Parameter DPRAM_ADDR_WIDTH bound to: 13 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_ram_pointer.vhd:21]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_ram_pointer.vhd:32]
INFO: [Synth 8-256] done synthesizing module 'rx_ram_pointer' (71#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/rx_ram_pointer.vhd:27]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
	Parameter ADDR_WIDTH bound to: 13 - type: integer 
	Parameter DATA_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized3' (71#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
INFO: [Synth 8-256] done synthesizing module 'ipbus_data_sink' (72#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_data_sink.vhd:35]
INFO: [Synth 8-256] done synthesizing module 'ipbus_mgt_sink' (73#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/DSS_buffer/hdl/ipbus_mgt_sink.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
	Parameter N_CTRL bound to: 1 - type: integer 
	Parameter N_STAT bound to: 4 - type: integer 
	Parameter SWAP_ORDER bound to: 0 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized2' (73#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68]
INFO: [Synth 8-638] synthesizing module 'ipbus_self_configure' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/ipbus_self_configure.vhd:22]
INFO: [Synth 8-638] synthesizing module 'reconfigure_fsm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:16]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:21]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:22]
INFO: [Synth 8-5534] Detected attribute (* dont_touch = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:23]
	Parameter DEVICE_ID bound to: 32'b00000011011001010001000010010011 
	Parameter ICAP_WIDTH bound to: X32 - type: string 
	Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string 
INFO: [Synth 8-113] binding component instance 'ICAPE2_inst' to cell 'ICAPE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:64]
INFO: [Synth 8-256] done synthesizing module 'reconfigure_fsm' (74#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/reconfigure_fsm.vhd:16]
INFO: [Synth 8-256] done synthesizing module 'ipbus_self_configure' (75#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Configure/hdl/ipbus_self_configure.vhd:22]
INFO: [Synth 8-638] synthesizing module 'ipbus_xadc_array' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/ipbus_xadc_array.vhd:25]
INFO: [Synth 8-638] synthesizing module 'xadc_ftm' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/xadc_ftm.vhd:45]
	Parameter INIT_40 bound to: 16'b1001000000000000 
	Parameter INIT_41 bound to: 16'b0010111011110000 
	Parameter INIT_42 bound to: 16'b0000001100000000 
	Parameter INIT_43 bound to: 16'b0010111011110000 
	Parameter INIT_44 bound to: 16'b0000000000000000 
	Parameter INIT_45 bound to: 16'b0000000000000000 
	Parameter INIT_46 bound to: 16'b0000000000000001 
	Parameter INIT_47 bound to: 16'b0000000000000000 
	Parameter INIT_48 bound to: 16'b0100011100000001 
	Parameter INIT_49 bound to: 16'b0000000000001111 
	Parameter INIT_4A bound to: 16'b0000000000000000 
	Parameter INIT_4B bound to: 16'b0000000000000000 
	Parameter INIT_4C bound to: 16'b0000000000000000 
	Parameter INIT_4D bound to: 16'b0000000000000000 
	Parameter INIT_4E bound to: 16'b0000000000000000 
	Parameter INIT_4F bound to: 16'b0000000000000000 
	Parameter INIT_50 bound to: 16'b1011010111101101 
	Parameter INIT_51 bound to: 16'b0101100110011001 
	Parameter INIT_52 bound to: 16'b1010000101000111 
	Parameter INIT_53 bound to: 16'b1101110111011101 
	Parameter INIT_54 bound to: 16'b1010100100111010 
	Parameter INIT_55 bound to: 16'b0101000100010001 
	Parameter INIT_56 bound to: 16'b1001000111101011 
	Parameter INIT_57 bound to: 16'b1010111001001110 
	Parameter INIT_58 bound to: 16'b0101100110011001 
	Parameter INIT_59 bound to: 16'b0000000000000000 
	Parameter INIT_5A bound to: 16'b0000000000000000 
	Parameter INIT_5B bound to: 16'b0000000000000000 
	Parameter INIT_5C bound to: 16'b0000000000000000 
	Parameter INIT_5D bound to: 16'b0000000000000000 
	Parameter INIT_5E bound to: 16'b0000000000000000 
	Parameter INIT_5F bound to: 16'b0000000000000000 
	Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 
	Parameter IS_DCLK_INVERTED bound to: 1'b0 
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
	Parameter SIM_MONITOR_FILE bound to: design.txt - type: string 
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/xadc_ftm.vhd:98]
INFO: [Synth 8-256] done synthesizing module 'xadc_ftm' (76#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/xadc_ftm.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'ipbus_xadc_array' (77#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/xadc/hdl/ipbus_xadc_array.vhd:25]
INFO: [Synth 8-638] synthesizing module 'ipbus_i2c_master_arb' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_i2c_master_arb.vhd:27]
	Parameter addr_width bound to: 0 - type: integer 
INFO: [Synth 8-638] synthesizing module 'ipbus_i2c_master' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/ipbus_i2c_master.vhd:25]
	Parameter addr_width bound to: 0 - type: integer 
INFO: [Synth 8-638] synthesizing module 'i2c_master_top' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:111]
	Parameter ARST_LVL bound to: 0 - type: integer 
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:258]
INFO: [Synth 8-3491] module 'i2c_master_byte_ctrl' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:80' bound to instance 'byte_controller' of component 'i2c_master_byte_ctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:283]
INFO: [Synth 8-638] synthesizing module 'i2c_master_byte_ctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'i2c_master_byte_ctrl' (78#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:106]
INFO: [Synth 8-3491] module 'i2c_master_bit_ctrl' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:122' bound to instance 'bit_controller' of component 'i2c_master_bit_ctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:303]
INFO: [Synth 8-638] synthesizing module 'i2c_master_bit_ctrl' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:146]
INFO: [Synth 8-256] done synthesizing module 'i2c_master_bit_ctrl' (79#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:146]
INFO: [Synth 8-3491] module 'i2c_master_registers' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:81' bound to instance 'registers' of component 'i2c_master_registers' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:322]
INFO: [Synth 8-638] synthesizing module 'i2c_master_registers' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:101]
INFO: [Synth 8-256] done synthesizing module 'i2c_master_registers' (80#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:101]
INFO: [Synth 8-256] done synthesizing module 'i2c_master_top' (81#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:111]
INFO: [Synth 8-256] done synthesizing module 'ipbus_i2c_master' (82#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/ipbus_i2c_master.vhd:25]
INFO: [Synth 8-638] synthesizing module 'ipbus_watchdog__parameterized0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_watchdog.vhd:34]
	Parameter TIMER_WIDTH bound to: 10 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_watchdog__parameterized0' (82#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_watchdog.vhd:34]
INFO: [Synth 8-256] done synthesizing module 'ipbus_i2c_master_arb' (83#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_i2c_master_arb.vhd:27]
INFO: [Synth 8-638] synthesizing module 'eeprom_addr_reader' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/eeprom_addr_reader.vhd:59]
	Parameter ADDRESS_WORD bound to: 8'b00000000 
	Parameter N_WORDS bound to: 8'b00000111 
INFO: [Synth 8-256] done synthesizing module 'eeprom_addr_reader' (84#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/eeprom_addr_reader.vhd:59]
INFO: [Synth 8-638] synthesizing module 'ipbus_module_playback' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_module_playback.vhd:42]
	Parameter INIT bound to: 32'b00000000000000000000000000000000 
	Parameter IS_CLK_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'DelayComp' to cell 'SRLC32E' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_module_playback.vhd:195]
INFO: [Synth 8-256] done synthesizing module 'ipbus_module_playback' (85#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_module_playback.vhd:42]
INFO: [Synth 8-638] synthesizing module 'ipbus_L1A_Generator' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_L1A_Generator.vhd:30]
INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized3' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
	Parameter NSLV bound to: 2 - type: integer 
	Parameter STROBE_GAP bound to: 0 - type: bool 
	Parameter DECODE_BASE bound to: 12 - type: integer 
WARNING: [Synth 8-5858] RAM ipb_to_slaves_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized3' (85#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/ipbus_fabric_branch.vhd:35]
INFO: [Synth 8-638] synthesizing module 'ipbus_dpram__parameterized4' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
	Parameter ADDR_WIDTH bound to: 12 - type: integer 
	Parameter DATA_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram__parameterized4' (85#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62]
INFO: [Synth 8-638] synthesizing module 'L1A_Gen' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/L1A_Gen.vhd:30]
	Parameter ADDR_WIDTH bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'L1A_Gen' (86#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/L1A_Gen.vhd:30]
INFO: [Synth 8-256] done synthesizing module 'ipbus_L1A_Generator' (87#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/ipbus_L1A_Generator.vhd:30]
INFO: [Synth 8-256] done synthesizing module 'slaves' (88#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/FTM/Control/hdl/slaves_FTM_control.vhd:120]
INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:996]
INFO: [Synth 8-638] synthesizing module 'startup' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/startup.vhd:15]
	Parameter PROG_USR bound to: FALSE - type: string 
	Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double 
INFO: [Synth 8-113] binding component instance 'STARTUPE2_inst' to cell 'STARTUPE2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/startup.vhd:27]
INFO: [Synth 8-256] done synthesizing module 'startup' (89#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/Misc/hdl/startup.vhd:15]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter DQS_BIAS bound to: FALSE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 'ibufgds0' to cell 'IBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1055]
INFO: [Synth 8-638] synthesizing module 'ttc_fmc' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/ipbus_ttc_fmc_wrapper.vhd:47]
INFO: [Synth 8-638] synthesizing module 'pll_160MHz' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/pll_160MHz.vhd:86]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 25.000000 - type: double 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double 
	Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLKIN1_PERIOD bound to: 6.250000 - type: double 
	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double 
	Parameter CLKOUT0_DIVIDE_F bound to: 6.250000 - type: double 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT5_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double 
	Parameter CLKOUT6_USE_FINE_PS bound to: 0 - type: bool 
	Parameter CLOCK_HOLD bound to: 0 - type: bool 
	Parameter COMPENSATION bound to: ZHOLD - type: string 
	Parameter DIVCLK_DIVIDE bound to: 4 - type: integer 
	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
	Parameter REF_JITTER2 bound to: 0.000000 - type: double 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
INFO: [Synth 8-113] binding component instance 'mmcm_adv_inst' to cell 'MMCM_ADV' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/pll_160MHz.vhd:127]
INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/pll_160MHz.vhd:187]
INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/pll_160MHz.vhd:193]
INFO: [Synth 8-256] done synthesizing module 'pll_160MHz' (90#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/pll_160MHz.vhd:86]
INFO: [Synth 8-638] synthesizing module 'ttc_decoder_core' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/ttc_decoder_core.vhd:128]
INFO: [Synth 8-638] synthesizing module 'cdr2a_b_clk' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/cdr2a_b_clk.vhd:97]
	Parameter pll_locked_delay bound to: 200 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'cdr2a_b_clk' (91#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/cdr2a_b_clk.vhd:97]
INFO: [Synth 8-638] synthesizing module 'serialb_com' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/TTC_hamming_decoder_alme.vhd:56]
	Parameter include_hamming bound to: 1 - type: bool 
INFO: [Synth 8-256] done synthesizing module 'serialb_com' (92#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/TTC_hamming_decoder_alme.vhd:56]
INFO: [Synth 8-256] done synthesizing module 'ttc_decoder_core' (93#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/decoder_release_1.1/ttc_decoder_core.vhd:128]
INFO: [Synth 8-256] done synthesizing module 'ttc_fmc' (94#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/common/TTC_FMC/hdl/ipbus_ttc_fmc_wrapper.vhd:47]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 'ibufdcdrclk' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1090]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 'ibufdfmcclk' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1096]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter DIFF_TERM bound to: 0 - type: bool 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: 1 - type: bool 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-113] binding component instance 'ibufddata' to cell 'IBUFGDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1102]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'dss1_bcr' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1108]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'dss2_bcr' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1116]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'dss1sync' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1127]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
	Parameter SLEW bound to: SLOW - type: string 
INFO: [Synth 8-113] binding component instance 'dss2sync' to cell 'OBUFDS' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1135]
INFO: [Synth 8-3491] module 'ila_tx' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/.Xil/Vivado-10109-hog-vm0.cern.ch/realtime/ila_tx_stub.vhdl:5' bound to instance 'pll_sync_reset' of component 'ila_tx' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:1144]
WARNING: [Synth 8-3848] Net mgt_source_clk2 in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:327]
WARNING: [Synth 8-3848] Net mgt_sink_data[15][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[15][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[14][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[14][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[13][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[13][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[12][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[12][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[11][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[11][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[10][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[10][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[9][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[9][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[8][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[8][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[7][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[7][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[6][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[6][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[5][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[5][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[4][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[4][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[3][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[3][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[2][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[2][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[1][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[1][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[0][data] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_data[0][ctrl] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:328]
WARNING: [Synth 8-3848] Net mgt_sink_clk2 in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:329]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][qpll1_lock_out] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][qpll1_ref_lost] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][7][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][7][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][7][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][7][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][7][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][6][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][6][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][6][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][6][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][6][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][5][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][5][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][5][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][5][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][5][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][4][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][4][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][4][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][4][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][4][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][3][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][3][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][3][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][3][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][3][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][2][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][2][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][2][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][2][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][2][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][0][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][0][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][0][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][0][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt115_116][channel][0][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][qpll0_lock_out] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][qpll0_ref_lost] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][qpll1_lock_out] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][qpll1_ref_lost] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][7][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][7][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][7][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][7][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][7][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][6][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][6][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][6][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][6][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][6][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][5][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][5][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][5][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][5][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][5][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][4][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][4][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][4][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][4][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][4][rx_disperror] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][3][tx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][3][rx_reset_done] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][3][rx_byteisaligned] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
WARNING: [Synth 8-3848] Net mgt_status[mgt117_118][channel][3][rx_notintable] in module/entity top_ftm_control does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:340]
INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'top_ftm_control' (95#1670) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/top_FTM_Control.vhd:182]
WARNING: [Synth 8-3301] Unused top level parameter/generic DEFAULT_VER
WARNING: [Synth 8-3301] Unused top level parameter/generic DEFAULT_SHA
WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_VER
WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_SHA
WARNING: [Synth 8-3917] design top_ftm_control has port aerr_led_n driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port alert_led_n driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port div_div4 driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port ttcfmc_2de driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port trigger_Inhibit driven by constant 0
WARNING: [Synth 8-3917] design top_ftm_control has port trigger_BGO driven by constant 0
WARNING: [Synth 8-3917] design top_ftm_control has port bridge_reset_n driven by constant 1
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[127]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[126]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[125]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[124]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[123]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[122]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[121]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[120]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[119]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[118]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[117]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[116]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[115]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[114]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[113]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[112]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[111]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[110]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[109]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[108]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[107]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[106]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[105]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[104]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[103]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[102]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[101]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[100]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[99]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[98]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[97]
WARNING: [Synth 8-3331] design ttc_fmc has unconnected port ttc_status[96]
WARNING: [Synth 8-3331] design L1A_Gen has unconnected port reset
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port rst
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][31]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][30]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][29]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][28]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][27]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][26]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][25]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][24]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][23]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][22]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][21]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][20]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][19]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][18]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][17]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][16]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][15]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][14]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][13]
WARNING: [Synth 8-3331] design ipbus_dpram__parameterized4 has unconnected port ipb_in[ipb_addr][12]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][31]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][30]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][29]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][28]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][27]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][26]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][25]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][24]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][23]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][22]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][21]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][20]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][19]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][18]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][17]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][16]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][15]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][14]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][13]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][12]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][11]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][10]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][9]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][8]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][7]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][6]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][5]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][4]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][3]
WARNING: [Synth 8-3331] design ipbus_ctrlreg_v has unconnected port ipbus_in[ipb_addr][2]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][31]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][30]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][29]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][28]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][27]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][26]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][25]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][24]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][23]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][22]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][21]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][20]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][19]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][18]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][17]
WARNING: [Synth 8-3331] design ipbus_module_playback has unconnected port ipb_in[ipb_addr][16]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 2351.508 ; gain = 365.438 ; free physical = 3162 ; free virtual = 21256
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:21 . Memory (MB): peak = 2363.379 ; gain = 377.309 ; free physical = 3186 ; free virtual = 21280
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:21 . Memory (MB): peak = 2363.379 ; gain = 377.309 ; free physical = 3186 ; free virtual = 21280
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2366.348 ; gain = 0.000 ; free physical = 3158 ; free virtual = 21252
INFO: [Netlist 29-17] Analyzing 58 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_rx/ila_rx_in_context.xdc] for cell 'mgt_ttcinfo/rx_data'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_rx/ila_rx_in_context.xdc] for cell 'mgt_ttcinfo/rx_data'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4/mac_fifo_axi4_in_context.xdc] for cell 'eth/fifo'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4/mac_fifo_axi4_in_context.xdc] for cell 'eth/fifo'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/gtwizard_0_in_context.xdc] for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/gtwizard_0_in_context.xdc] for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx/ila_tx_in_context.xdc] for cell 'mgt_ttcinfo/tx_data'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx/ila_tx_in_context.xdc] for cell 'mgt_ttcinfo/tx_data'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx/ila_tx_in_context.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx/ila_tx_in_context.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx/ila_tx_in_context.xdc] for cell 'pll_sync_reset'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx/ila_tx_in_context.xdc] for cell 'pll_sync_reset'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc] for cell 'eth/emac0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc] for cell 'eth/emac0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_ftm_control_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_ftm_control_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:48]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_ftm_control_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_ftm_control_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc:3]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_ftm_control_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_ftm_control_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/ttcinfo_mgt.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/ttcinfo_mgt.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2482.004 ; gain = 0.000 ; free physical = 3017 ; free virtual = 21111
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 35 instances were transformed.
  IBUFGDS => IBUFDS: 6 instances
  MMCME2_BASE => MMCME2_ADV: 1 instance 
  MMCM_ADV => MMCME2_ADV: 1 instance 
  OBUFDS => OBUFDS: 26 instances
  SRL16 => SRL16E: 1 instance 

Constraint Validation Runtime : Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2482.004 ; gain = 0.000 ; free physical = 3017 ; free virtual = 21111
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:43 . Memory (MB): peak = 2482.004 ; gain = 495.934 ; free physical = 3163 ; free virtual = 21257
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:43 . Memory (MB): peak = 2482.004 ; gain = 495.934 ; free physical = 3163 ; free virtual = 21257
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_clk. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 5).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_clk. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 6).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_dv. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 7).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_dv. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 8).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_er. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 9).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_er. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 10).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[0]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 11).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[0]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 12).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[1]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 13).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[1]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 14).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[2]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 15).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[2]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 16).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[3]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 17).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[3]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 18).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[4]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 19).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[4]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 20).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[5]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 21).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[5]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 22).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[6]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 23).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[6]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 24).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[7]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 25).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[7]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 26).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_gtx_clk. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 27).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_gtx_clk. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 28).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_tx_en. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 29).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_tx_en. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 30).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_tx_er. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 31).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_tx_er. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 32).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[0]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 33).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[0]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 34).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[1]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 35).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[1]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 36).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[2]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 37).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[2]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 38).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[3]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 39).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[3]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 40).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[4]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 41).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[4]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 42).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[5]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 43).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[5]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 44).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[6]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 45).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[6]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 46).
Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[7]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 47).
Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[7]. (constraint file  /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii_in_context.xdc, line 48).
Applied set_property DONT_TOUCH = true for mgt_ttcinfo/rx_data. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for eth/fifo. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for pll_sync_reset. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for slaves/ttc_info/ttcin/ttc_sink. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for mgt_ttcinfo/tx_data. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for eth/emac0. (constraint file  auto generated constraint, line ).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:43 . Memory (MB): peak = 2482.004 ; gain = 495.934 ; free physical = 3163 ; free virtual = 21257
---------------------------------------------------------------------------------
WARNING: [Synth 8-3936] Found unconnected internal register 'DataOut_reg' and it is trimmed from '10' to '1' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_master_fifo.vhd:72]
INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "int_data_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "send_buf_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "do_sum_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "clr_sum_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "int_valid_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "int_data_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "send_buf_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "load_buf_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "do_sum_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "clr_sum_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "int_valid_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5587] ROM size for "int_data_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5546] ROM "payload_len" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "addr_to_set_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ipbus_hdr_int" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-3936] Found unconnected internal register 'pkt_rdy_buf_reg' and it is trimmed from '3' to '2' bits. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:128]
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm'
INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'command_sync'
INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control'
INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'pulseSM_reg' in module 'ttcinfo_source'
INFO: [Synth 8-802] inferred FSM for state register 'NEXT_STATE_reg' in module 'reconfigure_fsm'
INFO: [Synth 8-5544] ROM "NEXT_STATE" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'xadc_ftm'
INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_byte_ctrl'
INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_bit_ctrl'
INFO: [Synth 8-5546] ROM "c_state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "cmd_ack" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "scl_oen_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sda_oen_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "c_state" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'timerSM_reg' in module 'L1A_Gen'
INFO: [Synth 8-802] inferred FSM for state register 'hamming.next_state_reg' in module 'serialb_com'
INFO: [Synth 8-5544] ROM "next_state" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "next_state" won't be mapped to RAM because it is too sparse
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 st_idle |                          0000010 |                              000
                st_first |                          1000000 |                              001
                  st_hdr |                          0100000 |                              010
              st_prebody |                          0010000 |                              011
                 st_body |                          0001000 |                              100
                 st_done |                          0000100 |                              101
                  st_gap |                          0000001 |                              110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 st_idle |                           100000 |                              000
                  st_hdr |                           001000 |                              001
                 st_addr |                           010000 |                              010
            st_bus_cycle |                           000010 |                              011
                st_rmw_1 |                           000100 |                              100
                st_rmw_2 |                           000001 |                              101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm'
INFO: [Synth 8-3971] The signal "ipbus_dpram:/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    idle |                             0001 |                               00
                 request |                             0010 |                               01
                    done |                             0100 |                               10
                  iSTATE |                             1000 |                               11
*
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'one-hot' in module 'command_sync'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    idle |                              000 |                              000
             start_frame |                              001 |                              001
                read_mem |                              010 |                              010
                shift_io |                              011 |                              011
               write_mem |                              100 |                              100
               end_frame |                              101 |                              101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control'
INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized2:/ram_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    idle |                              000 |                              000
             start_frame |                              001 |                              001
                read_mem |                              010 |                              010
                shift_io |                              011 |                              011
               write_mem |                              100 |                              100
               end_frame |                              101 |                              101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control__parameterized0'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    idle |                               00 |                               00
                   waitf |                               01 |                               01
                   pulse |                               10 |                               10
                    done |                               11 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'pulseSM_reg' using encoding 'sequential' in module 'ttcinfo_source'
INFO: [Synth 8-3971] The signal "ipbus_dpram_frame_init:/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal "ipbus_dpram_ctrl_init:/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized3:/ram_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    idle |                             0000 |                             0000
                 data_00 |                             0001 |                             0001
                 data_01 |                             0010 |                             0010
                 data_02 |                             0011 |                             0011
                 data_03 |                             0100 |                             0100
                 data_04 |                             0101 |                             0101
                 data_05 |                             0110 |                             0110
                 data_06 |                             0111 |                             0111
                 data_07 |                             1000 |                             1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'NEXT_STATE_reg' using encoding 'sequential' in module 'reconfigure_fsm'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
               init_read |                            00000 |                            00000
           read_waitdrdy |                            00001 |                            00001
          write_waitdrdy |                            00010 |                            00010
              read_reg00 |                            00011 |                            00011
          reg00_waitdrdy |                            00100 |                            00100
              read_reg01 |                            00101 |                            00101
          reg01_waitdrdy |                            00110 |                            00110
              read_reg02 |                            00111 |                            00111
          reg02_waitdrdy |                            01000 |                            01000
              read_reg06 |                            01001 |                            01001
          reg06_waitdrdy |                            01010 |                            01010
              read_reg20 |                            01011 |                            01011
          reg20_waitdrdy |                            01100 |                            01100
              read_reg21 |                            01101 |                            01101
          reg21_waitdrdy |                            01110 |                            01110
              read_reg22 |                            01111 |                            01111
          reg22_waitdrdy |                            10000 |                            10000
              read_reg23 |                            10001 |                            10001
          reg23_waitdrdy |                            10010 |                            10010
              read_reg24 |                            10011 |                            10011
          reg24_waitdrdy |                            10100 |                            10100
              read_reg25 |                            10101 |                            10101
          reg25_waitdrdy |                            10110 |                            10110
              read_reg26 |                            10111 |                            10111
          reg26_waitdrdy |                            11000 |                            11000
              read_reg27 |                            11001 |                            11001
          reg27_waitdrdy |                            11010 |                            11010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'xadc_ftm'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 st_idle |                              000 |                            00000
                st_start |                              001 |                            00001
                 st_read |                              010 |                            00010
                st_write |                              011 |                            00100
                  st_ack |                              100 |                            01000
                 st_stop |                              101 |                            10000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_byte_ctrl'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    idle |                            00000 |                00000000000000000
                 start_a |                            00001 |                00000000000000001
                 start_b |                            00010 |                00000000000000010
                 start_c |                            00011 |                00000000000000100
                 start_d |                            00100 |                00000000000001000
                 start_e |                            00101 |                00000000000010000
                  stop_a |                            00110 |                00000000000100000
                  stop_b |                            00111 |                00000000001000000
                  stop_c |                            01000 |                00000000010000000
                  stop_d |                            01001 |                00000000100000000
                    wr_a |                            01010 |                00010000000000000
                    wr_b |                            01011 |                00100000000000000
                    wr_c |                            01100 |                01000000000000000
                    wr_d |                            01101 |                10000000000000000
                    rd_a |                            01110 |                00000001000000000
                    rd_b |                            01111 |                00000010000000000
                    rd_c |                            10000 |                00000100000000000
                    rd_d |                            10001 |                00001000000000000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_bit_ctrl'
INFO: [Synth 8-3971] The signal "ipbus_dpram__parameterized4:/ram_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 waiting |                              000 |                              000
                 readmem |                              001 |                              001
                    done |                              010 |                              100
                   again |                              011 |                              011
                  timing |                              100 |                              010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'timerSM_reg' using encoding 'sequential' in module 'L1A_Gen'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                              000 |                              000
                   s_fmt |                              001 |                              001
              s_get_data |                              010 |                              010
         s_get_broadcast |                              011 |                              011
                  s_stop |                              100 |                              100
                 s_error |                              101 |                              101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'hamming.next_state_reg' using encoding 'sequential' in module 'serialb_com'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:37 ; elapsed = 00:00:54 . Memory (MB): peak = 2482.008 ; gain = 495.938 ; free physical = 3137 ; free virtual = 21237
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+----------------------+------------+----------+
|      |RTL Partition         |Replication |Instances |
+------+----------------------+------------+----------+
|1     |clocks_7s_extphy__GC0 |           1|       132|
|2     |top_ftm_control__GCB0 |           1|     38231|
|3     |top_ftm_control__GCB1 |           1|     19900|
|4     |top_ftm_control__GCB3 |           1|        11|
+------+----------------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     32 Bit       Adders := 4     
	   2 Input     31 Bit       Adders := 6     
	   2 Input     24 Bit       Adders := 1     
	   2 Input     16 Bit       Adders := 5     
	   2 Input     13 Bit       Adders := 3     
	   2 Input     12 Bit       Adders := 1     
	   2 Input      9 Bit       Adders := 5     
	   2 Input      8 Bit       Adders := 10    
	   2 Input      7 Bit       Adders := 1     
	   2 Input      6 Bit       Adders := 9     
	   3 Input      6 Bit       Adders := 4     
	   2 Input      5 Bit       Adders := 7     
	   2 Input      4 Bit       Adders := 6     
	   2 Input      3 Bit       Adders := 6     
	   2 Input      2 Bit       Adders := 38    
+---XORs : 
	   2 Input     16 Bit         XORs := 1     
	   4 Input     16 Bit         XORs := 1     
	   2 Input      7 Bit         XORs := 1     
	   2 Input      5 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 44    
	   3 Input      1 Bit         XORs := 9     
	   9 Input      1 Bit         XORs := 6     
	   4 Input      1 Bit         XORs := 10    
	  21 Input      1 Bit         XORs := 2     
	  15 Input      1 Bit         XORs := 2     
	  10 Input      1 Bit         XORs := 6     
	  19 Input      1 Bit         XORs := 2     
	  14 Input      1 Bit         XORs := 3     
	  12 Input      1 Bit         XORs := 4     
	   7 Input      1 Bit         XORs := 2     
	   8 Input      1 Bit         XORs := 4     
	  35 Input      1 Bit         XORs := 1     
+---Registers : 
	              128 Bit    Registers := 7     
	              120 Bit    Registers := 1     
	              112 Bit    Registers := 1     
	               80 Bit    Registers := 2     
	               64 Bit    Registers := 1     
	               56 Bit    Registers := 1     
	               48 Bit    Registers := 4     
	               45 Bit    Registers := 2     
	               42 Bit    Registers := 4     
	               40 Bit    Registers := 1     
	               39 Bit    Registers := 2     
	               38 Bit    Registers := 1     
	               36 Bit    Registers := 1     
	               34 Bit    Registers := 1     
	               32 Bit    Registers := 126   
	               31 Bit    Registers := 6     
	               24 Bit    Registers := 3     
	               22 Bit    Registers := 1     
	               20 Bit    Registers := 2     
	               16 Bit    Registers := 63    
	               14 Bit    Registers := 1     
	               13 Bit    Registers := 24    
	               12 Bit    Registers := 7     
	               10 Bit    Registers := 7     
	                9 Bit    Registers := 18    
	                8 Bit    Registers := 62    
	                7 Bit    Registers := 6     
	                6 Bit    Registers := 18    
	                5 Bit    Registers := 13    
	                4 Bit    Registers := 62    
	                3 Bit    Registers := 49    
	                2 Bit    Registers := 46    
	                1 Bit    Registers := 944   
+---RAMs : 
	             256K Bit         RAMs := 33    
	             128K Bit         RAMs := 1     
	              64K Bit         RAMs := 4     
	              32K Bit         RAMs := 17    
	               4K Bit         RAMs := 2     
	              512 Bit         RAMs := 2     
	              320 Bit         RAMs := 2     
+---Muxes : 
	   2 Input    128 Bit        Muxes := 8     
	   4 Input    128 Bit        Muxes := 1     
	   2 Input    120 Bit        Muxes := 1     
	   2 Input    112 Bit        Muxes := 1     
	   2 Input     80 Bit        Muxes := 4     
	  14 Input     64 Bit        Muxes := 2     
	   2 Input     64 Bit        Muxes := 1     
	   2 Input     56 Bit        Muxes := 1     
	   3 Input     56 Bit        Muxes := 1     
	   2 Input     48 Bit        Muxes := 4     
	   5 Input     48 Bit        Muxes := 1     
	   6 Input     42 Bit        Muxes := 2     
	   2 Input     42 Bit        Muxes := 3     
	   3 Input     42 Bit        Muxes := 1     
	   5 Input     40 Bit        Muxes := 1     
	   2 Input     39 Bit        Muxes := 6     
	   6 Input     39 Bit        Muxes := 2     
	   3 Input     38 Bit        Muxes := 1     
	   3 Input     36 Bit        Muxes := 1     
	   3 Input     34 Bit        Muxes := 1     
	   2 Input     32 Bit        Muxes := 124   
	   8 Input     32 Bit        Muxes := 1     
	   4 Input     32 Bit        Muxes := 17    
	   3 Input     32 Bit        Muxes := 4     
	   9 Input     32 Bit        Muxes := 1     
	   5 Input     32 Bit        Muxes := 1     
	   6 Input     32 Bit        Muxes := 1     
	   2 Input     31 Bit        Muxes := 12    
	   2 Input     24 Bit        Muxes := 4     
	   5 Input     24 Bit        Muxes := 2     
	   3 Input     22 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 52    
	   7 Input     16 Bit        Muxes := 4     
	   4 Input     16 Bit        Muxes := 6     
	   8 Input     16 Bit        Muxes := 1     
	   5 Input     16 Bit        Muxes := 1     
	  14 Input     16 Bit        Muxes := 3     
	  11 Input     16 Bit        Muxes := 1     
	   6 Input     16 Bit        Muxes := 1     
	  18 Input     16 Bit        Muxes := 4     
	   2 Input     14 Bit        Muxes := 1     
	   2 Input     13 Bit        Muxes := 31    
	   4 Input     13 Bit        Muxes := 2     
	   8 Input     13 Bit        Muxes := 1     
	   3 Input     13 Bit        Muxes := 1     
	   7 Input     13 Bit        Muxes := 1     
	   4 Input     12 Bit        Muxes := 1     
	   2 Input     12 Bit        Muxes := 3     
	   2 Input     10 Bit        Muxes := 10    
	   4 Input     10 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 15    
	   3 Input      8 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 81    
	   6 Input      8 Bit        Muxes := 2     
	  14 Input      8 Bit        Muxes := 2     
	  13 Input      8 Bit        Muxes := 1     
	   5 Input      8 Bit        Muxes := 6     
	   4 Input      8 Bit        Muxes := 1     
	  17 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 12    
	   5 Input      7 Bit        Muxes := 1     
	   7 Input      7 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 30    
	   6 Input      6 Bit        Muxes := 5     
	  27 Input      6 Bit        Muxes := 1     
	   3 Input      6 Bit        Muxes := 1     
	   4 Input      6 Bit        Muxes := 1     
	   8 Input      6 Bit        Muxes := 1     
	   7 Input      6 Bit        Muxes := 1     
	   5 Input      6 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 50    
	   6 Input      5 Bit        Muxes := 1     
	  27 Input      5 Bit        Muxes := 1     
	  24 Input      5 Bit        Muxes := 4     
	  19 Input      5 Bit        Muxes := 1     
	   5 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 64    
	   4 Input      4 Bit        Muxes := 6     
	   9 Input      4 Bit        Muxes := 1     
	   6 Input      4 Bit        Muxes := 5     
	   3 Input      4 Bit        Muxes := 2     
	   5 Input      4 Bit        Muxes := 3     
	   6 Input      3 Bit        Muxes := 2     
	   2 Input      3 Bit        Muxes := 22    
	   3 Input      3 Bit        Muxes := 35    
	  15 Input      3 Bit        Muxes := 4     
	   5 Input      3 Bit        Muxes := 3     
	  58 Input      3 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 3     
	   4 Input      3 Bit        Muxes := 1     
	   7 Input      3 Bit        Muxes := 1     
	   4 Input      2 Bit        Muxes := 3     
	   2 Input      2 Bit        Muxes := 35    
	  27 Input      2 Bit        Muxes := 2     
	   3 Input      2 Bit        Muxes := 2     
	   6 Input      2 Bit        Muxes := 1     
	  17 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 697   
	   3 Input      1 Bit        Muxes := 13    
	   4 Input      1 Bit        Muxes := 30    
	   6 Input      1 Bit        Muxes := 52    
	   9 Input      1 Bit        Muxes := 7     
	  27 Input      1 Bit        Muxes := 16    
	  18 Input      1 Bit        Muxes := 28    
	  14 Input      1 Bit        Muxes := 8     
	   5 Input      1 Bit        Muxes := 9     
	  34 Input      1 Bit        Muxes := 1     
	  10 Input      1 Bit        Muxes := 1     
	  35 Input      1 Bit        Muxes := 1     
	  12 Input      1 Bit        Muxes := 3     
	  11 Input      1 Bit        Muxes := 2     
	  13 Input      1 Bit        Muxes := 9     
	   8 Input      1 Bit        Muxes := 9     
	   7 Input      1 Bit        Muxes := 8     
	  16 Input      1 Bit        Muxes := 9     
	  17 Input      1 Bit        Muxes := 1     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module top_ftm_control 
Detailed RTL Component Info : 
+---XORs : 
	   9 Input      1 Bit         XORs := 2     
	  10 Input      1 Bit         XORs := 2     
+---Registers : 
	                9 Bit    Registers := 4     
	                1 Bit    Registers := 7     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 2     
	   4 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 7     
	   3 Input      1 Bit        Muxes := 1     
Module clock_div 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 3     
Module clocks_7s_extphy 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 7     
Module gtwizard_0_common_reset 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      8 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module gtwizard_0_exdes 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 7     
Module pll_synch 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	                6 Bit    Registers := 1     
	                1 Bit    Registers := 9     
Module mac_arbiter 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   3 Input      8 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 4     
Module UDP_master_if__1 
Detailed RTL Component Info : 
+---Registers : 
	               10 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 24    
	   3 Input      1 Bit        Muxes := 1     
Module UDP_master_fifo__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
	   3 Input      6 Bit       Adders := 2     
	   2 Input      5 Bit       Adders := 2     
+---Registers : 
	                8 Bit    Registers := 1     
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 2     
	                1 Bit    Registers := 8     
+---RAMs : 
	              320 Bit         RAMs := 1     
+---Muxes : 
	   2 Input     10 Bit        Muxes := 5     
	   2 Input      6 Bit        Muxes := 2     
	   2 Input      5 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
Module UDP_master_if 
Detailed RTL Component Info : 
+---Registers : 
	               10 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 24    
	   3 Input      1 Bit        Muxes := 1     
Module UDP_master_fifo 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
	   3 Input      6 Bit       Adders := 2     
	   2 Input      5 Bit       Adders := 2     
+---Registers : 
	                8 Bit    Registers := 1     
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 2     
	                1 Bit    Registers := 8     
+---RAMs : 
	              320 Bit         RAMs := 1     
+---Muxes : 
	   2 Input     10 Bit        Muxes := 5     
	   2 Input      6 Bit        Muxes := 2     
	   2 Input      5 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
Module ipbus_fabric_sel 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 18    
Module ipbus_ftm_fpga_id_version 
Detailed RTL Component Info : 
+---Muxes : 
	   8 Input     32 Bit        Muxes := 1     
Module ipbus_ctrlreg_v 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 6     
	   2 Input      1 Bit        Muxes := 4     
Module ipbus_fabric_branch 
Detailed RTL Component Info : 
+---Muxes : 
	   4 Input     32 Bit        Muxes := 1     
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 4     
Module ipbus_ctrlreg_v__parameterized0 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 4     
	                4 Bit    Registers := 1     
+---Muxes : 
	   4 Input     32 Bit        Muxes := 3     
	   2 Input     32 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 12    
Module ipbus_watchdog 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     31 Bit       Adders := 1     
+---Registers : 
	               31 Bit    Registers := 1     
	               20 Bit    Registers := 1     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input     31 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 5     
Module ipbus_dpram 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              512 Bit         RAMs := 1     
Module ipbus_dpram__parameterized0 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              512 Bit         RAMs := 1     
Module command_sync 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   4 Input      4 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 1     
Module spi32_8_control 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   3 Input     32 Bit        Muxes := 1     
	   6 Input      6 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 1     
	   6 Input      5 Bit        Muxes := 1     
	   6 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 4     
	   6 Input      1 Bit        Muxes := 4     
	   3 Input      1 Bit        Muxes := 1     
Module clock_pulse__2 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	                1 Bit    Registers := 2     
Module ipbus_spi32 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 1     
Module ipbus_fabric_branch__parameterized0 
Detailed RTL Component Info : 
+---Muxes : 
	   4 Input     32 Bit        Muxes := 1     
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 4     
Module ipbus_ctrlreg_v__parameterized0__1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 4     
	                4 Bit    Registers := 1     
+---Muxes : 
	   4 Input     32 Bit        Muxes := 3     
	   2 Input     32 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 12    
Module ipbus_watchdog__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     31 Bit       Adders := 1     
+---Registers : 
	               31 Bit    Registers := 1     
	               20 Bit    Registers := 1     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input     31 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 5     
Module ipbus_dpram__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	               4K Bit         RAMs := 1     
Module ipbus_dpram__parameterized2 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	               4K Bit         RAMs := 1     
Module command_sync__1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   4 Input      4 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 1     
Module spi32_8_control__parameterized0 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      8 Bit       Adders := 2     
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                6 Bit    Registers := 1     
	                1 Bit    Registers := 7     
+---Muxes : 
	   3 Input     32 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 1     
	   6 Input      8 Bit        Muxes := 1     
	   6 Input      6 Bit        Muxes := 1     
	   6 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   6 Input      1 Bit        Muxes := 4     
	   3 Input      1 Bit        Muxes := 4     
Module clock_pulse__1 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	                1 Bit    Registers := 2     
Module ipbus_spi32__parameterized0 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 1     
Module ipbus_fabric_sel__parameterized0 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 4     
Module ipbus_ctrlreg_v__parameterized1__1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 4     
	   4 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 6     
Module ipbus_con_2quad_control__1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 3     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 4     
Module ipbus_ctrlreg_v__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 4     
	   4 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 6     
Module ipbus_con_2quad_control 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 3     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 4     
Module ipbus_ftm_buffer_control 
Detailed RTL Component Info : 
+---Registers : 
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 7     
+---Muxes : 
	   4 Input     12 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_branch__parameterized1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_ttcinfo_control 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	               12 Bit    Registers := 2     
	                8 Bit    Registers := 1     
	                7 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 14    
+---Muxes : 
	   2 Input      1 Bit        Muxes := 8     
Module delay_128__1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module delay_128__2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module delay_128 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module frame_sync_ttc_tx 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module osum_crc9d32 
Detailed RTL Component Info : 
+---XORs : 
	   3 Input      1 Bit         XORs := 3     
	   9 Input      1 Bit         XORs := 2     
	   2 Input      1 Bit         XORs := 11    
	   4 Input      1 Bit         XORs := 3     
	  21 Input      1 Bit         XORs := 1     
	  15 Input      1 Bit         XORs := 1     
	  10 Input      1 Bit         XORs := 2     
	  19 Input      1 Bit         XORs := 1     
	  14 Input      1 Bit         XORs := 1     
	  12 Input      1 Bit         XORs := 1     
	   7 Input      1 Bit         XORs := 1     
+---Registers : 
	                9 Bit    Registers := 1     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 1     
Module ttcinfo_source 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      8 Bit       Adders := 1     
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	               32 Bit    Registers := 6     
	               12 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                4 Bit    Registers := 6     
	                1 Bit    Registers := 3     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 6     
	   2 Input     24 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 2     
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
	   4 Input      1 Bit        Muxes := 1     
Module osum_crc9d32__1 
Detailed RTL Component Info : 
+---XORs : 
	   3 Input      1 Bit         XORs := 3     
	   9 Input      1 Bit         XORs := 2     
	   2 Input      1 Bit         XORs := 11    
	   4 Input      1 Bit         XORs := 3     
	  21 Input      1 Bit         XORs := 1     
	  15 Input      1 Bit         XORs := 1     
	  10 Input      1 Bit         XORs := 2     
	  19 Input      1 Bit         XORs := 1     
	  14 Input      1 Bit         XORs := 1     
	  12 Input      1 Bit         XORs := 1     
	   7 Input      1 Bit         XORs := 1     
+---Registers : 
	                9 Bit    Registers := 1     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 1     
Module ttcinfo_sink 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     12 Bit       Adders := 1     
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	               12 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                2 Bit    Registers := 3     
	                1 Bit    Registers := 15    
+---Muxes : 
	   3 Input     32 Bit        Muxes := 1     
	   2 Input     12 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_counter_array 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 2     
	                1 Bit    Registers := 3     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
Module ipbus_ttcinfo 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
Module clock_pulse 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	                1 Bit    Registers := 2     
Module ipbus_fabric_branch__parameterized2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 16    
Module framing_sync_logic__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__1 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__2 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__2 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__2 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__3 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__3 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__3 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__3 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__3 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__4 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__4 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__4 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__4 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__4 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__5 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__5 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__5 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__5 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__5 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__6 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__6 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__6 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__6 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__6 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__7 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__7 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__7 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__7 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__7 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__8 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__8 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__8 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__8 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__8 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__9 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__9 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__9 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__9 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__9 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__10 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__10 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__10 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__10 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__10 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__11 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__11 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__11 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__11 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__11 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__12 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__12 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__12 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__12 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__12 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__13 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__13 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__13 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__13 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__13 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__14 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__14 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__14 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__14 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__14 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic__15 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge__15 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init__15 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init__15 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source__15 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module framing_sync_logic 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 11    
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_fabric_merge 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_dpram_frame_init 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_dpram_ctrl_init 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ipbus_data_source 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
Module ipbus_fabric_branch__parameterized2__1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 16    
Module rx_framing_sync_logic__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__1 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__2 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__2 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__2 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__3 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__3 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__3 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__3 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__4 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__4 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__4 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__4 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__5 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__5 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__5 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__5 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__6 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__6 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__6 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__6 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__7 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__7 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__7 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__7 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__8 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__8 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__8 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__8 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__9 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__9 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__9 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__9 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__10 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__10 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__10 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__10 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__11 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__11 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__11 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__11 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__12 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__12 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__12 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__12 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__13 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__13 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__13 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__13 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__14 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__14 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__14 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__14 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic__15 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer__15 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3__15 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink__15 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rx_framing_sync_logic 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
+---Muxes : 
	   3 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module rx_ram_pointer 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_dpram__parameterized3 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
Module ipbus_data_sink 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module ipbus_ctrlreg_v__parameterized2 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   4 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 3     
Module ipbus_ctrlreg_v__2 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 6     
	   2 Input      1 Bit        Muxes := 4     
Module reconfigure_fsm 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                1 Bit    Registers := 3     
+---Muxes : 
	   9 Input     32 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 1     
	   9 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
	   9 Input      1 Bit        Muxes := 3     
Module xadc_ftm 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 13    
	                7 Bit    Registers := 1     
	                2 Bit    Registers := 2     
+---Muxes : 
	  27 Input      6 Bit        Muxes := 1     
	  27 Input      5 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 14    
	   2 Input      2 Bit        Muxes := 2     
	  27 Input      2 Bit        Muxes := 2     
	  27 Input      1 Bit        Muxes := 16    
Module ipbus_xadc_array 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
Module ipbus_fabric_branch__parameterized1__2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module i2c_master_byte_ctrl__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 6     
	   6 Input      4 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	  15 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   6 Input      1 Bit        Muxes := 6     
Module i2c_master_bit_ctrl__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     16 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	                1 Bit    Registers := 16    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	  24 Input      5 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 15    
	  18 Input      1 Bit        Muxes := 7     
Module i2c_master_registers__1 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
	                8 Bit    Registers := 3     
	                1 Bit    Registers := 4     
+---Muxes : 
	   7 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 4     
	   2 Input      1 Bit        Muxes := 4     
	   4 Input      1 Bit        Muxes := 2     
Module i2c_master_top__1 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_watchdog__parameterized0__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     31 Bit       Adders := 1     
+---Registers : 
	               31 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input     31 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 5     
Module eeprom_addr_reader 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      8 Bit       Adders := 3     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               64 Bit    Registers := 1     
	                8 Bit    Registers := 4     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	  14 Input     64 Bit        Muxes := 2     
	   2 Input     64 Bit        Muxes := 1     
	  14 Input      8 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   3 Input      4 Bit        Muxes := 1     
	   4 Input      4 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 2     
	   3 Input      3 Bit        Muxes := 3     
	   2 Input      3 Bit        Muxes := 2     
	   3 Input      2 Bit        Muxes := 2     
	  14 Input      1 Bit        Muxes := 8     
	   2 Input      1 Bit        Muxes := 7     
Module ipbus_fabric_branch__parameterized1__3 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module i2c_master_byte_ctrl__2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 6     
	   6 Input      4 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	  15 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   6 Input      1 Bit        Muxes := 6     
Module i2c_master_bit_ctrl__2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     16 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	                1 Bit    Registers := 16    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	  24 Input      5 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 15    
	  18 Input      1 Bit        Muxes := 7     
Module i2c_master_registers__2 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
	                8 Bit    Registers := 3     
	                1 Bit    Registers := 4     
+---Muxes : 
	   7 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 4     
	   2 Input      1 Bit        Muxes := 4     
	   4 Input      1 Bit        Muxes := 2     
Module i2c_master_top__2 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_watchdog__parameterized0__2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     31 Bit       Adders := 1     
+---Registers : 
	               31 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input     31 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 5     
Module ipbus_fabric_branch__parameterized1__4 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module i2c_master_byte_ctrl__3 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 6     
	   6 Input      4 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	  15 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   6 Input      1 Bit        Muxes := 6     
Module i2c_master_bit_ctrl__3 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     16 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	                1 Bit    Registers := 16    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	  24 Input      5 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 15    
	  18 Input      1 Bit        Muxes := 7     
Module i2c_master_registers__3 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
	                8 Bit    Registers := 3     
	                1 Bit    Registers := 4     
+---Muxes : 
	   7 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 4     
	   2 Input      1 Bit        Muxes := 4     
	   4 Input      1 Bit        Muxes := 2     
Module i2c_master_top__3 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_watchdog__parameterized0__3 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     31 Bit       Adders := 1     
+---Registers : 
	               31 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input     31 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 5     
Module ipbus_fabric_branch__parameterized1__1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module i2c_master_byte_ctrl 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 6     
	   6 Input      4 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	  15 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   6 Input      1 Bit        Muxes := 6     
Module i2c_master_bit_ctrl 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     16 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	                1 Bit    Registers := 16    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	  24 Input      5 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 15    
	  18 Input      1 Bit        Muxes := 7     
Module i2c_master_registers 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
	                8 Bit    Registers := 3     
	                1 Bit    Registers := 4     
+---Muxes : 
	   7 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 4     
	   2 Input      1 Bit        Muxes := 4     
	   4 Input      1 Bit        Muxes := 2     
Module i2c_master_top 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module ipbus_watchdog__parameterized0 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     31 Bit       Adders := 1     
+---Registers : 
	               31 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input     31 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 5     
Module ipbus_module_playback 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                3 Bit    Registers := 2     
	                1 Bit    Registers := 11    
+---Muxes : 
	   4 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
Module ipbus_fabric_branch__parameterized3 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module ipbus_ctrlreg_v__1 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 6     
	   2 Input      1 Bit        Muxes := 4     
Module ipbus_dpram__parameterized4 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---RAMs : 
	             128K Bit         RAMs := 1     
Module L1A_Gen 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     32 Bit       Adders := 2     
+---Registers : 
	               32 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   5 Input     32 Bit        Muxes := 1     
	   5 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 1     
	   3 Input      1 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 3     
	   5 Input      1 Bit        Muxes := 3     
Module ipbus_L1A_Generator 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 3     
Module slaves 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 3     
+---Muxes : 
	  19 Input      5 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module cdr2a_b_clk 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      5 Bit       Adders := 1     
	   2 Input      4 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
	   2 Input      2 Bit       Adders := 1     
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	                5 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 2     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 3     
Module serialb_com 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      7 Bit         XORs := 1     
	   2 Input      5 Bit         XORs := 1     
	   3 Input      1 Bit         XORs := 3     
	   4 Input      1 Bit         XORs := 4     
	   8 Input      1 Bit         XORs := 4     
	  14 Input      1 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 5     
	  12 Input      1 Bit         XORs := 2     
	  35 Input      1 Bit         XORs := 1     
+---Registers : 
	               42 Bit    Registers := 1     
	               39 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 8     
+---Muxes : 
	   6 Input     42 Bit        Muxes := 2     
	   2 Input     42 Bit        Muxes := 1     
	   2 Input     39 Bit        Muxes := 6     
	   6 Input     39 Bit        Muxes := 2     
	   2 Input     32 Bit        Muxes := 1     
	  58 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   6 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 8     
	  34 Input      1 Bit        Muxes := 1     
	  10 Input      1 Bit        Muxes := 1     
	  35 Input      1 Bit        Muxes := 1     
	  12 Input      1 Bit        Muxes := 1     
	   6 Input      1 Bit        Muxes := 6     
Module ttc_decoder_core 
Detailed RTL Component Info : 
+---Registers : 
	               14 Bit    Registers := 1     
	                8 Bit    Registers := 2     
	                4 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 9     
+---Muxes : 
	   2 Input     14 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
Module udp_rarp_block 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     24 Bit       Adders := 1     
	   2 Input      6 Bit       Adders := 2     
+---XORs : 
	   2 Input     16 Bit         XORs := 1     
	   4 Input     16 Bit         XORs := 1     
+---Registers : 
	               56 Bit    Registers := 1     
	               42 Bit    Registers := 1     
	               24 Bit    Registers := 1     
	               16 Bit    Registers := 2     
	               13 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                6 Bit    Registers := 4     
	                5 Bit    Registers := 1     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input     56 Bit        Muxes := 1     
	   3 Input     56 Bit        Muxes := 1     
	   2 Input     42 Bit        Muxes := 2     
	   2 Input     24 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 4     
	   2 Input      8 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 3     
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 7     
	   4 Input      1 Bit        Muxes := 1     
Module udp_build_arp 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	               48 Bit    Registers := 2     
	               13 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                6 Bit    Registers := 4     
	                1 Bit    Registers := 7     
+---Muxes : 
	   2 Input     48 Bit        Muxes := 3     
	   2 Input      8 Bit        Muxes := 2     
	   3 Input      6 Bit        Muxes := 1     
	   6 Input      6 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 8     
	   2 Input      3 Bit        Muxes := 1     
	   6 Input      1 Bit        Muxes := 6     
	   2 Input      1 Bit        Muxes := 5     
Module udp_build_ping 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     13 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 2     
	               13 Bit    Registers := 4     
	                8 Bit    Registers := 2     
	                6 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 14    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   8 Input     16 Bit        Muxes := 1     
	   5 Input     16 Bit        Muxes := 1     
	   2 Input     13 Bit        Muxes := 8     
	   4 Input     13 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 3     
	   2 Input      6 Bit        Muxes := 4     
	   6 Input      6 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   4 Input      4 Bit        Muxes := 1     
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 10    
	   6 Input      1 Bit        Muxes := 2     
	   4 Input      1 Bit        Muxes := 8     
	   5 Input      1 Bit        Muxes := 3     
Module udp_ipaddr_block 
Detailed RTL Component Info : 
+---Registers : 
	               80 Bit    Registers := 2     
	               48 Bit    Registers := 1     
	               42 Bit    Registers := 1     
	               32 Bit    Registers := 1     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input     80 Bit        Muxes := 4     
	   2 Input      1 Bit        Muxes := 2     
Module udp_build_payload 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     13 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	               16 Bit    Registers := 4     
	               13 Bit    Registers := 6     
	                8 Bit    Registers := 2     
	                1 Bit    Registers := 20    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 6     
	   4 Input     16 Bit        Muxes := 2     
	  14 Input     16 Bit        Muxes := 3     
	  11 Input     16 Bit        Muxes := 1     
	   2 Input     13 Bit        Muxes := 12    
	   2 Input      8 Bit        Muxes := 2     
	  13 Input      8 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 1     
	   4 Input      6 Bit        Muxes := 1     
	   8 Input      6 Bit        Muxes := 1     
	   4 Input      4 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 23    
	   9 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 2     
	  11 Input      1 Bit        Muxes := 2     
	  12 Input      1 Bit        Muxes := 2     
	  13 Input      1 Bit        Muxes := 9     
Module udp_build_resend 
Detailed RTL Component Info : 
+---Registers : 
	               45 Bit    Registers := 1     
	               16 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module udp_build_status 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	              128 Bit    Registers := 1     
	               13 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                7 Bit    Registers := 4     
	                1 Bit    Registers := 9     
+---Muxes : 
	   2 Input    128 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 2     
	   2 Input      7 Bit        Muxes := 9     
	   2 Input      6 Bit        Muxes := 2     
	   7 Input      6 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   8 Input      1 Bit        Muxes := 1     
	   6 Input      1 Bit        Muxes := 3     
Module udp_status_buffer 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     16 Bit       Adders := 1     
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	              128 Bit    Registers := 4     
	               16 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                5 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 13    
+---Muxes : 
	   2 Input    128 Bit        Muxes := 4     
	   4 Input    128 Bit        Muxes := 1     
	   2 Input     32 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 3     
	   5 Input      8 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 3     
	   5 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 3     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 25    
	   4 Input      1 Bit        Muxes := 2     
Module udp_byte_sum__1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
+---Registers : 
	                9 Bit    Registers := 4     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 6     
	   2 Input      8 Bit        Muxes := 7     
	   2 Input      1 Bit        Muxes := 9     
Module udp_do_rx_reset 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     12 Bit        Muxes := 1     
Module udp_packet_parser 
Detailed RTL Component Info : 
+---Registers : 
	              128 Bit    Registers := 1     
	              120 Bit    Registers := 1     
	              112 Bit    Registers := 1     
	               48 Bit    Registers := 1     
	               45 Bit    Registers := 1     
	               42 Bit    Registers := 1     
	               38 Bit    Registers := 1     
	               36 Bit    Registers := 1     
	               34 Bit    Registers := 1     
	               32 Bit    Registers := 4     
	               24 Bit    Registers := 2     
	               22 Bit    Registers := 1     
	               16 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 18    
+---Muxes : 
	   2 Input    128 Bit        Muxes := 1     
	   2 Input    120 Bit        Muxes := 1     
	   2 Input    112 Bit        Muxes := 1     
	   2 Input     48 Bit        Muxes := 1     
	   5 Input     48 Bit        Muxes := 1     
	   3 Input     42 Bit        Muxes := 1     
	   3 Input     38 Bit        Muxes := 1     
	   3 Input     36 Bit        Muxes := 1     
	   3 Input     34 Bit        Muxes := 1     
	   2 Input     32 Bit        Muxes := 4     
	   4 Input     32 Bit        Muxes := 1     
	   2 Input     24 Bit        Muxes := 2     
	   5 Input     24 Bit        Muxes := 2     
	   3 Input     22 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 1     
	   6 Input     16 Bit        Muxes := 1     
	   4 Input     10 Bit        Muxes := 1     
	   5 Input      8 Bit        Muxes := 5     
	   6 Input      8 Bit        Muxes := 1     
	   5 Input      7 Bit        Muxes := 1     
	   5 Input      6 Bit        Muxes := 1     
	   5 Input      4 Bit        Muxes := 3     
	   6 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 44    
	   4 Input      1 Bit        Muxes := 1     
	   5 Input      1 Bit        Muxes := 1     
Module udp_rxram_mux 
Detailed RTL Component Info : 
+---Registers : 
	               13 Bit    Registers := 2     
	                8 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      3 Bit        Muxes := 2     
	   5 Input      3 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 5     
Module udp_DualPortRAM 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module udp_buffer_selector 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 3     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input      2 Bit        Muxes := 8     
	   2 Input      1 Bit        Muxes := 2     
Module udp_rxram_shim 
Detailed RTL Component Info : 
+---Registers : 
	               13 Bit    Registers := 3     
	                1 Bit    Registers := 3     
+---Muxes : 
	   2 Input     13 Bit        Muxes := 1     
Module udp_DualPortRAM_rx 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 4     
+---RAMs : 
	              64K Bit         RAMs := 4     
+---Muxes : 
	   4 Input      1 Bit        Muxes := 4     
Module udp_buffer_selector__parameterized0 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 2     
+---Registers : 
	               16 Bit    Registers := 3     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 8     
	   2 Input      4 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module udp_rxtransactor_if 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 3     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module udp_DualPortRAM_tx 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 1     
	                2 Bit    Registers := 1     
+---RAMs : 
	             256K Bit         RAMs := 1     
+---Muxes : 
	   4 Input      8 Bit        Muxes := 1     
Module udp_buffer_selector__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 2     
+---Registers : 
	               16 Bit    Registers := 3     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 8     
	   2 Input      4 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module udp_byte_sum 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
+---Registers : 
	                9 Bit    Registers := 4     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 6     
	   2 Input      8 Bit        Muxes := 7     
	   2 Input      1 Bit        Muxes := 9     
Module udp_tx_mux 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     13 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	               16 Bit    Registers := 4     
	               13 Bit    Registers := 6     
	                8 Bit    Registers := 4     
	                5 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 25    
+---Muxes : 
	   6 Input     32 Bit        Muxes := 1     
	  18 Input     16 Bit        Muxes := 4     
	   2 Input     13 Bit        Muxes := 10    
	   8 Input     13 Bit        Muxes := 1     
	   4 Input     13 Bit        Muxes := 1     
	   3 Input     13 Bit        Muxes := 1     
	   7 Input     13 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 13    
	  17 Input      8 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	  17 Input      2 Bit        Muxes := 2     
	   2 Input      2 Bit        Muxes := 1     
	   8 Input      1 Bit        Muxes := 8     
	   7 Input      1 Bit        Muxes := 7     
	   2 Input      1 Bit        Muxes := 27    
	   5 Input      1 Bit        Muxes := 2     
	   9 Input      1 Bit        Muxes := 3     
	  16 Input      1 Bit        Muxes := 8     
	  17 Input      1 Bit        Muxes := 1     
	   3 Input      1 Bit        Muxes := 2     
Module udp_txtransactor_if 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 16    
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 16    
	  16 Input      1 Bit        Muxes := 1     
Module udp_clock_crossing_if 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 10    
+---Registers : 
	                4 Bit    Registers := 5     
	                3 Bit    Registers := 7     
	                2 Bit    Registers := 5     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input      4 Bit        Muxes := 2     
	   2 Input      3 Bit        Muxes := 2     
Module UDP_if 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 1     
Module transactor_if 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 1     
	               16 Bit    Registers := 3     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 1     
	   3 Input     32 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 3     
	   7 Input      7 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 3     
	   7 Input      1 Bit        Muxes := 1     
Module transactor_sm 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     32 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 3     
+---Registers : 
	               32 Bit    Registers := 5     
	                8 Bit    Registers := 3     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 5     
	   3 Input      8 Bit        Muxes := 1     
	   6 Input      6 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 6     
	   2 Input      4 Bit        Muxes := 1     
	   3 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
	   4 Input      1 Bit        Muxes := 1     
	   3 Input      1 Bit        Muxes := 2     
	   6 Input      1 Bit        Muxes := 1     
Module transactor_cfg 
Detailed RTL Component Info : 
+---Registers : 
	              128 Bit    Registers := 1     
+---Muxes : 
	   2 Input    128 Bit        Muxes := 1     
	   4 Input     32 Bit        Muxes := 1     
Module udp_master_rarp 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	               40 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                6 Bit    Registers := 2     
	                1 Bit    Registers := 4     
+---Muxes : 
	   5 Input     40 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 1     
	   7 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
	   6 Input      1 Bit        Muxes := 2     
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
INFO: [Synth 8-5544] ROM "buf_to_load_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-3917] design top_ftm_control has port aerr_led_n driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port alert_led_n driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port div_div4 driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port ttcfmc_2de driven by constant 1
WARNING: [Synth 8-3917] design top_ftm_control has port trigger_Inhibit driven by constant 0
WARNING: [Synth 8-3917] design top_ftm_control has port trigger_BGO driven by constant 0
WARNING: [Synth 8-3917] design top_ftm_control has port bridge_reset_n driven by constant 1
INFO: [Synth 8-3971] The signal "i_0/slaves/spi_pll/spi_dpram_in/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/spi_flash/spi_dpram_in/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[15].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[15].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[14].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[14].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[13].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[13].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[12].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[12].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[11].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[11].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[10].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[10].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[9].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[9].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[8].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[8].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[7].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[7].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[6].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[6].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[5].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[5].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[4].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[4].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[3].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[3].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[2].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[2].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[1].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[1].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-3971] The signal "i_0/slaves/rx_bufs/bufgen[0].rxbuf/dssram/ram_reg" was recognized as a true dual port RAM template.
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM bufgen[0].rxbuf/dssram/ram_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power
INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[28] )
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[15].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[14].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[13].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[12].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[11].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[10].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[9].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[8].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[7].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[6].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[5].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[4].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[3].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[2].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/tx_bufs/bufgen[1].txbuf/framer/sync_frame_r_reg' (FD) to 'i_0/slaves/tx_bufs/bufgen[0].txbuf/framer/sync_frame_r_reg'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[32] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[33] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[34] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[35] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[36] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[37] )
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][ctrl][0]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][ctrl][1]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][ctrl][2]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][ctrl][3]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][12]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][26]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][15]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][16]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][13]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][23]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][27]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][29]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][14]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][18]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][24]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][25]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][17]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][30]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][28]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[3][data][31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/ttc_info/\ttcout/ttcreg_reg[3][data][31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[38] )
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][ctrl][0]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][ctrl][1]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][ctrl][1]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][ctrl][2]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][ctrl][2]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][ctrl][3]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][ctrl][3]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][12]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][12]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][13]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][26]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][13]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][15]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][13]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][16]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][13]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][13]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][14]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][23]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][14]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][27]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][14]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][29]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][14]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][14]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][17]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][18]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][17]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][24]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][17]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][25]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][17]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][17]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][28]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][30]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][28]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][28]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[2][data][31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[39] )
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[1][ctrl][0]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[1][ctrl][1]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[1][ctrl][1]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[1][ctrl][2]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[1][ctrl][2]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[1][ctrl][3]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[40] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[15].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[14].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[13].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[12].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[11].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[10].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[9].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[8].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[7].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[6].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[5].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[4].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[3].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[2].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[1].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[0].rxbuf/ram_pointer/enable_stop_reg )
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[0][ctrl][1]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[0][ctrl][2]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[0][ctrl][2]' (FDR) to 'i_0/slaves/ttc_info/ttcout/ttcreg_reg[0][ctrl][3]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_data_reg[41] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\ttc/ttc_dec/serialb_com0 /\hamming.test_init_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[15].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[14].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[13].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[12].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[11].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[10].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[9].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[8].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[7].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[6].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[5].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[4].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[3].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[2].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[1].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[0].rxbuf/ram_pointer/stop_wr_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[15].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[14].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[13].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[12].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[11].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[10].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[9].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[8].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[7].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[6].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[5].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[4].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[3].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[2].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[1].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/tx_bufs/\bufgen[0].txbuf/framer/frame_index_reg[2] )
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcregdel_reg[ctrl][1]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcregdel_reg[ctrl][2]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/ttc_info/ttcout/ttcregdel_reg[ctrl][2]' (FD) to 'i_0/slaves/ttc_info/ttcout/ttcregdel_reg[ctrl][3]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/monitoring/adc_inst/daddr_reg[3]' (FDE) to 'i_0/slaves/monitoring/adc_inst/daddr_reg[4]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/monitoring/\adc_inst/daddr_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[15].rxbuf/frame_sync/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[14].rxbuf/frame_sync/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[13].rxbuf/frame_sync/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[12].rxbuf/frame_sync/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[11].rxbuf/frame_sync/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[10].rxbuf/frame_sync/frame_index_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/slaves/rx_bufs/\bufgen[9].rxbuf/frame_sync/frame_index_reg[2] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3886] merging instance 'i_0/UDP_FIFO2/DataOut_reg[0]' (FD) to 'i_0/UDP_FIFO2/mac_tx_last_reg'
INFO: [Synth 8-3886] merging instance 'i_0/UDP_FIFO1/DataOut_reg[0]' (FD) to 'i_0/UDP_FIFO1/mac_tx_last_reg'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][0]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[2][0]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[0][0]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[3][0]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[1][0]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[2][0]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][1]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[2][1]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[0][1]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[3][1]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[0][1]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][2]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[2][2]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[0][2]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[3][2]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[1][2]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[2][2]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[0][2]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][3]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[2][3]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[0][3]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[3][3]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[1][3]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[2][3]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[0][3]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][4]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[2][4]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[0][4]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[3][4]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[1][4]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[2][4]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][5]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[2][5]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[0][5]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[3][5]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[1][5]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Synth 8-3886] merging instance 'i_0/slaves/xcvr_control/quad115_116_regs/xcvr_status_reg[2][5]' (FD) to 'i_0/slaves/xcvr_control/quad117_118_regs/xcvr_status_reg[1][7]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3332] Sequential element (synch/FSM_onehot_sequencer_reg[3]) is unused and will be removed from module ipbus_spi32.
WARNING: [Synth 8-3332] Sequential element (synch/FSM_onehot_sequencer_reg[3]) is unused and will be removed from module ipbus_spi32__parameterized0.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:51 ; elapsed = 00:02:14 . Memory (MB): peak = 2596.031 ; gain = 609.961 ; free physical = 2906 ; free virtual = 21073
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Block RAM: Preliminary Mapping	Report (see note below)
+--------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name                     | RTL Object                       | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+--------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|ipbus_dpram:                    | ram_reg                          | 16 x 32(READ_FIRST)    | W | R | 16 x 32(READ_FIRST)    | W | R | Port A and B     | 0      | 1      | 
|i_0/slaves/spi_pll              | spi_dpram_in/ram_reg             | 16 x 32(NO_CHANGE)     | W |   | 16 x 32(READ_FIRST)    | W | R | Port A and B     | 0      | 1      | 
|i_0/slaves/spi_flash            | spi_dpram_out/ram_reg            | 128 x 32(READ_FIRST)   | W | R | 128 x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/spi_flash            | spi_dpram_in/ram_reg             | 128 x 32(NO_CHANGE)    | W |   | 128 x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[15].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[15].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[14].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[14].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[13].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[13].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[12].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[12].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[11].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[11].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[10].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[10].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[9].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[9].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[8].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[8].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[7].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[7].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[6].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[6].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[5].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[5].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[4].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[4].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[3].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[3].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[2].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[2].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[1].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[1].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[0].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[0].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/rx_bufs              | bufgen[15].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[14].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[13].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[12].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[11].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[10].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[9].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[8].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[7].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[6].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[5].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[4].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[3].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[2].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[1].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[0].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/l1a_generator        | delay_memory/ram_reg             | 4 K x 32(READ_FIRST)   | W | R | 4 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 4      | 
|i_1/\ipbus/udp_if               | internal_ram/ram_reg             | 4 K x 8(READ_FIRST)    | W |   | 4 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram1_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram2_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram3_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram4_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if /ipbus_tx_ram | ram_reg                          | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
+--------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 

Distributed RAM: Preliminary Mapping	Report (see note below)
+----------------+----------------------+-----------+----------------------+----------------+
|Module Name     | RTL Object           | Inference | Size (Depth x Width) | Primitives     | 
+----------------+----------------------+-----------+----------------------+----------------+
|top_ftm_control | UDP_FIFO1/Memory_reg | Implied   | 32 x 10              | RAM32X1D x 10	 | 
|top_ftm_control | UDP_FIFO2/Memory_reg | Implied   | 32 x 10              | RAM32X1D x 10	 | 
+----------------+----------------------+-----------+----------------------+----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+----------------------+------------+----------+
|      |RTL Partition         |Replication |Instances |
+------+----------------------+------------+----------+
|1     |clocks_7s_extphy__GC0 |           1|        54|
|2     |top_ftm_control__GCB0 |           1|     19146|
|3     |top_ftm_control__GCB1 |           1|     11721|
|4     |top_ftm_control__GCB3 |           1|        11|
+------+----------------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
INFO: [Synth 8-5578] Moved timing constraint from pin 'clk200' to pin 'bufg200/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'onehz' to pin 'clkdiv/d28_reg/Q'
INFO: [Synth 8-5819] Moved 2 constraints on hierarchical pins to their respective driving/loading pins
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:01 ; elapsed = 00:02:31 . Memory (MB): peak = 2596.035 ; gain = 609.965 ; free physical = 2791 ; free virtual = 20958
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:24 ; elapsed = 00:02:55 . Memory (MB): peak = 2652.035 ; gain = 665.965 ; free physical = 2754 ; free virtual = 20921
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Block RAM: Final Mapping	Report
+--------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name                     | RTL Object                       | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+--------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|ipbus_dpram:                    | ram_reg                          | 16 x 32(READ_FIRST)    | W | R | 16 x 32(READ_FIRST)    | W | R | Port A and B     | 0      | 1      | 
|i_0/slaves/spi_pll              | spi_dpram_in/ram_reg             | 16 x 32(NO_CHANGE)     | W |   | 16 x 32(READ_FIRST)    | W | R | Port A and B     | 0      | 1      | 
|i_0/slaves/spi_flash            | spi_dpram_out/ram_reg            | 128 x 32(READ_FIRST)   | W | R | 128 x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/spi_flash            | spi_dpram_in/ram_reg             | 128 x 32(NO_CHANGE)    | W |   | 128 x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[15].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[15].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[14].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[14].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[13].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[13].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[12].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[12].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[11].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[11].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[10].txbuf/dssram/ram_reg  | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[10].txbuf/ctrlram/ram_reg | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[9].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[9].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[8].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[8].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[7].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[7].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[6].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[6].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[5].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[5].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[4].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[4].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[3].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[3].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[2].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[2].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[1].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[1].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/tx_bufs              | bufgen[0].txbuf/dssram/ram_reg   | 8 K x 32(READ_FIRST)   | W | R | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
|i_0/slaves/tx_bufs              | bufgen[0].txbuf/ctrlram/ram_reg  | 8 K x 4(READ_FIRST)    | W | R | 8 K x 4(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_0/slaves/rx_bufs              | bufgen[15].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[14].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[13].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[12].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[11].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[10].rxbuf/dssram/ram_reg  | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[9].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[8].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[7].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[6].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[5].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[4].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[3].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[2].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[1].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/rx_bufs              | bufgen[0].rxbuf/dssram/ram_reg   | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(READ_FIRST)   | W | R | Port A and B     | 0      | 8      | 
|i_0/slaves/l1a_generator        | delay_memory/ram_reg             | 4 K x 32(READ_FIRST)   | W | R | 4 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 4      | 
|i_1/\ipbus/udp_if               | internal_ram/ram_reg             | 4 K x 8(READ_FIRST)    | W |   | 4 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 1      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram1_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram2_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram3_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if               | ipbus_rx_ram/ram4_reg            | 8 K x 8(NO_CHANGE)     | W |   | 8 K x 8(WRITE_FIRST)   |   | R | Port A and B     | 0      | 2      | 
|i_1/\ipbus/udp_if /ipbus_tx_ram | ram_reg                          | 8 K x 32(NO_CHANGE)    | W |   | 8 K x 32(WRITE_FIRST)  |   | R | Port A and B     | 0      | 8      | 
+--------------------------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+


Distributed RAM: Final Mapping	Report
+----------------+----------------------+-----------+----------------------+----------------+
|Module Name     | RTL Object           | Inference | Size (Depth x Width) | Primitives     | 
+----------------+----------------------+-----------+----------------------+----------------+
|top_ftm_control | UDP_FIFO1/Memory_reg | Implied   | 32 x 10              | RAM32X1D x 10	 | 
|top_ftm_control | UDP_FIFO2/Memory_reg | Implied   | 32 x 10              | RAM32X1D x 10	 | 
+----------------+----------------------+-----------+----------------------+----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+----------------------+------------+----------+
|      |RTL Partition         |Replication |Instances |
+------+----------------------+------------+----------+
|1     |clocks_7s_extphy__GC0 |           1|        54|
|2     |top_ftm_control__GCB3 |           1|        11|
|3     |top_ftm_control_GT0   |           1|     30693|
+------+----------------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7053] The timing for the instance slaves/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/spi_pll/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[15].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[14].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[13].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[12].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[11].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[10].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[9].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[8].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[7].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/dssram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[6].txbuf/ctrlram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[5].txbuf/dssram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[5].txbuf/dssram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[5].txbuf/dssram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7053] The timing for the instance slaves/tx_bufs/bufgen[5].txbuf/dssram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-7053' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:02:35 ; elapsed = 00:03:07 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2848 ; free virtual = 21015
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
INFO: [Synth 8-5365] Flop spi_engine/gen_enable_bytes.le_int_reg is being inverted and renamed to spi_engine/gen_enable_bytes.le_int_reg_inv.
INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [6] is driving 276 big block pins (URAM, BRAM and DSP loads). Created 49 replicas of its driver. 
INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [3] is driving 276 big block pins (URAM, BRAM and DSP loads). Created 49 replicas of its driver. 
INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_addr] [3] is sub-optimal because some of its loads are not in same hierarchy as its driver   
INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [5] is driving 276 big block pins (URAM, BRAM and DSP loads). Created 49 replicas of its driver. 
INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_addr] [5] is sub-optimal because some of its loads are not in same hierarchy as its driver   
INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [4] is driving 276 big block pins (URAM, BRAM and DSP loads). Created 49 replicas of its driver. 
INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_addr] [4] is sub-optimal because some of its loads are not in same hierarchy as its driver   
INFO: [Synth 8-6064] Net \ipb_master_out[ipb_addr] [8] is driving 276 big block pins (URAM, BRAM and DSP loads). Created 49 replicas of its driver. 
INFO: [Synth 8-5778] max_fanout handling on net \ipb_master_out[ipb_addr] [8] is sub-optimal because some of its loads are not in same hierarchy as its driver   
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
WARNING: [Synth 8-3295] tying undriven pin gt_txfsmresetdone_r_inferred:in0 to constant 0
WARNING: [Synth 8-3295] tying undriven pin gt_txfsmresetdone_r2_inferred:in0 to constant 0
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:02:40 ; elapsed = 00:03:12 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2846 ; free virtual = 21014
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:02:40 ; elapsed = 00:03:12 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2846 ; free virtual = 21014
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:43 ; elapsed = 00:03:15 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2845 ; free virtual = 21013
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:02:43 ; elapsed = 00:03:15 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2845 ; free virtual = 21013
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:02:44 ; elapsed = 00:03:16 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2845 ; free virtual = 21013
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:02:44 ; elapsed = 00:03:16 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2845 ; free virtual = 21013
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Static Shift Register Report:
+----------------+----------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name     | RTL Name                                                       | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | 
+----------------+----------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|top_ftm_control | ipbus/udp_if/IPADDR/pkt_mask_reg[41]                           | 32     | 1     | YES          | NO                 | YES               | 0      | 1       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[44]                 | 37     | 1     | YES          | NO                 | YES               | 0      | 2       | 
|top_ftm_control | ipbus/udp_if/resend/pkt_mask_reg[44]                           | 43     | 1     | YES          | NO                 | YES               | 0      | 2       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[33]__0              | 6      | 5     | YES          | NO                 | YES               | 5      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[29]__0 | 10     | 1     | YES          | NO                 | YES               | 1      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[18]__0              | 5      | 1     | YES          | NO                 | YES               | 1      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[35]    | 23     | 1     | YES          | NO                 | YES               | 0      | 1       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[37]__0              | 23     | 1     | YES          | NO                 | YES               | 0      | 1       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[41]    | 12     | 1     | YES          | NO                 | YES               | 1      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_mask_reg[19]__0 | 8      | 1     | YES          | NO                 | YES               | 1      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[11]__0              | 8      | 1     | YES          | NO                 | YES               | 1      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_mask_reg[11]__1              | 10     | 1     | YES          | NO                 | YES               | 1      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_data_reg[71]                 | 5      | 4     | YES          | NO                 | YES               | 4      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/pkt_data_reg[59]                 | 4      | 1     | YES          | NO                 | YES               | 1      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_data_reg[111]   | 10     | 4     | YES          | NO                 | YES               | 4      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_data_reg[90]    | 4      | 2     | YES          | NO                 | YES               | 2      | 0       | 
|top_ftm_control | ipbus/udp_if/rx_packet_parser/primary_mode.pkt_data_reg[72]    | 5      | 2     | YES          | NO                 | YES               | 2      | 0       | 
+----------------+----------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+------+--------------------+----------+
|      |BlackBox name       |Instances |
+------+--------------------+----------+
|1     |ila_tx              |         3|
|2     |gtwizard_0          |         1|
|3     |ila_rx              |         1|
|4     |temac_gbe_v9_0_gmii |         1|
|5     |mac_fifo_axi4       |         1|
+------+--------------------+----------+

Report Cell Usage: 
+------+---------------------------+------+
|      |Cell                       |Count |
+------+---------------------------+------+
|1     |gtwizard_0_bbox_2          |     1|
|2     |ila_rx_bbox_4              |     1|
|3     |ila_tx_bbox_3              |     1|
|4     |ila_tx_bbox_7              |     1|
|5     |ila_tx_bbox_8              |     1|
|6     |mac_fifo_axi4_bbox_6       |     1|
|7     |temac_gbe_v9_0_gmii_bbox_5 |     1|
|8     |BUFG                       |    12|
|9     |CARRY4                     |   432|
|10    |GTXE2_COMMON               |     1|
|11    |IBUFDS_GTE2                |     1|
|12    |ICAPE2                     |     1|
|13    |IDELAYCTRL                 |     1|
|14    |LUT1                       |   500|
|15    |LUT2                       |   724|
|16    |LUT3                       |   889|
|17    |LUT4                       |   784|
|18    |LUT5                       |  1852|
|19    |LUT6                       |  2776|
|20    |MMCME2_BASE                |     1|
|21    |MMCM_ADV                   |     1|
|22    |MUXF7                      |   120|
|23    |MUXF8                      |     5|
|24    |RAM32X1D                   |    20|
|25    |RAMB36E1                   |     1|
|26    |RAMB36E1_1                 |     2|
|27    |RAMB36E1_10                |    16|
|28    |RAMB36E1_2                 |     1|
|29    |RAMB36E1_3                 |    16|
|30    |RAMB36E1_4                 |    16|
|31    |RAMB36E1_5                 |    96|
|32    |RAMB36E1_6                 |    16|
|33    |RAMB36E1_7                 |   128|
|34    |RAMB36E1_8                 |     4|
|35    |RAMB36E1_9                 |     1|
|36    |SRL16                      |     1|
|37    |SRL16E                     |    24|
|38    |SRLC32E                    |    22|
|39    |STARTUPE2                  |     1|
|40    |XADC                       |     1|
|41    |FDCE                       |   112|
|42    |FDPE                       |     5|
|43    |FDRE                       |  6990|
|44    |FDSE                       |   418|
|45    |IBUF                       |    31|
|46    |IBUFDS                     |    21|
|47    |IBUFGDS                    |     6|
|48    |IOBUF                      |     4|
|49    |OBUF                       |    41|
|50    |OBUFDS                     |    26|
|51    |OBUFT                      |     2|
+------+---------------------------+------+

Report Instance Areas: 
+------+--------------------------------+------------------------------------+------+
|      |Instance                        |Module                              |Cells |
+------+--------------------------------+------------------------------------+------+
|1     |top                             |                                    | 16331|
|2     |  mgt_ttcinfo                   |gtwizard_0_exdes                    |   155|
|3     |    gtwizard_0_support_i        |gtwizard_0_support                  |   138|
|4     |      common0_i                 |gtwizard_0_common                   |     1|
|5     |      common_reset_i            |gtwizard_0_common_reset             |    28|
|6     |      gt_usrclk_source          |gtwizard_0_GT_USRCLK_SOURCE         |     3|
|7     |  UDP_FIFO1                     |UDP_master_fifo                     |   104|
|8     |  UDP_FIFO2                     |UDP_master_fifo_0                   |   107|
|9     |  UDP_master_if1                |UDP_master_if                       |    62|
|10    |  UDP_master_if2                |UDP_master_if_1                     |    64|
|11    |  cclk_o                        |startup                             |     1|
|12    |  clocks                        |clocks_7s_extphy                    |    88|
|13    |    clkdiv                      |clock_div                           |    45|
|14    |  eth                           |eth_7s_gmii                         |   115|
|15    |  external_pll                  |pll_synch                           |    28|
|16    |  ipbus                         |ipbus_ctrl                          |  7948|
|17    |    trans                       |transactor                          |  2787|
|18    |      cfg                       |transactor_cfg                      |     3|
|19    |      iface                     |transactor_if                       |   689|
|20    |      sm                        |transactor_sm                       |  2081|
|21    |    udp_if                      |UDP_if                              |  5156|
|22    |      ipbus_rx_ram              |udp_DualPortRAM_rx                  |     8|
|23    |      IPADDR                    |udp_ipaddr_block                    |   253|
|24    |      clock_crossing_if         |udp_clock_crossing_if               |    89|
|25    |      internal_ram              |udp_DualPortRAM                     |     1|
|26    |      internal_ram_selector     |udp_buffer_selector                 |    19|
|27    |      internal_ram_shim         |udp_rxram_shim                      |    68|
|28    |      ipbus_tx_ram              |udp_DualPortRAM_tx                  |    18|
|29    |      payload                   |udp_build_payload                   |   411|
|30    |      \primary_mode.ARP         |udp_build_arp                       |   240|
|31    |      \primary_mode.RARP_block  |udp_rarp_block                      |   367|
|32    |      \primary_mode.ping        |udp_build_ping                      |   215|
|33    |      resend                    |udp_build_resend                    |    82|
|34    |      rx_byte_sum               |udp_byte_sum                        |    89|
|35    |      rx_packet_parser          |udp_packet_parser                   |   827|
|36    |      rx_ram_mux                |udp_rxram_mux                       |    49|
|37    |      rx_ram_selector           |udp_buffer_selector__parameterized0 |   125|
|38    |      rx_reset_block            |udp_do_rx_reset                     |    25|
|39    |      rx_transactor             |udp_rxtransactor_if                 |     6|
|40    |      status                    |udp_build_status                    |   323|
|41    |      status_buffer             |udp_status_buffer                   |   682|
|42    |      tx_byte_sum               |udp_byte_sum_169                    |    76|
|43    |      tx_main                   |udp_tx_mux                          |   528|
|44    |      tx_ram_selector           |udp_buffer_selector__parameterized1 |   199|
|45    |      tx_transactor             |udp_txtransactor_if                 |   442|
|46    |  rarpd                         |udp_master_rarp                     |   112|
|47    |  slaves                        |slaves                              |  6810|
|48    |    spi_pll                     |ipbus_spi32                         |   601|
|49    |      arbitration               |ipbus_watchdog_165                  |   260|
|50    |      gen_clock                 |clock_pulse_166                     |     4|
|51    |      spi_control               |ipbus_ctrlreg_v__parameterized0_167 |   165|
|52    |      spi_dpram_in              |ipbus_dpram__parameterized0         |     8|
|53    |      spi_dpram_out             |ipbus_dpram                         |    63|
|54    |      spi_engine                |spi32_8_control                     |    82|
|55    |      synch                     |command_sync_168                    |     9|
|56    |    spi_flash                   |ipbus_spi32__parameterized0         |   633|
|57    |      arbitration               |ipbus_watchdog                      |   250|
|58    |      gen_clock                 |clock_pulse                         |     4|
|59    |      spi_control               |ipbus_ctrlreg_v__parameterized0     |   176|
|60    |      spi_dpram_in              |ipbus_dpram__parameterized2         |    43|
|61    |      spi_dpram_out             |ipbus_dpram__parameterized1         |     4|
|62    |      spi_engine                |spi32_8_control__parameterized0     |   134|
|63    |      synch                     |command_sync                        |     9|
|64    |    address_reader              |eeprom_addr_reader                  |   115|
|65    |    buffer_control              |ipbus_ftm_buffer_control            |    29|
|66    |    configure                   |ipbus_self_configure                |   189|
|67    |      \config                   |reconfigure_fsm                     |   102|
|68    |      wbstart_reg               |ipbus_ctrlreg_v_164                 |    87|
|69    |    fpga_id                     |ipbus_ftm_fpga_id_version           |    15|
|70    |    i2c_adcs                    |ipbus_i2c_master_arb                |   452|
|71    |      arbitration               |ipbus_watchdog__parameterized0_158  |   207|
|72    |      i2c_eeprom                |ipbus_i2c_master_159                |   245|
|73    |        i2c                     |i2c_master_top_160                  |   245|
|74    |          bit_controller        |i2c_master_bit_ctrl_161             |   108|
|75    |          byte_controller       |i2c_master_byte_ctrl_162            |    59|
|76    |          registers             |i2c_master_registers_163            |    68|
|77    |    i2c_bridge                  |ipbus_i2c_master_arb_2              |   451|
|78    |      arbitration               |ipbus_watchdog__parameterized0_152  |   207|
|79    |      i2c_eeprom                |ipbus_i2c_master_153                |   244|
|80    |        i2c                     |i2c_master_top_154                  |   244|
|81    |          bit_controller        |i2c_master_bit_ctrl_155             |   108|
|82    |          byte_controller       |i2c_master_byte_ctrl_156            |    59|
|83    |          registers             |i2c_master_registers_157            |    68|
|84    |    i2c_eeprom                  |ipbus_i2c_master_arb_3              |   469|
|85    |      arbitration               |ipbus_watchdog__parameterized0_146  |   209|
|86    |      i2c_eeprom                |ipbus_i2c_master_147                |   248|
|87    |        i2c                     |i2c_master_top_148                  |   248|
|88    |          bit_controller        |i2c_master_bit_ctrl_149             |   109|
|89    |          byte_controller       |i2c_master_byte_ctrl_150            |    62|
|90    |          registers             |i2c_master_registers_151            |    68|
|91    |    i2c_mpod                    |ipbus_i2c_master_arb_4              |   454|
|92    |      arbitration               |ipbus_watchdog__parameterized0      |   209|
|93    |      i2c_eeprom                |ipbus_i2c_master                    |   245|
|94    |        i2c                     |i2c_master_top                      |   245|
|95    |          bit_controller        |i2c_master_bit_ctrl                 |   108|
|96    |          byte_controller       |i2c_master_byte_ctrl                |    59|
|97    |          registers             |i2c_master_registers                |    68|
|98    |    l1a_generator               |ipbus_L1A_Generator                 |   330|
|99    |      L1A_gen                   |L1A_Gen                             |   238|
|100   |      control_reg               |ipbus_ctrlreg_v_145                 |    76|
|101   |      delay_memory              |ipbus_dpram__parameterized4         |    13|
|102   |    module_control              |ipbus_ctrlreg_v                     |    77|
|103   |    monitoring                  |ipbus_xadc_array                    |   313|
|104   |      adc_inst                  |xadc_ftm                            |   312|
|105   |    playback_control            |ipbus_module_playback               |    66|
|106   |    rx_bufs                     |ipbus_mgt_sink                      |   899|
|107   |      \bufgen[0].rxbuf          |ipbus_data_sink                     |    44|
|108   |        dssram                  |ipbus_dpram__parameterized3_142     |     9|
|109   |        frame_sync              |rx_framing_sync_logic_143           |     6|
|110   |        ram_pointer             |rx_ram_pointer_144                  |    28|
|111   |      \bufgen[10].rxbuf         |ipbus_data_sink_85                  |    44|
|112   |        dssram                  |ipbus_dpram__parameterized3_139     |     9|
|113   |        frame_sync              |rx_framing_sync_logic_140           |     6|
|114   |        ram_pointer             |rx_ram_pointer_141                  |    28|
|115   |      \bufgen[11].rxbuf         |ipbus_data_sink_86                  |    76|
|116   |        dssram                  |ipbus_dpram__parameterized3_136     |    41|
|117   |        frame_sync              |rx_framing_sync_logic_137           |     6|
|118   |        ram_pointer             |rx_ram_pointer_138                  |    28|
|119   |      \bufgen[12].rxbuf         |ipbus_data_sink_87                  |    44|
|120   |        dssram                  |ipbus_dpram__parameterized3_133     |     9|
|121   |        frame_sync              |rx_framing_sync_logic_134           |     6|
|122   |        ram_pointer             |rx_ram_pointer_135                  |    28|
|123   |      \bufgen[13].rxbuf         |ipbus_data_sink_88                  |    44|
|124   |        dssram                  |ipbus_dpram__parameterized3_130     |     9|
|125   |        frame_sync              |rx_framing_sync_logic_131           |     6|
|126   |        ram_pointer             |rx_ram_pointer_132                  |    28|
|127   |      \bufgen[14].rxbuf         |ipbus_data_sink_89                  |    45|
|128   |        dssram                  |ipbus_dpram__parameterized3_127     |    10|
|129   |        frame_sync              |rx_framing_sync_logic_128           |     6|
|130   |        ram_pointer             |rx_ram_pointer_129                  |    28|
|131   |      \bufgen[15].rxbuf         |ipbus_data_sink_90                  |    76|
|132   |        dssram                  |ipbus_dpram__parameterized3_124     |    41|
|133   |        frame_sync              |rx_framing_sync_logic_125           |     6|
|134   |        ram_pointer             |rx_ram_pointer_126                  |    28|
|135   |      \bufgen[1].rxbuf          |ipbus_data_sink_91                  |    44|
|136   |        dssram                  |ipbus_dpram__parameterized3_121     |     9|
|137   |        frame_sync              |rx_framing_sync_logic_122           |     6|
|138   |        ram_pointer             |rx_ram_pointer_123                  |    28|
|139   |      \bufgen[2].rxbuf          |ipbus_data_sink_92                  |    44|
|140   |        dssram                  |ipbus_dpram__parameterized3_118     |     9|
|141   |        frame_sync              |rx_framing_sync_logic_119           |     6|
|142   |        ram_pointer             |rx_ram_pointer_120                  |    28|
|143   |      \bufgen[3].rxbuf          |ipbus_data_sink_93                  |   141|
|144   |        dssram                  |ipbus_dpram__parameterized3_115     |   106|
|145   |        frame_sync              |rx_framing_sync_logic_116           |     6|
|146   |        ram_pointer             |rx_ram_pointer_117                  |    28|
|147   |      \bufgen[4].rxbuf          |ipbus_data_sink_94                  |    44|
|148   |        dssram                  |ipbus_dpram__parameterized3_112     |     9|
|149   |        frame_sync              |rx_framing_sync_logic_113           |     6|
|150   |        ram_pointer             |rx_ram_pointer_114                  |    28|
|151   |      \bufgen[5].rxbuf          |ipbus_data_sink_95                  |    44|
|152   |        dssram                  |ipbus_dpram__parameterized3_109     |     9|
|153   |        frame_sync              |rx_framing_sync_logic_110           |     6|
|154   |        ram_pointer             |rx_ram_pointer_111                  |    28|
|155   |      \bufgen[6].rxbuf          |ipbus_data_sink_96                  |    44|
|156   |        dssram                  |ipbus_dpram__parameterized3_106     |     9|
|157   |        frame_sync              |rx_framing_sync_logic_107           |     6|
|158   |        ram_pointer             |rx_ram_pointer_108                  |    28|
|159   |      \bufgen[7].rxbuf          |ipbus_data_sink_97                  |    76|
|160   |        dssram                  |ipbus_dpram__parameterized3_103     |    41|
|161   |        frame_sync              |rx_framing_sync_logic_104           |     6|
|162   |        ram_pointer             |rx_ram_pointer_105                  |    28|
|163   |      \bufgen[8].rxbuf          |ipbus_data_sink_98                  |    45|
|164   |        dssram                  |ipbus_dpram__parameterized3_100     |    10|
|165   |        frame_sync              |rx_framing_sync_logic_101           |     6|
|166   |        ram_pointer             |rx_ram_pointer_102                  |    28|
|167   |      \bufgen[9].rxbuf          |ipbus_data_sink_99                  |    44|
|168   |        dssram                  |ipbus_dpram__parameterized3         |     9|
|169   |        frame_sync              |rx_framing_sync_logic               |     6|
|170   |        ram_pointer             |rx_ram_pointer                      |    28|
|171   |    ttc                         |ipbus_ctrlreg_v__parameterized2     |    32|
|172   |    ttc_info                    |ipbus_ttcinfo                       |   765|
|173   |      BCR_pipe                  |delay_128                           |     5|
|174   |      ECR_pipe                  |delay_128_82                        |     7|
|175   |      L1A_pipe                  |delay_128_83                        |     7|
|176   |      control                   |ipbus_ttcinfo_control               |   102|
|177   |      error_counters            |ipbus_counter_array                 |    88|
|178   |      ttcin                     |ttcinfo_sink                        |   147|
|179   |        crc32                   |osum_crc9d32_84                     |    55|
|180   |      ttcout                    |ttcinfo_source                      |   340|
|181   |        crc32                   |osum_crc9d32                        |    46|
|182   |        framer                  |frame_sync_ttc_tx                   |    45|
|183   |    tx_bufs                     |ipbus_mgt_source                    |   757|
|184   |      \bufgen[0].txbuf          |ipbus_data_source                   |    50|
|185   |        ctrlram                 |ipbus_dpram_ctrl_init_78            |     6|
|186   |        dssram                  |ipbus_dpram_frame_init_79           |    10|
|187   |        framer                  |framing_sync_logic_80               |    16|
|188   |        ram_pointer             |tx_ram_pointer_81                   |    18|
|189   |      \bufgen[10].txbuf         |ipbus_data_source_7                 |    56|
|190   |        ctrlram                 |ipbus_dpram_ctrl_init_74            |    14|
|191   |        dssram                  |ipbus_dpram_frame_init_75           |     9|
|192   |        framer                  |framing_sync_logic_76               |    15|
|193   |        ram_pointer             |tx_ram_pointer_77                   |    18|
|194   |      \bufgen[11].txbuf         |ipbus_data_source_8                 |    45|
|195   |        ctrlram                 |ipbus_dpram_ctrl_init_70            |     2|
|196   |        dssram                  |ipbus_dpram_frame_init_71           |    10|
|197   |        framer                  |framing_sync_logic_72               |    15|
|198   |        ram_pointer             |tx_ram_pointer_73                   |    18|
|199   |      \bufgen[12].txbuf         |ipbus_data_source_9                 |    49|
|200   |        ctrlram                 |ipbus_dpram_ctrl_init_66            |     7|
|201   |        dssram                  |ipbus_dpram_frame_init_67           |     9|
|202   |        framer                  |framing_sync_logic_68               |    15|
|203   |        ram_pointer             |tx_ram_pointer_69                   |    18|
|204   |      \bufgen[13].txbuf         |ipbus_data_source_10                |    44|
|205   |        ctrlram                 |ipbus_dpram_ctrl_init_62            |     2|
|206   |        dssram                  |ipbus_dpram_frame_init_63           |     9|
|207   |        framer                  |framing_sync_logic_64               |    15|
|208   |        ram_pointer             |tx_ram_pointer_65                   |    18|
|209   |      \bufgen[14].txbuf         |ipbus_data_source_11                |    48|
|210   |        ctrlram                 |ipbus_dpram_ctrl_init_58            |     6|
|211   |        dssram                  |ipbus_dpram_frame_init_59           |     9|
|212   |        framer                  |framing_sync_logic_60               |    15|
|213   |        ram_pointer             |tx_ram_pointer_61                   |    18|
|214   |      \bufgen[15].txbuf         |ipbus_data_source_12                |    44|
|215   |        ctrlram                 |ipbus_dpram_ctrl_init_54            |     2|
|216   |        dssram                  |ipbus_dpram_frame_init_55           |     9|
|217   |        framer                  |framing_sync_logic_56               |    15|
|218   |        ram_pointer             |tx_ram_pointer_57                   |    18|
|219   |      \bufgen[1].txbuf          |ipbus_data_source_13                |    44|
|220   |        ctrlram                 |ipbus_dpram_ctrl_init_50            |     2|
|221   |        dssram                  |ipbus_dpram_frame_init_51           |     9|
|222   |        framer                  |framing_sync_logic_52               |    15|
|223   |        ram_pointer             |tx_ram_pointer_53                   |    18|
|224   |      \bufgen[2].txbuf          |ipbus_data_source_14                |    53|
|225   |        ctrlram                 |ipbus_dpram_ctrl_init_46            |    10|
|226   |        dssram                  |ipbus_dpram_frame_init_47           |    10|
|227   |        framer                  |framing_sync_logic_48               |    15|
|228   |        ram_pointer             |tx_ram_pointer_49                   |    18|
|229   |      \bufgen[3].txbuf          |ipbus_data_source_15                |    44|
|230   |        ctrlram                 |ipbus_dpram_ctrl_init_42            |     2|
|231   |        dssram                  |ipbus_dpram_frame_init_43           |     9|
|232   |        framer                  |framing_sync_logic_44               |    15|
|233   |        ram_pointer             |tx_ram_pointer_45                   |    18|
|234   |      \bufgen[4].txbuf          |ipbus_data_source_16                |    49|
|235   |        ctrlram                 |ipbus_dpram_ctrl_init_38            |     6|
|236   |        dssram                  |ipbus_dpram_frame_init_39           |    10|
|237   |        framer                  |framing_sync_logic_40               |    15|
|238   |        ram_pointer             |tx_ram_pointer_41                   |    18|
|239   |      \bufgen[5].txbuf          |ipbus_data_source_17                |    44|
|240   |        ctrlram                 |ipbus_dpram_ctrl_init_34            |     2|
|241   |        dssram                  |ipbus_dpram_frame_init_35           |     9|
|242   |        framer                  |framing_sync_logic_36               |    15|
|243   |        ram_pointer             |tx_ram_pointer_37                   |    18|
|244   |      \bufgen[6].txbuf          |ipbus_data_source_18                |    49|
|245   |        ctrlram                 |ipbus_dpram_ctrl_init_30            |     6|
|246   |        dssram                  |ipbus_dpram_frame_init_31           |    10|
|247   |        framer                  |framing_sync_logic_32               |    15|
|248   |        ram_pointer             |tx_ram_pointer_33                   |    18|
|249   |      \bufgen[7].txbuf          |ipbus_data_source_19                |    45|
|250   |        ctrlram                 |ipbus_dpram_ctrl_init_26            |     2|
|251   |        dssram                  |ipbus_dpram_frame_init_27           |    10|
|252   |        framer                  |framing_sync_logic_28               |    15|
|253   |        ram_pointer             |tx_ram_pointer_29                   |    18|
|254   |      \bufgen[8].txbuf          |ipbus_data_source_20                |    49|
|255   |        ctrlram                 |ipbus_dpram_ctrl_init_22            |     7|
|256   |        dssram                  |ipbus_dpram_frame_init_23           |     9|
|257   |        framer                  |framing_sync_logic_24               |    15|
|258   |        ram_pointer             |tx_ram_pointer_25                   |    18|
|259   |      \bufgen[9].txbuf          |ipbus_data_source_21                |    44|
|260   |        ctrlram                 |ipbus_dpram_ctrl_init               |     2|
|261   |        dssram                  |ipbus_dpram_frame_init              |     9|
|262   |        framer                  |framing_sync_logic                  |    15|
|263   |        ram_pointer             |tx_ram_pointer                      |    18|
|264   |    xcvr_control                |ipbus_con_xcvr_control              |   142|
|265   |      quad115_116_regs          |ipbus_con_2quad_control             |    78|
|266   |        xcvr_control            |ipbus_ctrlreg_v__parameterized1_6   |    69|
|267   |      quad117_118_regs          |ipbus_con_2quad_control_5           |    64|
|268   |        xcvr_control            |ipbus_ctrlreg_v__parameterized1     |    64|
|269   |  ttc                           |ttc_fmc                             |   468|
|270   |    pll                         |pll_160MHz                          |     4|
|271   |    ttc_dec                     |ttc_decoder_core                    |   464|
|272   |      from_cdr_to_AandB         |cdr2a_b_clk                         |   144|
|273   |      serialb_com0              |serialb_com                         |   276|
|274   |  tx_arbiter                    |mac_arbiter                         |    31|
+------+--------------------------------+------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:02:44 ; elapsed = 00:03:16 . Memory (MB): peak = 2673.777 ; gain = 687.707 ; free physical = 2845 ; free virtual = 21013
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 52 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:02:35 ; elapsed = 00:03:05 . Memory (MB): peak = 2673.777 ; gain = 569.082 ; free physical = 2896 ; free virtual = 21064
Synthesis Optimization Complete : Time (s): cpu = 00:02:44 ; elapsed = 00:03:16 . Memory (MB): peak = 2673.781 ; gain = 687.707 ; free physical = 2896 ; free virtual = 21064
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2673.781 ; gain = 0.000 ; free physical = 2959 ; free virtual = 21127
INFO: [Netlist 29-17] Analyzing 936 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 1 inverter(s) to 4 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2673.781 ; gain = 0.000 ; free physical = 2898 ; free virtual = 21069
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 59 instances were transformed.
  IBUFGDS => IBUFDS: 6 instances
  IOBUF => IOBUF (IBUF, OBUFT): 4 instances
  MMCME2_BASE => MMCME2_ADV: 1 instance 
  MMCM_ADV => MMCME2_ADV: 1 instance 
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 26 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances
  SRL16 => SRL16E: 1 instance 

INFO: [Common 17-83] Releasing license: Synthesis
1008 Infos, 347 Warnings, 3 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:03:02 ; elapsed = 00:03:41 . Memory (MB): peak = 2673.781 ; gain = 959.547 ; free physical = 3070 ; free virtual = 21241
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2673.781 ; gain = 0.000 ; free physical = 3070 ; free virtual = 21241
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/synth_1/top_FTM_Control.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2673.781 ; gain = 0.000 ; free physical = 3070 ; free virtual = 21244
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_synth.rpt -pb top_FTM_Control_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed May 11 17:47:45 2022...