*** Running vivado with args -log DSS_3Quads_11g2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source DSS_3Quads_11g2.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source DSS_3Quads_11g2.tcl -notrace Command: synth_design -top DSS_3Quads_11g2 -part xc7vx415tffg1158-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx415t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx415t' INFO: [Device 21-403] Loading part xc7vx415tffg1158-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4806 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 2189.969 ; gain = 201.715 ; free physical = 2309 ; free virtual = 20422 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2.vhd:1064] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_init' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:75' bound to instance 'U0' of component 'DSS_3Quads_11g2_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2.vhd:2080] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:1078] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_multi_gt' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:73' bound to instance 'DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_multi_gt' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:3392] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_multi_gt' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:1349] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt0_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:1636] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:196] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 Parameter ACJTAG_DEBUG_MODE bound to: 1'b0 Parameter ACJTAG_MODE bound to: 1'b0 Parameter ACJTAG_RESET bound to: 1'b0 Parameter ADAPT_CFG0 bound to: 20'b00000000110000010000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 Parameter ALIGN_COMMA_WORD bound to: 4 - type: integer Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter A_RXOSCALRESET bound to: 1'b0 Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string Parameter CFOK_CFG bound to: 44'b00100100100000000000000001000000111010000000 Parameter CFOK_CFG2 bound to: 8'b00100000 Parameter CFOK_CFG3 bound to: 8'b00100000 Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 20 - type: integer Parameter CLK_COR_MIN_LAT bound to: 16 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 32'b00000000101111000000011111011100 Parameter CPLL_FBDIV bound to: 4 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: TRUE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CLK_PHASE_SEL bound to: 1'b0 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b000 Parameter IS_CLKRSVD0_INVERTED bound to: 1'b0 Parameter IS_CLKRSVD1_INVERTED bound to: 1'b0 Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter IS_DMONITORCLK_INVERTED bound to: 1'b0 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 Parameter IS_SIGVALIDCLK_INVERTED bound to: 1'b0 Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 Parameter LOOPBACK_CFG bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 32'b00000000000000000000000010000000 Parameter PMA_RSV2 bound to: 32'b00011100000000000000000000001010 Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 16'b0000000000001000 Parameter PMA_RSV5 bound to: 4'b0000 Parameter RESET_POWERSAVE_DISABLE bound to: 1'b0 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 84'b000000000000001000000000011111111110001000000000000011000010000010000000000000011010 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 12'b000000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: FALSE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00001000000000 Parameter RXLPM_LF_CFG bound to: 18'b001001000000000000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOOB_CLK_CFG bound to: PMA - type: string Parameter RXOSCALRESET_TIME bound to: 5'b00011 Parameter RXOSCALRESET_TIMEOUT bound to: 5'b00000 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b110000000000000000000010 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPI_CFG0 bound to: 2'b00 Parameter RXPI_CFG1 bound to: 2'b11 Parameter RXPI_CFG2 bound to: 2'b11 Parameter RXPI_CFG3 bound to: 2'b11 Parameter RXPI_CFG4 bound to: 1'b0 Parameter RXPI_CFG5 bound to: 1'b0 Parameter RXPI_CFG6 bound to: 3'b100 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: PCS - type: string Parameter RXSYNC_MULTILANE bound to: 1'b1 Parameter RXSYNC_OVRD bound to: 1'b0 Parameter RXSYNC_SKIP_DA bound to: 1'b0 Parameter RX_BIAS_CFG bound to: 24'b000011000000000000010000 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 12 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b11 Parameter RX_CM_TRIM bound to: 4'b1010 Parameter RX_DATA_WIDTH bound to: 40 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 14'b00000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFELPM_CFG0 bound to: 4'b0110 Parameter RX_DFELPM_CFG1 bound to: 1'b0 Parameter RX_DFELPM_KLKH_AGC_STUP_EN bound to: 1'b1 Parameter RX_DFE_AGC_CFG0 bound to: 2'b00 Parameter RX_DFE_AGC_CFG1 bound to: 3'b010 Parameter RX_DFE_AGC_CFG2 bound to: 4'b0000 Parameter RX_DFE_AGC_OVRDEN bound to: 1'b1 Parameter RX_DFE_GAIN_CFG bound to: 24'b000000000010000011000000 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011100000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_H6_CFG bound to: 12'b000000100000 Parameter RX_DFE_H7_CFG bound to: 12'b000000100000 Parameter RX_DFE_KL_CFG bound to: 33'b001000001000000000000001100010000 Parameter RX_DFE_KL_LPM_KH_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KH_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KH_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KH_OVRDEN bound to: 1'b1 Parameter RX_DFE_KL_LPM_KL_CFG0 bound to: 2'b01 Parameter RX_DFE_KL_LPM_KL_CFG1 bound to: 3'b010 Parameter RX_DFE_KL_LPM_KL_CFG2 bound to: 4'b0010 Parameter RX_DFE_KL_LPM_KL_OVRDEN bound to: 1'b1 Parameter RX_DFE_LPM_CFG bound to: 16'b0000000010000000 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_ST_CFG bound to: 56'b00000000111000010000000000000000000011000000000000111111 Parameter RX_DFE_UT_CFG bound to: 17'b00011100000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011101010100011 Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string Parameter RX_INT_DATAWIDTH bound to: 1 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXUSR - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter TERM_RCAL_CFG bound to: 15'b100001000010000 Parameter TERM_RCAL_OVRD bound to: 3'b000 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 Parameter TXBUF_EN bound to: FALSE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 12'b000000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: FALSE - type: string Parameter TXOOB_CFG bound to: 1'b0 Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPI_CFG0 bound to: 2'b00 Parameter TXPI_CFG1 bound to: 2'b00 Parameter TXPI_CFG2 bound to: 2'b00 Parameter TXPI_CFG3 bound to: 1'b0 Parameter TXPI_CFG4 bound to: 1'b0 Parameter TXPI_CFG5 bound to: 3'b100 Parameter TXPI_GREY_SEL bound to: 1'b0 Parameter TXPI_INVSTROBE_SEL bound to: 1'b0 Parameter TXPI_PPMCLK_SEL bound to: TXUSRCLK2 - type: string Parameter TXPI_PPM_CFG bound to: 8'b00000000 Parameter TXPI_SYNFREQ_PPM bound to: 3'b001 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TXSYNC_MULTILANE bound to: 1'b0 Parameter TXSYNC_OVRD bound to: 1'b1 Parameter TXSYNC_SKIP_DA bound to: 1'b0 Parameter TX_CLK25_DIV bound to: 12 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 40 - type: integer Parameter TX_DEEMPH0 bound to: 6'b000000 Parameter TX_DEEMPH1 bound to: 6'b000000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 Parameter TX_RXDETECT_PRECHARGE_TIME bound to: 20'b00010101010111001100 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXUSR - type: string Parameter UCODEER_CLR bound to: 1'b0 Parameter USE_PCS_CLK_PHASE_SEL bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'gthe2_i' to cell 'GTHE2_CHANNEL' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:247] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_GT' (1#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:196] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt1_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:1759] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt2_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:1883] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt3_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2007] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt4_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2131] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt5_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2254] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt6_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2378] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt7_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2502] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt8_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2626] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt9_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2749] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt10_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2873] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter TXSYNC_OVRD_IN bound to: 1'b1 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter TXSYNC_MULTILANE_IN bound to: 1'b0 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_gt.vhd:72' bound to instance 'gt11_DSS_3Quads_11g2_i' of component 'DSS_3Quads_11g2_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:2997] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_multi_gt' (2#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd:1349] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt0_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:4857] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:120] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_run_phase_alignment_int' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:276] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:97] Parameter INITIALISE bound to: 6'b000000 Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg1' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:130] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg2' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:140] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg3' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:150] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg4' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:160] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg5' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:170] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg6' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:180] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_sync_block' (3#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:97] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_tx_fsm_reset_done_int' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:284] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXRESETDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:301] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_time_out_wait_bypass' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:309] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_mmcm_lock_reclocked' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:317] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_CPLLLOCK' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:337] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_QPLLLOCK' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:345] WARNING: [Synth 8-6014] Unused sequential element cplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:332] WARNING: [Synth 8-6014] Unused sequential element qplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:333] WARNING: [Synth 8-6014] Unused sequential element cplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:358] WARNING: [Synth 8-6014] Unused sequential element qplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:373] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_TX_STARTUP_FSM' (4#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:120] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt1_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:4891] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt2_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:4925] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt3_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:4959] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt4_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:4993] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt5_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5027] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt6_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5061] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt7_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5095] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt8_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5129] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt9_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5163] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt10_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5197] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 1 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_startup_fsm.vhd:74' bound to instance 'gt11_txresetfsm_i' of component 'DSS_3Quads_11g2_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5231] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt0_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5272] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:134] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:248] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'reset_sync1_rx' to cell 'FDP' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:304] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'reset_sync2_rx' to cell 'FDP' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:315] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_pmaresetdone_fallingedge_detect' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:337] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_rxpmaresetdone' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:345] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_rxpmaresetdone_rx_s' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:353] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_run_phase_alignment_int' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:445] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_rx_fsm_reset_done_int' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:458] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_RXRESETDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:475] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_time_out_wait_bypass' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:483] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_mmcm_lock_reclocked' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:491] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_data_valid' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:499] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_CPLLLOCK' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:519] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_QPLLLOCK' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:527] WARNING: [Synth 8-6014] Unused sequential element adapt_wait_hw.adapt_count_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:284] WARNING: [Synth 8-6014] Unused sequential element adapt_wait_hw.time_out_adapt_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:285] WARNING: [Synth 8-6014] Unused sequential element time_out_500us_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:389] WARNING: [Synth 8-6014] Unused sequential element time_out_1us_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:390] WARNING: [Synth 8-6014] Unused sequential element cplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:514] WARNING: [Synth 8-6014] Unused sequential element qplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:515] WARNING: [Synth 8-6014] Unused sequential element cplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:541] WARNING: [Synth 8-6014] Unused sequential element qplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:556] WARNING: [Synth 8-6014] Unused sequential element rx_fsm_reset_done_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:628] WARNING: [Synth 8-6014] Unused sequential element pll_reset_asserted_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:631] WARNING: [Synth 8-6014] Unused sequential element adapt_count_reset_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:283] WARNING: [Synth 8-3848] Net pmaresetdone_fallingedge_detect in module/entity DSS_3Quads_11g2_RX_STARTUP_FSM does not have driver. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:206] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_RX_STARTUP_FSM' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:134] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt1_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5319] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt2_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5366] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt3_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5413] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt4_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5460] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt5_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5507] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt6_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5554] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt7_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5601] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt8_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5648] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt9_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5695] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt10_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5742] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:76' bound to instance 'gt11_rxresetfsm_i' of component 'DSS_3Quads_11g2_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5789] Parameter NUMBER_OF_LANES bound to: 4 - type: integer Parameter MASTER_LANE_ID bound to: 0 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:73' bound to instance 'gt0_tx_manual_phase_i' of component 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6037] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:93] Parameter NUMBER_OF_LANES bound to: 4 - type: integer Parameter MASTER_LANE_ID bound to: 0 - type: integer Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXPHALIGNDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:146] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXDLYSRESETDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:154] Parameter C_NUM_SRETCH_REGS bound to: 3 - type: integer Parameter C_NUM_SYNC_REGS bound to: 3 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_pulse' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:75' bound to instance 'sync_TXPHINITDONE' of component 'DSS_3Quads_11g2_sync_pulse' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:162] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_sync_pulse' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:92] Parameter C_NUM_SRETCH_REGS bound to: 3 - type: integer Parameter C_NUM_SYNC_REGS bound to: 3 - type: integer INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:98] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:98] INFO: [Synth 8-5534] Detected attribute (* shreg_extract = "no" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:99] INFO: [Synth 8-5534] Detected attribute (* async_reg = "TRUE" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:99] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_sync_pulse' (6#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:92] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXPHALIGNDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:146] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXDLYSRESETDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:154] Parameter C_NUM_SRETCH_REGS bound to: 3 - type: integer Parameter C_NUM_SYNC_REGS bound to: 3 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_pulse' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:75' bound to instance 'sync_TXPHINITDONE' of component 'DSS_3Quads_11g2_sync_pulse' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:162] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXPHALIGNDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:146] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXDLYSRESETDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:154] Parameter C_NUM_SRETCH_REGS bound to: 3 - type: integer Parameter C_NUM_SYNC_REGS bound to: 3 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_pulse' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:75' bound to instance 'sync_TXPHINITDONE' of component 'DSS_3Quads_11g2_sync_pulse' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:162] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXPHALIGNDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:146] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_TXDLYSRESETDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:154] Parameter C_NUM_SRETCH_REGS bound to: 3 - type: integer Parameter C_NUM_SYNC_REGS bound to: 3 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_pulse' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd:75' bound to instance 'sync_TXPHINITDONE' of component 'DSS_3Quads_11g2_sync_pulse' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:162] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' (7#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:93] Parameter NUMBER_OF_LANES bound to: 4 - type: integer Parameter MASTER_LANE_ID bound to: 0 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:73' bound to instance 'gt4_tx_manual_phase_i' of component 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6133] Parameter NUMBER_OF_LANES bound to: 4 - type: integer Parameter MASTER_LANE_ID bound to: 0 - type: integer INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:73' bound to instance 'gt8_tx_manual_phase_i' of component 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6229] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt0_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6334] INFO: [Synth 8-638] synthesizing module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:93] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_PHALIGNDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:120] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_block.vhd:81' bound to instance 'sync_DLYSRESETDONE' of component 'DSS_3Quads_11g2_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:128] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:162] WARNING: [Synth 8-6014] Unused sequential element count_phalign_edges_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:150] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' (8#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:93] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt1_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6354] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt2_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6371] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt3_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6388] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt4_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6405] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt5_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6422] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt6_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6439] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt7_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6456] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt8_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6473] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt9_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6490] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt10_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6507] INFO: [Synth 8-3491] module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd:80' bound to instance 'gt11_rx_auto_phase_align_i' of component 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6524] WARNING: [Synth 8-6014] Unused sequential element gt1_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5856] WARNING: [Synth 8-6014] Unused sequential element gt1_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5857] WARNING: [Synth 8-6014] Unused sequential element gt2_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5871] WARNING: [Synth 8-6014] Unused sequential element gt2_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5872] WARNING: [Synth 8-6014] Unused sequential element gt3_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5886] WARNING: [Synth 8-6014] Unused sequential element gt3_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5887] WARNING: [Synth 8-6014] Unused sequential element gt4_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5901] WARNING: [Synth 8-6014] Unused sequential element gt4_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5902] WARNING: [Synth 8-6014] Unused sequential element gt5_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5916] WARNING: [Synth 8-6014] Unused sequential element gt5_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5917] WARNING: [Synth 8-6014] Unused sequential element gt6_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5931] WARNING: [Synth 8-6014] Unused sequential element gt6_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5932] WARNING: [Synth 8-6014] Unused sequential element gt7_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5946] WARNING: [Synth 8-6014] Unused sequential element gt7_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5947] WARNING: [Synth 8-6014] Unused sequential element gt8_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5961] WARNING: [Synth 8-6014] Unused sequential element gt8_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5962] WARNING: [Synth 8-6014] Unused sequential element gt9_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5976] WARNING: [Synth 8-6014] Unused sequential element gt9_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5977] WARNING: [Synth 8-6014] Unused sequential element gt10_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5991] WARNING: [Synth 8-6014] Unused sequential element gt10_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:5992] WARNING: [Synth 8-6014] Unused sequential element gt11_rx_cdrlocked_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6006] WARNING: [Synth 8-6014] Unused sequential element gt11_rx_cdrlock_counter_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:6007] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2_init' (9#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2_init.vhd:1078] INFO: [Synth 8-256] done synthesizing module 'DSS_3Quads_11g2' (10#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/dss_3quads_11g2.vhd:1064] WARNING: [Synth 8-3331] design DSS_3Quads_11g2_RX_STARTUP_FSM has unconnected port QPLLREFCLKLOST WARNING: [Synth 8-3331] design DSS_3Quads_11g2_RX_STARTUP_FSM has unconnected port CPLLREFCLKLOST WARNING: [Synth 8-3331] design DSS_3Quads_11g2_TX_STARTUP_FSM has unconnected port CPLLREFCLKLOST WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt11_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt11_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt11_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt11_txuserrdy_in --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2262.691 ; gain = 274.438 ; free physical = 2302 ; free virtual = 20416 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2265.656 ; gain = 277.402 ; free physical = 2301 ; free virtual = 20415 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2265.656 ; gain = 277.402 ; free physical = 2301 ; free virtual = 20415 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2271.594 ; gain = 0.000 ; free physical = 2294 ; free virtual = 20408 INFO: [Netlist 29-17] Analyzing 1608 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2_ooc.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/DSS_3Quads_11g2_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/DSS_3Quads_11g2_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2402.391 ; gain = 0.000 ; free physical = 2190 ; free virtual = 20303 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1608 instances were transformed. FD => FDRE: 1584 instances FDP => FDPE: 24 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2409.328 ; gain = 6.938 ; free physical = 2188 ; free virtual = 20302 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 2409.328 ; gain = 421.074 ; free physical = 2274 ; free virtual = 20388 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx415tffg1158-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 2409.328 ; gain = 421.074 ; free physical = 2274 ; free virtual = 20388 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/DSS_3Quads_11g2_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 2409.328 ; gain = 421.074 ; free physical = 2274 ; free virtual = 20388 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'tx_state_reg' in module 'DSS_3Quads_11g2_TX_STARTUP_FSM' INFO: [Synth 8-5544] ROM "TXUSERRDY" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "gttxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MMCM_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "tx_fsm_reset_done_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "QPLL_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-4471] merging register 'CPLL_RESET_reg' into 'QPLL_RESET_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:630] INFO: [Synth 8-4471] merging register 'RXDFELFHOLD_reg' into 'RXDFEAGCHOLD_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:640] INFO: [Synth 8-4471] merging register 'RXLPMLFHOLD_reg' into 'RXDFEAGCHOLD_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:641] INFO: [Synth 8-4471] merging register 'RXLPMHFHOLD_reg' into 'RXDFEAGCHOLD_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd:642] INFO: [Synth 8-802] inferred FSM for state register 'rx_state_reg' in module 'DSS_3Quads_11g2_RX_STARTUP_FSM' INFO: [Synth 8-5544] ROM "gtrxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "mmcm_reset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "RXDFEAGCHOLD" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-4471] merging register 'txphinitdone_clear_slave_reg' into 'txdone_clear_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd:209] INFO: [Synth 8-802] inferred FSM for state register 'tx_phalign_manual_state_reg' in module 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' INFO: [Synth 8-5544] ROM "PHASE_ALIGNMENT_DONE" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "TXPHINIT" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "TXPHALIGN" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "TXDLYEN" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "txphinitdone_clear_slave" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'phalign_state_reg' in module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 assert_all_resets | 0001 | 0001 wait_for_pll_lock | 0010 | 0010 release_pll_reset | 0011 | 0011 wait_for_txoutclk | 0100 | 0100 release_mmcm_reset | 0101 | 0101 wait_for_txusrclk | 0110 | 0110 wait_reset_done | 0111 | 0111 do_phase_alignment | 1000 | 1000 reset_fsm_done | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_state_reg' using encoding 'sequential' in module 'DSS_3Quads_11g2_TX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 assert_all_resets | 0001 | 0001 wait_for_pll_lock | 0010 | 0010 release_pll_reset | 0011 | 0011 verify_recclk_stable | 0100 | 0100 release_mmcm_reset | 0101 | 0101 wait_for_rxusrclk | 0110 | 0110 wait_reset_done | 0111 | 0111 do_phase_alignment | 1000 | 1000 monitor_data_valid | 1001 | 1001 fsm_done | 1010 | 1010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_reg' using encoding 'sequential' in module 'DSS_3Quads_11g2_RX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 wait_phrst_done | 0001 | 0001 m_phinit | 0010 | 0010 m_phalign | 0011 | 0011 m_dlyen | 0100 | 0100 s_phinit | 0101 | 0101 s_phalign | 0110 | 0110 m_dlyen2 | 0111 | 0111 phalign_done | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_phalign_manual_state_reg' using encoding 'sequential' in module 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0001 | 00 wait_phrst_done | 0010 | 01 count_phalign_done | 0100 | 10 phalign_done | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'phalign_state_reg' using encoding 'one-hot' in module 'DSS_3Quads_11g2_AUTO_PHASE_ALIGN' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:25 ; elapsed = 00:00:39 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2264 ; free virtual = 20380 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 11 Bit Adders := 1 2 Input 8 Bit Adders := 48 2 Input 7 Bit Adders := 48 2 Input 2 Bit Adders := 12 +---Registers : 11 Bit Registers := 1 8 Bit Registers := 48 7 Bit Registers := 48 4 Bit Registers := 27 3 Bit Registers := 36 2 Bit Registers := 12 1 Bit Registers := 571 +---Muxes : 2 Input 8 Bit Muxes := 24 10 Input 4 Bit Muxes := 12 2 Input 4 Bit Muxes := 141 11 Input 4 Bit Muxes := 12 9 Input 4 Bit Muxes := 24 4 Input 4 Bit Muxes := 12 2 Input 2 Bit Muxes := 12 2 Input 1 Bit Muxes := 273 10 Input 1 Bit Muxes := 204 11 Input 1 Bit Muxes := 204 9 Input 1 Bit Muxes := 15 4 Input 1 Bit Muxes := 24 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module DSS_3Quads_11g2_TX_STARTUP_FSM Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 2 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 2 1 Bit Registers := 20 +---Muxes : 2 Input 8 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 1 Bit Muxes := 10 10 Input 1 Bit Muxes := 17 Module DSS_3Quads_11g2_RX_STARTUP_FSM Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 2 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 23 +---Muxes : 2 Input 8 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 6 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 12 11 Input 1 Bit Muxes := 17 Module DSS_3Quads_11g2_sync_pulse Detailed RTL Component Info : +---Registers : 3 Bit Registers := 3 1 Bit Registers := 1 Module DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN Detailed RTL Component Info : +---Registers : 4 Bit Registers := 9 1 Bit Registers := 2 +---Muxes : 2 Input 4 Bit Muxes := 3 9 Input 4 Bit Muxes := 8 2 Input 1 Bit Muxes := 3 9 Input 1 Bit Muxes := 5 Module DSS_3Quads_11g2_AUTO_PHASE_ALIGN Detailed RTL Component Info : +---Registers : 1 Bit Registers := 3 +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 4 Input 1 Bit Muxes := 2 Module DSS_3Quads_11g2_init Detailed RTL Component Info : +---Adders : 2 Input 11 Bit Adders := 1 +---Registers : 11 Bit Registers := 1 1 Bit Registers := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2160 (col length:120) BRAMs: 1760 (col length: RAMB18 120 RAMB36 60) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met WARNING: [Synth 8-3331] design DSS_3Quads_11g2_RX_STARTUP_FSM has unconnected port QPLLREFCLKLOST WARNING: [Synth 8-3331] design DSS_3Quads_11g2_RX_STARTUP_FSM has unconnected port CPLLREFCLKLOST WARNING: [Synth 8-3331] design DSS_3Quads_11g2_TX_STARTUP_FSM has unconnected port CPLLREFCLKLOST WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt0_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt1_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt2_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt3_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt4_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt5_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt6_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt7_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt8_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt9_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_gtrxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_gttxreset_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt10_txuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt11_rxuserrdy_in WARNING: [Synth 8-3331] design DSS_3Quads_11g2_init has unconnected port gt11_gtrxreset_in INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (DSS_3Quads_11g2_RX_STARTUP_FSM:/RXDFEAGCHOLD_reg) INFO: [Synth 8-3333] propagating constant 0 across sequential element (DSS_3Quads_11g2_RX_STARTUP_FSM:/QPLL_RESET_reg) INFO: [Synth 8-3886] merging instance 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN:/TXDLYEN_reg[1]' (FDRE) to 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN:/TXDLYEN_reg[3]' INFO: [Synth 8-3886] merging instance 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN:/TXDLYEN_reg[2]' (FDRE) to 'DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN:/TXDLYEN_reg[3]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN:/\TXDLYEN_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (DSS_3Quads_11g2_TX_STARTUP_FSM:/CPLL_RESET_reg) WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg1) is unused and will be removed from module DSS_3Quads_11g2_TX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg2) is unused and will be removed from module DSS_3Quads_11g2_TX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg3) is unused and will be removed from module DSS_3Quads_11g2_TX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg4) is unused and will be removed from module DSS_3Quads_11g2_TX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg5) is unused and will be removed from module DSS_3Quads_11g2_TX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg6) is unused and will be removed from module DSS_3Quads_11g2_TX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_pmaresetdone_fallingedge_detect/data_sync_reg1) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_pmaresetdone_fallingedge_detect/data_sync_reg2) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_pmaresetdone_fallingedge_detect/data_sync_reg3) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_pmaresetdone_fallingedge_detect/data_sync_reg4) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_pmaresetdone_fallingedge_detect/data_sync_reg5) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_pmaresetdone_fallingedge_detect/data_sync_reg6) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg1) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg2) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg3) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg4) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg5) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone/data_sync_reg6) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg1) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg2) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg3) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg4) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg5) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_rxpmaresetdone_rx_s/data_sync_reg6) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg1) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg2) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg3) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg4) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg5) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (sync_CPLLLOCK/data_sync_reg6) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (reset_sync1_rx) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. WARNING: [Synth 8-3332] Sequential element (reset_sync2_rx) is unused and will be removed from module DSS_3Quads_11g2_RX_STARTUP_FSM. INFO: [Synth 8-3332] Sequential element (gt1_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt2_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt3_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt4_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt5_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt6_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt7_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt8_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt9_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt10_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3332] Sequential element (gt11_rx_auto_phase_align_i/FSM_onehot_phalign_state_reg[3]) is unused and will be removed from module DSS_3Quads_11g2_init. INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt11_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt11_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt10_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt10_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt9_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt9_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt8_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt8_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt7_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt7_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt6_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt6_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt5_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt5_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt4_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt4_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt3_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt3_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt2_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt2_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt1_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt1_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt0_rxresetfsm_i/\recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/gt0_rxresetfsm_i/\recclk_mon_restart_count_reg[1] ) --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:53 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2244 ; free virtual = 20363 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:44 ; elapsed = 00:01:10 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2119 ; free virtual = 20239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:46 ; elapsed = 00:01:11 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2112 ; free virtual = 20231 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:49 ; elapsed = 00:01:15 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20223 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:53 ; elapsed = 00:01:19 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:53 ; elapsed = 00:01:19 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20222 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:54 ; elapsed = 00:01:20 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:54 ; elapsed = 00:01:20 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:54 ; elapsed = 00:01:20 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:54 ; elapsed = 00:01:20 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------------+------+ | |Cell |Count | +------+--------------+------+ |1 |CARRY4 | 264| |2 |GTHE2_CHANNEL | 12| |3 |LUT1 | 196| |4 |LUT2 | 410| |5 |LUT3 | 260| |6 |LUT4 | 433| |7 |LUT5 | 451| |8 |LUT6 | 643| |9 |FD | 1224| |10 |FDCE | 228| |11 |FDRE | 1798| |12 |FDSE | 100| +------+--------------+------+ Report Instance Areas: +------+------------------------------------+-----------------------------------------+------+ | |Instance |Module |Cells | +------+------------------------------------+-----------------------------------------+------+ |1 |top | | 6019| |2 | U0 |DSS_3Quads_11g2_init | 6019| |3 | DSS_3Quads_11g2_i |DSS_3Quads_11g2_multi_gt | 27| |4 | gt0_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT | 2| |5 | gt10_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_249 | 3| |6 | gt11_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_250 | 2| |7 | gt1_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_251 | 2| |8 | gt2_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_252 | 2| |9 | gt3_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_253 | 3| |10 | gt4_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_254 | 2| |11 | gt5_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_255 | 2| |12 | gt6_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_256 | 2| |13 | gt7_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_257 | 3| |14 | gt8_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_258 | 2| |15 | gt9_DSS_3Quads_11g2_i |DSS_3Quads_11g2_GT_259 | 2| |16 | gt0_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN | 24| |17 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_247 | 6| |18 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_248 | 8| |19 | gt0_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM | 226| |20 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_240 | 7| |21 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_241 | 6| |22 | sync_data_valid |DSS_3Quads_11g2_sync_block_242 | 15| |23 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_243 | 8| |24 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_244 | 6| |25 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_245 | 6| |26 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_246 | 6| |27 | gt0_tx_manual_phase_i |DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN | 174| |28 | \cdc[0].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_228 | 7| |29 | \cdc[0].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_229 | 13| |30 | \cdc[0].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_230 | 14| |31 | \cdc[1].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_231 | 7| |32 | \cdc[1].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_232 | 7| |33 | \cdc[1].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_233 | 12| |34 | \cdc[2].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_234 | 7| |35 | \cdc[2].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_235 | 7| |36 | \cdc[2].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_236 | 12| |37 | \cdc[3].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_237 | 7| |38 | \cdc[3].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_238 | 7| |39 | \cdc[3].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_239 | 12| |40 | gt0_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM | 208| |41 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_222 | 11| |42 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_223 | 6| |43 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_224 | 8| |44 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_225 | 6| |45 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_226 | 6| |46 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_227 | 6| |47 | gt10_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_0 | 22| |48 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_220 | 6| |49 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_221 | 9| |50 | gt10_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_1 | 225| |51 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_213 | 7| |52 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_214 | 6| |53 | sync_data_valid |DSS_3Quads_11g2_sync_block_215 | 15| |54 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_216 | 8| |55 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_217 | 6| |56 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_218 | 6| |57 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_219 | 6| |58 | gt10_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_2 | 205| |59 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_207 | 11| |60 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_208 | 6| |61 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_209 | 8| |62 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_210 | 6| |63 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_211 | 6| |64 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_212 | 6| |65 | gt11_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_3 | 22| |66 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_205 | 6| |67 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_206 | 9| |68 | gt11_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_4 | 225| |69 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_198 | 7| |70 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_199 | 6| |71 | sync_data_valid |DSS_3Quads_11g2_sync_block_200 | 15| |72 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_201 | 8| |73 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_202 | 6| |74 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_203 | 6| |75 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_204 | 6| |76 | gt11_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_5 | 207| |77 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_192 | 11| |78 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_193 | 6| |79 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_194 | 8| |80 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_195 | 6| |81 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_196 | 6| |82 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_197 | 6| |83 | gt1_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_6 | 22| |84 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_190 | 6| |85 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_191 | 9| |86 | gt1_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_7 | 225| |87 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_183 | 7| |88 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_184 | 6| |89 | sync_data_valid |DSS_3Quads_11g2_sync_block_185 | 15| |90 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_186 | 8| |91 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_187 | 6| |92 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_188 | 6| |93 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_189 | 6| |94 | gt1_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_8 | 205| |95 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_177 | 11| |96 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_178 | 6| |97 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_179 | 8| |98 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_180 | 6| |99 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_181 | 6| |100 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_182 | 6| |101 | gt2_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_9 | 22| |102 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_175 | 6| |103 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_176 | 9| |104 | gt2_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_10 | 225| |105 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_168 | 7| |106 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_169 | 6| |107 | sync_data_valid |DSS_3Quads_11g2_sync_block_170 | 15| |108 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_171 | 8| |109 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_172 | 6| |110 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_173 | 6| |111 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_174 | 6| |112 | gt2_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_11 | 205| |113 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_162 | 11| |114 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_163 | 6| |115 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_164 | 8| |116 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_165 | 6| |117 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_166 | 6| |118 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_167 | 6| |119 | gt3_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_12 | 22| |120 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_160 | 6| |121 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_161 | 9| |122 | gt3_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_13 | 225| |123 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_153 | 7| |124 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_154 | 6| |125 | sync_data_valid |DSS_3Quads_11g2_sync_block_155 | 15| |126 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_156 | 8| |127 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_157 | 6| |128 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_158 | 6| |129 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_159 | 6| |130 | gt3_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_14 | 207| |131 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_147 | 11| |132 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_148 | 6| |133 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_149 | 8| |134 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_150 | 6| |135 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_151 | 6| |136 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_152 | 6| |137 | gt4_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_15 | 22| |138 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_145 | 6| |139 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_146 | 9| |140 | gt4_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_16 | 225| |141 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_138 | 7| |142 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_139 | 6| |143 | sync_data_valid |DSS_3Quads_11g2_sync_block_140 | 15| |144 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_141 | 8| |145 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_142 | 6| |146 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_143 | 6| |147 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_144 | 6| |148 | gt4_tx_manual_phase_i |DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN_17 | 174| |149 | \cdc[0].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_126 | 7| |150 | \cdc[0].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_127 | 13| |151 | \cdc[0].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_128 | 14| |152 | \cdc[1].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_129 | 7| |153 | \cdc[1].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_130 | 7| |154 | \cdc[1].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_131 | 12| |155 | \cdc[2].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_132 | 7| |156 | \cdc[2].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_133 | 7| |157 | \cdc[2].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_134 | 12| |158 | \cdc[3].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_135 | 7| |159 | \cdc[3].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_136 | 7| |160 | \cdc[3].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_137 | 12| |161 | gt4_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_18 | 208| |162 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_120 | 11| |163 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_121 | 6| |164 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_122 | 8| |165 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_123 | 6| |166 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_124 | 6| |167 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_125 | 6| |168 | gt5_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_19 | 22| |169 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_118 | 6| |170 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_119 | 9| |171 | gt5_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_20 | 225| |172 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_111 | 7| |173 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_112 | 6| |174 | sync_data_valid |DSS_3Quads_11g2_sync_block_113 | 15| |175 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_114 | 8| |176 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_115 | 6| |177 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_116 | 6| |178 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_117 | 6| |179 | gt5_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_21 | 205| |180 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_105 | 11| |181 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_106 | 6| |182 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_107 | 8| |183 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_108 | 6| |184 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_109 | 6| |185 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_110 | 6| |186 | gt6_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_22 | 22| |187 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_103 | 6| |188 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_104 | 9| |189 | gt6_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_23 | 225| |190 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_96 | 7| |191 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_97 | 6| |192 | sync_data_valid |DSS_3Quads_11g2_sync_block_98 | 15| |193 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_99 | 8| |194 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_100 | 6| |195 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_101 | 6| |196 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_102 | 6| |197 | gt6_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_24 | 205| |198 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_90 | 11| |199 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_91 | 6| |200 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_92 | 8| |201 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_93 | 6| |202 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_94 | 6| |203 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_95 | 6| |204 | gt7_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_25 | 22| |205 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_88 | 6| |206 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_89 | 9| |207 | gt7_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_26 | 225| |208 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_81 | 7| |209 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_82 | 6| |210 | sync_data_valid |DSS_3Quads_11g2_sync_block_83 | 15| |211 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_84 | 8| |212 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_85 | 6| |213 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_86 | 6| |214 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_87 | 6| |215 | gt7_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_27 | 207| |216 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_75 | 11| |217 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_76 | 6| |218 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_77 | 8| |219 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_78 | 6| |220 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_79 | 6| |221 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_80 | 6| |222 | gt8_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_28 | 22| |223 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_73 | 6| |224 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_74 | 9| |225 | gt8_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_29 | 225| |226 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_66 | 7| |227 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_67 | 6| |228 | sync_data_valid |DSS_3Quads_11g2_sync_block_68 | 15| |229 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_69 | 8| |230 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_70 | 6| |231 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_71 | 6| |232 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_72 | 6| |233 | gt8_tx_manual_phase_i |DSS_3Quads_11g2_TX_MANUAL_PHASE_ALIGN_30 | 174| |234 | \cdc[0].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_55 | 7| |235 | \cdc[0].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_56 | 13| |236 | \cdc[0].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse | 14| |237 | \cdc[1].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_57 | 7| |238 | \cdc[1].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_58 | 7| |239 | \cdc[1].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_59 | 12| |240 | \cdc[2].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_60 | 7| |241 | \cdc[2].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_61 | 7| |242 | \cdc[2].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_62 | 12| |243 | \cdc[3].sync_TXDLYSRESETDONE |DSS_3Quads_11g2_sync_block_63 | 7| |244 | \cdc[3].sync_TXPHALIGNDONE |DSS_3Quads_11g2_sync_block_64 | 7| |245 | \cdc[3].sync_TXPHINITDONE |DSS_3Quads_11g2_sync_pulse_65 | 12| |246 | gt8_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_31 | 208| |247 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_49 | 11| |248 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_50 | 6| |249 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_51 | 8| |250 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_52 | 6| |251 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_53 | 6| |252 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_54 | 6| |253 | gt9_rx_auto_phase_align_i |DSS_3Quads_11g2_AUTO_PHASE_ALIGN_32 | 22| |254 | sync_DLYSRESETDONE |DSS_3Quads_11g2_sync_block_47 | 6| |255 | sync_PHALIGNDONE |DSS_3Quads_11g2_sync_block_48 | 9| |256 | gt9_rxresetfsm_i |DSS_3Quads_11g2_RX_STARTUP_FSM_33 | 225| |257 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block_40 | 7| |258 | sync_RXRESETDONE |DSS_3Quads_11g2_sync_block_41 | 6| |259 | sync_data_valid |DSS_3Quads_11g2_sync_block_42 | 15| |260 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_43 | 8| |261 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_44 | 6| |262 | sync_rx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_45 | 6| |263 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_46 | 6| |264 | gt9_txresetfsm_i |DSS_3Quads_11g2_TX_STARTUP_FSM_34 | 205| |265 | sync_QPLLLOCK |DSS_3Quads_11g2_sync_block | 11| |266 | sync_TXRESETDONE |DSS_3Quads_11g2_sync_block_35 | 6| |267 | sync_mmcm_lock_reclocked |DSS_3Quads_11g2_sync_block_36 | 8| |268 | sync_run_phase_alignment_int |DSS_3Quads_11g2_sync_block_37 | 6| |269 | sync_time_out_wait_bypass |DSS_3Quads_11g2_sync_block_38 | 6| |270 | sync_tx_fsm_reset_done_int |DSS_3Quads_11g2_sync_block_39 | 6| +------+------------------------------------+-----------------------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:54 ; elapsed = 00:01:20 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2103 ; free virtual = 20222 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 83 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:47 ; elapsed = 00:01:12 . Memory (MB): peak = 2409.332 ; gain = 277.406 ; free physical = 2155 ; free virtual = 20275 Synthesis Optimization Complete : Time (s): cpu = 00:00:54 ; elapsed = 00:01:20 . Memory (MB): peak = 2409.332 ; gain = 421.078 ; free physical = 2155 ; free virtual = 20275 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2409.332 ; gain = 0.000 ; free physical = 2225 ; free virtual = 20345 INFO: [Netlist 29-17] Analyzing 1488 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2413.297 ; gain = 0.000 ; free physical = 2162 ; free virtual = 20282 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1224 instances were transformed. FD => FDRE: 1224 instances INFO: [Common 17-83] Releasing license: Synthesis 203 Infos, 171 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:19 ; elapsed = 00:02:12 . Memory (MB): peak = 2413.297 ; gain = 791.781 ; free physical = 2303 ; free virtual = 20422 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2413.297 ; gain = 0.000 ; free physical = 2303 ; free virtual = 20422 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/DSS_3Quads_11g2_synth_1/DSS_3Quads_11g2.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP DSS_3Quads_11g2, cache-ID = ecb786f6a1ce763b INFO: [Coretcl 2-1174] Renamed 269 cell refs. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2437.312 ; gain = 0.000 ; free physical = 2279 ; free virtual = 20407 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/DSS_3Quads_11g2_synth_1/DSS_3Quads_11g2.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file DSS_3Quads_11g2_utilization_synth.rpt -pb DSS_3Quads_11g2_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Wed Jun 8 13:31:17 2022...