*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: link_design -top top_FTM_DSS -part xc7vx415tffg1158-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.dcp' for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_bcr.dcp' for cell 'slaves/buffer_control/bcr_delays'
Netlist sorting complete. Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2100.039 ; gain = 3.996 ; free physical = 3377 ; free virtual = 21528
INFO: [Netlist 29-17] Analyzing 3334 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: slaves/buffer_control/bcr_delays UUID: b6fbd4f1-3519-5b57-8709-90667c26e79c 
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_114_116/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_214_216/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xdc] for cell 'mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_bcr/ila_v6_2/constraints/ila.xdc] for cell 'slaves/buffer_control/bcr_delays/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc:5]
get_clocks: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 3124.676 ; gain = 793.535 ; free physical = 2480 ; free virtual = 20631
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS_pinout.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_refclks.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/FTM_DSS.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/spi_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS/xdc/DSS_mgt_ip.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3298.570 ; gain = 0.000 ; free physical = 2530 ; free virtual = 20682
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 42 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances
  OBUFDS => OBUFDS: 10 instances

12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:01:05 ; elapsed = 00:02:01 . Memory (MB): peak = 3298.570 ; gain = 1659.488 ; free physical = 2530 ; free virtual = 20682
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/DSS_3Quads_11g2.xci
Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7vx415t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/DSS_3Quads_11g2/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:01 . Memory (MB): peak = 3314.578 ; gain = 8.004 ; free physical = 2529 ; free virtual = 20680

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 190fa4b9c

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3321.578 ; gain = 7.000 ; free physical = 2295 ; free virtual = 20447

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3577.160 ; gain = 43.965 ; free physical = 2044 ; free virtual = 20201
Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3577.160 ; gain = 0.000 ; free physical = 2045 ; free virtual = 20201
Phase 1 Generate And Synthesize Debug Cores | Checksum: 13b87e7da

Time (s): cpu = 00:02:27 ; elapsed = 00:04:55 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2045 ; free virtual = 20201

Phase 2 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 2 Retarget | Checksum: 1fd9b4d11

Time (s): cpu = 00:02:32 ; elapsed = 00:05:01 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2176 ; free virtual = 20332
INFO: [Opt 31-389] Phase Retarget created 54 cells and removed 120 cells
INFO: [Opt 31-1021] In phase Retarget, 112 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 3 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 3 Constant propagation | Checksum: 1fb19ed41

Time (s): cpu = 00:02:33 ; elapsed = 00:05:02 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2176 ; free virtual = 20332
INFO: [Opt 31-389] Phase Constant propagation created 13 cells and removed 30 cells
INFO: [Opt 31-1021] In phase Constant propagation, 47 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Sweep
Phase 4 Sweep | Checksum: 17082cee0

Time (s): cpu = 00:02:38 ; elapsed = 00:05:06 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2173 ; free virtual = 20330
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 706 cells
INFO: [Opt 31-1021] In phase Sweep, 954 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 BUFG optimization
INFO: [Opt 31-274] Optimized connectivity to 4 cascaded buffer cells
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
Phase 5 BUFG optimization | Checksum: 187d4dd5a

Time (s): cpu = 00:02:39 ; elapsed = 00:05:08 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2176 ; free virtual = 20332
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 4 cells.

Phase 6 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 6 Shift Register Optimization | Checksum: 187d4dd5a

Time (s): cpu = 00:02:40 ; elapsed = 00:05:09 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2176 ; free virtual = 20332
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 7 Post Processing Netlist
Phase 7 Post Processing Netlist | Checksum: 2007ce183

Time (s): cpu = 00:02:41 ; elapsed = 00:05:09 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2176 ; free virtual = 20332
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 58 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              54  |             120  |                                            112  |
|  Constant propagation         |              13  |              30  |                                             47  |
|  Sweep                        |               0  |             706  |                                            954  |
|  BUFG optimization            |               0  |               4  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                             58  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3577.164 ; gain = 0.000 ; free physical = 2175 ; free virtual = 20332
Ending Logic Optimization Task | Checksum: 14d06f75b

Time (s): cpu = 00:02:44 ; elapsed = 00:05:12 . Memory (MB): peak = 3577.164 ; gain = 75.840 ; free physical = 2175 ; free virtual = 20332

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.475 | TNS=0.000 |
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 644 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 1288
Ending PowerOpt Patch Enables Task | Checksum: 151d66602

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4700.500 ; gain = 0.000 ; free physical = 1888 ; free virtual = 20045
Ending Power Optimization Task | Checksum: 151d66602

Time (s): cpu = 00:01:35 ; elapsed = 00:01:40 . Memory (MB): peak = 4700.500 ; gain = 1123.336 ; free physical = 1997 ; free virtual = 20154

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 1d03688b4

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 4700.500 ; gain = 0.000 ; free physical = 1857 ; free virtual = 20013
Ending Final Cleanup Task | Checksum: 1d03688b4

Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 4700.500 ; gain = 0.000 ; free physical = 1855 ; free virtual = 20012

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4700.500 ; gain = 0.000 ; free physical = 1855 ; free virtual = 20012
Ending Netlist Obfuscation Task | Checksum: 1d03688b4

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4700.500 ; gain = 0.000 ; free physical = 1855 ; free virtual = 20012
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:04:53 ; elapsed = 00:07:31 . Memory (MB): peak = 4700.500 ; gain = 1401.930 ; free physical = 1855 ; free virtual = 20012
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-35] Done setting XDC timing constraints.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4700.500 ; gain = 0.000 ; free physical = 1574 ; free virtual = 19730
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.18 . Memory (MB): peak = 4700.500 ; gain = 0.000 ; free physical = 1368 ; free virtual = 19714
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 4700.504 ; gain = 0.004 ; free physical = 1540 ; free virtual = 19716
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
Command: report_drc -file top_FTM_DSS_drc_opted.rpt -pb top_FTM_DSS_drc_opted.pb -rpx top_FTM_DSS_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1534 ; free virtual = 19710
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1531 ; free virtual = 19707
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15f34e0d6

Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1531 ; free virtual = 19707
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1531 ; free virtual = 19707

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 239d725a

Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1514 ; free virtual = 19691

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 161e42096

Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1466 ; free virtual = 19642

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 161e42096

Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1465 ; free virtual = 19641
Phase 1 Placer Initialization | Checksum: 161e42096

Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1461 ; free virtual = 19637

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 16ef6ba66

Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1439 ; free virtual = 19615

Phase 2.2 Global Placement Core

Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-1018] Found 1017 candidate LUT instances to create LUTNM shape
INFO: [Physopt 32-775] End 1 Pass. Optimized 420 nets or cells. Created 13 new cells, deleted 407 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1427 ; free virtual = 19603

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |           13  |            407  |                   420  |           0  |           1  |  00:00:02  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:01  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |           13  |            407  |                   420  |           0  |           7  |  00:00:03  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2.1 Physical Synthesis In Placer | Checksum: 24bb3fff1

Time (s): cpu = 00:02:34 ; elapsed = 00:02:39 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1426 ; free virtual = 19603
Phase 2.2 Global Placement Core | Checksum: 1177606e3

Time (s): cpu = 00:02:39 ; elapsed = 00:02:45 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1420 ; free virtual = 19596
Phase 2 Global Placement | Checksum: 1177606e3

Time (s): cpu = 00:02:40 ; elapsed = 00:02:45 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1443 ; free virtual = 19619

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1a4071cce

Time (s): cpu = 00:02:49 ; elapsed = 00:02:55 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1434 ; free virtual = 19610

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 175246446

Time (s): cpu = 00:03:06 ; elapsed = 00:03:12 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1429 ; free virtual = 19605

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1e2abb723

Time (s): cpu = 00:03:07 ; elapsed = 00:03:14 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1429 ; free virtual = 19605

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1b61352e9

Time (s): cpu = 00:03:08 ; elapsed = 00:03:14 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1428 ; free virtual = 19604

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 1a203d0f1

Time (s): cpu = 00:03:24 ; elapsed = 00:03:31 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1431 ; free virtual = 19607

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: b39ef16f

Time (s): cpu = 00:03:45 ; elapsed = 00:03:52 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1385 ; free virtual = 19561

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 14abe0f8e

Time (s): cpu = 00:03:49 ; elapsed = 00:03:56 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1387 ; free virtual = 19563

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 19b5bb9e9

Time (s): cpu = 00:03:50 ; elapsed = 00:03:57 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1386 ; free virtual = 19563

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 24478d940

Time (s): cpu = 00:04:12 ; elapsed = 00:04:20 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1381 ; free virtual = 19558
Phase 3 Detail Placement | Checksum: 24478d940

Time (s): cpu = 00:04:13 ; elapsed = 00:04:21 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1381 ; free virtual = 19558

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 24ea88010

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 24ea88010

Time (s): cpu = 00:04:47 ; elapsed = 00:04:56 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1181 ; free virtual = 19357
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.023. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 17c174cb4

Time (s): cpu = 00:05:43 ; elapsed = 00:05:52 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1194 ; free virtual = 19370
Phase 4.1 Post Commit Optimization | Checksum: 17c174cb4

Time (s): cpu = 00:05:44 ; elapsed = 00:05:53 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1194 ; free virtual = 19371

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 17c174cb4

Time (s): cpu = 00:05:45 ; elapsed = 00:05:54 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1203 ; free virtual = 19379

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 17c174cb4

Time (s): cpu = 00:05:46 ; elapsed = 00:05:55 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1204 ; free virtual = 19380

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1204 ; free virtual = 19380
Phase 4.4 Final Placement Cleanup | Checksum: c49b05bd

Time (s): cpu = 00:05:46 ; elapsed = 00:05:56 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1204 ; free virtual = 19380
Phase 4 Post Placement Optimization and Clean-Up | Checksum: c49b05bd

Time (s): cpu = 00:05:47 ; elapsed = 00:05:56 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1203 ; free virtual = 19380
Ending Placer Task | Checksum: 58198fab

Time (s): cpu = 00:05:47 ; elapsed = 00:05:56 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1203 ; free virtual = 19380
INFO: [Common 17-83] Releasing license: Implementation
85 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:05:53 ; elapsed = 00:06:03 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1260 ; free virtual = 19436
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1260 ; free virtual = 19436
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 993 ; free virtual = 19420
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1222 ; free virtual = 19424
INFO: [runtcl-4] Executing : report_io -file top_FTM_DSS_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.58 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1194 ; free virtual = 19396
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed.rpt -pb top_FTM_DSS_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_DSS_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.43 . Memory (MB): peak = 4700.504 ; gain = 0.000 ; free physical = 1218 ; free virtual = 19421
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_DSS_utilization_placed_1.rpt -pb top_FTM_DSS_utilization_placed_1.pb
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2020.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: 26bbb930 ConstDB: 0 ShapeSum: 315dd67b RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 10b1bfee4

Time (s): cpu = 00:01:28 ; elapsed = 00:01:29 . Memory (MB): peak = 4733.570 ; gain = 33.066 ; free physical = 880 ; free virtual = 19082
Post Restoration Checksum: NetGraph: 4c66a35f NumContArr: beb55b85 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 10b1bfee4

Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4762.785 ; gain = 62.281 ; free physical = 856 ; free virtual = 19058

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 10b1bfee4

Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4770.004 ; gain = 69.500 ; free physical = 843 ; free virtual = 19046

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 10b1bfee4

Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 4770.008 ; gain = 69.504 ; free physical = 843 ; free virtual = 19046
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 256249e4e

Time (s): cpu = 00:02:21 ; elapsed = 00:02:24 . Memory (MB): peak = 4872.562 ; gain = 172.059 ; free physical = 790 ; free virtual = 18993
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.063 | TNS=-0.102 | WHS=-0.515 | THS=-2300.176|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 1c8e47d7c

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 4872.562 ; gain = 172.059 ; free physical = 778 ; free virtual = 18980
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.063 | TNS=-0.023 | WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 1fe3d3be5

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 4888.562 ; gain = 188.059 ; free physical = 777 ; free virtual = 18979
Phase 2 Router Initialization | Checksum: 20ff3e38b

Time (s): cpu = 00:02:40 ; elapsed = 00:02:43 . Memory (MB): peak = 4888.562 ; gain = 188.059 ; free physical = 777 ; free virtual = 18979

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00346423 %
  Global Horizontal Routing Utilization  = 0.0015827 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 49192
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 49191
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1dae5eefd

Time (s): cpu = 00:07:10 ; elapsed = 00:07:17 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 754 ; free virtual = 18957
INFO: [Route 35-580] Design has 8 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
|       Launch Clock       |      Capture Clock       |                                                 Pin                                                      |
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
| mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_117_119/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt4_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                     regtxdata[18].mgt_source_data_regd_reg[18][ctrl][0]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[47].mgt_source_data_regd_reg[47][data][18]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[47].mgt_source_data_regd_reg[47][data][22]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[46].mgt_source_data_regd_reg[46][data][29]/D|
| mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |mgts_217_219/DSS_3Quads_11g2_support_i/DSS_3Quads_11g2_init_i/U0/DSS_3Quads_11g2_i/gt8_DSS_3Quads_11g2_i/gthe2_i/TXOUTCLK |                                                    regtxdata[47].mgt_source_data_regd_reg[47][data][20]/D|
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 5398
 Number of Nodes with overlaps = 787
 Number of Nodes with overlaps = 177
 Number of Nodes with overlaps = 48
 Number of Nodes with overlaps = 18
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.049  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: be34ebf0

Time (s): cpu = 00:09:22 ; elapsed = 00:09:32 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 764 ; free virtual = 18967
Phase 4 Rip-up And Reroute | Checksum: be34ebf0

Time (s): cpu = 00:09:22 ; elapsed = 00:09:32 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 764 ; free virtual = 18967

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: be34ebf0

Time (s): cpu = 00:09:22 ; elapsed = 00:09:33 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 764 ; free virtual = 18967

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: be34ebf0

Time (s): cpu = 00:09:23 ; elapsed = 00:09:33 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 764 ; free virtual = 18967
Phase 5 Delay and Skew Optimization | Checksum: be34ebf0

Time (s): cpu = 00:09:23 ; elapsed = 00:09:34 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 764 ; free virtual = 18967

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: ecd98e9b

Time (s): cpu = 00:09:32 ; elapsed = 00:09:42 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 765 ; free virtual = 18967
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.148  | TNS=0.000  | WHS=0.026  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 648f066d

Time (s): cpu = 00:09:32 ; elapsed = 00:09:43 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 764 ; free virtual = 18967
Phase 6 Post Hold Fix | Checksum: 648f066d

Time (s): cpu = 00:09:33 ; elapsed = 00:09:43 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 765 ; free virtual = 18967

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 5.01702 %
  Global Horizontal Routing Utilization  = 7.41681 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 1217b2445

Time (s): cpu = 00:09:34 ; elapsed = 00:09:44 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 763 ; free virtual = 18965

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1217b2445

Time (s): cpu = 00:09:34 ; elapsed = 00:09:45 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 761 ; free virtual = 18964

Phase 9 Depositing Routes
INFO: [Route 35-467] Router swapped GT pin mgts_217_219/DSS_3Quads_11g2_support_i/common2_i/gthe2_common_i/GTREFCLK1 to physical pin GTHE2_COMMON_X0Y5/GTNORTHREFCLK1
Phase 9 Depositing Routes | Checksum: 1999205b2

Time (s): cpu = 00:09:40 ; elapsed = 00:09:51 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 758 ; free virtual = 18960

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.148  | TNS=0.000  | WHS=0.026  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1999205b2

Time (s): cpu = 00:09:41 ; elapsed = 00:09:52 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 763 ; free virtual = 18966
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:09:41 ; elapsed = 00:09:52 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 819 ; free virtual = 19022

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
106 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:09:52 ; elapsed = 00:10:03 . Memory (MB): peak = 4919.562 ; gain = 219.059 ; free physical = 819 ; free virtual = 19022
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_DSS was modified...
INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean.
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:Msg-0] Found last SHA for FTM_DSS: 5dd1f64
INFO: [Hog:Msg-0] The git SHA value 5dd1f64 will be set as bitstream USERID.
INFO: [Hog:Msg-0] All done.
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4919.562 ; gain = 0.000 ; free physical = 820 ; free virtual = 19023
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4919.562 ; gain = 0.000 ; free physical = 537 ; free virtual = 19012
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 4919.566 ; gain = 0.004 ; free physical = 783 ; free virtual = 19017
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
Command: report_drc -file top_FTM_DSS_drc_routed.rpt -pb top_FTM_DSS_drc_routed.pb -rpx top_FTM_DSS_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 4919.566 ; gain = 0.000 ; free physical = 765 ; free virtual = 18999
INFO: [runtcl-4] Executing : report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
Command: report_methodology -file top_FTM_DSS_methodology_drc_routed.rpt -pb top_FTM_DSS_methodology_drc_routed.pb -rpx top_FTM_DSS_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:54 ; elapsed = 00:00:56 . Memory (MB): peak = 5125.562 ; gain = 205.996 ; free physical = 603 ; free virtual = 18838
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
Command: report_power -file top_FTM_DSS_power_routed.rpt -pb top_FTM_DSS_power_summary_routed.pb -rpx top_FTM_DSS_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
126 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 5175.570 ; gain = 50.008 ; free physical = 388 ; free virtual = 18636
INFO: [runtcl-4] Executing : report_route_status -file top_FTM_DSS_route_status.rpt -pb top_FTM_DSS_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_DSS_timing_summary_routed.rpt -pb top_FTM_DSS_timing_summary_routed.pb -rpx top_FTM_DSS_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5195.570 ; gain = 20.000 ; free physical = 357 ; free virtual = 18613
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_DSS_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_DSS_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_DSS_bus_skew_routed.rpt -pb top_FTM_DSS_bus_skew_routed.pb -rpx top_FTM_DSS_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
Command: report_drc -file top_FTM_DSS_drc_routed_1.rpt -pb top_FTM_DSS_drc_routed_1.pb -rpx top_FTM_DSS_drc_routed_1.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS_drc_routed_1.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 5297.297 ; gain = 101.727 ; free physical = 339 ; free virtual = 18595
INFO: [runtcl-4] Executing : report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Command: report_power -file top_FTM_DSS_power_routed_1.rpt -pb top_FTM_DSS_power_summary_routed_1.pb -rpx top_FTM_DSS_power_routed_1.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
138 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 5297.297 ; gain = 0.000 ; free physical = 332 ; free virtual = 18601
INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_DSS_timing_summary_routed_1.rpt -pb top_FTM_DSS_timing_summary_routed_1.pb -rpx top_FTM_DSS_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5297.297 ; gain = 0.000 ; free physical = 327 ; free virtual = 18597
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
INFO: [Common 17-206] Exiting Vivado at Wed Jun  8 14:11:41 2022...

*** Running vivado
    with args -log top_FTM_DSS.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_DSS.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_DSS.tcl -notrace
Command: open_checkpoint top_FTM_DSS_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1595.273 ; gain = 0.000 ; free physical = 3891 ; free virtual = 22158
INFO: [Device 21-403] Loading part xc7vx415tffg1158-2
Netlist sorting complete. Time (s): cpu = 00:00:00.80 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2072.992 ; gain = 0.000 ; free physical = 3285 ; free virtual = 21552
INFO: [Netlist 29-17] Analyzing 3350 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3137.105 ; gain = 65.133 ; free physical = 2270 ; free virtual = 20538
Restored from archive | CPU: 6.410000 secs | Memory: 76.612846 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3137.105 ; gain = 65.133 ; free physical = 2270 ; free virtual = 20538
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3137.105 ; gain = 0.000 ; free physical = 2276 ; free virtual = 20543
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 40 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 32 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 6 instances
  SRLC32E => SRL16E: 2 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876
open_checkpoint: Time (s): cpu = 00:01:16 ; elapsed = 00:02:24 . Memory (MB): peak = 3137.105 ; gain = 1541.836 ; free physical = 2276 ; free virtual = 20543
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: write_bitstream -force top_FTM_DSS.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx415t'
INFO: [Common 17-1540] The version limit for your license is '2021.04' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [DRC RTSTAT-10] No routable loads: 25 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/s_bscan_tms, slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[13], slaves/buffer_control/bcr_delays/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_daddr_o[14]... and (the first 15 of 23 listed).
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 60877344 bits.
Writing bitstream ./top_FTM_DSS.bit...
Writing bitstream ./top_FTM_DSS.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Jun  8 14:18:15 2022. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
26 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:03:34 ; elapsed = 00:03:46 . Memory (MB): peak = 3814.414 ; gain = 677.309 ; free physical = 2161 ; free virtual = 20447
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating Git sha for FTM_DSS...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_DSS clean.
INFO: [Hog:Msg-0] Git describe set to: v3.3.0-8-g5dd1f64
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v3.3.0-8-g5dd1f64...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_DSS/FTM_DSS.runs/impl_1/top_FTM_DSS.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_DSS-v3.3.0-8-g5dd1f64/FTM_DSS-v3.3.0-8-g5dd1f64.bit...