*** Running vivado with args -log gtwizard_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source gtwizard_0.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source gtwizard_0.tcl -notrace Command: synth_design -top gtwizard_0 -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17763 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:17 . Memory (MB): peak = 2107.484 ; gain = 201.715 ; free physical = 276 ; free virtual = 18773 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'gtwizard_0' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.vhd:172] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer INFO: [Synth 8-3491] module 'gtwizard_0_init' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_init.vhd:75' bound to instance 'U0' of component 'gtwizard_0_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.vhd:296] INFO: [Synth 8-638] synthesizing module 'gtwizard_0_init' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_init.vhd:186] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string INFO: [Synth 8-3491] module 'gtwizard_0_multi_gt' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_multi_gt.vhd:73' bound to instance 'gtwizard_0_i' of component 'gtwizard_0_multi_gt' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_init.vhd:525] INFO: [Synth 8-638] synthesizing module 'gtwizard_0_multi_gt' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_multi_gt.vhd:183] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter RX_DFE_KL_CFG2_IN bound to: 32'b00110000000100010100100010101100 Parameter PMA_RSV_IN bound to: 32'b00000000000000011000010010000000 Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter RX_DFE_KL_CFG2_IN bound to: 806439084 - type: integer Parameter PMA_RSV_IN bound to: 99456 - type: integer Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter PCS_RSVD_ATTR_IN bound to: 48'b000000000000000000000000000000000000000000000000 INFO: [Synth 8-3491] module 'gtwizard_0_GT' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_gt.vhd:72' bound to instance 'gt0_gtwizard_0_i' of component 'gtwizard_0_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_multi_gt.vhd:342] INFO: [Synth 8-638] synthesizing module 'gtwizard_0_GT' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_gt.vhd:179] Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter RX_DFE_KL_CFG2_IN bound to: 806439084 - type: integer Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter PMA_RSV_IN bound to: 99456 - type: integer Parameter PCS_RSVD_ATTR_IN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string Parameter ALIGN_COMMA_ENABLE bound to: 10'b1111111111 Parameter ALIGN_COMMA_WORD bound to: 4 - type: integer Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer Parameter CLK_CORRECT_USE bound to: FALSE - type: string Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string Parameter CLK_COR_MAX_LAT bound to: 20 - type: integer Parameter CLK_COR_MIN_LAT bound to: 16 - type: integer Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer Parameter CLK_COR_SEQ_1_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0100000000 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 Parameter CLK_COR_SEQ_2_USE bound to: FALSE - type: string Parameter CLK_COR_SEQ_LEN bound to: 1 - type: integer Parameter CPLL_CFG bound to: 24'b101111000000011111011100 Parameter CPLL_FBDIV bound to: 4 - type: integer Parameter CPLL_FBDIV_45 bound to: 5 - type: integer Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string Parameter DEC_VALID_COMMA_ONLY bound to: TRUE - type: string Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 Parameter ES_CONTROL bound to: 6'b000000 Parameter ES_ERRDET_EN bound to: FALSE - type: string Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 Parameter ES_PMA_CFG bound to: 10'b0000000000 Parameter ES_PRESCALE bound to: 5'b00000 Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter ES_VERT_OFFSET bound to: 9'b000000000 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string Parameter GEARBOX_MODE bound to: 3'b000 Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 Parameter OUTREFCLK_SEL_INV bound to: 2'b11 Parameter PCS_PCIE_EN bound to: FALSE - type: string Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00111100 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 Parameter PMA_RSV bound to: 99456 - type: integer Parameter PMA_RSV2 bound to: 16'b0010000001010000 Parameter PMA_RSV3 bound to: 2'b00 Parameter PMA_RSV4 bound to: 32'b00000000000000000000000000000000 Parameter RXBUFRESET_TIME bound to: 5'b00001 Parameter RXBUF_ADDR_MODE bound to: FAST - type: string Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 Parameter RXBUF_EN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string Parameter RXBUF_THRESH_UNDFLW bound to: 4 - type: integer Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 Parameter RXCDR_CFG bound to: 72'b000000110000000000000000001000111111111100010000010000000000000000100000 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RXCDR_LOCK_CFG bound to: 6'b010101 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 Parameter RXDLY_CFG bound to: 16'b0000000000011111 Parameter RXDLY_LCFG bound to: 12'b000000110000 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter RXGEARBOX_EN bound to: FALSE - type: string Parameter RXISCANRESET_TIME bound to: 5'b00001 Parameter RXLPM_HF_CFG bound to: 14'b00000011110000 Parameter RXLPM_LF_CFG bound to: 14'b00000011110000 Parameter RXOOB_CFG bound to: 7'b0000110 Parameter RXOUT_DIV bound to: 1 - type: integer Parameter RXPCSRESET_TIME bound to: 5'b00001 Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter RXPH_CFG bound to: 24'b000000000000000000000000 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 Parameter RXPMARESET_TIME bound to: 5'b00011 Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer Parameter RXSLIDE_MODE bound to: PCS - type: string Parameter RX_BIAS_CFG bound to: 12'b000000000100 Parameter RX_BUFFER_CFG bound to: 6'b000000 Parameter RX_CLK25_DIV bound to: 7 - type: integer Parameter RX_CLKMUX_PD bound to: 1'b1 Parameter RX_CM_SEL bound to: 2'b11 Parameter RX_CM_TRIM bound to: 3'b010 Parameter RX_DATA_WIDTH bound to: 40 - type: integer Parameter RX_DDI_SEL bound to: 6'b000000 Parameter RX_DEBUG_CFG bound to: 12'b000000000000 Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string Parameter RX_DFE_GAIN_CFG bound to: 24'b000000100000111111101010 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 Parameter RX_DFE_H4_CFG bound to: 11'b00011110000 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 Parameter RX_DFE_KL_CFG bound to: 13'b0000011111110 Parameter RX_DFE_KL_CFG2 bound to: 806439084 - type: integer Parameter RX_DFE_LPM_CFG bound to: 16'b0000100100000100 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 Parameter RX_DFE_UT_CFG bound to: 17'b10001111000000000 Parameter RX_DFE_VP_CFG bound to: 17'b00011111100000011 Parameter RX_DFE_XYD_CFG bound to: 13'b0000000000000 Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string Parameter RX_INT_DATAWIDTH bound to: 1 - type: integer Parameter RX_OS_CFG bound to: 13'b0000010000000 Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer Parameter RX_XCLK_SEL bound to: RXUSR - type: string Parameter SAS_MAX_COM bound to: 64 - type: integer Parameter SAS_MIN_COM bound to: 36 - type: integer Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 Parameter SATA_BURST_VAL bound to: 3'b100 Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string Parameter SATA_EIDLE_VAL bound to: 3'b100 Parameter SATA_MAX_BURST bound to: 8 - type: integer Parameter SATA_MAX_INIT bound to: 21 - type: integer Parameter SATA_MAX_WAKE bound to: 7 - type: integer Parameter SATA_MIN_BURST bound to: 4 - type: integer Parameter SATA_MIN_INIT bound to: 12 - type: integer Parameter SATA_MIN_WAKE bound to: 4 - type: integer Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string Parameter SIM_VERSION bound to: 4.0 - type: string Parameter TERM_RCAL_CFG bound to: 5'b10000 Parameter TERM_RCAL_OVRD bound to: 1'b0 Parameter TRANS_TIME_RATE bound to: 8'b00001110 Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 Parameter TXBUF_EN bound to: TRUE - type: string Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string Parameter TXDLY_CFG bound to: 16'b0000000000011111 Parameter TXDLY_LCFG bound to: 12'b000000110000 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 Parameter TXGEARBOX_EN bound to: FALSE - type: string Parameter TXOUT_DIV bound to: 1 - type: integer Parameter TXPCSRESET_TIME bound to: 5'b00001 Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 Parameter TXPH_CFG bound to: 16'b0000011110000000 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 Parameter TXPMARESET_TIME bound to: 5'b00001 Parameter TX_CLK25_DIV bound to: 7 - type: integer Parameter TX_CLKMUX_PD bound to: 1'b1 Parameter TX_DATA_WIDTH bound to: 40 - type: integer Parameter TX_DEEMPH0 bound to: 5'b00000 Parameter TX_DEEMPH1 bound to: 5'b00000 Parameter TX_DRIVE_MODE bound to: DIRECT - type: string Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 Parameter TX_INT_DATAWIDTH bound to: 1 - type: integer Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string Parameter TX_MAINCURSOR_SEL bound to: 1'b0 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 Parameter TX_PREDRIVER_MODE bound to: 1'b0 Parameter TX_QPI_STATUS_EN bound to: 1'b0 Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 Parameter TX_RXDETECT_REF bound to: 3'b100 Parameter TX_XCLK_SEL bound to: TXOUT - type: string Parameter UCODEER_CLR bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'gtxe2_i' to cell 'GTXE2_CHANNEL' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_gt.vhd:224] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_GT' (1#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_gt.vhd:179] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_multi_gt' (2#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_multi_gt.vhd:183] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'gtwizard_0_TX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:74' bound to instance 'gt0_txresetfsm_i' of component 'gtwizard_0_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_init.vhd:654] INFO: [Synth 8-638] synthesizing module 'gtwizard_0_TX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:120] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_run_phase_alignment_int' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:279] INFO: [Synth 8-638] synthesizing module 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:97] Parameter INITIALISE bound to: 6'b000000 Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg1' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:130] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg2' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:140] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg3' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:150] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg4' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:160] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg5' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:170] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'data_sync_reg6' to cell 'FD' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:180] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_sync_block' (3#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:97] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_tx_fsm_reset_done_int' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:287] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_TXRESETDONE' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:304] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_time_out_wait_bypass' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:312] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_mmcm_lock_reclocked' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:320] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_CPLLLOCK' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:340] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_QPLLLOCK' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:348] WARNING: [Synth 8-6014] Unused sequential element cplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:335] WARNING: [Synth 8-6014] Unused sequential element qplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:336] WARNING: [Synth 8-6014] Unused sequential element cplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:361] WARNING: [Synth 8-6014] Unused sequential element qplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:376] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_TX_STARTUP_FSM' (4#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_tx_startup_fsm.vhd:120] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-3491] module 'gtwizard_0_RX_STARTUP_FSM' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:76' bound to instance 'gt0_rxresetfsm_i' of component 'gtwizard_0_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_init.vhd:695] INFO: [Synth 8-638] synthesizing module 'gtwizard_0_RX_STARTUP_FSM' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:131] Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer Parameter EQ_MODE bound to: LPM - type: string Parameter STABLE_CLOCK_PERIOD bound to: 8 - type: integer Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer Parameter TX_QPLL_USED bound to: 1 - type: bool Parameter RX_QPLL_USED bound to: 1 - type: bool Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:244] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_run_phase_alignment_int' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:375] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_rx_fsm_reset_done_int' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:388] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_RXRESETDONE' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:405] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_time_out_wait_bypass' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:413] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_mmcm_lock_reclocked' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:421] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_data_valid' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:429] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_CPLLLOCK' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:449] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_QPLLLOCK' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:457] WARNING: [Synth 8-6014] Unused sequential element time_out_500us_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:319] WARNING: [Synth 8-6014] Unused sequential element time_out_1us_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:320] WARNING: [Synth 8-6014] Unused sequential element cplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:444] WARNING: [Synth 8-6014] Unused sequential element qplllock_prev_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:445] WARNING: [Synth 8-6014] Unused sequential element cplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:471] WARNING: [Synth 8-6014] Unused sequential element qplllock_ris_edge_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:486] WARNING: [Synth 8-6014] Unused sequential element refclk_stable_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:535] WARNING: [Synth 8-6014] Unused sequential element refclk_stable_count_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:534] WARNING: [Synth 8-6014] Unused sequential element rx_fsm_reset_done_int_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:569] WARNING: [Synth 8-6014] Unused sequential element pll_reset_asserted_reg was removed. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:572] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_RX_STARTUP_FSM' (5#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:131] INFO: [Synth 8-3491] module 'gtwizard_0_AUTO_PHASE_ALIGN' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_auto_phase_align.vhd:80' bound to instance 'gt0_rx_auto_phase_align_i' of component 'gtwizard_0_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_init.vhd:774] INFO: [Synth 8-638] synthesizing module 'gtwizard_0_AUTO_PHASE_ALIGN' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_auto_phase_align.vhd:93] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_PHALIGNDONE' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_auto_phase_align.vhd:120] Parameter INITIALISE bound to: 6'b000000 INFO: [Synth 8-3491] module 'gtwizard_0_sync_block' declared at '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_sync_block.vhd:81' bound to instance 'sync_DLYSRESETDONE' of component 'gtwizard_0_sync_block' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_auto_phase_align.vhd:128] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_auto_phase_align.vhd:162] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_AUTO_PHASE_ALIGN' (6#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_auto_phase_align.vhd:93] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0_init' (7#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_init.vhd:186] INFO: [Synth 8-256] done synthesizing module 'gtwizard_0' (8#1) [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.vhd:172] WARNING: [Synth 8-3331] design gtwizard_0_RX_STARTUP_FSM has unconnected port QPLLREFCLKLOST WARNING: [Synth 8-3331] design gtwizard_0_RX_STARTUP_FSM has unconnected port CPLLREFCLKLOST WARNING: [Synth 8-3331] design gtwizard_0_TX_STARTUP_FSM has unconnected port CPLLREFCLKLOST WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_rxuserrdy_in WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_gtrxreset_in WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_gttxreset_in WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_txuserrdy_in --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2172.207 ; gain = 266.438 ; free physical = 250 ; free virtual = 18750 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:22 . Memory (MB): peak = 2172.207 ; gain = 266.438 ; free physical = 245 ; free virtual = 18745 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:22 . Memory (MB): peak = 2172.207 ; gain = 266.438 ; free physical = 245 ; free virtual = 18745 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2182.109 ; gain = 0.000 ; free physical = 240 ; free virtual = 18740 INFO: [Netlist 29-17] Analyzing 102 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0_ooc.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xdc] for cell 'U0' Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xdc] for cell 'U0' Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/gtwizard_0_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/gtwizard_0_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.906 ; gain = 0.000 ; free physical = 143 ; free virtual = 18653 INFO: [Project 1-111] Unisim Transformation Summary: A total of 102 instances were transformed. FD => FDRE: 102 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2307.906 ; gain = 0.000 ; free physical = 143 ; free virtual = 18653 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2307.906 ; gain = 402.137 ; free physical = 215 ; free virtual = 18725 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2307.906 ; gain = 402.137 ; free physical = 215 ; free virtual = 18725 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/gtwizard_0_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:38 . Memory (MB): peak = 2307.906 ; gain = 402.137 ; free physical = 215 ; free virtual = 18725 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'tx_state_reg' in module 'gtwizard_0_TX_STARTUP_FSM' INFO: [Synth 8-5544] ROM "TXUSERRDY" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "gttxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "MMCM_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "tx_fsm_reset_done_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "QPLL_RESET" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-4471] merging register 'CPLL_RESET_reg' into 'QPLL_RESET_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:571] INFO: [Synth 8-4471] merging register 'recclk_mon_count_reset_reg' into 'adapt_count_reset_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:297] INFO: [Synth 8-4471] merging register 'RXDFELFHOLD_reg' into 'RXDFEAGCHOLD_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:581] INFO: [Synth 8-4471] merging register 'RXLPMLFHOLD_reg' into 'RXDFEAGCHOLD_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:582] INFO: [Synth 8-4471] merging register 'RXLPMHFHOLD_reg' into 'RXDFEAGCHOLD_reg' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0/example_design/gtwizard_0_rx_startup_fsm.vhd:583] INFO: [Synth 8-802] inferred FSM for state register 'rx_state_reg' in module 'gtwizard_0_RX_STARTUP_FSM' INFO: [Synth 8-5544] ROM "gtrxreset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "mmcm_reset_i" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "run_phase_alignment_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-802] inferred FSM for state register 'phalign_state_reg' in module 'gtwizard_0_AUTO_PHASE_ALIGN' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 assert_all_resets | 0001 | 0001 wait_for_pll_lock | 0010 | 0010 release_pll_reset | 0011 | 0011 wait_for_txoutclk | 0100 | 0100 release_mmcm_reset | 0101 | 0101 wait_for_txusrclk | 0110 | 0110 wait_reset_done | 0111 | 0111 do_phase_alignment | 1000 | 1000 reset_fsm_done | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_state_reg' using encoding 'sequential' in module 'gtwizard_0_TX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 assert_all_resets | 0001 | 0001 wait_for_pll_lock | 0010 | 0010 release_pll_reset | 0011 | 0011 verify_recclk_stable | 0100 | 0100 release_mmcm_reset | 0101 | 0101 wait_for_rxusrclk | 0110 | 0110 wait_reset_done | 0111 | 0111 do_phase_alignment | 1000 | 1000 monitor_data_valid | 1001 | 1001 fsm_done | 1010 | 1010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'rx_state_reg' using encoding 'sequential' in module 'gtwizard_0_RX_STARTUP_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0001 | 00 wait_phrst_done | 0010 | 01 count_phalign_done | 0100 | 10 phalign_done | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'phalign_state_reg' using encoding 'one-hot' in module 'gtwizard_0_AUTO_PHASE_ALIGN' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:39 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 206 ; free virtual = 18717 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 4 2 Input 7 Bit Adders := 4 2 Input 2 Bit Adders := 2 +---Registers : 8 Bit Registers := 4 7 Bit Registers := 4 2 Bit Registers := 2 1 Bit Registers := 47 +---Muxes : 2 Input 8 Bit Muxes := 2 10 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 10 11 Input 4 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 23 10 Input 1 Bit Muxes := 17 11 Input 1 Bit Muxes := 17 4 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module gtwizard_0_TX_STARTUP_FSM Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 2 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 2 1 Bit Registers := 21 +---Muxes : 2 Input 8 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 4 2 Input 1 Bit Muxes := 10 10 Input 1 Bit Muxes := 17 Module gtwizard_0_RX_STARTUP_FSM Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 2 2 Input 2 Bit Adders := 1 +---Registers : 8 Bit Registers := 2 7 Bit Registers := 2 2 Bit Registers := 1 1 Bit Registers := 22 +---Muxes : 2 Input 8 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 6 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 12 11 Input 1 Bit Muxes := 17 Module gtwizard_0_AUTO_PHASE_ALIGN Detailed RTL Component Info : +---Adders : 2 Input 2 Bit Adders := 1 +---Registers : 2 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 2 Module gtwizard_0_init Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_rxuserrdy_in WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_gtrxreset_in WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_gttxreset_in WARNING: [Synth 8-3331] design gtwizard_0_init has unconnected port gt0_txuserrdy_in INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\gt0_rxresetfsm_i/recclk_mon_restart_count_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\gt0_rxresetfsm_i/recclk_mon_restart_count_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\gt0_rxresetfsm_i/RXDFEAGCHOLD_reg ) INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_CPLLLOCK/data_sync_reg1) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_CPLLLOCK/data_sync_reg2) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_CPLLLOCK/data_sync_reg3) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_CPLLLOCK/data_sync_reg4) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_CPLLLOCK/data_sync_reg5) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_txresetfsm_i/sync_CPLLLOCK/data_sync_reg6) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg1) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg2) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg3) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg4) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg5) is unused and will be removed from module gtwizard_0_init. INFO: [Synth 8-3332] Sequential element (gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg6) is unused and will be removed from module gtwizard_0_init. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:42 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 191 ; free virtual = 18705 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:59 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 132 ; free virtual = 18525 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:01:00 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 166 ; free virtual = 18519 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:01:00 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 164 ; free virtual = 18517 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 156 ; free virtual = 18508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 156 ; free virtual = 18508 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 156 ; free virtual = 18508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 156 ; free virtual = 18508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 156 ; free virtual = 18508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 156 ; free virtual = 18508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------------+------+ | |Cell |Count | +------+--------------+------+ |1 |CARRY4 | 29| |2 |GTXE2_CHANNEL | 1| |3 |LUT1 | 17| |4 |LUT2 | 29| |5 |LUT3 | 23| |6 |LUT4 | 50| |7 |LUT5 | 45| |8 |LUT6 | 40| |9 |FD | 90| |10 |FDCE | 16| |11 |FDRE | 168| |12 |FDSE | 8| +------+--------------+------+ Report Instance Areas: +------+-----------------------------------+----------------------------+------+ | |Instance |Module |Cells | +------+-----------------------------------+----------------------------+------+ |1 |top | | 516| |2 | U0 |gtwizard_0_init | 516| |3 | gt0_rx_auto_phase_align_i |gtwizard_0_AUTO_PHASE_ALIGN | 26| |4 | sync_DLYSRESETDONE |gtwizard_0_sync_block_12 | 6| |5 | sync_PHALIGNDONE |gtwizard_0_sync_block_13 | 6| |6 | gt0_rxresetfsm_i |gtwizard_0_RX_STARTUP_FSM | 228| |7 | sync_QPLLLOCK |gtwizard_0_sync_block_5 | 7| |8 | sync_RXRESETDONE |gtwizard_0_sync_block_6 | 6| |9 | sync_data_valid |gtwizard_0_sync_block_7 | 18| |10 | sync_mmcm_lock_reclocked |gtwizard_0_sync_block_8 | 8| |11 | sync_run_phase_alignment_int |gtwizard_0_sync_block_9 | 6| |12 | sync_rx_fsm_reset_done_int |gtwizard_0_sync_block_10 | 6| |13 | sync_time_out_wait_bypass |gtwizard_0_sync_block_11 | 6| |14 | gt0_txresetfsm_i |gtwizard_0_TX_STARTUP_FSM | 240| |15 | sync_QPLLLOCK |gtwizard_0_sync_block | 11| |16 | sync_TXRESETDONE |gtwizard_0_sync_block_0 | 6| |17 | sync_mmcm_lock_reclocked |gtwizard_0_sync_block_1 | 8| |18 | sync_run_phase_alignment_int |gtwizard_0_sync_block_2 | 6| |19 | sync_time_out_wait_bypass |gtwizard_0_sync_block_3 | 6| |20 | sync_tx_fsm_reset_done_int |gtwizard_0_sync_block_4 | 6| |21 | gtwizard_0_i |gtwizard_0_multi_gt | 1| |22 | gt0_gtwizard_0_i |gtwizard_0_GT | 1| +------+-----------------------------------+----------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 156 ; free virtual = 18508 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 4 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:59 . Memory (MB): peak = 2307.910 ; gain = 266.441 ; free physical = 208 ; free virtual = 18561 Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:01:04 . Memory (MB): peak = 2307.910 ; gain = 402.141 ; free physical = 208 ; free virtual = 18561 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2307.910 ; gain = 0.000 ; free physical = 273 ; free virtual = 18628 INFO: [Netlist 29-17] Analyzing 119 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.910 ; gain = 0.000 ; free physical = 202 ; free virtual = 18567 INFO: [Project 1-111] Unisim Transformation Summary: A total of 90 instances were transformed. FD => FDRE: 90 instances INFO: [Common 17-83] Releasing license: Synthesis 96 Infos, 25 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:47 ; elapsed = 00:01:25 . Memory (MB): peak = 2307.910 ; gain = 686.246 ; free physical = 330 ; free virtual = 18700 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.910 ; gain = 0.000 ; free physical = 328 ; free virtual = 18700 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/gtwizard_0_synth_1/gtwizard_0.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP gtwizard_0, cache-ID = a9622c4148eceb8e INFO: [Coretcl 2-1174] Renamed 21 cell refs. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2331.922 ; gain = 0.000 ; free physical = 317 ; free virtual = 18699 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/gtwizard_0_synth_1/gtwizard_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file gtwizard_0_utilization_synth.rpt -pb gtwizard_0_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Wed Jun 29 23:55:14 2022...