*** Running vivado
    with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_Control.tcl -notrace
Command: link_design -top top_FTM_Control -part xc7k325tffg900-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_tx.dcp' for cell 'pll_sync_reset'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/temac_gbe_v9_0_gmii.dcp' for cell 'eth/emac0'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_rx.dcp' for cell 'mgt_ttcinfo/rx_data'
INFO: [Project 1-454] Reading design checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.dcp' for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i'
Netlist sorting complete. Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2020.582 ; gain = 0.000 ; free physical = 3358 ; free virtual = 21581
INFO: [Netlist 29-17] Analyzing 1398 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: mgt_ttcinfo/rx_data UUID: 2e216d50-fdcc-5e22-b690-e434f5351049 
INFO: [Chipscope 16-324] Core: mgt_ttcinfo/tx_data UUID: 5b89df68-5880-5164-8735-ef82a233b4c0 
INFO: [Chipscope 16-324] Core: pll_sync_reset UUID: 93b37abd-9bf1-5b91-b254-f9275f803806 
INFO: [Chipscope 16-324] Core: slaves/ttc_info/ttcin/ttc_sink UUID: 40ec53cc-f74b-5d06-9bbf-5235d0ce3e6b 
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_rx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/rx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xdc] for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xdc] for cell 'mgt_ttcinfo/gtwizard_0_support_i/gtwizard_0_init_i/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'pll_sync_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'pll_sync_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila_impl.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'mgt_ttcinfo/tx_data/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'pll_sync_reset/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'pll_sync_reset/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/ila_tx/ila_v6_2/constraints/ila.xdc] for cell 'slaves/ttc_info/ttcin/ttc_sink/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_board.xdc] for cell 'eth/emac0/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii.xdc] for cell 'eth/emac0/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control_pinout.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4]
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:4]
get_clocks: Time (s): cpu = 00:00:15 ; elapsed = 00:00:26 . Memory (MB): peak = 2736.824 ; gain = 556.016 ; free physical = 2757 ; free virtual = 20996
INFO: [Timing 38-2] Deriving generated clocks [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc:48]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/spi_timing.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/FTM_Control.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/ttcinfo_mgt.xdc]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control/xdc/ttcinfo_mgt.xdc]
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0'
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0'
Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0'
INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:40]
INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc:41]
Finished Parsing XDC File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_clocks.xdc] for cell 'eth/emac0/U0'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr'
Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2767.895 ; gain = 0.000 ; free physical = 2770 ; free virtual = 21009
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 272 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 212 instances
  IOBUF => IOBUF (IBUF, OBUFT): 4 instances
  OBUFDS => OBUFDS: 26 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances

21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:39 ; elapsed = 00:01:07 . Memory (MB): peak = 2767.895 ; gain = 1107.121 ; free physical = 2770 ; free virtual = 21009
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
Parsing TCL File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/tcl/v7ht.tcl] from IP /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/gtwizard_0.xci
Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/tcl/v7ht.tcl]

****************************************************************************************
*  WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices.  *
*           Your current part is xc7k325t.                                            *
****************************************************************************************

Finished Sourcing Tcl File [/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/IP/gtwizard_0/tcl/v7ht.tcl]
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:01 . Memory (MB): peak = 2775.898 ; gain = 8.000 ; free physical = 2765 ; free virtual = 21006

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 19ca215c5

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2775.898 ; gain = 0.000 ; free physical = 2736 ; free virtual = 20979

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2903.766 ; gain = 0.000 ; free physical = 2537 ; free virtual = 20807
Phase 1 Generate And Synthesize Debug Cores | Checksum: 166d1448e

Time (s): cpu = 00:01:55 ; elapsed = 00:03:47 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2537 ; free virtual = 20807

Phase 2 Retarget
INFO: [Opt 31-138] Pushed 3 inverter(s) to 6 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 2 Retarget | Checksum: 2427f78b7

Time (s): cpu = 00:01:57 ; elapsed = 00:03:49 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2563 ; free virtual = 20833
INFO: [Opt 31-389] Phase Retarget created 19 cells and removed 61 cells
INFO: [Opt 31-1021] In phase Retarget, 170 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 3 Constant propagation
INFO: [Opt 31-138] Pushed 1 inverter(s) to 11 load pin(s).
Phase 3 Constant propagation | Checksum: 1b438dc69

Time (s): cpu = 00:01:58 ; elapsed = 00:03:50 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2563 ; free virtual = 20833
INFO: [Opt 31-389] Phase Constant propagation created 115 cells and removed 1122 cells
INFO: [Opt 31-1021] In phase Constant propagation, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Sweep
Phase 4 Sweep | Checksum: 18020dc7e

Time (s): cpu = 00:01:59 ; elapsed = 00:03:51 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2561 ; free virtual = 20832
INFO: [Opt 31-389] Phase Sweep created 5 cells and removed 388 cells
INFO: [Opt 31-1021] In phase Sweep, 2233 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 5 BUFG optimization
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
Phase 5 BUFG optimization | Checksum: 18020dc7e

Time (s): cpu = 00:02:00 ; elapsed = 00:03:52 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2558 ; free virtual = 20832
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 6 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 6 Shift Register Optimization | Checksum: 18421592d

Time (s): cpu = 00:02:00 ; elapsed = 00:03:52 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2558 ; free virtual = 20832
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 7 Post Processing Netlist
Phase 7 Post Processing Netlist | Checksum: 12a242205

Time (s): cpu = 00:02:00 ; elapsed = 00:03:52 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2555 ; free virtual = 20833
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 112 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              19  |              61  |                                            170  |
|  Constant propagation         |             115  |            1122  |                                             99  |
|  Sweep                        |               5  |             388  |                                           2233  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                            112  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2903.766 ; gain = 0.000 ; free physical = 2555 ; free virtual = 20833
Ending Logic Optimization Task | Checksum: 1188c86e5

Time (s): cpu = 00:02:01 ; elapsed = 00:03:53 . Memory (MB): peak = 2903.766 ; gain = 33.871 ; free physical = 2555 ; free virtual = 20833

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.045 | TNS=0.000 |
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 26 BRAM(s) out of a total of 325 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 144 WE to EN ports
Number of BRAM Ports augmented: 52 newly gated: 152 Total Ports: 650
Ending PowerOpt Patch Enables Task | Checksum: 6f42a729

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3601.258 ; gain = 0.000 ; free physical = 2452 ; free virtual = 20740
Ending Power Optimization Task | Checksum: 6f42a729

Time (s): cpu = 00:01:30 ; elapsed = 00:01:32 . Memory (MB): peak = 3601.258 ; gain = 697.492 ; free physical = 2493 ; free virtual = 20781

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 1705c962c

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3601.258 ; gain = 0.000 ; free physical = 2492 ; free virtual = 20784
Ending Final Cleanup Task | Checksum: 1705c962c

Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 3601.258 ; gain = 0.000 ; free physical = 2492 ; free virtual = 20784

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3601.258 ; gain = 0.000 ; free physical = 2492 ; free virtual = 20784
Ending Netlist Obfuscation Task | Checksum: 1705c962c

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3601.258 ; gain = 0.000 ; free physical = 2492 ; free virtual = 20784
INFO: [Common 17-83] Releasing license: Implementation
60 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:03:51 ; elapsed = 00:05:50 . Memory (MB): peak = 3601.258 ; gain = 833.363 ; free physical = 2492 ; free virtual = 20784
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-35] Done setting XDC timing constraints.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3601.258 ; gain = 0.000 ; free physical = 2468 ; free virtual = 20760
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3601.258 ; gain = 0.000 ; free physical = 2452 ; free virtual = 20757
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_opt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 3601.262 ; gain = 0.004 ; free physical = 2456 ; free virtual = 20756
INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx
Command: report_drc -file top_FTM_Control_drc_opted.rpt -pb top_FTM_Control_drc_opted.pb -rpx top_FTM_Control_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2451 ; free virtual = 20752
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d2682299

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2451 ; free virtual = 20752
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2451 ; free virtual = 20752

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 49230be9

Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2435 ; free virtual = 20741

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: cdd19ba2

Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2389 ; free virtual = 20695

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: cdd19ba2

Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2389 ; free virtual = 20695
Phase 1 Placer Initialization | Checksum: cdd19ba2

Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2385 ; free virtual = 20693

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 151d15cb7

Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2370 ; free virtual = 20677

Phase 2.2 Global Placement Core

Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-1018] Found 653 candidate LUT instances to create LUTNM shape
INFO: [Physopt 32-775] End 1 Pass. Optimized 246 nets or cells. Created 1 new cell, deleted 245 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2355 ; free virtual = 20665

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            1  |            245  |                   246  |           0  |           1  |  00:00:01  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            1  |            245  |                   246  |           0  |           7  |  00:00:01  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2.1 Physical Synthesis In Placer | Checksum: 12e1e0223

Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20667
Phase 2.2 Global Placement Core | Checksum: 127a450a7

Time (s): cpu = 00:01:06 ; elapsed = 00:01:08 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2351 ; free virtual = 20661
Phase 2 Global Placement | Checksum: 127a450a7

Time (s): cpu = 00:01:06 ; elapsed = 00:01:08 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2364 ; free virtual = 20674

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: bce7476d

Time (s): cpu = 00:01:10 ; elapsed = 00:01:12 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2360 ; free virtual = 20670

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 180fe04d4

Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20667

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 171d780bf

Time (s): cpu = 00:01:17 ; elapsed = 00:01:20 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20667

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1991976e3

Time (s): cpu = 00:01:17 ; elapsed = 00:01:20 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2357 ; free virtual = 20667

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 1d7d989e2

Time (s): cpu = 00:01:24 ; elapsed = 00:01:26 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2355 ; free virtual = 20669

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 14e5b3f3b

Time (s): cpu = 00:01:33 ; elapsed = 00:01:36 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2331 ; free virtual = 20645

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1281815f4

Time (s): cpu = 00:01:34 ; elapsed = 00:01:37 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2332 ; free virtual = 20646

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1cb3584ad

Time (s): cpu = 00:01:35 ; elapsed = 00:01:38 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2332 ; free virtual = 20646

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 21090be91

Time (s): cpu = 00:01:45 ; elapsed = 00:01:48 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2330 ; free virtual = 20644
Phase 3 Detail Placement | Checksum: 21090be91

Time (s): cpu = 00:01:45 ; elapsed = 00:01:48 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2330 ; free virtual = 20644

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1dced76d5

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-33] Processed net clocks/rsto_ipb, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1dced76d5

Time (s): cpu = 00:01:58 ; elapsed = 00:02:01 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2331 ; free virtual = 20645
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.208. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 3af71757

Time (s): cpu = 00:02:13 ; elapsed = 00:02:16 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2336 ; free virtual = 20650
Phase 4.1 Post Commit Optimization | Checksum: 3af71757

Time (s): cpu = 00:02:13 ; elapsed = 00:02:16 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2336 ; free virtual = 20650

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 3af71757

Time (s): cpu = 00:02:14 ; elapsed = 00:02:17 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2343 ; free virtual = 20657

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 3af71757

Time (s): cpu = 00:02:14 ; elapsed = 00:02:17 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2343 ; free virtual = 20657

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2343 ; free virtual = 20657
Phase 4.4 Final Placement Cleanup | Checksum: 1240adba4

Time (s): cpu = 00:02:14 ; elapsed = 00:02:17 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2343 ; free virtual = 20657
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1240adba4

Time (s): cpu = 00:02:14 ; elapsed = 00:02:18 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2343 ; free virtual = 20657
Ending Placer Task | Checksum: 117076df8

Time (s): cpu = 00:02:14 ; elapsed = 00:02:18 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2343 ; free virtual = 20657
INFO: [Common 17-83] Releasing license: Implementation
91 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:02:17 ; elapsed = 00:02:21 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2376 ; free virtual = 20690
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2376 ; free virtual = 20690
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2334 ; free virtual = 20688
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2363 ; free virtual = 20688
INFO: [runtcl-4] Executing : report_io -file top_FTM_Control_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2339 ; free virtual = 20664
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed.rpt -pb top_FTM_Control_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_FTM_Control_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2359 ; free virtual = 20684
INFO: [runtcl-4] Executing : report_utilization -file top_FTM_Control_utilization_placed_1.rpt -pb top_FTM_Control_utilization_placed_1.pb
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: 22d0cbb2 ConstDB: 0 ShapeSum: f436a246 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 9a53be4e

Time (s): cpu = 00:00:56 ; elapsed = 00:00:57 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2082 ; free virtual = 20412
Post Restoration Checksum: NetGraph: 139f6e54 NumContArr: 86b44ffa Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 9a53be4e

Time (s): cpu = 00:00:56 ; elapsed = 00:00:57 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2052 ; free virtual = 20385

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 9a53be4e

Time (s): cpu = 00:00:57 ; elapsed = 00:00:57 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2042 ; free virtual = 20377

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 9a53be4e

Time (s): cpu = 00:00:57 ; elapsed = 00:00:57 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2042 ; free virtual = 20377
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 10f1f7380

Time (s): cpu = 00:01:19 ; elapsed = 00:01:20 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2010 ; free virtual = 20344
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.154 | TNS=-0.307 | WHS=-0.402 | THS=-712.479|


Phase 2.5 Update Timing for Bus Skew

Phase 2.5.1 Update Timing
Phase 2.5.1 Update Timing | Checksum: 10ef0c7b2

Time (s): cpu = 00:01:27 ; elapsed = 00:01:29 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2006 ; free virtual = 20340
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.154 | TNS=-0.303 | WHS=N/A    | THS=N/A    |

Phase 2.5 Update Timing for Bus Skew | Checksum: 118827dca

Time (s): cpu = 00:01:27 ; elapsed = 00:01:29 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2005 ; free virtual = 20339
Phase 2 Router Initialization | Checksum: 1f7827630

Time (s): cpu = 00:01:27 ; elapsed = 00:01:29 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2005 ; free virtual = 20339

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.000141874 %
  Global Horizontal Routing Utilization  = 0.000138953 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 22932
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 22930
  Number of Partially Routed Nets     = 2
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 9e4ff6c3

Time (s): cpu = 00:02:10 ; elapsed = 00:02:12 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1994 ; free virtual = 20328

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 2060
 Number of Nodes with overlaps = 160
 Number of Nodes with overlaps = 11
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.072  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 17111076f

Time (s): cpu = 00:02:34 ; elapsed = 00:02:38 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335
Phase 4 Rip-up And Reroute | Checksum: 17111076f

Time (s): cpu = 00:02:34 ; elapsed = 00:02:38 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 17111076f

Time (s): cpu = 00:02:35 ; elapsed = 00:02:38 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 17111076f

Time (s): cpu = 00:02:35 ; elapsed = 00:02:38 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335
Phase 5 Delay and Skew Optimization | Checksum: 17111076f

Time (s): cpu = 00:02:35 ; elapsed = 00:02:38 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1c3d2488c

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.072  | TNS=0.000  | WHS=0.052  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1af95bb77

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335
Phase 6 Post Hold Fix | Checksum: 1af95bb77

Time (s): cpu = 00:02:39 ; elapsed = 00:02:42 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2001 ; free virtual = 20335

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 2.27264 %
  Global Horizontal Routing Utilization  = 2.45459 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 124222835

Time (s): cpu = 00:02:40 ; elapsed = 00:02:43 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2000 ; free virtual = 20334

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 124222835

Time (s): cpu = 00:02:40 ; elapsed = 00:02:43 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1999 ; free virtual = 20333

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1a1622223

Time (s): cpu = 00:02:42 ; elapsed = 00:02:46 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1995 ; free virtual = 20330

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.072  | TNS=0.000  | WHS=0.052  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1a1622223

Time (s): cpu = 00:02:43 ; elapsed = 00:02:46 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1997 ; free virtual = 20331
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:02:43 ; elapsed = 00:02:46 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2030 ; free virtual = 20364

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
109 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:02:47 ; elapsed = 00:02:51 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2030 ; free virtual = 20364
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-implementation.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating last git SHA in which FTM_Control was modified...
INFO: [Hog:Msg-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware clean.
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains 135A77A, will use most recent tag v3.3.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:GetVerFromSHA-0] No tag contains 135A77A, will use most recent tag v3.3.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Found last SHA for FTM_Control: 135a77a
INFO: [Hog:Msg-0] The git SHA value 135a77a will be set as bitstream USERID.
INFO: [Hog:Msg-0] All done.
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2032 ; free virtual = 20366
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1981 ; free virtual = 20365
INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2017 ; free virtual = 20365
INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx
Command: report_drc -file top_FTM_Control_drc_routed.rpt -pb top_FTM_Control_drc_routed.pb -rpx top_FTM_Control_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 2008 ; free virtual = 20355
INFO: [runtcl-4] Executing : report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx
Command: report_methodology -file top_FTM_Control_methodology_drc_routed.rpt -pb top_FTM_Control_methodology_drc_routed.pb -rpx top_FTM_Control_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1998 ; free virtual = 20346
INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx
Command: report_power -file top_FTM_Control_power_routed.rpt -pb top_FTM_Control_power_summary_routed.pb -rpx top_FTM_Control_power_routed.rpx
INFO: [Power 33-23] Power model is not available for STARTUPE2_inst
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
131 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1950 ; free virtual = 20308
INFO: [runtcl-4] Executing : report_route_status -file top_FTM_Control_route_status.rpt -pb top_FTM_Control_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_FTM_Control_timing_summary_routed.rpt -pb top_FTM_Control_timing_summary_routed.pb -rpx top_FTM_Control_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
INFO: [runtcl-4] Executing : report_incremental_reuse -file top_FTM_Control_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file top_FTM_Control_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_FTM_Control_bus_skew_routed.rpt -pb top_FTM_Control_bus_skew_routed.pb -rpx top_FTM_Control_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx
Command: report_drc -file top_FTM_Control_drc_routed_1.rpt -pb top_FTM_Control_drc_routed_1.pb -rpx top_FTM_Control_drc_routed_1.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control_drc_routed_1.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1923 ; free virtual = 20287
INFO: [runtcl-4] Executing : report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx
Command: report_power -file top_FTM_Control_power_routed_1.rpt -pb top_FTM_Control_power_summary_routed_1.pb -rpx top_FTM_Control_power_routed_1.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
143 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3601.262 ; gain = 0.000 ; free physical = 1913 ; free virtual = 20285
INFO: [runtcl-4] Executing : report_timing_summary -file top_FTM_Control_timing_summary_routed_1.rpt -pb top_FTM_Control_timing_summary_routed_1.pb -rpx top_FTM_Control_timing_summary_routed_1.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
INFO: [runtcl-4] Executing : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb
INFO: [Common 17-206] Exiting Vivado at Thu Jun 30 00:18:22 2022...

*** Running vivado
    with args -log top_FTM_Control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_FTM_Control.tcl -notrace


****** Vivado v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source top_FTM_Control.tcl -notrace
Command: open_checkpoint top_FTM_Control_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1552.035 ; gain = 0.000 ; free physical = 3723 ; free virtual = 22093
INFO: [Device 21-403] Loading part xc7k325tffg900-2
Netlist sorting complete. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1945.523 ; gain = 0.000 ; free physical = 3246 ; free virtual = 21616
INFO: [Netlist 29-17] Analyzing 1285 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings.  Mismatching parameters are:
  general.maxThreads
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2674.473 ; gain = 21.332 ; free physical = 2567 ; free virtual = 20937
Restored from archive | CPU: 2.980000 secs | Memory: 34.787186 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2674.473 ; gain = 21.332 ; free physical = 2567 ; free virtual = 20937
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2674.473 ; gain = 0.000 ; free physical = 2569 ; free virtual = 20939
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 254 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 212 instances
  IOBUF => IOBUF (IBUF, OBUFT): 4 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 8 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 20 instances
  RAM64X1D => RAM64X1D (RAMD64E(x2)): 8 instances
  SRLC32E => SRL16E: 2 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2019.2 (64-bit) build 2708876
open_checkpoint: Time (s): cpu = 00:00:36 ; elapsed = 00:01:10 . Memory (MB): peak = 2674.473 ; gain = 1122.441 ; free physical = 2569 ; free virtual = 20939
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/pre-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile
INFO: [Hog:Msg-0] All done
Command: write_bitstream -force top_FTM_Control.bit -bin_file
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more IP cores that use separately licensed features. If the design has been configured to make use of evaluation features, please note that these features will cease to function after a certain period of time. Please consult the core datasheet to determine whether the core which you have configured will be affected. Evaluation features should NOT be used in production systems.

Evaluation cores found in this design:
    IP core 'temac_gbe_v9_0_gmii' (temac_gbe_v9_0_gmii_block) was generated with multiple features:
        IP feature 'eth_avb_endpoint@2015.04' was enabled using a design_linking license.
        IP feature 'tri_mode_eth_mac@2015.04' was enabled using a bought license.

Resolution: If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [DRC RTSTAT-10] No routable loads: 101 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i, eth/fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rd_rst_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0]... and (the first 15 of 53 listed).
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 49355744 bits.
Writing bitstream ./top_FTM_Control.bit...
Writing bitstream ./top_FTM_Control.bin...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] '/home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Jun 30 00:21:51 2022. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
25 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:01:45 ; elapsed = 00:01:57 . Memory (MB): peak = 3233.051 ; gain = 558.578 ; free physical = 2477 ; free virtual = 20862
source /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog/Tcl/integrated/post-bitstream.tcl
INFO: [Hog:GitVersion-0] Found Git version: git version 2.22.0
INFO: [Hog:Msg-0] Evaluating Git sha for FTM_Control...
INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Hog clean.
INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Top/FTM_Control clean.
INFO: [Hog:GetVerFromSHA-0] No tag contains 135A77A, will use most recent tag v3.3.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:GetVerFromSHA-0] No tag contains 135A77A, will use most recent tag v3.3.2. As this is an official tag, patch will be incremented to 3.
INFO: [Hog:Msg-0] Git describe set to: v3.3.2-2-g135a77a
INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v3.3.2-2-g135a77a...
INFO: [Hog:Msg-0] Evaluating differences with last commit...
INFO: [Hog:Msg-0] No uncommitted changes found.
INFO: [Hog:Msg-0] Copying bit file /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/Projects/FTM_Control/FTM_Control.runs/impl_1/top_FTM_Control.bit into /home/gitlab-runner/builds/V78q8JmG/0/atlas-l1calo-efex/FTMFirmware/bin/FTM_Control-v3.3.2-2-g135a77a/FTM_Control-v3.3.2-2-g135a77a.bit...