------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 3.6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard -- / / Filename : mgt_combined_ttc_rx.vhd -- /___/ /\ -- \ \ / \ -- \___\/\___\ -- -- -- Module MGT_combined_ttc_rx (a Core Top) -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard -- -- -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VCOMPONENTS.ALL; --***************************** Entity Declaration **************************** entity MGT_combined_ttc_rx is port ( SYSCLK_IN : in std_logic; SOFT_RESET_RX_IN : in std_logic; DONT_RESET_ON_DATA_ERROR_IN : in std_logic; GT0_TX_FSM_RESET_DONE_OUT : out std_logic; GT0_RX_FSM_RESET_DONE_OUT : out std_logic; GT0_DATA_VALID_IN : in std_logic; --_________________________________________________________________________ --GT0 (X0Y38) --____________________________CHANNEL PORTS________________________________ --------------------------------- CPLL Ports ------------------------------- gt0_cpllfbclklost_out : out std_logic; gt0_cplllock_out : out std_logic; gt0_cplllockdetclk_in : in std_logic; gt0_cpllreset_in : in std_logic; -------------------------- Channel - Clocking Ports ------------------------ gt0_gtrefclk0_in : in std_logic; gt0_gtrefclk1_in : in std_logic; ---------------------------- Channel - DRP Ports -------------------------- gt0_drpaddr_in : in std_logic_vector(8 downto 0); gt0_drpclk_in : in std_logic; gt0_drpdi_in : in std_logic_vector(15 downto 0); gt0_drpdo_out : out std_logic_vector(15 downto 0); gt0_drpen_in : in std_logic; gt0_drprdy_out : out std_logic; gt0_drpwe_in : in std_logic; --------------------- RX Initialization and Reset Ports -------------------- gt0_eyescanreset_in : in std_logic; gt0_rxuserrdy_in : in std_logic; -------------------------- RX Margin Analysis Ports ------------------------ gt0_eyescandataerror_out : out std_logic; gt0_eyescantrigger_in : in std_logic; ------------------- Receive Ports - Digital Monitor Ports ------------------ gt0_dmonitorout_out : out std_logic_vector(14 downto 0); ------------------ Receive Ports - FPGA RX Interface Ports ----------------- gt0_rxusrclk_in : in std_logic; gt0_rxusrclk2_in : in std_logic; ------------------ Receive Ports - FPGA RX interface Ports ----------------- gt0_rxdata_out : out std_logic_vector(31 downto 0); ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- gt0_rxdisperr_out : out std_logic_vector(3 downto 0); gt0_rxnotintable_out : out std_logic_vector(3 downto 0); ------------------------ Receive Ports - RX AFE Ports ---------------------- gt0_gthrxn_in : in std_logic; -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ gt0_rxpcommaalignen_in : in std_logic; --------------------- Receive Ports - RX Equalizer Ports ------------------- gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); --------------- Receive Ports - RX Fabric Output Control Ports ------------- gt0_rxoutclk_out : out std_logic; gt0_rxoutclkfabric_out : out std_logic; ------------- Receive Ports - RX Initialization and Reset Ports ------------ gt0_gtrxreset_in : in std_logic; ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- gt0_rxcharisk_out : out std_logic_vector(3 downto 0); ------------------------ Receive Ports -RX AFE Ports ----------------------- gt0_gthrxp_in : in std_logic; -------------- Receive Ports -RX Initialization and Reset Ports ------------ gt0_rxresetdone_out : out std_logic; --------------------- TX Initialization and Reset Ports -------------------- gt0_gttxreset_in : in std_logic; --____________________________COMMON PORTS________________________________ GT0_QPLLOUTCLK_IN : in std_logic; GT0_QPLLOUTREFCLK_IN : in std_logic ); end MGT_combined_ttc_rx; architecture RTL of MGT_combined_ttc_rx is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of RTL : architecture is "MGT_combined_ttc_rx,gtwizard_v3_6_11,{protocol_file=Start_from_scratch}"; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of RTL : architecture is "MGT_combined_ttc_rx,gtwizard_v3_6_11,{protocol_file=Start_from_scratch}"; --**************************Component Declarations***************************** component MGT_combined_ttc_rx_init generic ( EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic STABLE_CLOCK_PERIOD : integer := 24; -- Set to 1 for simulation EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets ); port ( SYSCLK_IN : in std_logic; SOFT_RESET_RX_IN : in std_logic; DONT_RESET_ON_DATA_ERROR_IN : in std_logic; GT0_TX_FSM_RESET_DONE_OUT : out std_logic; GT0_RX_FSM_RESET_DONE_OUT : out std_logic; GT0_DATA_VALID_IN : in std_logic; --_________________________________________________________________________ --GT0 (X0Y38) --____________________________CHANNEL PORTS________________________________ --------------------------------- CPLL Ports ------------------------------- gt0_cpllfbclklost_out : out std_logic; gt0_cplllock_out : out std_logic; gt0_cplllockdetclk_in : in std_logic; gt0_cpllreset_in : in std_logic; -------------------------- Channel - Clocking Ports ------------------------ gt0_gtrefclk0_in : in std_logic; gt0_gtrefclk1_in : in std_logic; ---------------------------- Channel - DRP Ports -------------------------- gt0_drpaddr_in : in std_logic_vector(8 downto 0); gt0_drpclk_in : in std_logic; gt0_drpdi_in : in std_logic_vector(15 downto 0); gt0_drpdo_out : out std_logic_vector(15 downto 0); gt0_drpen_in : in std_logic; gt0_drprdy_out : out std_logic; gt0_drpwe_in : in std_logic; --------------------- RX Initialization and Reset Ports -------------------- gt0_eyescanreset_in : in std_logic; gt0_rxuserrdy_in : in std_logic; -------------------------- RX Margin Analysis Ports ------------------------ gt0_eyescandataerror_out : out std_logic; gt0_eyescantrigger_in : in std_logic; ------------------- Receive Ports - Digital Monitor Ports ------------------ gt0_dmonitorout_out : out std_logic_vector(14 downto 0); ------------------ Receive Ports - FPGA RX Interface Ports ----------------- gt0_rxusrclk_in : in std_logic; gt0_rxusrclk2_in : in std_logic; ------------------ Receive Ports - FPGA RX interface Ports ----------------- gt0_rxdata_out : out std_logic_vector(31 downto 0); ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- gt0_rxdisperr_out : out std_logic_vector(3 downto 0); gt0_rxnotintable_out : out std_logic_vector(3 downto 0); ------------------------ Receive Ports - RX AFE Ports ---------------------- gt0_gthrxn_in : in std_logic; -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ gt0_rxpcommaalignen_in : in std_logic; --------------------- Receive Ports - RX Equalizer Ports ------------------- gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); --------------- Receive Ports - RX Fabric Output Control Ports ------------- gt0_rxoutclk_out : out std_logic; gt0_rxoutclkfabric_out : out std_logic; ------------- Receive Ports - RX Initialization and Reset Ports ------------ gt0_gtrxreset_in : in std_logic; ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- gt0_rxcharisk_out : out std_logic_vector(3 downto 0); ------------------------ Receive Ports -RX AFE Ports ----------------------- gt0_gthrxp_in : in std_logic; -------------- Receive Ports -RX Initialization and Reset Ports ------------ gt0_rxresetdone_out : out std_logic; --------------------- TX Initialization and Reset Ports -------------------- gt0_gttxreset_in : in std_logic; --____________________________COMMON PORTS________________________________ GT0_QPLLOUTCLK_IN : in std_logic; GT0_QPLLOUTREFCLK_IN : in std_logic ); end component; --**************************** Main Body of Code ******************************* begin U0 : MGT_combined_ttc_rx_init generic map ( EXAMPLE_SIM_GTRESET_SPEEDUP => "TRUE", EXAMPLE_SIMULATION => 0, USE_BUFG => 0, STABLE_CLOCK_PERIOD => 24, EXAMPLE_USE_CHIPSCOPE => 0 ) port map ( SYSCLK_IN => SYSCLK_IN, SOFT_RESET_RX_IN => SOFT_RESET_RX_IN, DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN, GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT, GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT, GT0_DATA_VALID_IN => GT0_DATA_VALID_IN, --_________________________________________________________________________ --GT0 (X0Y38) --____________________________CHANNEL PORTS________________________________ --------------------------------- CPLL Ports ------------------------------- gt0_cpllfbclklost_out => gt0_cpllfbclklost_out, gt0_cplllock_out => gt0_cplllock_out, gt0_cplllockdetclk_in => gt0_cplllockdetclk_in, gt0_cpllreset_in => gt0_cpllreset_in, -------------------------- Channel - Clocking Ports ------------------------ gt0_gtrefclk0_in => gt0_gtrefclk0_in, gt0_gtrefclk1_in => gt0_gtrefclk1_in, ---------------------------- Channel - DRP Ports -------------------------- gt0_drpaddr_in => gt0_drpaddr_in, gt0_drpclk_in => gt0_drpclk_in, gt0_drpdi_in => gt0_drpdi_in, gt0_drpdo_out => gt0_drpdo_out, gt0_drpen_in => gt0_drpen_in, gt0_drprdy_out => gt0_drprdy_out, gt0_drpwe_in => gt0_drpwe_in, --------------------- RX Initialization and Reset Ports -------------------- gt0_eyescanreset_in => gt0_eyescanreset_in, gt0_rxuserrdy_in => gt0_rxuserrdy_in, -------------------------- RX Margin Analysis Ports ------------------------ gt0_eyescandataerror_out => gt0_eyescandataerror_out, gt0_eyescantrigger_in => gt0_eyescantrigger_in, ------------------- Receive Ports - Digital Monitor Ports ------------------ gt0_dmonitorout_out => gt0_dmonitorout_out, ------------------ Receive Ports - FPGA RX Interface Ports ----------------- gt0_rxusrclk_in => gt0_rxusrclk_in, gt0_rxusrclk2_in => gt0_rxusrclk2_in, ------------------ Receive Ports - FPGA RX interface Ports ----------------- gt0_rxdata_out => gt0_rxdata_out, ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- gt0_rxdisperr_out => gt0_rxdisperr_out, gt0_rxnotintable_out => gt0_rxnotintable_out, ------------------------ Receive Ports - RX AFE Ports ---------------------- gt0_gthrxn_in => gt0_gthrxn_in, -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ gt0_rxpcommaalignen_in => gt0_rxpcommaalignen_in, --------------------- Receive Ports - RX Equalizer Ports ------------------- gt0_rxmonitorout_out => gt0_rxmonitorout_out, gt0_rxmonitorsel_in => gt0_rxmonitorsel_in, --------------- Receive Ports - RX Fabric Output Control Ports ------------- gt0_rxoutclk_out => gt0_rxoutclk_out, gt0_rxoutclkfabric_out => gt0_rxoutclkfabric_out, ------------- Receive Ports - RX Initialization and Reset Ports ------------ gt0_gtrxreset_in => gt0_gtrxreset_in, ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- gt0_rxcharisk_out => gt0_rxcharisk_out, ------------------------ Receive Ports -RX AFE Ports ----------------------- gt0_gthrxp_in => gt0_gthrxp_in, -------------- Receive Ports -RX Initialization and Reset Ports ------------ gt0_rxresetdone_out => gt0_rxresetdone_out, --------------------- TX Initialization and Reset Ports -------------------- gt0_gttxreset_in => gt0_gttxreset_in, --____________________________COMMON PORTS________________________________ GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN, GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN ); end RTL;