-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Mon Mar 21 18:28:36 2022
-- Host        : hog-efex3.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode funcsim
--               /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_sim_netlist.vhdl
-- Design      : aurora_1ln_rx_lpm
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx550tffg1927-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL is
  port (
    MUX_SELECT : out STD_LOGIC_VECTOR ( 0 to 0 );
    mux_select_c : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL : entity is "aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL is
begin
\MUX_SELECT_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => mux_select_c(0),
      Q => MUX_SELECT(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_MUX is
  port (
    \MUXED_DATA_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    D : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
    MUX_SELECT : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    STORAGE_SELECT_Buffer : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_MUX : entity is "aurora_1ln_rx_lpm_LEFT_ALIGN_MUX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_MUX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_MUX is
  signal \^muxed_data_buffer_reg[0]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \MUXED_DATA_Buffer_reg_n_0_[16]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[17]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[18]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[19]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[20]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[21]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[22]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[23]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[24]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[25]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[26]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[27]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[28]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[29]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[30]\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer_reg_n_0_[31]\ : STD_LOGIC;
  signal muxed_data_c : STD_LOGIC_VECTOR ( 0 to 15 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[0]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[10]_i_1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[11]_i_1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[12]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[13]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[14]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[15]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[1]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[2]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[3]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[4]_i_1\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[5]_i_1\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[6]_i_1\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[7]_i_1\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[8]_i_1\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[9]_i_1\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[0]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[10]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[11]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[12]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[13]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[14]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[15]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[16]_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[17]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[18]_i_1\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[19]_i_1\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[1]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[20]_i_1\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[21]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[22]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[23]_i_1\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[24]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[25]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[26]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[27]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[28]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[29]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[2]_i_1\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[30]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[31]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[3]_i_1\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[4]_i_1\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[5]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[6]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[7]_i_1\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[8]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \STORAGE_DATA_Buffer[9]_i_1\ : label is "soft_lutpair61";
begin
  \MUXED_DATA_Buffer_reg[0]_0\(15 downto 0) <= \^muxed_data_buffer_reg[0]_0\(15 downto 0);
\MUXED_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => MUX_SELECT(0),
      I2 => Q(31),
      O => muxed_data_c(0)
    );
\MUXED_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => MUX_SELECT(0),
      I2 => Q(21),
      O => muxed_data_c(10)
    );
\MUXED_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => MUX_SELECT(0),
      I2 => Q(20),
      O => muxed_data_c(11)
    );
\MUXED_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(3),
      I1 => MUX_SELECT(0),
      I2 => Q(19),
      O => muxed_data_c(12)
    );
\MUXED_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(2),
      I1 => MUX_SELECT(0),
      I2 => Q(18),
      O => muxed_data_c(13)
    );
\MUXED_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => MUX_SELECT(0),
      I2 => Q(17),
      O => muxed_data_c(14)
    );
\MUXED_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => MUX_SELECT(0),
      I2 => Q(16),
      O => muxed_data_c(15)
    );
\MUXED_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => MUX_SELECT(0),
      I2 => Q(30),
      O => muxed_data_c(1)
    );
\MUXED_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => MUX_SELECT(0),
      I2 => Q(29),
      O => muxed_data_c(2)
    );
\MUXED_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => MUX_SELECT(0),
      I2 => Q(28),
      O => muxed_data_c(3)
    );
\MUXED_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => MUX_SELECT(0),
      I2 => Q(27),
      O => muxed_data_c(4)
    );
\MUXED_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => MUX_SELECT(0),
      I2 => Q(26),
      O => muxed_data_c(5)
    );
\MUXED_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => MUX_SELECT(0),
      I2 => Q(25),
      O => muxed_data_c(6)
    );
\MUXED_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => MUX_SELECT(0),
      I2 => Q(24),
      O => muxed_data_c(7)
    );
\MUXED_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => MUX_SELECT(0),
      I2 => Q(23),
      O => muxed_data_c(8)
    );
\MUXED_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => MUX_SELECT(0),
      I2 => Q(22),
      O => muxed_data_c(9)
    );
\MUXED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(0),
      Q => \^muxed_data_buffer_reg[0]_0\(15),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(10),
      Q => \^muxed_data_buffer_reg[0]_0\(5),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(11),
      Q => \^muxed_data_buffer_reg[0]_0\(4),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(12),
      Q => \^muxed_data_buffer_reg[0]_0\(3),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(13),
      Q => \^muxed_data_buffer_reg[0]_0\(2),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(14),
      Q => \^muxed_data_buffer_reg[0]_0\(1),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(15),
      Q => \^muxed_data_buffer_reg[0]_0\(0),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(15),
      Q => \MUXED_DATA_Buffer_reg_n_0_[16]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(14),
      Q => \MUXED_DATA_Buffer_reg_n_0_[17]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(13),
      Q => \MUXED_DATA_Buffer_reg_n_0_[18]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(12),
      Q => \MUXED_DATA_Buffer_reg_n_0_[19]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(1),
      Q => \^muxed_data_buffer_reg[0]_0\(14),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(11),
      Q => \MUXED_DATA_Buffer_reg_n_0_[20]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(10),
      Q => \MUXED_DATA_Buffer_reg_n_0_[21]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(9),
      Q => \MUXED_DATA_Buffer_reg_n_0_[22]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(8),
      Q => \MUXED_DATA_Buffer_reg_n_0_[23]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(7),
      Q => \MUXED_DATA_Buffer_reg_n_0_[24]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(6),
      Q => \MUXED_DATA_Buffer_reg_n_0_[25]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(5),
      Q => \MUXED_DATA_Buffer_reg_n_0_[26]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(4),
      Q => \MUXED_DATA_Buffer_reg_n_0_[27]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(3),
      Q => \MUXED_DATA_Buffer_reg_n_0_[28]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(2),
      Q => \MUXED_DATA_Buffer_reg_n_0_[29]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(2),
      Q => \^muxed_data_buffer_reg[0]_0\(13),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(1),
      Q => \MUXED_DATA_Buffer_reg_n_0_[30]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => \MUXED_DATA_Buffer_reg_n_0_[31]\,
      R => '0'
    );
\MUXED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(3),
      Q => \^muxed_data_buffer_reg[0]_0\(12),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(4),
      Q => \^muxed_data_buffer_reg[0]_0\(11),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(5),
      Q => \^muxed_data_buffer_reg[0]_0\(10),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(6),
      Q => \^muxed_data_buffer_reg[0]_0\(9),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(7),
      Q => \^muxed_data_buffer_reg[0]_0\(8),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(8),
      Q => \^muxed_data_buffer_reg[0]_0\(7),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(9),
      Q => \^muxed_data_buffer_reg[0]_0\(6),
      R => '0'
    );
\STORAGE_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[16]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(15),
      O => D(31)
    );
\STORAGE_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[26]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(5),
      O => D(21)
    );
\STORAGE_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[27]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(4),
      O => D(20)
    );
\STORAGE_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[28]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(3),
      O => D(19)
    );
\STORAGE_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[29]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(2),
      O => D(18)
    );
\STORAGE_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[30]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(1),
      O => D(17)
    );
\STORAGE_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[31]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(0),
      O => D(16)
    );
\STORAGE_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[16]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(15),
      O => D(15)
    );
\STORAGE_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[17]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(14),
      O => D(14)
    );
\STORAGE_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[18]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(13),
      O => D(13)
    );
\STORAGE_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[19]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(12),
      O => D(12)
    );
\STORAGE_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[17]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(14),
      O => D(30)
    );
\STORAGE_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[20]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(11),
      O => D(11)
    );
\STORAGE_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[21]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(10),
      O => D(10)
    );
\STORAGE_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[22]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(9),
      O => D(9)
    );
\STORAGE_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[23]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(8),
      O => D(8)
    );
\STORAGE_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[24]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(7),
      O => D(7)
    );
\STORAGE_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[25]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(6),
      O => D(6)
    );
\STORAGE_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[26]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(5),
      O => D(5)
    );
\STORAGE_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[27]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(4),
      O => D(4)
    );
\STORAGE_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[28]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(3),
      O => D(3)
    );
\STORAGE_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[29]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(2),
      O => D(2)
    );
\STORAGE_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[18]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(13),
      O => D(29)
    );
\STORAGE_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[30]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(1),
      O => D(1)
    );
\STORAGE_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[31]\,
      I1 => STORAGE_SELECT_Buffer(0),
      I2 => \^muxed_data_buffer_reg[0]_0\(0),
      O => D(0)
    );
\STORAGE_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[19]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(12),
      O => D(28)
    );
\STORAGE_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[20]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(11),
      O => D(27)
    );
\STORAGE_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[21]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(10),
      O => D(26)
    );
\STORAGE_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[22]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(9),
      O => D(25)
    );
\STORAGE_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[23]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(8),
      O => D(24)
    );
\STORAGE_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[24]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(7),
      O => D(23)
    );
\STORAGE_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MUXED_DATA_Buffer_reg_n_0_[25]\,
      I1 => STORAGE_SELECT_Buffer(1),
      I2 => \^muxed_data_buffer_reg[0]_0\(6),
      O => D(22)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LL_TO_AXI is
  port (
    M_AXI_RX_TKEEP : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rx_eof : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LL_TO_AXI : entity is "aurora_1ln_rx_lpm_LL_TO_AXI";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LL_TO_AXI;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LL_TO_AXI is
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[1]_INST_0\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[3]_INST_0\ : label is "soft_lutpair138";
begin
\M_AXI_RX_TKEEP[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rx_eof,
      I1 => Q(0),
      I2 => Q(1),
      O => M_AXI_RX_TKEEP(0)
    );
\M_AXI_RX_TKEEP[2]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rx_eof,
      I1 => Q(1),
      O => M_AXI_RX_TKEEP(1)
    );
\M_AXI_RX_TKEEP[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => rx_eof,
      I1 => Q(1),
      I2 => Q(0),
      O => M_AXI_RX_TKEEP(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_MUX is
  port (
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
    user_clk : in STD_LOGIC;
    \OUTPUT_DATA_Buffer_reg[16]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    OUTPUT_SELECT_Buffer : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_MUX : entity is "aurora_1ln_rx_lpm_OUTPUT_MUX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_MUX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_MUX is
  signal output_data_c : STD_LOGIC_VECTOR ( 16 to 31 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[16]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[17]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[18]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[19]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[20]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[21]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[22]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[23]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[24]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[25]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[26]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[27]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[28]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[29]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[30]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[31]_i_1\ : label is "soft_lutpair34";
begin
\OUTPUT_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(15),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(15),
      O => output_data_c(16)
    );
\OUTPUT_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(14),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(14),
      O => output_data_c(17)
    );
\OUTPUT_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(13),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(13),
      O => output_data_c(18)
    );
\OUTPUT_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(12),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(12),
      O => output_data_c(19)
    );
\OUTPUT_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(11),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(11),
      O => output_data_c(20)
    );
\OUTPUT_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(10),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(10),
      O => output_data_c(21)
    );
\OUTPUT_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(9),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(9),
      O => output_data_c(22)
    );
\OUTPUT_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(8),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(8),
      O => output_data_c(23)
    );
\OUTPUT_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(7),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(7),
      O => output_data_c(24)
    );
\OUTPUT_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(6),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(6),
      O => output_data_c(25)
    );
\OUTPUT_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(5),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(5),
      O => output_data_c(26)
    );
\OUTPUT_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(4),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(4),
      O => output_data_c(27)
    );
\OUTPUT_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(3),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(3),
      O => output_data_c(28)
    );
\OUTPUT_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(2),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(2),
      O => output_data_c(29)
    );
\OUTPUT_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(1),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(1),
      O => output_data_c(30)
    );
\OUTPUT_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[16]_0\(0),
      I1 => OUTPUT_SELECT_Buffer,
      I2 => Q(0),
      O => output_data_c(31)
    );
\OUTPUT_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(31),
      Q => M_AXI_RX_TDATA(7),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(21),
      Q => M_AXI_RX_TDATA(13),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(20),
      Q => M_AXI_RX_TDATA(12),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(19),
      Q => M_AXI_RX_TDATA(11),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(18),
      Q => M_AXI_RX_TDATA(10),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(17),
      Q => M_AXI_RX_TDATA(9),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(16),
      Q => M_AXI_RX_TDATA(8),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(16),
      Q => M_AXI_RX_TDATA(23),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(17),
      Q => M_AXI_RX_TDATA(22),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(18),
      Q => M_AXI_RX_TDATA(21),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(19),
      Q => M_AXI_RX_TDATA(20),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(30),
      Q => M_AXI_RX_TDATA(6),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(20),
      Q => M_AXI_RX_TDATA(19),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(21),
      Q => M_AXI_RX_TDATA(18),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(22),
      Q => M_AXI_RX_TDATA(17),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(23),
      Q => M_AXI_RX_TDATA(16),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(24),
      Q => M_AXI_RX_TDATA(31),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(25),
      Q => M_AXI_RX_TDATA(30),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(26),
      Q => M_AXI_RX_TDATA(29),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(27),
      Q => M_AXI_RX_TDATA(28),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(28),
      Q => M_AXI_RX_TDATA(27),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(29),
      Q => M_AXI_RX_TDATA(26),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(29),
      Q => M_AXI_RX_TDATA(5),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(30),
      Q => M_AXI_RX_TDATA(25),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(31),
      Q => M_AXI_RX_TDATA(24),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(28),
      Q => M_AXI_RX_TDATA(4),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(27),
      Q => M_AXI_RX_TDATA(3),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(26),
      Q => M_AXI_RX_TDATA(2),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(25),
      Q => M_AXI_RX_TDATA(1),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(24),
      Q => M_AXI_RX_TDATA(0),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(23),
      Q => M_AXI_RX_TDATA(15),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(22),
      Q => M_AXI_RX_TDATA(14),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL is
  port (
    OUTPUT_SELECT_Buffer : out STD_LOGIC;
    output_select_c : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL : entity is "aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL is
begin
\OUTPUT_SELECT_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_select_c(0),
      Q => OUTPUT_SELECT_Buffer,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX is
  port (
    SOFT_ERR : out STD_LOGIC;
    RX_HARD_ERR : out STD_LOGIC;
    reset_channel_i : out STD_LOGIC;
    wait_for_lane_up_r0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    rx_hard_err_i : in STD_LOGIC;
    RX_LANE_UP : in STD_LOGIC;
    wait_for_lane_up_r_reg : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX : entity is "aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX is
  signal RESET_CHANNEL_Buffer_i_1_n_0 : STD_LOGIC;
  signal channel_soft_err_c : STD_LOGIC;
  signal hard_err_r : STD_LOGIC;
  signal lane_up_r : STD_LOGIC;
  signal \^reset_channel_i\ : STD_LOGIC;
  signal \soft_err_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \soft_err_r_reg_n_0_[1]\ : STD_LOGIC;
begin
  reset_channel_i <= \^reset_channel_i\;
CHANNEL_HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => hard_err_r,
      Q => RX_HARD_ERR,
      R => '0'
    );
CHANNEL_SOFT_ERR_Buffer_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \soft_err_r_reg_n_0_[0]\,
      I1 => \soft_err_r_reg_n_0_[1]\,
      O => channel_soft_err_c
    );
CHANNEL_SOFT_ERR_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => channel_soft_err_c,
      Q => SOFT_ERR,
      R => '0'
    );
RESET_CHANNEL_Buffer_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => POWER_DOWN,
      I1 => lane_up_r,
      O => RESET_CHANNEL_Buffer_i_1_n_0
    );
RESET_CHANNEL_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => RESET_CHANNEL_Buffer_i_1_n_0,
      Q => \^reset_channel_i\,
      R => '0'
    );
hard_err_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_hard_err_i,
      Q => hard_err_r,
      R => '0'
    );
lane_up_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_LANE_UP,
      Q => lane_up_r,
      R => '0'
    );
\soft_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => \soft_err_r_reg_n_0_[0]\,
      R => '0'
    );
\soft_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \soft_err_r_reg_n_0_[1]\,
      R => '0'
    );
wait_for_lane_up_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset_channel_i\,
      I1 => wait_for_lane_up_r_reg,
      O => wait_for_lane_up_r0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    GTRXRESET_OUT : out STD_LOGIC;
    RX_CHANNEL_UP : out STD_LOGIC;
    START_RX : out STD_LOGIC;
    RESET : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    GOT_V : in STD_LOGIC;
    wait_for_lane_up_r0 : in STD_LOGIC;
    START_RX_Buffer_reg_0 : in STD_LOGIC;
    reset_channel_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX : entity is "aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX is
  signal D : STD_LOGIC;
  signal GTRXRESET_OUT_i_1_n_0 : STD_LOGIC;
  signal GTRXRESET_OUT_i_2_n_0 : STD_LOGIC;
  signal Q : STD_LOGIC;
  signal \^start_rx\ : STD_LOGIC;
  signal START_RX_Buffer0 : STD_LOGIC;
  signal all_lanes_v_r : STD_LOGIC;
  signal bad_v_r : STD_LOGIC;
  signal bad_v_r0 : STD_LOGIC;
  signal \free_count_r[13]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[13]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[13]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[13]_i_5_n_0\ : STD_LOGIC;
  signal \free_count_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_5_n_0\ : STD_LOGIC;
  signal free_count_r_reg : STD_LOGIC_VECTOR ( 0 to 13 );
  signal \free_count_r_reg[13]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[1]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[1]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[1]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_7\ : STD_LOGIC;
  signal got_first_v_r : STD_LOGIC;
  signal got_first_v_r_i_1_n_0 : STD_LOGIC;
  signal gtrxreset_extend_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal next_ready_c : STD_LOGIC;
  signal next_verify_c : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_2_out : STD_LOGIC_VECTOR ( 15 to 15 );
  signal ready_r : STD_LOGIC;
  signal ready_r2 : STD_LOGIC;
  signal \rxver_count_r_reg[1]_srl2_i_1_n_0\ : STD_LOGIC;
  signal \rxver_count_r_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \rxver_count_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \v_count_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \v_count_r_reg_n_0_[15]\ : STD_LOGIC;
  signal verify_r : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_i_1_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_i_2_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_i_3_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_i_4_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg_n_0_[15]\ : STD_LOGIC;
  signal wait_for_lane_up_r : STD_LOGIC;
  signal \NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of got_first_v_r_i_1 : label is "soft_lutpair32";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of gtreset_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of gtreset_flop_0_i : label is "FD";
  attribute SOFT_HLUTNM of gtreset_flop_0_i_i_1 : label is "soft_lutpair33";
  attribute BOX_TYPE of reset_lanes_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_i : label is "FD";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \rxver_count_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \rxver_count_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg[1]_srl2 ";
  attribute srl_bus_name of \v_count_r_reg[14]_srl15\ : label is "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg ";
  attribute srl_name of \v_count_r_reg[14]_srl15\ : label is "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg[14]_srl15 ";
  attribute SOFT_HLUTNM of \v_count_r_reg[14]_srl15_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of verify_r_i_1 : label is "soft_lutpair33";
  attribute srl_bus_name of \verify_watchdog_r_reg[14]_srl15\ : label is "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg ";
  attribute srl_name of \verify_watchdog_r_reg[14]_srl15\ : label is "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg[14]_srl15 ";
begin
  START_RX <= \^start_rx\;
CHANNEL_UP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ready_r2,
      Q => RX_CHANNEL_UP,
      R => '0'
    );
FRAME_ERR_Buffer_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^start_rx\,
      O => RESET
    );
GTRXRESET_OUT_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => gtrxreset_extend_r(2),
      I1 => gtrxreset_extend_r(3),
      I2 => gtrxreset_extend_r(0),
      I3 => gtrxreset_extend_r(1),
      I4 => GTRXRESET_OUT_i_2_n_0,
      O => GTRXRESET_OUT_i_1_n_0
    );
GTRXRESET_OUT_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => gtrxreset_extend_r(5),
      I1 => gtrxreset_extend_r(4),
      I2 => gtrxreset_extend_r(7),
      I3 => gtrxreset_extend_r(6),
      O => GTRXRESET_OUT_i_2_n_0
    );
GTRXRESET_OUT_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => GTRXRESET_OUT_i_1_n_0,
      Q => GTRXRESET_OUT,
      R => '0'
    );
START_RX_Buffer_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_for_lane_up_r,
      O => START_RX_Buffer0
    );
START_RX_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => START_RX_Buffer0,
      Q => \^start_rx\,
      R => START_RX_Buffer_reg_0
    );
all_lanes_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => GOT_V,
      Q => all_lanes_v_r,
      R => '0'
    );
bad_v_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => got_first_v_r,
      I1 => all_lanes_v_r,
      I2 => \v_count_r_reg_n_0_[15]\,
      O => bad_v_r0
    );
bad_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => bad_v_r0,
      Q => bad_v_r,
      R => '0'
    );
\free_count_r[13]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(10),
      O => \free_count_r[13]_i_2_n_0\
    );
\free_count_r[13]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(11),
      O => \free_count_r[13]_i_3_n_0\
    );
\free_count_r[13]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(12),
      O => \free_count_r[13]_i_4_n_0\
    );
\free_count_r[13]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(13),
      O => \free_count_r[13]_i_5_n_0\
    );
\free_count_r[1]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(0),
      O => \free_count_r[1]_i_2_n_0\
    );
\free_count_r[1]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(1),
      O => \free_count_r[1]_i_3_n_0\
    );
\free_count_r[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(2),
      O => \free_count_r[5]_i_2_n_0\
    );
\free_count_r[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(3),
      O => \free_count_r[5]_i_3_n_0\
    );
\free_count_r[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(4),
      O => \free_count_r[5]_i_4_n_0\
    );
\free_count_r[5]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(5),
      O => \free_count_r[5]_i_5_n_0\
    );
\free_count_r[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(6),
      O => \free_count_r[9]_i_2_n_0\
    );
\free_count_r[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(7),
      O => \free_count_r[9]_i_3_n_0\
    );
\free_count_r[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(8),
      O => \free_count_r[9]_i_4_n_0\
    );
\free_count_r[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(9),
      O => \free_count_r[9]_i_5_n_0\
    );
\free_count_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[1]_i_1_n_6\,
      Q => free_count_r_reg(0),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_4\,
      Q => free_count_r_reg(10),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[11]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_5\,
      Q => free_count_r_reg(11),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[12]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_6\,
      Q => free_count_r_reg(12),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[13]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_7\,
      Q => free_count_r_reg(13),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[13]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \free_count_r_reg[13]_i_1_n_0\,
      CO(2) => \free_count_r_reg[13]_i_1_n_1\,
      CO(1) => \free_count_r_reg[13]_i_1_n_2\,
      CO(0) => \free_count_r_reg[13]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[13]_i_1_n_4\,
      O(2) => \free_count_r_reg[13]_i_1_n_5\,
      O(1) => \free_count_r_reg[13]_i_1_n_6\,
      O(0) => \free_count_r_reg[13]_i_1_n_7\,
      S(3) => \free_count_r[13]_i_2_n_0\,
      S(2) => \free_count_r[13]_i_3_n_0\,
      S(1) => \free_count_r[13]_i_4_n_0\,
      S(0) => \free_count_r[13]_i_5_n_0\
    );
\free_count_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[1]_i_1_n_7\,
      Q => free_count_r_reg(1),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[1]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[5]_i_1_n_0\,
      CO(3 downto 1) => \NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \free_count_r_reg[1]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3 downto 2) => \NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1) => \free_count_r_reg[1]_i_1_n_6\,
      O(0) => \free_count_r_reg[1]_i_1_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \free_count_r[1]_i_2_n_0\,
      S(0) => \free_count_r[1]_i_3_n_0\
    );
\free_count_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_4\,
      Q => free_count_r_reg(2),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_5\,
      Q => free_count_r_reg(3),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_6\,
      Q => free_count_r_reg(4),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_7\,
      Q => free_count_r_reg(5),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[9]_i_1_n_0\,
      CO(3) => \free_count_r_reg[5]_i_1_n_0\,
      CO(2) => \free_count_r_reg[5]_i_1_n_1\,
      CO(1) => \free_count_r_reg[5]_i_1_n_2\,
      CO(0) => \free_count_r_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[5]_i_1_n_4\,
      O(2) => \free_count_r_reg[5]_i_1_n_5\,
      O(1) => \free_count_r_reg[5]_i_1_n_6\,
      O(0) => \free_count_r_reg[5]_i_1_n_7\,
      S(3) => \free_count_r[5]_i_2_n_0\,
      S(2) => \free_count_r[5]_i_3_n_0\,
      S(1) => \free_count_r[5]_i_4_n_0\,
      S(0) => \free_count_r[5]_i_5_n_0\
    );
\free_count_r_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_4\,
      Q => free_count_r_reg(6),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_5\,
      Q => free_count_r_reg(7),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_6\,
      Q => free_count_r_reg(8),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[9]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_7\,
      Q => free_count_r_reg(9),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[13]_i_1_n_0\,
      CO(3) => \free_count_r_reg[9]_i_1_n_0\,
      CO(2) => \free_count_r_reg[9]_i_1_n_1\,
      CO(1) => \free_count_r_reg[9]_i_1_n_2\,
      CO(0) => \free_count_r_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[9]_i_1_n_4\,
      O(2) => \free_count_r_reg[9]_i_1_n_5\,
      O(1) => \free_count_r_reg[9]_i_1_n_6\,
      O(0) => \free_count_r_reg[9]_i_1_n_7\,
      S(3) => \free_count_r[9]_i_2_n_0\,
      S(2) => \free_count_r[9]_i_3_n_0\,
      S(1) => \free_count_r[9]_i_4_n_0\,
      S(0) => \free_count_r[9]_i_5_n_0\
    );
got_first_v_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => verify_r,
      I1 => got_first_v_r,
      I2 => all_lanes_v_r,
      O => got_first_v_r_i_1_n_0
    );
got_first_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_first_v_r_i_1_n_0,
      Q => got_first_v_r,
      R => '0'
    );
gtreset_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_2_in,
      Q => Q,
      R => '0'
    );
gtreset_flop_0_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => verify_r,
      I1 => \verify_watchdog_r_reg_n_0_[15]\,
      I2 => \rxver_count_r_reg_n_0_[2]\,
      I3 => bad_v_r,
      O => p_2_in
    );
\gtrxreset_extend_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(1),
      Q => gtrxreset_extend_r(0),
      R => START_RX_Buffer_reg_0
    );
\gtrxreset_extend_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(2),
      Q => gtrxreset_extend_r(1),
      R => START_RX_Buffer_reg_0
    );
\gtrxreset_extend_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(3),
      Q => gtrxreset_extend_r(2),
      R => START_RX_Buffer_reg_0
    );
\gtrxreset_extend_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(4),
      Q => gtrxreset_extend_r(3),
      R => START_RX_Buffer_reg_0
    );
\gtrxreset_extend_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(5),
      Q => gtrxreset_extend_r(4),
      R => START_RX_Buffer_reg_0
    );
\gtrxreset_extend_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(6),
      Q => gtrxreset_extend_r(5),
      R => START_RX_Buffer_reg_0
    );
\gtrxreset_extend_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(7),
      Q => gtrxreset_extend_r(6),
      R => START_RX_Buffer_reg_0
    );
\gtrxreset_extend_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => Q,
      Q => gtrxreset_extend_r(7),
      R => START_RX_Buffer_reg_0
    );
ready_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ready_r,
      Q => ready_r2,
      R => '0'
    );
\ready_r_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => ready_r,
      I1 => verify_r,
      I2 => \rxver_count_r_reg_n_0_[2]\,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => ready_r,
      R => wait_for_lane_up_r0
    );
reset_lanes_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => SR(0),
      R => '0'
    );
reset_lanes_flop_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => p_2_in,
      I1 => reset_channel_i,
      I2 => wait_for_lane_up_r,
      I3 => START_RX_Buffer_reg_0,
      O => D
    );
\rxver_count_r_reg[1]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => \rxver_count_r_reg[1]_srl2_i_1_n_0\,
      CLK => user_clk,
      D => verify_r,
      Q => \rxver_count_r_reg[1]_srl2_n_0\
    );
\rxver_count_r_reg[1]_srl2_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => all_lanes_v_r,
      I1 => \v_count_r_reg_n_0_[15]\,
      I2 => verify_r,
      O => \rxver_count_r_reg[1]_srl2_i_1_n_0\
    );
\rxver_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \rxver_count_r_reg[1]_srl2_i_1_n_0\,
      D => \rxver_count_r_reg[1]_srl2_n_0\,
      Q => \rxver_count_r_reg_n_0_[2]\,
      R => '0'
    );
\v_count_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => '1',
      CLK => user_clk,
      D => p_2_out(15),
      Q => \v_count_r_reg[14]_srl15_n_0\
    );
\v_count_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \v_count_r_reg_n_0_[15]\,
      I1 => verify_r,
      I2 => got_first_v_r,
      I3 => all_lanes_v_r,
      O => p_2_out(15)
    );
\v_count_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \v_count_r_reg[14]_srl15_n_0\,
      Q => \v_count_r_reg_n_0_[15]\,
      R => '0'
    );
verify_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => wait_for_lane_up_r,
      I1 => \rxver_count_r_reg_n_0_[2]\,
      I2 => verify_r,
      O => next_verify_c
    );
verify_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_verify_c,
      Q => verify_r,
      R => wait_for_lane_up_r0
    );
\verify_watchdog_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => \verify_watchdog_r_reg[14]_srl15_i_1_n_0\,
      CLK => user_clk,
      D => verify_r,
      Q => \verify_watchdog_r_reg[14]_srl15_n_0\
    );
\verify_watchdog_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10FF"
    )
        port map (
      I0 => \verify_watchdog_r_reg[14]_srl15_i_2_n_0\,
      I1 => \verify_watchdog_r_reg[14]_srl15_i_3_n_0\,
      I2 => \verify_watchdog_r_reg[14]_srl15_i_4_n_0\,
      I3 => verify_r,
      O => \verify_watchdog_r_reg[14]_srl15_i_1_n_0\
    );
\verify_watchdog_r_reg[14]_srl15_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => free_count_r_reg(2),
      I1 => free_count_r_reg(6),
      I2 => free_count_r_reg(5),
      I3 => free_count_r_reg(11),
      O => \verify_watchdog_r_reg[14]_srl15_i_2_n_0\
    );
\verify_watchdog_r_reg[14]_srl15_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => free_count_r_reg(1),
      I1 => free_count_r_reg(10),
      I2 => free_count_r_reg(0),
      I3 => free_count_r_reg(12),
      O => \verify_watchdog_r_reg[14]_srl15_i_3_n_0\
    );
\verify_watchdog_r_reg[14]_srl15_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => free_count_r_reg(8),
      I1 => free_count_r_reg(9),
      I2 => free_count_r_reg(7),
      I3 => free_count_r_reg(3),
      I4 => free_count_r_reg(4),
      I5 => free_count_r_reg(13),
      O => \verify_watchdog_r_reg[14]_srl15_i_4_n_0\
    );
\verify_watchdog_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \verify_watchdog_r_reg[14]_srl15_i_1_n_0\,
      D => \verify_watchdog_r_reg[14]_srl15_n_0\,
      Q => \verify_watchdog_r_reg_n_0_[15]\,
      R => '0'
    );
wait_for_lane_up_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => wait_for_lane_up_r0,
      Q => wait_for_lane_up_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE is
  port (
    begin_r0 : out STD_LOGIC;
    rx_hard_err_i : out STD_LOGIC;
    \SOFT_ERR_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    good_cnt_r3 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    hard_err_gt0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    enable_err_detect_i : in STD_LOGIC;
    \soft_err_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE : entity is "aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE is
  signal cnt_good_code_r : STD_LOGIC;
  signal cnt_good_code_r_i_3_n_0 : STD_LOGIC;
  signal cnt_good_code_r_i_4_n_0 : STD_LOGIC;
  signal cnt_soft_err_r : STD_LOGIC;
  signal err_cnt_r : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \err_cnt_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \err_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \err_cnt_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \err_cnt_r[2]_i_2_n_0\ : STD_LOGIC;
  signal \good_cnt_r[3]_i_1_n_0\ : STD_LOGIC;
  signal good_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal hard_err_frm_soft_err : STD_LOGIC;
  signal hard_err_gt : STD_LOGIC;
  signal next_good_code_c : STD_LOGIC;
  signal next_soft_err_c : STD_LOGIC;
  signal next_start_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_out : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \soft_err_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \soft_err_r_reg_n_0_[3]\ : STD_LOGIC;
  signal start_r : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \SOFT_ERR_Buffer[0]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of align_r_i_1 : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of cnt_good_code_r_i_3 : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of cnt_good_code_r_i_4 : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \err_cnt_r[1]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \err_cnt_r[2]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \err_cnt_r[2]_i_2\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \good_cnt_r[0]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \good_cnt_r[1]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \good_cnt_r[2]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \good_cnt_r[3]_i_2\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of hard_err_r_i_1 : label is "soft_lutpair3";
begin
\SOFT_ERR_Buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_2_in,
      I1 => \soft_err_r_reg_n_0_[0]\,
      O => p_3_out(1)
    );
\SOFT_ERR_Buffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \soft_err_r_reg_n_0_[3]\,
      I1 => p_1_in,
      O => p_3_out(0)
    );
\SOFT_ERR_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_3_out(1),
      Q => \SOFT_ERR_Buffer_reg[0]_0\(1),
      R => '0'
    );
\SOFT_ERR_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_3_out(0),
      Q => \SOFT_ERR_Buffer_reg[0]_0\(0),
      R => '0'
    );
align_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => SR(0),
      I1 => p_0_in,
      I2 => hard_err_frm_soft_err,
      I3 => hard_err_gt,
      O => begin_r0
    );
cnt_good_code_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA2A00"
    )
        port map (
      I0 => cnt_good_code_r_i_3_n_0,
      I1 => cnt_good_code_r_i_4_n_0,
      I2 => good_cnt_r_reg(3),
      I3 => cnt_good_code_r,
      I4 => cnt_soft_err_r,
      O => next_good_code_c
    );
cnt_good_code_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \soft_err_r_reg_n_0_[0]\,
      I1 => p_2_in,
      I2 => p_1_in,
      I3 => \soft_err_r_reg_n_0_[3]\,
      O => cnt_good_code_r_i_3_n_0
    );
cnt_good_code_r_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => good_cnt_r_reg(2),
      I1 => good_cnt_r_reg(1),
      I2 => good_cnt_r_reg(0),
      O => cnt_good_code_r_i_4_n_0
    );
cnt_good_code_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_good_code_c,
      Q => cnt_good_code_r,
      R => good_cnt_r3
    );
cnt_soft_err_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => cnt_soft_err_r,
      I1 => start_r,
      I2 => cnt_good_code_r,
      I3 => cnt_good_code_r_i_3_n_0,
      O => next_soft_err_c
    );
cnt_soft_err_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_soft_err_c,
      Q => cnt_soft_err_r,
      R => good_cnt_r3
    );
\err_cnt_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BEBE4140"
    )
        port map (
      I0 => p_0_in,
      I1 => \err_cnt_r[2]_i_2_n_0\,
      I2 => cnt_soft_err_r,
      I3 => err_cnt_r(1),
      I4 => err_cnt_r(0),
      O => \err_cnt_r[0]_i_1_n_0\
    );
\err_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCC6CC8"
    )
        port map (
      I0 => err_cnt_r(0),
      I1 => err_cnt_r(1),
      I2 => cnt_soft_err_r,
      I3 => \err_cnt_r[2]_i_2_n_0\,
      I4 => p_0_in,
      O => \err_cnt_r[1]_i_1_n_0\
    );
\err_cnt_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF8000"
    )
        port map (
      I0 => err_cnt_r(0),
      I1 => err_cnt_r(1),
      I2 => cnt_soft_err_r,
      I3 => \err_cnt_r[2]_i_2_n_0\,
      I4 => p_0_in,
      O => \err_cnt_r[2]_i_1_n_0\
    );
\err_cnt_r[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF1"
    )
        port map (
      I0 => good_cnt_r_reg(3),
      I1 => good_cnt_r_reg(2),
      I2 => good_cnt_r_reg(1),
      I3 => good_cnt_r_reg(0),
      O => \err_cnt_r[2]_i_2_n_0\
    );
\err_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \err_cnt_r[0]_i_1_n_0\,
      Q => err_cnt_r(0),
      R => good_cnt_r3
    );
\err_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \err_cnt_r[1]_i_1_n_0\,
      Q => err_cnt_r(1),
      R => good_cnt_r3
    );
\err_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \err_cnt_r[2]_i_1_n_0\,
      Q => p_0_in,
      R => good_cnt_r3
    );
\good_cnt_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => good_cnt_r_reg(0),
      O => plusOp(0)
    );
\good_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => good_cnt_r_reg(0),
      I1 => good_cnt_r_reg(1),
      O => plusOp(1)
    );
\good_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => good_cnt_r_reg(0),
      I1 => good_cnt_r_reg(1),
      I2 => good_cnt_r_reg(2),
      O => plusOp(2)
    );
\good_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => start_r,
      I1 => cnt_soft_err_r,
      I2 => enable_err_detect_i,
      I3 => cnt_good_code_r,
      O => \good_cnt_r[3]_i_1_n_0\
    );
\good_cnt_r[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => good_cnt_r_reg(3),
      I1 => good_cnt_r_reg(0),
      I2 => good_cnt_r_reg(1),
      I3 => good_cnt_r_reg(2),
      O => plusOp(3)
    );
\good_cnt_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => plusOp(0),
      Q => good_cnt_r_reg(0),
      R => \good_cnt_r[3]_i_1_n_0\
    );
\good_cnt_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => plusOp(1),
      Q => good_cnt_r_reg(1),
      R => \good_cnt_r[3]_i_1_n_0\
    );
\good_cnt_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => plusOp(2),
      Q => good_cnt_r_reg(2),
      R => \good_cnt_r[3]_i_1_n_0\
    );
\good_cnt_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => plusOp(3),
      Q => good_cnt_r_reg(3),
      R => \good_cnt_r[3]_i_1_n_0\
    );
hard_err_frm_soft_err_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in,
      Q => hard_err_frm_soft_err,
      R => good_cnt_r3
    );
hard_err_gt_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_gt0,
      Q => hard_err_gt,
      R => good_cnt_r3
    );
hard_err_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => hard_err_gt,
      I1 => hard_err_frm_soft_err,
      I2 => p_0_in,
      O => rx_hard_err_i
    );
\soft_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(3),
      Q => \soft_err_r_reg_n_0_[0]\,
      R => '0'
    );
\soft_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(2),
      Q => p_2_in,
      R => '0'
    );
\soft_err_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(1),
      Q => p_1_in,
      R => '0'
    );
\soft_err_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(0),
      Q => \soft_err_r_reg_n_0_[3]\,
      R => '0'
    );
start_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => cnt_good_code_r_i_3_n_0,
      I1 => start_r,
      I2 => cnt_good_code_r_i_4_n_0,
      I3 => good_cnt_r_reg(3),
      I4 => cnt_good_code_r,
      O => next_start_c
    );
start_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_start_c,
      Q => start_r,
      S => good_cnt_r3
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE is
  port (
    RX_LANE_UP : out STD_LOGIC;
    align_r_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    begin_r : out STD_LOGIC;
    enable_err_detect_i : out STD_LOGIC;
    rx_polarity_i : out STD_LOGIC;
    good_cnt_r3 : out STD_LOGIC;
    ready_r_reg_0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    begin_r0 : in STD_LOGIC;
    inc_count_r0 : in STD_LOGIC;
    begin_r_reg_0 : in STD_LOGIC;
    RX_NEG_Buffer : in STD_LOGIC;
    reset_count_r_reg_0 : in STD_LOGIC;
    reset_count_r_reg_1 : in STD_LOGIC;
    RX_CHANNEL_UP : in STD_LOGIC;
    rx_sp_i : in STD_LOGIC;
    RXCHARISK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE : entity is "aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE is
  signal D : STD_LOGIC;
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^align_r_reg_0\ : STD_LOGIC;
  signal \^begin_r\ : STD_LOGIC;
  signal counter1_r0 : STD_LOGIC;
  signal \counter1_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \counter1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal counter2_r0 : STD_LOGIC;
  signal \counter2_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \counter2_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \^enable_err_detect_i\ : STD_LOGIC;
  signal gtx_rx_reset_i : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_begin_c : STD_LOGIC;
  signal next_polarity_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_realign_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal polarity_r : STD_LOGIC;
  signal realign_r : STD_LOGIC;
  signal reset_count_r : STD_LOGIC;
  signal reset_count_r0 : STD_LOGIC;
  signal \^rx_polarity_i\ : STD_LOGIC;
  signal rx_polarity_r_i_1_n_0 : STD_LOGIC;
  signal std_bool : STD_LOGIC;
  signal std_bool0_in : STD_LOGIC;
  signal std_bool0_in3_in : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of align_r_i_2 : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \counter1_r[0]_i_3\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \counter1_r[3]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \counter1_r[4]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \counter1_r[5]_i_1\ : label is "soft_lutpair9";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \counter2_r_reg[14]_srl15\ : label is "U0/\aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/counter2_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \counter2_r_reg[14]_srl15\ : label is "U0/\aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/counter2_r_reg[14]_srl15 ";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute SOFT_HLUTNM of polarity_r_i_1 : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of realign_r_i_1 : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of rst_r_i_1 : label is "soft_lutpair8";
begin
  E(0) <= \^e\(0);
  align_r_reg_0 <= \^align_r_reg_0\;
  begin_r <= \^begin_r\;
  enable_err_detect_i <= \^enable_err_detect_i\;
  rx_polarity_i <= \^rx_polarity_i\;
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => \^enable_err_detect_i\,
      R => '0'
    );
align_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => std_bool0_in,
      I2 => std_bool0_in3_in,
      I3 => gtx_rx_reset_i,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => \^align_r_reg_0\,
      R => begin_r0
    );
begin_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => realign_r,
      I1 => begin_r_reg_0,
      I2 => D,
      I3 => \counter2_r_reg_n_0_[15]\,
      I4 => polarity_r,
      I5 => RX_NEG_Buffer,
      O => next_begin_c
    );
begin_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_begin_c,
      Q => \^begin_r\,
      S => begin_r0
    );
cnt_good_code_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^enable_err_detect_i\,
      O => good_cnt_r3
    );
\counter1_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => D,
      I1 => reset_count_r,
      O => counter1_r0
    );
\counter1_r[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool0_in,
      I1 => std_bool,
      I2 => std_bool0_in3_in,
      I3 => \counter1_r[0]_i_3_n_0\,
      I4 => \counter1_r_reg_n_0_[3]\,
      I5 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(7)
    );
\counter1_r[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[5]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[7]\,
      O => \counter1_r[0]_i_3_n_0\
    );
\counter1_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[1]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r[0]_i_3_n_0\,
      I3 => std_bool0_in3_in,
      I4 => std_bool,
      O => p_0_in(6)
    );
\counter1_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool,
      I1 => std_bool0_in3_in,
      I2 => \counter1_r_reg_n_0_[7]\,
      I3 => \counter1_r_reg_n_0_[6]\,
      I4 => \counter1_r_reg_n_0_[5]\,
      I5 => \counter1_r_reg_n_0_[3]\,
      O => \counter1_r[2]_i_1_n_0\
    );
\counter1_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[5]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[7]\,
      I4 => std_bool0_in3_in,
      O => p_0_in(4)
    );
\counter1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => std_bool0_in3_in,
      I1 => \counter1_r_reg_n_0_[7]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(3)
    );
\counter1_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(2)
    );
\counter1_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      O => p_0_in(1)
    );
\counter1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => p_0_in(7),
      Q => std_bool0_in,
      R => counter1_r0
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => p_0_in(6),
      Q => \counter1_r_reg_n_0_[1]\,
      R => counter1_r0
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => \counter1_r[2]_i_1_n_0\,
      Q => std_bool,
      R => counter1_r0
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => p_0_in(4),
      Q => \counter1_r_reg_n_0_[3]\,
      R => counter1_r0
    );
\counter1_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => p_0_in(3),
      Q => std_bool0_in3_in,
      R => counter1_r0
    );
\counter1_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[5]\,
      R => counter1_r0
    );
\counter1_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[6]\,
      R => counter1_r0
    );
\counter1_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[7]\,
      S => counter1_r0
    );
\counter2_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => counter2_r0,
      CLK => user_clk,
      D => D,
      Q => \counter2_r_reg[14]_srl15_n_0\
    );
\counter2_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => D,
      I1 => RX_CHANNEL_UP,
      I2 => rx_sp_i,
      O => counter2_r0
    );
\counter2_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => counter2_r0,
      D => \counter2_r_reg[14]_srl15_n_0\,
      Q => \counter2_r_reg_n_0_[15]\,
      R => '0'
    );
inc_count_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => inc_count_r0,
      Q => \^e\(0),
      R => '0'
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => RX_LANE_UP,
      R => SR(0)
    );
\left_align_select_r[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF888F"
    )
        port map (
      I0 => RXCHARISK(1),
      I1 => RXCHARISK(0),
      I2 => D,
      I3 => \^align_r_reg_0\,
      I4 => first_v_received_r,
      O => ready_r_reg_0
    );
polarity_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => std_bool,
      I1 => realign_r,
      I2 => begin_r_reg_0,
      O => next_polarity_c
    );
polarity_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_polarity_c,
      Q => polarity_r,
      R => begin_r0
    );
ready_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \counter2_r_reg_n_0_[15]\,
      I1 => D,
      I2 => RX_NEG_Buffer,
      I3 => polarity_r,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D,
      R => begin_r0
    );
realign_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040404"
    )
        port map (
      I0 => begin_r_reg_0,
      I1 => realign_r,
      I2 => std_bool,
      I3 => std_bool0_in,
      I4 => \^align_r_reg_0\,
      O => next_realign_c
    );
realign_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_realign_c,
      Q => realign_r,
      R => begin_r0
    );
reset_count_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0F00BBBB"
    )
        port map (
      I0 => reset_count_r_reg_0,
      I1 => reset_count_r_reg_1,
      I2 => \^begin_r\,
      I3 => std_bool0_in3_in,
      I4 => gtx_rx_reset_i,
      I5 => SR(0),
      O => reset_count_r0
    );
reset_count_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => reset_count_r0,
      Q => reset_count_r,
      R => '0'
    );
rst_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^begin_r\,
      I1 => std_bool0_in3_in,
      I2 => gtx_rx_reset_i,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => gtx_rx_reset_i,
      R => begin_r0
    );
rx_polarity_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RX_NEG_Buffer,
      I1 => polarity_r,
      I2 => \^rx_polarity_i\,
      O => rx_polarity_r_i_1_n_0
    );
rx_polarity_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_polarity_r_i_1_n_0,
      Q => \^rx_polarity_i\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_DEFRAMER is
  port (
    mux_select_c : out STD_LOGIC_VECTOR ( 0 to 0 );
    \AFTER_SCP_Buffer_reg[0]_0\ : out STD_LOGIC;
    \AFTER_SCP_Buffer_reg[0]_1\ : out STD_LOGIC;
    \AFTER_SCP_Buffer_reg[0]_2\ : out STD_LOGIC;
    \DEFRAMED_DATA_V_Buffer_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \stage_1_ecp_r_reg[0]\ : out STD_LOGIC;
    \IN_FRAME_Buffer_reg[1]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    in_frame_r_reg_0 : in STD_LOGIC;
    S1_in : in STD_LOGIC;
    \AFTER_SCP_Buffer_reg[1]_0\ : in STD_LOGIC;
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    stage_2_frame_err_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \DEFRAMED_DATA_V_Buffer_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_DEFRAMER : entity is "aurora_1ln_rx_lpm_RX_LL_DEFRAMER";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_DEFRAMER;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_DEFRAMER is
  signal CI : STD_LOGIC;
  signal \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal after_scp_c_1 : STD_LOGIC;
  signal data_after_start_muxcy_1_n_0 : STD_LOGIC;
  signal in_frame_c_0 : STD_LOGIC;
  signal in_frame_c_1 : STD_LOGIC;
  signal stage_1_after_scp_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal stage_1_data_v_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal stage_1_in_frame_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \COUNT_Buffer[0]_i_1\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \COUNT_Buffer[1]_i_1\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \MUX_SELECT_Buffer[2]_i_1\ : label is "soft_lutpair44";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of data_after_start_muxcy_0_CARRY4 : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of data_after_start_muxcy_0_CARRY4 : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_after_start_muxcy_0_CARRY4 : label is "(MUXCY,XORCY)";
  attribute BOX_TYPE of in_frame_muxcy_0_CARRY4 : label is "PRIMITIVE";
  attribute OPT_MODIFIED of in_frame_muxcy_0_CARRY4 : label is "MLO";
  attribute XILINX_LEGACY_PRIM of in_frame_muxcy_0_CARRY4 : label is "(MUXCY,XORCY)";
  attribute SOFT_HLUTNM of stage_2_end_after_start_r_i_1 : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of stage_2_end_before_start_r_i_1 : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of stage_2_start_with_data_r_i_1 : label is "soft_lutpair44";
begin
\AFTER_SCP_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => after_scp_c_1,
      Q => stage_1_after_scp_r(0),
      R => RESET
    );
\AFTER_SCP_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => data_after_start_muxcy_1_n_0,
      Q => stage_1_after_scp_r(1),
      R => RESET
    );
\COUNT_Buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => stage_1_data_v_r(1),
      I1 => stage_1_data_v_r(0),
      O => \DEFRAMED_DATA_V_Buffer_reg[1]_0\(1)
    );
\COUNT_Buffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => stage_1_data_v_r(0),
      I1 => stage_1_data_v_r(1),
      O => \DEFRAMED_DATA_V_Buffer_reg[1]_0\(0)
    );
\DEFRAMED_DATA_V_Buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => in_frame_c_1,
      I1 => \DEFRAMED_DATA_V_Buffer_reg[0]_0\(1),
      O => \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0\
    );
\DEFRAMED_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => in_frame_c_0,
      I1 => \DEFRAMED_DATA_V_Buffer_reg[0]_0\(0),
      O => \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0\
    );
\DEFRAMED_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0\,
      Q => stage_1_data_v_r(0),
      R => RESET
    );
\DEFRAMED_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0\,
      Q => stage_1_data_v_r(1),
      R => RESET
    );
\IN_FRAME_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => CI,
      Q => stage_1_in_frame_r(0),
      R => RESET
    );
\IN_FRAME_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => in_frame_c_1,
      Q => stage_1_in_frame_r(1),
      R => RESET
    );
\MUX_SELECT_Buffer[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => stage_1_data_v_r(1),
      I1 => stage_1_data_v_r(0),
      O => mux_select_c(0)
    );
data_after_start_muxcy_0_CARRY4: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3 downto 2) => NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED(3 downto 2),
      CO(1) => data_after_start_muxcy_1_n_0,
      CO(0) => after_scp_c_1,
      CYINIT => '0',
      DI(3 downto 2) => NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED(3 downto 2),
      DI(1 downto 0) => B"11",
      O(3 downto 0) => NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED(3 downto 2),
      S(1) => \AFTER_SCP_Buffer_reg[1]_0\,
      S(0) => S1_in
    );
in_frame_muxcy_0_CARRY4: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3 downto 2) => NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED(3 downto 2),
      CO(1) => in_frame_c_0,
      CO(0) => in_frame_c_1,
      CYINIT => CI,
      DI(3 downto 2) => NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED(3 downto 2),
      DI(1) => D(0),
      DI(0) => D(1),
      O(3 downto 0) => NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED(3 downto 2),
      S(1) => in_frame_r_reg_0,
      S(0) => \IN_FRAME_Buffer_reg[1]_0\
    );
in_frame_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => in_frame_c_0,
      Q => CI,
      R => RESET
    );
stage_2_end_after_start_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => stage_1_after_scp_r(0),
      I1 => Q(1),
      I2 => stage_1_after_scp_r(1),
      I3 => Q(0),
      O => \AFTER_SCP_Buffer_reg[0]_2\
    );
stage_2_end_before_start_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stage_1_after_scp_r(0),
      I1 => Q(1),
      I2 => stage_1_after_scp_r(1),
      I3 => Q(0),
      O => \AFTER_SCP_Buffer_reg[0]_1\
    );
stage_2_frame_err_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF0AAFCEEFCEE"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => stage_2_frame_err_r_reg(1),
      I3 => stage_1_in_frame_r(0),
      I4 => stage_2_frame_err_r_reg(0),
      I5 => stage_1_in_frame_r(1),
      O => \stage_1_ecp_r_reg[0]\
    );
stage_2_start_with_data_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => stage_1_after_scp_r(0),
      I1 => stage_1_data_v_r(0),
      I2 => stage_1_after_scp_r(1),
      I3 => stage_1_data_v_r(1),
      O => \AFTER_SCP_Buffer_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SIDEBAND_OUTPUT is
  port (
    SRC_RDY_N_Buffer : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    EOF_N_Buffer : out STD_LOGIC;
    stage_3_end_storage_r : out STD_LOGIC;
    FRAME_ERR_RESULT_Buffer : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_REM_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC;
    EOF_N_Buffer_reg_0 : in STD_LOGIC;
    end_storage_r0 : in STD_LOGIC;
    FRAME_ERR_RESULT_Buffer0 : in STD_LOGIC;
    stage_2_start_with_data_r : in STD_LOGIC;
    stage_2_pad_r : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_REM_Buffer_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    std_bool6_in : in STD_LOGIC;
    stage_2_end_before_start_r : in STD_LOGIC;
    stage_2_frame_err_r : in STD_LOGIC;
    START_RX : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SIDEBAND_OUTPUT : entity is "aurora_1ln_rx_lpm_SIDEBAND_OUTPUT";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SIDEBAND_OUTPUT;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SIDEBAND_OUTPUT is
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal SRC_RDY_N_Buffer_i_2_n_0 : STD_LOGIC;
  signal pad_storage_r : STD_LOGIC;
  signal pad_storage_r_i_1_n_0 : STD_LOGIC;
  signal rx_rem_c : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^stage_3_end_storage_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \RX_REM_Buffer[0]_i_1\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \storage_count_r[1]_i_1\ : label is "soft_lutpair42";
begin
  SR(0) <= \^sr\(0);
  stage_3_end_storage_r <= \^stage_3_end_storage_r\;
EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EOF_N_Buffer_reg_0,
      Q => EOF_N_Buffer,
      R => '0'
    );
FRAME_ERR_RESULT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => FRAME_ERR_RESULT_Buffer0,
      Q => FRAME_ERR_RESULT_Buffer,
      R => '0'
    );
\RX_REM_Buffer[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1E0F"
    )
        port map (
      I0 => \^stage_3_end_storage_r\,
      I1 => stage_2_start_with_data_r,
      I2 => Q(0),
      I3 => \RX_REM_Buffer_reg[0]_1\(0),
      O => rx_rem_c(1)
    );
\RX_REM_Buffer[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EF"
    )
        port map (
      I0 => \^stage_3_end_storage_r\,
      I1 => stage_2_start_with_data_r,
      I2 => stage_2_pad_r,
      I3 => pad_storage_r,
      O => rx_rem_c(0)
    );
\RX_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_rem_c(1),
      Q => \RX_REM_Buffer_reg[0]_0\(1),
      R => '0'
    );
\RX_REM_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_rem_c(0),
      Q => \RX_REM_Buffer_reg[0]_0\(0),
      R => '0'
    );
SRC_RDY_N_Buffer_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => stage_2_frame_err_r,
      I1 => START_RX,
      O => \^sr\(0)
    );
SRC_RDY_N_Buffer_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0145"
    )
        port map (
      I0 => \^stage_3_end_storage_r\,
      I1 => stage_2_start_with_data_r,
      I2 => std_bool6_in,
      I3 => stage_2_end_before_start_r,
      O => SRC_RDY_N_Buffer_i_2_n_0
    );
SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => SRC_RDY_N_Buffer_i_2_n_0,
      Q => SRC_RDY_N_Buffer,
      S => \^sr\(0)
    );
end_storage_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => end_storage_r0,
      Q => \^stage_3_end_storage_r\,
      R => \^sr\(0)
    );
pad_storage_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAABBABBAAAAAAAA"
    )
        port map (
      I0 => stage_2_pad_r,
      I1 => \^stage_3_end_storage_r\,
      I2 => stage_2_start_with_data_r,
      I3 => std_bool6_in,
      I4 => stage_2_end_before_start_r,
      I5 => pad_storage_r,
      O => pad_storage_r_i_1_n_0
    );
pad_storage_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => pad_storage_r_i_1_n_0,
      Q => pad_storage_r,
      R => \^sr\(0)
    );
\storage_count_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E1F0"
    )
        port map (
      I0 => \^stage_3_end_storage_r\,
      I1 => stage_2_start_with_data_r,
      I2 => \RX_REM_Buffer_reg[0]_1\(0),
      I3 => Q(0),
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_CE_CONTROL is
  port (
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    RESET : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_CE_CONTROL : entity is "aurora_1ln_rx_lpm_STORAGE_CE_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_CE_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_CE_CONTROL is
begin
\STORAGE_CE_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => RESET
    );
\STORAGE_CE_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL is
  port (
    output_select_c : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    FRAME_ERR_RESULT_Buffer0 : out STD_LOGIC;
    end_storage_r_reg : out STD_LOGIC;
    stage_2_start_with_data_r : in STD_LOGIC;
    stage_3_end_storage_r : in STD_LOGIC;
    stage_2_frame_err_r : in STD_LOGIC;
    stage_2_end_after_start_r : in STD_LOGIC;
    stage_2_end_before_start_r : in STD_LOGIC;
    std_bool2_in : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL : entity is "aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \sideband_output_i/std_bool\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EOF_N_Buffer_i_1 : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \OUTPUT_SELECT_Buffer[9]_i_1\ : label is "soft_lutpair71";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
EOF_N_Buffer_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"15151555"
    )
        port map (
      I0 => stage_3_end_storage_r,
      I1 => stage_2_end_before_start_r,
      I2 => stage_2_start_with_data_r,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => end_storage_r_reg
    );
FRAME_ERR_RESULT_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDFFCCFCDDFCCCFC"
    )
        port map (
      I0 => \sideband_output_i/std_bool\,
      I1 => stage_2_frame_err_r,
      I2 => stage_2_end_after_start_r,
      I3 => stage_2_start_with_data_r,
      I4 => stage_2_end_before_start_r,
      I5 => std_bool2_in,
      O => FRAME_ERR_RESULT_Buffer0
    );
FRAME_ERR_RESULT_Buffer_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \sideband_output_i/std_bool\
    );
\OUTPUT_SELECT_Buffer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(1),
      I1 => stage_2_start_with_data_r,
      I2 => stage_3_end_storage_r,
      O => output_select_c(0)
    );
\storage_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => \^q\(1),
      R => SR(0)
    );
\storage_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \^q\(0),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_MUX is
  port (
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    E : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 31 downto 0 );
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_MUX : entity is "aurora_1ln_rx_lpm_STORAGE_MUX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_MUX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_MUX is
begin
\STORAGE_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(31),
      Q => Q(31),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(21),
      Q => Q(21),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(20),
      Q => Q(20),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(19),
      Q => Q(19),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(18),
      Q => Q(18),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(17),
      Q => Q(17),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(16),
      Q => Q(16),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(15),
      Q => Q(15),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(14),
      Q => Q(14),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(13),
      Q => Q(13),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(12),
      Q => Q(12),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(30),
      Q => Q(30),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(11),
      Q => Q(11),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(10),
      Q => Q(10),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(9),
      Q => Q(9),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(8),
      Q => Q(8),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(7),
      Q => Q(7),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(6),
      Q => Q(6),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(5),
      Q => Q(5),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(4),
      Q => Q(4),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(3),
      Q => Q(3),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(2),
      Q => Q(2),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(29),
      Q => Q(29),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(0),
      Q => Q(0),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(28),
      Q => Q(28),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(27),
      Q => Q(27),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(26),
      Q => Q(26),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(25),
      Q => Q(25),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(24),
      Q => Q(24),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(23),
      Q => Q(23),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(22),
      Q => Q(22),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL is
  port (
    STORAGE_SELECT_Buffer : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    stage_2_start_with_data_r : in STD_LOGIC;
    stage_3_end_storage_r : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL : entity is "aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL is
  signal \STORAGE_SELECT_Buffer[4]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_SELECT_Buffer[9]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \STORAGE_SELECT_Buffer[4]_i_1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \STORAGE_SELECT_Buffer[9]_i_1\ : label is "soft_lutpair72";
begin
\STORAGE_SELECT_Buffer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => Q(0),
      I1 => stage_2_start_with_data_r,
      I2 => stage_3_end_storage_r,
      O => \STORAGE_SELECT_Buffer[4]_i_1_n_0\
    );
\STORAGE_SELECT_Buffer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => Q(0),
      I1 => stage_2_start_with_data_r,
      I2 => stage_3_end_storage_r,
      O => \STORAGE_SELECT_Buffer[9]_i_1_n_0\
    );
\STORAGE_SELECT_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \STORAGE_SELECT_Buffer[4]_i_1_n_0\,
      Q => STORAGE_SELECT_Buffer(1),
      R => '0'
    );
\STORAGE_SELECT_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \STORAGE_SELECT_Buffer[9]_i_1_n_0\,
      Q => STORAGE_SELECT_Buffer(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SYM_DEC_4BYTE is
  port (
    RX_NEG_Buffer : out STD_LOGIC;
    rx_sp_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    GOT_V : out STD_LOGIC;
    RX_PE_DATA : out STD_LOGIC_VECTOR ( 5 downto 0 );
    first_v_received_r : out STD_LOGIC;
    \left_align_select_r_reg[1]_0\ : out STD_LOGIC;
    \left_align_select_r_reg[0]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    neqOp : out STD_LOGIC;
    \RX_SUF_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \RX_PE_DATA_Buffer_reg[26]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[26]_1\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[25]_0\ : out STD_LOGIC;
    \RX_SUF_Buffer_reg[1]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[27]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[16]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \RX_PE_DATA_V_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    p_9_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    p_8_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    p_2_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[3]_0\ : in STD_LOGIC;
    RXDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    RXCHARISK : in STD_LOGIC_VECTOR ( 3 downto 0 );
    RX_LANE_UP : in STD_LOGIC;
    \left_align_select_r_reg[0]_1\ : in STD_LOGIC;
    \word_aligned_data_r_reg[24]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[16]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SYM_DEC_4BYTE : entity is "aurora_1ln_rx_lpm_SYM_DEC_4BYTE";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SYM_DEC_4BYTE;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SYM_DEC_4BYTE is
  signal \EXP_IN_inferred__0/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__1/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__10/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__11/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__12/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__13/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__14/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__15/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__16/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__17/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__18/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__19/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__2/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__20/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__21/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__22/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__23/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__24/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__25/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__26/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__3/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__34/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__35/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__4/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__44/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__45/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__46/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__47/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__5/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__6/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__8/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__9/i__n_0\ : STD_LOGIC;
  signal EXP_IN_n_0 : STD_LOGIC;
  signal GOT_V_Buffer_i_2_n_0 : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal RX_CC_Buffer_i_1_n_0 : STD_LOGIC;
  signal RX_CC_Buffer_i_2_n_0 : STD_LOGIC;
  signal RX_CC_Buffer_i_3_n_0 : STD_LOGIC;
  signal RX_NEG_Buffer0 : STD_LOGIC;
  signal \^rx_pe_data\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \RX_PE_DATA_V_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \RX_PE_DATA_V_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal RX_SP_Buffer_i_2_n_0 : STD_LOGIC;
  signal RX_SP_Buffer_i_3_n_0 : STD_LOGIC;
  signal \^rx_suf_buffer_reg[0]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^first_v_received_r\ : STD_LOGIC;
  signal first_v_received_r_i_1_n_0 : STD_LOGIC;
  signal \left_align_select_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \left_align_select_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \^left_align_select_r_reg[0]_0\ : STD_LOGIC;
  signal \^left_align_select_r_reg[1]_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal p_0_in14_in : STD_LOGIC;
  signal p_0_in18_in : STD_LOGIC;
  signal p_0_in26_in : STD_LOGIC;
  signal p_0_in28_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_1_in29_in : STD_LOGIC;
  signal p_21_in : STD_LOGIC;
  signal p_2_in30_in : STD_LOGIC;
  signal p_32_in : STD_LOGIC;
  signal p_3_in : STD_LOGIC;
  signal p_5_out : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_6_in22_in : STD_LOGIC;
  signal p_6_in34_in : STD_LOGIC;
  signal previous_cycle_control_r : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal previous_cycle_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal rx_cc_r : STD_LOGIC_VECTOR ( 1 to 7 );
  signal \rx_ecp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rx_ecp_d_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \rx_ecp_d_r_reg_n_0_[7]\ : STD_LOGIC;
  signal rx_pad_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \rx_pe_control_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_pe_data_r : STD_LOGIC_VECTOR ( 8 to 26 );
  signal \rx_scp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rx_scp_d_r_reg_n_0_[7]\ : STD_LOGIC;
  signal rx_sp_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal rx_sp_r : STD_LOGIC_VECTOR ( 0 to 7 );
  signal \rx_sp_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \rx_sp_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \rx_sp_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \rx_sp_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \rx_sp_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \rx_sp_r[7]_i_1_n_0\ : STD_LOGIC;
  signal rx_spa_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal rx_v_d_r : STD_LOGIC_VECTOR ( 2 to 7 );
  signal std_bool13_in : STD_LOGIC;
  signal std_bool13_out : STD_LOGIC;
  signal std_bool16_in : STD_LOGIC;
  signal std_bool1_out : STD_LOGIC;
  signal word_aligned_control_bits_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \word_aligned_control_bits_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_control_bits_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_control_bits_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[10]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[11]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[12]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[13]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[14]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[15]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[17]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[19]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[21]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[23]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[4]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[5]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[6]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[7]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[8]_i_1_n_0\ : STD_LOGIC;
  signal \word_aligned_data_r[9]_i_1_n_0\ : STD_LOGIC;
  signal \^word_aligned_data_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^word_aligned_data_r_reg[11]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^word_aligned_data_r_reg[16]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^word_aligned_data_r_reg[27]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \word_aligned_data_r_reg_n_0_[24]\ : STD_LOGIC;
  signal \word_aligned_data_r_reg_n_0_[25]\ : STD_LOGIC;
  signal \word_aligned_data_r_reg_n_0_[26]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EXP_IN : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__0/i_\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__1/i_\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__10/i_\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__11/i_\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__12/i_\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__13/i_\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__14/i_\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__15/i_\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__16/i_\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__17/i_\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__18/i_\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__19/i_\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__2/i_\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__20/i_\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__21/i_\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__22/i_\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__23/i_\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__24/i_\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__26/i_\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__27/i_\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__28/i_\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__3/i_\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__34/i_\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__35/i_\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__4/i_\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__44/i_\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__46/i_\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__5/i_\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__6/i_\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__8/i_\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__9/i_\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \RX_PE_DATA_V_Buffer[0]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \RX_PE_DATA_V_Buffer[1]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of RX_SP_Buffer_i_2 : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of load_ufc_control_code_r_i_1 : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \rx_pad_r_reg[1]_srl2_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \rx_sp_r[2]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \rx_sp_r[3]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \rx_sp_r[4]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \rx_sp_r[5]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \rx_sp_r[6]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \rx_sp_r[7]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \stage_1_count_value_r[2]_i_1\ : label is "soft_lutpair10";
begin
  Q(3 downto 0) <= \^q\(3 downto 0);
  RX_PE_DATA(5 downto 0) <= \^rx_pe_data\(5 downto 0);
  \RX_SUF_Buffer_reg[0]_0\(1 downto 0) <= \^rx_suf_buffer_reg[0]_0\(1 downto 0);
  first_v_received_r <= \^first_v_received_r\;
  \left_align_select_r_reg[0]_0\ <= \^left_align_select_r_reg[0]_0\;
  \left_align_select_r_reg[1]_0\ <= \^left_align_select_r_reg[1]_0\;
  \word_aligned_data_r_reg[0]_0\(7 downto 0) <= \^word_aligned_data_r_reg[0]_0\(7 downto 0);
  \word_aligned_data_r_reg[11]_0\(4 downto 0) <= \^word_aligned_data_r_reg[11]_0\(4 downto 0);
  \word_aligned_data_r_reg[16]_0\(7 downto 0) <= \^word_aligned_data_r_reg[16]_0\(7 downto 0);
  \word_aligned_data_r_reg[27]_0\(4 downto 0) <= \^word_aligned_data_r_reg[27]_0\(4 downto 0);
EXP_IN: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(2),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => EXP_IN_n_0
    );
\EXP_IN_inferred__0/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(7),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__0/i__n_0\
    );
\EXP_IN_inferred__1/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[27]_0\(2),
      I1 => \^word_aligned_data_r_reg[27]_0\(1),
      I2 => \^word_aligned_data_r_reg[27]_0\(3),
      I3 => \^word_aligned_data_r_reg[27]_0\(0),
      O => \EXP_IN_inferred__1/i__n_0\
    );
\EXP_IN_inferred__10/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(1),
      I1 => \^word_aligned_data_r_reg[11]_0\(0),
      I2 => \^word_aligned_data_r_reg[11]_0\(2),
      I3 => \^word_aligned_data_r_reg[11]_0\(3),
      O => \EXP_IN_inferred__10/i__n_0\
    );
\EXP_IN_inferred__11/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__11/i__n_0\
    );
\EXP_IN_inferred__12/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[27]_0\(2),
      I1 => \^word_aligned_data_r_reg[27]_0\(3),
      I2 => \^word_aligned_data_r_reg[27]_0\(1),
      I3 => \^word_aligned_data_r_reg[27]_0\(0),
      O => \EXP_IN_inferred__12/i__n_0\
    );
\EXP_IN_inferred__13/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \word_aligned_data_r_reg_n_0_[26]\,
      I1 => \^word_aligned_data_r_reg[27]_0\(4),
      I2 => \word_aligned_data_r_reg_n_0_[25]\,
      I3 => \word_aligned_data_r_reg_n_0_[24]\,
      O => \EXP_IN_inferred__13/i__n_0\
    );
\EXP_IN_inferred__14/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(1),
      I1 => \^word_aligned_data_r_reg[16]_0\(0),
      I2 => \^word_aligned_data_r_reg[16]_0\(2),
      I3 => \^word_aligned_data_r_reg[16]_0\(3),
      O => \EXP_IN_inferred__14/i__n_0\
    );
\EXP_IN_inferred__15/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(7),
      I1 => \^word_aligned_data_r_reg[16]_0\(5),
      I2 => \^word_aligned_data_r_reg[16]_0\(6),
      I3 => \^word_aligned_data_r_reg[16]_0\(4),
      O => \EXP_IN_inferred__15/i__n_0\
    );
\EXP_IN_inferred__16/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(3),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__16/i__n_0\
    );
\EXP_IN_inferred__17/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \^word_aligned_data_r_reg[11]_0\(4),
      I2 => p_0_in(2),
      I3 => p_0_in(3),
      O => \EXP_IN_inferred__17/i__n_0\
    );
\EXP_IN_inferred__18/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__18/i__n_0\
    );
\EXP_IN_inferred__19/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[27]_0\(0),
      I1 => \^word_aligned_data_r_reg[27]_0\(2),
      I2 => \^word_aligned_data_r_reg[27]_0\(3),
      I3 => \^word_aligned_data_r_reg[27]_0\(1),
      O => \EXP_IN_inferred__19/i__n_0\
    );
\EXP_IN_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[27]_0\(4),
      I1 => \word_aligned_data_r_reg_n_0_[25]\,
      I2 => \word_aligned_data_r_reg_n_0_[24]\,
      I3 => \word_aligned_data_r_reg_n_0_[26]\,
      O => \EXP_IN_inferred__2/i__n_0\
    );
\EXP_IN_inferred__20/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(1),
      I1 => \^word_aligned_data_r_reg[16]_0\(2),
      I2 => \^word_aligned_data_r_reg[16]_0\(3),
      I3 => \^word_aligned_data_r_reg[16]_0\(0),
      O => \EXP_IN_inferred__20/i__n_0\
    );
\EXP_IN_inferred__21/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(5),
      I1 => \^word_aligned_data_r_reg[16]_0\(4),
      I2 => \^word_aligned_data_r_reg[16]_0\(6),
      I3 => \^word_aligned_data_r_reg[16]_0\(7),
      O => \EXP_IN_inferred__21/i__n_0\
    );
\EXP_IN_inferred__22/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(0),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(1),
      O => \EXP_IN_inferred__22/i__n_0\
    );
\EXP_IN_inferred__23/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__23/i__n_0\
    );
\EXP_IN_inferred__24/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(5),
      I1 => \^word_aligned_data_r_reg[0]_0\(4),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(7),
      O => \EXP_IN_inferred__24/i__n_0\
    );
\EXP_IN_inferred__25/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(6),
      I1 => \^word_aligned_data_r_reg[16]_0\(5),
      I2 => \^word_aligned_data_r_reg[16]_0\(7),
      I3 => \^word_aligned_data_r_reg[16]_0\(4),
      O => \EXP_IN_inferred__25/i__n_0\
    );
\EXP_IN_inferred__26/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__26/i__n_0\
    );
\EXP_IN_inferred__27/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(3),
      I1 => \^word_aligned_data_r_reg[11]_0\(1),
      I2 => \^word_aligned_data_r_reg[11]_0\(2),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => std_bool13_in
    );
\EXP_IN_inferred__28/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(3),
      I2 => p_0_in(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => std_bool16_in
    );
\EXP_IN_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(2),
      I1 => \^word_aligned_data_r_reg[16]_0\(1),
      I2 => \^word_aligned_data_r_reg[16]_0\(3),
      I3 => \^word_aligned_data_r_reg[16]_0\(0),
      O => \EXP_IN_inferred__3/i__n_0\
    );
\EXP_IN_inferred__34/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(3),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__34/i__n_0\
    );
\EXP_IN_inferred__35/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__35/i__n_0\
    );
\EXP_IN_inferred__4/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(4),
      I1 => \^word_aligned_data_r_reg[16]_0\(6),
      I2 => \^word_aligned_data_r_reg[16]_0\(7),
      I3 => \^word_aligned_data_r_reg[16]_0\(5),
      O => \EXP_IN_inferred__4/i__n_0\
    );
\EXP_IN_inferred__44/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[27]_0\(3),
      I1 => \^word_aligned_data_r_reg[27]_0\(2),
      I2 => \^word_aligned_data_r_reg[27]_0\(1),
      I3 => \^word_aligned_data_r_reg[27]_0\(0),
      O => \EXP_IN_inferred__44/i__n_0\
    );
\EXP_IN_inferred__45/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(3),
      I1 => \^word_aligned_data_r_reg[16]_0\(2),
      I2 => \^word_aligned_data_r_reg[16]_0\(1),
      I3 => \^word_aligned_data_r_reg[16]_0\(0),
      O => \EXP_IN_inferred__45/i__n_0\
    );
\EXP_IN_inferred__46/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(3),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__46/i__n_0\
    );
\EXP_IN_inferred__47/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(3),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__47/i__n_0\
    );
\EXP_IN_inferred__5/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(1),
      I2 => \^word_aligned_data_r_reg[11]_0\(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__5/i__n_0\
    );
\EXP_IN_inferred__6/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(4),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => p_0_in(1),
      O => \EXP_IN_inferred__6/i__n_0\
    );
\EXP_IN_inferred__8/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[27]_0\(1),
      I1 => \^word_aligned_data_r_reg[27]_0\(0),
      I2 => \^word_aligned_data_r_reg[27]_0\(2),
      I3 => \^word_aligned_data_r_reg[27]_0\(3),
      O => \EXP_IN_inferred__8/i__n_0\
    );
\EXP_IN_inferred__9/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \word_aligned_data_r_reg_n_0_[25]\,
      I1 => \word_aligned_data_r_reg_n_0_[26]\,
      I2 => \word_aligned_data_r_reg_n_0_[24]\,
      I3 => \^word_aligned_data_r_reg[27]_0\(4),
      O => \EXP_IN_inferred__9/i__n_0\
    );
GOT_V_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000000000"
    )
        port map (
      I0 => RX_SP_Buffer_i_2_n_0,
      I1 => GOT_V_Buffer_i_2_n_0,
      I2 => rx_sp_r(0),
      I3 => rx_sp_r(1),
      I4 => rx_v_d_r(3),
      I5 => rx_v_d_r(2),
      O => std_bool1_out
    );
GOT_V_Buffer_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => rx_v_d_r(5),
      I1 => rx_v_d_r(4),
      I2 => rx_v_d_r(7),
      I3 => rx_v_d_r(6),
      O => GOT_V_Buffer_i_2_n_0
    );
GOT_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool1_out,
      Q => GOT_V,
      R => '0'
    );
RX_CC_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => p_1_in,
      I1 => \rx_pe_control_r_reg_n_0_[3]\,
      I2 => p_3_in,
      I3 => p_0_in26_in,
      I4 => RX_CC_Buffer_i_2_n_0,
      I5 => RX_CC_Buffer_i_3_n_0,
      O => RX_CC_Buffer_i_1_n_0
    );
RX_CC_Buffer_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => rx_cc_r(5),
      I1 => p_0_in18_in,
      I2 => rx_cc_r(7),
      I3 => p_2_in30_in,
      O => RX_CC_Buffer_i_2_n_0
    );
RX_CC_Buffer_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => p_21_in,
      I1 => rx_cc_r(1),
      I2 => rx_cc_r(3),
      I3 => p_6_in34_in,
      O => RX_CC_Buffer_i_3_n_0
    );
RX_CC_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_CC_Buffer_i_1_n_0,
      Q => D(0),
      R => '0'
    );
RX_NEG_Buffer_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F888"
    )
        port map (
      I0 => rx_spa_neg_d_r(1),
      I1 => rx_spa_neg_d_r(0),
      I2 => rx_sp_neg_d_r(1),
      I3 => rx_sp_neg_d_r(0),
      I4 => p_0_in26_in,
      O => RX_NEG_Buffer0
    );
RX_NEG_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_NEG_Buffer0,
      Q => RX_NEG_Buffer,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(10),
      Q => \^rx_pe_data\(3),
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(24),
      Q => \^rx_pe_data\(2),
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(25),
      Q => \^rx_pe_data\(1),
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(26),
      Q => \^rx_pe_data\(0),
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(8),
      Q => \^rx_pe_data\(5),
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(9),
      Q => \^rx_pe_data\(4),
      R => '0'
    );
\RX_PE_DATA_V_Buffer[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_3_in,
      O => \RX_PE_DATA_V_Buffer[0]_i_1_n_0\
    );
\RX_PE_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_1_in,
      O => \RX_PE_DATA_V_Buffer[1]_i_1_n_0\
    );
\RX_PE_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_PE_DATA_V_Buffer[0]_i_1_n_0\,
      Q => \RX_PE_DATA_V_Buffer_reg[0]_0\(1),
      R => '0'
    );
\RX_PE_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_PE_DATA_V_Buffer[1]_i_1_n_0\,
      Q => \RX_PE_DATA_V_Buffer_reg[0]_0\(0),
      R => '0'
    );
RX_SP_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000000000000000"
    )
        port map (
      I0 => RX_SP_Buffer_i_2_n_0,
      I1 => RX_SP_Buffer_i_3_n_0,
      I2 => rx_sp_r(0),
      I3 => rx_sp_r(1),
      I4 => rx_sp_r(3),
      I5 => rx_sp_r(2),
      O => std_bool13_out
    );
RX_SP_Buffer_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[3]\,
      I1 => p_0_in26_in,
      I2 => p_3_in,
      I3 => p_1_in,
      O => RX_SP_Buffer_i_2_n_0
    );
RX_SP_Buffer_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => rx_sp_r(5),
      I1 => rx_sp_r(4),
      I2 => rx_sp_r(7),
      I3 => rx_sp_r(6),
      O => RX_SP_Buffer_i_3_n_0
    );
RX_SP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool13_out,
      Q => rx_sp_i,
      R => '0'
    );
\RX_SUF_Buffer[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => p_3_in,
      I1 => p_15_in,
      I2 => rx_sp_r(1),
      O => p_5_out(1)
    );
\RX_SUF_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => p_1_in,
      I1 => p_0_in14_in,
      I2 => p_1_in29_in,
      O => p_5_out(0)
    );
\RX_SUF_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_5_out(1),
      Q => \^rx_suf_buffer_reg[0]_0\(1),
      R => '0'
    );
\RX_SUF_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_5_out(0),
      Q => \^rx_suf_buffer_reg[0]_0\(0),
      R => '0'
    );
first_v_received_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => RX_LANE_UP,
      I1 => \^first_v_received_r\,
      I2 => std_bool1_out,
      O => first_v_received_r_i_1_n_0
    );
first_v_received_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => first_v_received_r_i_1_n_0,
      Q => \^first_v_received_r\,
      R => '0'
    );
\left_align_select_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFAFFFB10401110"
    )
        port map (
      I0 => \left_align_select_r_reg[0]_1\,
      I1 => RXCHARISK(0),
      I2 => RXCHARISK(2),
      I3 => RXCHARISK(3),
      I4 => RXCHARISK(1),
      I5 => \^left_align_select_r_reg[0]_0\,
      O => \left_align_select_r[0]_i_1_n_0\
    );
\left_align_select_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFEB10051100"
    )
        port map (
      I0 => \left_align_select_r_reg[0]_1\,
      I1 => RXCHARISK(0),
      I2 => RXCHARISK(2),
      I3 => RXCHARISK(3),
      I4 => RXCHARISK(1),
      I5 => \^left_align_select_r_reg[1]_0\,
      O => \left_align_select_r[1]_i_1_n_0\
    );
\left_align_select_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \left_align_select_r[0]_i_1_n_0\,
      Q => \^left_align_select_r_reg[0]_0\,
      R => '0'
    );
\left_align_select_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \left_align_select_r[1]_i_1_n_0\,
      Q => \^left_align_select_r_reg[1]_0\,
      R => '0'
    );
load_ufc_control_code_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^rx_suf_buffer_reg[0]_0\(1),
      I1 => \^rx_suf_buffer_reg[0]_0\(0),
      O => neqOp
    );
\previous_cycle_control_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXCHARISK(3),
      Q => previous_cycle_control_r(0),
      R => '0'
    );
\previous_cycle_control_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXCHARISK(2),
      Q => previous_cycle_control_r(1),
      R => '0'
    );
\previous_cycle_control_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXCHARISK(1),
      Q => previous_cycle_control_r(2),
      R => '0'
    );
\previous_cycle_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(24),
      Q => previous_cycle_data_r(0),
      R => '0'
    );
\previous_cycle_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(18),
      Q => previous_cycle_data_r(10),
      R => '0'
    );
\previous_cycle_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(19),
      Q => previous_cycle_data_r(11),
      R => '0'
    );
\previous_cycle_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(20),
      Q => previous_cycle_data_r(12),
      R => '0'
    );
\previous_cycle_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(21),
      Q => previous_cycle_data_r(13),
      R => '0'
    );
\previous_cycle_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(22),
      Q => previous_cycle_data_r(14),
      R => '0'
    );
\previous_cycle_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(23),
      Q => previous_cycle_data_r(15),
      R => '0'
    );
\previous_cycle_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(8),
      Q => previous_cycle_data_r(16),
      R => '0'
    );
\previous_cycle_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(9),
      Q => previous_cycle_data_r(17),
      R => '0'
    );
\previous_cycle_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(10),
      Q => previous_cycle_data_r(18),
      R => '0'
    );
\previous_cycle_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(11),
      Q => previous_cycle_data_r(19),
      R => '0'
    );
\previous_cycle_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(25),
      Q => \^q\(0),
      R => '0'
    );
\previous_cycle_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(12),
      Q => previous_cycle_data_r(20),
      R => '0'
    );
\previous_cycle_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(13),
      Q => previous_cycle_data_r(21),
      R => '0'
    );
\previous_cycle_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(14),
      Q => previous_cycle_data_r(22),
      R => '0'
    );
\previous_cycle_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(15),
      Q => previous_cycle_data_r(23),
      R => '0'
    );
\previous_cycle_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(26),
      Q => previous_cycle_data_r(2),
      R => '0'
    );
\previous_cycle_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(27),
      Q => \^q\(1),
      R => '0'
    );
\previous_cycle_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(28),
      Q => previous_cycle_data_r(4),
      R => '0'
    );
\previous_cycle_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(29),
      Q => \^q\(2),
      R => '0'
    );
\previous_cycle_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(30),
      Q => previous_cycle_data_r(6),
      R => '0'
    );
\previous_cycle_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(31),
      Q => \^q\(3),
      R => '0'
    );
\previous_cycle_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(16),
      Q => previous_cycle_data_r(8),
      R => '0'
    );
\previous_cycle_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RXDATA(17),
      Q => previous_cycle_data_r(9),
      R => '0'
    );
\rx_cc_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__47/i__n_0\,
      Q => rx_cc_r(1),
      R => '0'
    );
\rx_cc_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__46/i__n_0\,
      Q => rx_cc_r(3),
      R => '0'
    );
\rx_cc_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__45/i__n_0\,
      Q => rx_cc_r(5),
      R => '0'
    );
\rx_cc_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__44/i__n_0\,
      Q => rx_cc_r(7),
      R => '0'
    );
\rx_ecp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__24/i__n_0\,
      Q => p_21_in,
      R => '0'
    );
\rx_ecp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__23/i__n_0\,
      Q => p_6_in22_in,
      R => '0'
    );
\rx_ecp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__22/i__n_0\,
      Q => \rx_ecp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_ecp_d_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__21/i__n_0\,
      Q => p_0_in18_in,
      R => '0'
    );
\rx_ecp_d_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__20/i__n_0\,
      Q => \rx_ecp_d_r_reg_n_0_[5]\,
      R => '0'
    );
\rx_ecp_d_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__19/i__n_0\,
      Q => \rx_ecp_d_r_reg_n_0_[7]\,
      R => '0'
    );
\rx_ecp_r_reg[0]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => p_0_in26_in,
      I1 => p_3_in,
      I2 => p_6_in22_in,
      I3 => p_21_in,
      I4 => \rx_ecp_d_r_reg_n_0_[3]\,
      I5 => p_6_in34_in,
      O => p_9_out(1)
    );
\rx_ecp_r_reg[1]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[3]\,
      I1 => p_1_in,
      I2 => \rx_ecp_d_r_reg_n_0_[5]\,
      I3 => p_0_in18_in,
      I4 => \rx_ecp_d_r_reg_n_0_[7]\,
      I5 => p_2_in30_in,
      O => p_9_out(0)
    );
\rx_pad_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__11/i__n_0\,
      Q => rx_pad_d_r(0),
      R => '0'
    );
\rx_pad_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__10/i__n_0\,
      Q => rx_pad_d_r(1),
      R => '0'
    );
\rx_pad_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__9/i__n_0\,
      Q => rx_pad_d_r(2),
      R => '0'
    );
\rx_pad_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__8/i__n_0\,
      Q => rx_pad_d_r(3),
      R => '0'
    );
\rx_pad_r_reg[0]_srl2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => rx_pad_d_r(0),
      I1 => rx_pad_d_r(1),
      I2 => p_3_in,
      I3 => p_0_in26_in,
      O => p_2_out(1)
    );
\rx_pad_r_reg[1]_srl2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => rx_pad_d_r(2),
      I1 => rx_pad_d_r(3),
      I2 => p_1_in,
      I3 => \rx_pe_control_r_reg_n_0_[3]\,
      O => p_2_out(0)
    );
\rx_pe_control_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(0),
      Q => p_3_in,
      R => '0'
    );
\rx_pe_control_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(1),
      Q => p_0_in26_in,
      R => '0'
    );
\rx_pe_control_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(2),
      Q => p_1_in,
      R => '0'
    );
\rx_pe_control_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(3),
      Q => \rx_pe_control_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => rx_pe_data_r(10),
      R => '0'
    );
\rx_pe_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg_n_0_[24]\,
      Q => rx_pe_data_r(24),
      R => '0'
    );
\rx_pe_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg_n_0_[25]\,
      Q => rx_pe_data_r(25),
      R => '0'
    );
\rx_pe_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg_n_0_[26]\,
      Q => rx_pe_data_r(26),
      R => '0'
    );
\rx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => rx_pe_data_r(8),
      R => '0'
    );
\rx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => rx_pe_data_r(9),
      R => '0'
    );
\rx_scp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__18/i__n_0\,
      Q => p_32_in,
      R => '0'
    );
\rx_scp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__17/i__n_0\,
      Q => p_6_in34_in,
      R => '0'
    );
\rx_scp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__16/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_scp_d_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__15/i__n_0\,
      Q => p_0_in28_in,
      R => '0'
    );
\rx_scp_d_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__14/i__n_0\,
      Q => p_1_in29_in,
      R => '0'
    );
\rx_scp_d_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__13/i__n_0\,
      Q => p_2_in30_in,
      R => '0'
    );
\rx_scp_d_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__12/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[7]\,
      R => '0'
    );
\rx_scp_r_reg[0]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => p_0_in26_in,
      I1 => p_3_in,
      I2 => rx_sp_r(1),
      I3 => p_32_in,
      I4 => \rx_scp_d_r_reg_n_0_[3]\,
      I5 => p_6_in34_in,
      O => p_8_out(1)
    );
\rx_scp_r_reg[1]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[3]\,
      I1 => p_1_in,
      I2 => p_1_in29_in,
      I3 => p_0_in28_in,
      I4 => \rx_scp_d_r_reg_n_0_[7]\,
      I5 => p_2_in30_in,
      O => p_8_out(0)
    );
\rx_sp_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool16_in,
      Q => rx_sp_neg_d_r(0),
      R => '0'
    );
\rx_sp_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool13_in,
      Q => rx_sp_neg_d_r(1),
      R => '0'
    );
\rx_sp_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(4),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => p_0_in(2),
      O => \rx_sp_r[2]_i_1_n_0\
    );
\rx_sp_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(0),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(3),
      O => \rx_sp_r[3]_i_1_n_0\
    );
\rx_sp_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0810"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(5),
      I1 => \^word_aligned_data_r_reg[16]_0\(4),
      I2 => \^word_aligned_data_r_reg[16]_0\(6),
      I3 => \^word_aligned_data_r_reg[16]_0\(7),
      O => \rx_sp_r[4]_i_1_n_0\
    );
\rx_sp_r[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[16]_0\(2),
      I1 => \^word_aligned_data_r_reg[16]_0\(0),
      I2 => \^word_aligned_data_r_reg[16]_0\(1),
      I3 => \^word_aligned_data_r_reg[16]_0\(3),
      O => \rx_sp_r[5]_i_1_n_0\
    );
\rx_sp_r[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0810"
    )
        port map (
      I0 => \word_aligned_data_r_reg_n_0_[26]\,
      I1 => \^word_aligned_data_r_reg[27]_0\(4),
      I2 => \word_aligned_data_r_reg_n_0_[25]\,
      I3 => \word_aligned_data_r_reg_n_0_[24]\,
      O => \rx_sp_r[6]_i_1_n_0\
    );
\rx_sp_r[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[27]_0\(2),
      I1 => \^word_aligned_data_r_reg[27]_0\(0),
      I2 => \^word_aligned_data_r_reg[27]_0\(1),
      I3 => \^word_aligned_data_r_reg[27]_0\(3),
      O => \rx_sp_r[7]_i_1_n_0\
    );
\rx_sp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__0/i__n_0\,
      Q => rx_sp_r(0),
      R => '0'
    );
\rx_sp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EXP_IN_n_0,
      Q => rx_sp_r(1),
      R => '0'
    );
\rx_sp_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_sp_r[2]_i_1_n_0\,
      Q => rx_sp_r(2),
      R => '0'
    );
\rx_sp_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_sp_r[3]_i_1_n_0\,
      Q => rx_sp_r(3),
      R => '0'
    );
\rx_sp_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_sp_r[4]_i_1_n_0\,
      Q => rx_sp_r(4),
      R => '0'
    );
\rx_sp_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_sp_r[5]_i_1_n_0\,
      Q => rx_sp_r(5),
      R => '0'
    );
\rx_sp_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_sp_r[6]_i_1_n_0\,
      Q => rx_sp_r(6),
      R => '0'
    );
\rx_sp_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_sp_r[7]_i_1_n_0\,
      Q => rx_sp_r(7),
      R => '0'
    );
\rx_spa_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__35/i__n_0\,
      Q => rx_spa_neg_d_r(0),
      R => '0'
    );
\rx_spa_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__34/i__n_0\,
      Q => rx_spa_neg_d_r(1),
      R => '0'
    );
\rx_suf_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__26/i__n_0\,
      Q => p_15_in,
      R => '0'
    );
\rx_suf_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__25/i__n_0\,
      Q => p_0_in14_in,
      R => '0'
    );
\rx_v_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__6/i__n_0\,
      Q => rx_v_d_r(2),
      R => '0'
    );
\rx_v_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__5/i__n_0\,
      Q => rx_v_d_r(3),
      R => '0'
    );
\rx_v_d_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__4/i__n_0\,
      Q => rx_v_d_r(4),
      R => '0'
    );
\rx_v_d_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__3/i__n_0\,
      Q => rx_v_d_r(5),
      R => '0'
    );
\rx_v_d_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__2/i__n_0\,
      Q => rx_v_d_r(6),
      R => '0'
    );
\rx_v_d_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__1/i__n_0\,
      Q => rx_v_d_r(7),
      R => '0'
    );
\stage_1_count_value_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^rx_suf_buffer_reg[0]_0\(0),
      I1 => \^rx_pe_data\(2),
      I2 => \^rx_pe_data\(0),
      I3 => \^rx_pe_data\(1),
      O => \RX_SUF_Buffer_reg[1]_0\
    );
\stage_1_count_value_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"78FF780078007800"
    )
        port map (
      I0 => \^rx_pe_data\(1),
      I1 => \^rx_pe_data\(0),
      I2 => \^rx_pe_data\(2),
      I3 => \^rx_suf_buffer_reg[0]_0\(0),
      I4 => \^rx_suf_buffer_reg[0]_0\(1),
      I5 => \^rx_pe_data\(5),
      O => \RX_PE_DATA_Buffer_reg[25]_0\
    );
\stage_1_count_value_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6F606060"
    )
        port map (
      I0 => \^rx_pe_data\(0),
      I1 => \^rx_pe_data\(1),
      I2 => \^rx_suf_buffer_reg[0]_0\(0),
      I3 => \^rx_suf_buffer_reg[0]_0\(1),
      I4 => \^rx_pe_data\(4),
      O => \RX_PE_DATA_Buffer_reg[26]_1\
    );
\stage_1_count_value_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7444"
    )
        port map (
      I0 => \^rx_pe_data\(0),
      I1 => \^rx_suf_buffer_reg[0]_0\(0),
      I2 => \^rx_suf_buffer_reg[0]_0\(1),
      I3 => \^rx_pe_data\(3),
      O => \RX_PE_DATA_Buffer_reg[26]_0\
    );
\word_aligned_control_bits_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => RXCHARISK(0),
      I1 => previous_cycle_control_r(2),
      I2 => previous_cycle_control_r(1),
      I3 => \^left_align_select_r_reg[0]_0\,
      I4 => \^left_align_select_r_reg[1]_0\,
      I5 => previous_cycle_control_r(0),
      O => \word_aligned_control_bits_r[0]_i_1_n_0\
    );
\word_aligned_control_bits_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => RXCHARISK(1),
      I1 => previous_cycle_control_r(1),
      I2 => previous_cycle_control_r(0),
      I3 => \^left_align_select_r_reg[0]_0\,
      I4 => \^left_align_select_r_reg[1]_0\,
      I5 => RXCHARISK(0),
      O => \word_aligned_control_bits_r[1]_i_1_n_0\
    );
\word_aligned_control_bits_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCAAF000CCAAF0"
    )
        port map (
      I0 => previous_cycle_control_r(0),
      I1 => RXCHARISK(0),
      I2 => RXCHARISK(2),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => RXCHARISK(1),
      O => \word_aligned_control_bits_r[2]_i_1_n_0\
    );
\word_aligned_control_bits_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r[0]_i_1_n_0\,
      Q => word_aligned_control_bits_r(0),
      R => '0'
    );
\word_aligned_control_bits_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r[1]_i_1_n_0\,
      Q => word_aligned_control_bits_r(1),
      R => '0'
    );
\word_aligned_control_bits_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r[2]_i_1_n_0\,
      Q => word_aligned_control_bits_r(2),
      R => '0'
    );
\word_aligned_control_bits_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[3]_0\,
      Q => word_aligned_control_bits_r(3),
      R => '0'
    );
\word_aligned_data_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => RXDATA(7),
      I1 => previous_cycle_data_r(23),
      I2 => \^q\(3),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => previous_cycle_data_r(15),
      O => \word_aligned_data_r[0]_i_1_n_0\
    );
\word_aligned_data_r[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => RXDATA(13),
      I1 => previous_cycle_data_r(13),
      I2 => RXDATA(5),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => \^q\(2),
      O => \word_aligned_data_r[10]_i_1_n_0\
    );
\word_aligned_data_r[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCAAF000CCAAF0"
    )
        port map (
      I0 => previous_cycle_data_r(12),
      I1 => previous_cycle_data_r(4),
      I2 => RXDATA(12),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => RXDATA(4),
      O => \word_aligned_data_r[11]_i_1_n_0\
    );
\word_aligned_data_r[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => RXDATA(11),
      I1 => previous_cycle_data_r(11),
      I2 => RXDATA(3),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => \^q\(1),
      O => \word_aligned_data_r[12]_i_1_n_0\
    );
\word_aligned_data_r[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => RXDATA(10),
      I1 => previous_cycle_data_r(10),
      I2 => RXDATA(2),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => previous_cycle_data_r(2),
      O => \word_aligned_data_r[13]_i_1_n_0\
    );
\word_aligned_data_r[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => RXDATA(9),
      I1 => previous_cycle_data_r(9),
      I2 => RXDATA(1),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => \^q\(0),
      O => \word_aligned_data_r[14]_i_1_n_0\
    );
\word_aligned_data_r[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => previous_cycle_data_r(8),
      I1 => RXDATA(0),
      I2 => RXDATA(8),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => previous_cycle_data_r(0),
      O => \word_aligned_data_r[15]_i_1_n_0\
    );
\word_aligned_data_r[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => previous_cycle_data_r(6),
      I1 => RXDATA(14),
      I2 => RXDATA(22),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => RXDATA(6),
      O => \word_aligned_data_r[17]_i_1_n_0\
    );
\word_aligned_data_r[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => previous_cycle_data_r(4),
      I1 => RXDATA(12),
      I2 => RXDATA(20),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => RXDATA(4),
      O => \word_aligned_data_r[19]_i_1_n_0\
    );
\word_aligned_data_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => RXDATA(6),
      I1 => previous_cycle_data_r(22),
      I2 => previous_cycle_data_r(14),
      I3 => \^left_align_select_r_reg[0]_0\,
      I4 => \^left_align_select_r_reg[1]_0\,
      I5 => previous_cycle_data_r(6),
      O => \word_aligned_data_r[1]_i_1_n_0\
    );
\word_aligned_data_r[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCAAF000CCAAF0"
    )
        port map (
      I0 => previous_cycle_data_r(2),
      I1 => RXDATA(2),
      I2 => RXDATA(18),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => RXDATA(10),
      O => \word_aligned_data_r[21]_i_1_n_0\
    );
\word_aligned_data_r[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => previous_cycle_data_r(0),
      I1 => RXDATA(8),
      I2 => RXDATA(16),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => RXDATA(0),
      O => \word_aligned_data_r[23]_i_1_n_0\
    );
\word_aligned_data_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => RXDATA(5),
      I1 => previous_cycle_data_r(21),
      I2 => \^q\(2),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => previous_cycle_data_r(13),
      O => \word_aligned_data_r[2]_i_1_n_0\
    );
\word_aligned_data_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => previous_cycle_data_r(20),
      I1 => previous_cycle_data_r(4),
      I2 => RXDATA(4),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => previous_cycle_data_r(12),
      O => \word_aligned_data_r[3]_i_1_n_0\
    );
\word_aligned_data_r[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCAAF000CCAAF0"
    )
        port map (
      I0 => previous_cycle_data_r(19),
      I1 => previous_cycle_data_r(11),
      I2 => RXDATA(3),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => \^q\(1),
      O => \word_aligned_data_r[4]_i_1_n_0\
    );
\word_aligned_data_r[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => RXDATA(2),
      I1 => previous_cycle_data_r(18),
      I2 => previous_cycle_data_r(10),
      I3 => \^left_align_select_r_reg[0]_0\,
      I4 => \^left_align_select_r_reg[1]_0\,
      I5 => previous_cycle_data_r(2),
      O => \word_aligned_data_r[5]_i_1_n_0\
    );
\word_aligned_data_r[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => RXDATA(1),
      I1 => previous_cycle_data_r(17),
      I2 => \^q\(0),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => previous_cycle_data_r(9),
      O => \word_aligned_data_r[6]_i_1_n_0\
    );
\word_aligned_data_r[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => previous_cycle_data_r(16),
      I1 => previous_cycle_data_r(0),
      I2 => RXDATA(0),
      I3 => \^left_align_select_r_reg[1]_0\,
      I4 => \^left_align_select_r_reg[0]_0\,
      I5 => previous_cycle_data_r(8),
      O => \word_aligned_data_r[7]_i_1_n_0\
    );
\word_aligned_data_r[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => RXDATA(15),
      I1 => previous_cycle_data_r(15),
      I2 => \^q\(3),
      I3 => \^left_align_select_r_reg[0]_0\,
      I4 => \^left_align_select_r_reg[1]_0\,
      I5 => RXDATA(7),
      O => \word_aligned_data_r[8]_i_1_n_0\
    );
\word_aligned_data_r[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => RXDATA(14),
      I1 => previous_cycle_data_r(14),
      I2 => previous_cycle_data_r(6),
      I3 => \^left_align_select_r_reg[0]_0\,
      I4 => \^left_align_select_r_reg[1]_0\,
      I5 => RXDATA(6),
      O => \word_aligned_data_r[9]_i_1_n_0\
    );
\word_aligned_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[0]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(7),
      R => '0'
    );
\word_aligned_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[10]_i_1_n_0\,
      Q => p_0_in(1),
      R => '0'
    );
\word_aligned_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[11]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[11]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[12]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[11]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[13]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[11]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[14]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[11]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[15]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[11]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[16]_1\(3),
      Q => \^word_aligned_data_r_reg[16]_0\(7),
      R => '0'
    );
\word_aligned_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[17]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[16]_0\(6),
      R => '0'
    );
\word_aligned_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[16]_1\(2),
      Q => \^word_aligned_data_r_reg[16]_0\(5),
      R => '0'
    );
\word_aligned_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[19]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[16]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[1]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(6),
      R => '0'
    );
\word_aligned_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[16]_1\(1),
      Q => \^word_aligned_data_r_reg[16]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[21]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[16]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[16]_1\(0),
      Q => \^word_aligned_data_r_reg[16]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[23]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[16]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(7),
      Q => \word_aligned_data_r_reg_n_0_[24]\,
      R => '0'
    );
\word_aligned_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(6),
      Q => \word_aligned_data_r_reg_n_0_[25]\,
      R => '0'
    );
\word_aligned_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(5),
      Q => \word_aligned_data_r_reg_n_0_[26]\,
      R => '0'
    );
\word_aligned_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(4),
      Q => \^word_aligned_data_r_reg[27]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(3),
      Q => \^word_aligned_data_r_reg[27]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(2),
      Q => \^word_aligned_data_r_reg[27]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[2]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(5),
      R => '0'
    );
\word_aligned_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(1),
      Q => \^word_aligned_data_r_reg[27]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[24]_0\(0),
      Q => \^word_aligned_data_r_reg[27]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[3]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[4]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[5]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[6]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[7]_i_1_n_0\,
      Q => \^word_aligned_data_r_reg[0]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[8]_i_1_n_0\,
      Q => p_0_in(3),
      R => '0'
    );
\word_aligned_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r[9]_i_1_n_0\,
      Q => p_0_in(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER is
  port (
    SHIFTED_DATA_Buffer : out STD_LOGIC_VECTOR ( 0 to 31 );
    \SHIFTED_DATA_Buffer_reg[15]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[14]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[13]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[12]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[11]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[10]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[9]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[8]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[7]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[6]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[5]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[4]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[3]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[2]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[1]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[0]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    BARREL_SHIFTER_CONTROL_Buffer : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    UFC_OUTPUT_SELECT_Buffer : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MUXED_DATA_Buffer_reg[31]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[30]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[29]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[28]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[27]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[26]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[25]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[24]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[23]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[22]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[21]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[20]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[19]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[18]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[17]\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[16]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER : entity is "aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER is
  signal \^shifted_data_buffer\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal shifted_data_c : STD_LOGIC_VECTOR ( 0 to 15 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[16]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[17]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[18]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[19]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[20]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[21]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[22]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[23]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[24]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[25]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[26]_i_1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[27]_i_1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[28]_i_1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[29]_i_1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[30]_i_1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[31]_i_1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[0]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[10]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[11]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[12]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[13]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[14]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[15]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[1]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[2]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[3]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[4]_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[5]_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[6]_i_1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[7]_i_1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[8]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[9]_i_1\ : label is "soft_lutpair76";
begin
  SHIFTED_DATA_Buffer(0 to 31) <= \^shifted_data_buffer\(0 to 31);
\MUXED_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(0),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[16]\,
      O => \SHIFTED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(1),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[17]\,
      O => \SHIFTED_DATA_Buffer_reg[1]_0\
    );
\MUXED_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(2),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[18]\,
      O => \SHIFTED_DATA_Buffer_reg[2]_0\
    );
\MUXED_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(3),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[19]\,
      O => \SHIFTED_DATA_Buffer_reg[3]_0\
    );
\MUXED_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(4),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[20]\,
      O => \SHIFTED_DATA_Buffer_reg[4]_0\
    );
\MUXED_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(5),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[21]\,
      O => \SHIFTED_DATA_Buffer_reg[5]_0\
    );
\MUXED_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(6),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[22]\,
      O => \SHIFTED_DATA_Buffer_reg[6]_0\
    );
\MUXED_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(7),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[23]\,
      O => \SHIFTED_DATA_Buffer_reg[7]_0\
    );
\MUXED_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(8),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[24]\,
      O => \SHIFTED_DATA_Buffer_reg[8]_0\
    );
\MUXED_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(9),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[25]\,
      O => \SHIFTED_DATA_Buffer_reg[9]_0\
    );
\MUXED_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(10),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[26]\,
      O => \SHIFTED_DATA_Buffer_reg[10]_0\
    );
\MUXED_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(11),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[27]\,
      O => \SHIFTED_DATA_Buffer_reg[11]_0\
    );
\MUXED_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(12),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[28]\,
      O => \SHIFTED_DATA_Buffer_reg[12]_0\
    );
\MUXED_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(13),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[29]\,
      O => \SHIFTED_DATA_Buffer_reg[13]_0\
    );
\MUXED_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(14),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[30]\,
      O => \SHIFTED_DATA_Buffer_reg[14]_0\
    );
\MUXED_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^shifted_data_buffer\(15),
      I1 => UFC_OUTPUT_SELECT_Buffer(0),
      I2 => \MUXED_DATA_Buffer_reg[31]\,
      O => \SHIFTED_DATA_Buffer_reg[15]_0\
    );
\SHIFTED_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(15),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(31),
      O => shifted_data_c(0)
    );
\SHIFTED_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(5),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(21),
      O => shifted_data_c(10)
    );
\SHIFTED_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(4),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(20),
      O => shifted_data_c(11)
    );
\SHIFTED_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(3),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(19),
      O => shifted_data_c(12)
    );
\SHIFTED_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(2),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(18),
      O => shifted_data_c(13)
    );
\SHIFTED_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(1),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(17),
      O => shifted_data_c(14)
    );
\SHIFTED_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(0),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(16),
      O => shifted_data_c(15)
    );
\SHIFTED_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(14),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(30),
      O => shifted_data_c(1)
    );
\SHIFTED_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(13),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(29),
      O => shifted_data_c(2)
    );
\SHIFTED_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(12),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(28),
      O => shifted_data_c(3)
    );
\SHIFTED_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(11),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(27),
      O => shifted_data_c(4)
    );
\SHIFTED_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(10),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(26),
      O => shifted_data_c(5)
    );
\SHIFTED_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(9),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(25),
      O => shifted_data_c(6)
    );
\SHIFTED_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(8),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(24),
      O => shifted_data_c(7)
    );
\SHIFTED_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(7),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(23),
      O => shifted_data_c(8)
    );
\SHIFTED_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(6),
      I1 => BARREL_SHIFTER_CONTROL_Buffer,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_1\(22),
      O => shifted_data_c(9)
    );
\SHIFTED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(0),
      Q => \^shifted_data_buffer\(0),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(10),
      Q => \^shifted_data_buffer\(10),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(11),
      Q => \^shifted_data_buffer\(11),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(12),
      Q => \^shifted_data_buffer\(12),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(13),
      Q => \^shifted_data_buffer\(13),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(14),
      Q => \^shifted_data_buffer\(14),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(15),
      Q => \^shifted_data_buffer\(15),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(15),
      Q => \^shifted_data_buffer\(16),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(14),
      Q => \^shifted_data_buffer\(17),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(13),
      Q => \^shifted_data_buffer\(18),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(12),
      Q => \^shifted_data_buffer\(19),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(1),
      Q => \^shifted_data_buffer\(1),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(11),
      Q => \^shifted_data_buffer\(20),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(10),
      Q => \^shifted_data_buffer\(21),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(9),
      Q => \^shifted_data_buffer\(22),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(8),
      Q => \^shifted_data_buffer\(23),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(7),
      Q => \^shifted_data_buffer\(24),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(6),
      Q => \^shifted_data_buffer\(25),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(5),
      Q => \^shifted_data_buffer\(26),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(4),
      Q => \^shifted_data_buffer\(27),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(3),
      Q => \^shifted_data_buffer\(28),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(2),
      Q => \^shifted_data_buffer\(29),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(2),
      Q => \^shifted_data_buffer\(2),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(1),
      Q => \^shifted_data_buffer\(30),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[0]_1\(0),
      Q => \^shifted_data_buffer\(31),
      R => BARREL_SHIFTER_CONTROL_Buffer
    );
\SHIFTED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(3),
      Q => \^shifted_data_buffer\(3),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(4),
      Q => \^shifted_data_buffer\(4),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(5),
      Q => \^shifted_data_buffer\(5),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(6),
      Q => \^shifted_data_buffer\(6),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(7),
      Q => \^shifted_data_buffer\(7),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(8),
      Q => \^shifted_data_buffer\(8),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(9),
      Q => \^shifted_data_buffer\(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL is
  port (
    BARREL_SHIFTER_CONTROL_Buffer : out STD_LOGIC;
    barrel_shifter_control_i : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL : entity is "aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL is
begin
\BARREL_SHIFTER_CONTROL_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => barrel_shifter_control_i,
      Q => BARREL_SHIFTER_CONTROL_Buffer,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_FILTER is
  port (
    UFC_START : out STD_LOGIC;
    barrel_shifter_control_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \PDU_ECP_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \word_aligned_data_r_reg[0]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[1]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[2]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[3]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[4]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[5]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[6]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[7]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[11]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[12]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[13]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[14]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[15]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[16]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[17]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[18]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[19]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[20]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[21]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[22]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[23]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[24]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[25]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[26]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[27]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[28]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[29]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[30]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[31]\ : out STD_LOGIC;
    \PDU_PAD_Buffer_reg[0]_0\ : out STD_LOGIC;
    \PDU_ECP_Buffer_reg[1]_0\ : out STD_LOGIC;
    \PDU_ECP_Buffer_reg[0]_1\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \UFC_DATA_V_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \PDU_SCP_Buffer_reg[1]_0\ : out STD_LOGIC;
    S1_in : out STD_LOGIC;
    RESET : in STD_LOGIC;
    neqOp : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \rx_suf_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_8_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_9_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_2_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stage_1_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    RX_PE_DATA : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \stage_1_data_r_reg[11]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \stage_1_data_r_reg[16]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[27]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \stage_1_count_value_r_reg[0]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]_0\ : in STD_LOGIC;
    \rx_data_v_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_FILTER : entity is "aurora_1ln_rx_lpm_UFC_FILTER";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_FILTER;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_FILTER is
  signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal L : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \PDU_DATA_V_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \PDU_DATA_V_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal \^pdu_ecp_buffer_reg[0]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal PDU_PAD : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \UFC_DATA_V_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal UFC_START_Buffer_i_1_n_0 : STD_LOGIC;
  signal load_ufc_control_code_r : STD_LOGIC;
  signal rx_data_v_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \rx_ecp_r_reg[0]_srl2_n_0\ : STD_LOGIC;
  signal \rx_ecp_r_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \rx_pad_r_reg[0]_srl2_n_0\ : STD_LOGIC;
  signal \rx_pad_r_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \rx_scp_r_reg[0]_srl2_n_0\ : STD_LOGIC;
  signal \rx_scp_r_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \rx_suf_r_reg_n_0_[1]\ : STD_LOGIC;
  signal stage_1_count_value_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal stage_2_count_value_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \stage_2_count_value_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_count_value_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_count_value_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_count_value_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_lane_mask_c__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute srl_bus_name : string;
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[0]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name : string;
  attribute srl_name of \PDU_DATA_Buffer_reg[0]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[0]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[10]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[10]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[10]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[11]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[11]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[11]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[12]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[12]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[12]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[13]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[13]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[13]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[14]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[14]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[14]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[15]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[15]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[15]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[16]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[16]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[16]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[17]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[17]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[17]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[18]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[18]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[18]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[19]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[19]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[19]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[1]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[1]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[1]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[20]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[20]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[20]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[21]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[21]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[21]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[22]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[22]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[22]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[23]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[23]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[23]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[24]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[24]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[24]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[25]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[25]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[25]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[26]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[26]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[26]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[27]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[27]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[27]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[28]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[28]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[28]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[29]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[29]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[29]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[2]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[2]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[2]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[30]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[30]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[30]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[31]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[31]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[31]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[3]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[3]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[3]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[4]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[4]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[4]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[5]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[5]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[5]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[6]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[6]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[6]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[7]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[7]_srl4\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[7]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[8]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[8]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[8]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[9]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[9]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[9]_srl2 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \PDU_DATA_V_Buffer[0]_i_1\ : label is "soft_lutpair111";
  attribute srl_bus_name of \rx_ecp_r_reg[0]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg ";
  attribute srl_name of \rx_ecp_r_reg[0]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[0]_srl2 ";
  attribute srl_bus_name of \rx_ecp_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg ";
  attribute srl_name of \rx_ecp_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[1]_srl2 ";
  attribute srl_bus_name of \rx_pad_r_reg[0]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg ";
  attribute srl_name of \rx_pad_r_reg[0]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg[0]_srl2 ";
  attribute srl_bus_name of \rx_pad_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg ";
  attribute srl_name of \rx_pad_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg[1]_srl2 ";
  attribute srl_bus_name of \rx_scp_r_reg[0]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg ";
  attribute srl_name of \rx_scp_r_reg[0]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg[0]_srl2 ";
  attribute srl_bus_name of \rx_scp_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg ";
  attribute srl_name of \rx_scp_r_reg[1]_srl2\ : label is "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg[1]_srl2 ";
  attribute SOFT_HLUTNM of stage_2_lane_mask_c : label is "soft_lutpair111";
begin
  D(1 downto 0) <= \^d\(1 downto 0);
  \PDU_ECP_Buffer_reg[0]_0\(1 downto 0) <= \^pdu_ecp_buffer_reg[0]_0\(1 downto 0);
\PDU_DATA_Buffer_reg[0]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(7),
      Q => \word_aligned_data_r_reg[0]\
    );
\PDU_DATA_Buffer_reg[10]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(3),
      Q => \RX_PE_DATA_Buffer_reg[10]\
    );
\PDU_DATA_Buffer_reg[11]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(4),
      Q => \word_aligned_data_r_reg[11]\
    );
\PDU_DATA_Buffer_reg[12]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(3),
      Q => \word_aligned_data_r_reg[12]\
    );
\PDU_DATA_Buffer_reg[13]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(2),
      Q => \word_aligned_data_r_reg[13]\
    );
\PDU_DATA_Buffer_reg[14]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(1),
      Q => \word_aligned_data_r_reg[14]\
    );
\PDU_DATA_Buffer_reg[15]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(0),
      Q => \word_aligned_data_r_reg[15]\
    );
\PDU_DATA_Buffer_reg[16]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(7),
      Q => \word_aligned_data_r_reg[16]\
    );
\PDU_DATA_Buffer_reg[17]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(6),
      Q => \word_aligned_data_r_reg[17]\
    );
\PDU_DATA_Buffer_reg[18]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(5),
      Q => \word_aligned_data_r_reg[18]\
    );
\PDU_DATA_Buffer_reg[19]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(4),
      Q => \word_aligned_data_r_reg[19]\
    );
\PDU_DATA_Buffer_reg[1]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(6),
      Q => \word_aligned_data_r_reg[1]\
    );
\PDU_DATA_Buffer_reg[20]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(3),
      Q => \word_aligned_data_r_reg[20]\
    );
\PDU_DATA_Buffer_reg[21]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(2),
      Q => \word_aligned_data_r_reg[21]\
    );
\PDU_DATA_Buffer_reg[22]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(1),
      Q => \word_aligned_data_r_reg[22]\
    );
\PDU_DATA_Buffer_reg[23]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(0),
      Q => \word_aligned_data_r_reg[23]\
    );
\PDU_DATA_Buffer_reg[24]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(2),
      Q => \RX_PE_DATA_Buffer_reg[24]\
    );
\PDU_DATA_Buffer_reg[25]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(1),
      Q => \RX_PE_DATA_Buffer_reg[25]\
    );
\PDU_DATA_Buffer_reg[26]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(0),
      Q => \RX_PE_DATA_Buffer_reg[26]\
    );
\PDU_DATA_Buffer_reg[27]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[27]\(4),
      Q => \word_aligned_data_r_reg[27]\
    );
\PDU_DATA_Buffer_reg[28]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[27]\(3),
      Q => \word_aligned_data_r_reg[28]\
    );
\PDU_DATA_Buffer_reg[29]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[27]\(2),
      Q => \word_aligned_data_r_reg[29]\
    );
\PDU_DATA_Buffer_reg[2]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(5),
      Q => \word_aligned_data_r_reg[2]\
    );
\PDU_DATA_Buffer_reg[30]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[27]\(1),
      Q => \word_aligned_data_r_reg[30]\
    );
\PDU_DATA_Buffer_reg[31]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[27]\(0),
      Q => \word_aligned_data_r_reg[31]\
    );
\PDU_DATA_Buffer_reg[3]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(4),
      Q => \word_aligned_data_r_reg[3]\
    );
\PDU_DATA_Buffer_reg[4]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(3),
      Q => \word_aligned_data_r_reg[4]\
    );
\PDU_DATA_Buffer_reg[5]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(2),
      Q => \word_aligned_data_r_reg[5]\
    );
\PDU_DATA_Buffer_reg[6]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(1),
      Q => \word_aligned_data_r_reg[6]\
    );
\PDU_DATA_Buffer_reg[7]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(0),
      Q => \word_aligned_data_r_reg[7]\
    );
\PDU_DATA_Buffer_reg[8]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(5),
      Q => \RX_PE_DATA_Buffer_reg[8]\
    );
\PDU_DATA_Buffer_reg[9]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(4),
      Q => \RX_PE_DATA_Buffer_reg[9]\
    );
\PDU_DATA_V_Buffer[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888882"
    )
        port map (
      I0 => rx_data_v_r(0),
      I1 => stage_2_count_value_r(0),
      I2 => stage_2_count_value_r(1),
      I3 => stage_2_count_value_r(2),
      I4 => stage_2_count_value_r(3),
      O => \PDU_DATA_V_Buffer[0]_i_1_n_0\
    );
\PDU_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA02A802"
    )
        port map (
      I0 => rx_data_v_r(1),
      I1 => stage_2_count_value_r(2),
      I2 => stage_2_count_value_r(1),
      I3 => stage_2_count_value_r(0),
      I4 => stage_2_count_value_r(3),
      I5 => L(0),
      O => \PDU_DATA_V_Buffer[1]_i_1_n_0\
    );
\PDU_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \PDU_DATA_V_Buffer[0]_i_1_n_0\,
      Q => Q(1),
      R => RESET
    );
\PDU_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \PDU_DATA_V_Buffer[1]_i_1_n_0\,
      Q => Q(0),
      R => RESET
    );
\PDU_ECP_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_ecp_r_reg[0]_srl2_n_0\,
      Q => \^pdu_ecp_buffer_reg[0]_0\(1),
      R => '0'
    );
\PDU_ECP_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_ecp_r_reg[1]_srl2_n_0\,
      Q => \^pdu_ecp_buffer_reg[0]_0\(0),
      R => '0'
    );
\PDU_PAD_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_pad_r_reg[0]_srl2_n_0\,
      Q => PDU_PAD(0),
      R => '0'
    );
\PDU_PAD_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_pad_r_reg[1]_srl2_n_0\,
      Q => PDU_PAD(1),
      R => '0'
    );
\PDU_SCP_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_scp_r_reg[0]_srl2_n_0\,
      Q => \^d\(1),
      R => '0'
    );
\PDU_SCP_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_scp_r_reg[1]_srl2_n_0\,
      Q => \^d\(0),
      R => '0'
    );
\UFC_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFAFAFBA"
    )
        port map (
      I0 => L(0),
      I1 => stage_2_count_value_r(3),
      I2 => stage_2_count_value_r(0),
      I3 => stage_2_count_value_r(1),
      I4 => stage_2_count_value_r(2),
      O => \UFC_DATA_V_Buffer[1]_i_1_n_0\
    );
\UFC_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_lane_mask_c__0\(0),
      Q => \UFC_DATA_V_Buffer_reg[0]_0\(1),
      R => RESET
    );
\UFC_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_DATA_V_Buffer[1]_i_1_n_0\,
      Q => \UFC_DATA_V_Buffer_reg[0]_0\(0),
      R => RESET
    );
\UFC_MESSAGE_START_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => L(0),
      Q => barrel_shifter_control_i,
      R => RESET
    );
UFC_START_Buffer_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => L(0),
      I1 => L(1),
      O => UFC_START_Buffer_i_1_n_0
    );
UFC_START_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_START_Buffer_i_1_n_0,
      Q => UFC_START,
      R => RESET
    );
data_after_start_muxcy_0_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d\(1),
      O => S1_in
    );
data_after_start_muxcy_1_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d\(0),
      O => \PDU_SCP_Buffer_reg[1]_0\
    );
in_frame_muxcy_0_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^pdu_ecp_buffer_reg[0]_0\(1),
      I1 => \^d\(1),
      O => \PDU_ECP_Buffer_reg[0]_1\
    );
in_frame_muxcy_1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^pdu_ecp_buffer_reg[0]_0\(0),
      I1 => \^d\(0),
      O => \PDU_ECP_Buffer_reg[1]_0\
    );
load_ufc_control_code_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => neqOp,
      Q => load_ufc_control_code_r,
      R => RESET
    );
\rx_data_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_data_v_r_reg[0]_0\(1),
      Q => rx_data_v_r(0),
      R => RESET
    );
\rx_data_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_data_v_r_reg[0]_0\(0),
      Q => rx_data_v_r(1),
      R => RESET
    );
\rx_ecp_r_reg[0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => p_9_out(1),
      Q => \rx_ecp_r_reg[0]_srl2_n_0\
    );
\rx_ecp_r_reg[1]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => p_9_out(0),
      Q => \rx_ecp_r_reg[1]_srl2_n_0\
    );
\rx_pad_r_reg[0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => p_2_out(1),
      Q => \rx_pad_r_reg[0]_srl2_n_0\
    );
\rx_pad_r_reg[1]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => p_2_out(0),
      Q => \rx_pad_r_reg[1]_srl2_n_0\
    );
\rx_scp_r_reg[0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => p_8_out(1),
      Q => \rx_scp_r_reg[0]_srl2_n_0\
    );
\rx_scp_r_reg[1]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => p_8_out(0),
      Q => \rx_scp_r_reg[1]_srl2_n_0\
    );
\rx_suf_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg[0]_0\(1),
      Q => L(0),
      R => RESET
    );
\rx_suf_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg[0]_0\(0),
      Q => \rx_suf_r_reg_n_0_[1]\,
      R => RESET
    );
save_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg_n_0_[1]\,
      Q => L(1),
      R => RESET
    );
\stage_1_count_value_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[0]_0\,
      Q => stage_1_count_value_r(0),
      R => RESET
    );
\stage_1_count_value_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[1]_0\,
      Q => stage_1_count_value_r(1),
      R => RESET
    );
\stage_1_count_value_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[2]_0\,
      Q => stage_1_count_value_r(2),
      R => RESET
    );
\stage_1_count_value_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[3]_0\,
      Q => stage_1_count_value_r(3),
      R => RESET
    );
stage_1_pad_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => PDU_PAD(0),
      I1 => PDU_PAD(1),
      O => \PDU_PAD_Buffer_reg[0]_0\
    );
\stage_2_count_value_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => load_ufc_control_code_r,
      I1 => stage_1_count_value_r(0),
      O => \stage_2_count_value_r[0]_i_1_n_0\
    );
\stage_2_count_value_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B888B88888888B8"
    )
        port map (
      I0 => stage_1_count_value_r(1),
      I1 => load_ufc_control_code_r,
      I2 => stage_2_count_value_r(0),
      I3 => stage_2_count_value_r(1),
      I4 => stage_2_count_value_r(3),
      I5 => stage_2_count_value_r(2),
      O => \stage_2_count_value_r[1]_i_1_n_0\
    );
\stage_2_count_value_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"888B888B88888B88"
    )
        port map (
      I0 => stage_1_count_value_r(2),
      I1 => load_ufc_control_code_r,
      I2 => stage_2_count_value_r(2),
      I3 => stage_2_count_value_r(0),
      I4 => stage_2_count_value_r(3),
      I5 => stage_2_count_value_r(1),
      O => \stage_2_count_value_r[2]_i_1_n_0\
    );
\stage_2_count_value_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8B8B8B8888888888"
    )
        port map (
      I0 => stage_1_count_value_r(3),
      I1 => load_ufc_control_code_r,
      I2 => stage_2_count_value_r(0),
      I3 => stage_2_count_value_r(2),
      I4 => stage_2_count_value_r(1),
      I5 => stage_2_count_value_r(3),
      O => \stage_2_count_value_r[3]_i_1_n_0\
    );
\stage_2_count_value_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[0]_i_1_n_0\,
      Q => stage_2_count_value_r(0),
      R => RESET
    );
\stage_2_count_value_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[1]_i_1_n_0\,
      Q => stage_2_count_value_r(1),
      R => RESET
    );
\stage_2_count_value_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[2]_i_1_n_0\,
      Q => stage_2_count_value_r(2),
      R => RESET
    );
\stage_2_count_value_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[3]_i_1_n_0\,
      Q => stage_2_count_value_r(3),
      R => RESET
    );
stage_2_lane_mask_c: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FE"
    )
        port map (
      I0 => stage_2_count_value_r(3),
      I1 => stage_2_count_value_r(2),
      I2 => stage_2_count_value_r(1),
      I3 => stage_2_count_value_r(0),
      O => \stage_2_lane_mask_c__0\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_MUX is
  port (
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    user_clk : in STD_LOGIC;
    UFC_OUTPUT_SELECT_Buffer : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MUXED_DATA_Buffer_reg[16]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[17]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[18]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[19]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[20]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[21]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[22]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[23]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[24]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[25]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[26]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[27]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[28]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[29]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[30]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[31]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_MUX : entity is "aurora_1ln_rx_lpm_UFC_OUTPUT_MUX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_MUX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_MUX is
begin
\MUXED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(15),
      Q => M_AXI_UFC_RX_TDATA(7),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(5),
      Q => M_AXI_UFC_RX_TDATA(13),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(4),
      Q => M_AXI_UFC_RX_TDATA(12),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => M_AXI_UFC_RX_TDATA(11),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => M_AXI_UFC_RX_TDATA(10),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => M_AXI_UFC_RX_TDATA(9),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => M_AXI_UFC_RX_TDATA(8),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[16]_0\,
      Q => M_AXI_UFC_RX_TDATA(23),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[17]_0\,
      Q => M_AXI_UFC_RX_TDATA(22),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[18]_0\,
      Q => M_AXI_UFC_RX_TDATA(21),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[19]_0\,
      Q => M_AXI_UFC_RX_TDATA(20),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(14),
      Q => M_AXI_UFC_RX_TDATA(6),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[20]_0\,
      Q => M_AXI_UFC_RX_TDATA(19),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[21]_0\,
      Q => M_AXI_UFC_RX_TDATA(18),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[22]_0\,
      Q => M_AXI_UFC_RX_TDATA(17),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[23]_0\,
      Q => M_AXI_UFC_RX_TDATA(16),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[24]_0\,
      Q => M_AXI_UFC_RX_TDATA(31),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[25]_0\,
      Q => M_AXI_UFC_RX_TDATA(30),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[26]_0\,
      Q => M_AXI_UFC_RX_TDATA(29),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[27]_0\,
      Q => M_AXI_UFC_RX_TDATA(28),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[28]_0\,
      Q => M_AXI_UFC_RX_TDATA(27),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[29]_0\,
      Q => M_AXI_UFC_RX_TDATA(26),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(13),
      Q => M_AXI_UFC_RX_TDATA(5),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[30]_0\,
      Q => M_AXI_UFC_RX_TDATA(25),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[31]_0\,
      Q => M_AXI_UFC_RX_TDATA(24),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(12),
      Q => M_AXI_UFC_RX_TDATA(4),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(11),
      Q => M_AXI_UFC_RX_TDATA(3),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(10),
      Q => M_AXI_UFC_RX_TDATA(2),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(9),
      Q => M_AXI_UFC_RX_TDATA(1),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(8),
      Q => M_AXI_UFC_RX_TDATA(0),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(7),
      Q => M_AXI_UFC_RX_TDATA(15),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(6),
      Q => M_AXI_UFC_RX_TDATA(14),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL is
  port (
    UFC_OUTPUT_SELECT_Buffer : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \UFC_OUTPUT_SELECT_Buffer_reg[4]_0\ : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL : entity is "aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL is
  signal \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0\ : STD_LOGIC;
begin
\UFC_OUTPUT_SELECT_Buffer[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      O => \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0\
    );
\UFC_OUTPUT_SELECT_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer_reg[4]_0\,
      Q => UFC_OUTPUT_SELECT_Buffer(1),
      R => '0'
    );
\UFC_OUTPUT_SELECT_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0\,
      Q => UFC_OUTPUT_SELECT_Buffer(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT is
  port (
    \UFC_REM_Buffer_reg[0]_0\ : out STD_LOGIC;
    UFC_SRC_RDY_N_Buffer : out STD_LOGIC;
    UFC_EOF_N_Buffer : out STD_LOGIC;
    \UFC_REM_Buffer_reg[0]_1\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    RESET : in STD_LOGIC;
    UFC_SRC_RDY_N_Buffer_reg_0 : in STD_LOGIC;
    UFC_EOF_N_Buffer_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT : entity is "aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT is
begin
UFC_EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_EOF_N_Buffer_reg_0,
      Q => UFC_EOF_N_Buffer,
      R => '0'
    );
\UFC_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_REM_Buffer_reg[0]_1\,
      Q => \UFC_REM_Buffer_reg[0]_0\,
      R => '0'
    );
UFC_SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_SRC_RDY_N_Buffer_reg_0,
      Q => UFC_SRC_RDY_N_Buffer,
      S => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL is
  port (
    stage_1_ufc_start_r_reg : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \storage_count_r_reg[1]_0\ : out STD_LOGIC;
    \storage_count_r_reg[1]_1\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \storage_count_r_reg[0]_0\ : out STD_LOGIC;
    stage_1_ufc_start_r_reg_0 : out STD_LOGIC;
    stage_1_ufc_start_r : in STD_LOGIC;
    UFC_EOF_N_Buffer_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL : entity is "aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL is
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal storage_count_c : STD_LOGIC_VECTOR ( 0 to 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of UFC_EOF_N_Buffer_i_1 : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \UFC_REM_Buffer[0]_i_1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of UFC_SRC_RDY_N_Buffer_i_1 : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \UFC_STORAGE_SELECT_Buffer[0]_i_2\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \UFC_STORAGE_SELECT_Buffer[1]_i_1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \UFC_STORAGE_SELECT_Buffer[5]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \storage_count_r[0]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \storage_count_r[1]_i_1\ : label is "soft_lutpair89";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
UFC_EOF_N_Buffer_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55547733"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => \^q\(0),
      I2 => UFC_EOF_N_Buffer_reg(0),
      I3 => UFC_EOF_N_Buffer_reg(1),
      I4 => \^q\(1),
      O => stage_1_ufc_start_r_reg
    );
\UFC_REM_Buffer[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6433"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => UFC_EOF_N_Buffer_reg(0),
      O => stage_1_ufc_start_r_reg_0
    );
UFC_SRC_RDY_N_Buffer_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \storage_count_r_reg[0]_0\
    );
\UFC_STORAGE_SELECT_Buffer[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \storage_count_r_reg[1]_0\
    );
\UFC_STORAGE_SELECT_Buffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \storage_count_r_reg[1]_1\
    );
\UFC_STORAGE_SELECT_Buffer[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABFF"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => \^q\(1),
      I2 => UFC_EOF_N_Buffer_reg(1),
      I3 => \^q\(0),
      O => D(0)
    );
\storage_count_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"9CC8C8C8"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => UFC_EOF_N_Buffer_reg(1),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => UFC_EOF_N_Buffer_reg(0),
      O => storage_count_c(0)
    );
\storage_count_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAFE5400"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => UFC_EOF_N_Buffer_reg(1),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => UFC_EOF_N_Buffer_reg(0),
      O => storage_count_c(1)
    );
\storage_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => storage_count_c(0),
      Q => \^q\(1),
      R => RESET
    );
\storage_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => storage_count_c(1),
      Q => \^q\(0),
      R => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_MUX is
  port (
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \MUXED_DATA_Buffer_reg[16]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[17]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[18]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[19]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[20]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[21]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[22]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[23]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[24]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[25]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[26]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[27]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[28]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[29]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[30]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[31]_0\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[0]_0\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    UFC_STORAGE_SELECT_Buffer : in STD_LOGIC_VECTOR ( 2 downto 0 );
    SHIFTED_DATA_Buffer : in STD_LOGIC_VECTOR ( 0 to 31 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_MUX : entity is "aurora_1ln_rx_lpm_UFC_STORAGE_MUX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_MUX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_MUX is
  signal \MUXED_DATA_Buffer[0]_i_2_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[10]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[11]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[12]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[13]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[14]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[15]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[16]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[17]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[18]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[19]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[20]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[21]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[22]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[23]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[24]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[25]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[26]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[27]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[28]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[29]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[2]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[30]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[31]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[4]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[5]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[6]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[7]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[8]_i_1_n_0\ : STD_LOGIC;
  signal \MUXED_DATA_Buffer[9]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[0]_i_2\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[10]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[11]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[12]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[13]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[14]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[15]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[16]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[17]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[18]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[19]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[1]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[20]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[21]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[22]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[23]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[24]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[25]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[26]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[27]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[28]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[29]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[2]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[30]_i_1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[31]_i_1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[3]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[4]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[5]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[6]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[7]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[8]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[9]_i_1\ : label is "soft_lutpair104";
begin
\MUXED_DATA_Buffer[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(16),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(0),
      O => \MUXED_DATA_Buffer[0]_i_2_n_0\
    );
\MUXED_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(26),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(10),
      O => \MUXED_DATA_Buffer[10]_i_1_n_0\
    );
\MUXED_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(27),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(11),
      O => \MUXED_DATA_Buffer[11]_i_1_n_0\
    );
\MUXED_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(28),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(12),
      O => \MUXED_DATA_Buffer[12]_i_1_n_0\
    );
\MUXED_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(29),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(13),
      O => \MUXED_DATA_Buffer[13]_i_1_n_0\
    );
\MUXED_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(30),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(14),
      O => \MUXED_DATA_Buffer[14]_i_1_n_0\
    );
\MUXED_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(31),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(15),
      O => \MUXED_DATA_Buffer[15]_i_1_n_0\
    );
\MUXED_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(16),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(0),
      O => \MUXED_DATA_Buffer[16]_i_1_n_0\
    );
\MUXED_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(17),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(1),
      O => \MUXED_DATA_Buffer[17]_i_1_n_0\
    );
\MUXED_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(18),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(2),
      O => \MUXED_DATA_Buffer[18]_i_1_n_0\
    );
\MUXED_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(19),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(3),
      O => \MUXED_DATA_Buffer[19]_i_1_n_0\
    );
\MUXED_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(17),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(1),
      O => \MUXED_DATA_Buffer[1]_i_1_n_0\
    );
\MUXED_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(20),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(4),
      O => \MUXED_DATA_Buffer[20]_i_1_n_0\
    );
\MUXED_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(21),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(5),
      O => \MUXED_DATA_Buffer[21]_i_1_n_0\
    );
\MUXED_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(22),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(6),
      O => \MUXED_DATA_Buffer[22]_i_1_n_0\
    );
\MUXED_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(23),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(7),
      O => \MUXED_DATA_Buffer[23]_i_1_n_0\
    );
\MUXED_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(24),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(8),
      O => \MUXED_DATA_Buffer[24]_i_1_n_0\
    );
\MUXED_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(25),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(9),
      O => \MUXED_DATA_Buffer[25]_i_1_n_0\
    );
\MUXED_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(26),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(10),
      O => \MUXED_DATA_Buffer[26]_i_1_n_0\
    );
\MUXED_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(27),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(11),
      O => \MUXED_DATA_Buffer[27]_i_1_n_0\
    );
\MUXED_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(28),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(12),
      O => \MUXED_DATA_Buffer[28]_i_1_n_0\
    );
\MUXED_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(29),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(13),
      O => \MUXED_DATA_Buffer[29]_i_1_n_0\
    );
\MUXED_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(18),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(2),
      O => \MUXED_DATA_Buffer[2]_i_1_n_0\
    );
\MUXED_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(30),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(14),
      O => \MUXED_DATA_Buffer[30]_i_1_n_0\
    );
\MUXED_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(31),
      I1 => UFC_STORAGE_SELECT_Buffer(0),
      I2 => SHIFTED_DATA_Buffer(15),
      O => \MUXED_DATA_Buffer[31]_i_1_n_0\
    );
\MUXED_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(19),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(3),
      O => \MUXED_DATA_Buffer[3]_i_1_n_0\
    );
\MUXED_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(20),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(4),
      O => \MUXED_DATA_Buffer[4]_i_1_n_0\
    );
\MUXED_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(21),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(5),
      O => \MUXED_DATA_Buffer[5]_i_1_n_0\
    );
\MUXED_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(22),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(6),
      O => \MUXED_DATA_Buffer[6]_i_1_n_0\
    );
\MUXED_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(23),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(7),
      O => \MUXED_DATA_Buffer[7]_i_1_n_0\
    );
\MUXED_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(24),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(8),
      O => \MUXED_DATA_Buffer[8]_i_1_n_0\
    );
\MUXED_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(25),
      I1 => UFC_STORAGE_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(9),
      O => \MUXED_DATA_Buffer[9]_i_1_n_0\
    );
\MUXED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[0]_i_2_n_0\,
      Q => D(15),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[10]_i_1_n_0\,
      Q => D(5),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[11]_i_1_n_0\,
      Q => D(4),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[12]_i_1_n_0\,
      Q => D(3),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[13]_i_1_n_0\,
      Q => D(2),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[14]_i_1_n_0\,
      Q => D(1),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[15]_i_1_n_0\,
      Q => D(0),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[16]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[16]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[17]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[17]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[18]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[18]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[19]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[19]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[1]_i_1_n_0\,
      Q => D(14),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[20]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[20]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[21]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[21]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[22]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[22]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[23]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[23]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[24]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[24]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[25]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[25]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[26]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[26]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[27]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[27]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[28]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[28]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[29]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[29]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[2]_i_1_n_0\,
      Q => D(13),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[30]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[30]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[31]_i_1_n_0\,
      Q => \MUXED_DATA_Buffer_reg[31]_0\,
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[3]_i_1_n_0\,
      Q => D(12),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[4]_i_1_n_0\,
      Q => D(11),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[5]_i_1_n_0\,
      Q => D(10),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[6]_i_1_n_0\,
      Q => D(9),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[7]_i_1_n_0\,
      Q => D(8),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[8]_i_1_n_0\,
      Q => D(7),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
\MUXED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer[9]_i_1_n_0\,
      Q => D(6),
      R => \MUXED_DATA_Buffer_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL is
  port (
    \UFC_STORAGE_SELECT_Buffer_reg[0]_0\ : out STD_LOGIC;
    \UFC_STORAGE_SELECT_Buffer_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    \UFC_STORAGE_SELECT_Buffer_reg[0]_1\ : in STD_LOGIC;
    \UFC_STORAGE_SELECT_Buffer_reg[1]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \UFC_STORAGE_SELECT_Buffer_reg[4]_0\ : in STD_LOGIC;
    stage_1_ufc_start_r : in STD_LOGIC;
    \UFC_STORAGE_SELECT_Buffer_reg[4]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL : entity is "aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL is
  signal UFC_STORAGE_SELECT_Buffer : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\ : STD_LOGIC;
begin
\MUXED_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => UFC_STORAGE_SELECT_Buffer(0),
      I1 => UFC_STORAGE_SELECT_Buffer(1),
      O => \UFC_STORAGE_SELECT_Buffer_reg[0]_0\
    );
\UFC_STORAGE_SELECT_Buffer[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABABBF"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => Q(1),
      I2 => \UFC_STORAGE_SELECT_Buffer_reg[4]_1\(1),
      I3 => \UFC_STORAGE_SELECT_Buffer_reg[4]_1\(0),
      I4 => Q(0),
      O => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_STORAGE_SELECT_Buffer_reg[0]_1\,
      Q => UFC_STORAGE_SELECT_Buffer(0),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_STORAGE_SELECT_Buffer_reg[1]_0\,
      Q => UFC_STORAGE_SELECT_Buffer(1),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => \UFC_STORAGE_SELECT_Buffer_reg[2]_0\(2),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_STORAGE_SELECT_Buffer_reg[4]_0\,
      Q => \UFC_STORAGE_SELECT_Buffer_reg[2]_0\(1),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \UFC_STORAGE_SELECT_Buffer_reg[2]_0\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER is
  port (
    \COUNT_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER : entity is "aurora_1ln_rx_lpm_VALID_DATA_COUNTER";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER is
  signal \COUNT_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \COUNT_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \COUNT_Buffer[0]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \COUNT_Buffer[1]_i_1\ : label is "soft_lutpair109";
begin
\COUNT_Buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => Q(0),
      I1 => Q(1),
      O => \COUNT_Buffer[0]_i_1_n_0\
    );
\COUNT_Buffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      O => \COUNT_Buffer[1]_i_1_n_0\
    );
\COUNT_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \COUNT_Buffer[0]_i_1_n_0\,
      Q => \COUNT_Buffer_reg[0]_0\(1),
      R => RESET
    );
\COUNT_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \COUNT_Buffer[1]_i_1_n_0\,
      Q => \COUNT_Buffer_reg[0]_0\(0),
      R => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15 is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    end_storage_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    end_storage_r0 : out STD_LOGIC;
    std_bool2_in : out STD_LOGIC;
    std_bool6_in : out STD_LOGIC;
    \STORAGE_CE_Buffer_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    stage_3_end_storage_r : in STD_LOGIC;
    stage_2_start_with_data_r : in STD_LOGIC;
    stage_2_end_before_start_r : in STD_LOGIC;
    stage_2_end_after_start_r : in STD_LOGIC;
    RESET : in STD_LOGIC;
    \COUNT_Buffer_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15 : entity is "aurora_1ln_rx_lpm_VALID_DATA_COUNTER";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15 is
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal stage_2_data_v_count_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^std_bool2_in\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of SRC_RDY_N_Buffer_i_3 : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of end_storage_r_i_2 : label is "soft_lutpair46";
begin
  Q(0) <= \^q\(0);
  std_bool2_in <= \^std_bool2_in\;
\COUNT_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \COUNT_Buffer_reg[0]_0\(1),
      Q => stage_2_data_v_count_r(0),
      R => RESET
    );
\COUNT_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \COUNT_Buffer_reg[0]_0\(0),
      Q => \^q\(0),
      R => RESET
    );
SRC_RDY_N_Buffer_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE0"
    )
        port map (
      I0 => \^q\(0),
      I1 => \STORAGE_CE_Buffer_reg[0]\(0),
      I2 => \STORAGE_CE_Buffer_reg[0]\(1),
      I3 => stage_2_data_v_count_r(0),
      O => std_bool6_in
    );
\STORAGE_CE_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFAEF"
    )
        port map (
      I0 => stage_2_data_v_count_r(0),
      I1 => \^q\(0),
      I2 => \STORAGE_CE_Buffer_reg[0]\(1),
      I3 => \STORAGE_CE_Buffer_reg[0]\(0),
      I4 => stage_3_end_storage_r,
      I5 => stage_2_start_with_data_r,
      O => D(1)
    );
\STORAGE_CE_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => stage_2_data_v_count_r(0),
      I1 => \STORAGE_CE_Buffer_reg[0]\(0),
      I2 => \^q\(0),
      I3 => \STORAGE_CE_Buffer_reg[0]\(1),
      I4 => stage_3_end_storage_r,
      I5 => stage_2_start_with_data_r,
      O => D(0)
    );
end_storage_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F404"
    )
        port map (
      I0 => \^std_bool2_in\,
      I1 => stage_2_end_before_start_r,
      I2 => stage_2_start_with_data_r,
      I3 => stage_2_end_after_start_r,
      O => end_storage_r0
    );
end_storage_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^q\(0),
      I1 => \STORAGE_CE_Buffer_reg[0]\(0),
      I2 => \STORAGE_CE_Buffer_reg[0]\(1),
      I3 => stage_2_data_v_count_r(0),
      O => \^std_bool2_in\
    );
\storage_count_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFEEF10011000"
    )
        port map (
      I0 => stage_3_end_storage_r,
      I1 => stage_2_start_with_data_r,
      I2 => \^q\(0),
      I3 => \STORAGE_CE_Buffer_reg[0]\(0),
      I4 => \STORAGE_CE_Buffer_reg[0]\(1),
      I5 => stage_2_data_v_count_r(0),
      O => end_storage_r_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync is
  port (
    \out\ : out STD_LOGIC;
    HPCNT_RESET : out STD_LOGIC;
    GT_RESET : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    \hotplug_count_synth.count_for_reset_r_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync : entity is "aurora_1ln_rx_lpm_cdc_sync";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
  p_level_in_int <= GT_RESET;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
\hotplug_count_synth.count_for_reset_r[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => s_level_out_d3,
      I1 => \hotplug_count_synth.count_for_reset_r_reg[0]\,
      O => HPCNT_RESET
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_0 is
  port (
    \out\ : out STD_LOGIC;
    RX_SYSTEM_RESET : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_0 : entity is "aurora_1ln_rx_lpm_cdc_sync";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_0;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_0 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
  p_level_in_int <= RX_SYSTEM_RESET;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_1 is
  port (
    \out\ : out STD_LOGIC;
    RX_SYSTEM_RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_1 : entity is "aurora_1ln_rx_lpm_cdc_sync";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_1;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_1 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
  p_level_in_int <= RX_SYSTEM_RESET;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_11 is
  port (
    \out\ : out STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_11 : entity is "aurora_1ln_rx_lpm_cdc_sync";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_11;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_11 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => p_level_in_int
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_3 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC;
    TX_LOCK : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    reset_time_out_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_1\ : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_3\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_4\ : in STD_LOGIC;
    rxresetdone_s3 : in STD_LOGIC;
    reset_time_out_reg_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_3 : entity is "aurora_1ln_rx_lpm_cdc_sync";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_3;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_3 is
  signal \FSM_sequential_rx_state[3]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_7_n_0\ : STD_LOGIC;
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal reset_time_out_i_2_n_0 : STD_LOGIC;
  signal reset_time_out_i_3_n_0 : STD_LOGIC;
  signal reset_time_out_i_4_n_0 : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  p_level_in_int <= TX_LOCK;
\FSM_sequential_rx_state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_3_n_0\,
      I1 => \FSM_sequential_rx_state_reg[0]\,
      I2 => \FSM_sequential_rx_state_reg[0]_0\,
      I3 => reset_time_out_reg_0,
      I4 => \FSM_sequential_rx_state[3]_i_7_n_0\,
      I5 => \FSM_sequential_rx_state_reg[0]_1\,
      O => E(0)
    );
\FSM_sequential_rx_state[3]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => reset_time_out_reg_2,
      I1 => s_level_out_d3,
      O => \FSM_sequential_rx_state[3]_i_13_n_0\
    );
\FSM_sequential_rx_state[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000400040004"
    )
        port map (
      I0 => reset_time_out_reg_1,
      I1 => \FSM_sequential_rx_state_reg[0]_2\,
      I2 => \FSM_sequential_rx_state_reg[0]_3\,
      I3 => Q(3),
      I4 => \FSM_sequential_rx_state_reg[0]_4\,
      I5 => \FSM_sequential_rx_state[3]_i_13_n_0\,
      O => \FSM_sequential_rx_state[3]_i_3_n_0\
    );
\FSM_sequential_rx_state[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5410000000000000"
    )
        port map (
      I0 => Q(3),
      I1 => Q(2),
      I2 => s_level_out_d3,
      I3 => rxresetdone_s3,
      I4 => Q(1),
      I5 => Q(0),
      O => \FSM_sequential_rx_state[3]_i_7_n_0\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
reset_time_out_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFFFFFEEE0000"
    )
        port map (
      I0 => reset_time_out_reg_0,
      I1 => reset_time_out_i_2_n_0,
      I2 => Q(1),
      I3 => reset_time_out_i_3_n_0,
      I4 => reset_time_out_i_4_n_0,
      I5 => reset_time_out_reg_1,
      O => \FSM_sequential_rx_state_reg[1]\
    );
reset_time_out_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => Q(1),
      I1 => reset_time_out_reg_2,
      I2 => s_level_out_d3,
      I3 => Q(3),
      I4 => Q(2),
      O => reset_time_out_i_2_n_0
    );
reset_time_out_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00AC"
    )
        port map (
      I0 => rxresetdone_s3,
      I1 => s_level_out_d3,
      I2 => Q(2),
      I3 => Q(3),
      O => reset_time_out_i_3_n_0
    );
reset_time_out_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"330233023FCC3CCC"
    )
        port map (
      I0 => reset_time_out_reg,
      I1 => Q(3),
      I2 => Q(1),
      I3 => Q(0),
      I4 => \FSM_sequential_rx_state[3]_i_13_n_0\,
      I5 => Q(2),
      O => reset_time_out_i_4_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_4 is
  port (
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_4 : entity is "aurora_1ln_rx_lpm_cdc_sync";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_4;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_4 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => p_level_in_int
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_6 is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    mmcm_lock_reclocked_reg : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    mmcm_lock_reclocked : in STD_LOGIC;
    mmcm_lock_reclocked_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_6 : entity is "aurora_1ln_rx_lpm_cdc_sync";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_6;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_6 is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => p_level_in_int
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => p_level_in_d1_cdc_from
    );
\mmcm_lock_count[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => s_level_out_d3,
      O => SR(0)
    );
mmcm_lock_reclocked_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => mmcm_lock_reclocked_reg_0,
      I2 => s_level_out_d3,
      O => mmcm_lock_reclocked_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2\ is
  port (
    \out\ : out STD_LOGIC;
    GTRXRESET_OUT : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => GTRXRESET_OUT,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_10\ is
  port (
    rxpmaresetdone_i : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_10\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_10\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_10\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rxpmaresetdone_i,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_12\ is
  port (
    \out\ : out STD_LOGIC;
    time_out_wait_bypass : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_12\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_12\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_12\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => time_out_wait_bypass,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_13\ is
  port (
    \out\ : out STD_LOGIC;
    link_reset_r : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_13\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_13\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_13\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_14\ is
  port (
    \out\ : out STD_LOGIC;
    tx_lock_comb_r : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_14\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_14\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_14\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => tx_lock_comb_r,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_16\ is
  port (
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[23]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[25]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rx_cc_extend_r2 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    \hotplug_count_synth.count_for_reset_r_reg\ : in STD_LOGIC_VECTOR ( 25 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_16\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_16\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_16\ is
  signal \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
\hotplug_count_synth.count_for_reset_r[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I1 => s_level_out_d3,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0\,
      O(3 downto 0) => O(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[15]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[19]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[23]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0\,
      CO(3 downto 1) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[25]\(1 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[7]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[11]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0\
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_2\ is
  port (
    \out\ : out STD_LOGIC;
    fsm_gt_rx_reset_t : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_2\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_2\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_2\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => fsm_gt_rx_reset_t,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_5\ is
  port (
    \out\ : out STD_LOGIC;
    rxfsm_rxresetdone_r : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_5\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_5\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_5\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rxfsm_rxresetdone_r,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_7\ is
  port (
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_7\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_7\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_7\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => '0',
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_8\ is
  port (
    \out\ : out STD_LOGIC;
    run_phase_alignment_int : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_8\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_8\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_8\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => run_phase_alignment_int,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_9\ is
  port (
    \out\ : out STD_LOGIC;
    rx_fsm_reset_done_int : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_9\ : entity is "aurora_1ln_rx_lpm_cdc_sync";
end \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_9\;

architecture STRUCTURE of \aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_9\ is
  signal p_level_in_d1_cdc_from : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of p_level_in_d1_cdc_from : signal is "true";
  signal p_level_in_int : STD_LOGIC;
  signal s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of s_level_out_d1_aurora_1ln_rx_lpm_cdc_to : signal is "no";
  signal s_level_out_d2 : STD_LOGIC;
  attribute async_reg of s_level_out_d2 : signal is "true";
  attribute shift_extract of s_level_out_d2 : signal is "no";
  signal s_level_out_d3 : STD_LOGIC;
  attribute async_reg of s_level_out_d3 : signal is "true";
  attribute shift_extract of s_level_out_d3 : signal is "no";
  signal s_level_out_d4 : STD_LOGIC;
  attribute async_reg of s_level_out_d4 : signal is "true";
  attribute shift_extract of s_level_out_d4 : signal is "no";
  signal s_level_out_d5 : STD_LOGIC;
  attribute async_reg of s_level_out_d5 : signal is "true";
  attribute shift_extract of s_level_out_d5 : signal is "no";
  signal s_level_out_d6 : STD_LOGIC;
  attribute async_reg of s_level_out_d6 : signal is "true";
  attribute shift_extract of s_level_out_d6 : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= s_level_out_d3;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_fsm_reset_done_int,
      Q => p_level_in_d1_cdc_from,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_level_in_int,
      Q => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d1_aurora_1ln_rx_lpm_cdc_to,
      Q => s_level_out_d2,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d2,
      Q => s_level_out_d3,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d3,
      Q => s_level_out_d4,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d4,
      Q => s_level_out_d5,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_level_out_d5,
      Q => s_level_out_d6,
      R => '0'
    );
p_level_in_d1_cdc_from_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_level_in_d1_cdc_from,
      O => p_level_in_int
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_gt is
  port (
    TX_LOCK : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rx_realign_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RXDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RXCHARISK : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ack_flag : out STD_LOGIC;
    hard_err_gt0 : out STD_LOGIC;
    inc_count_r0 : out STD_LOGIC;
    inc_count_r_reg : out STD_LOGIC;
    init_clk_in_0 : out STD_LOGIC;
    \previous_cycle_data_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \left_align_select_r_reg[1]\ : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC;
    RXP : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    fsm_gt_rx_reset_t : in STD_LOGIC;
    gt_qpllclk_quad1_in : in STD_LOGIC;
    gt_qpllrefclk_quad1_in : in STD_LOGIC;
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i : in STD_LOGIC;
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    begin_r : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \word_aligned_data_r_reg[22]\ : in STD_LOGIC;
    \word_aligned_data_r_reg[22]_0\ : in STD_LOGIC;
    enable_err_detect_i : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_gt : entity is "aurora_1ln_rx_lpm_gt";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_gt;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_gt is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D_0 : STD_LOGIC;
  signal \^rxcharisk\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^rxdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^ack_flag\ : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal flag2 : STD_LOGIC;
  signal flag_i_1_n_0 : STD_LOGIC;
  signal gt0_pllrefclklost_i : STD_LOGIC;
  signal \^gt0_rx_disp_err_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^gt0_rx_not_in_table_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^gt0_rx_realign_out\ : STD_LOGIC;
  signal \^gt0_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_112 : STD_LOGIC;
  signal gthe2_i_n_113 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_5 : STD_LOGIC;
  signal gthe2_i_n_54 : STD_LOGIC;
  signal gthe2_i_n_6 : STD_LOGIC;
  signal gthe2_i_n_624 : STD_LOGIC;
  signal gthe2_i_n_625 : STD_LOGIC;
  signal gthe2_i_n_626 : STD_LOGIC;
  signal gthe2_i_n_627 : STD_LOGIC;
  signal gthe2_i_n_628 : STD_LOGIC;
  signal gthe2_i_n_629 : STD_LOGIC;
  signal gthe2_i_n_630 : STD_LOGIC;
  signal gthe2_i_n_631 : STD_LOGIC;
  signal gthe2_i_n_632 : STD_LOGIC;
  signal gthe2_i_n_633 : STD_LOGIC;
  signal gthe2_i_n_634 : STD_LOGIC;
  signal gthe2_i_n_635 : STD_LOGIC;
  signal gthe2_i_n_636 : STD_LOGIC;
  signal gthe2_i_n_637 : STD_LOGIC;
  signal gthe2_i_n_638 : STD_LOGIC;
  signal gthe2_i_n_639 : STD_LOGIC;
  signal rx_char_is_comma_i : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXCHBONDO_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \soft_err_r[0]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \soft_err_r[1]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \soft_err_r[2]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \soft_err_r[3]_i_1\ : label is "soft_lutpair113";
begin
  RXCHARISK(3 downto 0) <= \^rxcharisk\(3 downto 0);
  RXDATA(31 downto 0) <= \^rxdata\(31 downto 0);
  ack_flag <= \^ack_flag\;
  gt0_rx_disp_err_out(3 downto 0) <= \^gt0_rx_disp_err_out\(3 downto 0);
  gt0_rx_not_in_table_out(3 downto 0) <= \^gt0_rx_not_in_table_out\(3 downto 0);
  gt0_rx_realign_out <= \^gt0_rx_realign_out\;
  gt0_rxbufstatus_out(2 downto 0) <= \^gt0_rxbufstatus_out\(2 downto 0);
  gthe2_i_n_624 <= 'Z';
  gthe2_i_n_625 <= 'Z';
  gthe2_i_n_626 <= 'Z';
  gthe2_i_n_627 <= 'Z';
  gthe2_i_n_628 <= 'Z';
  gthe2_i_n_629 <= 'Z';
  gthe2_i_n_630 <= 'Z';
  gthe2_i_n_631 <= 'Z';
  gthe2_i_n_632 <= 'Z';
  gthe2_i_n_633 <= 'Z';
  gthe2_i_n_634 <= 'Z';
  gthe2_i_n_635 <= 'Z';
  gthe2_i_n_636 <= 'Z';
  gthe2_i_n_637 <= 'Z';
  gthe2_i_n_638 <= 'Z';
  gthe2_i_n_639 <= 'Z';
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => \^ack_flag\,
      I3 => flag2,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => \^ack_flag\,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D_0,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag2_reg_0,
      Q => flag2,
      R => '0'
    );
flag_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \^ack_flag\,
      I1 => cpll_reset_i,
      I2 => D_0,
      O => flag_i_1_n_0
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag_i_1_n_0,
      Q => D_0,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 31,
      CLK_COR_MIN_LAT => 24,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0111110111",
      CLK_COR_SEQ_1_4 => B"0111110111",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 4,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 40,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 1,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 40,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 1,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => TX_LOCK,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => gt0_pllrefclklost_i,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN => DRPEN_IN,
      DRPRDY => DRPRDY_OUT,
      DRPWE => DRPWE_IN,
      EYESCANDATAERROR => gt0_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt0_eyescanreset_in,
      EYESCANTRIGGER => gt0_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => RXN,
      GTHRXP => RXP,
      GTHTXN => gthe2_i_n_5,
      GTHTXP => gthe2_i_n_6,
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => SR(0),
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => fsm_gt_rx_reset_t,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad1_in,
      QPLLREFCLK => gt_qpllrefclk_quad1_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => gt0_rxbufreset_in,
      RXBUFSTATUS(2 downto 0) => \^gt0_rxbufstatus_out\(2 downto 0),
      RXBYTEISALIGNED => gt0_rxbyteisaligned_out,
      RXBYTEREALIGN => \^gt0_rx_realign_out\,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => gt0_rxcdrhold_in,
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => gt0_rxcdrovrden_in,
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED,
      RXCHANISALIGNED => NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED,
      RXCHANREALIGN => NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED,
      RXCHARISCOMMA(7 downto 4) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 4),
      RXCHARISCOMMA(3 downto 0) => rx_char_is_comma_i(3 downto 0),
      RXCHARISK(7 downto 4) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 4),
      RXCHARISK(3 downto 0) => \^rxcharisk\(3 downto 0),
      RXCHBONDEN => '0',
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4 downto 0) => NLW_gthe2_i_RXCHBONDO_UNCONNECTED(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt0_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 32) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 32),
      RXDATA(31 downto 0) => \^rxdata\(31 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => gt0_rxdfelpmreset_in,
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 4) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 4),
      RXDISPERR(3 downto 0) => \^gt0_rx_disp_err_out\(3 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => gt0_rxlpmen_in,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => ena_comma_align_i,
      RXMONITOROUT(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 4) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 4),
      RXNOTINTABLE(3 downto 0) => \^gt0_rx_not_in_table_out\(3 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => ena_comma_align_i,
      RXPCSRESET => gt0_rxpcsreset_in,
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => gt0_rxpmareset_in,
      RXPMARESETDONE => gt0_rxpmaresetdone_out,
      RXPOLARITY => rx_polarity_i,
      RXPRBSCNTRESET => gt0_rxprbscntreset_in,
      RXPRBSERR => gt0_rxprbserr_out,
      RXPRBSSEL(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt0_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1) => gthe2_i_n_112,
      TXBUFSTATUS(0) => gthe2_i_n_113,
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 0) => B"00000000",
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 32) => B"00000000000000000000000000000000",
      TXDATA(31) => gthe2_i_n_624,
      TXDATA(30) => gthe2_i_n_625,
      TXDATA(29) => gthe2_i_n_626,
      TXDATA(28) => gthe2_i_n_627,
      TXDATA(27) => gthe2_i_n_628,
      TXDATA(26) => gthe2_i_n_629,
      TXDATA(25) => gthe2_i_n_630,
      TXDATA(24) => gthe2_i_n_631,
      TXDATA(23) => gthe2_i_n_632,
      TXDATA(22) => gthe2_i_n_633,
      TXDATA(21) => gthe2_i_n_634,
      TXDATA(20) => gthe2_i_n_635,
      TXDATA(19) => gthe2_i_n_636,
      TXDATA(18) => gthe2_i_n_637,
      TXDATA(17) => gthe2_i_n_638,
      TXDATA(16) => gthe2_i_n_639,
      TXDATA(15 downto 0) => B"0000000000000000",
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => TX_OUT_CLK,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => '0',
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gthe2_i_n_54,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => '1',
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
hard_err_gt_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt0_rx_realign_out\,
      I1 => \^gt0_rxbufstatus_out\(2),
      O => hard_err_gt0
    );
inc_count_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0116FFFF"
    )
        port map (
      I0 => rx_char_is_comma_i(0),
      I1 => rx_char_is_comma_i(1),
      I2 => rx_char_is_comma_i(3),
      I3 => rx_char_is_comma_i(2),
      I4 => ena_comma_align_i,
      O => inc_count_r0
    );
reset_count_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^gt0_rx_disp_err_out\(3),
      I1 => \^gt0_rx_not_in_table_out\(3),
      I2 => \^gt0_rx_not_in_table_out\(1),
      I3 => \^gt0_rx_disp_err_out\(1),
      I4 => \^gt0_rx_disp_err_out\(0),
      I5 => \^gt0_rx_disp_err_out\(2),
      O => init_clk_in_0
    );
reset_count_r_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^gt0_rx_not_in_table_out\(2),
      I1 => \^gt0_rx_not_in_table_out\(0),
      I2 => E(0),
      I3 => begin_r,
      O => inc_count_r_reg
    );
\soft_err_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => enable_err_detect_i,
      I1 => \^gt0_rx_disp_err_out\(0),
      I2 => \^gt0_rx_not_in_table_out\(0),
      O => ENABLE_ERR_DETECT_Buffer_reg(3)
    );
\soft_err_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \^gt0_rx_disp_err_out\(1),
      I1 => \^gt0_rx_not_in_table_out\(1),
      I2 => enable_err_detect_i,
      O => ENABLE_ERR_DETECT_Buffer_reg(2)
    );
\soft_err_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => enable_err_detect_i,
      I1 => \^gt0_rx_disp_err_out\(2),
      I2 => \^gt0_rx_not_in_table_out\(2),
      O => ENABLE_ERR_DETECT_Buffer_reg(1)
    );
\soft_err_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \^gt0_rx_disp_err_out\(3),
      I1 => \^gt0_rx_not_in_table_out\(3),
      I2 => enable_err_detect_i,
      O => ENABLE_ERR_DETECT_Buffer_reg(0)
    );
\word_aligned_control_bits_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCAAF000CCAAF0"
    )
        port map (
      I0 => \^rxcharisk\(0),
      I1 => \^rxcharisk\(1),
      I2 => \^rxcharisk\(3),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxcharisk\(2),
      O => \left_align_select_r_reg[1]\
    );
\word_aligned_data_r[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => \^rxdata\(23),
      I1 => Q(3),
      I2 => \^rxdata\(15),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(7),
      O => \previous_cycle_data_r_reg[7]\(3)
    );
\word_aligned_data_r[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => \^rxdata\(21),
      I1 => Q(2),
      I2 => \^rxdata\(13),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(5),
      O => \previous_cycle_data_r_reg[7]\(2)
    );
\word_aligned_data_r[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => \^rxdata\(19),
      I1 => Q(1),
      I2 => \^rxdata\(3),
      I3 => \word_aligned_data_r_reg[22]_0\,
      I4 => \word_aligned_data_r_reg[22]\,
      I5 => \^rxdata\(11),
      O => \previous_cycle_data_r_reg[7]\(1)
    );
\word_aligned_data_r[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => \^rxdata\(17),
      I1 => Q(0),
      I2 => \^rxdata\(9),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(1),
      O => \previous_cycle_data_r_reg[7]\(0)
    );
\word_aligned_data_r[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCF0AA00CCF0AA"
    )
        port map (
      I0 => \^rxdata\(31),
      I1 => \^rxdata\(7),
      I2 => \^rxdata\(15),
      I3 => \word_aligned_data_r_reg[22]_0\,
      I4 => \word_aligned_data_r_reg[22]\,
      I5 => \^rxdata\(23),
      O => D(7)
    );
\word_aligned_data_r[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \^rxdata\(6),
      I1 => \^rxdata\(22),
      I2 => \^rxdata\(30),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(14),
      O => D(6)
    );
\word_aligned_data_r[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => \^rxdata\(29),
      I1 => \^rxdata\(5),
      I2 => \^rxdata\(21),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(13),
      O => D(5)
    );
\word_aligned_data_r[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \^rxdata\(4),
      I1 => \^rxdata\(20),
      I2 => \^rxdata\(28),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(12),
      O => D(4)
    );
\word_aligned_data_r[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCAAF000CCAAF0"
    )
        port map (
      I0 => \^rxdata\(3),
      I1 => \^rxdata\(11),
      I2 => \^rxdata\(27),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(19),
      O => D(3)
    );
\word_aligned_data_r[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFCCAAF000CCAAF0"
    )
        port map (
      I0 => \^rxdata\(2),
      I1 => \^rxdata\(10),
      I2 => \^rxdata\(26),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(18),
      O => D(2)
    );
\word_aligned_data_r[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFCCAAF000CCAA"
    )
        port map (
      I0 => \^rxdata\(25),
      I1 => \^rxdata\(1),
      I2 => \^rxdata\(17),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(9),
      O => D(1)
    );
\word_aligned_data_r[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCFFAAF0CC00AAF0"
    )
        port map (
      I0 => \^rxdata\(0),
      I1 => \^rxdata\(16),
      I2 => \^rxdata\(24),
      I3 => \word_aligned_data_r_reg[22]\,
      I4 => \word_aligned_data_r_reg[22]_0\,
      I5 => \^rxdata\(8),
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_HOTPLUG is
  port (
    LINK_RESET_OUT : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_HOTPLUG : entity is "aurora_1ln_rx_lpm_HOTPLUG";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_HOTPLUG;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_HOTPLUG is
  signal \hotplug_count_synth.count_for_reset_r_reg\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal link_reset_0 : STD_LOGIC;
  signal link_reset_r_i_2_n_0 : STD_LOGIC;
  signal link_reset_r_i_3_n_0 : STD_LOGIC;
  signal link_reset_r_i_4_n_0 : STD_LOGIC;
  signal link_reset_r_i_5_n_0 : STD_LOGIC;
  signal link_reset_r_i_6_n_0 : STD_LOGIC;
  signal link_reset_r_reg_n_0 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_0 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_1 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_10 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_11 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_12 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_13 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_14 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_15 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_16 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_17 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_18 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_19 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_2 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_20 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_21 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_22 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_23 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_24 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_25 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_3 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_4 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_5 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_6 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_7 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_8 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_9 : STD_LOGIC;
  signal rx_cc_extend_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_cc_extend_r2 : STD_LOGIC;
  signal rx_cc_extend_r2_i_1_n_0 : STD_LOGIC;
  signal rx_cc_extend_r2_i_2_n_0 : STD_LOGIC;
begin
\hotplug_count_synth.count_for_reset_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_3,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(0)
    );
\hotplug_count_synth.count_for_reset_r_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_9,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(10)
    );
\hotplug_count_synth.count_for_reset_r_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_8,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(11)
    );
\hotplug_count_synth.count_for_reset_r_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_15,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(12)
    );
\hotplug_count_synth.count_for_reset_r_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_14,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(13)
    );
\hotplug_count_synth.count_for_reset_r_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_13,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(14)
    );
\hotplug_count_synth.count_for_reset_r_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_12,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(15)
    );
\hotplug_count_synth.count_for_reset_r_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_19,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(16)
    );
\hotplug_count_synth.count_for_reset_r_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_18,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(17)
    );
\hotplug_count_synth.count_for_reset_r_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_17,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(18)
    );
\hotplug_count_synth.count_for_reset_r_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_16,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(19)
    );
\hotplug_count_synth.count_for_reset_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_2,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(1)
    );
\hotplug_count_synth.count_for_reset_r_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_23,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(20)
    );
\hotplug_count_synth.count_for_reset_r_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_22,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(21)
    );
\hotplug_count_synth.count_for_reset_r_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_21,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(22)
    );
\hotplug_count_synth.count_for_reset_r_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_20,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(23)
    );
\hotplug_count_synth.count_for_reset_r_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_25,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(24)
    );
\hotplug_count_synth.count_for_reset_r_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_24,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(25)
    );
\hotplug_count_synth.count_for_reset_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_1,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(2)
    );
\hotplug_count_synth.count_for_reset_r_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_0,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(3)
    );
\hotplug_count_synth.count_for_reset_r_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_7,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(4)
    );
\hotplug_count_synth.count_for_reset_r_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_6,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(5)
    );
\hotplug_count_synth.count_for_reset_r_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_5,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(6)
    );
\hotplug_count_synth.count_for_reset_r_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_4,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(7)
    );
\hotplug_count_synth.count_for_reset_r_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_11,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(8)
    );
\hotplug_count_synth.count_for_reset_r_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_10,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(9)
    );
\hotplug_enable.LINK_RESET_OUT_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r_reg_n_0,
      Q => LINK_RESET_OUT,
      R => '0'
    );
link_reset_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => link_reset_r_i_2_n_0,
      I1 => link_reset_r_i_3_n_0,
      I2 => link_reset_r_i_4_n_0,
      I3 => link_reset_r_i_5_n_0,
      I4 => link_reset_r_i_6_n_0,
      O => link_reset_0
    );
link_reset_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      O => link_reset_r_i_2_n_0
    );
link_reset_r_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78F8F8F8"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      O => link_reset_r_i_3_n_0
    );
link_reset_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      O => link_reset_r_i_4_n_0
    );
link_reset_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      O => link_reset_r_i_5_n_0
    );
link_reset_r_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      O => link_reset_r_i_6_n_0
    );
link_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_0,
      Q => link_reset_r_reg_n_0,
      R => '0'
    );
rx_cc_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_16\
     port map (
      O(3) => rx_cc_cdc_sync_n_0,
      O(2) => rx_cc_cdc_sync_n_1,
      O(1) => rx_cc_cdc_sync_n_2,
      O(0) => rx_cc_cdc_sync_n_3,
      \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0) => \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0),
      \hotplug_count_synth.count_for_reset_r_reg[11]\(3) => rx_cc_cdc_sync_n_8,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(2) => rx_cc_cdc_sync_n_9,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(1) => rx_cc_cdc_sync_n_10,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(0) => rx_cc_cdc_sync_n_11,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(3) => rx_cc_cdc_sync_n_12,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(2) => rx_cc_cdc_sync_n_13,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(1) => rx_cc_cdc_sync_n_14,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(0) => rx_cc_cdc_sync_n_15,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(3) => rx_cc_cdc_sync_n_16,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(2) => rx_cc_cdc_sync_n_17,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(1) => rx_cc_cdc_sync_n_18,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(0) => rx_cc_cdc_sync_n_19,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(3) => rx_cc_cdc_sync_n_20,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(2) => rx_cc_cdc_sync_n_21,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(1) => rx_cc_cdc_sync_n_22,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(0) => rx_cc_cdc_sync_n_23,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(1) => rx_cc_cdc_sync_n_24,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(0) => rx_cc_cdc_sync_n_25,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(3) => rx_cc_cdc_sync_n_4,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(2) => rx_cc_cdc_sync_n_5,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(1) => rx_cc_cdc_sync_n_6,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(0) => rx_cc_cdc_sync_n_7,
      init_clk_in => init_clk_in,
      rx_cc_extend_r2 => rx_cc_extend_r2,
      user_clk => user_clk
    );
rx_cc_extend_r2_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => rx_cc_extend_r(2),
      I1 => rx_cc_extend_r(3),
      I2 => rx_cc_extend_r(0),
      I3 => rx_cc_extend_r(1),
      I4 => rx_cc_extend_r2_i_2_n_0,
      O => rx_cc_extend_r2_i_1_n_0
    );
rx_cc_extend_r2_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rx_cc_extend_r(5),
      I1 => rx_cc_extend_r(4),
      I2 => rx_cc_extend_r(7),
      I3 => rx_cc_extend_r(6),
      O => rx_cc_extend_r2_i_2_n_0
    );
rx_cc_extend_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2_i_1_n_0,
      Q => rx_cc_extend_r2,
      R => '0'
    );
\rx_cc_extend_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(1),
      Q => rx_cc_extend_r(0),
      R => SR(0)
    );
\rx_cc_extend_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(2),
      Q => rx_cc_extend_r(1),
      R => SR(0)
    );
\rx_cc_extend_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(3),
      Q => rx_cc_extend_r(2),
      R => SR(0)
    );
\rx_cc_extend_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(4),
      Q => rx_cc_extend_r(3),
      R => SR(0)
    );
\rx_cc_extend_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(5),
      Q => rx_cc_extend_r(4),
      R => SR(0)
    );
\rx_cc_extend_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(6),
      Q => rx_cc_extend_r(5),
      R => SR(0)
    );
\rx_cc_extend_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(7),
      Q => rx_cc_extend_r(6),
      R => SR(0)
    );
\rx_cc_extend_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => rx_cc_extend_r(7),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RESET_LOGIC is
  port (
    link_reset_r : out STD_LOGIC;
    sys_reset_out : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    LINK_RESET_OUT : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    TX_LOCK : in STD_LOGIC;
    gt_rxresetdone_r2_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RESET_LOGIC : entity is "aurora_1ln_rx_lpm_RESET_LOGIC";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RESET_LOGIC;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RESET_LOGIC is
  signal SYSTEM_RESET0_n_0 : STD_LOGIC;
  signal gt_rxresetdone_r : STD_LOGIC;
  signal gt_rxresetdone_r2 : STD_LOGIC;
  signal gt_rxresetdone_r3 : STD_LOGIC;
  signal \^link_reset_r\ : STD_LOGIC;
  signal scndry_out : STD_LOGIC;
  signal tx_lock_comb_r : STD_LOGIC;
  signal tx_lock_sync : STD_LOGIC;
begin
  link_reset_r <= \^link_reset_r\;
SYSTEM_RESET0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => tx_lock_sync,
      I1 => \out\,
      I2 => gt_rxresetdone_r3,
      I3 => scndry_out,
      O => SYSTEM_RESET0_n_0
    );
SYSTEM_RESET_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => SYSTEM_RESET0_n_0,
      Q => sys_reset_out,
      R => '0'
    );
gt_rxresetdone_r2_reg: unisim.vcomponents.FDCE
     port map (
      C => user_clk,
      CE => '1',
      CLR => gt_rxresetdone_r2_reg_0,
      D => gt_rxresetdone_r,
      Q => gt_rxresetdone_r2
    );
gt_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt_rxresetdone_r2,
      Q => gt_rxresetdone_r3,
      R => '0'
    );
gt_rxresetdone_r_reg: unisim.vcomponents.FDCE
     port map (
      C => user_clk,
      CE => '1',
      CLR => gt_rxresetdone_r2_reg_0,
      D => '1',
      Q => gt_rxresetdone_r
    );
link_reset_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_13\
     port map (
      init_clk_in => init_clk_in,
      link_reset_r => \^link_reset_r\,
      \out\ => scndry_out,
      user_clk => user_clk
    );
link_reset_comb_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => LINK_RESET_OUT,
      Q => \^link_reset_r\,
      R => '0'
    );
tx_lock_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_14\
     port map (
      init_clk_in => init_clk_in,
      \out\ => tx_lock_sync,
      tx_lock_comb_r => tx_lock_comb_r,
      user_clk => user_clk
    );
tx_lock_comb_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => TX_LOCK,
      Q => tx_lock_comb_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    GTRXRESET_OUT : out STD_LOGIC;
    RX_CHANNEL_UP : out STD_LOGIC;
    SOFT_ERR : out STD_LOGIC;
    RX_HARD_ERR : out STD_LOGIC;
    START_RX : out STD_LOGIC;
    RESET : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    GOT_V : in STD_LOGIC;
    rx_hard_err_i : in STD_LOGIC;
    RX_LANE_UP : in STD_LOGIC;
    START_RX_Buffer_reg : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX : entity is "aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX is
  signal reset_channel_i : STD_LOGIC;
  signal wait_for_lane_up_r0 : STD_LOGIC;
begin
rx_channel_err_detect_simplex_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX
     port map (
      D(1 downto 0) => D(1 downto 0),
      POWER_DOWN => POWER_DOWN,
      RX_HARD_ERR => RX_HARD_ERR,
      RX_LANE_UP => RX_LANE_UP,
      SOFT_ERR => SOFT_ERR,
      reset_channel_i => reset_channel_i,
      rx_hard_err_i => rx_hard_err_i,
      user_clk => user_clk,
      wait_for_lane_up_r0 => wait_for_lane_up_r0,
      wait_for_lane_up_r_reg => START_RX_Buffer_reg
    );
rx_channel_init_sm_simplex_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX
     port map (
      GOT_V => GOT_V,
      GTRXRESET_OUT => GTRXRESET_OUT,
      RESET => RESET,
      RX_CHANNEL_UP => RX_CHANNEL_UP,
      SR(0) => SR(0),
      START_RX => START_RX,
      START_RX_Buffer_reg_0 => START_RX_Buffer_reg,
      reset_channel_i => reset_channel_i,
      user_clk => user_clk,
      wait_for_lane_up_r0 => wait_for_lane_up_r0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH is
  port (
    rx_eof : out STD_LOGIC;
    FRAME_ERR : out STD_LOGIC;
    M_AXI_RX_TLAST : out STD_LOGIC;
    M_AXI_RX_TVALID : out STD_LOGIC;
    \RX_REM_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \IN_FRAME_Buffer_reg[1]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    in_frame_r_reg : in STD_LOGIC;
    S1_in : in STD_LOGIC;
    \AFTER_SCP_Buffer_reg[1]\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    RESET : in STD_LOGIC;
    stage_1_pad_r_reg_0 : in STD_LOGIC;
    START_RX : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stage_1_ecp_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stage_2_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH : entity is "aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH is
  signal EOF_N_Buffer : STD_LOGIC;
  signal FRAME_ERR_RESULT_Buffer : STD_LOGIC;
  signal FRAME_ERR_RESULT_Buffer0 : STD_LOGIC;
  signal MUX_SELECT : STD_LOGIC_VECTOR ( 2 to 2 );
  signal OUTPUT_SELECT_Buffer : STD_LOGIC;
  signal RX_REM_Buffer : STD_LOGIC_VECTOR ( 0 to 1 );
  signal RX_SRC_RDY_N_Buffer : STD_LOGIC;
  signal SRC_RDY_N_Buffer : STD_LOGIC;
  signal STORAGE_DATA : STD_LOGIC_VECTOR ( 0 to 31 );
  signal STORAGE_SELECT_Buffer : STD_LOGIC_VECTOR ( 4 to 9 );
  signal ce_command_c : STD_LOGIC_VECTOR ( 0 to 1 );
  signal end_storage_r0 : STD_LOGIC;
  signal mux_select_c : STD_LOGIC_VECTOR ( 2 to 2 );
  signal output_select_c : STD_LOGIC_VECTOR ( 9 to 9 );
  signal p_0_in0 : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^rx_eof\ : STD_LOGIC;
  signal sideband_output_i_n_1 : STD_LOGIC;
  signal sideband_output_i_n_5 : STD_LOGIC;
  signal stage_1_ecp_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal stage_1_pad_r : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_1 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_2 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_3 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_4 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_5 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_6 : STD_LOGIC;
  signal stage_1_scp_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal stage_2_data_r : STD_LOGIC_VECTOR ( 0 to 31 );
  signal stage_2_data_v_count_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal stage_2_end_after_start_r : STD_LOGIC;
  signal stage_2_end_before_start_r : STD_LOGIC;
  signal stage_2_frame_err_r : STD_LOGIC;
  signal stage_2_pad_r : STD_LOGIC;
  signal stage_2_start_with_data_r : STD_LOGIC;
  signal stage_2_valid_data_counter_i_n_3 : STD_LOGIC;
  signal stage_3_end_storage_r : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_16 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_17 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_18 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_19 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_20 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_21 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_22 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_23 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_24 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_25 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_26 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_27 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_28 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_29 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_30 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_31 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_32 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_33 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_34 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_35 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_36 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_37 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_38 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_39 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_40 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_41 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_42 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_43 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_44 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_45 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_46 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_47 : STD_LOGIC;
  signal stage_3_storage_ce_control_i_n_1 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_4 : STD_LOGIC;
  signal stage_3_storage_count_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal std_bool2_in : STD_LOGIC;
  signal std_bool6_in : STD_LOGIC;
begin
  rx_eof <= \^rx_eof\;
FRAME_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => FRAME_ERR_RESULT_Buffer,
      Q => FRAME_ERR,
      R => RESET
    );
M_AXI_RX_TLAST_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rx_eof\,
      O => M_AXI_RX_TLAST
    );
M_AXI_RX_TVALID_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => RX_SRC_RDY_N_Buffer,
      O => M_AXI_RX_TVALID
    );
RX_EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EOF_N_Buffer,
      Q => \^rx_eof\,
      R => '0'
    );
\RX_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_REM_Buffer(0),
      Q => \RX_REM_Buffer_reg[0]_0\(1),
      R => '0'
    );
\RX_REM_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_REM_Buffer(1),
      Q => \RX_REM_Buffer_reg[0]_0\(0),
      R => '0'
    );
RX_SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => SRC_RDY_N_Buffer,
      Q => RX_SRC_RDY_N_Buffer,
      S => RESET
    );
output_mux_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_MUX
     port map (
      M_AXI_RX_TDATA(31 downto 0) => M_AXI_RX_TDATA(31 downto 0),
      \OUTPUT_DATA_Buffer_reg[16]_0\(15 downto 0) => p_1_in(15 downto 0),
      OUTPUT_SELECT_Buffer => OUTPUT_SELECT_Buffer,
      Q(31) => STORAGE_DATA(0),
      Q(30) => STORAGE_DATA(1),
      Q(29) => STORAGE_DATA(2),
      Q(28) => STORAGE_DATA(3),
      Q(27) => STORAGE_DATA(4),
      Q(26) => STORAGE_DATA(5),
      Q(25) => STORAGE_DATA(6),
      Q(24) => STORAGE_DATA(7),
      Q(23) => STORAGE_DATA(8),
      Q(22) => STORAGE_DATA(9),
      Q(21) => STORAGE_DATA(10),
      Q(20) => STORAGE_DATA(11),
      Q(19) => STORAGE_DATA(12),
      Q(18) => STORAGE_DATA(13),
      Q(17) => STORAGE_DATA(14),
      Q(16) => STORAGE_DATA(15),
      Q(15) => STORAGE_DATA(16),
      Q(14) => STORAGE_DATA(17),
      Q(13) => STORAGE_DATA(18),
      Q(12) => STORAGE_DATA(19),
      Q(11) => STORAGE_DATA(20),
      Q(10) => STORAGE_DATA(21),
      Q(9) => STORAGE_DATA(22),
      Q(8) => STORAGE_DATA(23),
      Q(7) => STORAGE_DATA(24),
      Q(6) => STORAGE_DATA(25),
      Q(5) => STORAGE_DATA(26),
      Q(4) => STORAGE_DATA(27),
      Q(3) => STORAGE_DATA(28),
      Q(2) => STORAGE_DATA(29),
      Q(1) => STORAGE_DATA(30),
      Q(0) => STORAGE_DATA(31),
      user_clk => user_clk
    );
sideband_output_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SIDEBAND_OUTPUT
     port map (
      D(0) => sideband_output_i_n_5,
      EOF_N_Buffer => EOF_N_Buffer,
      EOF_N_Buffer_reg_0 => stage_3_storage_count_control_i_n_4,
      FRAME_ERR_RESULT_Buffer => FRAME_ERR_RESULT_Buffer,
      FRAME_ERR_RESULT_Buffer0 => FRAME_ERR_RESULT_Buffer0,
      Q(0) => stage_3_storage_count_r(1),
      \RX_REM_Buffer_reg[0]_0\(1) => RX_REM_Buffer(0),
      \RX_REM_Buffer_reg[0]_0\(0) => RX_REM_Buffer(1),
      \RX_REM_Buffer_reg[0]_1\(0) => stage_2_data_v_count_r(1),
      SR(0) => sideband_output_i_n_1,
      SRC_RDY_N_Buffer => SRC_RDY_N_Buffer,
      START_RX => START_RX,
      end_storage_r0 => end_storage_r0,
      stage_2_end_before_start_r => stage_2_end_before_start_r,
      stage_2_frame_err_r => stage_2_frame_err_r,
      stage_2_pad_r => stage_2_pad_r,
      stage_2_start_with_data_r => stage_2_start_with_data_r,
      stage_3_end_storage_r => stage_3_end_storage_r,
      std_bool6_in => std_bool6_in,
      user_clk => user_clk
    );
\stage_1_ecp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_ecp_r_reg[0]_0\(1),
      Q => stage_1_ecp_r(0),
      R => '0'
    );
\stage_1_ecp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_ecp_r_reg[0]_0\(0),
      Q => stage_1_ecp_r(1),
      R => '0'
    );
stage_1_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_pad_r_reg_0,
      Q => stage_1_pad_r,
      R => '0'
    );
stage_1_rx_ll_deframer_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_DEFRAMER
     port map (
      \AFTER_SCP_Buffer_reg[0]_0\ => stage_1_rx_ll_deframer_i_n_1,
      \AFTER_SCP_Buffer_reg[0]_1\ => stage_1_rx_ll_deframer_i_n_2,
      \AFTER_SCP_Buffer_reg[0]_2\ => stage_1_rx_ll_deframer_i_n_3,
      \AFTER_SCP_Buffer_reg[1]_0\ => \AFTER_SCP_Buffer_reg[1]\,
      D(1 downto 0) => D(1 downto 0),
      \DEFRAMED_DATA_V_Buffer_reg[0]_0\(1 downto 0) => Q(1 downto 0),
      \DEFRAMED_DATA_V_Buffer_reg[1]_0\(1) => stage_1_rx_ll_deframer_i_n_4,
      \DEFRAMED_DATA_V_Buffer_reg[1]_0\(0) => stage_1_rx_ll_deframer_i_n_5,
      \IN_FRAME_Buffer_reg[1]_0\ => \IN_FRAME_Buffer_reg[1]\,
      Q(1) => stage_1_ecp_r(0),
      Q(0) => stage_1_ecp_r(1),
      RESET => RESET,
      S1_in => S1_in,
      in_frame_r_reg_0 => in_frame_r_reg,
      mux_select_c(0) => mux_select_c(2),
      \stage_1_ecp_r_reg[0]\ => stage_1_rx_ll_deframer_i_n_6,
      stage_2_frame_err_r_reg(1) => stage_1_scp_r(0),
      stage_2_frame_err_r_reg(0) => stage_1_scp_r(1),
      user_clk => user_clk
    );
\stage_1_scp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => stage_1_scp_r(0),
      R => '0'
    );
\stage_1_scp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => stage_1_scp_r(1),
      R => '0'
    );
\stage_2_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(31),
      Q => stage_2_data_r(0),
      R => '0'
    );
\stage_2_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(21),
      Q => stage_2_data_r(10),
      R => '0'
    );
\stage_2_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(20),
      Q => stage_2_data_r(11),
      R => '0'
    );
\stage_2_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(19),
      Q => stage_2_data_r(12),
      R => '0'
    );
\stage_2_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(18),
      Q => stage_2_data_r(13),
      R => '0'
    );
\stage_2_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(17),
      Q => stage_2_data_r(14),
      R => '0'
    );
\stage_2_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(16),
      Q => stage_2_data_r(15),
      R => '0'
    );
\stage_2_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(15),
      Q => stage_2_data_r(16),
      R => '0'
    );
\stage_2_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(14),
      Q => stage_2_data_r(17),
      R => '0'
    );
\stage_2_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(13),
      Q => stage_2_data_r(18),
      R => '0'
    );
\stage_2_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(12),
      Q => stage_2_data_r(19),
      R => '0'
    );
\stage_2_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(30),
      Q => stage_2_data_r(1),
      R => '0'
    );
\stage_2_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(11),
      Q => stage_2_data_r(20),
      R => '0'
    );
\stage_2_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(10),
      Q => stage_2_data_r(21),
      R => '0'
    );
\stage_2_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(9),
      Q => stage_2_data_r(22),
      R => '0'
    );
\stage_2_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(8),
      Q => stage_2_data_r(23),
      R => '0'
    );
\stage_2_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(7),
      Q => stage_2_data_r(24),
      R => '0'
    );
\stage_2_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(6),
      Q => stage_2_data_r(25),
      R => '0'
    );
\stage_2_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(5),
      Q => stage_2_data_r(26),
      R => '0'
    );
\stage_2_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(4),
      Q => stage_2_data_r(27),
      R => '0'
    );
\stage_2_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(3),
      Q => stage_2_data_r(28),
      R => '0'
    );
\stage_2_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(2),
      Q => stage_2_data_r(29),
      R => '0'
    );
\stage_2_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(29),
      Q => stage_2_data_r(2),
      R => '0'
    );
\stage_2_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(1),
      Q => stage_2_data_r(30),
      R => '0'
    );
\stage_2_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(0),
      Q => stage_2_data_r(31),
      R => '0'
    );
\stage_2_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(28),
      Q => stage_2_data_r(3),
      R => '0'
    );
\stage_2_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(27),
      Q => stage_2_data_r(4),
      R => '0'
    );
\stage_2_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(26),
      Q => stage_2_data_r(5),
      R => '0'
    );
\stage_2_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(25),
      Q => stage_2_data_r(6),
      R => '0'
    );
\stage_2_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(24),
      Q => stage_2_data_r(7),
      R => '0'
    );
\stage_2_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(23),
      Q => stage_2_data_r(8),
      R => '0'
    );
\stage_2_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(22),
      Q => stage_2_data_r(9),
      R => '0'
    );
stage_2_end_after_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_rx_ll_deframer_i_n_3,
      Q => stage_2_end_after_start_r,
      R => RESET
    );
stage_2_end_before_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_rx_ll_deframer_i_n_2,
      Q => stage_2_end_before_start_r,
      R => RESET
    );
stage_2_frame_err_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_rx_ll_deframer_i_n_6,
      Q => stage_2_frame_err_r,
      R => RESET
    );
stage_2_left_align_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL
     port map (
      MUX_SELECT(0) => MUX_SELECT(2),
      mux_select_c(0) => mux_select_c(2),
      user_clk => user_clk
    );
stage_2_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_pad_r,
      Q => stage_2_pad_r,
      R => '0'
    );
stage_2_start_with_data_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_rx_ll_deframer_i_n_1,
      Q => stage_2_start_with_data_r,
      R => RESET
    );
stage_2_valid_data_counter_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15
     port map (
      \COUNT_Buffer_reg[0]_0\(1) => stage_1_rx_ll_deframer_i_n_4,
      \COUNT_Buffer_reg[0]_0\(0) => stage_1_rx_ll_deframer_i_n_5,
      D(1) => ce_command_c(0),
      D(0) => ce_command_c(1),
      Q(0) => stage_2_data_v_count_r(1),
      RESET => RESET,
      \STORAGE_CE_Buffer_reg[0]\(1) => stage_3_storage_count_r(0),
      \STORAGE_CE_Buffer_reg[0]\(0) => stage_3_storage_count_r(1),
      end_storage_r0 => end_storage_r0,
      end_storage_r_reg(0) => stage_2_valid_data_counter_i_n_3,
      stage_2_end_after_start_r => stage_2_end_after_start_r,
      stage_2_end_before_start_r => stage_2_end_before_start_r,
      stage_2_start_with_data_r => stage_2_start_with_data_r,
      stage_3_end_storage_r => stage_3_end_storage_r,
      std_bool2_in => std_bool2_in,
      std_bool6_in => std_bool6_in,
      user_clk => user_clk
    );
stage_3_left_align_datapath_mux_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_MUX
     port map (
      D(31) => stage_3_left_align_datapath_mux_i_n_16,
      D(30) => stage_3_left_align_datapath_mux_i_n_17,
      D(29) => stage_3_left_align_datapath_mux_i_n_18,
      D(28) => stage_3_left_align_datapath_mux_i_n_19,
      D(27) => stage_3_left_align_datapath_mux_i_n_20,
      D(26) => stage_3_left_align_datapath_mux_i_n_21,
      D(25) => stage_3_left_align_datapath_mux_i_n_22,
      D(24) => stage_3_left_align_datapath_mux_i_n_23,
      D(23) => stage_3_left_align_datapath_mux_i_n_24,
      D(22) => stage_3_left_align_datapath_mux_i_n_25,
      D(21) => stage_3_left_align_datapath_mux_i_n_26,
      D(20) => stage_3_left_align_datapath_mux_i_n_27,
      D(19) => stage_3_left_align_datapath_mux_i_n_28,
      D(18) => stage_3_left_align_datapath_mux_i_n_29,
      D(17) => stage_3_left_align_datapath_mux_i_n_30,
      D(16) => stage_3_left_align_datapath_mux_i_n_31,
      D(15) => stage_3_left_align_datapath_mux_i_n_32,
      D(14) => stage_3_left_align_datapath_mux_i_n_33,
      D(13) => stage_3_left_align_datapath_mux_i_n_34,
      D(12) => stage_3_left_align_datapath_mux_i_n_35,
      D(11) => stage_3_left_align_datapath_mux_i_n_36,
      D(10) => stage_3_left_align_datapath_mux_i_n_37,
      D(9) => stage_3_left_align_datapath_mux_i_n_38,
      D(8) => stage_3_left_align_datapath_mux_i_n_39,
      D(7) => stage_3_left_align_datapath_mux_i_n_40,
      D(6) => stage_3_left_align_datapath_mux_i_n_41,
      D(5) => stage_3_left_align_datapath_mux_i_n_42,
      D(4) => stage_3_left_align_datapath_mux_i_n_43,
      D(3) => stage_3_left_align_datapath_mux_i_n_44,
      D(2) => stage_3_left_align_datapath_mux_i_n_45,
      D(1) => stage_3_left_align_datapath_mux_i_n_46,
      D(0) => stage_3_left_align_datapath_mux_i_n_47,
      \MUXED_DATA_Buffer_reg[0]_0\(15 downto 0) => p_1_in(15 downto 0),
      MUX_SELECT(0) => MUX_SELECT(2),
      Q(31) => stage_2_data_r(0),
      Q(30) => stage_2_data_r(1),
      Q(29) => stage_2_data_r(2),
      Q(28) => stage_2_data_r(3),
      Q(27) => stage_2_data_r(4),
      Q(26) => stage_2_data_r(5),
      Q(25) => stage_2_data_r(6),
      Q(24) => stage_2_data_r(7),
      Q(23) => stage_2_data_r(8),
      Q(22) => stage_2_data_r(9),
      Q(21) => stage_2_data_r(10),
      Q(20) => stage_2_data_r(11),
      Q(19) => stage_2_data_r(12),
      Q(18) => stage_2_data_r(13),
      Q(17) => stage_2_data_r(14),
      Q(16) => stage_2_data_r(15),
      Q(15) => stage_2_data_r(16),
      Q(14) => stage_2_data_r(17),
      Q(13) => stage_2_data_r(18),
      Q(12) => stage_2_data_r(19),
      Q(11) => stage_2_data_r(20),
      Q(10) => stage_2_data_r(21),
      Q(9) => stage_2_data_r(22),
      Q(8) => stage_2_data_r(23),
      Q(7) => stage_2_data_r(24),
      Q(6) => stage_2_data_r(25),
      Q(5) => stage_2_data_r(26),
      Q(4) => stage_2_data_r(27),
      Q(3) => stage_2_data_r(28),
      Q(2) => stage_2_data_r(29),
      Q(1) => stage_2_data_r(30),
      Q(0) => stage_2_data_r(31),
      STORAGE_SELECT_Buffer(1) => STORAGE_SELECT_Buffer(4),
      STORAGE_SELECT_Buffer(0) => STORAGE_SELECT_Buffer(9),
      user_clk => user_clk
    );
stage_3_output_switch_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL
     port map (
      OUTPUT_SELECT_Buffer => OUTPUT_SELECT_Buffer,
      output_select_c(0) => output_select_c(9),
      user_clk => user_clk
    );
stage_3_storage_ce_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_CE_CONTROL
     port map (
      D(1) => ce_command_c(0),
      D(0) => ce_command_c(1),
      Q(1) => p_0_in0,
      Q(0) => stage_3_storage_ce_control_i_n_1,
      RESET => RESET,
      user_clk => user_clk
    );
stage_3_storage_count_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL
     port map (
      D(1) => stage_2_valid_data_counter_i_n_3,
      D(0) => sideband_output_i_n_5,
      FRAME_ERR_RESULT_Buffer0 => FRAME_ERR_RESULT_Buffer0,
      Q(1) => stage_3_storage_count_r(0),
      Q(0) => stage_3_storage_count_r(1),
      SR(0) => sideband_output_i_n_1,
      end_storage_r_reg => stage_3_storage_count_control_i_n_4,
      output_select_c(0) => output_select_c(9),
      stage_2_end_after_start_r => stage_2_end_after_start_r,
      stage_2_end_before_start_r => stage_2_end_before_start_r,
      stage_2_frame_err_r => stage_2_frame_err_r,
      stage_2_start_with_data_r => stage_2_start_with_data_r,
      stage_3_end_storage_r => stage_3_end_storage_r,
      std_bool2_in => std_bool2_in,
      user_clk => user_clk
    );
stage_3_storage_switch_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL
     port map (
      Q(0) => stage_3_storage_count_r(1),
      STORAGE_SELECT_Buffer(1) => STORAGE_SELECT_Buffer(4),
      STORAGE_SELECT_Buffer(0) => STORAGE_SELECT_Buffer(9),
      stage_2_start_with_data_r => stage_2_start_with_data_r,
      stage_3_end_storage_r => stage_3_end_storage_r,
      user_clk => user_clk
    );
stage_4_storage_mux_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_MUX
     port map (
      D(31) => stage_3_left_align_datapath_mux_i_n_16,
      D(30) => stage_3_left_align_datapath_mux_i_n_17,
      D(29) => stage_3_left_align_datapath_mux_i_n_18,
      D(28) => stage_3_left_align_datapath_mux_i_n_19,
      D(27) => stage_3_left_align_datapath_mux_i_n_20,
      D(26) => stage_3_left_align_datapath_mux_i_n_21,
      D(25) => stage_3_left_align_datapath_mux_i_n_22,
      D(24) => stage_3_left_align_datapath_mux_i_n_23,
      D(23) => stage_3_left_align_datapath_mux_i_n_24,
      D(22) => stage_3_left_align_datapath_mux_i_n_25,
      D(21) => stage_3_left_align_datapath_mux_i_n_26,
      D(20) => stage_3_left_align_datapath_mux_i_n_27,
      D(19) => stage_3_left_align_datapath_mux_i_n_28,
      D(18) => stage_3_left_align_datapath_mux_i_n_29,
      D(17) => stage_3_left_align_datapath_mux_i_n_30,
      D(16) => stage_3_left_align_datapath_mux_i_n_31,
      D(15) => stage_3_left_align_datapath_mux_i_n_32,
      D(14) => stage_3_left_align_datapath_mux_i_n_33,
      D(13) => stage_3_left_align_datapath_mux_i_n_34,
      D(12) => stage_3_left_align_datapath_mux_i_n_35,
      D(11) => stage_3_left_align_datapath_mux_i_n_36,
      D(10) => stage_3_left_align_datapath_mux_i_n_37,
      D(9) => stage_3_left_align_datapath_mux_i_n_38,
      D(8) => stage_3_left_align_datapath_mux_i_n_39,
      D(7) => stage_3_left_align_datapath_mux_i_n_40,
      D(6) => stage_3_left_align_datapath_mux_i_n_41,
      D(5) => stage_3_left_align_datapath_mux_i_n_42,
      D(4) => stage_3_left_align_datapath_mux_i_n_43,
      D(3) => stage_3_left_align_datapath_mux_i_n_44,
      D(2) => stage_3_left_align_datapath_mux_i_n_45,
      D(1) => stage_3_left_align_datapath_mux_i_n_46,
      D(0) => stage_3_left_align_datapath_mux_i_n_47,
      E(1) => p_0_in0,
      E(0) => stage_3_storage_ce_control_i_n_1,
      Q(31) => STORAGE_DATA(0),
      Q(30) => STORAGE_DATA(1),
      Q(29) => STORAGE_DATA(2),
      Q(28) => STORAGE_DATA(3),
      Q(27) => STORAGE_DATA(4),
      Q(26) => STORAGE_DATA(5),
      Q(25) => STORAGE_DATA(6),
      Q(24) => STORAGE_DATA(7),
      Q(23) => STORAGE_DATA(8),
      Q(22) => STORAGE_DATA(9),
      Q(21) => STORAGE_DATA(10),
      Q(20) => STORAGE_DATA(11),
      Q(19) => STORAGE_DATA(12),
      Q(18) => STORAGE_DATA(13),
      Q(17) => STORAGE_DATA(14),
      Q(16) => STORAGE_DATA(15),
      Q(15) => STORAGE_DATA(16),
      Q(14) => STORAGE_DATA(17),
      Q(13) => STORAGE_DATA(18),
      Q(12) => STORAGE_DATA(19),
      Q(11) => STORAGE_DATA(20),
      Q(10) => STORAGE_DATA(21),
      Q(9) => STORAGE_DATA(22),
      Q(8) => STORAGE_DATA(23),
      Q(7) => STORAGE_DATA(24),
      Q(6) => STORAGE_DATA(25),
      Q(5) => STORAGE_DATA(26),
      Q(4) => STORAGE_DATA(27),
      Q(3) => STORAGE_DATA(28),
      Q(2) => STORAGE_DATA(29),
      Q(1) => STORAGE_DATA(30),
      Q(0) => STORAGE_DATA(31),
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH is
  port (
    \stage_1_data_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_UFC_RX_TVALID : out STD_LOGIC;
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_UFC_RX_TKEEP : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_UFC_RX_TLAST : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    RESET : in STD_LOGIC;
    UFC_START : in STD_LOGIC;
    barrel_shifter_control_i : in STD_LOGIC;
    \stage_1_data_r_reg[0]_1\ : in STD_LOGIC;
    \stage_1_data_r_reg[1]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[2]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[3]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[4]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[5]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[6]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[7]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[8]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[9]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[10]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[11]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[12]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[13]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[14]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[15]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[16]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[17]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[18]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[19]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[20]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[21]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[22]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[23]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[24]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[25]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[26]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[27]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[28]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[29]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[30]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[31]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH : entity is "aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH is
  signal BARREL_SHIFTER_CONTROL_Buffer : STD_LOGIC;
  signal SHIFTED_DATA_Buffer : STD_LOGIC_VECTOR ( 0 to 31 );
  signal UFC_EOF_N_Buffer : STD_LOGIC;
  signal UFC_OUTPUT_SELECT_Buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal UFC_RX_REM_Buffer : STD_LOGIC_VECTOR ( 0 to 0 );
  signal UFC_RX_SRC_RDY_N_Buffer : STD_LOGIC;
  signal UFC_SRC_RDY_N_Buffer : STD_LOGIC;
  signal UFC_STORAGE_SELECT_Buffer : STD_LOGIC_VECTOR ( 2 to 5 );
  signal barrel_shifted_count_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal rx_ufc_eof : STD_LOGIC;
  signal \^stage_1_data_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal stage_1_ufc_start_r : STD_LOGIC;
  signal storage_count_2x_c : STD_LOGIC_VECTOR ( 1 to 1 );
  signal ufc_barrel_shifter_i_n_32 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_33 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_34 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_35 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_36 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_37 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_38 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_39 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_40 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_41 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_42 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_43 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_44 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_45 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_46 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_47 : STD_LOGIC;
  signal ufc_sideband_output_i_n_0 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_0 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_1 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_3 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_4 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_5 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_6 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_7 : STD_LOGIC;
  signal ufc_storage_mux_i_n_0 : STD_LOGIC;
  signal ufc_storage_mux_i_n_1 : STD_LOGIC;
  signal ufc_storage_mux_i_n_10 : STD_LOGIC;
  signal ufc_storage_mux_i_n_11 : STD_LOGIC;
  signal ufc_storage_mux_i_n_12 : STD_LOGIC;
  signal ufc_storage_mux_i_n_13 : STD_LOGIC;
  signal ufc_storage_mux_i_n_14 : STD_LOGIC;
  signal ufc_storage_mux_i_n_15 : STD_LOGIC;
  signal ufc_storage_mux_i_n_16 : STD_LOGIC;
  signal ufc_storage_mux_i_n_17 : STD_LOGIC;
  signal ufc_storage_mux_i_n_18 : STD_LOGIC;
  signal ufc_storage_mux_i_n_19 : STD_LOGIC;
  signal ufc_storage_mux_i_n_2 : STD_LOGIC;
  signal ufc_storage_mux_i_n_20 : STD_LOGIC;
  signal ufc_storage_mux_i_n_21 : STD_LOGIC;
  signal ufc_storage_mux_i_n_22 : STD_LOGIC;
  signal ufc_storage_mux_i_n_23 : STD_LOGIC;
  signal ufc_storage_mux_i_n_24 : STD_LOGIC;
  signal ufc_storage_mux_i_n_25 : STD_LOGIC;
  signal ufc_storage_mux_i_n_26 : STD_LOGIC;
  signal ufc_storage_mux_i_n_27 : STD_LOGIC;
  signal ufc_storage_mux_i_n_28 : STD_LOGIC;
  signal ufc_storage_mux_i_n_29 : STD_LOGIC;
  signal ufc_storage_mux_i_n_3 : STD_LOGIC;
  signal ufc_storage_mux_i_n_30 : STD_LOGIC;
  signal ufc_storage_mux_i_n_31 : STD_LOGIC;
  signal ufc_storage_mux_i_n_4 : STD_LOGIC;
  signal ufc_storage_mux_i_n_5 : STD_LOGIC;
  signal ufc_storage_mux_i_n_6 : STD_LOGIC;
  signal ufc_storage_mux_i_n_7 : STD_LOGIC;
  signal ufc_storage_mux_i_n_8 : STD_LOGIC;
  signal ufc_storage_mux_i_n_9 : STD_LOGIC;
  signal \ufc_storage_switch_control_i/_n_0\ : STD_LOGIC;
  signal ufc_storage_switch_control_i_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \M_AXI_UFC_RX_TKEEP[2]_INST_0\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of M_AXI_UFC_RX_TLAST_INST_0 : label is "soft_lutpair110";
begin
  \stage_1_data_r_reg[0]_0\(31 downto 0) <= \^stage_1_data_r_reg[0]_0\(31 downto 0);
\M_AXI_UFC_RX_TKEEP[2]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rx_ufc_eof,
      I1 => UFC_RX_REM_Buffer(0),
      O => M_AXI_UFC_RX_TKEEP(0)
    );
M_AXI_UFC_RX_TLAST_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_ufc_eof,
      O => M_AXI_UFC_RX_TLAST
    );
M_AXI_UFC_RX_TVALID_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => UFC_RX_SRC_RDY_N_Buffer,
      O => M_AXI_UFC_RX_TVALID
    );
UFC_RX_EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_EOF_N_Buffer,
      Q => rx_ufc_eof,
      R => '0'
    );
\UFC_RX_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ufc_sideband_output_i_n_0,
      Q => UFC_RX_REM_Buffer(0),
      R => '0'
    );
UFC_RX_SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_SRC_RDY_N_Buffer,
      Q => UFC_RX_SRC_RDY_N_Buffer,
      S => RESET
    );
\stage_1_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[0]_1\,
      Q => \^stage_1_data_r_reg[0]_0\(31),
      R => '0'
    );
\stage_1_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[10]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(21),
      R => '0'
    );
\stage_1_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[11]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(20),
      R => '0'
    );
\stage_1_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[12]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(19),
      R => '0'
    );
\stage_1_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[13]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(18),
      R => '0'
    );
\stage_1_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[14]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(17),
      R => '0'
    );
\stage_1_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[15]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(16),
      R => '0'
    );
\stage_1_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[16]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(15),
      R => '0'
    );
\stage_1_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[17]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(14),
      R => '0'
    );
\stage_1_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[18]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(13),
      R => '0'
    );
\stage_1_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[19]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(12),
      R => '0'
    );
\stage_1_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[1]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(30),
      R => '0'
    );
\stage_1_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[20]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(11),
      R => '0'
    );
\stage_1_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[21]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(10),
      R => '0'
    );
\stage_1_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[22]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(9),
      R => '0'
    );
\stage_1_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[23]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(8),
      R => '0'
    );
\stage_1_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[24]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(7),
      R => '0'
    );
\stage_1_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[25]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(6),
      R => '0'
    );
\stage_1_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[26]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(5),
      R => '0'
    );
\stage_1_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[27]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(4),
      R => '0'
    );
\stage_1_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[28]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(3),
      R => '0'
    );
\stage_1_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[29]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(2),
      R => '0'
    );
\stage_1_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[2]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(29),
      R => '0'
    );
\stage_1_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[30]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(1),
      R => '0'
    );
\stage_1_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[31]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(0),
      R => '0'
    );
\stage_1_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[3]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(28),
      R => '0'
    );
\stage_1_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[4]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(27),
      R => '0'
    );
\stage_1_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[5]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(26),
      R => '0'
    );
\stage_1_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[6]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(25),
      R => '0'
    );
\stage_1_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[7]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(24),
      R => '0'
    );
\stage_1_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[8]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(23),
      R => '0'
    );
\stage_1_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[9]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(22),
      R => '0'
    );
stage_1_ufc_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_START,
      Q => stage_1_ufc_start_r,
      R => RESET
    );
ufc_barrel_shifter_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL
     port map (
      BARREL_SHIFTER_CONTROL_Buffer => BARREL_SHIFTER_CONTROL_Buffer,
      barrel_shifter_control_i => barrel_shifter_control_i,
      user_clk => user_clk
    );
ufc_barrel_shifter_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER
     port map (
      BARREL_SHIFTER_CONTROL_Buffer => BARREL_SHIFTER_CONTROL_Buffer,
      \MUXED_DATA_Buffer_reg[16]\ => ufc_storage_mux_i_n_16,
      \MUXED_DATA_Buffer_reg[17]\ => ufc_storage_mux_i_n_17,
      \MUXED_DATA_Buffer_reg[18]\ => ufc_storage_mux_i_n_18,
      \MUXED_DATA_Buffer_reg[19]\ => ufc_storage_mux_i_n_19,
      \MUXED_DATA_Buffer_reg[20]\ => ufc_storage_mux_i_n_20,
      \MUXED_DATA_Buffer_reg[21]\ => ufc_storage_mux_i_n_21,
      \MUXED_DATA_Buffer_reg[22]\ => ufc_storage_mux_i_n_22,
      \MUXED_DATA_Buffer_reg[23]\ => ufc_storage_mux_i_n_23,
      \MUXED_DATA_Buffer_reg[24]\ => ufc_storage_mux_i_n_24,
      \MUXED_DATA_Buffer_reg[25]\ => ufc_storage_mux_i_n_25,
      \MUXED_DATA_Buffer_reg[26]\ => ufc_storage_mux_i_n_26,
      \MUXED_DATA_Buffer_reg[27]\ => ufc_storage_mux_i_n_27,
      \MUXED_DATA_Buffer_reg[28]\ => ufc_storage_mux_i_n_28,
      \MUXED_DATA_Buffer_reg[29]\ => ufc_storage_mux_i_n_29,
      \MUXED_DATA_Buffer_reg[30]\ => ufc_storage_mux_i_n_30,
      \MUXED_DATA_Buffer_reg[31]\ => ufc_storage_mux_i_n_31,
      SHIFTED_DATA_Buffer(0 to 31) => SHIFTED_DATA_Buffer(0 to 31),
      \SHIFTED_DATA_Buffer_reg[0]_0\ => ufc_barrel_shifter_i_n_47,
      \SHIFTED_DATA_Buffer_reg[0]_1\(31 downto 0) => \^stage_1_data_r_reg[0]_0\(31 downto 0),
      \SHIFTED_DATA_Buffer_reg[10]_0\ => ufc_barrel_shifter_i_n_37,
      \SHIFTED_DATA_Buffer_reg[11]_0\ => ufc_barrel_shifter_i_n_36,
      \SHIFTED_DATA_Buffer_reg[12]_0\ => ufc_barrel_shifter_i_n_35,
      \SHIFTED_DATA_Buffer_reg[13]_0\ => ufc_barrel_shifter_i_n_34,
      \SHIFTED_DATA_Buffer_reg[14]_0\ => ufc_barrel_shifter_i_n_33,
      \SHIFTED_DATA_Buffer_reg[15]_0\ => ufc_barrel_shifter_i_n_32,
      \SHIFTED_DATA_Buffer_reg[1]_0\ => ufc_barrel_shifter_i_n_46,
      \SHIFTED_DATA_Buffer_reg[2]_0\ => ufc_barrel_shifter_i_n_45,
      \SHIFTED_DATA_Buffer_reg[3]_0\ => ufc_barrel_shifter_i_n_44,
      \SHIFTED_DATA_Buffer_reg[4]_0\ => ufc_barrel_shifter_i_n_43,
      \SHIFTED_DATA_Buffer_reg[5]_0\ => ufc_barrel_shifter_i_n_42,
      \SHIFTED_DATA_Buffer_reg[6]_0\ => ufc_barrel_shifter_i_n_41,
      \SHIFTED_DATA_Buffer_reg[7]_0\ => ufc_barrel_shifter_i_n_40,
      \SHIFTED_DATA_Buffer_reg[8]_0\ => ufc_barrel_shifter_i_n_39,
      \SHIFTED_DATA_Buffer_reg[9]_0\ => ufc_barrel_shifter_i_n_38,
      UFC_OUTPUT_SELECT_Buffer(0) => UFC_OUTPUT_SELECT_Buffer(0),
      user_clk => user_clk
    );
ufc_output_mux_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_MUX
     port map (
      D(15) => ufc_storage_mux_i_n_0,
      D(14) => ufc_storage_mux_i_n_1,
      D(13) => ufc_storage_mux_i_n_2,
      D(12) => ufc_storage_mux_i_n_3,
      D(11) => ufc_storage_mux_i_n_4,
      D(10) => ufc_storage_mux_i_n_5,
      D(9) => ufc_storage_mux_i_n_6,
      D(8) => ufc_storage_mux_i_n_7,
      D(7) => ufc_storage_mux_i_n_8,
      D(6) => ufc_storage_mux_i_n_9,
      D(5) => ufc_storage_mux_i_n_10,
      D(4) => ufc_storage_mux_i_n_11,
      D(3) => ufc_storage_mux_i_n_12,
      D(2) => ufc_storage_mux_i_n_13,
      D(1) => ufc_storage_mux_i_n_14,
      D(0) => ufc_storage_mux_i_n_15,
      \MUXED_DATA_Buffer_reg[16]_0\ => ufc_barrel_shifter_i_n_47,
      \MUXED_DATA_Buffer_reg[17]_0\ => ufc_barrel_shifter_i_n_46,
      \MUXED_DATA_Buffer_reg[18]_0\ => ufc_barrel_shifter_i_n_45,
      \MUXED_DATA_Buffer_reg[19]_0\ => ufc_barrel_shifter_i_n_44,
      \MUXED_DATA_Buffer_reg[20]_0\ => ufc_barrel_shifter_i_n_43,
      \MUXED_DATA_Buffer_reg[21]_0\ => ufc_barrel_shifter_i_n_42,
      \MUXED_DATA_Buffer_reg[22]_0\ => ufc_barrel_shifter_i_n_41,
      \MUXED_DATA_Buffer_reg[23]_0\ => ufc_barrel_shifter_i_n_40,
      \MUXED_DATA_Buffer_reg[24]_0\ => ufc_barrel_shifter_i_n_39,
      \MUXED_DATA_Buffer_reg[25]_0\ => ufc_barrel_shifter_i_n_38,
      \MUXED_DATA_Buffer_reg[26]_0\ => ufc_barrel_shifter_i_n_37,
      \MUXED_DATA_Buffer_reg[27]_0\ => ufc_barrel_shifter_i_n_36,
      \MUXED_DATA_Buffer_reg[28]_0\ => ufc_barrel_shifter_i_n_35,
      \MUXED_DATA_Buffer_reg[29]_0\ => ufc_barrel_shifter_i_n_34,
      \MUXED_DATA_Buffer_reg[30]_0\ => ufc_barrel_shifter_i_n_33,
      \MUXED_DATA_Buffer_reg[31]_0\ => ufc_barrel_shifter_i_n_32,
      M_AXI_UFC_RX_TDATA(31 downto 0) => M_AXI_UFC_RX_TDATA(31 downto 0),
      UFC_OUTPUT_SELECT_Buffer(0) => UFC_OUTPUT_SELECT_Buffer(1),
      user_clk => user_clk
    );
ufc_output_switch_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL
     port map (
      Q(1) => ufc_storage_count_control_i_n_1,
      Q(0) => storage_count_2x_c(1),
      UFC_OUTPUT_SELECT_Buffer(1 downto 0) => UFC_OUTPUT_SELECT_Buffer(1 downto 0),
      \UFC_OUTPUT_SELECT_Buffer_reg[4]_0\ => ufc_storage_count_control_i_n_6,
      user_clk => user_clk
    );
ufc_sideband_output_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT
     port map (
      RESET => RESET,
      UFC_EOF_N_Buffer => UFC_EOF_N_Buffer,
      UFC_EOF_N_Buffer_reg_0 => ufc_storage_count_control_i_n_0,
      \UFC_REM_Buffer_reg[0]_0\ => ufc_sideband_output_i_n_0,
      \UFC_REM_Buffer_reg[0]_1\ => ufc_storage_count_control_i_n_7,
      UFC_SRC_RDY_N_Buffer => UFC_SRC_RDY_N_Buffer,
      UFC_SRC_RDY_N_Buffer_reg_0 => ufc_storage_count_control_i_n_6,
      user_clk => user_clk
    );
ufc_storage_count_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL
     port map (
      D(0) => ufc_storage_count_control_i_n_5,
      Q(1) => ufc_storage_count_control_i_n_1,
      Q(0) => storage_count_2x_c(1),
      RESET => RESET,
      UFC_EOF_N_Buffer_reg(1) => barrel_shifted_count_r(0),
      UFC_EOF_N_Buffer_reg(0) => barrel_shifted_count_r(1),
      stage_1_ufc_start_r => stage_1_ufc_start_r,
      stage_1_ufc_start_r_reg => ufc_storage_count_control_i_n_0,
      stage_1_ufc_start_r_reg_0 => ufc_storage_count_control_i_n_7,
      \storage_count_r_reg[0]_0\ => ufc_storage_count_control_i_n_6,
      \storage_count_r_reg[1]_0\ => ufc_storage_count_control_i_n_3,
      \storage_count_r_reg[1]_1\ => ufc_storage_count_control_i_n_4,
      user_clk => user_clk
    );
ufc_storage_mux_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_MUX
     port map (
      D(15) => ufc_storage_mux_i_n_0,
      D(14) => ufc_storage_mux_i_n_1,
      D(13) => ufc_storage_mux_i_n_2,
      D(12) => ufc_storage_mux_i_n_3,
      D(11) => ufc_storage_mux_i_n_4,
      D(10) => ufc_storage_mux_i_n_5,
      D(9) => ufc_storage_mux_i_n_6,
      D(8) => ufc_storage_mux_i_n_7,
      D(7) => ufc_storage_mux_i_n_8,
      D(6) => ufc_storage_mux_i_n_9,
      D(5) => ufc_storage_mux_i_n_10,
      D(4) => ufc_storage_mux_i_n_11,
      D(3) => ufc_storage_mux_i_n_12,
      D(2) => ufc_storage_mux_i_n_13,
      D(1) => ufc_storage_mux_i_n_14,
      D(0) => ufc_storage_mux_i_n_15,
      \MUXED_DATA_Buffer_reg[0]_0\ => ufc_storage_switch_control_i_n_0,
      \MUXED_DATA_Buffer_reg[16]_0\ => ufc_storage_mux_i_n_16,
      \MUXED_DATA_Buffer_reg[17]_0\ => ufc_storage_mux_i_n_17,
      \MUXED_DATA_Buffer_reg[18]_0\ => ufc_storage_mux_i_n_18,
      \MUXED_DATA_Buffer_reg[19]_0\ => ufc_storage_mux_i_n_19,
      \MUXED_DATA_Buffer_reg[20]_0\ => ufc_storage_mux_i_n_20,
      \MUXED_DATA_Buffer_reg[21]_0\ => ufc_storage_mux_i_n_21,
      \MUXED_DATA_Buffer_reg[22]_0\ => ufc_storage_mux_i_n_22,
      \MUXED_DATA_Buffer_reg[23]_0\ => ufc_storage_mux_i_n_23,
      \MUXED_DATA_Buffer_reg[24]_0\ => ufc_storage_mux_i_n_24,
      \MUXED_DATA_Buffer_reg[25]_0\ => ufc_storage_mux_i_n_25,
      \MUXED_DATA_Buffer_reg[26]_0\ => ufc_storage_mux_i_n_26,
      \MUXED_DATA_Buffer_reg[27]_0\ => ufc_storage_mux_i_n_27,
      \MUXED_DATA_Buffer_reg[28]_0\ => ufc_storage_mux_i_n_28,
      \MUXED_DATA_Buffer_reg[29]_0\ => ufc_storage_mux_i_n_29,
      \MUXED_DATA_Buffer_reg[30]_0\ => ufc_storage_mux_i_n_30,
      \MUXED_DATA_Buffer_reg[31]_0\ => ufc_storage_mux_i_n_31,
      SHIFTED_DATA_Buffer(0 to 31) => SHIFTED_DATA_Buffer(0 to 31),
      UFC_STORAGE_SELECT_Buffer(2) => UFC_STORAGE_SELECT_Buffer(2),
      UFC_STORAGE_SELECT_Buffer(1) => UFC_STORAGE_SELECT_Buffer(4),
      UFC_STORAGE_SELECT_Buffer(0) => UFC_STORAGE_SELECT_Buffer(5),
      user_clk => user_clk
    );
ufc_storage_switch_control_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL
     port map (
      D(0) => ufc_storage_count_control_i_n_5,
      Q(1) => ufc_storage_count_control_i_n_1,
      Q(0) => storage_count_2x_c(1),
      \UFC_STORAGE_SELECT_Buffer_reg[0]_0\ => ufc_storage_switch_control_i_n_0,
      \UFC_STORAGE_SELECT_Buffer_reg[0]_1\ => ufc_storage_count_control_i_n_3,
      \UFC_STORAGE_SELECT_Buffer_reg[1]_0\ => ufc_storage_count_control_i_n_4,
      \UFC_STORAGE_SELECT_Buffer_reg[2]_0\(2) => UFC_STORAGE_SELECT_Buffer(2),
      \UFC_STORAGE_SELECT_Buffer_reg[2]_0\(1) => UFC_STORAGE_SELECT_Buffer(4),
      \UFC_STORAGE_SELECT_Buffer_reg[2]_0\(0) => UFC_STORAGE_SELECT_Buffer(5),
      \UFC_STORAGE_SELECT_Buffer_reg[4]_0\ => \ufc_storage_switch_control_i/_n_0\,
      \UFC_STORAGE_SELECT_Buffer_reg[4]_1\(1) => barrel_shifted_count_r(0),
      \UFC_STORAGE_SELECT_Buffer_reg[4]_1\(0) => barrel_shifted_count_r(1),
      stage_1_ufc_start_r => stage_1_ufc_start_r,
      user_clk => user_clk
    );
\ufc_storage_switch_control_i/\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ufc_storage_count_control_i_n_1,
      O => \ufc_storage_switch_control_i/_n_0\
    );
ufc_valid_data_counter: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER
     port map (
      \COUNT_Buffer_reg[0]_0\(1) => barrel_shifted_count_r(0),
      \COUNT_Buffer_reg[0]_0\(0) => barrel_shifted_count_r(1),
      Q(1 downto 0) => Q(1 downto 0),
      RESET => RESET,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_multi_gt is
  port (
    TX_LOCK : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rx_realign_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RXDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RXCHARISK : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ack_flag : out STD_LOGIC;
    hard_err_gt0 : out STD_LOGIC;
    inc_count_r0 : out STD_LOGIC;
    inc_count_r_reg : out STD_LOGIC;
    init_clk_in_0 : out STD_LOGIC;
    \previous_cycle_data_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \left_align_select_r_reg[1]\ : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC;
    RXP : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    fsm_gt_rx_reset_t : in STD_LOGIC;
    gt_qpllclk_quad1_in : in STD_LOGIC;
    gt_qpllrefclk_quad1_in : in STD_LOGIC;
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i : in STD_LOGIC;
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    begin_r : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \word_aligned_data_r_reg[22]\ : in STD_LOGIC;
    \word_aligned_data_r_reg[22]_0\ : in STD_LOGIC;
    enable_err_detect_i : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_multi_gt : entity is "aurora_1ln_rx_lpm_multi_gt";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_multi_gt;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_multi_gt is
begin
gt0_aurora_1ln_rx_lpm_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_gt
     port map (
      D(7 downto 0) => D(7 downto 0),
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPWE_IN => DRPWE_IN,
      E(0) => E(0),
      ENABLE_ERR_DETECT_Buffer_reg(3 downto 0) => ENABLE_ERR_DETECT_Buffer_reg(3 downto 0),
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      Q(3 downto 0) => Q(3 downto 0),
      RXCHARISK(3 downto 0) => RXCHARISK(3 downto 0),
      RXDATA(31 downto 0) => RXDATA(31 downto 0),
      RXN => RXN,
      RXP => RXP,
      SR(0) => SR(0),
      TX_LOCK => TX_LOCK,
      TX_OUT_CLK => TX_OUT_CLK,
      ack_flag => ack_flag,
      begin_r => begin_r,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      ena_comma_align_i => ena_comma_align_i,
      enable_err_detect_i => enable_err_detect_i,
      flag2_reg_0 => flag2_reg,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_rx_disp_err_out(3 downto 0) => gt0_rx_disp_err_out(3 downto 0),
      gt0_rx_not_in_table_out(3 downto 0) => gt0_rx_not_in_table_out(3 downto 0),
      gt0_rx_realign_out => gt0_rx_realign_out,
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2 downto 0) => gt0_rxbufstatus_out(2 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt_qpllclk_quad1_in => gt_qpllclk_quad1_in,
      gt_qpllrefclk_quad1_in => gt_qpllrefclk_quad1_in,
      gt_refclk1 => gt_refclk1,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      hard_err_gt0 => hard_err_gt0,
      inc_count_r0 => inc_count_r0,
      inc_count_r_reg => inc_count_r_reg,
      init_clk_in => init_clk_in,
      init_clk_in_0 => init_clk_in_0,
      \left_align_select_r_reg[1]\ => \left_align_select_r_reg[1]\,
      \previous_cycle_data_r_reg[7]\(3 downto 0) => \previous_cycle_data_r_reg[7]\(3 downto 0),
      rx_polarity_i => rx_polarity_i,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_data_r_reg[22]\ => \word_aligned_data_r_reg[22]\,
      \word_aligned_data_r_reg[22]_0\ => \word_aligned_data_r_reg[22]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_rx_startup_fsm is
  port (
    fsm_gt_rx_reset_t : out STD_LOGIC;
    gt_rxuserrdy_i : out STD_LOGIC;
    cpll_reset_i : out STD_LOGIC;
    CPLL_RESET_reg_0 : out STD_LOGIC;
    TX_LOCK : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    rxfsm_rxresetdone_r : in STD_LOGIC;
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    reset_time_out_reg_0 : in STD_LOGIC;
    ack_flag : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_rx_startup_fsm : entity is "aurora_1ln_rx_lpm_rx_startup_fsm";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_rx_startup_fsm;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_rx_startup_fsm is
  signal CPLL_RESET_i_1_n_0 : STD_LOGIC;
  signal \FSM_sequential_rx_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_14_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_15_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_16_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_9_n_0\ : STD_LOGIC;
  signal RXUSERRDY_i_1_n_0 : STD_LOGIC;
  signal check_tlock_max_i_1_n_0 : STD_LOGIC;
  signal check_tlock_max_reg_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \^cpll_reset_i\ : STD_LOGIC;
  signal \^fsm_gt_rx_reset_t\ : STD_LOGIC;
  signal \^gt_rxuserrdy_i\ : STD_LOGIC;
  signal gtrxreset_i_i_1_n_0 : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[6]_i_3_n_0\ : STD_LOGIC;
  signal \init_wait_count[6]_i_4_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal init_wait_done_i_1_n_0 : STD_LOGIC;
  signal init_wait_done_i_2_n_0 : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[9]_i_2_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[9]_i_4_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal mmcm_lock_reclocked_i_2_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal pll_reset_asserted_i_1_n_0 : STD_LOGIC;
  signal pll_reset_asserted_reg_n_0 : STD_LOGIC;
  signal reset_time_out_reg_n_0 : STD_LOGIC;
  signal run_phase_alignment_int : STD_LOGIC;
  signal run_phase_alignment_int_i_1_n_0 : STD_LOGIC;
  signal run_phase_alignment_int_s2 : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal rx_fsm_reset_done_int : STD_LOGIC;
  signal rx_fsm_reset_done_int_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_1_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_3_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_4_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_5_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal rx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxpmaresetdone_i : STD_LOGIC;
  signal rxpmaresetdone_rx_s : STD_LOGIC;
  signal rxresetdone_s2 : STD_LOGIC;
  signal rxresetdone_s3 : STD_LOGIC;
  signal scndry_out : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_CPLLLOCK_cdc_sync_n_0 : STD_LOGIC;
  signal sync_CPLLLOCK_cdc_sync_n_1 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_cdc_sync_n_0 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_cdc_sync_n_1 : STD_LOGIC;
  signal sync_rx_fsm_reset_done_int_cdc_sync_n_0 : STD_LOGIC;
  signal time_out_100us_i_1_n_0 : STD_LOGIC;
  signal time_out_100us_i_2_n_0 : STD_LOGIC;
  signal time_out_100us_i_3_n_0 : STD_LOGIC;
  signal time_out_100us_i_4_n_0 : STD_LOGIC;
  signal time_out_100us_reg_n_0 : STD_LOGIC;
  signal time_out_1us_i_1_n_0 : STD_LOGIC;
  signal time_out_1us_i_2_n_0 : STD_LOGIC;
  signal time_out_1us_i_3_n_0 : STD_LOGIC;
  signal time_out_1us_i_4_n_0 : STD_LOGIC;
  signal time_out_1us_reg_n_0 : STD_LOGIC;
  signal time_out_2ms_i_1_n_0 : STD_LOGIC;
  signal time_out_2ms_i_2_n_0 : STD_LOGIC;
  signal time_out_2ms_i_3_n_0 : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_6_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_7_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_8_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \time_out_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal time_out_wait_bypass : STD_LOGIC;
  signal time_out_wait_bypass_i_1_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal time_tlock_max : STD_LOGIC;
  signal time_tlock_max1 : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_1\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_2\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_3\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_n_3\ : STD_LOGIC;
  signal time_tlock_max1_carry_i_1_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_2_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_3_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_4_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_5_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_1 : STD_LOGIC;
  signal time_tlock_max1_carry_n_2 : STD_LOGIC;
  signal time_tlock_max1_carry_n_3 : STD_LOGIC;
  signal time_tlock_max_i_1_n_0 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_5_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_6_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_7_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \wait_time_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_time_tlock_max1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[2]_i_2\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_10\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_11\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_12\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_15\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_5\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_9\ : label is "soft_lutpair118";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[0]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[1]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[2]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[3]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute SOFT_HLUTNM of check_tlock_max_i_1 : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of gtrxreset_i_i_1 : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \init_wait_count[0]_i_1\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \init_wait_count[6]_i_3\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \init_wait_count[6]_i_4\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of init_wait_done_i_2 : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \mmcm_lock_count[8]_i_1\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \mmcm_lock_count[9]_i_3\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of mmcm_lock_reclocked_i_2 : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of run_phase_alignment_int_i_1 : label is "soft_lutpair115";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of run_phase_alignment_int_s3_reg : label is "no";
  attribute SOFT_HLUTNM of rx_fsm_reset_done_int_i_5 : label is "soft_lutpair122";
  attribute equivalent_register_removal of rx_fsm_reset_done_int_s3_reg : label is "no";
  attribute equivalent_register_removal of rxresetdone_s3_reg : label is "no";
  attribute SOFT_HLUTNM of time_out_100us_i_1 : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of time_out_1us_i_3 : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of time_out_2ms_i_3 : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \time_out_counter[0]_i_5\ : label is "soft_lutpair117";
  attribute equivalent_register_removal of time_out_wait_bypass_s3_reg : label is "no";
  attribute SOFT_HLUTNM of time_tlock_max_i_1 : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1\ : label is "soft_lutpair123";
begin
  cpll_reset_i <= \^cpll_reset_i\;
  fsm_gt_rx_reset_t <= \^fsm_gt_rx_reset_t\;
  gt_rxuserrdy_i <= \^gt_rxuserrdy_i\;
CPLL_RESET_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFF00000100"
    )
        port map (
      I0 => pll_reset_asserted_reg_n_0,
      I1 => rx_state(3),
      I2 => rx_state(2),
      I3 => rx_state(0),
      I4 => rx_state(1),
      I5 => \^cpll_reset_i\,
      O => CPLL_RESET_i_1_n_0
    );
CPLL_RESET_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => CPLL_RESET_i_1_n_0,
      Q => \^cpll_reset_i\,
      R => AR(0)
    );
\FSM_sequential_rx_state[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFEFEF"
    )
        port map (
      I0 => \FSM_sequential_rx_state[0]_i_2_n_0\,
      I1 => \FSM_sequential_rx_state[3]_i_5_n_0\,
      I2 => rx_state(0),
      I3 => rx_state(1),
      I4 => rx_state(3),
      O => \rx_state__0\(0)
    );
\FSM_sequential_rx_state[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222AAAA00300000"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => reset_time_out_reg_n_0,
      I2 => time_tlock_max,
      I3 => rx_state(3),
      I4 => rx_state(2),
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[0]_i_2_n_0\
    );
\FSM_sequential_rx_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00F00010"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(2),
      I2 => rx_state(0),
      I3 => rx_state(1),
      I4 => reset_time_out_reg_n_0,
      I5 => \FSM_sequential_rx_state[1]_i_2_n_0\,
      O => \rx_state__0\(1)
    );
\FSM_sequential_rx_state[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"303000301C1C1C1C"
    )
        port map (
      I0 => time_tlock_max,
      I1 => rx_state(1),
      I2 => rx_state(0),
      I3 => time_out_100us_reg_n_0,
      I4 => \^gt_rxuserrdy_i\,
      I5 => rx_state(3),
      O => \FSM_sequential_rx_state[1]_i_2_n_0\
    );
\FSM_sequential_rx_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010C0C0C01000C0C"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(1),
      I4 => rx_state(0),
      I5 => \FSM_sequential_rx_state[2]_i_2_n_0\,
      O => \rx_state__0\(2)
    );
\FSM_sequential_rx_state[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_tlock_max,
      O => \FSM_sequential_rx_state[2]_i_2_n_0\
    );
\FSM_sequential_rx_state[3]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => time_out_100us_reg_n_0,
      I1 => \^gt_rxuserrdy_i\,
      I2 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_10_n_0\
    );
\FSM_sequential_rx_state[3]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_11_n_0\
    );
\FSM_sequential_rx_state[3]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(2),
      I2 => rx_state(0),
      I3 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_12_n_0\
    );
\FSM_sequential_rx_state[3]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000008F888888"
    )
        port map (
      I0 => rx_state(3),
      I1 => \^gt_rxuserrdy_i\,
      I2 => rx_state(0),
      I3 => rx_state(2),
      I4 => reset_time_out_reg_0,
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_14_n_0\
    );
\FSM_sequential_rx_state[3]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(0),
      O => \FSM_sequential_rx_state[3]_i_15_n_0\
    );
\FSM_sequential_rx_state[3]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(0),
      I2 => rx_state(2),
      I3 => init_wait_done_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_16_n_0\
    );
\FSM_sequential_rx_state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAAEAEFAAAA"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_9_n_0\,
      I1 => \FSM_sequential_rx_state[3]_i_10_n_0\,
      I2 => rx_state(0),
      I3 => time_out_wait_bypass_s3,
      I4 => rx_state(3),
      I5 => rx_state(1),
      O => \rx_state__0\(3)
    );
\FSM_sequential_rx_state[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000400C000040000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[2]_i_2_n_0\,
      I1 => rx_state(0),
      I2 => rx_state(1),
      I3 => rx_state(3),
      I4 => rx_state(2),
      I5 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_4_n_0\
    );
\FSM_sequential_rx_state[3]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rx_state(3),
      I1 => reset_time_out_reg_n_0,
      I2 => \^gt_rxuserrdy_i\,
      I3 => time_out_100us_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_5_n_0\
    );
\FSM_sequential_rx_state[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAEAFFAAAAEA"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_14_n_0\,
      I1 => mmcm_lock_reclocked,
      I2 => rx_state(2),
      I3 => rx_state(3),
      I4 => \FSM_sequential_rx_state[3]_i_15_n_0\,
      I5 => \^gt_rxuserrdy_i\,
      O => \FSM_sequential_rx_state[3]_i_6_n_0\
    );
\FSM_sequential_rx_state[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAABAAAA"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_16_n_0\,
      I1 => \wait_time_cnt[6]_i_4_n_0\,
      I2 => wait_time_cnt_reg(6),
      I3 => rx_state(3),
      I4 => rx_state(1),
      I5 => rx_state(0),
      O => \FSM_sequential_rx_state[3]_i_8_n_0\
    );
\FSM_sequential_rx_state[3]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80800080"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(2),
      I3 => time_out_2ms_reg_n_0,
      I4 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_9_n_0\
    );
\FSM_sequential_rx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(0),
      Q => rx_state(0),
      R => AR(0)
    );
\FSM_sequential_rx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(1),
      Q => rx_state(1),
      R => AR(0)
    );
\FSM_sequential_rx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(2),
      Q => rx_state(2),
      R => AR(0)
    );
\FSM_sequential_rx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(3),
      Q => rx_state(3),
      R => AR(0)
    );
RXUSERRDY_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0080"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(0),
      I2 => rx_state(2),
      I3 => rx_state(3),
      I4 => \^gt_rxuserrdy_i\,
      O => RXUSERRDY_i_1_n_0
    );
RXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => RXUSERRDY_i_1_n_0,
      Q => \^gt_rxuserrdy_i\,
      R => AR(0)
    );
check_tlock_max_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0008"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(0),
      I2 => rx_state(1),
      I3 => rx_state(3),
      I4 => check_tlock_max_reg_n_0,
      O => check_tlock_max_i_1_n_0
    );
check_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => check_tlock_max_i_1_n_0,
      Q => check_tlock_max_reg_n_0,
      R => AR(0)
    );
flag2_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^cpll_reset_i\,
      I1 => ack_flag,
      O => CPLL_RESET_reg_0
    );
gtrxreset_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_2\
     port map (
      fsm_gt_rx_reset_t => \^fsm_gt_rx_reset_t\,
      init_clk_in => init_clk_in,
      \out\ => scndry_out,
      user_clk => user_clk
    );
gtrxreset_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEF0004"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(0),
      I2 => rx_state(2),
      I3 => rx_state(3),
      I4 => \^fsm_gt_rx_reset_t\,
      O => gtrxreset_i_i_1_n_0
    );
gtrxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_i_i_1_n_0,
      Q => \^fsm_gt_rx_reset_t\,
      R => AR(0)
    );
\init_wait_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => p_0_in(0)
    );
\init_wait_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(2),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(1),
      I4 => init_wait_count_reg(3),
      I5 => init_wait_count_reg(5),
      O => p_0_in(5)
    );
\init_wait_count[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => \init_wait_count[6]_i_3_n_0\,
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(1),
      I5 => init_wait_count_reg(0),
      O => init_wait_count
    );
\init_wait_count[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C6"
    )
        port map (
      I0 => init_wait_count_reg(5),
      I1 => init_wait_count_reg(6),
      I2 => \init_wait_count[6]_i_4_n_0\,
      O => p_0_in(6)
    );
\init_wait_count[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => init_wait_count_reg(5),
      I1 => init_wait_count_reg(6),
      O => \init_wait_count[6]_i_3_n_0\
    );
\init_wait_count[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => \init_wait_count[6]_i_4_n_0\
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(0),
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_count_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(6),
      Q => init_wait_count_reg(6)
    );
init_wait_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0100"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_done_i_2_n_0,
      I4 => init_wait_done_reg_n_0,
      O => init_wait_done_i_1_n_0
    );
init_wait_done_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(3),
      I2 => init_wait_count_reg(6),
      I3 => init_wait_count_reg(5),
      O => init_wait_done_i_2_n_0
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => AR(0),
      D => init_wait_done_i_1_n_0,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__1\(0)
    );
\mmcm_lock_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__1\(1)
    );
\mmcm_lock_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \p_0_in__1\(2)
    );
\mmcm_lock_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \p_0_in__1\(3)
    );
\mmcm_lock_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \p_0_in__1\(4)
    );
\mmcm_lock_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \p_0_in__1\(5)
    );
\mmcm_lock_count[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[9]_i_4_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \p_0_in__1\(6)
    );
\mmcm_lock_count[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \p_0_in__1\(7)
    );
\mmcm_lock_count[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => mmcm_lock_count_reg(7),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(6),
      I3 => mmcm_lock_count_reg(8),
      O => \p_0_in__1\(8)
    );
\mmcm_lock_count[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(7),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(6),
      I3 => mmcm_lock_count_reg(8),
      I4 => mmcm_lock_count_reg(9),
      O => \mmcm_lock_count[9]_i_2_n_0\
    );
\mmcm_lock_count[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FF0800"
    )
        port map (
      I0 => mmcm_lock_count_reg(8),
      I1 => mmcm_lock_count_reg(6),
      I2 => \mmcm_lock_count[9]_i_4_n_0\,
      I3 => mmcm_lock_count_reg(7),
      I4 => mmcm_lock_count_reg(9),
      O => \p_0_in__1\(9)
    );
\mmcm_lock_count[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[9]_i_4_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(2),
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(3),
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(4),
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(5),
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(6),
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(7),
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(8),
      Q => mmcm_lock_count_reg(8),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
\mmcm_lock_count_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__1\(9),
      Q => mmcm_lock_count_reg(9),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_0
    );
mmcm_lock_reclocked_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => mmcm_lock_count_reg(9),
      I1 => mmcm_lock_count_reg(8),
      I2 => mmcm_lock_count_reg(6),
      I3 => \mmcm_lock_count[9]_i_4_n_0\,
      I4 => mmcm_lock_count_reg(7),
      O => mmcm_lock_reclocked_i_2_n_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => sync_mmcm_lock_reclocked_cdc_sync_n_1,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
pll_reset_asserted_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDFF0100"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(0),
      I4 => pll_reset_asserted_reg_n_0,
      O => pll_reset_asserted_i_1_n_0
    );
pll_reset_asserted_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => pll_reset_asserted_i_1_n_0,
      Q => pll_reset_asserted_reg_n_0,
      R => AR(0)
    );
reset_time_out_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => sync_CPLLLOCK_cdc_sync_n_1,
      Q => reset_time_out_reg_n_0,
      S => AR(0)
    );
run_phase_alignment_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0100"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(0),
      I2 => rx_state(2),
      I3 => rx_state(3),
      I4 => run_phase_alignment_int,
      O => run_phase_alignment_int_i_1_n_0
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => run_phase_alignment_int_i_1_n_0,
      Q => run_phase_alignment_int,
      R => AR(0)
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => run_phase_alignment_int_s2,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
rx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABA8"
    )
        port map (
      I0 => rx_fsm_reset_done_int_0,
      I1 => rx_fsm_reset_done_int_i_3_n_0,
      I2 => rx_fsm_reset_done_int_i_4_n_0,
      I3 => rx_fsm_reset_done_int,
      O => rx_fsm_reset_done_int_i_1_n_0
    );
rx_fsm_reset_done_int_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => rx_state(0),
      I1 => time_out_1us_reg_n_0,
      I2 => rx_state(2),
      I3 => reset_time_out_reg_n_0,
      I4 => \^gt_rxuserrdy_i\,
      O => rx_fsm_reset_done_int_0
    );
rx_fsm_reset_done_int_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400040004040400"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_15_n_0\,
      I1 => rx_state(3),
      I2 => rx_state(2),
      I3 => \^gt_rxuserrdy_i\,
      I4 => time_out_100us_reg_n_0,
      I5 => reset_time_out_reg_n_0,
      O => rx_fsm_reset_done_int_i_3_n_0
    );
rx_fsm_reset_done_int_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000808080008"
    )
        port map (
      I0 => rx_fsm_reset_done_int_i_5_n_0,
      I1 => rx_state(1),
      I2 => rx_state(0),
      I3 => \^gt_rxuserrdy_i\,
      I4 => time_out_1us_reg_n_0,
      I5 => reset_time_out_reg_n_0,
      O => rx_fsm_reset_done_int_i_4_n_0
    );
rx_fsm_reset_done_int_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(2),
      O => rx_fsm_reset_done_int_i_5_n_0
    );
rx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_fsm_reset_done_int_i_1_n_0,
      Q => rx_fsm_reset_done_int,
      R => AR(0)
    );
rx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => sync_rx_fsm_reset_done_int_cdc_sync_n_0,
      Q => rx_fsm_reset_done_int_s3,
      R => '0'
    );
rxpmaresetdone_i_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      CLR => scndry_out,
      D => rxpmaresetdone_rx_s,
      Q => rxpmaresetdone_i
    );
rxresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rxresetdone_s2,
      Q => rxresetdone_s3,
      R => '0'
    );
sync_CPLLLOCK_cdc_sync: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_3
     port map (
      E(0) => sync_CPLLLOCK_cdc_sync_n_0,
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[3]_i_4_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => \FSM_sequential_rx_state[3]_i_5_n_0\,
      \FSM_sequential_rx_state_reg[0]_1\ => \FSM_sequential_rx_state[3]_i_8_n_0\,
      \FSM_sequential_rx_state_reg[0]_2\ => time_out_2ms_reg_n_0,
      \FSM_sequential_rx_state_reg[0]_3\ => \FSM_sequential_rx_state[3]_i_11_n_0\,
      \FSM_sequential_rx_state_reg[0]_4\ => \FSM_sequential_rx_state[3]_i_12_n_0\,
      \FSM_sequential_rx_state_reg[1]\ => sync_CPLLLOCK_cdc_sync_n_1,
      Q(3 downto 0) => rx_state(3 downto 0),
      TX_LOCK => TX_LOCK,
      init_clk_in => init_clk_in,
      reset_time_out_reg => reset_time_out_reg_0,
      reset_time_out_reg_0 => \FSM_sequential_rx_state[3]_i_6_n_0\,
      reset_time_out_reg_1 => reset_time_out_reg_n_0,
      reset_time_out_reg_2 => pll_reset_asserted_reg_n_0,
      rxresetdone_s3 => rxresetdone_s3
    );
sync_QPLLLOCK_cdc_sync: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_4
     port map (
      init_clk_in => init_clk_in
    );
sync_RXRESETDONE_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_5\
     port map (
      init_clk_in => init_clk_in,
      \out\ => rxresetdone_s2,
      rxfsm_rxresetdone_r => rxfsm_rxresetdone_r,
      user_clk => user_clk
    );
sync_mmcm_lock_reclocked_cdc_sync: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_6
     port map (
      SR(0) => sync_mmcm_lock_reclocked_cdc_sync_n_0,
      init_clk_in => init_clk_in,
      mmcm_lock_reclocked => mmcm_lock_reclocked,
      mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_cdc_sync_n_1,
      mmcm_lock_reclocked_reg_0 => mmcm_lock_reclocked_i_2_n_0
    );
sync_pmaresetdone_fallingedge_detect_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_7\
     port map (
      init_clk_in => init_clk_in,
      user_clk => user_clk
    );
sync_run_phase_alignment_int_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_8\
     port map (
      init_clk_in => init_clk_in,
      \out\ => run_phase_alignment_int_s2,
      run_phase_alignment_int => run_phase_alignment_int,
      user_clk => user_clk
    );
sync_rx_fsm_reset_done_int_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_9\
     port map (
      init_clk_in => init_clk_in,
      \out\ => sync_rx_fsm_reset_done_int_cdc_sync_n_0,
      rx_fsm_reset_done_int => rx_fsm_reset_done_int,
      user_clk => user_clk
    );
sync_rxpmaresetdone_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_10\
     port map (
      init_clk_in => init_clk_in,
      rxpmaresetdone_i => rxpmaresetdone_i,
      user_clk => user_clk
    );
sync_rxpmaresetdone_rx_s_cdc_sync: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_11
     port map (
      \out\ => rxpmaresetdone_rx_s,
      user_clk => user_clk
    );
sync_time_out_wait_bypass_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_12\
     port map (
      init_clk_in => init_clk_in,
      \out\ => time_out_wait_bypass_s2,
      time_out_wait_bypass => time_out_wait_bypass,
      user_clk => user_clk
    );
time_out_100us_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0002"
    )
        port map (
      I0 => time_out_100us_i_2_n_0,
      I1 => \time_out_counter[0]_i_3_n_0\,
      I2 => time_out_counter_reg(11),
      I3 => time_out_counter_reg(10),
      I4 => time_out_100us_reg_n_0,
      O => time_out_100us_i_1_n_0
    );
time_out_100us_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => time_out_100us_i_3_n_0,
      I1 => time_out_100us_i_4_n_0,
      I2 => \time_out_counter[0]_i_5_n_0\,
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(3),
      I5 => time_out_counter_reg(18),
      O => time_out_100us_i_2_n_0
    );
time_out_100us_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(16),
      I1 => time_out_counter_reg(17),
      O => time_out_100us_i_3_n_0
    );
time_out_100us_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => time_out_100us_i_4_n_0
    );
time_out_100us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_100us_i_1_n_0,
      Q => time_out_100us_reg_n_0,
      R => reset_time_out_reg_n_0
    );
time_out_1us_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF02000000"
    )
        port map (
      I0 => time_out_1us_i_2_n_0,
      I1 => time_out_1us_i_3_n_0,
      I2 => \time_out_counter[0]_i_5_n_0\,
      I3 => time_out_counter_reg(3),
      I4 => time_out_1us_i_4_n_0,
      I5 => time_out_1us_reg_n_0,
      O => time_out_1us_i_1_n_0
    );
time_out_1us_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => time_out_100us_i_4_n_0,
      I1 => time_out_100us_i_3_n_0,
      I2 => time_out_counter_reg(2),
      I3 => time_out_counter_reg(4),
      I4 => time_out_counter_reg(0),
      I5 => time_out_counter_reg(1),
      O => time_out_1us_i_2_n_0
    );
time_out_1us_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      O => time_out_1us_i_3_n_0
    );
time_out_1us_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => time_out_counter_reg(7),
      I1 => time_out_counter_reg(12),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(6),
      I4 => time_out_counter_reg(18),
      I5 => time_out_counter_reg(13),
      O => time_out_1us_i_4_n_0
    );
time_out_1us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_1us_i_1_n_0,
      Q => time_out_1us_reg_n_0,
      R => reset_time_out_reg_n_0
    );
time_out_2ms_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF08"
    )
        port map (
      I0 => time_out_2ms_i_2_n_0,
      I1 => time_out_2ms_i_3_n_0,
      I2 => \time_out_counter[0]_i_3_n_0\,
      I3 => time_out_2ms_reg_n_0,
      O => time_out_2ms_i_1_n_0
    );
time_out_2ms_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000008000000000"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(11),
      I3 => time_out_counter_reg(14),
      I4 => time_out_counter_reg(17),
      I5 => time_out_counter_reg(18),
      O => time_out_2ms_i_2_n_0
    );
time_out_2ms_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(2),
      I2 => time_out_counter_reg(3),
      I3 => time_out_counter_reg(8),
      I4 => time_out_counter_reg(9),
      O => time_out_2ms_i_3_n_0
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_2ms_i_1_n_0,
      Q => time_out_2ms_reg_n_0,
      R => reset_time_out_reg_n_0
    );
\time_out_counter[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \time_out_counter[0]_i_3_n_0\,
      I1 => \time_out_counter[0]_i_4_n_0\,
      I2 => time_out_counter_reg(10),
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(3),
      I5 => \time_out_counter[0]_i_5_n_0\,
      O => time_out_counter
    );
\time_out_counter[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF7FF"
    )
        port map (
      I0 => time_out_counter_reg(6),
      I1 => time_out_counter_reg(7),
      I2 => time_out_counter_reg(5),
      I3 => time_out_counter_reg(4),
      I4 => \time_out_counter[0]_i_7_n_0\,
      I5 => \time_out_counter[0]_i_8_n_0\,
      O => \time_out_counter[0]_i_3_n_0\
    );
\time_out_counter[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDFFFFFFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(18),
      I1 => time_out_counter_reg(17),
      I2 => time_out_counter_reg(15),
      I3 => time_out_counter_reg(16),
      I4 => time_out_counter_reg(14),
      I5 => time_out_counter_reg(11),
      O => \time_out_counter[0]_i_4_n_0\
    );
\time_out_counter[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      O => \time_out_counter[0]_i_5_n_0\
    );
\time_out_counter[0]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_6_n_0\
    );
\time_out_counter[0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(1),
      O => \time_out_counter[0]_i_7_n_0\
    );
\time_out_counter[0]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(13),
      O => \time_out_counter[0]_i_8_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_7\,
      Q => time_out_counter_reg(0),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_6_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_5\,
      Q => time_out_counter_reg(10),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_4\,
      Q => time_out_counter_reg(11),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_7\,
      Q => time_out_counter_reg(12),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_6\,
      Q => time_out_counter_reg(13),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_5\,
      Q => time_out_counter_reg(14),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_4\,
      Q => time_out_counter_reg(15),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1_n_7\,
      Q => time_out_counter_reg(16),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \time_out_counter_reg[16]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\(3),
      O(2) => \time_out_counter_reg[16]_i_1_n_5\,
      O(1) => \time_out_counter_reg[16]_i_1_n_6\,
      O(0) => \time_out_counter_reg[16]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => time_out_counter_reg(18 downto 16)
    );
\time_out_counter_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1_n_6\,
      Q => time_out_counter_reg(17),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1_n_5\,
      Q => time_out_counter_reg(18),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_6\,
      Q => time_out_counter_reg(1),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_5\,
      Q => time_out_counter_reg(2),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_4\,
      Q => time_out_counter_reg(3),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_7\,
      Q => time_out_counter_reg(4),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_6\,
      Q => time_out_counter_reg(5),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_5\,
      Q => time_out_counter_reg(6),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_4\,
      Q => time_out_counter_reg(7),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_7\,
      Q => time_out_counter_reg(8),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_6\,
      Q => time_out_counter_reg(9),
      R => reset_time_out_reg_n_0
    );
time_out_wait_bypass_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass,
      I1 => rx_fsm_reset_done_int_s3,
      I2 => \wait_bypass_count[0]_i_4_n_0\,
      I3 => run_phase_alignment_int_s3,
      O => time_out_wait_bypass_i_1_n_0
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => time_out_wait_bypass_i_1_n_0,
      Q => time_out_wait_bypass,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
time_tlock_max1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => time_tlock_max1_carry_n_0,
      CO(2) => time_tlock_max1_carry_n_1,
      CO(1) => time_tlock_max1_carry_n_2,
      CO(0) => time_tlock_max1_carry_n_3,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => time_out_counter_reg(5),
      DI(1) => time_out_counter_reg(3),
      DI(0) => time_tlock_max1_carry_i_1_n_0,
      O(3 downto 0) => NLW_time_tlock_max1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => time_tlock_max1_carry_i_2_n_0,
      S(2) => time_tlock_max1_carry_i_3_n_0,
      S(1) => time_tlock_max1_carry_i_4_n_0,
      S(0) => time_tlock_max1_carry_i_5_n_0
    );
\time_tlock_max1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => time_tlock_max1_carry_n_0,
      CO(3) => \time_tlock_max1_carry__0_n_0\,
      CO(2) => \time_tlock_max1_carry__0_n_1\,
      CO(1) => \time_tlock_max1_carry__0_n_2\,
      CO(0) => \time_tlock_max1_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \time_tlock_max1_carry__0_i_1_n_0\,
      DI(2) => '0',
      DI(1) => \time_tlock_max1_carry__0_i_2_n_0\,
      DI(0) => \time_tlock_max1_carry__0_i_3_n_0\,
      O(3 downto 0) => \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \time_tlock_max1_carry__0_i_4_n_0\,
      S(2) => \time_tlock_max1_carry__0_i_5_n_0\,
      S(1) => \time_tlock_max1_carry__0_i_6_n_0\,
      S(0) => \time_tlock_max1_carry__0_i_7_n_0\
    );
\time_tlock_max1_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_tlock_max1_carry__0_i_1_n_0\
    );
\time_tlock_max1_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      O => \time_tlock_max1_carry__0_i_2_n_0\
    );
\time_tlock_max1_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      O => \time_tlock_max1_carry__0_i_3_n_0\
    );
\time_tlock_max1_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(14),
      O => \time_tlock_max1_carry__0_i_4_n_0\
    );
\time_tlock_max1_carry__0_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(13),
      I1 => time_out_counter_reg(12),
      O => \time_tlock_max1_carry__0_i_5_n_0\
    );
\time_tlock_max1_carry__0_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(11),
      I1 => time_out_counter_reg(10),
      O => \time_tlock_max1_carry__0_i_6_n_0\
    );
\time_tlock_max1_carry__0_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(8),
      O => \time_tlock_max1_carry__0_i_7_n_0\
    );
\time_tlock_max1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_tlock_max1_carry__0_n_0\,
      CO(3 downto 2) => \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => time_tlock_max1,
      CO(0) => \time_tlock_max1_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => time_out_counter_reg(18),
      DI(0) => \time_tlock_max1_carry__1_i_1_n_0\,
      O(3 downto 0) => \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \time_tlock_max1_carry__1_i_2_n_0\,
      S(0) => \time_tlock_max1_carry__1_i_3_n_0\
    );
\time_tlock_max1_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(16),
      I1 => time_out_counter_reg(17),
      O => \time_tlock_max1_carry__1_i_1_n_0\
    );
\time_tlock_max1_carry__1_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(18),
      O => \time_tlock_max1_carry__1_i_2_n_0\
    );
\time_tlock_max1_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(17),
      I1 => time_out_counter_reg(16),
      O => \time_tlock_max1_carry__1_i_3_n_0\
    );
time_tlock_max1_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(1),
      O => time_tlock_max1_carry_i_1_n_0
    );
time_tlock_max1_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(7),
      I1 => time_out_counter_reg(6),
      O => time_tlock_max1_carry_i_2_n_0
    );
time_tlock_max1_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(5),
      O => time_tlock_max1_carry_i_3_n_0
    );
time_tlock_max1_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(2),
      I1 => time_out_counter_reg(3),
      O => time_tlock_max1_carry_i_4_n_0
    );
time_tlock_max1_carry_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(1),
      I1 => time_out_counter_reg(0),
      O => time_tlock_max1_carry_i_5_n_0
    );
time_tlock_max_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => check_tlock_max_reg_n_0,
      I1 => time_tlock_max1,
      I2 => time_tlock_max,
      O => time_tlock_max_i_1_n_0
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_tlock_max_i_1_n_0,
      Q => time_tlock_max,
      R => reset_time_out_reg_n_0
    );
\wait_bypass_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_4_n_0\,
      I1 => rx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2_n_0\
    );
\wait_bypass_count[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => \wait_bypass_count[0]_i_6_n_0\,
      I1 => wait_bypass_count_reg(1),
      I2 => wait_bypass_count_reg(11),
      I3 => wait_bypass_count_reg(0),
      I4 => \wait_bypass_count[0]_i_7_n_0\,
      O => \wait_bypass_count[0]_i_4_n_0\
    );
\wait_bypass_count[0]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_5_n_0\
    );
\wait_bypass_count[0]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(9),
      I1 => wait_bypass_count_reg(4),
      I2 => wait_bypass_count_reg(12),
      I3 => wait_bypass_count_reg(2),
      O => \wait_bypass_count[0]_i_6_n_0\
    );
\wait_bypass_count[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => wait_bypass_count_reg(5),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(3),
      I3 => wait_bypass_count_reg(6),
      I4 => wait_bypass_count_reg(10),
      I5 => wait_bypass_count_reg(8),
      O => \wait_bypass_count[0]_i_7_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_5_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[12]_i_1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(12)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(1)
    );
\wait_time_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      O => wait_time_cnt0(2)
    );
\wait_time_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      O => wait_time_cnt0(3)
    );
\wait_time_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      O => wait_time_cnt0(4)
    );
\wait_time_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => wait_time_cnt_reg(5),
      I1 => wait_time_cnt_reg(3),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(0),
      I4 => wait_time_cnt_reg(2),
      I5 => wait_time_cnt_reg(4),
      O => wait_time_cnt0(5)
    );
\wait_time_cnt[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(3),
      O => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(6),
      I1 => \wait_time_cnt[6]_i_4_n_0\,
      O => wait_time_cnt0(6)
    );
\wait_time_cnt[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(1),
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(2),
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(3),
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(4),
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(5),
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(6),
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_GT_WRAPPER is
  port (
    TX_LOCK : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rx_realign_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RXDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RXCHARISK : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    RX_RESETDONE_OUT : out STD_LOGIC;
    hard_err_gt0 : out STD_LOGIC;
    inc_count_r0 : out STD_LOGIC;
    inc_count_r_reg : out STD_LOGIC;
    init_clk_in_0 : out STD_LOGIC;
    \previous_cycle_data_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    D : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \left_align_select_r_reg[1]\ : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
    rxfsm_rxresetdone_r3_reg_0 : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC;
    RXP : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    gt_qpllclk_quad1_in : in STD_LOGIC;
    gt_qpllrefclk_quad1_in : in STD_LOGIC;
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i : in STD_LOGIC;
    gt0_rxprbscntreset_in : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    GTRXRESET_OUT : in STD_LOGIC;
    link_reset_r : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    begin_r : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \word_aligned_data_r_reg[22]\ : in STD_LOGIC;
    \word_aligned_data_r_reg[22]_0\ : in STD_LOGIC;
    enable_err_detect_i : in STD_LOGIC;
    \out\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_GT_WRAPPER : entity is "aurora_1ln_rx_lpm_GT_WRAPPER";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_GT_WRAPPER;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_GT_WRAPPER is
  signal \^rx_resetdone_out\ : STD_LOGIC;
  signal \^tx_lock\ : STD_LOGIC;
  signal cpll_reset_i : STD_LOGIC;
  signal fsm_gt_rx_reset_t : STD_LOGIC;
  signal \gt0_aurora_1ln_rx_lpm_i/ack_flag\ : STD_LOGIC;
  signal \^gt0_rxresetdone_out\ : STD_LOGIC;
  signal gt0_rxresetdone_r3_reg_srl3_n_0 : STD_LOGIC;
  signal gt_rx_reset_i : STD_LOGIC;
  signal gt_rxresetfsm_i_n_3 : STD_LOGIC;
  signal gt_rxuserrdy_i : STD_LOGIC;
  signal gtrxreset_pulse : STD_LOGIC;
  signal gtrxreset_pulse_i_1_n_0 : STD_LOGIC;
  signal gtrxreset_r1 : STD_LOGIC;
  signal gtrxreset_r2 : STD_LOGIC;
  signal gtrxreset_r3 : STD_LOGIC;
  signal gtrxreset_sync : STD_LOGIC;
  signal link_reset_r2 : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal rx_cdrlock_counter : STD_LOGIC;
  signal \rx_cdrlock_counter[10]_i_3_n_0\ : STD_LOGIC;
  signal \rx_cdrlock_counter[10]_i_4_n_0\ : STD_LOGIC;
  signal \rx_cdrlock_counter[10]_i_5_n_0\ : STD_LOGIC;
  signal rx_cdrlock_counter_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal rx_cdrlocked_i_1_n_0 : STD_LOGIC;
  signal rx_cdrlocked_i_2_n_0 : STD_LOGIC;
  signal rx_cdrlocked_i_3_n_0 : STD_LOGIC;
  signal rx_cdrlocked_reg_n_0 : STD_LOGIC;
  signal rxfsm_rxresetdone_r : STD_LOGIC;
  signal rxfsm_rxresetdone_r2 : STD_LOGIC;
  signal rxfsm_soft_reset_r : STD_LOGIC;
  signal rxfsm_soft_reset_r_i_1_n_0 : STD_LOGIC;
  attribute srl_name : string;
  attribute srl_name of gt0_rxresetdone_r3_reg_srl3 : label is "U0/\gt_wrapper_i/gt0_rxresetdone_r3_reg_srl3 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of gt_rx_reset_i_reg : label is "no";
  attribute equivalent_register_removal of gtrxreset_r1_reg : label is "no";
  attribute equivalent_register_removal of link_reset_r2_reg : label is "no";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[0]_i_1\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[10]_i_3\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[10]_i_4\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[1]_i_1\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[2]_i_1\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[3]_i_1\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[4]_i_1\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[6]_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[7]_i_1\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[8]_i_1\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[9]_i_1\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of rx_cdrlocked_i_2 : label is "soft_lutpair133";
  attribute equivalent_register_removal of rxfsm_rxresetdone_r2_reg : label is "no";
begin
  RX_RESETDONE_OUT <= \^rx_resetdone_out\;
  TX_LOCK <= \^tx_lock\;
  gt0_rxresetdone_out <= \^gt0_rxresetdone_out\;
aurora_1ln_rx_lpm_multi_gt_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_multi_gt
     port map (
      D(7 downto 0) => D(7 downto 0),
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPWE_IN => DRPWE_IN,
      E(0) => E(0),
      ENABLE_ERR_DETECT_Buffer_reg(3 downto 0) => ENABLE_ERR_DETECT_Buffer_reg(3 downto 0),
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      Q(3 downto 0) => Q(3 downto 0),
      RXCHARISK(3 downto 0) => RXCHARISK(3 downto 0),
      RXDATA(31 downto 0) => RXDATA(31 downto 0),
      RXN => RXN,
      RXP => RXP,
      SR(0) => gt_rx_reset_i,
      TX_LOCK => \^tx_lock\,
      TX_OUT_CLK => TX_OUT_CLK,
      ack_flag => \gt0_aurora_1ln_rx_lpm_i/ack_flag\,
      begin_r => begin_r,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      ena_comma_align_i => ena_comma_align_i,
      enable_err_detect_i => enable_err_detect_i,
      flag2_reg => gt_rxresetfsm_i_n_3,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_rx_disp_err_out(3 downto 0) => gt0_rx_disp_err_out(3 downto 0),
      gt0_rx_not_in_table_out(3 downto 0) => gt0_rx_not_in_table_out(3 downto 0),
      gt0_rx_realign_out => gt0_rx_realign_out,
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2 downto 0) => gt0_rxbufstatus_out(2 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => \^gt0_rxresetdone_out\,
      gt_qpllclk_quad1_in => gt_qpllclk_quad1_in,
      gt_qpllrefclk_quad1_in => gt_qpllrefclk_quad1_in,
      gt_refclk1 => gt_refclk1,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      hard_err_gt0 => hard_err_gt0,
      inc_count_r0 => inc_count_r0,
      inc_count_r_reg => inc_count_r_reg,
      init_clk_in => init_clk_in,
      init_clk_in_0 => init_clk_in_0,
      \left_align_select_r_reg[1]\ => \left_align_select_r_reg[1]\,
      \previous_cycle_data_r_reg[7]\(3 downto 0) => \previous_cycle_data_r_reg[7]\(3 downto 0),
      rx_polarity_i => rx_polarity_i,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_data_r_reg[22]\ => \word_aligned_data_r_reg[22]\,
      \word_aligned_data_r_reg[22]_0\ => \word_aligned_data_r_reg[22]_0\
    );
gt0_rxresetdone_r3_reg_srl3: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt0_rxresetdone_out\,
      Q => gt0_rxresetdone_r3_reg_srl3_n_0
    );
gt_rx_reset_i_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => fsm_gt_rx_reset_t,
      Q => gt_rx_reset_i,
      R => '0'
    );
gt_rxresetdone_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rx_resetdone_out\,
      O => rxfsm_rxresetdone_r3_reg_0
    );
gt_rxresetfsm_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_rx_startup_fsm
     port map (
      AR(0) => rxfsm_soft_reset_r,
      CPLL_RESET_reg_0 => gt_rxresetfsm_i_n_3,
      TX_LOCK => \^tx_lock\,
      ack_flag => \gt0_aurora_1ln_rx_lpm_i/ack_flag\,
      cpll_reset_i => cpll_reset_i,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      init_clk_in => init_clk_in,
      reset_time_out_reg_0 => rx_cdrlocked_reg_n_0,
      rxfsm_rxresetdone_r => rxfsm_rxresetdone_r,
      user_clk => user_clk
    );
gtrxreset_cdc_sync: entity work.\aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2\
     port map (
      GTRXRESET_OUT => GTRXRESET_OUT,
      init_clk_in => init_clk_in,
      \out\ => gtrxreset_sync,
      user_clk => user_clk
    );
gtrxreset_pulse_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => gtrxreset_r2,
      I1 => gtrxreset_r3,
      O => gtrxreset_pulse_i_1_n_0
    );
gtrxreset_pulse_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_pulse_i_1_n_0,
      Q => gtrxreset_pulse,
      R => '0'
    );
gtrxreset_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_sync,
      Q => gtrxreset_r1,
      R => '0'
    );
gtrxreset_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_r1,
      Q => gtrxreset_r2,
      R => '0'
    );
gtrxreset_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_r2,
      Q => gtrxreset_r3,
      R => '0'
    );
link_reset_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r,
      Q => link_reset_r2,
      R => '0'
    );
\rx_cdrlock_counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(0),
      O => \p_0_in__0\(0)
    );
\rx_cdrlock_counter[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => \rx_cdrlock_counter[10]_i_3_n_0\,
      I1 => rx_cdrlock_counter_reg(2),
      I2 => rx_cdrlock_counter_reg(3),
      I3 => rx_cdrlock_counter_reg(5),
      I4 => rx_cdrlock_counter_reg(4),
      I5 => \rx_cdrlock_counter[10]_i_4_n_0\,
      O => rx_cdrlock_counter
    );
\rx_cdrlock_counter[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC6CCCCCCCCCCCCC"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(9),
      I1 => rx_cdrlock_counter_reg(10),
      I2 => rx_cdrlock_counter_reg(7),
      I3 => \rx_cdrlock_counter[10]_i_5_n_0\,
      I4 => rx_cdrlock_counter_reg(6),
      I5 => rx_cdrlock_counter_reg(8),
      O => \p_0_in__0\(10)
    );
\rx_cdrlock_counter[10]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(1),
      I1 => rx_cdrlock_counter_reg(0),
      O => \rx_cdrlock_counter[10]_i_3_n_0\
    );
\rx_cdrlock_counter[10]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEFF"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(7),
      I1 => rx_cdrlock_counter_reg(6),
      I2 => rx_cdrlock_counter_reg(9),
      I3 => rx_cdrlock_counter_reg(10),
      I4 => rx_cdrlock_counter_reg(8),
      O => \rx_cdrlock_counter[10]_i_4_n_0\
    );
\rx_cdrlock_counter[10]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(4),
      I1 => rx_cdrlock_counter_reg(2),
      I2 => rx_cdrlock_counter_reg(0),
      I3 => rx_cdrlock_counter_reg(1),
      I4 => rx_cdrlock_counter_reg(3),
      I5 => rx_cdrlock_counter_reg(5),
      O => \rx_cdrlock_counter[10]_i_5_n_0\
    );
\rx_cdrlock_counter[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(0),
      I1 => rx_cdrlock_counter_reg(1),
      O => \p_0_in__0\(1)
    );
\rx_cdrlock_counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(1),
      I1 => rx_cdrlock_counter_reg(0),
      I2 => rx_cdrlock_counter_reg(2),
      O => \p_0_in__0\(2)
    );
\rx_cdrlock_counter[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(2),
      I1 => rx_cdrlock_counter_reg(0),
      I2 => rx_cdrlock_counter_reg(1),
      I3 => rx_cdrlock_counter_reg(3),
      O => \p_0_in__0\(3)
    );
\rx_cdrlock_counter[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(3),
      I1 => rx_cdrlock_counter_reg(1),
      I2 => rx_cdrlock_counter_reg(0),
      I3 => rx_cdrlock_counter_reg(2),
      I4 => rx_cdrlock_counter_reg(4),
      O => \p_0_in__0\(4)
    );
\rx_cdrlock_counter[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(4),
      I1 => rx_cdrlock_counter_reg(2),
      I2 => rx_cdrlock_counter_reg(0),
      I3 => rx_cdrlock_counter_reg(1),
      I4 => rx_cdrlock_counter_reg(3),
      I5 => rx_cdrlock_counter_reg(5),
      O => \p_0_in__0\(5)
    );
\rx_cdrlock_counter[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \rx_cdrlock_counter[10]_i_5_n_0\,
      I1 => rx_cdrlock_counter_reg(6),
      O => \p_0_in__0\(6)
    );
\rx_cdrlock_counter[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(6),
      I1 => \rx_cdrlock_counter[10]_i_5_n_0\,
      I2 => rx_cdrlock_counter_reg(7),
      O => \p_0_in__0\(7)
    );
\rx_cdrlock_counter[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(7),
      I1 => \rx_cdrlock_counter[10]_i_5_n_0\,
      I2 => rx_cdrlock_counter_reg(6),
      I3 => rx_cdrlock_counter_reg(8),
      O => \p_0_in__0\(8)
    );
\rx_cdrlock_counter[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FF0800"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(8),
      I1 => rx_cdrlock_counter_reg(6),
      I2 => \rx_cdrlock_counter[10]_i_5_n_0\,
      I3 => rx_cdrlock_counter_reg(7),
      I4 => rx_cdrlock_counter_reg(9),
      O => \p_0_in__0\(9)
    );
\rx_cdrlock_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(0),
      Q => rx_cdrlock_counter_reg(0),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(10),
      Q => rx_cdrlock_counter_reg(10),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(1),
      Q => rx_cdrlock_counter_reg(1),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(2),
      Q => rx_cdrlock_counter_reg(2),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(3),
      Q => rx_cdrlock_counter_reg(3),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(4),
      Q => rx_cdrlock_counter_reg(4),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(5),
      Q => rx_cdrlock_counter_reg(5),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(6),
      Q => rx_cdrlock_counter_reg(6),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(7),
      Q => rx_cdrlock_counter_reg(7),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(8),
      Q => rx_cdrlock_counter_reg(8),
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => rx_cdrlock_counter,
      D => \p_0_in__0\(9),
      Q => rx_cdrlock_counter_reg(9),
      R => gt_rx_reset_i
    );
rx_cdrlocked_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAABAAAA"
    )
        port map (
      I0 => rx_cdrlocked_reg_n_0,
      I1 => \rx_cdrlock_counter[10]_i_3_n_0\,
      I2 => rx_cdrlocked_i_2_n_0,
      I3 => rx_cdrlock_counter_reg(2),
      I4 => rx_cdrlocked_i_3_n_0,
      I5 => gt_rx_reset_i,
      O => rx_cdrlocked_i_1_n_0
    );
rx_cdrlocked_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(9),
      I1 => rx_cdrlock_counter_reg(10),
      O => rx_cdrlocked_i_2_n_0
    );
rx_cdrlocked_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => rx_cdrlock_counter_reg(5),
      I1 => rx_cdrlock_counter_reg(6),
      I2 => rx_cdrlock_counter_reg(4),
      I3 => rx_cdrlock_counter_reg(3),
      I4 => rx_cdrlock_counter_reg(8),
      I5 => rx_cdrlock_counter_reg(7),
      O => rx_cdrlocked_i_3_n_0
    );
rx_cdrlocked_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlocked_i_1_n_0,
      Q => rx_cdrlocked_reg_n_0,
      R => '0'
    );
rxfsm_rxresetdone_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rxfsm_rxresetdone_r,
      Q => rxfsm_rxresetdone_r2,
      R => '0'
    );
rxfsm_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rxfsm_rxresetdone_r2,
      Q => \^rx_resetdone_out\,
      R => '0'
    );
rxfsm_rxresetdone_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt0_rxresetdone_r3_reg_srl3_n_0,
      Q => rxfsm_rxresetdone_r,
      R => '0'
    );
rxfsm_soft_reset_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \out\,
      I1 => gtrxreset_pulse,
      I2 => link_reset_r2,
      O => rxfsm_soft_reset_r_i_1_n_0
    );
rxfsm_soft_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => rxfsm_soft_reset_r_i_1_n_0,
      Q => rxfsm_soft_reset_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE is
  port (
    RX_LANE_UP : out STD_LOGIC;
    LINK_RESET_OUT : out STD_LOGIC;
    ena_comma_align_i : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    begin_r : out STD_LOGIC;
    enable_err_detect_i : out STD_LOGIC;
    GOT_V : out STD_LOGIC;
    RX_PE_DATA : out STD_LOGIC_VECTOR ( 5 downto 0 );
    rx_polarity_i : out STD_LOGIC;
    rx_hard_err_i : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \left_align_select_r_reg[1]\ : out STD_LOGIC;
    \left_align_select_r_reg[0]\ : out STD_LOGIC;
    neqOp : out STD_LOGIC;
    \RX_SUF_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \RX_PE_DATA_Buffer_reg[26]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[26]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[25]\ : out STD_LOGIC;
    \RX_SUF_Buffer_reg[1]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[27]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[16]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \SOFT_ERR_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \RX_PE_DATA_V_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    p_9_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    p_8_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    p_2_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    inc_count_r0 : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[3]\ : in STD_LOGIC;
    hard_err_gt0 : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    begin_r_reg : in STD_LOGIC;
    reset_count_r_reg : in STD_LOGIC;
    reset_count_r_reg_0 : in STD_LOGIC;
    RX_CHANNEL_UP : in STD_LOGIC;
    RXCHARISK : in STD_LOGIC_VECTOR ( 3 downto 0 );
    RXDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[16]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \soft_err_r_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE : entity is "aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE is
  signal RX_CC_Buffer : STD_LOGIC;
  signal \^rx_lane_up\ : STD_LOGIC;
  signal RX_NEG_Buffer : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i_n_7 : STD_LOGIC;
  signal begin_r0 : STD_LOGIC;
  signal \^enable_err_detect_i\ : STD_LOGIC;
  signal first_v_received_r : STD_LOGIC;
  signal good_cnt_r3 : STD_LOGIC;
  signal rx_sp_i : STD_LOGIC;
begin
  RX_LANE_UP <= \^rx_lane_up\;
  enable_err_detect_i <= \^enable_err_detect_i\;
aurora_1ln_rx_lpm_hotplug_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_HOTPLUG
     port map (
      D(0) => RX_CC_Buffer,
      HPCNT_RESET => HPCNT_RESET,
      LINK_RESET_OUT => LINK_RESET_OUT,
      SR(0) => SR(0),
      init_clk_in => init_clk_in,
      user_clk => user_clk
    );
aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE
     port map (
      \SOFT_ERR_Buffer_reg[0]_0\(1 downto 0) => \SOFT_ERR_Buffer_reg[0]\(1 downto 0),
      SR(0) => SR(0),
      begin_r0 => begin_r0,
      enable_err_detect_i => \^enable_err_detect_i\,
      good_cnt_r3 => good_cnt_r3,
      hard_err_gt0 => hard_err_gt0,
      rx_hard_err_i => rx_hard_err_i,
      \soft_err_r_reg[0]_0\(3 downto 0) => \soft_err_r_reg[0]\(3 downto 0),
      user_clk => user_clk
    );
aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE
     port map (
      E(0) => E(0),
      RXCHARISK(1 downto 0) => RXCHARISK(3 downto 2),
      RX_CHANNEL_UP => RX_CHANNEL_UP,
      RX_LANE_UP => \^rx_lane_up\,
      RX_NEG_Buffer => RX_NEG_Buffer,
      SR(0) => SR(0),
      align_r_reg_0 => ena_comma_align_i,
      begin_r => begin_r,
      begin_r0 => begin_r0,
      begin_r_reg_0 => begin_r_reg,
      enable_err_detect_i => \^enable_err_detect_i\,
      first_v_received_r => first_v_received_r,
      good_cnt_r3 => good_cnt_r3,
      inc_count_r0 => inc_count_r0,
      ready_r_reg_0 => aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i_n_7,
      reset_count_r_reg_0 => reset_count_r_reg,
      reset_count_r_reg_1 => reset_count_r_reg_0,
      rx_polarity_i => rx_polarity_i,
      rx_sp_i => rx_sp_i,
      user_clk => user_clk
    );
aurora_1ln_rx_lpm_sym_dec_4byte_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SYM_DEC_4BYTE
     port map (
      D(0) => RX_CC_Buffer,
      GOT_V => GOT_V,
      Q(3 downto 0) => Q(3 downto 0),
      RXCHARISK(3 downto 0) => RXCHARISK(3 downto 0),
      RXDATA(31 downto 0) => RXDATA(31 downto 0),
      RX_LANE_UP => \^rx_lane_up\,
      RX_NEG_Buffer => RX_NEG_Buffer,
      RX_PE_DATA(5 downto 0) => RX_PE_DATA(5 downto 0),
      \RX_PE_DATA_Buffer_reg[25]_0\ => \RX_PE_DATA_Buffer_reg[25]\,
      \RX_PE_DATA_Buffer_reg[26]_0\ => \RX_PE_DATA_Buffer_reg[26]\,
      \RX_PE_DATA_Buffer_reg[26]_1\ => \RX_PE_DATA_Buffer_reg[26]_0\,
      \RX_PE_DATA_V_Buffer_reg[0]_0\(1 downto 0) => \RX_PE_DATA_V_Buffer_reg[0]\(1 downto 0),
      \RX_SUF_Buffer_reg[0]_0\(1 downto 0) => \RX_SUF_Buffer_reg[0]\(1 downto 0),
      \RX_SUF_Buffer_reg[1]_0\ => \RX_SUF_Buffer_reg[1]\,
      first_v_received_r => first_v_received_r,
      \left_align_select_r_reg[0]_0\ => \left_align_select_r_reg[0]\,
      \left_align_select_r_reg[0]_1\ => aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i_n_7,
      \left_align_select_r_reg[1]_0\ => \left_align_select_r_reg[1]\,
      neqOp => neqOp,
      p_2_out(1 downto 0) => p_2_out(1 downto 0),
      p_8_out(1 downto 0) => p_8_out(1 downto 0),
      p_9_out(1 downto 0) => p_9_out(1 downto 0),
      rx_sp_i => rx_sp_i,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[3]_0\ => \word_aligned_control_bits_r_reg[3]\,
      \word_aligned_data_r_reg[0]_0\(7 downto 0) => \word_aligned_data_r_reg[0]\(7 downto 0),
      \word_aligned_data_r_reg[11]_0\(4 downto 0) => \word_aligned_data_r_reg[11]\(4 downto 0),
      \word_aligned_data_r_reg[16]_0\(7 downto 0) => \word_aligned_data_r_reg[16]\(7 downto 0),
      \word_aligned_data_r_reg[16]_1\(3 downto 0) => \word_aligned_data_r_reg[16]_0\(3 downto 0),
      \word_aligned_data_r_reg[24]_0\(7 downto 0) => D(7 downto 0),
      \word_aligned_data_r_reg[27]_0\(4 downto 0) => \word_aligned_data_r_reg[27]\(4 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL is
  port (
    rx_eof : out STD_LOGIC;
    FRAME_ERR : out STD_LOGIC;
    M_AXI_RX_TLAST : out STD_LOGIC;
    M_AXI_RX_TVALID : out STD_LOGIC;
    M_AXI_UFC_RX_TVALID : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_UFC_RX_TKEEP : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_UFC_RX_TLAST : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    RESET : in STD_LOGIC;
    neqOp : in STD_LOGIC;
    \rx_suf_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_8_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_9_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_2_out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \stage_1_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    RX_PE_DATA : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \stage_1_data_r_reg[11]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \stage_1_data_r_reg[16]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[27]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    START_RX : in STD_LOGIC;
    \stage_1_count_value_r_reg[0]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL : entity is "aurora_1ln_rx_lpm_RX_LL";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL is
  signal UFC_START : STD_LOGIC;
  signal barrel_shifter_control_i : STD_LOGIC;
  signal pdu_data_v_i : STD_LOGIC_VECTOR ( 0 to 1 );
  signal pdu_ecp_i : STD_LOGIC_VECTOR ( 0 to 1 );
  signal pdu_scp_i : STD_LOGIC_VECTOR ( 0 to 1 );
  signal plusOp : STD_LOGIC;
  signal stage_1_data_r : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \stage_1_rx_ll_deframer_i/S1_in\ : STD_LOGIC;
  signal ufc_filter_i_n_10 : STD_LOGIC;
  signal ufc_filter_i_n_11 : STD_LOGIC;
  signal ufc_filter_i_n_12 : STD_LOGIC;
  signal ufc_filter_i_n_13 : STD_LOGIC;
  signal ufc_filter_i_n_14 : STD_LOGIC;
  signal ufc_filter_i_n_15 : STD_LOGIC;
  signal ufc_filter_i_n_16 : STD_LOGIC;
  signal ufc_filter_i_n_17 : STD_LOGIC;
  signal ufc_filter_i_n_18 : STD_LOGIC;
  signal ufc_filter_i_n_19 : STD_LOGIC;
  signal ufc_filter_i_n_20 : STD_LOGIC;
  signal ufc_filter_i_n_21 : STD_LOGIC;
  signal ufc_filter_i_n_22 : STD_LOGIC;
  signal ufc_filter_i_n_23 : STD_LOGIC;
  signal ufc_filter_i_n_24 : STD_LOGIC;
  signal ufc_filter_i_n_25 : STD_LOGIC;
  signal ufc_filter_i_n_26 : STD_LOGIC;
  signal ufc_filter_i_n_27 : STD_LOGIC;
  signal ufc_filter_i_n_28 : STD_LOGIC;
  signal ufc_filter_i_n_29 : STD_LOGIC;
  signal ufc_filter_i_n_30 : STD_LOGIC;
  signal ufc_filter_i_n_31 : STD_LOGIC;
  signal ufc_filter_i_n_32 : STD_LOGIC;
  signal ufc_filter_i_n_33 : STD_LOGIC;
  signal ufc_filter_i_n_34 : STD_LOGIC;
  signal ufc_filter_i_n_35 : STD_LOGIC;
  signal ufc_filter_i_n_36 : STD_LOGIC;
  signal ufc_filter_i_n_37 : STD_LOGIC;
  signal ufc_filter_i_n_38 : STD_LOGIC;
  signal ufc_filter_i_n_39 : STD_LOGIC;
  signal ufc_filter_i_n_40 : STD_LOGIC;
  signal ufc_filter_i_n_44 : STD_LOGIC;
  signal ufc_filter_i_n_45 : STD_LOGIC;
  signal ufc_filter_i_n_6 : STD_LOGIC;
  signal ufc_filter_i_n_7 : STD_LOGIC;
  signal ufc_filter_i_n_8 : STD_LOGIC;
  signal ufc_filter_i_n_9 : STD_LOGIC;
begin
rx_ll_pdu_datapath_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH
     port map (
      \AFTER_SCP_Buffer_reg[1]\ => ufc_filter_i_n_45,
      D(1) => pdu_scp_i(0),
      D(0) => pdu_scp_i(1),
      FRAME_ERR => FRAME_ERR,
      \IN_FRAME_Buffer_reg[1]\ => ufc_filter_i_n_40,
      M_AXI_RX_TDATA(31 downto 0) => M_AXI_RX_TDATA(31 downto 0),
      M_AXI_RX_TLAST => M_AXI_RX_TLAST,
      M_AXI_RX_TVALID => M_AXI_RX_TVALID,
      Q(1) => pdu_data_v_i(0),
      Q(0) => pdu_data_v_i(1),
      RESET => RESET,
      \RX_REM_Buffer_reg[0]_0\(1 downto 0) => Q(1 downto 0),
      S1_in => \stage_1_rx_ll_deframer_i/S1_in\,
      START_RX => START_RX,
      in_frame_r_reg => ufc_filter_i_n_39,
      rx_eof => rx_eof,
      \stage_1_ecp_r_reg[0]_0\(1) => pdu_ecp_i(0),
      \stage_1_ecp_r_reg[0]_0\(0) => pdu_ecp_i(1),
      stage_1_pad_r_reg_0 => ufc_filter_i_n_38,
      \stage_2_data_r_reg[0]_0\(31) => stage_1_data_r(0),
      \stage_2_data_r_reg[0]_0\(30) => stage_1_data_r(1),
      \stage_2_data_r_reg[0]_0\(29) => stage_1_data_r(2),
      \stage_2_data_r_reg[0]_0\(28) => stage_1_data_r(3),
      \stage_2_data_r_reg[0]_0\(27) => stage_1_data_r(4),
      \stage_2_data_r_reg[0]_0\(26) => stage_1_data_r(5),
      \stage_2_data_r_reg[0]_0\(25) => stage_1_data_r(6),
      \stage_2_data_r_reg[0]_0\(24) => stage_1_data_r(7),
      \stage_2_data_r_reg[0]_0\(23) => stage_1_data_r(8),
      \stage_2_data_r_reg[0]_0\(22) => stage_1_data_r(9),
      \stage_2_data_r_reg[0]_0\(21) => stage_1_data_r(10),
      \stage_2_data_r_reg[0]_0\(20) => stage_1_data_r(11),
      \stage_2_data_r_reg[0]_0\(19) => stage_1_data_r(12),
      \stage_2_data_r_reg[0]_0\(18) => stage_1_data_r(13),
      \stage_2_data_r_reg[0]_0\(17) => stage_1_data_r(14),
      \stage_2_data_r_reg[0]_0\(16) => stage_1_data_r(15),
      \stage_2_data_r_reg[0]_0\(15) => stage_1_data_r(16),
      \stage_2_data_r_reg[0]_0\(14) => stage_1_data_r(17),
      \stage_2_data_r_reg[0]_0\(13) => stage_1_data_r(18),
      \stage_2_data_r_reg[0]_0\(12) => stage_1_data_r(19),
      \stage_2_data_r_reg[0]_0\(11) => stage_1_data_r(20),
      \stage_2_data_r_reg[0]_0\(10) => stage_1_data_r(21),
      \stage_2_data_r_reg[0]_0\(9) => stage_1_data_r(22),
      \stage_2_data_r_reg[0]_0\(8) => stage_1_data_r(23),
      \stage_2_data_r_reg[0]_0\(7) => stage_1_data_r(24),
      \stage_2_data_r_reg[0]_0\(6) => stage_1_data_r(25),
      \stage_2_data_r_reg[0]_0\(5) => stage_1_data_r(26),
      \stage_2_data_r_reg[0]_0\(4) => stage_1_data_r(27),
      \stage_2_data_r_reg[0]_0\(3) => stage_1_data_r(28),
      \stage_2_data_r_reg[0]_0\(2) => stage_1_data_r(29),
      \stage_2_data_r_reg[0]_0\(1) => stage_1_data_r(30),
      \stage_2_data_r_reg[0]_0\(0) => stage_1_data_r(31),
      user_clk => user_clk
    );
rx_ll_ufc_datapath_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH
     port map (
      M_AXI_UFC_RX_TDATA(31 downto 0) => M_AXI_UFC_RX_TDATA(31 downto 0),
      M_AXI_UFC_RX_TKEEP(0) => M_AXI_UFC_RX_TKEEP(0),
      M_AXI_UFC_RX_TLAST => M_AXI_UFC_RX_TLAST,
      M_AXI_UFC_RX_TVALID => M_AXI_UFC_RX_TVALID,
      Q(1) => plusOp,
      Q(0) => ufc_filter_i_n_44,
      RESET => RESET,
      UFC_START => UFC_START,
      barrel_shifter_control_i => barrel_shifter_control_i,
      \stage_1_data_r_reg[0]_0\(31) => stage_1_data_r(0),
      \stage_1_data_r_reg[0]_0\(30) => stage_1_data_r(1),
      \stage_1_data_r_reg[0]_0\(29) => stage_1_data_r(2),
      \stage_1_data_r_reg[0]_0\(28) => stage_1_data_r(3),
      \stage_1_data_r_reg[0]_0\(27) => stage_1_data_r(4),
      \stage_1_data_r_reg[0]_0\(26) => stage_1_data_r(5),
      \stage_1_data_r_reg[0]_0\(25) => stage_1_data_r(6),
      \stage_1_data_r_reg[0]_0\(24) => stage_1_data_r(7),
      \stage_1_data_r_reg[0]_0\(23) => stage_1_data_r(8),
      \stage_1_data_r_reg[0]_0\(22) => stage_1_data_r(9),
      \stage_1_data_r_reg[0]_0\(21) => stage_1_data_r(10),
      \stage_1_data_r_reg[0]_0\(20) => stage_1_data_r(11),
      \stage_1_data_r_reg[0]_0\(19) => stage_1_data_r(12),
      \stage_1_data_r_reg[0]_0\(18) => stage_1_data_r(13),
      \stage_1_data_r_reg[0]_0\(17) => stage_1_data_r(14),
      \stage_1_data_r_reg[0]_0\(16) => stage_1_data_r(15),
      \stage_1_data_r_reg[0]_0\(15) => stage_1_data_r(16),
      \stage_1_data_r_reg[0]_0\(14) => stage_1_data_r(17),
      \stage_1_data_r_reg[0]_0\(13) => stage_1_data_r(18),
      \stage_1_data_r_reg[0]_0\(12) => stage_1_data_r(19),
      \stage_1_data_r_reg[0]_0\(11) => stage_1_data_r(20),
      \stage_1_data_r_reg[0]_0\(10) => stage_1_data_r(21),
      \stage_1_data_r_reg[0]_0\(9) => stage_1_data_r(22),
      \stage_1_data_r_reg[0]_0\(8) => stage_1_data_r(23),
      \stage_1_data_r_reg[0]_0\(7) => stage_1_data_r(24),
      \stage_1_data_r_reg[0]_0\(6) => stage_1_data_r(25),
      \stage_1_data_r_reg[0]_0\(5) => stage_1_data_r(26),
      \stage_1_data_r_reg[0]_0\(4) => stage_1_data_r(27),
      \stage_1_data_r_reg[0]_0\(3) => stage_1_data_r(28),
      \stage_1_data_r_reg[0]_0\(2) => stage_1_data_r(29),
      \stage_1_data_r_reg[0]_0\(1) => stage_1_data_r(30),
      \stage_1_data_r_reg[0]_0\(0) => stage_1_data_r(31),
      \stage_1_data_r_reg[0]_1\ => ufc_filter_i_n_6,
      \stage_1_data_r_reg[10]_0\ => ufc_filter_i_n_16,
      \stage_1_data_r_reg[11]_0\ => ufc_filter_i_n_17,
      \stage_1_data_r_reg[12]_0\ => ufc_filter_i_n_18,
      \stage_1_data_r_reg[13]_0\ => ufc_filter_i_n_19,
      \stage_1_data_r_reg[14]_0\ => ufc_filter_i_n_20,
      \stage_1_data_r_reg[15]_0\ => ufc_filter_i_n_21,
      \stage_1_data_r_reg[16]_0\ => ufc_filter_i_n_22,
      \stage_1_data_r_reg[17]_0\ => ufc_filter_i_n_23,
      \stage_1_data_r_reg[18]_0\ => ufc_filter_i_n_24,
      \stage_1_data_r_reg[19]_0\ => ufc_filter_i_n_25,
      \stage_1_data_r_reg[1]_0\ => ufc_filter_i_n_7,
      \stage_1_data_r_reg[20]_0\ => ufc_filter_i_n_26,
      \stage_1_data_r_reg[21]_0\ => ufc_filter_i_n_27,
      \stage_1_data_r_reg[22]_0\ => ufc_filter_i_n_28,
      \stage_1_data_r_reg[23]_0\ => ufc_filter_i_n_29,
      \stage_1_data_r_reg[24]_0\ => ufc_filter_i_n_30,
      \stage_1_data_r_reg[25]_0\ => ufc_filter_i_n_31,
      \stage_1_data_r_reg[26]_0\ => ufc_filter_i_n_32,
      \stage_1_data_r_reg[27]_0\ => ufc_filter_i_n_33,
      \stage_1_data_r_reg[28]_0\ => ufc_filter_i_n_34,
      \stage_1_data_r_reg[29]_0\ => ufc_filter_i_n_35,
      \stage_1_data_r_reg[2]_0\ => ufc_filter_i_n_8,
      \stage_1_data_r_reg[30]_0\ => ufc_filter_i_n_36,
      \stage_1_data_r_reg[31]_0\ => ufc_filter_i_n_37,
      \stage_1_data_r_reg[3]_0\ => ufc_filter_i_n_9,
      \stage_1_data_r_reg[4]_0\ => ufc_filter_i_n_10,
      \stage_1_data_r_reg[5]_0\ => ufc_filter_i_n_11,
      \stage_1_data_r_reg[6]_0\ => ufc_filter_i_n_12,
      \stage_1_data_r_reg[7]_0\ => ufc_filter_i_n_13,
      \stage_1_data_r_reg[8]_0\ => ufc_filter_i_n_14,
      \stage_1_data_r_reg[9]_0\ => ufc_filter_i_n_15,
      user_clk => user_clk
    );
ufc_filter_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_FILTER
     port map (
      D(1) => pdu_scp_i(0),
      D(0) => pdu_scp_i(1),
      \PDU_ECP_Buffer_reg[0]_0\(1) => pdu_ecp_i(0),
      \PDU_ECP_Buffer_reg[0]_0\(0) => pdu_ecp_i(1),
      \PDU_ECP_Buffer_reg[0]_1\ => ufc_filter_i_n_40,
      \PDU_ECP_Buffer_reg[1]_0\ => ufc_filter_i_n_39,
      \PDU_PAD_Buffer_reg[0]_0\ => ufc_filter_i_n_38,
      \PDU_SCP_Buffer_reg[1]_0\ => ufc_filter_i_n_45,
      Q(1) => pdu_data_v_i(0),
      Q(0) => pdu_data_v_i(1),
      RESET => RESET,
      RX_PE_DATA(5 downto 0) => RX_PE_DATA(5 downto 0),
      \RX_PE_DATA_Buffer_reg[10]\ => ufc_filter_i_n_16,
      \RX_PE_DATA_Buffer_reg[24]\ => ufc_filter_i_n_30,
      \RX_PE_DATA_Buffer_reg[25]\ => ufc_filter_i_n_31,
      \RX_PE_DATA_Buffer_reg[26]\ => ufc_filter_i_n_32,
      \RX_PE_DATA_Buffer_reg[8]\ => ufc_filter_i_n_14,
      \RX_PE_DATA_Buffer_reg[9]\ => ufc_filter_i_n_15,
      S1_in => \stage_1_rx_ll_deframer_i/S1_in\,
      \UFC_DATA_V_Buffer_reg[0]_0\(1) => plusOp,
      \UFC_DATA_V_Buffer_reg[0]_0\(0) => ufc_filter_i_n_44,
      UFC_START => UFC_START,
      barrel_shifter_control_i => barrel_shifter_control_i,
      neqOp => neqOp,
      p_2_out(1 downto 0) => p_2_out(1 downto 0),
      p_8_out(1 downto 0) => p_8_out(1 downto 0),
      p_9_out(1 downto 0) => p_9_out(1 downto 0),
      \rx_data_v_r_reg[0]_0\(1 downto 0) => D(1 downto 0),
      \rx_suf_r_reg[0]_0\(1 downto 0) => \rx_suf_r_reg[0]\(1 downto 0),
      \stage_1_count_value_r_reg[0]_0\ => \stage_1_count_value_r_reg[0]\,
      \stage_1_count_value_r_reg[1]_0\ => \stage_1_count_value_r_reg[1]\,
      \stage_1_count_value_r_reg[2]_0\ => \stage_1_count_value_r_reg[2]\,
      \stage_1_count_value_r_reg[3]_0\ => \stage_1_count_value_r_reg[3]\,
      \stage_1_data_r_reg[0]\(7 downto 0) => \stage_1_data_r_reg[0]\(7 downto 0),
      \stage_1_data_r_reg[11]\(4 downto 0) => \stage_1_data_r_reg[11]\(4 downto 0),
      \stage_1_data_r_reg[16]\(7 downto 0) => \stage_1_data_r_reg[16]\(7 downto 0),
      \stage_1_data_r_reg[27]\(4 downto 0) => \stage_1_data_r_reg[27]\(4 downto 0),
      user_clk => user_clk,
      \word_aligned_data_r_reg[0]\ => ufc_filter_i_n_6,
      \word_aligned_data_r_reg[11]\ => ufc_filter_i_n_17,
      \word_aligned_data_r_reg[12]\ => ufc_filter_i_n_18,
      \word_aligned_data_r_reg[13]\ => ufc_filter_i_n_19,
      \word_aligned_data_r_reg[14]\ => ufc_filter_i_n_20,
      \word_aligned_data_r_reg[15]\ => ufc_filter_i_n_21,
      \word_aligned_data_r_reg[16]\ => ufc_filter_i_n_22,
      \word_aligned_data_r_reg[17]\ => ufc_filter_i_n_23,
      \word_aligned_data_r_reg[18]\ => ufc_filter_i_n_24,
      \word_aligned_data_r_reg[19]\ => ufc_filter_i_n_25,
      \word_aligned_data_r_reg[1]\ => ufc_filter_i_n_7,
      \word_aligned_data_r_reg[20]\ => ufc_filter_i_n_26,
      \word_aligned_data_r_reg[21]\ => ufc_filter_i_n_27,
      \word_aligned_data_r_reg[22]\ => ufc_filter_i_n_28,
      \word_aligned_data_r_reg[23]\ => ufc_filter_i_n_29,
      \word_aligned_data_r_reg[27]\ => ufc_filter_i_n_33,
      \word_aligned_data_r_reg[28]\ => ufc_filter_i_n_34,
      \word_aligned_data_r_reg[29]\ => ufc_filter_i_n_35,
      \word_aligned_data_r_reg[2]\ => ufc_filter_i_n_8,
      \word_aligned_data_r_reg[30]\ => ufc_filter_i_n_36,
      \word_aligned_data_r_reg[31]\ => ufc_filter_i_n_37,
      \word_aligned_data_r_reg[3]\ => ufc_filter_i_n_9,
      \word_aligned_data_r_reg[4]\ => ufc_filter_i_n_10,
      \word_aligned_data_r_reg[5]\ => ufc_filter_i_n_11,
      \word_aligned_data_r_reg[6]\ => ufc_filter_i_n_12,
      \word_aligned_data_r_reg[7]\ => ufc_filter_i_n_13
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core is
  port (
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_RX_TKEEP : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_RX_TVALID : out STD_LOGIC;
    M_AXI_RX_TLAST : out STD_LOGIC;
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_UFC_RX_TKEEP : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_UFC_RX_TVALID : out STD_LOGIC;
    M_AXI_UFC_RX_TLAST : out STD_LOGIC;
    RXP : in STD_LOGIC;
    RXN : in STD_LOGIC;
    gt_refclk1 : in STD_LOGIC;
    RX_HARD_ERR : out STD_LOGIC;
    SOFT_ERR : out STD_LOGIC;
    FRAME_ERR : out STD_LOGIC;
    RX_CHANNEL_UP : out STD_LOGIC;
    RX_LANE_UP : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    RX_SYSTEM_RESET : in STD_LOGIC;
    RX_RESETDONE_OUT : out STD_LOGIC;
    LINK_RESET_OUT : out STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    GT_RESET : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    PLL_NOT_LOCKED : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN : in STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt0_qplllock_in : in STD_LOGIC;
    gt0_qpllrefclklost_in : in STD_LOGIC;
    gt0_qpllreset_out : out STD_LOGIC;
    gt_qpllclk_quad1_in : in STD_LOGIC;
    gt_qpllrefclk_quad1_in : in STD_LOGIC;
    gt0_cplllock_out : out STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_realign_out : out STD_LOGIC;
    gt0_rx_buf_err_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    sys_reset_out : out STD_LOGIC;
    TX_LOCK : out STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core : entity is "aurora_1ln_rx_lpm_core";
  attribute SIM_GTRESET_SPEEDUP : string;
  attribute SIM_GTRESET_SPEEDUP of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core : entity is "FALSE";
end aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core;

architecture STRUCTURE of aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal GOT_V : STD_LOGIC;
  signal GTRXRESET_OUT : STD_LOGIC;
  signal HPCNT_RESET : STD_LOGIC;
  signal \^link_reset_out\ : STD_LOGIC;
  signal \^m_axi_rx_tkeep\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \^m_axi_ufc_rx_tkeep\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal RESET : STD_LOGIC;
  signal \^rx_channel_up\ : STD_LOGIC;
  signal \^rx_lane_up\ : STD_LOGIC;
  signal RX_PE_DATA : STD_LOGIC_VECTOR ( 8 to 26 );
  signal RX_PE_DATA_V : STD_LOGIC_VECTOR ( 0 to 1 );
  signal START_RX : STD_LOGIC;
  signal \^tx_lock\ : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_19 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_20 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_24 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_25 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_26 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_27 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_28 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_29 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_30 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_31 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_32 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_33 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_34 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_35 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_36 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_37 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_38 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_39 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_40 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_42 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_43 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_44 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_45 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_46 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_47 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_48 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_49 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_50 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_51 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_52 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_53 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_54 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_55 : STD_LOGIC;
  signal \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/hard_err_gt0\ : STD_LOGIC;
  signal \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/begin_r\ : STD_LOGIC;
  signal \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r\ : STD_LOGIC;
  signal \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r0\ : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_ll_i_n_5 : STD_LOGIC;
  signal aurora_1ln_rx_lpm_rx_ll_i_n_6 : STD_LOGIC;
  signal \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_2_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_8_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_9_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal ena_comma_align_i : STD_LOGIC;
  signal enable_err_detect_i : STD_LOGIC;
  signal \^gt0_rx_buf_err_out\ : STD_LOGIC;
  signal \^gt0_rx_realign_out\ : STD_LOGIC;
  signal \^gt0_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gt_reset_sync_init_clk : STD_LOGIC;
  signal gt_wrapper_i_n_100 : STD_LOGIC;
  signal gt_wrapper_i_n_101 : STD_LOGIC;
  signal gt_wrapper_i_n_102 : STD_LOGIC;
  signal gt_wrapper_i_n_103 : STD_LOGIC;
  signal gt_wrapper_i_n_104 : STD_LOGIC;
  signal gt_wrapper_i_n_105 : STD_LOGIC;
  signal gt_wrapper_i_n_106 : STD_LOGIC;
  signal gt_wrapper_i_n_107 : STD_LOGIC;
  signal gt_wrapper_i_n_108 : STD_LOGIC;
  signal gt_wrapper_i_n_109 : STD_LOGIC;
  signal gt_wrapper_i_n_110 : STD_LOGIC;
  signal gt_wrapper_i_n_111 : STD_LOGIC;
  signal gt_wrapper_i_n_112 : STD_LOGIC;
  signal gt_wrapper_i_n_114 : STD_LOGIC;
  signal gt_wrapper_i_n_116 : STD_LOGIC;
  signal gt_wrapper_i_n_117 : STD_LOGIC;
  signal gt_wrapper_i_n_98 : STD_LOGIC;
  signal gt_wrapper_i_n_99 : STD_LOGIC;
  signal link_reset_r : STD_LOGIC;
  signal neqOp : STD_LOGIC;
  signal previous_cycle_data_r : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal reset_sync_init_clk : STD_LOGIC;
  signal reset_sync_user_clk : STD_LOGIC;
  signal rx_char_is_k_i : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rx_data_i : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal rx_eof : STD_LOGIC;
  signal rx_hard_err_i : STD_LOGIC;
  signal rx_polarity_i : STD_LOGIC;
  signal rx_reset_lanes_i : STD_LOGIC;
  signal rx_suf_i : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \^sys_reset_out\ : STD_LOGIC;
begin
  LINK_RESET_OUT <= \^link_reset_out\;
  M_AXI_RX_TKEEP(3 downto 1) <= \^m_axi_rx_tkeep\(3 downto 1);
  M_AXI_RX_TKEEP(0) <= \<const1>\;
  M_AXI_UFC_RX_TKEEP(3) <= \^m_axi_ufc_rx_tkeep\(3);
  M_AXI_UFC_RX_TKEEP(2) <= \^m_axi_ufc_rx_tkeep\(3);
  M_AXI_UFC_RX_TKEEP(1) <= \<const1>\;
  M_AXI_UFC_RX_TKEEP(0) <= \<const1>\;
  RX_CHANNEL_UP <= \^rx_channel_up\;
  RX_LANE_UP <= \^rx_lane_up\;
  TX_LOCK <= \^tx_lock\;
  gt0_cplllock_out <= \^tx_lock\;
  gt0_qpllreset_out <= \<const0>\;
  gt0_rx_buf_err_out <= \^gt0_rx_buf_err_out\;
  gt0_rx_realign_out <= \^gt0_rx_realign_out\;
  gt0_rxbufstatus_out(2) <= \^gt0_rx_buf_err_out\;
  gt0_rxbufstatus_out(1 downto 0) <= \^gt0_rxbufstatus_out\(1 downto 0);
  sys_reset_out <= \^sys_reset_out\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE
     port map (
      D(7) => gt_wrapper_i_n_104,
      D(6) => gt_wrapper_i_n_105,
      D(5) => gt_wrapper_i_n_106,
      D(4) => gt_wrapper_i_n_107,
      D(3) => gt_wrapper_i_n_108,
      D(2) => gt_wrapper_i_n_109,
      D(1) => gt_wrapper_i_n_110,
      D(0) => gt_wrapper_i_n_111,
      E(0) => \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r\,
      GOT_V => GOT_V,
      HPCNT_RESET => HPCNT_RESET,
      LINK_RESET_OUT => \^link_reset_out\,
      Q(3) => previous_cycle_data_r(7),
      Q(2) => previous_cycle_data_r(5),
      Q(1) => previous_cycle_data_r(3),
      Q(0) => previous_cycle_data_r(1),
      RXCHARISK(3 downto 0) => rx_char_is_k_i(3 downto 0),
      RXDATA(31 downto 0) => rx_data_i(31 downto 0),
      RX_CHANNEL_UP => \^rx_channel_up\,
      RX_LANE_UP => \^rx_lane_up\,
      RX_PE_DATA(5) => RX_PE_DATA(8),
      RX_PE_DATA(4) => RX_PE_DATA(9),
      RX_PE_DATA(3) => RX_PE_DATA(10),
      RX_PE_DATA(2) => RX_PE_DATA(24),
      RX_PE_DATA(1) => RX_PE_DATA(25),
      RX_PE_DATA(0) => RX_PE_DATA(26),
      \RX_PE_DATA_Buffer_reg[25]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_26,
      \RX_PE_DATA_Buffer_reg[26]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_24,
      \RX_PE_DATA_Buffer_reg[26]_0\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_25,
      \RX_PE_DATA_V_Buffer_reg[0]\(1) => RX_PE_DATA_V(0),
      \RX_PE_DATA_V_Buffer_reg[0]\(0) => RX_PE_DATA_V(1),
      \RX_SUF_Buffer_reg[0]\(1) => rx_suf_i(0),
      \RX_SUF_Buffer_reg[0]\(0) => rx_suf_i(1),
      \RX_SUF_Buffer_reg[1]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_27,
      \SOFT_ERR_Buffer_reg[0]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_54,
      \SOFT_ERR_Buffer_reg[0]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_55,
      SR(0) => rx_reset_lanes_i,
      begin_r => \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/begin_r\,
      begin_r_reg => \^gt0_rx_realign_out\,
      ena_comma_align_i => ena_comma_align_i,
      enable_err_detect_i => enable_err_detect_i,
      hard_err_gt0 => \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/hard_err_gt0\,
      inc_count_r0 => \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r0\,
      init_clk_in => init_clk_in,
      \left_align_select_r_reg[0]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_20,
      \left_align_select_r_reg[1]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_19,
      neqOp => neqOp,
      p_2_out(1 downto 0) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_2_out\(1 downto 0),
      p_8_out(1 downto 0) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_8_out\(1 downto 0),
      p_9_out(1 downto 0) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_9_out\(1 downto 0),
      reset_count_r_reg => gt_wrapper_i_n_99,
      reset_count_r_reg_0 => gt_wrapper_i_n_98,
      rx_hard_err_i => rx_hard_err_i,
      rx_polarity_i => rx_polarity_i,
      \soft_err_r_reg[0]\(3) => \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out\(3),
      \soft_err_r_reg[0]\(2) => gt_wrapper_i_n_114,
      \soft_err_r_reg[0]\(1) => \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out\(1),
      \soft_err_r_reg[0]\(0) => gt_wrapper_i_n_116,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[3]\ => gt_wrapper_i_n_112,
      \word_aligned_data_r_reg[0]\(7) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_46,
      \word_aligned_data_r_reg[0]\(6) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_47,
      \word_aligned_data_r_reg[0]\(5) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_48,
      \word_aligned_data_r_reg[0]\(4) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_49,
      \word_aligned_data_r_reg[0]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_50,
      \word_aligned_data_r_reg[0]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_51,
      \word_aligned_data_r_reg[0]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_52,
      \word_aligned_data_r_reg[0]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_53,
      \word_aligned_data_r_reg[11]\(4) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_0_in\(0),
      \word_aligned_data_r_reg[11]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_42,
      \word_aligned_data_r_reg[11]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_43,
      \word_aligned_data_r_reg[11]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_44,
      \word_aligned_data_r_reg[11]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_45,
      \word_aligned_data_r_reg[16]\(7) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_33,
      \word_aligned_data_r_reg[16]\(6) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_34,
      \word_aligned_data_r_reg[16]\(5) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_35,
      \word_aligned_data_r_reg[16]\(4) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_36,
      \word_aligned_data_r_reg[16]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_37,
      \word_aligned_data_r_reg[16]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_38,
      \word_aligned_data_r_reg[16]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_39,
      \word_aligned_data_r_reg[16]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_40,
      \word_aligned_data_r_reg[16]_0\(3) => gt_wrapper_i_n_100,
      \word_aligned_data_r_reg[16]_0\(2) => gt_wrapper_i_n_101,
      \word_aligned_data_r_reg[16]_0\(1) => gt_wrapper_i_n_102,
      \word_aligned_data_r_reg[16]_0\(0) => gt_wrapper_i_n_103,
      \word_aligned_data_r_reg[27]\(4) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_28,
      \word_aligned_data_r_reg[27]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_29,
      \word_aligned_data_r_reg[27]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_30,
      \word_aligned_data_r_reg[27]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_31,
      \word_aligned_data_r_reg[27]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_32
    );
aurora_1ln_rx_lpm_rx_global_logic_simplex_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX
     port map (
      D(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_54,
      D(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_55,
      GOT_V => GOT_V,
      GTRXRESET_OUT => GTRXRESET_OUT,
      POWER_DOWN => POWER_DOWN,
      RESET => RESET,
      RX_CHANNEL_UP => \^rx_channel_up\,
      RX_HARD_ERR => RX_HARD_ERR,
      RX_LANE_UP => \^rx_lane_up\,
      SOFT_ERR => SOFT_ERR,
      SR(0) => rx_reset_lanes_i,
      START_RX => START_RX,
      START_RX_Buffer_reg => \^sys_reset_out\,
      rx_hard_err_i => rx_hard_err_i,
      user_clk => user_clk
    );
aurora_1ln_rx_lpm_rx_ll_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL
     port map (
      D(1) => RX_PE_DATA_V(0),
      D(0) => RX_PE_DATA_V(1),
      FRAME_ERR => FRAME_ERR,
      M_AXI_RX_TDATA(31 downto 0) => M_AXI_RX_TDATA(31 downto 0),
      M_AXI_RX_TLAST => M_AXI_RX_TLAST,
      M_AXI_RX_TVALID => M_AXI_RX_TVALID,
      M_AXI_UFC_RX_TDATA(31 downto 0) => M_AXI_UFC_RX_TDATA(31 downto 0),
      M_AXI_UFC_RX_TKEEP(0) => \^m_axi_ufc_rx_tkeep\(3),
      M_AXI_UFC_RX_TLAST => M_AXI_UFC_RX_TLAST,
      M_AXI_UFC_RX_TVALID => M_AXI_UFC_RX_TVALID,
      Q(1) => aurora_1ln_rx_lpm_rx_ll_i_n_5,
      Q(0) => aurora_1ln_rx_lpm_rx_ll_i_n_6,
      RESET => RESET,
      RX_PE_DATA(5) => RX_PE_DATA(8),
      RX_PE_DATA(4) => RX_PE_DATA(9),
      RX_PE_DATA(3) => RX_PE_DATA(10),
      RX_PE_DATA(2) => RX_PE_DATA(24),
      RX_PE_DATA(1) => RX_PE_DATA(25),
      RX_PE_DATA(0) => RX_PE_DATA(26),
      START_RX => START_RX,
      neqOp => neqOp,
      p_2_out(1 downto 0) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_2_out\(1 downto 0),
      p_8_out(1 downto 0) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_8_out\(1 downto 0),
      p_9_out(1 downto 0) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_9_out\(1 downto 0),
      rx_eof => rx_eof,
      \rx_suf_r_reg[0]\(1) => rx_suf_i(0),
      \rx_suf_r_reg[0]\(0) => rx_suf_i(1),
      \stage_1_count_value_r_reg[0]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_27,
      \stage_1_count_value_r_reg[1]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_26,
      \stage_1_count_value_r_reg[2]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_25,
      \stage_1_count_value_r_reg[3]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_24,
      \stage_1_data_r_reg[0]\(7) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_46,
      \stage_1_data_r_reg[0]\(6) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_47,
      \stage_1_data_r_reg[0]\(5) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_48,
      \stage_1_data_r_reg[0]\(4) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_49,
      \stage_1_data_r_reg[0]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_50,
      \stage_1_data_r_reg[0]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_51,
      \stage_1_data_r_reg[0]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_52,
      \stage_1_data_r_reg[0]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_53,
      \stage_1_data_r_reg[11]\(4) => \aurora_1ln_rx_lpm_sym_dec_4byte_i/p_0_in\(0),
      \stage_1_data_r_reg[11]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_42,
      \stage_1_data_r_reg[11]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_43,
      \stage_1_data_r_reg[11]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_44,
      \stage_1_data_r_reg[11]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_45,
      \stage_1_data_r_reg[16]\(7) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_33,
      \stage_1_data_r_reg[16]\(6) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_34,
      \stage_1_data_r_reg[16]\(5) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_35,
      \stage_1_data_r_reg[16]\(4) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_36,
      \stage_1_data_r_reg[16]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_37,
      \stage_1_data_r_reg[16]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_38,
      \stage_1_data_r_reg[16]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_39,
      \stage_1_data_r_reg[16]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_40,
      \stage_1_data_r_reg[27]\(4) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_28,
      \stage_1_data_r_reg[27]\(3) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_29,
      \stage_1_data_r_reg[27]\(2) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_30,
      \stage_1_data_r_reg[27]\(1) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_31,
      \stage_1_data_r_reg[27]\(0) => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_32,
      user_clk => user_clk
    );
core_reset_logic_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RESET_LOGIC
     port map (
      LINK_RESET_OUT => \^link_reset_out\,
      TX_LOCK => \^tx_lock\,
      gt_rxresetdone_r2_reg_0 => gt_wrapper_i_n_117,
      init_clk_in => init_clk_in,
      link_reset_r => link_reset_r,
      \out\ => reset_sync_user_clk,
      sys_reset_out => \^sys_reset_out\,
      user_clk => user_clk
    );
gt_reset_cdc_sync: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync
     port map (
      GT_RESET => GT_RESET,
      HPCNT_RESET => HPCNT_RESET,
      \hotplug_count_synth.count_for_reset_r_reg[0]\ => reset_sync_init_clk,
      init_clk_in => init_clk_in,
      \out\ => gt_reset_sync_init_clk
    );
gt_wrapper_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_GT_WRAPPER
     port map (
      D(7) => gt_wrapper_i_n_104,
      D(6) => gt_wrapper_i_n_105,
      D(5) => gt_wrapper_i_n_106,
      D(4) => gt_wrapper_i_n_107,
      D(3) => gt_wrapper_i_n_108,
      D(2) => gt_wrapper_i_n_109,
      D(1) => gt_wrapper_i_n_110,
      D(0) => gt_wrapper_i_n_111,
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPWE_IN => DRPWE_IN,
      E(0) => \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r\,
      ENABLE_ERR_DETECT_Buffer_reg(3) => \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out\(3),
      ENABLE_ERR_DETECT_Buffer_reg(2) => gt_wrapper_i_n_114,
      ENABLE_ERR_DETECT_Buffer_reg(1) => \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out\(1),
      ENABLE_ERR_DETECT_Buffer_reg(0) => gt_wrapper_i_n_116,
      GTRXRESET_OUT => GTRXRESET_OUT,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      Q(3) => previous_cycle_data_r(7),
      Q(2) => previous_cycle_data_r(5),
      Q(1) => previous_cycle_data_r(3),
      Q(0) => previous_cycle_data_r(1),
      RXCHARISK(3 downto 0) => rx_char_is_k_i(3 downto 0),
      RXDATA(31 downto 0) => rx_data_i(31 downto 0),
      RXN => RXN,
      RXP => RXP,
      RX_RESETDONE_OUT => RX_RESETDONE_OUT,
      TX_LOCK => \^tx_lock\,
      TX_OUT_CLK => TX_OUT_CLK,
      begin_r => \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/begin_r\,
      drpclk_in => drpclk_in,
      ena_comma_align_i => ena_comma_align_i,
      enable_err_detect_i => enable_err_detect_i,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_rx_disp_err_out(3 downto 0) => gt0_rx_disp_err_out(3 downto 0),
      gt0_rx_not_in_table_out(3 downto 0) => gt0_rx_not_in_table_out(3 downto 0),
      gt0_rx_realign_out => \^gt0_rx_realign_out\,
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2) => \^gt0_rx_buf_err_out\,
      gt0_rxbufstatus_out(1 downto 0) => \^gt0_rxbufstatus_out\(1 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt_qpllclk_quad1_in => gt_qpllclk_quad1_in,
      gt_qpllrefclk_quad1_in => gt_qpllrefclk_quad1_in,
      gt_refclk1 => gt_refclk1,
      hard_err_gt0 => \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/hard_err_gt0\,
      inc_count_r0 => \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r0\,
      inc_count_r_reg => gt_wrapper_i_n_98,
      init_clk_in => init_clk_in,
      init_clk_in_0 => gt_wrapper_i_n_99,
      \left_align_select_r_reg[1]\ => gt_wrapper_i_n_112,
      link_reset_r => link_reset_r,
      \out\ => gt_reset_sync_init_clk,
      \previous_cycle_data_r_reg[7]\(3) => gt_wrapper_i_n_100,
      \previous_cycle_data_r_reg[7]\(2) => gt_wrapper_i_n_101,
      \previous_cycle_data_r_reg[7]\(1) => gt_wrapper_i_n_102,
      \previous_cycle_data_r_reg[7]\(0) => gt_wrapper_i_n_103,
      rx_polarity_i => rx_polarity_i,
      rxfsm_rxresetdone_r3_reg_0 => gt_wrapper_i_n_117,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_data_r_reg[22]\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_19,
      \word_aligned_data_r_reg[22]_0\ => aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_20
    );
hpcnt_reset_cdc_sync: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_0
     port map (
      RX_SYSTEM_RESET => RX_SYSTEM_RESET,
      init_clk_in => init_clk_in,
      \out\ => reset_sync_init_clk
    );
ll_to_axi_pdu_i: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LL_TO_AXI
     port map (
      M_AXI_RX_TKEEP(2 downto 0) => \^m_axi_rx_tkeep\(3 downto 1),
      Q(1) => aurora_1ln_rx_lpm_rx_ll_i_n_5,
      Q(0) => aurora_1ln_rx_lpm_rx_ll_i_n_6,
      rx_eof => rx_eof
    );
reset_sync_user_clk_cdc_sync: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_1
     port map (
      RX_SYSTEM_RESET => RX_SYSTEM_RESET,
      \out\ => reset_sync_user_clk,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_1ln_rx_lpm is
  port (
    m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_rx_tvalid : out STD_LOGIC;
    m_axi_rx_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rx_tlast : out STD_LOGIC;
    m_axi_ufc_rx_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    m_axi_ufc_rx_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_ufc_rx_tvalid : out STD_LOGIC;
    m_axi_ufc_rx_tlast : out STD_LOGIC;
    rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_refclk1 : in STD_LOGIC;
    frame_err : out STD_LOGIC;
    rx_hard_err : out STD_LOGIC;
    soft_err : out STD_LOGIC;
    rx_lane_up : out STD_LOGIC_VECTOR ( 0 to 0 );
    rx_channel_up : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    rx_system_reset : in STD_LOGIC;
    power_down : in STD_LOGIC;
    loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_reset : in STD_LOGIC;
    tx_lock : out STD_LOGIC;
    sys_reset_out : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    rx_resetdone_out : out STD_LOGIC;
    link_reset_out : out STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in : in STD_LOGIC;
    drprdy_out : out STD_LOGIC;
    drpwe_in : in STD_LOGIC;
    gt0_cplllock_out : out STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
    gt0_rx_realign_out : out STD_LOGIC;
    gt0_rx_buf_err_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_qplllock_in : in STD_LOGIC;
    gt0_qpllrefclklost_in : in STD_LOGIC;
    gt0_qpllreset_out : out STD_LOGIC;
    gt_qpllclk_quad1_in : in STD_LOGIC;
    gt_qpllrefclk_quad1_in : in STD_LOGIC;
    tx_out_clk : out STD_LOGIC;
    pll_not_locked : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of aurora_1ln_rx_lpm : entity is true;
end aurora_1ln_rx_lpm;

architecture STRUCTURE of aurora_1ln_rx_lpm is
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of U0 : label is 0;
  attribute SIM_GTRESET_SPEEDUP : string;
  attribute SIM_GTRESET_SPEEDUP of U0 : label is "FALSE";
begin
U0: entity work.aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core
     port map (
      DRPADDR_IN(8 downto 0) => drpaddr_in(8 downto 0),
      DRPDI_IN(15 downto 0) => drpdi_in(15 downto 0),
      DRPDO_OUT(15 downto 0) => drpdo_out(15 downto 0),
      DRPEN_IN => drpen_in,
      DRPRDY_OUT => drprdy_out,
      DRPWE_IN => drpwe_in,
      FRAME_ERR => frame_err,
      GT_RESET => gt_reset,
      LINK_RESET_OUT => link_reset_out,
      LOOPBACK(2 downto 0) => loopback(2 downto 0),
      M_AXI_RX_TDATA(31 downto 0) => m_axi_rx_tdata(31 downto 0),
      M_AXI_RX_TKEEP(3 downto 0) => m_axi_rx_tkeep(3 downto 0),
      M_AXI_RX_TLAST => m_axi_rx_tlast,
      M_AXI_RX_TVALID => m_axi_rx_tvalid,
      M_AXI_UFC_RX_TDATA(31 downto 0) => m_axi_ufc_rx_tdata(31 downto 0),
      M_AXI_UFC_RX_TKEEP(3 downto 0) => m_axi_ufc_rx_tkeep(3 downto 0),
      M_AXI_UFC_RX_TLAST => m_axi_ufc_rx_tlast,
      M_AXI_UFC_RX_TVALID => m_axi_ufc_rx_tvalid,
      PLL_NOT_LOCKED => pll_not_locked,
      POWER_DOWN => power_down,
      RXN => rxn(0),
      RXP => rxp(0),
      RX_CHANNEL_UP => rx_channel_up,
      RX_HARD_ERR => rx_hard_err,
      RX_LANE_UP => rx_lane_up(0),
      RX_RESETDONE_OUT => rx_resetdone_out,
      RX_SYSTEM_RESET => rx_system_reset,
      SOFT_ERR => soft_err,
      TX_LOCK => tx_lock,
      TX_OUT_CLK => tx_out_clk,
      drpclk_in => drpclk_in,
      gt0_cplllock_out => gt0_cplllock_out,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_qplllock_in => gt0_qplllock_in,
      gt0_qpllrefclklost_in => gt0_qpllrefclklost_in,
      gt0_qpllreset_out => gt0_qpllreset_out,
      gt0_rx_buf_err_out => gt0_rx_buf_err_out,
      gt0_rx_disp_err_out(3 downto 0) => gt0_rx_disp_err_out(3 downto 0),
      gt0_rx_not_in_table_out(3 downto 0) => gt0_rx_not_in_table_out(3 downto 0),
      gt0_rx_realign_out => gt0_rx_realign_out,
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2 downto 0) => gt0_rxbufstatus_out(2 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt_qpllclk_quad1_in => gt_qpllclk_quad1_in,
      gt_qpllrefclk_quad1_in => gt_qpllrefclk_quad1_in,
      gt_refclk1 => gt_refclk1,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      sys_reset_out => sys_reset_out,
      user_clk => user_clk
    );
end STRUCTURE;
