// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Mon Mar 21 18:28:36 2022
// Host        : hog-efex3.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode funcsim
//               /home/gitlab-runner/builds/xeGdLrzp/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_jfex/aurora_1ln_rx_lpm/aurora_1ln_rx_lpm_sim_netlist.v
// Design      : aurora_1ln_rx_lpm
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* NotValidForBitStream *)
module aurora_1ln_rx_lpm
   (m_axi_rx_tdata,
    m_axi_rx_tvalid,
    m_axi_rx_tkeep,
    m_axi_rx_tlast,
    m_axi_ufc_rx_tdata,
    m_axi_ufc_rx_tkeep,
    m_axi_ufc_rx_tvalid,
    m_axi_ufc_rx_tlast,
    rxp,
    rxn,
    gt_refclk1,
    frame_err,
    rx_hard_err,
    soft_err,
    rx_lane_up,
    rx_channel_up,
    user_clk,
    sync_clk,
    rx_system_reset,
    power_down,
    loopback,
    gt_reset,
    tx_lock,
    sys_reset_out,
    init_clk_in,
    rx_resetdone_out,
    link_reset_out,
    drpclk_in,
    drpaddr_in,
    drpdi_in,
    drpdo_out,
    drpen_in,
    drprdy_out,
    drpwe_in,
    gt0_cplllock_out,
    gt0_rxlpmen_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxmonitorout_out,
    gt0_rxmonitorsel_in,
    gt0_rxcdrhold_in,
    gt0_eyescanreset_in,
    gt0_eyescandataerror_out,
    gt0_eyescantrigger_in,
    gt0_rxbyteisaligned_out,
    gt0_rxcommadet_out,
    gt0_rxprbserr_out,
    gt0_rxprbssel_in,
    gt0_rxprbscntreset_in,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    gt0_rxpmaresetdone_out,
    gt0_dmonitorout_out,
    gt0_rxbufreset_in,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    gt0_rx_realign_out,
    gt0_rx_buf_err_out,
    gt0_rxresetdone_out,
    gt0_rxbufstatus_out,
    gt0_qplllock_in,
    gt0_qpllrefclklost_in,
    gt0_qpllreset_out,
    gt_qpllclk_quad1_in,
    gt_qpllrefclk_quad1_in,
    tx_out_clk,
    pll_not_locked);
  output [31:0]m_axi_rx_tdata;
  output m_axi_rx_tvalid;
  output [3:0]m_axi_rx_tkeep;
  output m_axi_rx_tlast;
  output [31:0]m_axi_ufc_rx_tdata;
  output [3:0]m_axi_ufc_rx_tkeep;
  output m_axi_ufc_rx_tvalid;
  output m_axi_ufc_rx_tlast;
  input [0:0]rxp;
  input [0:0]rxn;
  input gt_refclk1;
  output frame_err;
  output rx_hard_err;
  output soft_err;
  output [0:0]rx_lane_up;
  output rx_channel_up;
  input user_clk;
  input sync_clk;
  input rx_system_reset;
  input power_down;
  input [2:0]loopback;
  input gt_reset;
  output tx_lock;
  output sys_reset_out;
  input init_clk_in;
  output rx_resetdone_out;
  output link_reset_out;
  input drpclk_in;
  input [8:0]drpaddr_in;
  input [15:0]drpdi_in;
  output [15:0]drpdo_out;
  input drpen_in;
  output drprdy_out;
  input drpwe_in;
  output gt0_cplllock_out;
  input gt0_rxlpmen_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  output [6:0]gt0_rxmonitorout_out;
  input [1:0]gt0_rxmonitorsel_in;
  input gt0_rxcdrhold_in;
  input gt0_eyescanreset_in;
  output gt0_eyescandataerror_out;
  input gt0_eyescantrigger_in;
  output gt0_rxbyteisaligned_out;
  output gt0_rxcommadet_out;
  output gt0_rxprbserr_out;
  input [2:0]gt0_rxprbssel_in;
  input gt0_rxprbscntreset_in;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  output gt0_rxpmaresetdone_out;
  output [14:0]gt0_dmonitorout_out;
  input gt0_rxbufreset_in;
  output [3:0]gt0_rx_disp_err_out;
  output [3:0]gt0_rx_not_in_table_out;
  output gt0_rx_realign_out;
  output gt0_rx_buf_err_out;
  output gt0_rxresetdone_out;
  output [2:0]gt0_rxbufstatus_out;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt_qpllclk_quad1_in;
  input gt_qpllrefclk_quad1_in;
  output tx_out_clk;
  input pll_not_locked;

  wire [8:0]drpaddr_in;
  wire drpclk_in;
  wire [15:0]drpdi_in;
  wire [15:0]drpdo_out;
  wire drpen_in;
  wire drprdy_out;
  wire drpwe_in;
  wire frame_err;
  wire gt0_cplllock_out;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire gt0_qplllock_in;
  wire gt0_qpllrefclklost_in;
  wire gt0_qpllreset_out;
  wire gt0_rx_buf_err_out;
  wire [3:0]gt0_rx_disp_err_out;
  wire [3:0]gt0_rx_not_in_table_out;
  wire gt0_rx_realign_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt_qpllclk_quad1_in;
  wire gt_qpllrefclk_quad1_in;
  wire gt_refclk1;
  wire gt_reset;
  wire init_clk_in;
  wire link_reset_out;
  wire [2:0]loopback;
  wire [31:0]m_axi_rx_tdata;
  wire [3:0]m_axi_rx_tkeep;
  wire m_axi_rx_tlast;
  wire m_axi_rx_tvalid;
  wire [31:0]m_axi_ufc_rx_tdata;
  wire [3:0]m_axi_ufc_rx_tkeep;
  wire m_axi_ufc_rx_tlast;
  wire m_axi_ufc_rx_tvalid;
  wire pll_not_locked;
  wire power_down;
  wire rx_channel_up;
  wire rx_hard_err;
  wire [0:0]rx_lane_up;
  wire rx_resetdone_out;
  wire rx_system_reset;
  wire [0:0]rxn;
  wire [0:0]rxp;
  wire soft_err;
  wire sync_clk;
  wire sys_reset_out;
  wire tx_lock;
  wire tx_out_clk;
  wire user_clk;

  (* EXAMPLE_SIMULATION = "0" *) 
  (* SIM_GTRESET_SPEEDUP = "FALSE" *) 
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core U0
       (.DRPADDR_IN(drpaddr_in),
        .DRPDI_IN(drpdi_in),
        .DRPDO_OUT(drpdo_out),
        .DRPEN_IN(drpen_in),
        .DRPRDY_OUT(drprdy_out),
        .DRPWE_IN(drpwe_in),
        .FRAME_ERR(frame_err),
        .GT_RESET(gt_reset),
        .LINK_RESET_OUT(link_reset_out),
        .LOOPBACK(loopback),
        .M_AXI_RX_TDATA(m_axi_rx_tdata),
        .M_AXI_RX_TKEEP(m_axi_rx_tkeep),
        .M_AXI_RX_TLAST(m_axi_rx_tlast),
        .M_AXI_RX_TVALID(m_axi_rx_tvalid),
        .M_AXI_UFC_RX_TDATA(m_axi_ufc_rx_tdata),
        .M_AXI_UFC_RX_TKEEP(m_axi_ufc_rx_tkeep),
        .M_AXI_UFC_RX_TLAST(m_axi_ufc_rx_tlast),
        .M_AXI_UFC_RX_TVALID(m_axi_ufc_rx_tvalid),
        .PLL_NOT_LOCKED(pll_not_locked),
        .POWER_DOWN(power_down),
        .RXN(rxn),
        .RXP(rxp),
        .RX_CHANNEL_UP(rx_channel_up),
        .RX_HARD_ERR(rx_hard_err),
        .RX_LANE_UP(rx_lane_up),
        .RX_RESETDONE_OUT(rx_resetdone_out),
        .RX_SYSTEM_RESET(rx_system_reset),
        .SOFT_ERR(soft_err),
        .TX_LOCK(tx_lock),
        .TX_OUT_CLK(tx_out_clk),
        .drpclk_in(drpclk_in),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_qplllock_in(gt0_qplllock_in),
        .gt0_qpllrefclklost_in(gt0_qpllrefclklost_in),
        .gt0_qpllreset_out(gt0_qpllreset_out),
        .gt0_rx_buf_err_out(gt0_rx_buf_err_out),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rx_realign_out(gt0_rx_realign_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out(gt0_rxbufstatus_out),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt_qpllclk_quad1_in(gt_qpllclk_quad1_in),
        .gt_qpllrefclk_quad1_in(gt_qpllrefclk_quad1_in),
        .gt_refclk1(gt_refclk1),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .sys_reset_out(sys_reset_out),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_GT_WRAPPER" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_GT_WRAPPER
   (TX_LOCK,
    DRPRDY_OUT,
    gt0_eyescandataerror_out,
    gt0_rxbyteisaligned_out,
    gt0_rx_realign_out,
    gt0_rxcommadet_out,
    gt0_rxpmaresetdone_out,
    gt0_rxprbserr_out,
    gt0_rxresetdone_out,
    TX_OUT_CLK,
    gt0_dmonitorout_out,
    DRPDO_OUT,
    gt0_rxbufstatus_out,
    RXDATA,
    gt0_rxmonitorout_out,
    RXCHARISK,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    RX_RESETDONE_OUT,
    hard_err_gt0,
    inc_count_r0,
    inc_count_r_reg,
    init_clk_in_0,
    \previous_cycle_data_r_reg[7] ,
    D,
    \left_align_select_r_reg[1] ,
    ENABLE_ERR_DETECT_Buffer_reg,
    rxfsm_rxresetdone_r3_reg_0,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt0_eyescanreset_in,
    gt0_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    gt_qpllclk_quad1_in,
    gt_qpllrefclk_quad1_in,
    gt0_rxbufreset_in,
    gt0_rxcdrhold_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxlpmen_in,
    ena_comma_align_i,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    rx_polarity_i,
    gt0_rxprbscntreset_in,
    sync_clk,
    user_clk,
    DRPDI_IN,
    gt0_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt0_rxprbssel_in,
    DRPADDR_IN,
    GTRXRESET_OUT,
    link_reset_r,
    E,
    begin_r,
    Q,
    \word_aligned_data_r_reg[22] ,
    \word_aligned_data_r_reg[22]_0 ,
    enable_err_detect_i,
    out);
  output TX_LOCK;
  output DRPRDY_OUT;
  output gt0_eyescandataerror_out;
  output gt0_rxbyteisaligned_out;
  output gt0_rx_realign_out;
  output gt0_rxcommadet_out;
  output gt0_rxpmaresetdone_out;
  output gt0_rxprbserr_out;
  output gt0_rxresetdone_out;
  output TX_OUT_CLK;
  output [14:0]gt0_dmonitorout_out;
  output [15:0]DRPDO_OUT;
  output [2:0]gt0_rxbufstatus_out;
  output [31:0]RXDATA;
  output [6:0]gt0_rxmonitorout_out;
  output [3:0]RXCHARISK;
  output [3:0]gt0_rx_disp_err_out;
  output [3:0]gt0_rx_not_in_table_out;
  output RX_RESETDONE_OUT;
  output hard_err_gt0;
  output inc_count_r0;
  output inc_count_r_reg;
  output init_clk_in_0;
  output [3:0]\previous_cycle_data_r_reg[7] ;
  output [7:0]D;
  output \left_align_select_r_reg[1] ;
  output [3:0]ENABLE_ERR_DETECT_Buffer_reg;
  output rxfsm_rxresetdone_r3_reg_0;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt0_eyescanreset_in;
  input gt0_eyescantrigger_in;
  input RXN;
  input RXP;
  input gt_refclk1;
  input gt_qpllclk_quad1_in;
  input gt_qpllrefclk_quad1_in;
  input gt0_rxbufreset_in;
  input gt0_rxcdrhold_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  input gt0_rxlpmen_in;
  input ena_comma_align_i;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  input rx_polarity_i;
  input gt0_rxprbscntreset_in;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN;
  input [1:0]gt0_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_rxprbssel_in;
  input [8:0]DRPADDR_IN;
  input GTRXRESET_OUT;
  input link_reset_r;
  input [0:0]E;
  input begin_r;
  input [3:0]Q;
  input \word_aligned_data_r_reg[22] ;
  input \word_aligned_data_r_reg[22]_0 ;
  input enable_err_detect_i;
  input out;

  wire [7:0]D;
  wire [8:0]DRPADDR_IN;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDO_OUT;
  wire DRPEN_IN;
  wire DRPRDY_OUT;
  wire DRPWE_IN;
  wire [0:0]E;
  wire [3:0]ENABLE_ERR_DETECT_Buffer_reg;
  wire GTRXRESET_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [3:0]Q;
  wire [3:0]RXCHARISK;
  wire [31:0]RXDATA;
  wire RXN;
  wire RXP;
  wire RX_RESETDONE_OUT;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire begin_r;
  wire cpll_reset_i;
  wire drpclk_in;
  wire ena_comma_align_i;
  wire enable_err_detect_i;
  wire fsm_gt_rx_reset_t;
  wire \gt0_aurora_1ln_rx_lpm_i/ack_flag ;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire [3:0]gt0_rx_disp_err_out;
  wire [3:0]gt0_rx_not_in_table_out;
  wire gt0_rx_realign_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt0_rxresetdone_r3_reg_srl3_n_0;
  wire gt_qpllclk_quad1_in;
  wire gt_qpllrefclk_quad1_in;
  wire gt_refclk1;
  wire gt_rx_reset_i;
  wire gt_rxresetfsm_i_n_3;
  wire gt_rxuserrdy_i;
  wire gtrxreset_pulse;
  wire gtrxreset_pulse_i_1_n_0;
  wire gtrxreset_r1;
  wire gtrxreset_r2;
  wire gtrxreset_r3;
  wire gtrxreset_sync;
  wire hard_err_gt0;
  wire inc_count_r0;
  wire inc_count_r_reg;
  wire init_clk_in;
  wire init_clk_in_0;
  wire \left_align_select_r_reg[1] ;
  wire link_reset_r;
  wire link_reset_r2;
  wire out;
  wire [10:0]p_0_in__0;
  wire [3:0]\previous_cycle_data_r_reg[7] ;
  wire rx_cdrlock_counter;
  wire \rx_cdrlock_counter[10]_i_3_n_0 ;
  wire \rx_cdrlock_counter[10]_i_4_n_0 ;
  wire \rx_cdrlock_counter[10]_i_5_n_0 ;
  wire [10:0]rx_cdrlock_counter_reg;
  wire rx_cdrlocked_i_1_n_0;
  wire rx_cdrlocked_i_2_n_0;
  wire rx_cdrlocked_i_3_n_0;
  wire rx_cdrlocked_reg_n_0;
  wire rx_polarity_i;
  wire rxfsm_rxresetdone_r;
  wire rxfsm_rxresetdone_r2;
  wire rxfsm_rxresetdone_r3_reg_0;
  wire rxfsm_soft_reset_r;
  wire rxfsm_soft_reset_r_i_1_n_0;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_data_r_reg[22] ;
  wire \word_aligned_data_r_reg[22]_0 ;

  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_multi_gt aurora_1ln_rx_lpm_multi_gt_i
       (.D(D),
        .DRPADDR_IN(DRPADDR_IN),
        .DRPDI_IN(DRPDI_IN),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPEN_IN(DRPEN_IN),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPWE_IN(DRPWE_IN),
        .E(E),
        .ENABLE_ERR_DETECT_Buffer_reg(ENABLE_ERR_DETECT_Buffer_reg),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .Q(Q),
        .RXCHARISK(RXCHARISK),
        .RXDATA(RXDATA),
        .RXN(RXN),
        .RXP(RXP),
        .SR(gt_rx_reset_i),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .ack_flag(\gt0_aurora_1ln_rx_lpm_i/ack_flag ),
        .begin_r(begin_r),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .ena_comma_align_i(ena_comma_align_i),
        .enable_err_detect_i(enable_err_detect_i),
        .flag2_reg(gt_rxresetfsm_i_n_3),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rx_realign_out(gt0_rx_realign_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out(gt0_rxbufstatus_out),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt_qpllclk_quad1_in(gt_qpllclk_quad1_in),
        .gt_qpllrefclk_quad1_in(gt_qpllrefclk_quad1_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .hard_err_gt0(hard_err_gt0),
        .inc_count_r0(inc_count_r0),
        .inc_count_r_reg(inc_count_r_reg),
        .init_clk_in(init_clk_in),
        .init_clk_in_0(init_clk_in_0),
        .\left_align_select_r_reg[1] (\left_align_select_r_reg[1] ),
        .\previous_cycle_data_r_reg[7] (\previous_cycle_data_r_reg[7] ),
        .rx_polarity_i(rx_polarity_i),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_data_r_reg[22] (\word_aligned_data_r_reg[22] ),
        .\word_aligned_data_r_reg[22]_0 (\word_aligned_data_r_reg[22]_0 ));
  (* srl_name = "U0/\gt_wrapper_i/gt0_rxresetdone_r3_reg_srl3 " *) 
  SRL16E gt0_rxresetdone_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt0_rxresetdone_out),
        .Q(gt0_rxresetdone_r3_reg_srl3_n_0));
  (* equivalent_register_removal = "no" *) 
  FDRE gt_rx_reset_i_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(fsm_gt_rx_reset_t),
        .Q(gt_rx_reset_i),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    gt_rxresetdone_r_i_1
       (.I0(RX_RESETDONE_OUT),
        .O(rxfsm_rxresetdone_r3_reg_0));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_rx_startup_fsm gt_rxresetfsm_i
       (.AR(rxfsm_soft_reset_r),
        .CPLL_RESET_reg_0(gt_rxresetfsm_i_n_3),
        .TX_LOCK(TX_LOCK),
        .ack_flag(\gt0_aurora_1ln_rx_lpm_i/ack_flag ),
        .cpll_reset_i(cpll_reset_i),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .init_clk_in(init_clk_in),
        .reset_time_out_reg_0(rx_cdrlocked_reg_n_0),
        .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2 gtrxreset_cdc_sync
       (.GTRXRESET_OUT(GTRXRESET_OUT),
        .init_clk_in(init_clk_in),
        .out(gtrxreset_sync),
        .user_clk(user_clk));
  LUT2 #(
    .INIT(4'h2)) 
    gtrxreset_pulse_i_1
       (.I0(gtrxreset_r2),
        .I1(gtrxreset_r3),
        .O(gtrxreset_pulse_i_1_n_0));
  FDRE gtrxreset_pulse_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_pulse_i_1_n_0),
        .Q(gtrxreset_pulse),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE gtrxreset_r1_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_sync),
        .Q(gtrxreset_r1),
        .R(1'b0));
  FDRE gtrxreset_r2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_r1),
        .Q(gtrxreset_r2),
        .R(1'b0));
  FDRE gtrxreset_r3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_r2),
        .Q(gtrxreset_r3),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE link_reset_r2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(link_reset_r2),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rx_cdrlock_counter[0]_i_1 
       (.I0(rx_cdrlock_counter_reg[0]),
        .O(p_0_in__0[0]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \rx_cdrlock_counter[10]_i_1 
       (.I0(\rx_cdrlock_counter[10]_i_3_n_0 ),
        .I1(rx_cdrlock_counter_reg[2]),
        .I2(rx_cdrlock_counter_reg[3]),
        .I3(rx_cdrlock_counter_reg[5]),
        .I4(rx_cdrlock_counter_reg[4]),
        .I5(\rx_cdrlock_counter[10]_i_4_n_0 ),
        .O(rx_cdrlock_counter));
  LUT6 #(
    .INIT(64'hCC6CCCCCCCCCCCCC)) 
    \rx_cdrlock_counter[10]_i_2 
       (.I0(rx_cdrlock_counter_reg[9]),
        .I1(rx_cdrlock_counter_reg[10]),
        .I2(rx_cdrlock_counter_reg[7]),
        .I3(\rx_cdrlock_counter[10]_i_5_n_0 ),
        .I4(rx_cdrlock_counter_reg[6]),
        .I5(rx_cdrlock_counter_reg[8]),
        .O(p_0_in__0[10]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rx_cdrlock_counter[10]_i_3 
       (.I0(rx_cdrlock_counter_reg[1]),
        .I1(rx_cdrlock_counter_reg[0]),
        .O(\rx_cdrlock_counter[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \rx_cdrlock_counter[10]_i_4 
       (.I0(rx_cdrlock_counter_reg[7]),
        .I1(rx_cdrlock_counter_reg[6]),
        .I2(rx_cdrlock_counter_reg[9]),
        .I3(rx_cdrlock_counter_reg[10]),
        .I4(rx_cdrlock_counter_reg[8]),
        .O(\rx_cdrlock_counter[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \rx_cdrlock_counter[10]_i_5 
       (.I0(rx_cdrlock_counter_reg[4]),
        .I1(rx_cdrlock_counter_reg[2]),
        .I2(rx_cdrlock_counter_reg[0]),
        .I3(rx_cdrlock_counter_reg[1]),
        .I4(rx_cdrlock_counter_reg[3]),
        .I5(rx_cdrlock_counter_reg[5]),
        .O(\rx_cdrlock_counter[10]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rx_cdrlock_counter[1]_i_1 
       (.I0(rx_cdrlock_counter_reg[0]),
        .I1(rx_cdrlock_counter_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rx_cdrlock_counter[2]_i_1 
       (.I0(rx_cdrlock_counter_reg[1]),
        .I1(rx_cdrlock_counter_reg[0]),
        .I2(rx_cdrlock_counter_reg[2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \rx_cdrlock_counter[3]_i_1 
       (.I0(rx_cdrlock_counter_reg[2]),
        .I1(rx_cdrlock_counter_reg[0]),
        .I2(rx_cdrlock_counter_reg[1]),
        .I3(rx_cdrlock_counter_reg[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \rx_cdrlock_counter[4]_i_1 
       (.I0(rx_cdrlock_counter_reg[3]),
        .I1(rx_cdrlock_counter_reg[1]),
        .I2(rx_cdrlock_counter_reg[0]),
        .I3(rx_cdrlock_counter_reg[2]),
        .I4(rx_cdrlock_counter_reg[4]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \rx_cdrlock_counter[5]_i_1 
       (.I0(rx_cdrlock_counter_reg[4]),
        .I1(rx_cdrlock_counter_reg[2]),
        .I2(rx_cdrlock_counter_reg[0]),
        .I3(rx_cdrlock_counter_reg[1]),
        .I4(rx_cdrlock_counter_reg[3]),
        .I5(rx_cdrlock_counter_reg[5]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rx_cdrlock_counter[6]_i_1 
       (.I0(\rx_cdrlock_counter[10]_i_5_n_0 ),
        .I1(rx_cdrlock_counter_reg[6]),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rx_cdrlock_counter[7]_i_1 
       (.I0(rx_cdrlock_counter_reg[6]),
        .I1(\rx_cdrlock_counter[10]_i_5_n_0 ),
        .I2(rx_cdrlock_counter_reg[7]),
        .O(p_0_in__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \rx_cdrlock_counter[8]_i_1 
       (.I0(rx_cdrlock_counter_reg[7]),
        .I1(\rx_cdrlock_counter[10]_i_5_n_0 ),
        .I2(rx_cdrlock_counter_reg[6]),
        .I3(rx_cdrlock_counter_reg[8]),
        .O(p_0_in__0[8]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \rx_cdrlock_counter[9]_i_1 
       (.I0(rx_cdrlock_counter_reg[8]),
        .I1(rx_cdrlock_counter_reg[6]),
        .I2(\rx_cdrlock_counter[10]_i_5_n_0 ),
        .I3(rx_cdrlock_counter_reg[7]),
        .I4(rx_cdrlock_counter_reg[9]),
        .O(p_0_in__0[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[0] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[0]),
        .Q(rx_cdrlock_counter_reg[0]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[10] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[10]),
        .Q(rx_cdrlock_counter_reg[10]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[1] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[1]),
        .Q(rx_cdrlock_counter_reg[1]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[2] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[2]),
        .Q(rx_cdrlock_counter_reg[2]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[3] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[3]),
        .Q(rx_cdrlock_counter_reg[3]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[4] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[4]),
        .Q(rx_cdrlock_counter_reg[4]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[5] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[5]),
        .Q(rx_cdrlock_counter_reg[5]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[6] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[6]),
        .Q(rx_cdrlock_counter_reg[6]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[7] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[7]),
        .Q(rx_cdrlock_counter_reg[7]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[8] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[8]),
        .Q(rx_cdrlock_counter_reg[8]),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[9] 
       (.C(init_clk_in),
        .CE(rx_cdrlock_counter),
        .D(p_0_in__0[9]),
        .Q(rx_cdrlock_counter_reg[9]),
        .R(gt_rx_reset_i));
  LUT6 #(
    .INIT(64'h00000000AAABAAAA)) 
    rx_cdrlocked_i_1
       (.I0(rx_cdrlocked_reg_n_0),
        .I1(\rx_cdrlock_counter[10]_i_3_n_0 ),
        .I2(rx_cdrlocked_i_2_n_0),
        .I3(rx_cdrlock_counter_reg[2]),
        .I4(rx_cdrlocked_i_3_n_0),
        .I5(gt_rx_reset_i),
        .O(rx_cdrlocked_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'hB)) 
    rx_cdrlocked_i_2
       (.I0(rx_cdrlock_counter_reg[9]),
        .I1(rx_cdrlock_counter_reg[10]),
        .O(rx_cdrlocked_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    rx_cdrlocked_i_3
       (.I0(rx_cdrlock_counter_reg[5]),
        .I1(rx_cdrlock_counter_reg[6]),
        .I2(rx_cdrlock_counter_reg[4]),
        .I3(rx_cdrlock_counter_reg[3]),
        .I4(rx_cdrlock_counter_reg[8]),
        .I5(rx_cdrlock_counter_reg[7]),
        .O(rx_cdrlocked_i_3_n_0));
  FDRE rx_cdrlocked_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlocked_i_1_n_0),
        .Q(rx_cdrlocked_reg_n_0),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE rxfsm_rxresetdone_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rxfsm_rxresetdone_r),
        .Q(rxfsm_rxresetdone_r2),
        .R(1'b0));
  FDRE rxfsm_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rxfsm_rxresetdone_r2),
        .Q(RX_RESETDONE_OUT),
        .R(1'b0));
  FDRE rxfsm_rxresetdone_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt0_rxresetdone_r3_reg_srl3_n_0),
        .Q(rxfsm_rxresetdone_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    rxfsm_soft_reset_r_i_1
       (.I0(out),
        .I1(gtrxreset_pulse),
        .I2(link_reset_r2),
        .O(rxfsm_soft_reset_r_i_1_n_0));
  FDRE rxfsm_soft_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rxfsm_soft_reset_r_i_1_n_0),
        .Q(rxfsm_soft_reset_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_HOTPLUG" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_HOTPLUG
   (LINK_RESET_OUT,
    init_clk_in,
    user_clk,
    HPCNT_RESET,
    SR,
    D);
  output LINK_RESET_OUT;
  input init_clk_in;
  input user_clk;
  input HPCNT_RESET;
  input [0:0]SR;
  input [0:0]D;

  wire [0:0]D;
  wire HPCNT_RESET;
  wire LINK_RESET_OUT;
  wire [0:0]SR;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire init_clk_in;
  wire link_reset_0;
  wire link_reset_r_i_2_n_0;
  wire link_reset_r_i_3_n_0;
  wire link_reset_r_i_4_n_0;
  wire link_reset_r_i_5_n_0;
  wire link_reset_r_i_6_n_0;
  wire link_reset_r_reg_n_0;
  wire rx_cc_cdc_sync_n_0;
  wire rx_cc_cdc_sync_n_1;
  wire rx_cc_cdc_sync_n_10;
  wire rx_cc_cdc_sync_n_11;
  wire rx_cc_cdc_sync_n_12;
  wire rx_cc_cdc_sync_n_13;
  wire rx_cc_cdc_sync_n_14;
  wire rx_cc_cdc_sync_n_15;
  wire rx_cc_cdc_sync_n_16;
  wire rx_cc_cdc_sync_n_17;
  wire rx_cc_cdc_sync_n_18;
  wire rx_cc_cdc_sync_n_19;
  wire rx_cc_cdc_sync_n_2;
  wire rx_cc_cdc_sync_n_20;
  wire rx_cc_cdc_sync_n_21;
  wire rx_cc_cdc_sync_n_22;
  wire rx_cc_cdc_sync_n_23;
  wire rx_cc_cdc_sync_n_24;
  wire rx_cc_cdc_sync_n_25;
  wire rx_cc_cdc_sync_n_3;
  wire rx_cc_cdc_sync_n_4;
  wire rx_cc_cdc_sync_n_5;
  wire rx_cc_cdc_sync_n_6;
  wire rx_cc_cdc_sync_n_7;
  wire rx_cc_cdc_sync_n_8;
  wire rx_cc_cdc_sync_n_9;
  wire [7:0]rx_cc_extend_r;
  wire rx_cc_extend_r2;
  wire rx_cc_extend_r2_i_1_n_0;
  wire rx_cc_extend_r2_i_2_n_0;
  wire user_clk;

  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[0] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_3),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [0]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[10] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_9),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [10]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[11] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_8),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [11]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[12] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_15),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [12]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[13] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_14),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [13]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[14] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_13),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [14]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[15] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_12),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [15]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[16] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_19),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [16]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[17] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_18),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [17]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[18] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_17),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [18]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[19] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_16),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [19]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[1] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_2),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [1]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[20] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_23),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [20]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[21] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_22),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [21]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[22] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_21),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [22]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[23] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_20),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [23]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[24] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_25),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [24]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[25] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_24),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [25]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[2] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_1),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [2]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[3] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_0),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [3]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[4] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_7),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [4]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[5] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_6),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [5]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[6] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_5),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [6]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[7] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_4),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [7]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[8] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_11),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [8]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[9] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_10),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [9]));
  FDRE #(
    .INIT(1'b0)) 
    \hotplug_enable.LINK_RESET_OUT_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r_reg_n_0),
        .Q(LINK_RESET_OUT),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    link_reset_r_i_1
       (.I0(link_reset_r_i_2_n_0),
        .I1(link_reset_r_i_3_n_0),
        .I2(link_reset_r_i_4_n_0),
        .I3(link_reset_r_i_5_n_0),
        .I4(link_reset_r_i_6_n_0),
        .O(link_reset_0));
  LUT3 #(
    .INIT(8'h80)) 
    link_reset_r_i_2
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .O(link_reset_r_i_2_n_0));
  LUT5 #(
    .INIT(32'h78F8F8F8)) 
    link_reset_r_i_3
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .O(link_reset_r_i_3_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_4
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .O(link_reset_r_i_4_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_5
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .O(link_reset_r_i_5_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_6
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .O(link_reset_r_i_6_n_0));
  FDRE link_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_0),
        .Q(link_reset_r_reg_n_0),
        .R(1'b0));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_16 rx_cc_cdc_sync
       (.O({rx_cc_cdc_sync_n_0,rx_cc_cdc_sync_n_1,rx_cc_cdc_sync_n_2,rx_cc_cdc_sync_n_3}),
        .\hotplug_count_synth.count_for_reset_r_reg (\hotplug_count_synth.count_for_reset_r_reg ),
        .\hotplug_count_synth.count_for_reset_r_reg[11] ({rx_cc_cdc_sync_n_8,rx_cc_cdc_sync_n_9,rx_cc_cdc_sync_n_10,rx_cc_cdc_sync_n_11}),
        .\hotplug_count_synth.count_for_reset_r_reg[15] ({rx_cc_cdc_sync_n_12,rx_cc_cdc_sync_n_13,rx_cc_cdc_sync_n_14,rx_cc_cdc_sync_n_15}),
        .\hotplug_count_synth.count_for_reset_r_reg[19] ({rx_cc_cdc_sync_n_16,rx_cc_cdc_sync_n_17,rx_cc_cdc_sync_n_18,rx_cc_cdc_sync_n_19}),
        .\hotplug_count_synth.count_for_reset_r_reg[23] ({rx_cc_cdc_sync_n_20,rx_cc_cdc_sync_n_21,rx_cc_cdc_sync_n_22,rx_cc_cdc_sync_n_23}),
        .\hotplug_count_synth.count_for_reset_r_reg[25] ({rx_cc_cdc_sync_n_24,rx_cc_cdc_sync_n_25}),
        .\hotplug_count_synth.count_for_reset_r_reg[7] ({rx_cc_cdc_sync_n_4,rx_cc_cdc_sync_n_5,rx_cc_cdc_sync_n_6,rx_cc_cdc_sync_n_7}),
        .init_clk_in(init_clk_in),
        .rx_cc_extend_r2(rx_cc_extend_r2),
        .user_clk(user_clk));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    rx_cc_extend_r2_i_1
       (.I0(rx_cc_extend_r[2]),
        .I1(rx_cc_extend_r[3]),
        .I2(rx_cc_extend_r[0]),
        .I3(rx_cc_extend_r[1]),
        .I4(rx_cc_extend_r2_i_2_n_0),
        .O(rx_cc_extend_r2_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    rx_cc_extend_r2_i_2
       (.I0(rx_cc_extend_r[5]),
        .I1(rx_cc_extend_r[4]),
        .I2(rx_cc_extend_r[7]),
        .I3(rx_cc_extend_r[6]),
        .O(rx_cc_extend_r2_i_2_n_0));
  FDRE rx_cc_extend_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2_i_1_n_0),
        .Q(rx_cc_extend_r2),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[1]),
        .Q(rx_cc_extend_r[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[2]),
        .Q(rx_cc_extend_r[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[3]),
        .Q(rx_cc_extend_r[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[4]),
        .Q(rx_cc_extend_r[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[5]),
        .Q(rx_cc_extend_r[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[6]),
        .Q(rx_cc_extend_r[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[7]),
        .Q(rx_cc_extend_r[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(rx_cc_extend_r[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL
   (MUX_SELECT,
    mux_select_c,
    user_clk);
  output [0:0]MUX_SELECT;
  input [0:0]mux_select_c;
  input user_clk;

  wire [0:0]MUX_SELECT;
  wire [0:0]mux_select_c;
  wire user_clk;

  FDRE \MUX_SELECT_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(mux_select_c),
        .Q(MUX_SELECT),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_LEFT_ALIGN_MUX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_MUX
   (\MUXED_DATA_Buffer_reg[0]_0 ,
    D,
    Q,
    MUX_SELECT,
    user_clk,
    STORAGE_SELECT_Buffer);
  output [15:0]\MUXED_DATA_Buffer_reg[0]_0 ;
  output [31:0]D;
  input [31:0]Q;
  input [0:0]MUX_SELECT;
  input user_clk;
  input [1:0]STORAGE_SELECT_Buffer;

  wire [31:0]D;
  wire [15:0]\MUXED_DATA_Buffer_reg[0]_0 ;
  wire \MUXED_DATA_Buffer_reg_n_0_[16] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[17] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[18] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[19] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[20] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[21] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[22] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[23] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[24] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[25] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[26] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[27] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[28] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[29] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[30] ;
  wire \MUXED_DATA_Buffer_reg_n_0_[31] ;
  wire [0:0]MUX_SELECT;
  wire [31:0]Q;
  wire [1:0]STORAGE_SELECT_Buffer;
  wire [0:15]muxed_data_c;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[0]_i_1 
       (.I0(Q[15]),
        .I1(MUX_SELECT),
        .I2(Q[31]),
        .O(muxed_data_c[0]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[10]_i_1 
       (.I0(Q[5]),
        .I1(MUX_SELECT),
        .I2(Q[21]),
        .O(muxed_data_c[10]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[11]_i_1 
       (.I0(Q[4]),
        .I1(MUX_SELECT),
        .I2(Q[20]),
        .O(muxed_data_c[11]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[12]_i_1 
       (.I0(Q[3]),
        .I1(MUX_SELECT),
        .I2(Q[19]),
        .O(muxed_data_c[12]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[13]_i_1 
       (.I0(Q[2]),
        .I1(MUX_SELECT),
        .I2(Q[18]),
        .O(muxed_data_c[13]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[14]_i_1 
       (.I0(Q[1]),
        .I1(MUX_SELECT),
        .I2(Q[17]),
        .O(muxed_data_c[14]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[15]_i_1 
       (.I0(Q[0]),
        .I1(MUX_SELECT),
        .I2(Q[16]),
        .O(muxed_data_c[15]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[1]_i_1 
       (.I0(Q[14]),
        .I1(MUX_SELECT),
        .I2(Q[30]),
        .O(muxed_data_c[1]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[2]_i_1 
       (.I0(Q[13]),
        .I1(MUX_SELECT),
        .I2(Q[29]),
        .O(muxed_data_c[2]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[3]_i_1 
       (.I0(Q[12]),
        .I1(MUX_SELECT),
        .I2(Q[28]),
        .O(muxed_data_c[3]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[4]_i_1 
       (.I0(Q[11]),
        .I1(MUX_SELECT),
        .I2(Q[27]),
        .O(muxed_data_c[4]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[5]_i_1 
       (.I0(Q[10]),
        .I1(MUX_SELECT),
        .I2(Q[26]),
        .O(muxed_data_c[5]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[6]_i_1 
       (.I0(Q[9]),
        .I1(MUX_SELECT),
        .I2(Q[25]),
        .O(muxed_data_c[6]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[7]_i_1 
       (.I0(Q[8]),
        .I1(MUX_SELECT),
        .I2(Q[24]),
        .O(muxed_data_c[7]));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[8]_i_1 
       (.I0(Q[7]),
        .I1(MUX_SELECT),
        .I2(Q[23]),
        .O(muxed_data_c[8]));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[9]_i_1 
       (.I0(Q[6]),
        .I1(MUX_SELECT),
        .I2(Q[22]),
        .O(muxed_data_c[9]));
  FDRE \MUXED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[0]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [15]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[10]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[11]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[12]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[13]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[14]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[15]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[15]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[14]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[13]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[12]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[1]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [14]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[11]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[10]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[9]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[8]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[7]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[6]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[5]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[4]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[3]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[2]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[2]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [13]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[1]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[0]),
        .Q(\MUXED_DATA_Buffer_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[3]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [12]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[4]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [11]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[5]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [10]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[6]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [9]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[7]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [8]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[8]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[9]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[0]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[16] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [15]),
        .O(D[31]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[10]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[26] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [5]),
        .O(D[21]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[11]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[27] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [4]),
        .O(D[20]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[12]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[28] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [3]),
        .O(D[19]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[13]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[29] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [2]),
        .O(D[18]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[14]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[30] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [1]),
        .O(D[17]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[15]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[31] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [0]),
        .O(D[16]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[16]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[16] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [15]),
        .O(D[15]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[17]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[17] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [14]),
        .O(D[14]));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[18]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[18] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [13]),
        .O(D[13]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[19]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[19] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [12]),
        .O(D[12]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[1]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[17] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [14]),
        .O(D[30]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[20]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[20] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [11]),
        .O(D[11]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[21]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[21] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [10]),
        .O(D[10]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[22]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[22] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [9]),
        .O(D[9]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[23]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[23] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [8]),
        .O(D[8]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[24]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[24] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [7]),
        .O(D[7]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[25]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[25] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [6]),
        .O(D[6]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[26]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[26] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [5]),
        .O(D[5]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[27]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[27] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [4]),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[28]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[28] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [3]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[29]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[29] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [2]),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[2]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[18] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [13]),
        .O(D[29]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[30]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[30] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [1]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[31]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[31] ),
        .I1(STORAGE_SELECT_Buffer[0]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [0]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[3]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[19] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [12]),
        .O(D[28]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[4]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[20] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [11]),
        .O(D[27]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[5]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[21] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [10]),
        .O(D[26]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[6]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[22] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [9]),
        .O(D[25]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[7]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[23] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [8]),
        .O(D[24]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[8]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[24] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [7]),
        .O(D[23]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \STORAGE_DATA_Buffer[9]_i_1 
       (.I0(\MUXED_DATA_Buffer_reg_n_0_[25] ),
        .I1(STORAGE_SELECT_Buffer[1]),
        .I2(\MUXED_DATA_Buffer_reg[0]_0 [6]),
        .O(D[22]));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_LL_TO_AXI" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LL_TO_AXI
   (M_AXI_RX_TKEEP,
    rx_eof,
    Q);
  output [2:0]M_AXI_RX_TKEEP;
  input rx_eof;
  input [1:0]Q;

  wire [2:0]M_AXI_RX_TKEEP;
  wire [1:0]Q;
  wire rx_eof;

  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \M_AXI_RX_TKEEP[1]_INST_0 
       (.I0(rx_eof),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(M_AXI_RX_TKEEP[0]));
  LUT2 #(
    .INIT(4'hE)) 
    \M_AXI_RX_TKEEP[2]_INST_0 
       (.I0(rx_eof),
        .I1(Q[1]),
        .O(M_AXI_RX_TKEEP[1]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \M_AXI_RX_TKEEP[3]_INST_0 
       (.I0(rx_eof),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(M_AXI_RX_TKEEP[2]));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_OUTPUT_MUX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_MUX
   (M_AXI_RX_TDATA,
    Q,
    user_clk,
    \OUTPUT_DATA_Buffer_reg[16]_0 ,
    OUTPUT_SELECT_Buffer);
  output [31:0]M_AXI_RX_TDATA;
  input [31:0]Q;
  input user_clk;
  input [15:0]\OUTPUT_DATA_Buffer_reg[16]_0 ;
  input OUTPUT_SELECT_Buffer;

  wire [31:0]M_AXI_RX_TDATA;
  wire [15:0]\OUTPUT_DATA_Buffer_reg[16]_0 ;
  wire OUTPUT_SELECT_Buffer;
  wire [31:0]Q;
  wire [16:31]output_data_c;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[16]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [15]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[15]),
        .O(output_data_c[16]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[17]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [14]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[14]),
        .O(output_data_c[17]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[18]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [13]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[13]),
        .O(output_data_c[18]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[19]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [12]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[12]),
        .O(output_data_c[19]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[20]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [11]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[11]),
        .O(output_data_c[20]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[21]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [10]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[10]),
        .O(output_data_c[21]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[22]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [9]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[9]),
        .O(output_data_c[22]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[23]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [8]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[8]),
        .O(output_data_c[23]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[24]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [7]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[7]),
        .O(output_data_c[24]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[25]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [6]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[6]),
        .O(output_data_c[25]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[26]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [5]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[5]),
        .O(output_data_c[26]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[27]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [4]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[4]),
        .O(output_data_c[27]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[28]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [3]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[3]),
        .O(output_data_c[28]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[29]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [2]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[2]),
        .O(output_data_c[29]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[30]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [1]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[1]),
        .O(output_data_c[30]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[31]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[16]_0 [0]),
        .I1(OUTPUT_SELECT_Buffer),
        .I2(Q[0]),
        .O(output_data_c[31]));
  FDRE \OUTPUT_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[31]),
        .Q(M_AXI_RX_TDATA[7]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[21]),
        .Q(M_AXI_RX_TDATA[13]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[20]),
        .Q(M_AXI_RX_TDATA[12]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[19]),
        .Q(M_AXI_RX_TDATA[11]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[18]),
        .Q(M_AXI_RX_TDATA[10]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[17]),
        .Q(M_AXI_RX_TDATA[9]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[16]),
        .Q(M_AXI_RX_TDATA[8]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[16]),
        .Q(M_AXI_RX_TDATA[23]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[17]),
        .Q(M_AXI_RX_TDATA[22]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[18]),
        .Q(M_AXI_RX_TDATA[21]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[19]),
        .Q(M_AXI_RX_TDATA[20]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[30]),
        .Q(M_AXI_RX_TDATA[6]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[20]),
        .Q(M_AXI_RX_TDATA[19]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[21]),
        .Q(M_AXI_RX_TDATA[18]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[22]),
        .Q(M_AXI_RX_TDATA[17]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[23]),
        .Q(M_AXI_RX_TDATA[16]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[24]),
        .Q(M_AXI_RX_TDATA[31]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[25]),
        .Q(M_AXI_RX_TDATA[30]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[26]),
        .Q(M_AXI_RX_TDATA[29]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[27]),
        .Q(M_AXI_RX_TDATA[28]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[28]),
        .Q(M_AXI_RX_TDATA[27]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[29]),
        .Q(M_AXI_RX_TDATA[26]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[29]),
        .Q(M_AXI_RX_TDATA[5]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[30]),
        .Q(M_AXI_RX_TDATA[25]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[31]),
        .Q(M_AXI_RX_TDATA[24]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[28]),
        .Q(M_AXI_RX_TDATA[4]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[27]),
        .Q(M_AXI_RX_TDATA[3]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[26]),
        .Q(M_AXI_RX_TDATA[2]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[25]),
        .Q(M_AXI_RX_TDATA[1]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[24]),
        .Q(M_AXI_RX_TDATA[0]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[23]),
        .Q(M_AXI_RX_TDATA[15]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[22]),
        .Q(M_AXI_RX_TDATA[14]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL
   (OUTPUT_SELECT_Buffer,
    output_select_c,
    user_clk);
  output OUTPUT_SELECT_Buffer;
  input [0:0]output_select_c;
  input user_clk;

  wire OUTPUT_SELECT_Buffer;
  wire [0:0]output_select_c;
  wire user_clk;

  FDRE \OUTPUT_SELECT_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_select_c),
        .Q(OUTPUT_SELECT_Buffer),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RESET_LOGIC" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RESET_LOGIC
   (link_reset_r,
    sys_reset_out,
    out,
    LINK_RESET_OUT,
    init_clk_in,
    user_clk,
    TX_LOCK,
    gt_rxresetdone_r2_reg_0);
  output link_reset_r;
  output sys_reset_out;
  input out;
  input LINK_RESET_OUT;
  input init_clk_in;
  input user_clk;
  input TX_LOCK;
  input gt_rxresetdone_r2_reg_0;

  wire LINK_RESET_OUT;
  wire SYSTEM_RESET0_n_0;
  wire TX_LOCK;
  wire gt_rxresetdone_r;
  wire gt_rxresetdone_r2;
  wire gt_rxresetdone_r2_reg_0;
  wire gt_rxresetdone_r3;
  wire init_clk_in;
  wire link_reset_r;
  wire out;
  wire scndry_out;
  wire sys_reset_out;
  wire tx_lock_comb_r;
  wire tx_lock_sync;
  wire user_clk;

  LUT4 #(
    .INIT(16'hFFDF)) 
    SYSTEM_RESET0
       (.I0(tx_lock_sync),
        .I1(out),
        .I2(gt_rxresetdone_r3),
        .I3(scndry_out),
        .O(SYSTEM_RESET0_n_0));
  FDRE SYSTEM_RESET_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(SYSTEM_RESET0_n_0),
        .Q(sys_reset_out),
        .R(1'b0));
  FDCE gt_rxresetdone_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(gt_rxresetdone_r2_reg_0),
        .D(gt_rxresetdone_r),
        .Q(gt_rxresetdone_r2));
  FDRE gt_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt_rxresetdone_r2),
        .Q(gt_rxresetdone_r3),
        .R(1'b0));
  FDCE gt_rxresetdone_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(gt_rxresetdone_r2_reg_0),
        .D(1'b1),
        .Q(gt_rxresetdone_r));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_13 link_reset_cdc_sync
       (.init_clk_in(init_clk_in),
        .link_reset_r(link_reset_r),
        .out(scndry_out),
        .user_clk(user_clk));
  FDRE link_reset_comb_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(LINK_RESET_OUT),
        .Q(link_reset_r),
        .R(1'b0));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_14 tx_lock_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(tx_lock_sync),
        .tx_lock_comb_r(tx_lock_comb_r),
        .user_clk(user_clk));
  FDRE tx_lock_comb_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(TX_LOCK),
        .Q(tx_lock_comb_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE
   (RX_LANE_UP,
    LINK_RESET_OUT,
    ena_comma_align_i,
    E,
    begin_r,
    enable_err_detect_i,
    GOT_V,
    RX_PE_DATA,
    rx_polarity_i,
    rx_hard_err_i,
    Q,
    \left_align_select_r_reg[1] ,
    \left_align_select_r_reg[0] ,
    neqOp,
    \RX_SUF_Buffer_reg[0] ,
    \RX_PE_DATA_Buffer_reg[26] ,
    \RX_PE_DATA_Buffer_reg[26]_0 ,
    \RX_PE_DATA_Buffer_reg[25] ,
    \RX_SUF_Buffer_reg[1] ,
    \word_aligned_data_r_reg[27] ,
    \word_aligned_data_r_reg[16] ,
    \word_aligned_data_r_reg[11] ,
    \word_aligned_data_r_reg[0] ,
    \SOFT_ERR_Buffer_reg[0] ,
    \RX_PE_DATA_V_Buffer_reg[0] ,
    p_9_out,
    p_8_out,
    p_2_out,
    SR,
    user_clk,
    init_clk_in,
    inc_count_r0,
    \word_aligned_control_bits_r_reg[3] ,
    hard_err_gt0,
    HPCNT_RESET,
    begin_r_reg,
    reset_count_r_reg,
    reset_count_r_reg_0,
    RX_CHANNEL_UP,
    RXCHARISK,
    RXDATA,
    D,
    \word_aligned_data_r_reg[16]_0 ,
    \soft_err_r_reg[0] );
  output RX_LANE_UP;
  output LINK_RESET_OUT;
  output ena_comma_align_i;
  output [0:0]E;
  output begin_r;
  output enable_err_detect_i;
  output GOT_V;
  output [5:0]RX_PE_DATA;
  output rx_polarity_i;
  output rx_hard_err_i;
  output [3:0]Q;
  output \left_align_select_r_reg[1] ;
  output \left_align_select_r_reg[0] ;
  output neqOp;
  output [1:0]\RX_SUF_Buffer_reg[0] ;
  output \RX_PE_DATA_Buffer_reg[26] ;
  output \RX_PE_DATA_Buffer_reg[26]_0 ;
  output \RX_PE_DATA_Buffer_reg[25] ;
  output \RX_SUF_Buffer_reg[1] ;
  output [4:0]\word_aligned_data_r_reg[27] ;
  output [7:0]\word_aligned_data_r_reg[16] ;
  output [4:0]\word_aligned_data_r_reg[11] ;
  output [7:0]\word_aligned_data_r_reg[0] ;
  output [1:0]\SOFT_ERR_Buffer_reg[0] ;
  output [1:0]\RX_PE_DATA_V_Buffer_reg[0] ;
  output [1:0]p_9_out;
  output [1:0]p_8_out;
  output [1:0]p_2_out;
  input [0:0]SR;
  input user_clk;
  input init_clk_in;
  input inc_count_r0;
  input \word_aligned_control_bits_r_reg[3] ;
  input hard_err_gt0;
  input HPCNT_RESET;
  input begin_r_reg;
  input reset_count_r_reg;
  input reset_count_r_reg_0;
  input RX_CHANNEL_UP;
  input [3:0]RXCHARISK;
  input [31:0]RXDATA;
  input [7:0]D;
  input [3:0]\word_aligned_data_r_reg[16]_0 ;
  input [3:0]\soft_err_r_reg[0] ;

  wire [7:0]D;
  wire [0:0]E;
  wire GOT_V;
  wire HPCNT_RESET;
  wire LINK_RESET_OUT;
  wire [3:0]Q;
  wire [3:0]RXCHARISK;
  wire [31:0]RXDATA;
  wire RX_CC_Buffer;
  wire RX_CHANNEL_UP;
  wire RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [5:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[25] ;
  wire \RX_PE_DATA_Buffer_reg[26] ;
  wire \RX_PE_DATA_Buffer_reg[26]_0 ;
  wire [1:0]\RX_PE_DATA_V_Buffer_reg[0] ;
  wire [1:0]\RX_SUF_Buffer_reg[0] ;
  wire \RX_SUF_Buffer_reg[1] ;
  wire [1:0]\SOFT_ERR_Buffer_reg[0] ;
  wire [0:0]SR;
  wire aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i_n_7;
  wire begin_r;
  wire begin_r0;
  wire begin_r_reg;
  wire ena_comma_align_i;
  wire enable_err_detect_i;
  wire first_v_received_r;
  wire good_cnt_r3;
  wire hard_err_gt0;
  wire inc_count_r0;
  wire init_clk_in;
  wire \left_align_select_r_reg[0] ;
  wire \left_align_select_r_reg[1] ;
  wire neqOp;
  wire [1:0]p_2_out;
  wire [1:0]p_8_out;
  wire [1:0]p_9_out;
  wire reset_count_r_reg;
  wire reset_count_r_reg_0;
  wire rx_hard_err_i;
  wire rx_polarity_i;
  wire rx_sp_i;
  wire [3:0]\soft_err_r_reg[0] ;
  wire user_clk;
  wire \word_aligned_control_bits_r_reg[3] ;
  wire [7:0]\word_aligned_data_r_reg[0] ;
  wire [4:0]\word_aligned_data_r_reg[11] ;
  wire [7:0]\word_aligned_data_r_reg[16] ;
  wire [3:0]\word_aligned_data_r_reg[16]_0 ;
  wire [4:0]\word_aligned_data_r_reg[27] ;

  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_HOTPLUG aurora_1ln_rx_lpm_hotplug_i
       (.D(RX_CC_Buffer),
        .HPCNT_RESET(HPCNT_RESET),
        .LINK_RESET_OUT(LINK_RESET_OUT),
        .SR(SR),
        .init_clk_in(init_clk_in),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i
       (.\SOFT_ERR_Buffer_reg[0]_0 (\SOFT_ERR_Buffer_reg[0] ),
        .SR(SR),
        .begin_r0(begin_r0),
        .enable_err_detect_i(enable_err_detect_i),
        .good_cnt_r3(good_cnt_r3),
        .hard_err_gt0(hard_err_gt0),
        .rx_hard_err_i(rx_hard_err_i),
        .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i
       (.E(E),
        .RXCHARISK(RXCHARISK[3:2]),
        .RX_CHANNEL_UP(RX_CHANNEL_UP),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .SR(SR),
        .align_r_reg_0(ena_comma_align_i),
        .begin_r(begin_r),
        .begin_r0(begin_r0),
        .begin_r_reg_0(begin_r_reg),
        .enable_err_detect_i(enable_err_detect_i),
        .first_v_received_r(first_v_received_r),
        .good_cnt_r3(good_cnt_r3),
        .inc_count_r0(inc_count_r0),
        .ready_r_reg_0(aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i_n_7),
        .reset_count_r_reg_0(reset_count_r_reg),
        .reset_count_r_reg_1(reset_count_r_reg_0),
        .rx_polarity_i(rx_polarity_i),
        .rx_sp_i(rx_sp_i),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SYM_DEC_4BYTE aurora_1ln_rx_lpm_sym_dec_4byte_i
       (.D(RX_CC_Buffer),
        .GOT_V(GOT_V),
        .Q(Q),
        .RXCHARISK(RXCHARISK),
        .RXDATA(RXDATA),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .RX_PE_DATA(RX_PE_DATA),
        .\RX_PE_DATA_Buffer_reg[25]_0 (\RX_PE_DATA_Buffer_reg[25] ),
        .\RX_PE_DATA_Buffer_reg[26]_0 (\RX_PE_DATA_Buffer_reg[26] ),
        .\RX_PE_DATA_Buffer_reg[26]_1 (\RX_PE_DATA_Buffer_reg[26]_0 ),
        .\RX_PE_DATA_V_Buffer_reg[0]_0 (\RX_PE_DATA_V_Buffer_reg[0] ),
        .\RX_SUF_Buffer_reg[0]_0 (\RX_SUF_Buffer_reg[0] ),
        .\RX_SUF_Buffer_reg[1]_0 (\RX_SUF_Buffer_reg[1] ),
        .first_v_received_r(first_v_received_r),
        .\left_align_select_r_reg[0]_0 (\left_align_select_r_reg[0] ),
        .\left_align_select_r_reg[0]_1 (aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i_n_7),
        .\left_align_select_r_reg[1]_0 (\left_align_select_r_reg[1] ),
        .neqOp(neqOp),
        .p_2_out(p_2_out),
        .p_8_out(p_8_out),
        .p_9_out(p_9_out),
        .rx_sp_i(rx_sp_i),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[3]_0 (\word_aligned_control_bits_r_reg[3] ),
        .\word_aligned_data_r_reg[0]_0 (\word_aligned_data_r_reg[0] ),
        .\word_aligned_data_r_reg[11]_0 (\word_aligned_data_r_reg[11] ),
        .\word_aligned_data_r_reg[16]_0 (\word_aligned_data_r_reg[16] ),
        .\word_aligned_data_r_reg[16]_1 (\word_aligned_data_r_reg[16]_0 ),
        .\word_aligned_data_r_reg[24]_0 (D),
        .\word_aligned_data_r_reg[27]_0 (\word_aligned_data_r_reg[27] ));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX
   (SOFT_ERR,
    RX_HARD_ERR,
    reset_channel_i,
    wait_for_lane_up_r0,
    user_clk,
    rx_hard_err_i,
    RX_LANE_UP,
    wait_for_lane_up_r_reg,
    POWER_DOWN,
    D);
  output SOFT_ERR;
  output RX_HARD_ERR;
  output reset_channel_i;
  output wait_for_lane_up_r0;
  input user_clk;
  input rx_hard_err_i;
  input RX_LANE_UP;
  input wait_for_lane_up_r_reg;
  input POWER_DOWN;
  input [1:0]D;

  wire [1:0]D;
  wire POWER_DOWN;
  wire RESET_CHANNEL_Buffer_i_1_n_0;
  wire RX_HARD_ERR;
  wire RX_LANE_UP;
  wire SOFT_ERR;
  wire channel_soft_err_c;
  wire hard_err_r;
  wire lane_up_r;
  wire reset_channel_i;
  wire rx_hard_err_i;
  wire \soft_err_r_reg_n_0_[0] ;
  wire \soft_err_r_reg_n_0_[1] ;
  wire user_clk;
  wire wait_for_lane_up_r0;
  wire wait_for_lane_up_r_reg;

  FDRE #(
    .INIT(1'b1)) 
    CHANNEL_HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_r),
        .Q(RX_HARD_ERR),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    CHANNEL_SOFT_ERR_Buffer_i_1
       (.I0(\soft_err_r_reg_n_0_[0] ),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .O(channel_soft_err_c));
  FDRE #(
    .INIT(1'b1)) 
    CHANNEL_SOFT_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(channel_soft_err_c),
        .Q(SOFT_ERR),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    RESET_CHANNEL_Buffer_i_1
       (.I0(POWER_DOWN),
        .I1(lane_up_r),
        .O(RESET_CHANNEL_Buffer_i_1_n_0));
  FDRE #(
    .INIT(1'b1)) 
    RESET_CHANNEL_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RESET_CHANNEL_Buffer_i_1_n_0),
        .Q(reset_channel_i),
        .R(1'b0));
  FDRE hard_err_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_hard_err_i),
        .Q(hard_err_r),
        .R(1'b0));
  FDRE lane_up_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_LANE_UP),
        .Q(lane_up_r),
        .R(1'b0));
  FDRE \soft_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(\soft_err_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \soft_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\soft_err_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    wait_for_lane_up_r_i_1
       (.I0(reset_channel_i),
        .I1(wait_for_lane_up_r_reg),
        .O(wait_for_lane_up_r0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX
   (SR,
    GTRXRESET_OUT,
    RX_CHANNEL_UP,
    START_RX,
    RESET,
    user_clk,
    GOT_V,
    wait_for_lane_up_r0,
    START_RX_Buffer_reg_0,
    reset_channel_i);
  output [0:0]SR;
  output GTRXRESET_OUT;
  output RX_CHANNEL_UP;
  output START_RX;
  output RESET;
  input user_clk;
  input GOT_V;
  input wait_for_lane_up_r0;
  input START_RX_Buffer_reg_0;
  input reset_channel_i;

  wire D;
  wire GOT_V;
  wire GTRXRESET_OUT;
  wire GTRXRESET_OUT_i_1_n_0;
  wire GTRXRESET_OUT_i_2_n_0;
  wire Q;
  wire RESET;
  wire RX_CHANNEL_UP;
  wire [0:0]SR;
  wire START_RX;
  wire START_RX_Buffer0;
  wire START_RX_Buffer_reg_0;
  wire all_lanes_v_r;
  wire bad_v_r;
  wire bad_v_r0;
  wire \free_count_r[13]_i_2_n_0 ;
  wire \free_count_r[13]_i_3_n_0 ;
  wire \free_count_r[13]_i_4_n_0 ;
  wire \free_count_r[13]_i_5_n_0 ;
  wire \free_count_r[1]_i_2_n_0 ;
  wire \free_count_r[1]_i_3_n_0 ;
  wire \free_count_r[5]_i_2_n_0 ;
  wire \free_count_r[5]_i_3_n_0 ;
  wire \free_count_r[5]_i_4_n_0 ;
  wire \free_count_r[5]_i_5_n_0 ;
  wire \free_count_r[9]_i_2_n_0 ;
  wire \free_count_r[9]_i_3_n_0 ;
  wire \free_count_r[9]_i_4_n_0 ;
  wire \free_count_r[9]_i_5_n_0 ;
  wire [0:13]free_count_r_reg;
  wire \free_count_r_reg[13]_i_1_n_0 ;
  wire \free_count_r_reg[13]_i_1_n_1 ;
  wire \free_count_r_reg[13]_i_1_n_2 ;
  wire \free_count_r_reg[13]_i_1_n_3 ;
  wire \free_count_r_reg[13]_i_1_n_4 ;
  wire \free_count_r_reg[13]_i_1_n_5 ;
  wire \free_count_r_reg[13]_i_1_n_6 ;
  wire \free_count_r_reg[13]_i_1_n_7 ;
  wire \free_count_r_reg[1]_i_1_n_3 ;
  wire \free_count_r_reg[1]_i_1_n_6 ;
  wire \free_count_r_reg[1]_i_1_n_7 ;
  wire \free_count_r_reg[5]_i_1_n_0 ;
  wire \free_count_r_reg[5]_i_1_n_1 ;
  wire \free_count_r_reg[5]_i_1_n_2 ;
  wire \free_count_r_reg[5]_i_1_n_3 ;
  wire \free_count_r_reg[5]_i_1_n_4 ;
  wire \free_count_r_reg[5]_i_1_n_5 ;
  wire \free_count_r_reg[5]_i_1_n_6 ;
  wire \free_count_r_reg[5]_i_1_n_7 ;
  wire \free_count_r_reg[9]_i_1_n_0 ;
  wire \free_count_r_reg[9]_i_1_n_1 ;
  wire \free_count_r_reg[9]_i_1_n_2 ;
  wire \free_count_r_reg[9]_i_1_n_3 ;
  wire \free_count_r_reg[9]_i_1_n_4 ;
  wire \free_count_r_reg[9]_i_1_n_5 ;
  wire \free_count_r_reg[9]_i_1_n_6 ;
  wire \free_count_r_reg[9]_i_1_n_7 ;
  wire got_first_v_r;
  wire got_first_v_r_i_1_n_0;
  wire [7:0]gtrxreset_extend_r;
  wire next_ready_c;
  wire next_verify_c;
  wire p_2_in;
  wire [15:15]p_2_out;
  wire ready_r;
  wire ready_r2;
  wire reset_channel_i;
  wire \rxver_count_r_reg[1]_srl2_i_1_n_0 ;
  wire \rxver_count_r_reg[1]_srl2_n_0 ;
  wire \rxver_count_r_reg_n_0_[2] ;
  wire user_clk;
  wire \v_count_r_reg[14]_srl15_n_0 ;
  wire \v_count_r_reg_n_0_[15] ;
  wire verify_r;
  wire \verify_watchdog_r_reg[14]_srl15_i_1_n_0 ;
  wire \verify_watchdog_r_reg[14]_srl15_i_2_n_0 ;
  wire \verify_watchdog_r_reg[14]_srl15_i_3_n_0 ;
  wire \verify_watchdog_r_reg[14]_srl15_i_4_n_0 ;
  wire \verify_watchdog_r_reg[14]_srl15_n_0 ;
  wire \verify_watchdog_r_reg_n_0_[15] ;
  wire wait_for_lane_up_r;
  wire wait_for_lane_up_r0;
  wire [3:1]\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED ;

  FDRE CHANNEL_UP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ready_r2),
        .Q(RX_CHANNEL_UP),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    FRAME_ERR_Buffer_i_1
       (.I0(START_RX),
        .O(RESET));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    GTRXRESET_OUT_i_1
       (.I0(gtrxreset_extend_r[2]),
        .I1(gtrxreset_extend_r[3]),
        .I2(gtrxreset_extend_r[0]),
        .I3(gtrxreset_extend_r[1]),
        .I4(GTRXRESET_OUT_i_2_n_0),
        .O(GTRXRESET_OUT_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    GTRXRESET_OUT_i_2
       (.I0(gtrxreset_extend_r[5]),
        .I1(gtrxreset_extend_r[4]),
        .I2(gtrxreset_extend_r[7]),
        .I3(gtrxreset_extend_r[6]),
        .O(GTRXRESET_OUT_i_2_n_0));
  FDRE GTRXRESET_OUT_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(GTRXRESET_OUT_i_1_n_0),
        .Q(GTRXRESET_OUT),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    START_RX_Buffer_i_1
       (.I0(wait_for_lane_up_r),
        .O(START_RX_Buffer0));
  FDRE START_RX_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(START_RX_Buffer0),
        .Q(START_RX),
        .R(START_RX_Buffer_reg_0));
  FDRE all_lanes_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(GOT_V),
        .Q(all_lanes_v_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h28)) 
    bad_v_r_i_1
       (.I0(got_first_v_r),
        .I1(all_lanes_v_r),
        .I2(\v_count_r_reg_n_0_[15] ),
        .O(bad_v_r0));
  FDRE bad_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(bad_v_r0),
        .Q(bad_v_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_2 
       (.I0(free_count_r_reg[10]),
        .O(\free_count_r[13]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_3 
       (.I0(free_count_r_reg[11]),
        .O(\free_count_r[13]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_4 
       (.I0(free_count_r_reg[12]),
        .O(\free_count_r[13]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_5 
       (.I0(free_count_r_reg[13]),
        .O(\free_count_r[13]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[1]_i_2 
       (.I0(free_count_r_reg[0]),
        .O(\free_count_r[1]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[1]_i_3 
       (.I0(free_count_r_reg[1]),
        .O(\free_count_r[1]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_2 
       (.I0(free_count_r_reg[2]),
        .O(\free_count_r[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_3 
       (.I0(free_count_r_reg[3]),
        .O(\free_count_r[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_4 
       (.I0(free_count_r_reg[4]),
        .O(\free_count_r[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_5 
       (.I0(free_count_r_reg[5]),
        .O(\free_count_r[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_2 
       (.I0(free_count_r_reg[6]),
        .O(\free_count_r[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_3 
       (.I0(free_count_r_reg[7]),
        .O(\free_count_r[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_4 
       (.I0(free_count_r_reg[8]),
        .O(\free_count_r[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_5 
       (.I0(free_count_r_reg[9]),
        .O(\free_count_r[9]_i_5_n_0 ));
  FDSE \free_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[1]_i_1_n_6 ),
        .Q(free_count_r_reg[0]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_4 ),
        .Q(free_count_r_reg[10]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_5 ),
        .Q(free_count_r_reg[11]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_6 ),
        .Q(free_count_r_reg[12]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_7 ),
        .Q(free_count_r_reg[13]),
        .S(wait_for_lane_up_r0));
  CARRY4 \free_count_r_reg[13]_i_1 
       (.CI(1'b0),
        .CO({\free_count_r_reg[13]_i_1_n_0 ,\free_count_r_reg[13]_i_1_n_1 ,\free_count_r_reg[13]_i_1_n_2 ,\free_count_r_reg[13]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[13]_i_1_n_4 ,\free_count_r_reg[13]_i_1_n_5 ,\free_count_r_reg[13]_i_1_n_6 ,\free_count_r_reg[13]_i_1_n_7 }),
        .S({\free_count_r[13]_i_2_n_0 ,\free_count_r[13]_i_3_n_0 ,\free_count_r[13]_i_4_n_0 ,\free_count_r[13]_i_5_n_0 }));
  FDSE \free_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[1]_i_1_n_7 ),
        .Q(free_count_r_reg[1]),
        .S(wait_for_lane_up_r0));
  CARRY4 \free_count_r_reg[1]_i_1 
       (.CI(\free_count_r_reg[5]_i_1_n_0 ),
        .CO({\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED [3:1],\free_count_r_reg[1]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED [3:2],\free_count_r_reg[1]_i_1_n_6 ,\free_count_r_reg[1]_i_1_n_7 }),
        .S({1'b0,1'b0,\free_count_r[1]_i_2_n_0 ,\free_count_r[1]_i_3_n_0 }));
  FDSE \free_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_4 ),
        .Q(free_count_r_reg[2]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_5 ),
        .Q(free_count_r_reg[3]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_6 ),
        .Q(free_count_r_reg[4]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_7 ),
        .Q(free_count_r_reg[5]),
        .S(wait_for_lane_up_r0));
  CARRY4 \free_count_r_reg[5]_i_1 
       (.CI(\free_count_r_reg[9]_i_1_n_0 ),
        .CO({\free_count_r_reg[5]_i_1_n_0 ,\free_count_r_reg[5]_i_1_n_1 ,\free_count_r_reg[5]_i_1_n_2 ,\free_count_r_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[5]_i_1_n_4 ,\free_count_r_reg[5]_i_1_n_5 ,\free_count_r_reg[5]_i_1_n_6 ,\free_count_r_reg[5]_i_1_n_7 }),
        .S({\free_count_r[5]_i_2_n_0 ,\free_count_r[5]_i_3_n_0 ,\free_count_r[5]_i_4_n_0 ,\free_count_r[5]_i_5_n_0 }));
  FDSE \free_count_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_4 ),
        .Q(free_count_r_reg[6]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_5 ),
        .Q(free_count_r_reg[7]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_6 ),
        .Q(free_count_r_reg[8]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_7 ),
        .Q(free_count_r_reg[9]),
        .S(wait_for_lane_up_r0));
  CARRY4 \free_count_r_reg[9]_i_1 
       (.CI(\free_count_r_reg[13]_i_1_n_0 ),
        .CO({\free_count_r_reg[9]_i_1_n_0 ,\free_count_r_reg[9]_i_1_n_1 ,\free_count_r_reg[9]_i_1_n_2 ,\free_count_r_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[9]_i_1_n_4 ,\free_count_r_reg[9]_i_1_n_5 ,\free_count_r_reg[9]_i_1_n_6 ,\free_count_r_reg[9]_i_1_n_7 }),
        .S({\free_count_r[9]_i_2_n_0 ,\free_count_r[9]_i_3_n_0 ,\free_count_r[9]_i_4_n_0 ,\free_count_r[9]_i_5_n_0 }));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    got_first_v_r_i_1
       (.I0(verify_r),
        .I1(got_first_v_r),
        .I2(all_lanes_v_r),
        .O(got_first_v_r_i_1_n_0));
  FDRE got_first_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(got_first_v_r_i_1_n_0),
        .Q(got_first_v_r),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    gtreset_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(p_2_in),
        .Q(Q),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT4 #(
    .INIT(16'h8A88)) 
    gtreset_flop_0_i_i_1
       (.I0(verify_r),
        .I1(\verify_watchdog_r_reg_n_0_[15] ),
        .I2(\rxver_count_r_reg_n_0_[2] ),
        .I3(bad_v_r),
        .O(p_2_in));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[1]),
        .Q(gtrxreset_extend_r[0]),
        .R(START_RX_Buffer_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[2]),
        .Q(gtrxreset_extend_r[1]),
        .R(START_RX_Buffer_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[3]),
        .Q(gtrxreset_extend_r[2]),
        .R(START_RX_Buffer_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[4]),
        .Q(gtrxreset_extend_r[3]),
        .R(START_RX_Buffer_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[5]),
        .Q(gtrxreset_extend_r[4]),
        .R(START_RX_Buffer_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[6]),
        .Q(gtrxreset_extend_r[5]),
        .R(START_RX_Buffer_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[7]),
        .Q(gtrxreset_extend_r[6]),
        .R(START_RX_Buffer_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q),
        .Q(gtrxreset_extend_r[7]),
        .R(START_RX_Buffer_reg_0));
  FDRE ready_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ready_r),
        .Q(ready_r2),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hEA)) 
    ready_r_i_1__0
       (.I0(ready_r),
        .I1(verify_r),
        .I2(\rxver_count_r_reg_n_0_[2] ),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(ready_r),
        .R(wait_for_lane_up_r0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(SR),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFAE)) 
    reset_lanes_flop_i_i_1
       (.I0(p_2_in),
        .I1(reset_channel_i),
        .I2(wait_for_lane_up_r),
        .I3(START_RX_Buffer_reg_0),
        .O(D));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg[1]_srl2 " *) 
  SRL16E \rxver_count_r_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\rxver_count_r_reg[1]_srl2_i_1_n_0 ),
        .CLK(user_clk),
        .D(verify_r),
        .Q(\rxver_count_r_reg[1]_srl2_n_0 ));
  LUT3 #(
    .INIT(8'h8F)) 
    \rxver_count_r_reg[1]_srl2_i_1 
       (.I0(all_lanes_v_r),
        .I1(\v_count_r_reg_n_0_[15] ),
        .I2(verify_r),
        .O(\rxver_count_r_reg[1]_srl2_i_1_n_0 ));
  FDRE \rxver_count_r_reg[2] 
       (.C(user_clk),
        .CE(\rxver_count_r_reg[1]_srl2_i_1_n_0 ),
        .D(\rxver_count_r_reg[1]_srl2_n_0 ),
        .Q(\rxver_count_r_reg_n_0_[2] ),
        .R(1'b0));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg[14]_srl15 " *) 
  SRL16E \v_count_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_2_out),
        .Q(\v_count_r_reg[14]_srl15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT4 #(
    .INIT(16'h8F88)) 
    \v_count_r_reg[14]_srl15_i_1 
       (.I0(\v_count_r_reg_n_0_[15] ),
        .I1(verify_r),
        .I2(got_first_v_r),
        .I3(all_lanes_v_r),
        .O(p_2_out));
  FDRE \v_count_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\v_count_r_reg[14]_srl15_n_0 ),
        .Q(\v_count_r_reg_n_0_[15] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    verify_r_i_1
       (.I0(wait_for_lane_up_r),
        .I1(\rxver_count_r_reg_n_0_[2] ),
        .I2(verify_r),
        .O(next_verify_c));
  FDRE verify_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_verify_c),
        .Q(verify_r),
        .R(wait_for_lane_up_r0));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg[14]_srl15 " *) 
  SRL16E \verify_watchdog_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(\verify_watchdog_r_reg[14]_srl15_i_1_n_0 ),
        .CLK(user_clk),
        .D(verify_r),
        .Q(\verify_watchdog_r_reg[14]_srl15_n_0 ));
  LUT4 #(
    .INIT(16'h10FF)) 
    \verify_watchdog_r_reg[14]_srl15_i_1 
       (.I0(\verify_watchdog_r_reg[14]_srl15_i_2_n_0 ),
        .I1(\verify_watchdog_r_reg[14]_srl15_i_3_n_0 ),
        .I2(\verify_watchdog_r_reg[14]_srl15_i_4_n_0 ),
        .I3(verify_r),
        .O(\verify_watchdog_r_reg[14]_srl15_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \verify_watchdog_r_reg[14]_srl15_i_2 
       (.I0(free_count_r_reg[2]),
        .I1(free_count_r_reg[6]),
        .I2(free_count_r_reg[5]),
        .I3(free_count_r_reg[11]),
        .O(\verify_watchdog_r_reg[14]_srl15_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \verify_watchdog_r_reg[14]_srl15_i_3 
       (.I0(free_count_r_reg[1]),
        .I1(free_count_r_reg[10]),
        .I2(free_count_r_reg[0]),
        .I3(free_count_r_reg[12]),
        .O(\verify_watchdog_r_reg[14]_srl15_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \verify_watchdog_r_reg[14]_srl15_i_4 
       (.I0(free_count_r_reg[8]),
        .I1(free_count_r_reg[9]),
        .I2(free_count_r_reg[7]),
        .I3(free_count_r_reg[3]),
        .I4(free_count_r_reg[4]),
        .I5(free_count_r_reg[13]),
        .O(\verify_watchdog_r_reg[14]_srl15_i_4_n_0 ));
  FDRE \verify_watchdog_r_reg[15] 
       (.C(user_clk),
        .CE(\verify_watchdog_r_reg[14]_srl15_i_1_n_0 ),
        .D(\verify_watchdog_r_reg[14]_srl15_n_0 ),
        .Q(\verify_watchdog_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE wait_for_lane_up_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(wait_for_lane_up_r0),
        .Q(wait_for_lane_up_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_ERR_DETECT_SIMPLEX_GTX_4BYTE
   (begin_r0,
    rx_hard_err_i,
    \SOFT_ERR_Buffer_reg[0]_0 ,
    good_cnt_r3,
    user_clk,
    hard_err_gt0,
    SR,
    enable_err_detect_i,
    \soft_err_r_reg[0]_0 );
  output begin_r0;
  output rx_hard_err_i;
  output [1:0]\SOFT_ERR_Buffer_reg[0]_0 ;
  input good_cnt_r3;
  input user_clk;
  input hard_err_gt0;
  input [0:0]SR;
  input enable_err_detect_i;
  input [3:0]\soft_err_r_reg[0]_0 ;

  wire [1:0]\SOFT_ERR_Buffer_reg[0]_0 ;
  wire [0:0]SR;
  wire begin_r0;
  wire cnt_good_code_r;
  wire cnt_good_code_r_i_3_n_0;
  wire cnt_good_code_r_i_4_n_0;
  wire cnt_soft_err_r;
  wire enable_err_detect_i;
  wire [1:0]err_cnt_r;
  wire \err_cnt_r[0]_i_1_n_0 ;
  wire \err_cnt_r[1]_i_1_n_0 ;
  wire \err_cnt_r[2]_i_1_n_0 ;
  wire \err_cnt_r[2]_i_2_n_0 ;
  wire good_cnt_r3;
  wire \good_cnt_r[3]_i_1_n_0 ;
  wire [3:0]good_cnt_r_reg;
  wire hard_err_frm_soft_err;
  wire hard_err_gt;
  wire hard_err_gt0;
  wire next_good_code_c;
  wire next_soft_err_c;
  wire next_start_c;
  wire p_0_in;
  wire p_1_in;
  wire p_2_in;
  wire [1:0]p_3_out;
  wire [3:0]plusOp;
  wire rx_hard_err_i;
  wire [3:0]\soft_err_r_reg[0]_0 ;
  wire \soft_err_r_reg_n_0_[0] ;
  wire \soft_err_r_reg_n_0_[3] ;
  wire start_r;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \SOFT_ERR_Buffer[0]_i_1 
       (.I0(p_2_in),
        .I1(\soft_err_r_reg_n_0_[0] ),
        .O(p_3_out[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \SOFT_ERR_Buffer[1]_i_1 
       (.I0(\soft_err_r_reg_n_0_[3] ),
        .I1(p_1_in),
        .O(p_3_out[0]));
  FDRE \SOFT_ERR_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_3_out[1]),
        .Q(\SOFT_ERR_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \SOFT_ERR_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_3_out[0]),
        .Q(\SOFT_ERR_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'hFFAE)) 
    align_r_i_1
       (.I0(SR),
        .I1(p_0_in),
        .I2(hard_err_frm_soft_err),
        .I3(hard_err_gt),
        .O(begin_r0));
  LUT5 #(
    .INIT(32'hAAAA2A00)) 
    cnt_good_code_r_i_2
       (.I0(cnt_good_code_r_i_3_n_0),
        .I1(cnt_good_code_r_i_4_n_0),
        .I2(good_cnt_r_reg[3]),
        .I3(cnt_good_code_r),
        .I4(cnt_soft_err_r),
        .O(next_good_code_c));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    cnt_good_code_r_i_3
       (.I0(\soft_err_r_reg_n_0_[0] ),
        .I1(p_2_in),
        .I2(p_1_in),
        .I3(\soft_err_r_reg_n_0_[3] ),
        .O(cnt_good_code_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h80)) 
    cnt_good_code_r_i_4
       (.I0(good_cnt_r_reg[2]),
        .I1(good_cnt_r_reg[1]),
        .I2(good_cnt_r_reg[0]),
        .O(cnt_good_code_r_i_4_n_0));
  FDRE cnt_good_code_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_good_code_c),
        .Q(cnt_good_code_r),
        .R(good_cnt_r3));
  LUT4 #(
    .INIT(16'h00FE)) 
    cnt_soft_err_r_i_1
       (.I0(cnt_soft_err_r),
        .I1(start_r),
        .I2(cnt_good_code_r),
        .I3(cnt_good_code_r_i_3_n_0),
        .O(next_soft_err_c));
  FDRE cnt_soft_err_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_soft_err_c),
        .Q(cnt_soft_err_r),
        .R(good_cnt_r3));
  LUT5 #(
    .INIT(32'hBEBE4140)) 
    \err_cnt_r[0]_i_1 
       (.I0(p_0_in),
        .I1(\err_cnt_r[2]_i_2_n_0 ),
        .I2(cnt_soft_err_r),
        .I3(err_cnt_r[1]),
        .I4(err_cnt_r[0]),
        .O(\err_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'hCCCC6CC8)) 
    \err_cnt_r[1]_i_1 
       (.I0(err_cnt_r[0]),
        .I1(err_cnt_r[1]),
        .I2(cnt_soft_err_r),
        .I3(\err_cnt_r[2]_i_2_n_0 ),
        .I4(p_0_in),
        .O(\err_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'hFFFF8000)) 
    \err_cnt_r[2]_i_1 
       (.I0(err_cnt_r[0]),
        .I1(err_cnt_r[1]),
        .I2(cnt_soft_err_r),
        .I3(\err_cnt_r[2]_i_2_n_0 ),
        .I4(p_0_in),
        .O(\err_cnt_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'hFFF1)) 
    \err_cnt_r[2]_i_2 
       (.I0(good_cnt_r_reg[3]),
        .I1(good_cnt_r_reg[2]),
        .I2(good_cnt_r_reg[1]),
        .I3(good_cnt_r_reg[0]),
        .O(\err_cnt_r[2]_i_2_n_0 ));
  FDRE \err_cnt_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\err_cnt_r[0]_i_1_n_0 ),
        .Q(err_cnt_r[0]),
        .R(good_cnt_r3));
  FDRE \err_cnt_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\err_cnt_r[1]_i_1_n_0 ),
        .Q(err_cnt_r[1]),
        .R(good_cnt_r3));
  FDRE \err_cnt_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\err_cnt_r[2]_i_1_n_0 ),
        .Q(p_0_in),
        .R(good_cnt_r3));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \good_cnt_r[0]_i_1 
       (.I0(good_cnt_r_reg[0]),
        .O(plusOp[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \good_cnt_r[1]_i_1 
       (.I0(good_cnt_r_reg[0]),
        .I1(good_cnt_r_reg[1]),
        .O(plusOp[1]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \good_cnt_r[2]_i_1 
       (.I0(good_cnt_r_reg[0]),
        .I1(good_cnt_r_reg[1]),
        .I2(good_cnt_r_reg[2]),
        .O(plusOp[2]));
  LUT4 #(
    .INIT(16'hEFFF)) 
    \good_cnt_r[3]_i_1 
       (.I0(start_r),
        .I1(cnt_soft_err_r),
        .I2(enable_err_detect_i),
        .I3(cnt_good_code_r),
        .O(\good_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \good_cnt_r[3]_i_2 
       (.I0(good_cnt_r_reg[3]),
        .I1(good_cnt_r_reg[0]),
        .I2(good_cnt_r_reg[1]),
        .I3(good_cnt_r_reg[2]),
        .O(plusOp[3]));
  FDRE \good_cnt_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(plusOp[0]),
        .Q(good_cnt_r_reg[0]),
        .R(\good_cnt_r[3]_i_1_n_0 ));
  FDRE \good_cnt_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(plusOp[1]),
        .Q(good_cnt_r_reg[1]),
        .R(\good_cnt_r[3]_i_1_n_0 ));
  FDRE \good_cnt_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(plusOp[2]),
        .Q(good_cnt_r_reg[2]),
        .R(\good_cnt_r[3]_i_1_n_0 ));
  FDRE \good_cnt_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(plusOp[3]),
        .Q(good_cnt_r_reg[3]),
        .R(\good_cnt_r[3]_i_1_n_0 ));
  FDRE hard_err_frm_soft_err_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in),
        .Q(hard_err_frm_soft_err),
        .R(good_cnt_r3));
  FDRE hard_err_gt_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_gt0),
        .Q(hard_err_gt),
        .R(good_cnt_r3));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    hard_err_r_i_1
       (.I0(hard_err_gt),
        .I1(hard_err_frm_soft_err),
        .I2(p_0_in),
        .O(rx_hard_err_i));
  FDRE \soft_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [3]),
        .Q(\soft_err_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \soft_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [2]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \soft_err_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [1]),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \soft_err_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [0]),
        .Q(\soft_err_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hA8888888)) 
    start_r_i_1
       (.I0(cnt_good_code_r_i_3_n_0),
        .I1(start_r),
        .I2(cnt_good_code_r_i_4_n_0),
        .I3(good_cnt_r_reg[3]),
        .I4(cnt_good_code_r),
        .O(next_start_c));
  FDSE start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_start_c),
        .Q(start_r),
        .S(good_cnt_r3));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX
   (SR,
    GTRXRESET_OUT,
    RX_CHANNEL_UP,
    SOFT_ERR,
    RX_HARD_ERR,
    START_RX,
    RESET,
    user_clk,
    GOT_V,
    rx_hard_err_i,
    RX_LANE_UP,
    START_RX_Buffer_reg,
    POWER_DOWN,
    D);
  output [0:0]SR;
  output GTRXRESET_OUT;
  output RX_CHANNEL_UP;
  output SOFT_ERR;
  output RX_HARD_ERR;
  output START_RX;
  output RESET;
  input user_clk;
  input GOT_V;
  input rx_hard_err_i;
  input RX_LANE_UP;
  input START_RX_Buffer_reg;
  input POWER_DOWN;
  input [1:0]D;

  wire [1:0]D;
  wire GOT_V;
  wire GTRXRESET_OUT;
  wire POWER_DOWN;
  wire RESET;
  wire RX_CHANNEL_UP;
  wire RX_HARD_ERR;
  wire RX_LANE_UP;
  wire SOFT_ERR;
  wire [0:0]SR;
  wire START_RX;
  wire START_RX_Buffer_reg;
  wire reset_channel_i;
  wire rx_hard_err_i;
  wire user_clk;
  wire wait_for_lane_up_r0;

  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_ERR_DETECT_SIMPLEX rx_channel_err_detect_simplex_i
       (.D(D),
        .POWER_DOWN(POWER_DOWN),
        .RX_HARD_ERR(RX_HARD_ERR),
        .RX_LANE_UP(RX_LANE_UP),
        .SOFT_ERR(SOFT_ERR),
        .reset_channel_i(reset_channel_i),
        .rx_hard_err_i(rx_hard_err_i),
        .user_clk(user_clk),
        .wait_for_lane_up_r0(wait_for_lane_up_r0),
        .wait_for_lane_up_r_reg(START_RX_Buffer_reg));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_CHANNEL_INIT_SM_SIMPLEX rx_channel_init_sm_simplex_i
       (.GOT_V(GOT_V),
        .GTRXRESET_OUT(GTRXRESET_OUT),
        .RESET(RESET),
        .RX_CHANNEL_UP(RX_CHANNEL_UP),
        .SR(SR),
        .START_RX(START_RX),
        .START_RX_Buffer_reg_0(START_RX_Buffer_reg),
        .reset_channel_i(reset_channel_i),
        .user_clk(user_clk),
        .wait_for_lane_up_r0(wait_for_lane_up_r0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LANE_INIT_SM_SIMPLEX_4BYTE
   (RX_LANE_UP,
    align_r_reg_0,
    E,
    begin_r,
    enable_err_detect_i,
    rx_polarity_i,
    good_cnt_r3,
    ready_r_reg_0,
    SR,
    user_clk,
    begin_r0,
    inc_count_r0,
    begin_r_reg_0,
    RX_NEG_Buffer,
    reset_count_r_reg_0,
    reset_count_r_reg_1,
    RX_CHANNEL_UP,
    rx_sp_i,
    RXCHARISK,
    first_v_received_r);
  output RX_LANE_UP;
  output align_r_reg_0;
  output [0:0]E;
  output begin_r;
  output enable_err_detect_i;
  output rx_polarity_i;
  output good_cnt_r3;
  output ready_r_reg_0;
  input [0:0]SR;
  input user_clk;
  input begin_r0;
  input inc_count_r0;
  input begin_r_reg_0;
  input RX_NEG_Buffer;
  input reset_count_r_reg_0;
  input reset_count_r_reg_1;
  input RX_CHANNEL_UP;
  input rx_sp_i;
  input [1:0]RXCHARISK;
  input first_v_received_r;

  wire D;
  wire [0:0]E;
  wire [1:0]RXCHARISK;
  wire RX_CHANNEL_UP;
  wire RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [0:0]SR;
  wire align_r_reg_0;
  wire begin_r;
  wire begin_r0;
  wire begin_r_reg_0;
  wire counter1_r0;
  wire \counter1_r[0]_i_3_n_0 ;
  wire \counter1_r[2]_i_1_n_0 ;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire \counter1_r_reg_n_0_[5] ;
  wire \counter1_r_reg_n_0_[6] ;
  wire \counter1_r_reg_n_0_[7] ;
  wire counter2_r0;
  wire \counter2_r_reg[14]_srl15_n_0 ;
  wire \counter2_r_reg_n_0_[15] ;
  wire enable_err_detect_i;
  wire first_v_received_r;
  wire good_cnt_r3;
  wire gtx_rx_reset_i;
  wire inc_count_r0;
  wire next_align_c;
  wire next_begin_c;
  wire next_polarity_c;
  wire next_ready_c;
  wire next_realign_c;
  wire next_rst_c;
  wire [7:0]p_0_in;
  wire polarity_r;
  wire ready_r_reg_0;
  wire realign_r;
  wire reset_count_r;
  wire reset_count_r0;
  wire reset_count_r_reg_0;
  wire reset_count_r_reg_1;
  wire rx_polarity_i;
  wire rx_polarity_r_i_1_n_0;
  wire rx_sp_i;
  wire std_bool;
  wire std_bool0_in;
  wire std_bool0_in3_in;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(enable_err_detect_i),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'hF222)) 
    align_r_i_2
       (.I0(align_r_reg_0),
        .I1(std_bool0_in),
        .I2(std_bool0_in3_in),
        .I3(gtx_rx_reset_i),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r_reg_0),
        .R(begin_r0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    begin_r_i_1
       (.I0(realign_r),
        .I1(begin_r_reg_0),
        .I2(D),
        .I3(\counter2_r_reg_n_0_[15] ),
        .I4(polarity_r),
        .I5(RX_NEG_Buffer),
        .O(next_begin_c));
  FDSE begin_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_begin_c),
        .Q(begin_r),
        .S(begin_r0));
  LUT1 #(
    .INIT(2'h1)) 
    cnt_good_code_r_i_1
       (.I0(enable_err_detect_i),
        .O(good_cnt_r3));
  LUT2 #(
    .INIT(4'hE)) 
    \counter1_r[0]_i_1 
       (.I0(D),
        .I1(reset_count_r),
        .O(counter1_r0));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[0]_i_2 
       (.I0(std_bool0_in),
        .I1(std_bool),
        .I2(std_bool0_in3_in),
        .I3(\counter1_r[0]_i_3_n_0 ),
        .I4(\counter1_r_reg_n_0_[3] ),
        .I5(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \counter1_r[0]_i_3 
       (.I0(\counter1_r_reg_n_0_[5] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[7] ),
        .O(\counter1_r[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[1]_i_1 
       (.I0(\counter1_r_reg_n_0_[1] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r[0]_i_3_n_0 ),
        .I3(std_bool0_in3_in),
        .I4(std_bool),
        .O(p_0_in[6]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[2]_i_1 
       (.I0(std_bool),
        .I1(std_bool0_in3_in),
        .I2(\counter1_r_reg_n_0_[7] ),
        .I3(\counter1_r_reg_n_0_[6] ),
        .I4(\counter1_r_reg_n_0_[5] ),
        .I5(\counter1_r_reg_n_0_[3] ),
        .O(\counter1_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[3]_i_1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[5] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[7] ),
        .I4(std_bool0_in3_in),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \counter1_r[4]_i_1 
       (.I0(std_bool0_in3_in),
        .I1(\counter1_r_reg_n_0_[7] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[5]_i_1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[6]_i_1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[7]_i_1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(p_0_in[7]),
        .Q(std_bool0_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(p_0_in[6]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(\counter1_r[2]_i_1_n_0 ),
        .Q(std_bool),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(E),
        .D(p_0_in[4]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[4] 
       (.C(user_clk),
        .CE(E),
        .D(p_0_in[3]),
        .Q(std_bool0_in3_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[5] 
       (.C(user_clk),
        .CE(E),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[5] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[6] 
       (.C(user_clk),
        .CE(E),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[6] ),
        .R(counter1_r0));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[7] 
       (.C(user_clk),
        .CE(E),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[7] ),
        .S(counter1_r0));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/counter2_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i/aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/counter2_r_reg[14]_srl15 " *) 
  SRL16E \counter2_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(counter2_r0),
        .CLK(user_clk),
        .D(D),
        .Q(\counter2_r_reg[14]_srl15_n_0 ));
  LUT3 #(
    .INIT(8'hD5)) 
    \counter2_r_reg[14]_srl15_i_1 
       (.I0(D),
        .I1(RX_CHANNEL_UP),
        .I2(rx_sp_i),
        .O(counter2_r0));
  FDRE \counter2_r_reg[15] 
       (.C(user_clk),
        .CE(counter2_r0),
        .D(\counter2_r_reg[14]_srl15_n_0 ),
        .Q(\counter2_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE inc_count_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(inc_count_r0),
        .Q(E),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(RX_LANE_UP),
        .R(SR));
  LUT5 #(
    .INIT(32'hFFFF888F)) 
    \left_align_select_r[0]_i_2 
       (.I0(RXCHARISK[1]),
        .I1(RXCHARISK[0]),
        .I2(D),
        .I3(align_r_reg_0),
        .I4(first_v_received_r),
        .O(ready_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'h08)) 
    polarity_r_i_1
       (.I0(std_bool),
        .I1(realign_r),
        .I2(begin_r_reg_0),
        .O(next_polarity_c));
  FDRE polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_polarity_c),
        .Q(polarity_r),
        .R(begin_r0));
  LUT4 #(
    .INIT(16'h4F44)) 
    ready_r_i_1
       (.I0(\counter2_r_reg_n_0_[15] ),
        .I1(D),
        .I2(RX_NEG_Buffer),
        .I3(polarity_r),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D),
        .R(begin_r0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'hFF040404)) 
    realign_r_i_1
       (.I0(begin_r_reg_0),
        .I1(realign_r),
        .I2(std_bool),
        .I3(std_bool0_in),
        .I4(align_r_reg_0),
        .O(next_realign_c));
  FDRE realign_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_realign_c),
        .Q(realign_r),
        .R(begin_r0));
  LUT6 #(
    .INIT(64'hFFFFFFFF0F00BBBB)) 
    reset_count_r_i_1
       (.I0(reset_count_r_reg_0),
        .I1(reset_count_r_reg_1),
        .I2(begin_r),
        .I3(std_bool0_in3_in),
        .I4(gtx_rx_reset_i),
        .I5(SR),
        .O(reset_count_r0));
  FDRE reset_count_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_count_r0),
        .Q(reset_count_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    rst_r_i_1
       (.I0(begin_r),
        .I1(std_bool0_in3_in),
        .I2(gtx_rx_reset_i),
        .O(next_rst_c));
  FDRE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(gtx_rx_reset_i),
        .R(begin_r0));
  LUT3 #(
    .INIT(8'h78)) 
    rx_polarity_r_i_1
       (.I0(RX_NEG_Buffer),
        .I1(polarity_r),
        .I2(rx_polarity_i),
        .O(rx_polarity_r_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rx_polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_polarity_r_i_1_n_0),
        .Q(rx_polarity_i),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_LL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL
   (rx_eof,
    FRAME_ERR,
    M_AXI_RX_TLAST,
    M_AXI_RX_TVALID,
    M_AXI_UFC_RX_TVALID,
    Q,
    M_AXI_RX_TDATA,
    M_AXI_UFC_RX_TDATA,
    M_AXI_UFC_RX_TKEEP,
    M_AXI_UFC_RX_TLAST,
    user_clk,
    RESET,
    neqOp,
    \rx_suf_r_reg[0] ,
    p_8_out,
    p_9_out,
    p_2_out,
    \stage_1_data_r_reg[0] ,
    RX_PE_DATA,
    \stage_1_data_r_reg[11] ,
    \stage_1_data_r_reg[16] ,
    \stage_1_data_r_reg[27] ,
    START_RX,
    \stage_1_count_value_r_reg[0] ,
    \stage_1_count_value_r_reg[1] ,
    \stage_1_count_value_r_reg[2] ,
    \stage_1_count_value_r_reg[3] ,
    D);
  output rx_eof;
  output FRAME_ERR;
  output M_AXI_RX_TLAST;
  output M_AXI_RX_TVALID;
  output M_AXI_UFC_RX_TVALID;
  output [1:0]Q;
  output [31:0]M_AXI_RX_TDATA;
  output [31:0]M_AXI_UFC_RX_TDATA;
  output [0:0]M_AXI_UFC_RX_TKEEP;
  output M_AXI_UFC_RX_TLAST;
  input user_clk;
  input RESET;
  input neqOp;
  input [1:0]\rx_suf_r_reg[0] ;
  input [1:0]p_8_out;
  input [1:0]p_9_out;
  input [1:0]p_2_out;
  input [7:0]\stage_1_data_r_reg[0] ;
  input [5:0]RX_PE_DATA;
  input [4:0]\stage_1_data_r_reg[11] ;
  input [7:0]\stage_1_data_r_reg[16] ;
  input [4:0]\stage_1_data_r_reg[27] ;
  input START_RX;
  input \stage_1_count_value_r_reg[0] ;
  input \stage_1_count_value_r_reg[1] ;
  input \stage_1_count_value_r_reg[2] ;
  input \stage_1_count_value_r_reg[3] ;
  input [1:0]D;

  wire [1:0]D;
  wire FRAME_ERR;
  wire [31:0]M_AXI_RX_TDATA;
  wire M_AXI_RX_TLAST;
  wire M_AXI_RX_TVALID;
  wire [31:0]M_AXI_UFC_RX_TDATA;
  wire [0:0]M_AXI_UFC_RX_TKEEP;
  wire M_AXI_UFC_RX_TLAST;
  wire M_AXI_UFC_RX_TVALID;
  wire [1:0]Q;
  wire RESET;
  wire [5:0]RX_PE_DATA;
  wire START_RX;
  wire UFC_START;
  wire barrel_shifter_control_i;
  wire neqOp;
  wire [1:0]p_2_out;
  wire [1:0]p_8_out;
  wire [1:0]p_9_out;
  wire [0:1]pdu_data_v_i;
  wire [0:1]pdu_ecp_i;
  wire [0:1]pdu_scp_i;
  wire plusOp;
  wire rx_eof;
  wire [1:0]\rx_suf_r_reg[0] ;
  wire \stage_1_count_value_r_reg[0] ;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[2] ;
  wire \stage_1_count_value_r_reg[3] ;
  wire [0:31]stage_1_data_r;
  wire [7:0]\stage_1_data_r_reg[0] ;
  wire [4:0]\stage_1_data_r_reg[11] ;
  wire [7:0]\stage_1_data_r_reg[16] ;
  wire [4:0]\stage_1_data_r_reg[27] ;
  wire \stage_1_rx_ll_deframer_i/S1_in ;
  wire ufc_filter_i_n_10;
  wire ufc_filter_i_n_11;
  wire ufc_filter_i_n_12;
  wire ufc_filter_i_n_13;
  wire ufc_filter_i_n_14;
  wire ufc_filter_i_n_15;
  wire ufc_filter_i_n_16;
  wire ufc_filter_i_n_17;
  wire ufc_filter_i_n_18;
  wire ufc_filter_i_n_19;
  wire ufc_filter_i_n_20;
  wire ufc_filter_i_n_21;
  wire ufc_filter_i_n_22;
  wire ufc_filter_i_n_23;
  wire ufc_filter_i_n_24;
  wire ufc_filter_i_n_25;
  wire ufc_filter_i_n_26;
  wire ufc_filter_i_n_27;
  wire ufc_filter_i_n_28;
  wire ufc_filter_i_n_29;
  wire ufc_filter_i_n_30;
  wire ufc_filter_i_n_31;
  wire ufc_filter_i_n_32;
  wire ufc_filter_i_n_33;
  wire ufc_filter_i_n_34;
  wire ufc_filter_i_n_35;
  wire ufc_filter_i_n_36;
  wire ufc_filter_i_n_37;
  wire ufc_filter_i_n_38;
  wire ufc_filter_i_n_39;
  wire ufc_filter_i_n_40;
  wire ufc_filter_i_n_44;
  wire ufc_filter_i_n_45;
  wire ufc_filter_i_n_6;
  wire ufc_filter_i_n_7;
  wire ufc_filter_i_n_8;
  wire ufc_filter_i_n_9;
  wire user_clk;

  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH rx_ll_pdu_datapath_i
       (.\AFTER_SCP_Buffer_reg[1] (ufc_filter_i_n_45),
        .D({pdu_scp_i[0],pdu_scp_i[1]}),
        .FRAME_ERR(FRAME_ERR),
        .\IN_FRAME_Buffer_reg[1] (ufc_filter_i_n_40),
        .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
        .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
        .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
        .Q({pdu_data_v_i[0],pdu_data_v_i[1]}),
        .RESET(RESET),
        .\RX_REM_Buffer_reg[0]_0 (Q),
        .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
        .START_RX(START_RX),
        .in_frame_r_reg(ufc_filter_i_n_39),
        .rx_eof(rx_eof),
        .\stage_1_ecp_r_reg[0]_0 ({pdu_ecp_i[0],pdu_ecp_i[1]}),
        .stage_1_pad_r_reg_0(ufc_filter_i_n_38),
        .\stage_2_data_r_reg[0]_0 ({stage_1_data_r[0],stage_1_data_r[1],stage_1_data_r[2],stage_1_data_r[3],stage_1_data_r[4],stage_1_data_r[5],stage_1_data_r[6],stage_1_data_r[7],stage_1_data_r[8],stage_1_data_r[9],stage_1_data_r[10],stage_1_data_r[11],stage_1_data_r[12],stage_1_data_r[13],stage_1_data_r[14],stage_1_data_r[15],stage_1_data_r[16],stage_1_data_r[17],stage_1_data_r[18],stage_1_data_r[19],stage_1_data_r[20],stage_1_data_r[21],stage_1_data_r[22],stage_1_data_r[23],stage_1_data_r[24],stage_1_data_r[25],stage_1_data_r[26],stage_1_data_r[27],stage_1_data_r[28],stage_1_data_r[29],stage_1_data_r[30],stage_1_data_r[31]}),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH rx_ll_ufc_datapath_i
       (.M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
        .M_AXI_UFC_RX_TKEEP(M_AXI_UFC_RX_TKEEP),
        .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
        .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
        .Q({plusOp,ufc_filter_i_n_44}),
        .RESET(RESET),
        .UFC_START(UFC_START),
        .barrel_shifter_control_i(barrel_shifter_control_i),
        .\stage_1_data_r_reg[0]_0 ({stage_1_data_r[0],stage_1_data_r[1],stage_1_data_r[2],stage_1_data_r[3],stage_1_data_r[4],stage_1_data_r[5],stage_1_data_r[6],stage_1_data_r[7],stage_1_data_r[8],stage_1_data_r[9],stage_1_data_r[10],stage_1_data_r[11],stage_1_data_r[12],stage_1_data_r[13],stage_1_data_r[14],stage_1_data_r[15],stage_1_data_r[16],stage_1_data_r[17],stage_1_data_r[18],stage_1_data_r[19],stage_1_data_r[20],stage_1_data_r[21],stage_1_data_r[22],stage_1_data_r[23],stage_1_data_r[24],stage_1_data_r[25],stage_1_data_r[26],stage_1_data_r[27],stage_1_data_r[28],stage_1_data_r[29],stage_1_data_r[30],stage_1_data_r[31]}),
        .\stage_1_data_r_reg[0]_1 (ufc_filter_i_n_6),
        .\stage_1_data_r_reg[10]_0 (ufc_filter_i_n_16),
        .\stage_1_data_r_reg[11]_0 (ufc_filter_i_n_17),
        .\stage_1_data_r_reg[12]_0 (ufc_filter_i_n_18),
        .\stage_1_data_r_reg[13]_0 (ufc_filter_i_n_19),
        .\stage_1_data_r_reg[14]_0 (ufc_filter_i_n_20),
        .\stage_1_data_r_reg[15]_0 (ufc_filter_i_n_21),
        .\stage_1_data_r_reg[16]_0 (ufc_filter_i_n_22),
        .\stage_1_data_r_reg[17]_0 (ufc_filter_i_n_23),
        .\stage_1_data_r_reg[18]_0 (ufc_filter_i_n_24),
        .\stage_1_data_r_reg[19]_0 (ufc_filter_i_n_25),
        .\stage_1_data_r_reg[1]_0 (ufc_filter_i_n_7),
        .\stage_1_data_r_reg[20]_0 (ufc_filter_i_n_26),
        .\stage_1_data_r_reg[21]_0 (ufc_filter_i_n_27),
        .\stage_1_data_r_reg[22]_0 (ufc_filter_i_n_28),
        .\stage_1_data_r_reg[23]_0 (ufc_filter_i_n_29),
        .\stage_1_data_r_reg[24]_0 (ufc_filter_i_n_30),
        .\stage_1_data_r_reg[25]_0 (ufc_filter_i_n_31),
        .\stage_1_data_r_reg[26]_0 (ufc_filter_i_n_32),
        .\stage_1_data_r_reg[27]_0 (ufc_filter_i_n_33),
        .\stage_1_data_r_reg[28]_0 (ufc_filter_i_n_34),
        .\stage_1_data_r_reg[29]_0 (ufc_filter_i_n_35),
        .\stage_1_data_r_reg[2]_0 (ufc_filter_i_n_8),
        .\stage_1_data_r_reg[30]_0 (ufc_filter_i_n_36),
        .\stage_1_data_r_reg[31]_0 (ufc_filter_i_n_37),
        .\stage_1_data_r_reg[3]_0 (ufc_filter_i_n_9),
        .\stage_1_data_r_reg[4]_0 (ufc_filter_i_n_10),
        .\stage_1_data_r_reg[5]_0 (ufc_filter_i_n_11),
        .\stage_1_data_r_reg[6]_0 (ufc_filter_i_n_12),
        .\stage_1_data_r_reg[7]_0 (ufc_filter_i_n_13),
        .\stage_1_data_r_reg[8]_0 (ufc_filter_i_n_14),
        .\stage_1_data_r_reg[9]_0 (ufc_filter_i_n_15),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_FILTER ufc_filter_i
       (.D({pdu_scp_i[0],pdu_scp_i[1]}),
        .\PDU_ECP_Buffer_reg[0]_0 ({pdu_ecp_i[0],pdu_ecp_i[1]}),
        .\PDU_ECP_Buffer_reg[0]_1 (ufc_filter_i_n_40),
        .\PDU_ECP_Buffer_reg[1]_0 (ufc_filter_i_n_39),
        .\PDU_PAD_Buffer_reg[0]_0 (ufc_filter_i_n_38),
        .\PDU_SCP_Buffer_reg[1]_0 (ufc_filter_i_n_45),
        .Q({pdu_data_v_i[0],pdu_data_v_i[1]}),
        .RESET(RESET),
        .RX_PE_DATA(RX_PE_DATA),
        .\RX_PE_DATA_Buffer_reg[10] (ufc_filter_i_n_16),
        .\RX_PE_DATA_Buffer_reg[24] (ufc_filter_i_n_30),
        .\RX_PE_DATA_Buffer_reg[25] (ufc_filter_i_n_31),
        .\RX_PE_DATA_Buffer_reg[26] (ufc_filter_i_n_32),
        .\RX_PE_DATA_Buffer_reg[8] (ufc_filter_i_n_14),
        .\RX_PE_DATA_Buffer_reg[9] (ufc_filter_i_n_15),
        .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
        .\UFC_DATA_V_Buffer_reg[0]_0 ({plusOp,ufc_filter_i_n_44}),
        .UFC_START(UFC_START),
        .barrel_shifter_control_i(barrel_shifter_control_i),
        .neqOp(neqOp),
        .p_2_out(p_2_out),
        .p_8_out(p_8_out),
        .p_9_out(p_9_out),
        .\rx_data_v_r_reg[0]_0 (D),
        .\rx_suf_r_reg[0]_0 (\rx_suf_r_reg[0] ),
        .\stage_1_count_value_r_reg[0]_0 (\stage_1_count_value_r_reg[0] ),
        .\stage_1_count_value_r_reg[1]_0 (\stage_1_count_value_r_reg[1] ),
        .\stage_1_count_value_r_reg[2]_0 (\stage_1_count_value_r_reg[2] ),
        .\stage_1_count_value_r_reg[3]_0 (\stage_1_count_value_r_reg[3] ),
        .\stage_1_data_r_reg[0] (\stage_1_data_r_reg[0] ),
        .\stage_1_data_r_reg[11] (\stage_1_data_r_reg[11] ),
        .\stage_1_data_r_reg[16] (\stage_1_data_r_reg[16] ),
        .\stage_1_data_r_reg[27] (\stage_1_data_r_reg[27] ),
        .user_clk(user_clk),
        .\word_aligned_data_r_reg[0] (ufc_filter_i_n_6),
        .\word_aligned_data_r_reg[11] (ufc_filter_i_n_17),
        .\word_aligned_data_r_reg[12] (ufc_filter_i_n_18),
        .\word_aligned_data_r_reg[13] (ufc_filter_i_n_19),
        .\word_aligned_data_r_reg[14] (ufc_filter_i_n_20),
        .\word_aligned_data_r_reg[15] (ufc_filter_i_n_21),
        .\word_aligned_data_r_reg[16] (ufc_filter_i_n_22),
        .\word_aligned_data_r_reg[17] (ufc_filter_i_n_23),
        .\word_aligned_data_r_reg[18] (ufc_filter_i_n_24),
        .\word_aligned_data_r_reg[19] (ufc_filter_i_n_25),
        .\word_aligned_data_r_reg[1] (ufc_filter_i_n_7),
        .\word_aligned_data_r_reg[20] (ufc_filter_i_n_26),
        .\word_aligned_data_r_reg[21] (ufc_filter_i_n_27),
        .\word_aligned_data_r_reg[22] (ufc_filter_i_n_28),
        .\word_aligned_data_r_reg[23] (ufc_filter_i_n_29),
        .\word_aligned_data_r_reg[27] (ufc_filter_i_n_33),
        .\word_aligned_data_r_reg[28] (ufc_filter_i_n_34),
        .\word_aligned_data_r_reg[29] (ufc_filter_i_n_35),
        .\word_aligned_data_r_reg[2] (ufc_filter_i_n_8),
        .\word_aligned_data_r_reg[30] (ufc_filter_i_n_36),
        .\word_aligned_data_r_reg[31] (ufc_filter_i_n_37),
        .\word_aligned_data_r_reg[3] (ufc_filter_i_n_9),
        .\word_aligned_data_r_reg[4] (ufc_filter_i_n_10),
        .\word_aligned_data_r_reg[5] (ufc_filter_i_n_11),
        .\word_aligned_data_r_reg[6] (ufc_filter_i_n_12),
        .\word_aligned_data_r_reg[7] (ufc_filter_i_n_13));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_LL_DEFRAMER" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_DEFRAMER
   (mux_select_c,
    \AFTER_SCP_Buffer_reg[0]_0 ,
    \AFTER_SCP_Buffer_reg[0]_1 ,
    \AFTER_SCP_Buffer_reg[0]_2 ,
    \DEFRAMED_DATA_V_Buffer_reg[1]_0 ,
    \stage_1_ecp_r_reg[0] ,
    \IN_FRAME_Buffer_reg[1]_0 ,
    D,
    in_frame_r_reg_0,
    S1_in,
    \AFTER_SCP_Buffer_reg[1]_0 ,
    RESET,
    user_clk,
    Q,
    stage_2_frame_err_r_reg,
    \DEFRAMED_DATA_V_Buffer_reg[0]_0 );
  output [0:0]mux_select_c;
  output \AFTER_SCP_Buffer_reg[0]_0 ;
  output \AFTER_SCP_Buffer_reg[0]_1 ;
  output \AFTER_SCP_Buffer_reg[0]_2 ;
  output [1:0]\DEFRAMED_DATA_V_Buffer_reg[1]_0 ;
  output \stage_1_ecp_r_reg[0] ;
  input \IN_FRAME_Buffer_reg[1]_0 ;
  input [1:0]D;
  input in_frame_r_reg_0;
  input S1_in;
  input \AFTER_SCP_Buffer_reg[1]_0 ;
  input RESET;
  input user_clk;
  input [1:0]Q;
  input [1:0]stage_2_frame_err_r_reg;
  input [1:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;

  wire \AFTER_SCP_Buffer_reg[0]_0 ;
  wire \AFTER_SCP_Buffer_reg[0]_1 ;
  wire \AFTER_SCP_Buffer_reg[0]_2 ;
  wire \AFTER_SCP_Buffer_reg[1]_0 ;
  wire CI;
  wire [1:0]D;
  wire \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ;
  wire \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ;
  wire [1:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;
  wire [1:0]\DEFRAMED_DATA_V_Buffer_reg[1]_0 ;
  wire \IN_FRAME_Buffer_reg[1]_0 ;
  wire [1:0]Q;
  wire RESET;
  wire S1_in;
  wire after_scp_c_1;
  wire data_after_start_muxcy_1_n_0;
  wire in_frame_c_0;
  wire in_frame_c_1;
  wire in_frame_r_reg_0;
  wire [0:0]mux_select_c;
  wire [0:1]stage_1_after_scp_r;
  wire [0:1]stage_1_data_v_r;
  wire \stage_1_ecp_r_reg[0] ;
  wire [0:1]stage_1_in_frame_r;
  wire [1:0]stage_2_frame_err_r_reg;
  wire user_clk;
  wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED;
  wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED;
  wire [3:0]NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED;
  wire [3:2]NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED;
  wire [3:2]NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED;
  wire [3:2]NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED;
  wire [3:0]NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED;
  wire [3:2]NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED;

  FDRE \AFTER_SCP_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(after_scp_c_1),
        .Q(stage_1_after_scp_r[0]),
        .R(RESET));
  FDRE \AFTER_SCP_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(data_after_start_muxcy_1_n_0),
        .Q(stage_1_after_scp_r[1]),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \COUNT_Buffer[0]_i_1 
       (.I0(stage_1_data_v_r[1]),
        .I1(stage_1_data_v_r[0]),
        .O(\DEFRAMED_DATA_V_Buffer_reg[1]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \COUNT_Buffer[1]_i_1 
       (.I0(stage_1_data_v_r[0]),
        .I1(stage_1_data_v_r[1]),
        .O(\DEFRAMED_DATA_V_Buffer_reg[1]_0 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    \DEFRAMED_DATA_V_Buffer[0]_i_1 
       (.I0(in_frame_c_1),
        .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [1]),
        .O(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \DEFRAMED_DATA_V_Buffer[1]_i_1 
       (.I0(in_frame_c_0),
        .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [0]),
        .O(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ));
  FDRE \DEFRAMED_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ),
        .Q(stage_1_data_v_r[0]),
        .R(RESET));
  FDRE \DEFRAMED_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ),
        .Q(stage_1_data_v_r[1]),
        .R(RESET));
  FDRE \IN_FRAME_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(CI),
        .Q(stage_1_in_frame_r[0]),
        .R(RESET));
  FDRE \IN_FRAME_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(in_frame_c_1),
        .Q(stage_1_in_frame_r[1]),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \MUX_SELECT_Buffer[2]_i_1 
       (.I0(stage_1_data_v_r[1]),
        .I1(stage_1_data_v_r[0]),
        .O(mux_select_c));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  CARRY4 data_after_start_muxcy_0_CARRY4
       (.CI(1'b0),
        .CO({NLW_data_after_start_muxcy_0_CARRY4_CO_UNCONNECTED[3:2],data_after_start_muxcy_1_n_0,after_scp_c_1}),
        .CYINIT(1'b0),
        .DI({NLW_data_after_start_muxcy_0_CARRY4_DI_UNCONNECTED[3:2],1'b1,1'b1}),
        .O(NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
        .S({NLW_data_after_start_muxcy_0_CARRY4_S_UNCONNECTED[3:2],\AFTER_SCP_Buffer_reg[1]_0 ,S1_in}));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  CARRY4 in_frame_muxcy_0_CARRY4
       (.CI(1'b0),
        .CO({NLW_in_frame_muxcy_0_CARRY4_CO_UNCONNECTED[3:2],in_frame_c_0,in_frame_c_1}),
        .CYINIT(CI),
        .DI({NLW_in_frame_muxcy_0_CARRY4_DI_UNCONNECTED[3:2],D[0],D[1]}),
        .O(NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
        .S({NLW_in_frame_muxcy_0_CARRY4_S_UNCONNECTED[3:2],in_frame_r_reg_0,\IN_FRAME_Buffer_reg[1]_0 }));
  FDRE in_frame_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(in_frame_c_0),
        .Q(CI),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    stage_2_end_after_start_r_i_1
       (.I0(stage_1_after_scp_r[0]),
        .I1(Q[1]),
        .I2(stage_1_after_scp_r[1]),
        .I3(Q[0]),
        .O(\AFTER_SCP_Buffer_reg[0]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'h4F44)) 
    stage_2_end_before_start_r_i_1
       (.I0(stage_1_after_scp_r[0]),
        .I1(Q[1]),
        .I2(stage_1_after_scp_r[1]),
        .I3(Q[0]),
        .O(\AFTER_SCP_Buffer_reg[0]_1 ));
  LUT6 #(
    .INIT(64'hFFFFF0AAFCEEFCEE)) 
    stage_2_frame_err_r_i_1
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(stage_2_frame_err_r_reg[1]),
        .I3(stage_1_in_frame_r[0]),
        .I4(stage_2_frame_err_r_reg[0]),
        .I5(stage_1_in_frame_r[1]),
        .O(\stage_1_ecp_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    stage_2_start_with_data_r_i_1
       (.I0(stage_1_after_scp_r[0]),
        .I1(stage_1_data_v_r[0]),
        .I2(stage_1_after_scp_r[1]),
        .I3(stage_1_data_v_r[1]),
        .O(\AFTER_SCP_Buffer_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_PDU_DATAPATH
   (rx_eof,
    FRAME_ERR,
    M_AXI_RX_TLAST,
    M_AXI_RX_TVALID,
    \RX_REM_Buffer_reg[0]_0 ,
    M_AXI_RX_TDATA,
    \IN_FRAME_Buffer_reg[1] ,
    D,
    in_frame_r_reg,
    S1_in,
    \AFTER_SCP_Buffer_reg[1] ,
    user_clk,
    RESET,
    stage_1_pad_r_reg_0,
    START_RX,
    Q,
    \stage_1_ecp_r_reg[0]_0 ,
    \stage_2_data_r_reg[0]_0 );
  output rx_eof;
  output FRAME_ERR;
  output M_AXI_RX_TLAST;
  output M_AXI_RX_TVALID;
  output [1:0]\RX_REM_Buffer_reg[0]_0 ;
  output [31:0]M_AXI_RX_TDATA;
  input \IN_FRAME_Buffer_reg[1] ;
  input [1:0]D;
  input in_frame_r_reg;
  input S1_in;
  input \AFTER_SCP_Buffer_reg[1] ;
  input user_clk;
  input RESET;
  input stage_1_pad_r_reg_0;
  input START_RX;
  input [1:0]Q;
  input [1:0]\stage_1_ecp_r_reg[0]_0 ;
  input [31:0]\stage_2_data_r_reg[0]_0 ;

  wire \AFTER_SCP_Buffer_reg[1] ;
  wire [1:0]D;
  wire EOF_N_Buffer;
  wire FRAME_ERR;
  wire FRAME_ERR_RESULT_Buffer;
  wire FRAME_ERR_RESULT_Buffer0;
  wire \IN_FRAME_Buffer_reg[1] ;
  wire [2:2]MUX_SELECT;
  wire [31:0]M_AXI_RX_TDATA;
  wire M_AXI_RX_TLAST;
  wire M_AXI_RX_TVALID;
  wire OUTPUT_SELECT_Buffer;
  wire [1:0]Q;
  wire RESET;
  wire [0:1]RX_REM_Buffer;
  wire [1:0]\RX_REM_Buffer_reg[0]_0 ;
  wire RX_SRC_RDY_N_Buffer;
  wire S1_in;
  wire SRC_RDY_N_Buffer;
  wire START_RX;
  wire [0:31]STORAGE_DATA;
  wire [4:9]STORAGE_SELECT_Buffer;
  wire [0:1]ce_command_c;
  wire end_storage_r0;
  wire in_frame_r_reg;
  wire [2:2]mux_select_c;
  wire [9:9]output_select_c;
  wire p_0_in0;
  wire [15:0]p_1_in;
  wire rx_eof;
  wire sideband_output_i_n_1;
  wire sideband_output_i_n_5;
  wire [0:1]stage_1_ecp_r;
  wire [1:0]\stage_1_ecp_r_reg[0]_0 ;
  wire stage_1_pad_r;
  wire stage_1_pad_r_reg_0;
  wire stage_1_rx_ll_deframer_i_n_1;
  wire stage_1_rx_ll_deframer_i_n_2;
  wire stage_1_rx_ll_deframer_i_n_3;
  wire stage_1_rx_ll_deframer_i_n_4;
  wire stage_1_rx_ll_deframer_i_n_5;
  wire stage_1_rx_ll_deframer_i_n_6;
  wire [0:1]stage_1_scp_r;
  wire [0:31]stage_2_data_r;
  wire [31:0]\stage_2_data_r_reg[0]_0 ;
  wire [1:1]stage_2_data_v_count_r;
  wire stage_2_end_after_start_r;
  wire stage_2_end_before_start_r;
  wire stage_2_frame_err_r;
  wire stage_2_pad_r;
  wire stage_2_start_with_data_r;
  wire stage_2_valid_data_counter_i_n_3;
  wire stage_3_end_storage_r;
  wire stage_3_left_align_datapath_mux_i_n_16;
  wire stage_3_left_align_datapath_mux_i_n_17;
  wire stage_3_left_align_datapath_mux_i_n_18;
  wire stage_3_left_align_datapath_mux_i_n_19;
  wire stage_3_left_align_datapath_mux_i_n_20;
  wire stage_3_left_align_datapath_mux_i_n_21;
  wire stage_3_left_align_datapath_mux_i_n_22;
  wire stage_3_left_align_datapath_mux_i_n_23;
  wire stage_3_left_align_datapath_mux_i_n_24;
  wire stage_3_left_align_datapath_mux_i_n_25;
  wire stage_3_left_align_datapath_mux_i_n_26;
  wire stage_3_left_align_datapath_mux_i_n_27;
  wire stage_3_left_align_datapath_mux_i_n_28;
  wire stage_3_left_align_datapath_mux_i_n_29;
  wire stage_3_left_align_datapath_mux_i_n_30;
  wire stage_3_left_align_datapath_mux_i_n_31;
  wire stage_3_left_align_datapath_mux_i_n_32;
  wire stage_3_left_align_datapath_mux_i_n_33;
  wire stage_3_left_align_datapath_mux_i_n_34;
  wire stage_3_left_align_datapath_mux_i_n_35;
  wire stage_3_left_align_datapath_mux_i_n_36;
  wire stage_3_left_align_datapath_mux_i_n_37;
  wire stage_3_left_align_datapath_mux_i_n_38;
  wire stage_3_left_align_datapath_mux_i_n_39;
  wire stage_3_left_align_datapath_mux_i_n_40;
  wire stage_3_left_align_datapath_mux_i_n_41;
  wire stage_3_left_align_datapath_mux_i_n_42;
  wire stage_3_left_align_datapath_mux_i_n_43;
  wire stage_3_left_align_datapath_mux_i_n_44;
  wire stage_3_left_align_datapath_mux_i_n_45;
  wire stage_3_left_align_datapath_mux_i_n_46;
  wire stage_3_left_align_datapath_mux_i_n_47;
  wire stage_3_storage_ce_control_i_n_1;
  wire stage_3_storage_count_control_i_n_4;
  wire [0:1]stage_3_storage_count_r;
  wire std_bool2_in;
  wire std_bool6_in;
  wire user_clk;

  FDRE FRAME_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(FRAME_ERR_RESULT_Buffer),
        .Q(FRAME_ERR),
        .R(RESET));
  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_RX_TLAST_INST_0
       (.I0(rx_eof),
        .O(M_AXI_RX_TLAST));
  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_RX_TVALID_INST_0
       (.I0(RX_SRC_RDY_N_Buffer),
        .O(M_AXI_RX_TVALID));
  FDRE RX_EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(EOF_N_Buffer),
        .Q(rx_eof),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_REM_Buffer[0]),
        .Q(\RX_REM_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_REM_Buffer[1]),
        .Q(\RX_REM_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDSE RX_SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(SRC_RDY_N_Buffer),
        .Q(RX_SRC_RDY_N_Buffer),
        .S(RESET));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_MUX output_mux_i
       (.M_AXI_RX_TDATA(M_AXI_RX_TDATA),
        .\OUTPUT_DATA_Buffer_reg[16]_0 (p_1_in),
        .OUTPUT_SELECT_Buffer(OUTPUT_SELECT_Buffer),
        .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31]}),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SIDEBAND_OUTPUT sideband_output_i
       (.D(sideband_output_i_n_5),
        .EOF_N_Buffer(EOF_N_Buffer),
        .EOF_N_Buffer_reg_0(stage_3_storage_count_control_i_n_4),
        .FRAME_ERR_RESULT_Buffer(FRAME_ERR_RESULT_Buffer),
        .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
        .Q(stage_3_storage_count_r[1]),
        .\RX_REM_Buffer_reg[0]_0 ({RX_REM_Buffer[0],RX_REM_Buffer[1]}),
        .\RX_REM_Buffer_reg[0]_1 (stage_2_data_v_count_r),
        .SR(sideband_output_i_n_1),
        .SRC_RDY_N_Buffer(SRC_RDY_N_Buffer),
        .START_RX(START_RX),
        .end_storage_r0(end_storage_r0),
        .stage_2_end_before_start_r(stage_2_end_before_start_r),
        .stage_2_frame_err_r(stage_2_frame_err_r),
        .stage_2_pad_r(stage_2_pad_r),
        .stage_2_start_with_data_r(stage_2_start_with_data_r),
        .stage_3_end_storage_r(stage_3_end_storage_r),
        .std_bool6_in(std_bool6_in),
        .user_clk(user_clk));
  FDRE \stage_1_ecp_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_ecp_r_reg[0]_0 [1]),
        .Q(stage_1_ecp_r[0]),
        .R(1'b0));
  FDRE \stage_1_ecp_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_ecp_r_reg[0]_0 [0]),
        .Q(stage_1_ecp_r[1]),
        .R(1'b0));
  FDRE stage_1_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_pad_r_reg_0),
        .Q(stage_1_pad_r),
        .R(1'b0));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_DEFRAMER stage_1_rx_ll_deframer_i
       (.\AFTER_SCP_Buffer_reg[0]_0 (stage_1_rx_ll_deframer_i_n_1),
        .\AFTER_SCP_Buffer_reg[0]_1 (stage_1_rx_ll_deframer_i_n_2),
        .\AFTER_SCP_Buffer_reg[0]_2 (stage_1_rx_ll_deframer_i_n_3),
        .\AFTER_SCP_Buffer_reg[1]_0 (\AFTER_SCP_Buffer_reg[1] ),
        .D(D),
        .\DEFRAMED_DATA_V_Buffer_reg[0]_0 (Q),
        .\DEFRAMED_DATA_V_Buffer_reg[1]_0 ({stage_1_rx_ll_deframer_i_n_4,stage_1_rx_ll_deframer_i_n_5}),
        .\IN_FRAME_Buffer_reg[1]_0 (\IN_FRAME_Buffer_reg[1] ),
        .Q({stage_1_ecp_r[0],stage_1_ecp_r[1]}),
        .RESET(RESET),
        .S1_in(S1_in),
        .in_frame_r_reg_0(in_frame_r_reg),
        .mux_select_c(mux_select_c),
        .\stage_1_ecp_r_reg[0] (stage_1_rx_ll_deframer_i_n_6),
        .stage_2_frame_err_r_reg({stage_1_scp_r[0],stage_1_scp_r[1]}),
        .user_clk(user_clk));
  FDRE \stage_1_scp_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(stage_1_scp_r[0]),
        .R(1'b0));
  FDRE \stage_1_scp_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(stage_1_scp_r[1]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [31]),
        .Q(stage_2_data_r[0]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [21]),
        .Q(stage_2_data_r[10]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [20]),
        .Q(stage_2_data_r[11]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [19]),
        .Q(stage_2_data_r[12]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [18]),
        .Q(stage_2_data_r[13]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [17]),
        .Q(stage_2_data_r[14]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [16]),
        .Q(stage_2_data_r[15]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [15]),
        .Q(stage_2_data_r[16]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [14]),
        .Q(stage_2_data_r[17]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [13]),
        .Q(stage_2_data_r[18]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [12]),
        .Q(stage_2_data_r[19]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [30]),
        .Q(stage_2_data_r[1]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [11]),
        .Q(stage_2_data_r[20]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [10]),
        .Q(stage_2_data_r[21]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [9]),
        .Q(stage_2_data_r[22]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [8]),
        .Q(stage_2_data_r[23]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [7]),
        .Q(stage_2_data_r[24]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [6]),
        .Q(stage_2_data_r[25]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [5]),
        .Q(stage_2_data_r[26]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [4]),
        .Q(stage_2_data_r[27]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [3]),
        .Q(stage_2_data_r[28]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [2]),
        .Q(stage_2_data_r[29]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [29]),
        .Q(stage_2_data_r[2]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [1]),
        .Q(stage_2_data_r[30]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [0]),
        .Q(stage_2_data_r[31]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [28]),
        .Q(stage_2_data_r[3]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [27]),
        .Q(stage_2_data_r[4]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [26]),
        .Q(stage_2_data_r[5]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [25]),
        .Q(stage_2_data_r[6]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [24]),
        .Q(stage_2_data_r[7]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [23]),
        .Q(stage_2_data_r[8]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [22]),
        .Q(stage_2_data_r[9]),
        .R(1'b0));
  FDRE stage_2_end_after_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_rx_ll_deframer_i_n_3),
        .Q(stage_2_end_after_start_r),
        .R(RESET));
  FDRE stage_2_end_before_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_rx_ll_deframer_i_n_2),
        .Q(stage_2_end_before_start_r),
        .R(RESET));
  FDRE stage_2_frame_err_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_rx_ll_deframer_i_n_6),
        .Q(stage_2_frame_err_r),
        .R(RESET));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_CONTROL stage_2_left_align_control_i
       (.MUX_SELECT(MUX_SELECT),
        .mux_select_c(mux_select_c),
        .user_clk(user_clk));
  FDRE stage_2_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_pad_r),
        .Q(stage_2_pad_r),
        .R(1'b0));
  FDRE stage_2_start_with_data_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_rx_ll_deframer_i_n_1),
        .Q(stage_2_start_with_data_r),
        .R(RESET));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15 stage_2_valid_data_counter_i
       (.\COUNT_Buffer_reg[0]_0 ({stage_1_rx_ll_deframer_i_n_4,stage_1_rx_ll_deframer_i_n_5}),
        .D({ce_command_c[0],ce_command_c[1]}),
        .Q(stage_2_data_v_count_r),
        .RESET(RESET),
        .\STORAGE_CE_Buffer_reg[0] ({stage_3_storage_count_r[0],stage_3_storage_count_r[1]}),
        .end_storage_r0(end_storage_r0),
        .end_storage_r_reg(stage_2_valid_data_counter_i_n_3),
        .stage_2_end_after_start_r(stage_2_end_after_start_r),
        .stage_2_end_before_start_r(stage_2_end_before_start_r),
        .stage_2_start_with_data_r(stage_2_start_with_data_r),
        .stage_3_end_storage_r(stage_3_end_storage_r),
        .std_bool2_in(std_bool2_in),
        .std_bool6_in(std_bool6_in),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LEFT_ALIGN_MUX stage_3_left_align_datapath_mux_i
       (.D({stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,stage_3_left_align_datapath_mux_i_n_32,stage_3_left_align_datapath_mux_i_n_33,stage_3_left_align_datapath_mux_i_n_34,stage_3_left_align_datapath_mux_i_n_35,stage_3_left_align_datapath_mux_i_n_36,stage_3_left_align_datapath_mux_i_n_37,stage_3_left_align_datapath_mux_i_n_38,stage_3_left_align_datapath_mux_i_n_39,stage_3_left_align_datapath_mux_i_n_40,stage_3_left_align_datapath_mux_i_n_41,stage_3_left_align_datapath_mux_i_n_42,stage_3_left_align_datapath_mux_i_n_43,stage_3_left_align_datapath_mux_i_n_44,stage_3_left_align_datapath_mux_i_n_45,stage_3_left_align_datapath_mux_i_n_46,stage_3_left_align_datapath_mux_i_n_47}),
        .\MUXED_DATA_Buffer_reg[0]_0 (p_1_in),
        .MUX_SELECT(MUX_SELECT),
        .Q({stage_2_data_r[0],stage_2_data_r[1],stage_2_data_r[2],stage_2_data_r[3],stage_2_data_r[4],stage_2_data_r[5],stage_2_data_r[6],stage_2_data_r[7],stage_2_data_r[8],stage_2_data_r[9],stage_2_data_r[10],stage_2_data_r[11],stage_2_data_r[12],stage_2_data_r[13],stage_2_data_r[14],stage_2_data_r[15],stage_2_data_r[16],stage_2_data_r[17],stage_2_data_r[18],stage_2_data_r[19],stage_2_data_r[20],stage_2_data_r[21],stage_2_data_r[22],stage_2_data_r[23],stage_2_data_r[24],stage_2_data_r[25],stage_2_data_r[26],stage_2_data_r[27],stage_2_data_r[28],stage_2_data_r[29],stage_2_data_r[30],stage_2_data_r[31]}),
        .STORAGE_SELECT_Buffer({STORAGE_SELECT_Buffer[4],STORAGE_SELECT_Buffer[9]}),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_OUTPUT_SWITCH_CONTROL stage_3_output_switch_control_i
       (.OUTPUT_SELECT_Buffer(OUTPUT_SELECT_Buffer),
        .output_select_c(output_select_c),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_CE_CONTROL stage_3_storage_ce_control_i
       (.D({ce_command_c[0],ce_command_c[1]}),
        .Q({p_0_in0,stage_3_storage_ce_control_i_n_1}),
        .RESET(RESET),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL stage_3_storage_count_control_i
       (.D({stage_2_valid_data_counter_i_n_3,sideband_output_i_n_5}),
        .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
        .Q({stage_3_storage_count_r[0],stage_3_storage_count_r[1]}),
        .SR(sideband_output_i_n_1),
        .end_storage_r_reg(stage_3_storage_count_control_i_n_4),
        .output_select_c(output_select_c),
        .stage_2_end_after_start_r(stage_2_end_after_start_r),
        .stage_2_end_before_start_r(stage_2_end_before_start_r),
        .stage_2_frame_err_r(stage_2_frame_err_r),
        .stage_2_start_with_data_r(stage_2_start_with_data_r),
        .stage_3_end_storage_r(stage_3_end_storage_r),
        .std_bool2_in(std_bool2_in),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL stage_3_storage_switch_control_i
       (.Q(stage_3_storage_count_r[1]),
        .STORAGE_SELECT_Buffer({STORAGE_SELECT_Buffer[4],STORAGE_SELECT_Buffer[9]}),
        .stage_2_start_with_data_r(stage_2_start_with_data_r),
        .stage_3_end_storage_r(stage_3_end_storage_r),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_MUX stage_4_storage_mux_i
       (.D({stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,stage_3_left_align_datapath_mux_i_n_32,stage_3_left_align_datapath_mux_i_n_33,stage_3_left_align_datapath_mux_i_n_34,stage_3_left_align_datapath_mux_i_n_35,stage_3_left_align_datapath_mux_i_n_36,stage_3_left_align_datapath_mux_i_n_37,stage_3_left_align_datapath_mux_i_n_38,stage_3_left_align_datapath_mux_i_n_39,stage_3_left_align_datapath_mux_i_n_40,stage_3_left_align_datapath_mux_i_n_41,stage_3_left_align_datapath_mux_i_n_42,stage_3_left_align_datapath_mux_i_n_43,stage_3_left_align_datapath_mux_i_n_44,stage_3_left_align_datapath_mux_i_n_45,stage_3_left_align_datapath_mux_i_n_46,stage_3_left_align_datapath_mux_i_n_47}),
        .E({p_0_in0,stage_3_storage_ce_control_i_n_1}),
        .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31]}),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL_UFC_DATAPATH
   (\stage_1_data_r_reg[0]_0 ,
    M_AXI_UFC_RX_TVALID,
    M_AXI_UFC_RX_TDATA,
    M_AXI_UFC_RX_TKEEP,
    M_AXI_UFC_RX_TLAST,
    user_clk,
    RESET,
    UFC_START,
    barrel_shifter_control_i,
    \stage_1_data_r_reg[0]_1 ,
    \stage_1_data_r_reg[1]_0 ,
    \stage_1_data_r_reg[2]_0 ,
    \stage_1_data_r_reg[3]_0 ,
    \stage_1_data_r_reg[4]_0 ,
    \stage_1_data_r_reg[5]_0 ,
    \stage_1_data_r_reg[6]_0 ,
    \stage_1_data_r_reg[7]_0 ,
    \stage_1_data_r_reg[8]_0 ,
    \stage_1_data_r_reg[9]_0 ,
    \stage_1_data_r_reg[10]_0 ,
    \stage_1_data_r_reg[11]_0 ,
    \stage_1_data_r_reg[12]_0 ,
    \stage_1_data_r_reg[13]_0 ,
    \stage_1_data_r_reg[14]_0 ,
    \stage_1_data_r_reg[15]_0 ,
    \stage_1_data_r_reg[16]_0 ,
    \stage_1_data_r_reg[17]_0 ,
    \stage_1_data_r_reg[18]_0 ,
    \stage_1_data_r_reg[19]_0 ,
    \stage_1_data_r_reg[20]_0 ,
    \stage_1_data_r_reg[21]_0 ,
    \stage_1_data_r_reg[22]_0 ,
    \stage_1_data_r_reg[23]_0 ,
    \stage_1_data_r_reg[24]_0 ,
    \stage_1_data_r_reg[25]_0 ,
    \stage_1_data_r_reg[26]_0 ,
    \stage_1_data_r_reg[27]_0 ,
    \stage_1_data_r_reg[28]_0 ,
    \stage_1_data_r_reg[29]_0 ,
    \stage_1_data_r_reg[30]_0 ,
    \stage_1_data_r_reg[31]_0 ,
    Q);
  output [31:0]\stage_1_data_r_reg[0]_0 ;
  output M_AXI_UFC_RX_TVALID;
  output [31:0]M_AXI_UFC_RX_TDATA;
  output [0:0]M_AXI_UFC_RX_TKEEP;
  output M_AXI_UFC_RX_TLAST;
  input user_clk;
  input RESET;
  input UFC_START;
  input barrel_shifter_control_i;
  input \stage_1_data_r_reg[0]_1 ;
  input \stage_1_data_r_reg[1]_0 ;
  input \stage_1_data_r_reg[2]_0 ;
  input \stage_1_data_r_reg[3]_0 ;
  input \stage_1_data_r_reg[4]_0 ;
  input \stage_1_data_r_reg[5]_0 ;
  input \stage_1_data_r_reg[6]_0 ;
  input \stage_1_data_r_reg[7]_0 ;
  input \stage_1_data_r_reg[8]_0 ;
  input \stage_1_data_r_reg[9]_0 ;
  input \stage_1_data_r_reg[10]_0 ;
  input \stage_1_data_r_reg[11]_0 ;
  input \stage_1_data_r_reg[12]_0 ;
  input \stage_1_data_r_reg[13]_0 ;
  input \stage_1_data_r_reg[14]_0 ;
  input \stage_1_data_r_reg[15]_0 ;
  input \stage_1_data_r_reg[16]_0 ;
  input \stage_1_data_r_reg[17]_0 ;
  input \stage_1_data_r_reg[18]_0 ;
  input \stage_1_data_r_reg[19]_0 ;
  input \stage_1_data_r_reg[20]_0 ;
  input \stage_1_data_r_reg[21]_0 ;
  input \stage_1_data_r_reg[22]_0 ;
  input \stage_1_data_r_reg[23]_0 ;
  input \stage_1_data_r_reg[24]_0 ;
  input \stage_1_data_r_reg[25]_0 ;
  input \stage_1_data_r_reg[26]_0 ;
  input \stage_1_data_r_reg[27]_0 ;
  input \stage_1_data_r_reg[28]_0 ;
  input \stage_1_data_r_reg[29]_0 ;
  input \stage_1_data_r_reg[30]_0 ;
  input \stage_1_data_r_reg[31]_0 ;
  input [1:0]Q;

  wire BARREL_SHIFTER_CONTROL_Buffer;
  wire [31:0]M_AXI_UFC_RX_TDATA;
  wire [0:0]M_AXI_UFC_RX_TKEEP;
  wire M_AXI_UFC_RX_TLAST;
  wire M_AXI_UFC_RX_TVALID;
  wire [1:0]Q;
  wire RESET;
  wire [0:31]SHIFTED_DATA_Buffer;
  wire UFC_EOF_N_Buffer;
  wire [1:0]UFC_OUTPUT_SELECT_Buffer;
  wire [0:0]UFC_RX_REM_Buffer;
  wire UFC_RX_SRC_RDY_N_Buffer;
  wire UFC_SRC_RDY_N_Buffer;
  wire UFC_START;
  wire [2:5]UFC_STORAGE_SELECT_Buffer;
  wire [0:1]barrel_shifted_count_r;
  wire barrel_shifter_control_i;
  wire rx_ufc_eof;
  wire [31:0]\stage_1_data_r_reg[0]_0 ;
  wire \stage_1_data_r_reg[0]_1 ;
  wire \stage_1_data_r_reg[10]_0 ;
  wire \stage_1_data_r_reg[11]_0 ;
  wire \stage_1_data_r_reg[12]_0 ;
  wire \stage_1_data_r_reg[13]_0 ;
  wire \stage_1_data_r_reg[14]_0 ;
  wire \stage_1_data_r_reg[15]_0 ;
  wire \stage_1_data_r_reg[16]_0 ;
  wire \stage_1_data_r_reg[17]_0 ;
  wire \stage_1_data_r_reg[18]_0 ;
  wire \stage_1_data_r_reg[19]_0 ;
  wire \stage_1_data_r_reg[1]_0 ;
  wire \stage_1_data_r_reg[20]_0 ;
  wire \stage_1_data_r_reg[21]_0 ;
  wire \stage_1_data_r_reg[22]_0 ;
  wire \stage_1_data_r_reg[23]_0 ;
  wire \stage_1_data_r_reg[24]_0 ;
  wire \stage_1_data_r_reg[25]_0 ;
  wire \stage_1_data_r_reg[26]_0 ;
  wire \stage_1_data_r_reg[27]_0 ;
  wire \stage_1_data_r_reg[28]_0 ;
  wire \stage_1_data_r_reg[29]_0 ;
  wire \stage_1_data_r_reg[2]_0 ;
  wire \stage_1_data_r_reg[30]_0 ;
  wire \stage_1_data_r_reg[31]_0 ;
  wire \stage_1_data_r_reg[3]_0 ;
  wire \stage_1_data_r_reg[4]_0 ;
  wire \stage_1_data_r_reg[5]_0 ;
  wire \stage_1_data_r_reg[6]_0 ;
  wire \stage_1_data_r_reg[7]_0 ;
  wire \stage_1_data_r_reg[8]_0 ;
  wire \stage_1_data_r_reg[9]_0 ;
  wire stage_1_ufc_start_r;
  wire [1:1]storage_count_2x_c;
  wire ufc_barrel_shifter_i_n_32;
  wire ufc_barrel_shifter_i_n_33;
  wire ufc_barrel_shifter_i_n_34;
  wire ufc_barrel_shifter_i_n_35;
  wire ufc_barrel_shifter_i_n_36;
  wire ufc_barrel_shifter_i_n_37;
  wire ufc_barrel_shifter_i_n_38;
  wire ufc_barrel_shifter_i_n_39;
  wire ufc_barrel_shifter_i_n_40;
  wire ufc_barrel_shifter_i_n_41;
  wire ufc_barrel_shifter_i_n_42;
  wire ufc_barrel_shifter_i_n_43;
  wire ufc_barrel_shifter_i_n_44;
  wire ufc_barrel_shifter_i_n_45;
  wire ufc_barrel_shifter_i_n_46;
  wire ufc_barrel_shifter_i_n_47;
  wire ufc_sideband_output_i_n_0;
  wire ufc_storage_count_control_i_n_0;
  wire ufc_storage_count_control_i_n_1;
  wire ufc_storage_count_control_i_n_3;
  wire ufc_storage_count_control_i_n_4;
  wire ufc_storage_count_control_i_n_5;
  wire ufc_storage_count_control_i_n_6;
  wire ufc_storage_count_control_i_n_7;
  wire ufc_storage_mux_i_n_0;
  wire ufc_storage_mux_i_n_1;
  wire ufc_storage_mux_i_n_10;
  wire ufc_storage_mux_i_n_11;
  wire ufc_storage_mux_i_n_12;
  wire ufc_storage_mux_i_n_13;
  wire ufc_storage_mux_i_n_14;
  wire ufc_storage_mux_i_n_15;
  wire ufc_storage_mux_i_n_16;
  wire ufc_storage_mux_i_n_17;
  wire ufc_storage_mux_i_n_18;
  wire ufc_storage_mux_i_n_19;
  wire ufc_storage_mux_i_n_2;
  wire ufc_storage_mux_i_n_20;
  wire ufc_storage_mux_i_n_21;
  wire ufc_storage_mux_i_n_22;
  wire ufc_storage_mux_i_n_23;
  wire ufc_storage_mux_i_n_24;
  wire ufc_storage_mux_i_n_25;
  wire ufc_storage_mux_i_n_26;
  wire ufc_storage_mux_i_n_27;
  wire ufc_storage_mux_i_n_28;
  wire ufc_storage_mux_i_n_29;
  wire ufc_storage_mux_i_n_3;
  wire ufc_storage_mux_i_n_30;
  wire ufc_storage_mux_i_n_31;
  wire ufc_storage_mux_i_n_4;
  wire ufc_storage_mux_i_n_5;
  wire ufc_storage_mux_i_n_6;
  wire ufc_storage_mux_i_n_7;
  wire ufc_storage_mux_i_n_8;
  wire ufc_storage_mux_i_n_9;
  wire \ufc_storage_switch_control_i/_n_0 ;
  wire ufc_storage_switch_control_i_n_0;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \M_AXI_UFC_RX_TKEEP[2]_INST_0 
       (.I0(rx_ufc_eof),
        .I1(UFC_RX_REM_Buffer),
        .O(M_AXI_UFC_RX_TKEEP));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_UFC_RX_TLAST_INST_0
       (.I0(rx_ufc_eof),
        .O(M_AXI_UFC_RX_TLAST));
  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_UFC_RX_TVALID_INST_0
       (.I0(UFC_RX_SRC_RDY_N_Buffer),
        .O(M_AXI_UFC_RX_TVALID));
  FDRE UFC_RX_EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_EOF_N_Buffer),
        .Q(rx_ufc_eof),
        .R(1'b0));
  FDRE \UFC_RX_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ufc_sideband_output_i_n_0),
        .Q(UFC_RX_REM_Buffer),
        .R(1'b0));
  FDSE UFC_RX_SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_SRC_RDY_N_Buffer),
        .Q(UFC_RX_SRC_RDY_N_Buffer),
        .S(RESET));
  FDRE \stage_1_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[0]_1 ),
        .Q(\stage_1_data_r_reg[0]_0 [31]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[10]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [21]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[11]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [20]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[12]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [19]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[13]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [18]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[14]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [17]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[15]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [16]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[16]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [15]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[17]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [14]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[18]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [13]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[19]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [12]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[1]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [30]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[20]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [11]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[21]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [10]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[22]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [9]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[23]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [8]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[24]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[25]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[26]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[27]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[28]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[29]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[2]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [29]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[30]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[31]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[3]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [28]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[4]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [27]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[5]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [26]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[6]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [25]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[7]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [24]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[8]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [23]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[9]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [22]),
        .R(1'b0));
  FDRE stage_1_ufc_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_START),
        .Q(stage_1_ufc_start_r),
        .R(RESET));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL ufc_barrel_shifter_control_i
       (.BARREL_SHIFTER_CONTROL_Buffer(BARREL_SHIFTER_CONTROL_Buffer),
        .barrel_shifter_control_i(barrel_shifter_control_i),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER ufc_barrel_shifter_i
       (.BARREL_SHIFTER_CONTROL_Buffer(BARREL_SHIFTER_CONTROL_Buffer),
        .\MUXED_DATA_Buffer_reg[16] (ufc_storage_mux_i_n_16),
        .\MUXED_DATA_Buffer_reg[17] (ufc_storage_mux_i_n_17),
        .\MUXED_DATA_Buffer_reg[18] (ufc_storage_mux_i_n_18),
        .\MUXED_DATA_Buffer_reg[19] (ufc_storage_mux_i_n_19),
        .\MUXED_DATA_Buffer_reg[20] (ufc_storage_mux_i_n_20),
        .\MUXED_DATA_Buffer_reg[21] (ufc_storage_mux_i_n_21),
        .\MUXED_DATA_Buffer_reg[22] (ufc_storage_mux_i_n_22),
        .\MUXED_DATA_Buffer_reg[23] (ufc_storage_mux_i_n_23),
        .\MUXED_DATA_Buffer_reg[24] (ufc_storage_mux_i_n_24),
        .\MUXED_DATA_Buffer_reg[25] (ufc_storage_mux_i_n_25),
        .\MUXED_DATA_Buffer_reg[26] (ufc_storage_mux_i_n_26),
        .\MUXED_DATA_Buffer_reg[27] (ufc_storage_mux_i_n_27),
        .\MUXED_DATA_Buffer_reg[28] (ufc_storage_mux_i_n_28),
        .\MUXED_DATA_Buffer_reg[29] (ufc_storage_mux_i_n_29),
        .\MUXED_DATA_Buffer_reg[30] (ufc_storage_mux_i_n_30),
        .\MUXED_DATA_Buffer_reg[31] (ufc_storage_mux_i_n_31),
        .SHIFTED_DATA_Buffer(SHIFTED_DATA_Buffer),
        .\SHIFTED_DATA_Buffer_reg[0]_0 (ufc_barrel_shifter_i_n_47),
        .\SHIFTED_DATA_Buffer_reg[0]_1 (\stage_1_data_r_reg[0]_0 ),
        .\SHIFTED_DATA_Buffer_reg[10]_0 (ufc_barrel_shifter_i_n_37),
        .\SHIFTED_DATA_Buffer_reg[11]_0 (ufc_barrel_shifter_i_n_36),
        .\SHIFTED_DATA_Buffer_reg[12]_0 (ufc_barrel_shifter_i_n_35),
        .\SHIFTED_DATA_Buffer_reg[13]_0 (ufc_barrel_shifter_i_n_34),
        .\SHIFTED_DATA_Buffer_reg[14]_0 (ufc_barrel_shifter_i_n_33),
        .\SHIFTED_DATA_Buffer_reg[15]_0 (ufc_barrel_shifter_i_n_32),
        .\SHIFTED_DATA_Buffer_reg[1]_0 (ufc_barrel_shifter_i_n_46),
        .\SHIFTED_DATA_Buffer_reg[2]_0 (ufc_barrel_shifter_i_n_45),
        .\SHIFTED_DATA_Buffer_reg[3]_0 (ufc_barrel_shifter_i_n_44),
        .\SHIFTED_DATA_Buffer_reg[4]_0 (ufc_barrel_shifter_i_n_43),
        .\SHIFTED_DATA_Buffer_reg[5]_0 (ufc_barrel_shifter_i_n_42),
        .\SHIFTED_DATA_Buffer_reg[6]_0 (ufc_barrel_shifter_i_n_41),
        .\SHIFTED_DATA_Buffer_reg[7]_0 (ufc_barrel_shifter_i_n_40),
        .\SHIFTED_DATA_Buffer_reg[8]_0 (ufc_barrel_shifter_i_n_39),
        .\SHIFTED_DATA_Buffer_reg[9]_0 (ufc_barrel_shifter_i_n_38),
        .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer[0]),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_MUX ufc_output_mux_i
       (.D({ufc_storage_mux_i_n_0,ufc_storage_mux_i_n_1,ufc_storage_mux_i_n_2,ufc_storage_mux_i_n_3,ufc_storage_mux_i_n_4,ufc_storage_mux_i_n_5,ufc_storage_mux_i_n_6,ufc_storage_mux_i_n_7,ufc_storage_mux_i_n_8,ufc_storage_mux_i_n_9,ufc_storage_mux_i_n_10,ufc_storage_mux_i_n_11,ufc_storage_mux_i_n_12,ufc_storage_mux_i_n_13,ufc_storage_mux_i_n_14,ufc_storage_mux_i_n_15}),
        .\MUXED_DATA_Buffer_reg[16]_0 (ufc_barrel_shifter_i_n_47),
        .\MUXED_DATA_Buffer_reg[17]_0 (ufc_barrel_shifter_i_n_46),
        .\MUXED_DATA_Buffer_reg[18]_0 (ufc_barrel_shifter_i_n_45),
        .\MUXED_DATA_Buffer_reg[19]_0 (ufc_barrel_shifter_i_n_44),
        .\MUXED_DATA_Buffer_reg[20]_0 (ufc_barrel_shifter_i_n_43),
        .\MUXED_DATA_Buffer_reg[21]_0 (ufc_barrel_shifter_i_n_42),
        .\MUXED_DATA_Buffer_reg[22]_0 (ufc_barrel_shifter_i_n_41),
        .\MUXED_DATA_Buffer_reg[23]_0 (ufc_barrel_shifter_i_n_40),
        .\MUXED_DATA_Buffer_reg[24]_0 (ufc_barrel_shifter_i_n_39),
        .\MUXED_DATA_Buffer_reg[25]_0 (ufc_barrel_shifter_i_n_38),
        .\MUXED_DATA_Buffer_reg[26]_0 (ufc_barrel_shifter_i_n_37),
        .\MUXED_DATA_Buffer_reg[27]_0 (ufc_barrel_shifter_i_n_36),
        .\MUXED_DATA_Buffer_reg[28]_0 (ufc_barrel_shifter_i_n_35),
        .\MUXED_DATA_Buffer_reg[29]_0 (ufc_barrel_shifter_i_n_34),
        .\MUXED_DATA_Buffer_reg[30]_0 (ufc_barrel_shifter_i_n_33),
        .\MUXED_DATA_Buffer_reg[31]_0 (ufc_barrel_shifter_i_n_32),
        .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
        .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer[1]),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL ufc_output_switch_control_i
       (.Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
        .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer),
        .\UFC_OUTPUT_SELECT_Buffer_reg[4]_0 (ufc_storage_count_control_i_n_6),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT ufc_sideband_output_i
       (.RESET(RESET),
        .UFC_EOF_N_Buffer(UFC_EOF_N_Buffer),
        .UFC_EOF_N_Buffer_reg_0(ufc_storage_count_control_i_n_0),
        .\UFC_REM_Buffer_reg[0]_0 (ufc_sideband_output_i_n_0),
        .\UFC_REM_Buffer_reg[0]_1 (ufc_storage_count_control_i_n_7),
        .UFC_SRC_RDY_N_Buffer(UFC_SRC_RDY_N_Buffer),
        .UFC_SRC_RDY_N_Buffer_reg_0(ufc_storage_count_control_i_n_6),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL ufc_storage_count_control_i
       (.D(ufc_storage_count_control_i_n_5),
        .Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
        .RESET(RESET),
        .UFC_EOF_N_Buffer_reg({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
        .stage_1_ufc_start_r(stage_1_ufc_start_r),
        .stage_1_ufc_start_r_reg(ufc_storage_count_control_i_n_0),
        .stage_1_ufc_start_r_reg_0(ufc_storage_count_control_i_n_7),
        .\storage_count_r_reg[0]_0 (ufc_storage_count_control_i_n_6),
        .\storage_count_r_reg[1]_0 (ufc_storage_count_control_i_n_3),
        .\storage_count_r_reg[1]_1 (ufc_storage_count_control_i_n_4),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_MUX ufc_storage_mux_i
       (.D({ufc_storage_mux_i_n_0,ufc_storage_mux_i_n_1,ufc_storage_mux_i_n_2,ufc_storage_mux_i_n_3,ufc_storage_mux_i_n_4,ufc_storage_mux_i_n_5,ufc_storage_mux_i_n_6,ufc_storage_mux_i_n_7,ufc_storage_mux_i_n_8,ufc_storage_mux_i_n_9,ufc_storage_mux_i_n_10,ufc_storage_mux_i_n_11,ufc_storage_mux_i_n_12,ufc_storage_mux_i_n_13,ufc_storage_mux_i_n_14,ufc_storage_mux_i_n_15}),
        .\MUXED_DATA_Buffer_reg[0]_0 (ufc_storage_switch_control_i_n_0),
        .\MUXED_DATA_Buffer_reg[16]_0 (ufc_storage_mux_i_n_16),
        .\MUXED_DATA_Buffer_reg[17]_0 (ufc_storage_mux_i_n_17),
        .\MUXED_DATA_Buffer_reg[18]_0 (ufc_storage_mux_i_n_18),
        .\MUXED_DATA_Buffer_reg[19]_0 (ufc_storage_mux_i_n_19),
        .\MUXED_DATA_Buffer_reg[20]_0 (ufc_storage_mux_i_n_20),
        .\MUXED_DATA_Buffer_reg[21]_0 (ufc_storage_mux_i_n_21),
        .\MUXED_DATA_Buffer_reg[22]_0 (ufc_storage_mux_i_n_22),
        .\MUXED_DATA_Buffer_reg[23]_0 (ufc_storage_mux_i_n_23),
        .\MUXED_DATA_Buffer_reg[24]_0 (ufc_storage_mux_i_n_24),
        .\MUXED_DATA_Buffer_reg[25]_0 (ufc_storage_mux_i_n_25),
        .\MUXED_DATA_Buffer_reg[26]_0 (ufc_storage_mux_i_n_26),
        .\MUXED_DATA_Buffer_reg[27]_0 (ufc_storage_mux_i_n_27),
        .\MUXED_DATA_Buffer_reg[28]_0 (ufc_storage_mux_i_n_28),
        .\MUXED_DATA_Buffer_reg[29]_0 (ufc_storage_mux_i_n_29),
        .\MUXED_DATA_Buffer_reg[30]_0 (ufc_storage_mux_i_n_30),
        .\MUXED_DATA_Buffer_reg[31]_0 (ufc_storage_mux_i_n_31),
        .SHIFTED_DATA_Buffer(SHIFTED_DATA_Buffer),
        .UFC_STORAGE_SELECT_Buffer({UFC_STORAGE_SELECT_Buffer[2],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[5]}),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL ufc_storage_switch_control_i
       (.D(ufc_storage_count_control_i_n_5),
        .Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
        .\UFC_STORAGE_SELECT_Buffer_reg[0]_0 (ufc_storage_switch_control_i_n_0),
        .\UFC_STORAGE_SELECT_Buffer_reg[0]_1 (ufc_storage_count_control_i_n_3),
        .\UFC_STORAGE_SELECT_Buffer_reg[1]_0 (ufc_storage_count_control_i_n_4),
        .\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ({UFC_STORAGE_SELECT_Buffer[2],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[5]}),
        .\UFC_STORAGE_SELECT_Buffer_reg[4]_0 (\ufc_storage_switch_control_i/_n_0 ),
        .\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
        .stage_1_ufc_start_r(stage_1_ufc_start_r),
        .user_clk(user_clk));
  LUT1 #(
    .INIT(2'h1)) 
    \ufc_storage_switch_control_i/ 
       (.I0(ufc_storage_count_control_i_n_1),
        .O(\ufc_storage_switch_control_i/_n_0 ));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER ufc_valid_data_counter
       (.\COUNT_Buffer_reg[0]_0 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1]}),
        .Q(Q),
        .RESET(RESET),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_SIDEBAND_OUTPUT" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SIDEBAND_OUTPUT
   (SRC_RDY_N_Buffer,
    SR,
    EOF_N_Buffer,
    stage_3_end_storage_r,
    FRAME_ERR_RESULT_Buffer,
    D,
    \RX_REM_Buffer_reg[0]_0 ,
    user_clk,
    EOF_N_Buffer_reg_0,
    end_storage_r0,
    FRAME_ERR_RESULT_Buffer0,
    stage_2_start_with_data_r,
    stage_2_pad_r,
    Q,
    \RX_REM_Buffer_reg[0]_1 ,
    std_bool6_in,
    stage_2_end_before_start_r,
    stage_2_frame_err_r,
    START_RX);
  output SRC_RDY_N_Buffer;
  output [0:0]SR;
  output EOF_N_Buffer;
  output stage_3_end_storage_r;
  output FRAME_ERR_RESULT_Buffer;
  output [0:0]D;
  output [1:0]\RX_REM_Buffer_reg[0]_0 ;
  input user_clk;
  input EOF_N_Buffer_reg_0;
  input end_storage_r0;
  input FRAME_ERR_RESULT_Buffer0;
  input stage_2_start_with_data_r;
  input stage_2_pad_r;
  input [0:0]Q;
  input [0:0]\RX_REM_Buffer_reg[0]_1 ;
  input std_bool6_in;
  input stage_2_end_before_start_r;
  input stage_2_frame_err_r;
  input START_RX;

  wire [0:0]D;
  wire EOF_N_Buffer;
  wire EOF_N_Buffer_reg_0;
  wire FRAME_ERR_RESULT_Buffer;
  wire FRAME_ERR_RESULT_Buffer0;
  wire [0:0]Q;
  wire [1:0]\RX_REM_Buffer_reg[0]_0 ;
  wire [0:0]\RX_REM_Buffer_reg[0]_1 ;
  wire [0:0]SR;
  wire SRC_RDY_N_Buffer;
  wire SRC_RDY_N_Buffer_i_2_n_0;
  wire START_RX;
  wire end_storage_r0;
  wire pad_storage_r;
  wire pad_storage_r_i_1_n_0;
  wire [1:0]rx_rem_c;
  wire stage_2_end_before_start_r;
  wire stage_2_frame_err_r;
  wire stage_2_pad_r;
  wire stage_2_start_with_data_r;
  wire stage_3_end_storage_r;
  wire std_bool6_in;
  wire user_clk;

  FDRE EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(EOF_N_Buffer_reg_0),
        .Q(EOF_N_Buffer),
        .R(1'b0));
  FDRE FRAME_ERR_RESULT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(FRAME_ERR_RESULT_Buffer0),
        .Q(FRAME_ERR_RESULT_Buffer),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'h1E0F)) 
    \RX_REM_Buffer[0]_i_1 
       (.I0(stage_3_end_storage_r),
        .I1(stage_2_start_with_data_r),
        .I2(Q),
        .I3(\RX_REM_Buffer_reg[0]_1 ),
        .O(rx_rem_c[1]));
  LUT4 #(
    .INIT(16'h00EF)) 
    \RX_REM_Buffer[1]_i_1 
       (.I0(stage_3_end_storage_r),
        .I1(stage_2_start_with_data_r),
        .I2(stage_2_pad_r),
        .I3(pad_storage_r),
        .O(rx_rem_c[0]));
  FDRE \RX_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_rem_c[1]),
        .Q(\RX_REM_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_rem_c[0]),
        .Q(\RX_REM_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    SRC_RDY_N_Buffer_i_1
       (.I0(stage_2_frame_err_r),
        .I1(START_RX),
        .O(SR));
  LUT4 #(
    .INIT(16'h0145)) 
    SRC_RDY_N_Buffer_i_2
       (.I0(stage_3_end_storage_r),
        .I1(stage_2_start_with_data_r),
        .I2(std_bool6_in),
        .I3(stage_2_end_before_start_r),
        .O(SRC_RDY_N_Buffer_i_2_n_0));
  FDSE SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(SRC_RDY_N_Buffer_i_2_n_0),
        .Q(SRC_RDY_N_Buffer),
        .S(SR));
  FDRE end_storage_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(end_storage_r0),
        .Q(stage_3_end_storage_r),
        .R(SR));
  LUT6 #(
    .INIT(64'hAAABBABBAAAAAAAA)) 
    pad_storage_r_i_1
       (.I0(stage_2_pad_r),
        .I1(stage_3_end_storage_r),
        .I2(stage_2_start_with_data_r),
        .I3(std_bool6_in),
        .I4(stage_2_end_before_start_r),
        .I5(pad_storage_r),
        .O(pad_storage_r_i_1_n_0));
  FDRE pad_storage_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(pad_storage_r_i_1_n_0),
        .Q(pad_storage_r),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'hE1F0)) 
    \storage_count_r[1]_i_1 
       (.I0(stage_3_end_storage_r),
        .I1(stage_2_start_with_data_r),
        .I2(\RX_REM_Buffer_reg[0]_1 ),
        .I3(Q),
        .O(D));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_STORAGE_CE_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_CE_CONTROL
   (Q,
    RESET,
    D,
    user_clk);
  output [1:0]Q;
  input RESET;
  input [1:0]D;
  input user_clk;

  wire [1:0]D;
  wire [1:0]Q;
  wire RESET;
  wire user_clk;

  FDRE \STORAGE_CE_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(RESET));
  FDRE \STORAGE_CE_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(RESET));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_COUNT_CONTROL
   (output_select_c,
    Q,
    FRAME_ERR_RESULT_Buffer0,
    end_storage_r_reg,
    stage_2_start_with_data_r,
    stage_3_end_storage_r,
    stage_2_frame_err_r,
    stage_2_end_after_start_r,
    stage_2_end_before_start_r,
    std_bool2_in,
    SR,
    D,
    user_clk);
  output [0:0]output_select_c;
  output [1:0]Q;
  output FRAME_ERR_RESULT_Buffer0;
  output end_storage_r_reg;
  input stage_2_start_with_data_r;
  input stage_3_end_storage_r;
  input stage_2_frame_err_r;
  input stage_2_end_after_start_r;
  input stage_2_end_before_start_r;
  input std_bool2_in;
  input [0:0]SR;
  input [1:0]D;
  input user_clk;

  wire [1:0]D;
  wire FRAME_ERR_RESULT_Buffer0;
  wire [1:0]Q;
  wire [0:0]SR;
  wire end_storage_r_reg;
  wire [0:0]output_select_c;
  wire \sideband_output_i/std_bool ;
  wire stage_2_end_after_start_r;
  wire stage_2_end_before_start_r;
  wire stage_2_frame_err_r;
  wire stage_2_start_with_data_r;
  wire stage_3_end_storage_r;
  wire std_bool2_in;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT5 #(
    .INIT(32'h15151555)) 
    EOF_N_Buffer_i_1
       (.I0(stage_3_end_storage_r),
        .I1(stage_2_end_before_start_r),
        .I2(stage_2_start_with_data_r),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(end_storage_r_reg));
  LUT6 #(
    .INIT(64'hDDFFCCFCDDFCCCFC)) 
    FRAME_ERR_RESULT_Buffer_i_1
       (.I0(\sideband_output_i/std_bool ),
        .I1(stage_2_frame_err_r),
        .I2(stage_2_end_after_start_r),
        .I3(stage_2_start_with_data_r),
        .I4(stage_2_end_before_start_r),
        .I5(std_bool2_in),
        .O(FRAME_ERR_RESULT_Buffer0));
  LUT2 #(
    .INIT(4'hE)) 
    FRAME_ERR_RESULT_Buffer_i_2
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\sideband_output_i/std_bool ));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \OUTPUT_SELECT_Buffer[9]_i_1 
       (.I0(Q[1]),
        .I1(stage_2_start_with_data_r),
        .I2(stage_3_end_storage_r),
        .O(output_select_c));
  FDRE \storage_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE \storage_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_STORAGE_MUX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_MUX
   (Q,
    E,
    D,
    user_clk);
  output [31:0]Q;
  input [1:0]E;
  input [31:0]D;
  input user_clk;

  wire [31:0]D;
  wire [1:0]E;
  wire [31:0]Q;
  wire user_clk;

  FDRE \STORAGE_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[31]),
        .Q(Q[31]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[21]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[20]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[19]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[18]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[17]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[16]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[15]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[14]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[13]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[12]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[30]),
        .Q(Q[30]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[11]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[29]),
        .Q(Q[29]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[28]),
        .Q(Q[28]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[27]),
        .Q(Q[27]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[26]),
        .Q(Q[26]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[25]),
        .Q(Q[25]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[24]),
        .Q(Q[24]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[23]),
        .Q(Q[23]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[22]),
        .Q(Q[22]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_STORAGE_SWITCH_CONTROL
   (STORAGE_SELECT_Buffer,
    Q,
    stage_2_start_with_data_r,
    stage_3_end_storage_r,
    user_clk);
  output [1:0]STORAGE_SELECT_Buffer;
  input [0:0]Q;
  input stage_2_start_with_data_r;
  input stage_3_end_storage_r;
  input user_clk;

  wire [0:0]Q;
  wire [1:0]STORAGE_SELECT_Buffer;
  wire \STORAGE_SELECT_Buffer[4]_i_1_n_0 ;
  wire \STORAGE_SELECT_Buffer[9]_i_1_n_0 ;
  wire stage_2_start_with_data_r;
  wire stage_3_end_storage_r;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \STORAGE_SELECT_Buffer[4]_i_1 
       (.I0(Q),
        .I1(stage_2_start_with_data_r),
        .I2(stage_3_end_storage_r),
        .O(\STORAGE_SELECT_Buffer[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \STORAGE_SELECT_Buffer[9]_i_1 
       (.I0(Q),
        .I1(stage_2_start_with_data_r),
        .I2(stage_3_end_storage_r),
        .O(\STORAGE_SELECT_Buffer[9]_i_1_n_0 ));
  FDRE \STORAGE_SELECT_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\STORAGE_SELECT_Buffer[4]_i_1_n_0 ),
        .Q(STORAGE_SELECT_Buffer[1]),
        .R(1'b0));
  FDRE \STORAGE_SELECT_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\STORAGE_SELECT_Buffer[9]_i_1_n_0 ),
        .Q(STORAGE_SELECT_Buffer[0]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_SYM_DEC_4BYTE" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_SYM_DEC_4BYTE
   (RX_NEG_Buffer,
    rx_sp_i,
    D,
    GOT_V,
    RX_PE_DATA,
    first_v_received_r,
    \left_align_select_r_reg[1]_0 ,
    \left_align_select_r_reg[0]_0 ,
    Q,
    neqOp,
    \RX_SUF_Buffer_reg[0]_0 ,
    \RX_PE_DATA_Buffer_reg[26]_0 ,
    \RX_PE_DATA_Buffer_reg[26]_1 ,
    \RX_PE_DATA_Buffer_reg[25]_0 ,
    \RX_SUF_Buffer_reg[1]_0 ,
    \word_aligned_data_r_reg[27]_0 ,
    \word_aligned_data_r_reg[16]_0 ,
    \word_aligned_data_r_reg[11]_0 ,
    \word_aligned_data_r_reg[0]_0 ,
    \RX_PE_DATA_V_Buffer_reg[0]_0 ,
    p_9_out,
    p_8_out,
    p_2_out,
    user_clk,
    \word_aligned_control_bits_r_reg[3]_0 ,
    RXDATA,
    RXCHARISK,
    RX_LANE_UP,
    \left_align_select_r_reg[0]_1 ,
    \word_aligned_data_r_reg[24]_0 ,
    \word_aligned_data_r_reg[16]_1 );
  output RX_NEG_Buffer;
  output rx_sp_i;
  output [0:0]D;
  output GOT_V;
  output [5:0]RX_PE_DATA;
  output first_v_received_r;
  output \left_align_select_r_reg[1]_0 ;
  output \left_align_select_r_reg[0]_0 ;
  output [3:0]Q;
  output neqOp;
  output [1:0]\RX_SUF_Buffer_reg[0]_0 ;
  output \RX_PE_DATA_Buffer_reg[26]_0 ;
  output \RX_PE_DATA_Buffer_reg[26]_1 ;
  output \RX_PE_DATA_Buffer_reg[25]_0 ;
  output \RX_SUF_Buffer_reg[1]_0 ;
  output [4:0]\word_aligned_data_r_reg[27]_0 ;
  output [7:0]\word_aligned_data_r_reg[16]_0 ;
  output [4:0]\word_aligned_data_r_reg[11]_0 ;
  output [7:0]\word_aligned_data_r_reg[0]_0 ;
  output [1:0]\RX_PE_DATA_V_Buffer_reg[0]_0 ;
  output [1:0]p_9_out;
  output [1:0]p_8_out;
  output [1:0]p_2_out;
  input user_clk;
  input \word_aligned_control_bits_r_reg[3]_0 ;
  input [31:0]RXDATA;
  input [3:0]RXCHARISK;
  input RX_LANE_UP;
  input \left_align_select_r_reg[0]_1 ;
  input [7:0]\word_aligned_data_r_reg[24]_0 ;
  input [3:0]\word_aligned_data_r_reg[16]_1 ;

  wire [0:0]D;
  wire \EXP_IN_inferred__0/i__n_0 ;
  wire \EXP_IN_inferred__1/i__n_0 ;
  wire \EXP_IN_inferred__10/i__n_0 ;
  wire \EXP_IN_inferred__11/i__n_0 ;
  wire \EXP_IN_inferred__12/i__n_0 ;
  wire \EXP_IN_inferred__13/i__n_0 ;
  wire \EXP_IN_inferred__14/i__n_0 ;
  wire \EXP_IN_inferred__15/i__n_0 ;
  wire \EXP_IN_inferred__16/i__n_0 ;
  wire \EXP_IN_inferred__17/i__n_0 ;
  wire \EXP_IN_inferred__18/i__n_0 ;
  wire \EXP_IN_inferred__19/i__n_0 ;
  wire \EXP_IN_inferred__2/i__n_0 ;
  wire \EXP_IN_inferred__20/i__n_0 ;
  wire \EXP_IN_inferred__21/i__n_0 ;
  wire \EXP_IN_inferred__22/i__n_0 ;
  wire \EXP_IN_inferred__23/i__n_0 ;
  wire \EXP_IN_inferred__24/i__n_0 ;
  wire \EXP_IN_inferred__25/i__n_0 ;
  wire \EXP_IN_inferred__26/i__n_0 ;
  wire \EXP_IN_inferred__3/i__n_0 ;
  wire \EXP_IN_inferred__34/i__n_0 ;
  wire \EXP_IN_inferred__35/i__n_0 ;
  wire \EXP_IN_inferred__4/i__n_0 ;
  wire \EXP_IN_inferred__44/i__n_0 ;
  wire \EXP_IN_inferred__45/i__n_0 ;
  wire \EXP_IN_inferred__46/i__n_0 ;
  wire \EXP_IN_inferred__47/i__n_0 ;
  wire \EXP_IN_inferred__5/i__n_0 ;
  wire \EXP_IN_inferred__6/i__n_0 ;
  wire \EXP_IN_inferred__8/i__n_0 ;
  wire \EXP_IN_inferred__9/i__n_0 ;
  wire EXP_IN_n_0;
  wire GOT_V;
  wire GOT_V_Buffer_i_2_n_0;
  wire [3:0]Q;
  wire [3:0]RXCHARISK;
  wire [31:0]RXDATA;
  wire RX_CC_Buffer_i_1_n_0;
  wire RX_CC_Buffer_i_2_n_0;
  wire RX_CC_Buffer_i_3_n_0;
  wire RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire RX_NEG_Buffer0;
  wire [5:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[25]_0 ;
  wire \RX_PE_DATA_Buffer_reg[26]_0 ;
  wire \RX_PE_DATA_Buffer_reg[26]_1 ;
  wire \RX_PE_DATA_V_Buffer[0]_i_1_n_0 ;
  wire \RX_PE_DATA_V_Buffer[1]_i_1_n_0 ;
  wire [1:0]\RX_PE_DATA_V_Buffer_reg[0]_0 ;
  wire RX_SP_Buffer_i_2_n_0;
  wire RX_SP_Buffer_i_3_n_0;
  wire [1:0]\RX_SUF_Buffer_reg[0]_0 ;
  wire \RX_SUF_Buffer_reg[1]_0 ;
  wire first_v_received_r;
  wire first_v_received_r_i_1_n_0;
  wire \left_align_select_r[0]_i_1_n_0 ;
  wire \left_align_select_r[1]_i_1_n_0 ;
  wire \left_align_select_r_reg[0]_0 ;
  wire \left_align_select_r_reg[0]_1 ;
  wire \left_align_select_r_reg[1]_0 ;
  wire neqOp;
  wire [3:1]p_0_in;
  wire p_0_in14_in;
  wire p_0_in18_in;
  wire p_0_in26_in;
  wire p_0_in28_in;
  wire p_15_in;
  wire p_1_in;
  wire p_1_in29_in;
  wire p_21_in;
  wire p_2_in30_in;
  wire [1:0]p_2_out;
  wire p_32_in;
  wire p_3_in;
  wire [1:0]p_5_out;
  wire p_6_in22_in;
  wire p_6_in34_in;
  wire [1:0]p_8_out;
  wire [1:0]p_9_out;
  wire [2:0]previous_cycle_control_r;
  wire [23:0]previous_cycle_data_r;
  wire [1:7]rx_cc_r;
  wire \rx_ecp_d_r_reg_n_0_[3] ;
  wire \rx_ecp_d_r_reg_n_0_[5] ;
  wire \rx_ecp_d_r_reg_n_0_[7] ;
  wire [0:3]rx_pad_d_r;
  wire \rx_pe_control_r_reg_n_0_[3] ;
  wire [8:26]rx_pe_data_r;
  wire \rx_scp_d_r_reg_n_0_[3] ;
  wire \rx_scp_d_r_reg_n_0_[7] ;
  wire rx_sp_i;
  wire [0:1]rx_sp_neg_d_r;
  wire [0:7]rx_sp_r;
  wire \rx_sp_r[2]_i_1_n_0 ;
  wire \rx_sp_r[3]_i_1_n_0 ;
  wire \rx_sp_r[4]_i_1_n_0 ;
  wire \rx_sp_r[5]_i_1_n_0 ;
  wire \rx_sp_r[6]_i_1_n_0 ;
  wire \rx_sp_r[7]_i_1_n_0 ;
  wire [0:1]rx_spa_neg_d_r;
  wire [2:7]rx_v_d_r;
  wire std_bool13_in;
  wire std_bool13_out;
  wire std_bool16_in;
  wire std_bool1_out;
  wire user_clk;
  wire [0:3]word_aligned_control_bits_r;
  wire \word_aligned_control_bits_r[0]_i_1_n_0 ;
  wire \word_aligned_control_bits_r[1]_i_1_n_0 ;
  wire \word_aligned_control_bits_r[2]_i_1_n_0 ;
  wire \word_aligned_control_bits_r_reg[3]_0 ;
  wire \word_aligned_data_r[0]_i_1_n_0 ;
  wire \word_aligned_data_r[10]_i_1_n_0 ;
  wire \word_aligned_data_r[11]_i_1_n_0 ;
  wire \word_aligned_data_r[12]_i_1_n_0 ;
  wire \word_aligned_data_r[13]_i_1_n_0 ;
  wire \word_aligned_data_r[14]_i_1_n_0 ;
  wire \word_aligned_data_r[15]_i_1_n_0 ;
  wire \word_aligned_data_r[17]_i_1_n_0 ;
  wire \word_aligned_data_r[19]_i_1_n_0 ;
  wire \word_aligned_data_r[1]_i_1_n_0 ;
  wire \word_aligned_data_r[21]_i_1_n_0 ;
  wire \word_aligned_data_r[23]_i_1_n_0 ;
  wire \word_aligned_data_r[2]_i_1_n_0 ;
  wire \word_aligned_data_r[3]_i_1_n_0 ;
  wire \word_aligned_data_r[4]_i_1_n_0 ;
  wire \word_aligned_data_r[5]_i_1_n_0 ;
  wire \word_aligned_data_r[6]_i_1_n_0 ;
  wire \word_aligned_data_r[7]_i_1_n_0 ;
  wire \word_aligned_data_r[8]_i_1_n_0 ;
  wire \word_aligned_data_r[9]_i_1_n_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [4:0]\word_aligned_data_r_reg[11]_0 ;
  wire [7:0]\word_aligned_data_r_reg[16]_0 ;
  wire [3:0]\word_aligned_data_r_reg[16]_1 ;
  wire [7:0]\word_aligned_data_r_reg[24]_0 ;
  wire [4:0]\word_aligned_data_r_reg[27]_0 ;
  wire \word_aligned_data_r_reg_n_0_[24] ;
  wire \word_aligned_data_r_reg_n_0_[25] ;
  wire \word_aligned_data_r_reg_n_0_[26] ;

  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    EXP_IN
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [2]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(EXP_IN_n_0));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__0/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [7]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__0/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \EXP_IN_inferred__1/i_ 
       (.I0(\word_aligned_data_r_reg[27]_0 [2]),
        .I1(\word_aligned_data_r_reg[27]_0 [1]),
        .I2(\word_aligned_data_r_reg[27]_0 [3]),
        .I3(\word_aligned_data_r_reg[27]_0 [0]),
        .O(\EXP_IN_inferred__1/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__10/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [1]),
        .I1(\word_aligned_data_r_reg[11]_0 [0]),
        .I2(\word_aligned_data_r_reg[11]_0 [2]),
        .I3(\word_aligned_data_r_reg[11]_0 [3]),
        .O(\EXP_IN_inferred__10/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__11/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__11/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__12/i_ 
       (.I0(\word_aligned_data_r_reg[27]_0 [2]),
        .I1(\word_aligned_data_r_reg[27]_0 [3]),
        .I2(\word_aligned_data_r_reg[27]_0 [1]),
        .I3(\word_aligned_data_r_reg[27]_0 [0]),
        .O(\EXP_IN_inferred__12/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__13/i_ 
       (.I0(\word_aligned_data_r_reg_n_0_[26] ),
        .I1(\word_aligned_data_r_reg[27]_0 [4]),
        .I2(\word_aligned_data_r_reg_n_0_[25] ),
        .I3(\word_aligned_data_r_reg_n_0_[24] ),
        .O(\EXP_IN_inferred__13/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__14/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [1]),
        .I1(\word_aligned_data_r_reg[16]_0 [0]),
        .I2(\word_aligned_data_r_reg[16]_0 [2]),
        .I3(\word_aligned_data_r_reg[16]_0 [3]),
        .O(\EXP_IN_inferred__14/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__15/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [7]),
        .I1(\word_aligned_data_r_reg[16]_0 [5]),
        .I2(\word_aligned_data_r_reg[16]_0 [6]),
        .I3(\word_aligned_data_r_reg[16]_0 [4]),
        .O(\EXP_IN_inferred__15/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__16/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [3]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__16/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__17/i_ 
       (.I0(p_0_in[1]),
        .I1(\word_aligned_data_r_reg[11]_0 [4]),
        .I2(p_0_in[2]),
        .I3(p_0_in[3]),
        .O(\EXP_IN_inferred__17/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__18/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__18/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__19/i_ 
       (.I0(\word_aligned_data_r_reg[27]_0 [0]),
        .I1(\word_aligned_data_r_reg[27]_0 [2]),
        .I2(\word_aligned_data_r_reg[27]_0 [3]),
        .I3(\word_aligned_data_r_reg[27]_0 [1]),
        .O(\EXP_IN_inferred__19/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__2/i_ 
       (.I0(\word_aligned_data_r_reg[27]_0 [4]),
        .I1(\word_aligned_data_r_reg_n_0_[25] ),
        .I2(\word_aligned_data_r_reg_n_0_[24] ),
        .I3(\word_aligned_data_r_reg_n_0_[26] ),
        .O(\EXP_IN_inferred__2/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__20/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [1]),
        .I1(\word_aligned_data_r_reg[16]_0 [2]),
        .I2(\word_aligned_data_r_reg[16]_0 [3]),
        .I3(\word_aligned_data_r_reg[16]_0 [0]),
        .O(\EXP_IN_inferred__20/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__21/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [5]),
        .I1(\word_aligned_data_r_reg[16]_0 [4]),
        .I2(\word_aligned_data_r_reg[16]_0 [6]),
        .I3(\word_aligned_data_r_reg[16]_0 [7]),
        .O(\EXP_IN_inferred__21/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__22/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [0]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [3]),
        .I3(\word_aligned_data_r_reg[11]_0 [1]),
        .O(\EXP_IN_inferred__22/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__23/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__23/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__24/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [5]),
        .I1(\word_aligned_data_r_reg[0]_0 [4]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [7]),
        .O(\EXP_IN_inferred__24/i__n_0 ));
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__25/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [6]),
        .I1(\word_aligned_data_r_reg[16]_0 [5]),
        .I2(\word_aligned_data_r_reg[16]_0 [7]),
        .I3(\word_aligned_data_r_reg[16]_0 [4]),
        .O(\EXP_IN_inferred__25/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__26/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__26/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__27/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [3]),
        .I1(\word_aligned_data_r_reg[11]_0 [1]),
        .I2(\word_aligned_data_r_reg[11]_0 [2]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(std_bool13_in));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__28/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[3]),
        .I2(p_0_in[1]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(std_bool16_in));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \EXP_IN_inferred__3/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [2]),
        .I1(\word_aligned_data_r_reg[16]_0 [1]),
        .I2(\word_aligned_data_r_reg[16]_0 [3]),
        .I3(\word_aligned_data_r_reg[16]_0 [0]),
        .O(\EXP_IN_inferred__3/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__34/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [3]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__34/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__35/i_ 
       (.I0(p_0_in[1]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__35/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__4/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [4]),
        .I1(\word_aligned_data_r_reg[16]_0 [6]),
        .I2(\word_aligned_data_r_reg[16]_0 [7]),
        .I3(\word_aligned_data_r_reg[16]_0 [5]),
        .O(\EXP_IN_inferred__4/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__44/i_ 
       (.I0(\word_aligned_data_r_reg[27]_0 [3]),
        .I1(\word_aligned_data_r_reg[27]_0 [2]),
        .I2(\word_aligned_data_r_reg[27]_0 [1]),
        .I3(\word_aligned_data_r_reg[27]_0 [0]),
        .O(\EXP_IN_inferred__44/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__45/i_ 
       (.I0(\word_aligned_data_r_reg[16]_0 [3]),
        .I1(\word_aligned_data_r_reg[16]_0 [2]),
        .I2(\word_aligned_data_r_reg[16]_0 [1]),
        .I3(\word_aligned_data_r_reg[16]_0 [0]),
        .O(\EXP_IN_inferred__45/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__46/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [3]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__46/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__47/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [3]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__47/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \EXP_IN_inferred__5/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [1]),
        .I2(\word_aligned_data_r_reg[11]_0 [3]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__5/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__6/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [4]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(p_0_in[1]),
        .O(\EXP_IN_inferred__6/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__8/i_ 
       (.I0(\word_aligned_data_r_reg[27]_0 [1]),
        .I1(\word_aligned_data_r_reg[27]_0 [0]),
        .I2(\word_aligned_data_r_reg[27]_0 [2]),
        .I3(\word_aligned_data_r_reg[27]_0 [3]),
        .O(\EXP_IN_inferred__8/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__9/i_ 
       (.I0(\word_aligned_data_r_reg_n_0_[25] ),
        .I1(\word_aligned_data_r_reg_n_0_[26] ),
        .I2(\word_aligned_data_r_reg_n_0_[24] ),
        .I3(\word_aligned_data_r_reg[27]_0 [4]),
        .O(\EXP_IN_inferred__9/i__n_0 ));
  LUT6 #(
    .INIT(64'h2000000000000000)) 
    GOT_V_Buffer_i_1
       (.I0(RX_SP_Buffer_i_2_n_0),
        .I1(GOT_V_Buffer_i_2_n_0),
        .I2(rx_sp_r[0]),
        .I3(rx_sp_r[1]),
        .I4(rx_v_d_r[3]),
        .I5(rx_v_d_r[2]),
        .O(std_bool1_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    GOT_V_Buffer_i_2
       (.I0(rx_v_d_r[5]),
        .I1(rx_v_d_r[4]),
        .I2(rx_v_d_r[7]),
        .I3(rx_v_d_r[6]),
        .O(GOT_V_Buffer_i_2_n_0));
  FDRE GOT_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool1_out),
        .Q(GOT_V),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    RX_CC_Buffer_i_1
       (.I0(p_1_in),
        .I1(\rx_pe_control_r_reg_n_0_[3] ),
        .I2(p_3_in),
        .I3(p_0_in26_in),
        .I4(RX_CC_Buffer_i_2_n_0),
        .I5(RX_CC_Buffer_i_3_n_0),
        .O(RX_CC_Buffer_i_1_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    RX_CC_Buffer_i_2
       (.I0(rx_cc_r[5]),
        .I1(p_0_in18_in),
        .I2(rx_cc_r[7]),
        .I3(p_2_in30_in),
        .O(RX_CC_Buffer_i_2_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    RX_CC_Buffer_i_3
       (.I0(p_21_in),
        .I1(rx_cc_r[1]),
        .I2(rx_cc_r[3]),
        .I3(p_6_in34_in),
        .O(RX_CC_Buffer_i_3_n_0));
  FDRE RX_CC_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_CC_Buffer_i_1_n_0),
        .Q(D),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000F888)) 
    RX_NEG_Buffer_i_1
       (.I0(rx_spa_neg_d_r[1]),
        .I1(rx_spa_neg_d_r[0]),
        .I2(rx_sp_neg_d_r[1]),
        .I3(rx_sp_neg_d_r[0]),
        .I4(p_0_in26_in),
        .O(RX_NEG_Buffer0));
  FDRE RX_NEG_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_NEG_Buffer0),
        .Q(RX_NEG_Buffer),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[10]),
        .Q(RX_PE_DATA[3]),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[24]),
        .Q(RX_PE_DATA[2]),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[25]),
        .Q(RX_PE_DATA[1]),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[26]),
        .Q(RX_PE_DATA[0]),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[8]),
        .Q(RX_PE_DATA[5]),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[9]),
        .Q(RX_PE_DATA[4]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \RX_PE_DATA_V_Buffer[0]_i_1 
       (.I0(p_3_in),
        .O(\RX_PE_DATA_V_Buffer[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \RX_PE_DATA_V_Buffer[1]_i_1 
       (.I0(p_1_in),
        .O(\RX_PE_DATA_V_Buffer[1]_i_1_n_0 ));
  FDRE \RX_PE_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_PE_DATA_V_Buffer[0]_i_1_n_0 ),
        .Q(\RX_PE_DATA_V_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \RX_PE_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_PE_DATA_V_Buffer[1]_i_1_n_0 ),
        .Q(\RX_PE_DATA_V_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h2000000000000000)) 
    RX_SP_Buffer_i_1
       (.I0(RX_SP_Buffer_i_2_n_0),
        .I1(RX_SP_Buffer_i_3_n_0),
        .I2(rx_sp_r[0]),
        .I3(rx_sp_r[1]),
        .I4(rx_sp_r[3]),
        .I5(rx_sp_r[2]),
        .O(std_bool13_out));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    RX_SP_Buffer_i_2
       (.I0(\rx_pe_control_r_reg_n_0_[3] ),
        .I1(p_0_in26_in),
        .I2(p_3_in),
        .I3(p_1_in),
        .O(RX_SP_Buffer_i_2_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    RX_SP_Buffer_i_3
       (.I0(rx_sp_r[5]),
        .I1(rx_sp_r[4]),
        .I2(rx_sp_r[7]),
        .I3(rx_sp_r[6]),
        .O(RX_SP_Buffer_i_3_n_0));
  FDRE RX_SP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool13_out),
        .Q(rx_sp_i),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \RX_SUF_Buffer[0]_i_1 
       (.I0(p_3_in),
        .I1(p_15_in),
        .I2(rx_sp_r[1]),
        .O(p_5_out[1]));
  LUT3 #(
    .INIT(8'h80)) 
    \RX_SUF_Buffer[1]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in14_in),
        .I2(p_1_in29_in),
        .O(p_5_out[0]));
  FDRE \RX_SUF_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_5_out[1]),
        .Q(\RX_SUF_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \RX_SUF_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_5_out[0]),
        .Q(\RX_SUF_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hA8)) 
    first_v_received_r_i_1
       (.I0(RX_LANE_UP),
        .I1(first_v_received_r),
        .I2(std_bool1_out),
        .O(first_v_received_r_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    first_v_received_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(first_v_received_r_i_1_n_0),
        .Q(first_v_received_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFAFFFB10401110)) 
    \left_align_select_r[0]_i_1 
       (.I0(\left_align_select_r_reg[0]_1 ),
        .I1(RXCHARISK[0]),
        .I2(RXCHARISK[2]),
        .I3(RXCHARISK[3]),
        .I4(RXCHARISK[1]),
        .I5(\left_align_select_r_reg[0]_0 ),
        .O(\left_align_select_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFFFEB10051100)) 
    \left_align_select_r[1]_i_1 
       (.I0(\left_align_select_r_reg[0]_1 ),
        .I1(RXCHARISK[0]),
        .I2(RXCHARISK[2]),
        .I3(RXCHARISK[3]),
        .I4(RXCHARISK[1]),
        .I5(\left_align_select_r_reg[1]_0 ),
        .O(\left_align_select_r[1]_i_1_n_0 ));
  FDRE \left_align_select_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\left_align_select_r[0]_i_1_n_0 ),
        .Q(\left_align_select_r_reg[0]_0 ),
        .R(1'b0));
  FDRE \left_align_select_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\left_align_select_r[1]_i_1_n_0 ),
        .Q(\left_align_select_r_reg[1]_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hE)) 
    load_ufc_control_code_r_i_1
       (.I0(\RX_SUF_Buffer_reg[0]_0 [1]),
        .I1(\RX_SUF_Buffer_reg[0]_0 [0]),
        .O(neqOp));
  FDRE \previous_cycle_control_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXCHARISK[3]),
        .Q(previous_cycle_control_r[0]),
        .R(1'b0));
  FDRE \previous_cycle_control_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXCHARISK[2]),
        .Q(previous_cycle_control_r[1]),
        .R(1'b0));
  FDRE \previous_cycle_control_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXCHARISK[1]),
        .Q(previous_cycle_control_r[2]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[24]),
        .Q(previous_cycle_data_r[0]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[18]),
        .Q(previous_cycle_data_r[10]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[19]),
        .Q(previous_cycle_data_r[11]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[20]),
        .Q(previous_cycle_data_r[12]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[21]),
        .Q(previous_cycle_data_r[13]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[22]),
        .Q(previous_cycle_data_r[14]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[23]),
        .Q(previous_cycle_data_r[15]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[8]),
        .Q(previous_cycle_data_r[16]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[9]),
        .Q(previous_cycle_data_r[17]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[10]),
        .Q(previous_cycle_data_r[18]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[11]),
        .Q(previous_cycle_data_r[19]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[25]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[12]),
        .Q(previous_cycle_data_r[20]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[13]),
        .Q(previous_cycle_data_r[21]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[14]),
        .Q(previous_cycle_data_r[22]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[15]),
        .Q(previous_cycle_data_r[23]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[26]),
        .Q(previous_cycle_data_r[2]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[27]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[28]),
        .Q(previous_cycle_data_r[4]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[29]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[30]),
        .Q(previous_cycle_data_r[6]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[31]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[16]),
        .Q(previous_cycle_data_r[8]),
        .R(1'b0));
  FDRE \previous_cycle_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RXDATA[17]),
        .Q(previous_cycle_data_r[9]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__47/i__n_0 ),
        .Q(rx_cc_r[1]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__46/i__n_0 ),
        .Q(rx_cc_r[3]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__45/i__n_0 ),
        .Q(rx_cc_r[5]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__44/i__n_0 ),
        .Q(rx_cc_r[7]),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__24/i__n_0 ),
        .Q(p_21_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__23/i__n_0 ),
        .Q(p_6_in22_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__22/i__n_0 ),
        .Q(\rx_ecp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__21/i__n_0 ),
        .Q(p_0_in18_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__20/i__n_0 ),
        .Q(\rx_ecp_d_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__19/i__n_0 ),
        .Q(\rx_ecp_d_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_ecp_r_reg[0]_srl2_i_1 
       (.I0(p_0_in26_in),
        .I1(p_3_in),
        .I2(p_6_in22_in),
        .I3(p_21_in),
        .I4(\rx_ecp_d_r_reg_n_0_[3] ),
        .I5(p_6_in34_in),
        .O(p_9_out[1]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_ecp_r_reg[1]_srl2_i_1 
       (.I0(\rx_pe_control_r_reg_n_0_[3] ),
        .I1(p_1_in),
        .I2(\rx_ecp_d_r_reg_n_0_[5] ),
        .I3(p_0_in18_in),
        .I4(\rx_ecp_d_r_reg_n_0_[7] ),
        .I5(p_2_in30_in),
        .O(p_9_out[0]));
  FDRE \rx_pad_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__11/i__n_0 ),
        .Q(rx_pad_d_r[0]),
        .R(1'b0));
  FDRE \rx_pad_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__10/i__n_0 ),
        .Q(rx_pad_d_r[1]),
        .R(1'b0));
  FDRE \rx_pad_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__9/i__n_0 ),
        .Q(rx_pad_d_r[2]),
        .R(1'b0));
  FDRE \rx_pad_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__8/i__n_0 ),
        .Q(rx_pad_d_r[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0800)) 
    \rx_pad_r_reg[0]_srl2_i_1 
       (.I0(rx_pad_d_r[0]),
        .I1(rx_pad_d_r[1]),
        .I2(p_3_in),
        .I3(p_0_in26_in),
        .O(p_2_out[1]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \rx_pad_r_reg[1]_srl2_i_1 
       (.I0(rx_pad_d_r[2]),
        .I1(rx_pad_d_r[3]),
        .I2(p_1_in),
        .I3(\rx_pe_control_r_reg_n_0_[3] ),
        .O(p_2_out[0]));
  FDRE \rx_pe_control_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[0]),
        .Q(p_3_in),
        .R(1'b0));
  FDRE \rx_pe_control_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[1]),
        .Q(p_0_in26_in),
        .R(1'b0));
  FDRE \rx_pe_control_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[2]),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \rx_pe_control_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[3]),
        .Q(\rx_pe_control_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(rx_pe_data_r[10]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg_n_0_[24] ),
        .Q(rx_pe_data_r[24]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg_n_0_[25] ),
        .Q(rx_pe_data_r[25]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg_n_0_[26] ),
        .Q(rx_pe_data_r[26]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(rx_pe_data_r[8]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(rx_pe_data_r[9]),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__18/i__n_0 ),
        .Q(p_32_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__17/i__n_0 ),
        .Q(p_6_in34_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__16/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__15/i__n_0 ),
        .Q(p_0_in28_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__14/i__n_0 ),
        .Q(p_1_in29_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__13/i__n_0 ),
        .Q(p_2_in30_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__12/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_scp_r_reg[0]_srl2_i_1 
       (.I0(p_0_in26_in),
        .I1(p_3_in),
        .I2(rx_sp_r[1]),
        .I3(p_32_in),
        .I4(\rx_scp_d_r_reg_n_0_[3] ),
        .I5(p_6_in34_in),
        .O(p_8_out[1]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_scp_r_reg[1]_srl2_i_1 
       (.I0(\rx_pe_control_r_reg_n_0_[3] ),
        .I1(p_1_in),
        .I2(p_1_in29_in),
        .I3(p_0_in28_in),
        .I4(\rx_scp_d_r_reg_n_0_[7] ),
        .I5(p_2_in30_in),
        .O(p_8_out[0]));
  FDRE \rx_sp_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool16_in),
        .Q(rx_sp_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool13_in),
        .Q(rx_sp_neg_d_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \rx_sp_r[2]_i_1 
       (.I0(\word_aligned_data_r_reg[11]_0 [4]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(p_0_in[2]),
        .O(\rx_sp_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \rx_sp_r[3]_i_1 
       (.I0(\word_aligned_data_r_reg[11]_0 [0]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [3]),
        .O(\rx_sp_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'h0810)) 
    \rx_sp_r[4]_i_1 
       (.I0(\word_aligned_data_r_reg[16]_0 [5]),
        .I1(\word_aligned_data_r_reg[16]_0 [4]),
        .I2(\word_aligned_data_r_reg[16]_0 [6]),
        .I3(\word_aligned_data_r_reg[16]_0 [7]),
        .O(\rx_sp_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \rx_sp_r[5]_i_1 
       (.I0(\word_aligned_data_r_reg[16]_0 [2]),
        .I1(\word_aligned_data_r_reg[16]_0 [0]),
        .I2(\word_aligned_data_r_reg[16]_0 [1]),
        .I3(\word_aligned_data_r_reg[16]_0 [3]),
        .O(\rx_sp_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT4 #(
    .INIT(16'h0810)) 
    \rx_sp_r[6]_i_1 
       (.I0(\word_aligned_data_r_reg_n_0_[26] ),
        .I1(\word_aligned_data_r_reg[27]_0 [4]),
        .I2(\word_aligned_data_r_reg_n_0_[25] ),
        .I3(\word_aligned_data_r_reg_n_0_[24] ),
        .O(\rx_sp_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \rx_sp_r[7]_i_1 
       (.I0(\word_aligned_data_r_reg[27]_0 [2]),
        .I1(\word_aligned_data_r_reg[27]_0 [0]),
        .I2(\word_aligned_data_r_reg[27]_0 [1]),
        .I3(\word_aligned_data_r_reg[27]_0 [3]),
        .O(\rx_sp_r[7]_i_1_n_0 ));
  FDRE \rx_sp_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__0/i__n_0 ),
        .Q(rx_sp_r[0]),
        .R(1'b0));
  FDRE \rx_sp_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(EXP_IN_n_0),
        .Q(rx_sp_r[1]),
        .R(1'b0));
  FDRE \rx_sp_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_sp_r[2]_i_1_n_0 ),
        .Q(rx_sp_r[2]),
        .R(1'b0));
  FDRE \rx_sp_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_sp_r[3]_i_1_n_0 ),
        .Q(rx_sp_r[3]),
        .R(1'b0));
  FDRE \rx_sp_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_sp_r[4]_i_1_n_0 ),
        .Q(rx_sp_r[4]),
        .R(1'b0));
  FDRE \rx_sp_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_sp_r[5]_i_1_n_0 ),
        .Q(rx_sp_r[5]),
        .R(1'b0));
  FDRE \rx_sp_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_sp_r[6]_i_1_n_0 ),
        .Q(rx_sp_r[6]),
        .R(1'b0));
  FDRE \rx_sp_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_sp_r[7]_i_1_n_0 ),
        .Q(rx_sp_r[7]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__35/i__n_0 ),
        .Q(rx_spa_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__34/i__n_0 ),
        .Q(rx_spa_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_suf_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__26/i__n_0 ),
        .Q(p_15_in),
        .R(1'b0));
  FDRE \rx_suf_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__25/i__n_0 ),
        .Q(p_0_in14_in),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__6/i__n_0 ),
        .Q(rx_v_d_r[2]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__5/i__n_0 ),
        .Q(rx_v_d_r[3]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__4/i__n_0 ),
        .Q(rx_v_d_r[4]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__3/i__n_0 ),
        .Q(rx_v_d_r[5]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__2/i__n_0 ),
        .Q(rx_v_d_r[6]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__1/i__n_0 ),
        .Q(rx_v_d_r[7]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    \stage_1_count_value_r[0]_i_1 
       (.I0(\RX_SUF_Buffer_reg[0]_0 [0]),
        .I1(RX_PE_DATA[2]),
        .I2(RX_PE_DATA[0]),
        .I3(RX_PE_DATA[1]),
        .O(\RX_SUF_Buffer_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h78FF780078007800)) 
    \stage_1_count_value_r[1]_i_1 
       (.I0(RX_PE_DATA[1]),
        .I1(RX_PE_DATA[0]),
        .I2(RX_PE_DATA[2]),
        .I3(\RX_SUF_Buffer_reg[0]_0 [0]),
        .I4(\RX_SUF_Buffer_reg[0]_0 [1]),
        .I5(RX_PE_DATA[5]),
        .O(\RX_PE_DATA_Buffer_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT5 #(
    .INIT(32'h6F606060)) 
    \stage_1_count_value_r[2]_i_1 
       (.I0(RX_PE_DATA[0]),
        .I1(RX_PE_DATA[1]),
        .I2(\RX_SUF_Buffer_reg[0]_0 [0]),
        .I3(\RX_SUF_Buffer_reg[0]_0 [1]),
        .I4(RX_PE_DATA[4]),
        .O(\RX_PE_DATA_Buffer_reg[26]_1 ));
  LUT4 #(
    .INIT(16'h7444)) 
    \stage_1_count_value_r[3]_i_1 
       (.I0(RX_PE_DATA[0]),
        .I1(\RX_SUF_Buffer_reg[0]_0 [0]),
        .I2(\RX_SUF_Buffer_reg[0]_0 [1]),
        .I3(RX_PE_DATA[3]),
        .O(\RX_PE_DATA_Buffer_reg[26]_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_control_bits_r[0]_i_1 
       (.I0(RXCHARISK[0]),
        .I1(previous_cycle_control_r[2]),
        .I2(previous_cycle_control_r[1]),
        .I3(\left_align_select_r_reg[0]_0 ),
        .I4(\left_align_select_r_reg[1]_0 ),
        .I5(previous_cycle_control_r[0]),
        .O(\word_aligned_control_bits_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_control_bits_r[1]_i_1 
       (.I0(RXCHARISK[1]),
        .I1(previous_cycle_control_r[1]),
        .I2(previous_cycle_control_r[0]),
        .I3(\left_align_select_r_reg[0]_0 ),
        .I4(\left_align_select_r_reg[1]_0 ),
        .I5(RXCHARISK[0]),
        .O(\word_aligned_control_bits_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \word_aligned_control_bits_r[2]_i_1 
       (.I0(previous_cycle_control_r[0]),
        .I1(RXCHARISK[0]),
        .I2(RXCHARISK[2]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(RXCHARISK[1]),
        .O(\word_aligned_control_bits_r[2]_i_1_n_0 ));
  FDRE \word_aligned_control_bits_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r[0]_i_1_n_0 ),
        .Q(word_aligned_control_bits_r[0]),
        .R(1'b0));
  FDRE \word_aligned_control_bits_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r[1]_i_1_n_0 ),
        .Q(word_aligned_control_bits_r[1]),
        .R(1'b0));
  FDRE \word_aligned_control_bits_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r[2]_i_1_n_0 ),
        .Q(word_aligned_control_bits_r[2]),
        .R(1'b0));
  FDRE \word_aligned_control_bits_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[3]_0 ),
        .Q(word_aligned_control_bits_r[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[0]_i_1 
       (.I0(RXDATA[7]),
        .I1(previous_cycle_data_r[23]),
        .I2(Q[3]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(previous_cycle_data_r[15]),
        .O(\word_aligned_data_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[10]_i_1 
       (.I0(RXDATA[13]),
        .I1(previous_cycle_data_r[13]),
        .I2(RXDATA[5]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(Q[2]),
        .O(\word_aligned_data_r[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \word_aligned_data_r[11]_i_1 
       (.I0(previous_cycle_data_r[12]),
        .I1(previous_cycle_data_r[4]),
        .I2(RXDATA[12]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(RXDATA[4]),
        .O(\word_aligned_data_r[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[12]_i_1 
       (.I0(RXDATA[11]),
        .I1(previous_cycle_data_r[11]),
        .I2(RXDATA[3]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(Q[1]),
        .O(\word_aligned_data_r[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[13]_i_1 
       (.I0(RXDATA[10]),
        .I1(previous_cycle_data_r[10]),
        .I2(RXDATA[2]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(previous_cycle_data_r[2]),
        .O(\word_aligned_data_r[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[14]_i_1 
       (.I0(RXDATA[9]),
        .I1(previous_cycle_data_r[9]),
        .I2(RXDATA[1]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(Q[0]),
        .O(\word_aligned_data_r[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[15]_i_1 
       (.I0(previous_cycle_data_r[8]),
        .I1(RXDATA[0]),
        .I2(RXDATA[8]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(previous_cycle_data_r[0]),
        .O(\word_aligned_data_r[15]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[17]_i_1 
       (.I0(previous_cycle_data_r[6]),
        .I1(RXDATA[14]),
        .I2(RXDATA[22]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(RXDATA[6]),
        .O(\word_aligned_data_r[17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[19]_i_1 
       (.I0(previous_cycle_data_r[4]),
        .I1(RXDATA[12]),
        .I2(RXDATA[20]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(RXDATA[4]),
        .O(\word_aligned_data_r[19]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_data_r[1]_i_1 
       (.I0(RXDATA[6]),
        .I1(previous_cycle_data_r[22]),
        .I2(previous_cycle_data_r[14]),
        .I3(\left_align_select_r_reg[0]_0 ),
        .I4(\left_align_select_r_reg[1]_0 ),
        .I5(previous_cycle_data_r[6]),
        .O(\word_aligned_data_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \word_aligned_data_r[21]_i_1 
       (.I0(previous_cycle_data_r[2]),
        .I1(RXDATA[2]),
        .I2(RXDATA[18]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(RXDATA[10]),
        .O(\word_aligned_data_r[21]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[23]_i_1 
       (.I0(previous_cycle_data_r[0]),
        .I1(RXDATA[8]),
        .I2(RXDATA[16]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(RXDATA[0]),
        .O(\word_aligned_data_r[23]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[2]_i_1 
       (.I0(RXDATA[5]),
        .I1(previous_cycle_data_r[21]),
        .I2(Q[2]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(previous_cycle_data_r[13]),
        .O(\word_aligned_data_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[3]_i_1 
       (.I0(previous_cycle_data_r[20]),
        .I1(previous_cycle_data_r[4]),
        .I2(RXDATA[4]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(previous_cycle_data_r[12]),
        .O(\word_aligned_data_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \word_aligned_data_r[4]_i_1 
       (.I0(previous_cycle_data_r[19]),
        .I1(previous_cycle_data_r[11]),
        .I2(RXDATA[3]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(Q[1]),
        .O(\word_aligned_data_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_data_r[5]_i_1 
       (.I0(RXDATA[2]),
        .I1(previous_cycle_data_r[18]),
        .I2(previous_cycle_data_r[10]),
        .I3(\left_align_select_r_reg[0]_0 ),
        .I4(\left_align_select_r_reg[1]_0 ),
        .I5(previous_cycle_data_r[2]),
        .O(\word_aligned_data_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[6]_i_1 
       (.I0(RXDATA[1]),
        .I1(previous_cycle_data_r[17]),
        .I2(Q[0]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(previous_cycle_data_r[9]),
        .O(\word_aligned_data_r[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[7]_i_1 
       (.I0(previous_cycle_data_r[16]),
        .I1(previous_cycle_data_r[0]),
        .I2(RXDATA[0]),
        .I3(\left_align_select_r_reg[1]_0 ),
        .I4(\left_align_select_r_reg[0]_0 ),
        .I5(previous_cycle_data_r[8]),
        .O(\word_aligned_data_r[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_data_r[8]_i_1 
       (.I0(RXDATA[15]),
        .I1(previous_cycle_data_r[15]),
        .I2(Q[3]),
        .I3(\left_align_select_r_reg[0]_0 ),
        .I4(\left_align_select_r_reg[1]_0 ),
        .I5(RXDATA[7]),
        .O(\word_aligned_data_r[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_data_r[9]_i_1 
       (.I0(RXDATA[14]),
        .I1(previous_cycle_data_r[14]),
        .I2(previous_cycle_data_r[6]),
        .I3(\left_align_select_r_reg[0]_0 ),
        .I4(\left_align_select_r_reg[1]_0 ),
        .I5(RXDATA[6]),
        .O(\word_aligned_data_r[9]_i_1_n_0 ));
  FDRE \word_aligned_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[0]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[10]_i_1_n_0 ),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[11]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[11]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[12]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[11]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[13]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[11]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[14]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[11]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[15]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[11]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[16]_1 [3]),
        .Q(\word_aligned_data_r_reg[16]_0 [7]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[17]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[16]_0 [6]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[16]_1 [2]),
        .Q(\word_aligned_data_r_reg[16]_0 [5]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[19]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[16]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[1]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[16]_1 [1]),
        .Q(\word_aligned_data_r_reg[16]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[21]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[16]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[16]_1 [0]),
        .Q(\word_aligned_data_r_reg[16]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[23]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[16]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [7]),
        .Q(\word_aligned_data_r_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [6]),
        .Q(\word_aligned_data_r_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [5]),
        .Q(\word_aligned_data_r_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [4]),
        .Q(\word_aligned_data_r_reg[27]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [3]),
        .Q(\word_aligned_data_r_reg[27]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [2]),
        .Q(\word_aligned_data_r_reg[27]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[2]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [1]),
        .Q(\word_aligned_data_r_reg[27]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[24]_0 [0]),
        .Q(\word_aligned_data_r_reg[27]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[3]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[4]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[5]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[6]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[7]_i_1_n_0 ),
        .Q(\word_aligned_data_r_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[8]_i_1_n_0 ),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r[9]_i_1_n_0 ),
        .Q(p_0_in[2]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER
   (SHIFTED_DATA_Buffer,
    \SHIFTED_DATA_Buffer_reg[15]_0 ,
    \SHIFTED_DATA_Buffer_reg[14]_0 ,
    \SHIFTED_DATA_Buffer_reg[13]_0 ,
    \SHIFTED_DATA_Buffer_reg[12]_0 ,
    \SHIFTED_DATA_Buffer_reg[11]_0 ,
    \SHIFTED_DATA_Buffer_reg[10]_0 ,
    \SHIFTED_DATA_Buffer_reg[9]_0 ,
    \SHIFTED_DATA_Buffer_reg[8]_0 ,
    \SHIFTED_DATA_Buffer_reg[7]_0 ,
    \SHIFTED_DATA_Buffer_reg[6]_0 ,
    \SHIFTED_DATA_Buffer_reg[5]_0 ,
    \SHIFTED_DATA_Buffer_reg[4]_0 ,
    \SHIFTED_DATA_Buffer_reg[3]_0 ,
    \SHIFTED_DATA_Buffer_reg[2]_0 ,
    \SHIFTED_DATA_Buffer_reg[1]_0 ,
    \SHIFTED_DATA_Buffer_reg[0]_0 ,
    \SHIFTED_DATA_Buffer_reg[0]_1 ,
    BARREL_SHIFTER_CONTROL_Buffer,
    user_clk,
    UFC_OUTPUT_SELECT_Buffer,
    \MUXED_DATA_Buffer_reg[31] ,
    \MUXED_DATA_Buffer_reg[30] ,
    \MUXED_DATA_Buffer_reg[29] ,
    \MUXED_DATA_Buffer_reg[28] ,
    \MUXED_DATA_Buffer_reg[27] ,
    \MUXED_DATA_Buffer_reg[26] ,
    \MUXED_DATA_Buffer_reg[25] ,
    \MUXED_DATA_Buffer_reg[24] ,
    \MUXED_DATA_Buffer_reg[23] ,
    \MUXED_DATA_Buffer_reg[22] ,
    \MUXED_DATA_Buffer_reg[21] ,
    \MUXED_DATA_Buffer_reg[20] ,
    \MUXED_DATA_Buffer_reg[19] ,
    \MUXED_DATA_Buffer_reg[18] ,
    \MUXED_DATA_Buffer_reg[17] ,
    \MUXED_DATA_Buffer_reg[16] );
  output [0:31]SHIFTED_DATA_Buffer;
  output \SHIFTED_DATA_Buffer_reg[15]_0 ;
  output \SHIFTED_DATA_Buffer_reg[14]_0 ;
  output \SHIFTED_DATA_Buffer_reg[13]_0 ;
  output \SHIFTED_DATA_Buffer_reg[12]_0 ;
  output \SHIFTED_DATA_Buffer_reg[11]_0 ;
  output \SHIFTED_DATA_Buffer_reg[10]_0 ;
  output \SHIFTED_DATA_Buffer_reg[9]_0 ;
  output \SHIFTED_DATA_Buffer_reg[8]_0 ;
  output \SHIFTED_DATA_Buffer_reg[7]_0 ;
  output \SHIFTED_DATA_Buffer_reg[6]_0 ;
  output \SHIFTED_DATA_Buffer_reg[5]_0 ;
  output \SHIFTED_DATA_Buffer_reg[4]_0 ;
  output \SHIFTED_DATA_Buffer_reg[3]_0 ;
  output \SHIFTED_DATA_Buffer_reg[2]_0 ;
  output \SHIFTED_DATA_Buffer_reg[1]_0 ;
  output \SHIFTED_DATA_Buffer_reg[0]_0 ;
  input [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
  input BARREL_SHIFTER_CONTROL_Buffer;
  input user_clk;
  input [0:0]UFC_OUTPUT_SELECT_Buffer;
  input \MUXED_DATA_Buffer_reg[31] ;
  input \MUXED_DATA_Buffer_reg[30] ;
  input \MUXED_DATA_Buffer_reg[29] ;
  input \MUXED_DATA_Buffer_reg[28] ;
  input \MUXED_DATA_Buffer_reg[27] ;
  input \MUXED_DATA_Buffer_reg[26] ;
  input \MUXED_DATA_Buffer_reg[25] ;
  input \MUXED_DATA_Buffer_reg[24] ;
  input \MUXED_DATA_Buffer_reg[23] ;
  input \MUXED_DATA_Buffer_reg[22] ;
  input \MUXED_DATA_Buffer_reg[21] ;
  input \MUXED_DATA_Buffer_reg[20] ;
  input \MUXED_DATA_Buffer_reg[19] ;
  input \MUXED_DATA_Buffer_reg[18] ;
  input \MUXED_DATA_Buffer_reg[17] ;
  input \MUXED_DATA_Buffer_reg[16] ;

  wire BARREL_SHIFTER_CONTROL_Buffer;
  wire \MUXED_DATA_Buffer_reg[16] ;
  wire \MUXED_DATA_Buffer_reg[17] ;
  wire \MUXED_DATA_Buffer_reg[18] ;
  wire \MUXED_DATA_Buffer_reg[19] ;
  wire \MUXED_DATA_Buffer_reg[20] ;
  wire \MUXED_DATA_Buffer_reg[21] ;
  wire \MUXED_DATA_Buffer_reg[22] ;
  wire \MUXED_DATA_Buffer_reg[23] ;
  wire \MUXED_DATA_Buffer_reg[24] ;
  wire \MUXED_DATA_Buffer_reg[25] ;
  wire \MUXED_DATA_Buffer_reg[26] ;
  wire \MUXED_DATA_Buffer_reg[27] ;
  wire \MUXED_DATA_Buffer_reg[28] ;
  wire \MUXED_DATA_Buffer_reg[29] ;
  wire \MUXED_DATA_Buffer_reg[30] ;
  wire \MUXED_DATA_Buffer_reg[31] ;
  wire [0:31]SHIFTED_DATA_Buffer;
  wire \SHIFTED_DATA_Buffer_reg[0]_0 ;
  wire [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[10]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[11]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[12]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[13]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[14]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[15]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[1]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[2]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[3]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[4]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[5]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[6]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[7]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[8]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[9]_0 ;
  wire [0:0]UFC_OUTPUT_SELECT_Buffer;
  wire [0:15]shifted_data_c;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[16]_i_1 
       (.I0(SHIFTED_DATA_Buffer[0]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[16] ),
        .O(\SHIFTED_DATA_Buffer_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[17]_i_1 
       (.I0(SHIFTED_DATA_Buffer[1]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[17] ),
        .O(\SHIFTED_DATA_Buffer_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[18]_i_1 
       (.I0(SHIFTED_DATA_Buffer[2]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[18] ),
        .O(\SHIFTED_DATA_Buffer_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[19]_i_1 
       (.I0(SHIFTED_DATA_Buffer[3]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[19] ),
        .O(\SHIFTED_DATA_Buffer_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[20]_i_1 
       (.I0(SHIFTED_DATA_Buffer[4]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[20] ),
        .O(\SHIFTED_DATA_Buffer_reg[4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[21]_i_1 
       (.I0(SHIFTED_DATA_Buffer[5]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[21] ),
        .O(\SHIFTED_DATA_Buffer_reg[5]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[22]_i_1 
       (.I0(SHIFTED_DATA_Buffer[6]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[22] ),
        .O(\SHIFTED_DATA_Buffer_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[23]_i_1 
       (.I0(SHIFTED_DATA_Buffer[7]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[23] ),
        .O(\SHIFTED_DATA_Buffer_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[24]_i_1 
       (.I0(SHIFTED_DATA_Buffer[8]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[24] ),
        .O(\SHIFTED_DATA_Buffer_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[25]_i_1 
       (.I0(SHIFTED_DATA_Buffer[9]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[25] ),
        .O(\SHIFTED_DATA_Buffer_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[26]_i_1 
       (.I0(SHIFTED_DATA_Buffer[10]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[26] ),
        .O(\SHIFTED_DATA_Buffer_reg[10]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[27]_i_1 
       (.I0(SHIFTED_DATA_Buffer[11]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[27] ),
        .O(\SHIFTED_DATA_Buffer_reg[11]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[28]_i_1 
       (.I0(SHIFTED_DATA_Buffer[12]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[28] ),
        .O(\SHIFTED_DATA_Buffer_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[29]_i_1 
       (.I0(SHIFTED_DATA_Buffer[13]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[29] ),
        .O(\SHIFTED_DATA_Buffer_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[30]_i_1 
       (.I0(SHIFTED_DATA_Buffer[14]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[30] ),
        .O(\SHIFTED_DATA_Buffer_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[31]_i_1 
       (.I0(SHIFTED_DATA_Buffer[15]),
        .I1(UFC_OUTPUT_SELECT_Buffer),
        .I2(\MUXED_DATA_Buffer_reg[31] ),
        .O(\SHIFTED_DATA_Buffer_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[0]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [31]),
        .O(shifted_data_c[0]));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[10]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [21]),
        .O(shifted_data_c[10]));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[11]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [20]),
        .O(shifted_data_c[11]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[12]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [19]),
        .O(shifted_data_c[12]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[13]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [18]),
        .O(shifted_data_c[13]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[14]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [17]),
        .O(shifted_data_c[14]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[15]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [16]),
        .O(shifted_data_c[15]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[1]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [30]),
        .O(shifted_data_c[1]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[2]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [29]),
        .O(shifted_data_c[2]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[3]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [28]),
        .O(shifted_data_c[3]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[4]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [27]),
        .O(shifted_data_c[4]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[5]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [26]),
        .O(shifted_data_c[5]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[6]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [25]),
        .O(shifted_data_c[6]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[7]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [24]),
        .O(shifted_data_c[7]));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[8]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [23]),
        .O(shifted_data_c[8]));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[9]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
        .I1(BARREL_SHIFTER_CONTROL_Buffer),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_1 [22]),
        .O(shifted_data_c[9]));
  FDRE \SHIFTED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[0]),
        .Q(SHIFTED_DATA_Buffer[0]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[10]),
        .Q(SHIFTED_DATA_Buffer[10]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[11]),
        .Q(SHIFTED_DATA_Buffer[11]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[12]),
        .Q(SHIFTED_DATA_Buffer[12]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[13]),
        .Q(SHIFTED_DATA_Buffer[13]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[14]),
        .Q(SHIFTED_DATA_Buffer[14]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[15]),
        .Q(SHIFTED_DATA_Buffer[15]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
        .Q(SHIFTED_DATA_Buffer[16]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
        .Q(SHIFTED_DATA_Buffer[17]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
        .Q(SHIFTED_DATA_Buffer[18]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
        .Q(SHIFTED_DATA_Buffer[19]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[1]),
        .Q(SHIFTED_DATA_Buffer[1]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
        .Q(SHIFTED_DATA_Buffer[20]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
        .Q(SHIFTED_DATA_Buffer[21]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
        .Q(SHIFTED_DATA_Buffer[22]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
        .Q(SHIFTED_DATA_Buffer[23]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
        .Q(SHIFTED_DATA_Buffer[24]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
        .Q(SHIFTED_DATA_Buffer[25]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
        .Q(SHIFTED_DATA_Buffer[26]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
        .Q(SHIFTED_DATA_Buffer[27]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
        .Q(SHIFTED_DATA_Buffer[28]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
        .Q(SHIFTED_DATA_Buffer[29]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[2]),
        .Q(SHIFTED_DATA_Buffer[2]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
        .Q(SHIFTED_DATA_Buffer[30]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
        .Q(SHIFTED_DATA_Buffer[31]),
        .R(BARREL_SHIFTER_CONTROL_Buffer));
  FDRE \SHIFTED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[3]),
        .Q(SHIFTED_DATA_Buffer[3]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[4]),
        .Q(SHIFTED_DATA_Buffer[4]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[5]),
        .Q(SHIFTED_DATA_Buffer[5]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[6]),
        .Q(SHIFTED_DATA_Buffer[6]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[7]),
        .Q(SHIFTED_DATA_Buffer[7]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[8]),
        .Q(SHIFTED_DATA_Buffer[8]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[9]),
        .Q(SHIFTED_DATA_Buffer[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_BARREL_SHIFTER_CONTROL
   (BARREL_SHIFTER_CONTROL_Buffer,
    barrel_shifter_control_i,
    user_clk);
  output BARREL_SHIFTER_CONTROL_Buffer;
  input barrel_shifter_control_i;
  input user_clk;

  wire BARREL_SHIFTER_CONTROL_Buffer;
  wire barrel_shifter_control_i;
  wire user_clk;

  FDRE \BARREL_SHIFTER_CONTROL_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(barrel_shifter_control_i),
        .Q(BARREL_SHIFTER_CONTROL_Buffer),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_FILTER" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_FILTER
   (UFC_START,
    barrel_shifter_control_i,
    D,
    \PDU_ECP_Buffer_reg[0]_0 ,
    \word_aligned_data_r_reg[0] ,
    \word_aligned_data_r_reg[1] ,
    \word_aligned_data_r_reg[2] ,
    \word_aligned_data_r_reg[3] ,
    \word_aligned_data_r_reg[4] ,
    \word_aligned_data_r_reg[5] ,
    \word_aligned_data_r_reg[6] ,
    \word_aligned_data_r_reg[7] ,
    \RX_PE_DATA_Buffer_reg[8] ,
    \RX_PE_DATA_Buffer_reg[9] ,
    \RX_PE_DATA_Buffer_reg[10] ,
    \word_aligned_data_r_reg[11] ,
    \word_aligned_data_r_reg[12] ,
    \word_aligned_data_r_reg[13] ,
    \word_aligned_data_r_reg[14] ,
    \word_aligned_data_r_reg[15] ,
    \word_aligned_data_r_reg[16] ,
    \word_aligned_data_r_reg[17] ,
    \word_aligned_data_r_reg[18] ,
    \word_aligned_data_r_reg[19] ,
    \word_aligned_data_r_reg[20] ,
    \word_aligned_data_r_reg[21] ,
    \word_aligned_data_r_reg[22] ,
    \word_aligned_data_r_reg[23] ,
    \RX_PE_DATA_Buffer_reg[24] ,
    \RX_PE_DATA_Buffer_reg[25] ,
    \RX_PE_DATA_Buffer_reg[26] ,
    \word_aligned_data_r_reg[27] ,
    \word_aligned_data_r_reg[28] ,
    \word_aligned_data_r_reg[29] ,
    \word_aligned_data_r_reg[30] ,
    \word_aligned_data_r_reg[31] ,
    \PDU_PAD_Buffer_reg[0]_0 ,
    \PDU_ECP_Buffer_reg[1]_0 ,
    \PDU_ECP_Buffer_reg[0]_1 ,
    Q,
    \UFC_DATA_V_Buffer_reg[0]_0 ,
    \PDU_SCP_Buffer_reg[1]_0 ,
    S1_in,
    RESET,
    neqOp,
    user_clk,
    \rx_suf_r_reg[0]_0 ,
    p_8_out,
    p_9_out,
    p_2_out,
    \stage_1_data_r_reg[0] ,
    RX_PE_DATA,
    \stage_1_data_r_reg[11] ,
    \stage_1_data_r_reg[16] ,
    \stage_1_data_r_reg[27] ,
    \stage_1_count_value_r_reg[0]_0 ,
    \stage_1_count_value_r_reg[1]_0 ,
    \stage_1_count_value_r_reg[2]_0 ,
    \stage_1_count_value_r_reg[3]_0 ,
    \rx_data_v_r_reg[0]_0 );
  output UFC_START;
  output barrel_shifter_control_i;
  output [1:0]D;
  output [1:0]\PDU_ECP_Buffer_reg[0]_0 ;
  output \word_aligned_data_r_reg[0] ;
  output \word_aligned_data_r_reg[1] ;
  output \word_aligned_data_r_reg[2] ;
  output \word_aligned_data_r_reg[3] ;
  output \word_aligned_data_r_reg[4] ;
  output \word_aligned_data_r_reg[5] ;
  output \word_aligned_data_r_reg[6] ;
  output \word_aligned_data_r_reg[7] ;
  output \RX_PE_DATA_Buffer_reg[8] ;
  output \RX_PE_DATA_Buffer_reg[9] ;
  output \RX_PE_DATA_Buffer_reg[10] ;
  output \word_aligned_data_r_reg[11] ;
  output \word_aligned_data_r_reg[12] ;
  output \word_aligned_data_r_reg[13] ;
  output \word_aligned_data_r_reg[14] ;
  output \word_aligned_data_r_reg[15] ;
  output \word_aligned_data_r_reg[16] ;
  output \word_aligned_data_r_reg[17] ;
  output \word_aligned_data_r_reg[18] ;
  output \word_aligned_data_r_reg[19] ;
  output \word_aligned_data_r_reg[20] ;
  output \word_aligned_data_r_reg[21] ;
  output \word_aligned_data_r_reg[22] ;
  output \word_aligned_data_r_reg[23] ;
  output \RX_PE_DATA_Buffer_reg[24] ;
  output \RX_PE_DATA_Buffer_reg[25] ;
  output \RX_PE_DATA_Buffer_reg[26] ;
  output \word_aligned_data_r_reg[27] ;
  output \word_aligned_data_r_reg[28] ;
  output \word_aligned_data_r_reg[29] ;
  output \word_aligned_data_r_reg[30] ;
  output \word_aligned_data_r_reg[31] ;
  output \PDU_PAD_Buffer_reg[0]_0 ;
  output \PDU_ECP_Buffer_reg[1]_0 ;
  output \PDU_ECP_Buffer_reg[0]_1 ;
  output [1:0]Q;
  output [1:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
  output \PDU_SCP_Buffer_reg[1]_0 ;
  output S1_in;
  input RESET;
  input neqOp;
  input user_clk;
  input [1:0]\rx_suf_r_reg[0]_0 ;
  input [1:0]p_8_out;
  input [1:0]p_9_out;
  input [1:0]p_2_out;
  input [7:0]\stage_1_data_r_reg[0] ;
  input [5:0]RX_PE_DATA;
  input [4:0]\stage_1_data_r_reg[11] ;
  input [7:0]\stage_1_data_r_reg[16] ;
  input [4:0]\stage_1_data_r_reg[27] ;
  input \stage_1_count_value_r_reg[0]_0 ;
  input \stage_1_count_value_r_reg[1]_0 ;
  input \stage_1_count_value_r_reg[2]_0 ;
  input \stage_1_count_value_r_reg[3]_0 ;
  input [1:0]\rx_data_v_r_reg[0]_0 ;

  wire [1:0]D;
  wire [0:1]L;
  wire \PDU_DATA_V_Buffer[0]_i_1_n_0 ;
  wire \PDU_DATA_V_Buffer[1]_i_1_n_0 ;
  wire [1:0]\PDU_ECP_Buffer_reg[0]_0 ;
  wire \PDU_ECP_Buffer_reg[0]_1 ;
  wire \PDU_ECP_Buffer_reg[1]_0 ;
  wire [0:1]PDU_PAD;
  wire \PDU_PAD_Buffer_reg[0]_0 ;
  wire \PDU_SCP_Buffer_reg[1]_0 ;
  wire [1:0]Q;
  wire RESET;
  wire [5:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[10] ;
  wire \RX_PE_DATA_Buffer_reg[24] ;
  wire \RX_PE_DATA_Buffer_reg[25] ;
  wire \RX_PE_DATA_Buffer_reg[26] ;
  wire \RX_PE_DATA_Buffer_reg[8] ;
  wire \RX_PE_DATA_Buffer_reg[9] ;
  wire S1_in;
  wire \UFC_DATA_V_Buffer[1]_i_1_n_0 ;
  wire [1:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
  wire UFC_START;
  wire UFC_START_Buffer_i_1_n_0;
  wire barrel_shifter_control_i;
  wire load_ufc_control_code_r;
  wire neqOp;
  wire [1:0]p_2_out;
  wire [1:0]p_8_out;
  wire [1:0]p_9_out;
  wire [0:1]rx_data_v_r;
  wire [1:0]\rx_data_v_r_reg[0]_0 ;
  wire \rx_ecp_r_reg[0]_srl2_n_0 ;
  wire \rx_ecp_r_reg[1]_srl2_n_0 ;
  wire \rx_pad_r_reg[0]_srl2_n_0 ;
  wire \rx_pad_r_reg[1]_srl2_n_0 ;
  wire \rx_scp_r_reg[0]_srl2_n_0 ;
  wire \rx_scp_r_reg[1]_srl2_n_0 ;
  wire [1:0]\rx_suf_r_reg[0]_0 ;
  wire \rx_suf_r_reg_n_0_[1] ;
  wire [0:3]stage_1_count_value_r;
  wire \stage_1_count_value_r_reg[0]_0 ;
  wire \stage_1_count_value_r_reg[1]_0 ;
  wire \stage_1_count_value_r_reg[2]_0 ;
  wire \stage_1_count_value_r_reg[3]_0 ;
  wire [7:0]\stage_1_data_r_reg[0] ;
  wire [4:0]\stage_1_data_r_reg[11] ;
  wire [7:0]\stage_1_data_r_reg[16] ;
  wire [4:0]\stage_1_data_r_reg[27] ;
  wire [0:3]stage_2_count_value_r;
  wire \stage_2_count_value_r[0]_i_1_n_0 ;
  wire \stage_2_count_value_r[1]_i_1_n_0 ;
  wire \stage_2_count_value_r[2]_i_1_n_0 ;
  wire \stage_2_count_value_r[3]_i_1_n_0 ;
  wire [0:0]stage_2_lane_mask_c__0;
  wire user_clk;
  wire \word_aligned_data_r_reg[0] ;
  wire \word_aligned_data_r_reg[11] ;
  wire \word_aligned_data_r_reg[12] ;
  wire \word_aligned_data_r_reg[13] ;
  wire \word_aligned_data_r_reg[14] ;
  wire \word_aligned_data_r_reg[15] ;
  wire \word_aligned_data_r_reg[16] ;
  wire \word_aligned_data_r_reg[17] ;
  wire \word_aligned_data_r_reg[18] ;
  wire \word_aligned_data_r_reg[19] ;
  wire \word_aligned_data_r_reg[1] ;
  wire \word_aligned_data_r_reg[20] ;
  wire \word_aligned_data_r_reg[21] ;
  wire \word_aligned_data_r_reg[22] ;
  wire \word_aligned_data_r_reg[23] ;
  wire \word_aligned_data_r_reg[27] ;
  wire \word_aligned_data_r_reg[28] ;
  wire \word_aligned_data_r_reg[29] ;
  wire \word_aligned_data_r_reg[2] ;
  wire \word_aligned_data_r_reg[30] ;
  wire \word_aligned_data_r_reg[31] ;
  wire \word_aligned_data_r_reg[3] ;
  wire \word_aligned_data_r_reg[4] ;
  wire \word_aligned_data_r_reg[5] ;
  wire \word_aligned_data_r_reg[6] ;
  wire \word_aligned_data_r_reg[7] ;

  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[0]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[0]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [7]),
        .Q(\word_aligned_data_r_reg[0] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[10]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[10]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[3]),
        .Q(\RX_PE_DATA_Buffer_reg[10] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[11]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[11]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [4]),
        .Q(\word_aligned_data_r_reg[11] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[12]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[12]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [3]),
        .Q(\word_aligned_data_r_reg[12] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[13]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[13]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [2]),
        .Q(\word_aligned_data_r_reg[13] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[14]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[14]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [1]),
        .Q(\word_aligned_data_r_reg[14] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[15]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[15]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [0]),
        .Q(\word_aligned_data_r_reg[15] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[16]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[16]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [7]),
        .Q(\word_aligned_data_r_reg[16] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[17]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[17]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [6]),
        .Q(\word_aligned_data_r_reg[17] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[18]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[18]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [5]),
        .Q(\word_aligned_data_r_reg[18] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[19]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[19]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [4]),
        .Q(\word_aligned_data_r_reg[19] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[1]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[1]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [6]),
        .Q(\word_aligned_data_r_reg[1] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[20]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[20]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [3]),
        .Q(\word_aligned_data_r_reg[20] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[21]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[21]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [2]),
        .Q(\word_aligned_data_r_reg[21] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[22]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[22]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [1]),
        .Q(\word_aligned_data_r_reg[22] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[23]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[23]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [0]),
        .Q(\word_aligned_data_r_reg[23] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[24]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[24]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[2]),
        .Q(\RX_PE_DATA_Buffer_reg[24] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[25]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[25]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[1]),
        .Q(\RX_PE_DATA_Buffer_reg[25] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[26]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[26]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[0]),
        .Q(\RX_PE_DATA_Buffer_reg[26] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[27]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[27]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[27] [4]),
        .Q(\word_aligned_data_r_reg[27] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[28]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[28]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[27] [3]),
        .Q(\word_aligned_data_r_reg[28] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[29]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[29]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[27] [2]),
        .Q(\word_aligned_data_r_reg[29] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[2]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[2]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [5]),
        .Q(\word_aligned_data_r_reg[2] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[30]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[30]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[27] [1]),
        .Q(\word_aligned_data_r_reg[30] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[31]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[31]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[27] [0]),
        .Q(\word_aligned_data_r_reg[31] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[3]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[3]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [4]),
        .Q(\word_aligned_data_r_reg[3] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[4]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[4]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [3]),
        .Q(\word_aligned_data_r_reg[4] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[5]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[5]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [2]),
        .Q(\word_aligned_data_r_reg[5] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[6]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[6]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [1]),
        .Q(\word_aligned_data_r_reg[6] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[7]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[7]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [0]),
        .Q(\word_aligned_data_r_reg[7] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[8]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[8]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[5]),
        .Q(\RX_PE_DATA_Buffer_reg[8] ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[9]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[9]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[4]),
        .Q(\RX_PE_DATA_Buffer_reg[9] ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT5 #(
    .INIT(32'h88888882)) 
    \PDU_DATA_V_Buffer[0]_i_1 
       (.I0(rx_data_v_r[0]),
        .I1(stage_2_count_value_r[0]),
        .I2(stage_2_count_value_r[1]),
        .I3(stage_2_count_value_r[2]),
        .I4(stage_2_count_value_r[3]),
        .O(\PDU_DATA_V_Buffer[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AA02A802)) 
    \PDU_DATA_V_Buffer[1]_i_1 
       (.I0(rx_data_v_r[1]),
        .I1(stage_2_count_value_r[2]),
        .I2(stage_2_count_value_r[1]),
        .I3(stage_2_count_value_r[0]),
        .I4(stage_2_count_value_r[3]),
        .I5(L[0]),
        .O(\PDU_DATA_V_Buffer[1]_i_1_n_0 ));
  FDRE \PDU_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\PDU_DATA_V_Buffer[0]_i_1_n_0 ),
        .Q(Q[1]),
        .R(RESET));
  FDRE \PDU_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\PDU_DATA_V_Buffer[1]_i_1_n_0 ),
        .Q(Q[0]),
        .R(RESET));
  FDRE \PDU_ECP_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_ecp_r_reg[0]_srl2_n_0 ),
        .Q(\PDU_ECP_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \PDU_ECP_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_ecp_r_reg[1]_srl2_n_0 ),
        .Q(\PDU_ECP_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \PDU_PAD_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_pad_r_reg[0]_srl2_n_0 ),
        .Q(PDU_PAD[0]),
        .R(1'b0));
  FDRE \PDU_PAD_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_pad_r_reg[1]_srl2_n_0 ),
        .Q(PDU_PAD[1]),
        .R(1'b0));
  FDRE \PDU_SCP_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_scp_r_reg[0]_srl2_n_0 ),
        .Q(D[1]),
        .R(1'b0));
  FDRE \PDU_SCP_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_scp_r_reg[1]_srl2_n_0 ),
        .Q(D[0]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAFAFAFBA)) 
    \UFC_DATA_V_Buffer[1]_i_1 
       (.I0(L[0]),
        .I1(stage_2_count_value_r[3]),
        .I2(stage_2_count_value_r[0]),
        .I3(stage_2_count_value_r[1]),
        .I4(stage_2_count_value_r[2]),
        .O(\UFC_DATA_V_Buffer[1]_i_1_n_0 ));
  FDRE \UFC_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_2_lane_mask_c__0),
        .Q(\UFC_DATA_V_Buffer_reg[0]_0 [1]),
        .R(RESET));
  FDRE \UFC_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_DATA_V_Buffer[1]_i_1_n_0 ),
        .Q(\UFC_DATA_V_Buffer_reg[0]_0 [0]),
        .R(RESET));
  FDRE \UFC_MESSAGE_START_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(L[0]),
        .Q(barrel_shifter_control_i),
        .R(RESET));
  LUT2 #(
    .INIT(4'hE)) 
    UFC_START_Buffer_i_1
       (.I0(L[0]),
        .I1(L[1]),
        .O(UFC_START_Buffer_i_1_n_0));
  FDRE UFC_START_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_START_Buffer_i_1_n_0),
        .Q(UFC_START),
        .R(RESET));
  LUT1 #(
    .INIT(2'h1)) 
    data_after_start_muxcy_0_i_1
       (.I0(D[1]),
        .O(S1_in));
  LUT1 #(
    .INIT(2'h1)) 
    data_after_start_muxcy_1_i_1
       (.I0(D[0]),
        .O(\PDU_SCP_Buffer_reg[1]_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    in_frame_muxcy_0_i_1
       (.I0(\PDU_ECP_Buffer_reg[0]_0 [1]),
        .I1(D[1]),
        .O(\PDU_ECP_Buffer_reg[0]_1 ));
  LUT2 #(
    .INIT(4'h1)) 
    in_frame_muxcy_1_i_1
       (.I0(\PDU_ECP_Buffer_reg[0]_0 [0]),
        .I1(D[0]),
        .O(\PDU_ECP_Buffer_reg[1]_0 ));
  FDRE load_ufc_control_code_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(neqOp),
        .Q(load_ufc_control_code_r),
        .R(RESET));
  FDRE \rx_data_v_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_data_v_r_reg[0]_0 [1]),
        .Q(rx_data_v_r[0]),
        .R(RESET));
  FDRE \rx_data_v_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_data_v_r_reg[0]_0 [0]),
        .Q(rx_data_v_r[1]),
        .R(RESET));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[0]_srl2 " *) 
  SRL16E \rx_ecp_r_reg[0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_9_out[1]),
        .Q(\rx_ecp_r_reg[0]_srl2_n_0 ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_ecp_r_reg[1]_srl2 " *) 
  SRL16E \rx_ecp_r_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_9_out[0]),
        .Q(\rx_ecp_r_reg[1]_srl2_n_0 ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg[0]_srl2 " *) 
  SRL16E \rx_pad_r_reg[0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_2_out[1]),
        .Q(\rx_pad_r_reg[0]_srl2_n_0 ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_pad_r_reg[1]_srl2 " *) 
  SRL16E \rx_pad_r_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_2_out[0]),
        .Q(\rx_pad_r_reg[1]_srl2_n_0 ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg[0]_srl2 " *) 
  SRL16E \rx_scp_r_reg[0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_8_out[1]),
        .Q(\rx_scp_r_reg[0]_srl2_n_0 ));
  (* srl_bus_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg " *) 
  (* srl_name = "U0/\aurora_1ln_rx_lpm_rx_ll_i/ufc_filter_i/rx_scp_r_reg[1]_srl2 " *) 
  SRL16E \rx_scp_r_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_8_out[0]),
        .Q(\rx_scp_r_reg[1]_srl2_n_0 ));
  FDRE \rx_suf_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg[0]_0 [1]),
        .Q(L[0]),
        .R(RESET));
  FDRE \rx_suf_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg[0]_0 [0]),
        .Q(\rx_suf_r_reg_n_0_[1] ),
        .R(RESET));
  FDRE save_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg_n_0_[1] ),
        .Q(L[1]),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[0]_0 ),
        .Q(stage_1_count_value_r[0]),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[1]_0 ),
        .Q(stage_1_count_value_r[1]),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[2]_0 ),
        .Q(stage_1_count_value_r[2]),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[3]_0 ),
        .Q(stage_1_count_value_r[3]),
        .R(RESET));
  LUT2 #(
    .INIT(4'hE)) 
    stage_1_pad_r_i_1
       (.I0(PDU_PAD[0]),
        .I1(PDU_PAD[1]),
        .O(\PDU_PAD_Buffer_reg[0]_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \stage_2_count_value_r[0]_i_1 
       (.I0(load_ufc_control_code_r),
        .I1(stage_1_count_value_r[0]),
        .O(\stage_2_count_value_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8B888B88888888B8)) 
    \stage_2_count_value_r[1]_i_1 
       (.I0(stage_1_count_value_r[1]),
        .I1(load_ufc_control_code_r),
        .I2(stage_2_count_value_r[0]),
        .I3(stage_2_count_value_r[1]),
        .I4(stage_2_count_value_r[3]),
        .I5(stage_2_count_value_r[2]),
        .O(\stage_2_count_value_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h888B888B88888B88)) 
    \stage_2_count_value_r[2]_i_1 
       (.I0(stage_1_count_value_r[2]),
        .I1(load_ufc_control_code_r),
        .I2(stage_2_count_value_r[2]),
        .I3(stage_2_count_value_r[0]),
        .I4(stage_2_count_value_r[3]),
        .I5(stage_2_count_value_r[1]),
        .O(\stage_2_count_value_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8B8B8B8888888888)) 
    \stage_2_count_value_r[3]_i_1 
       (.I0(stage_1_count_value_r[3]),
        .I1(load_ufc_control_code_r),
        .I2(stage_2_count_value_r[0]),
        .I3(stage_2_count_value_r[2]),
        .I4(stage_2_count_value_r[1]),
        .I5(stage_2_count_value_r[3]),
        .O(\stage_2_count_value_r[3]_i_1_n_0 ));
  FDRE \stage_2_count_value_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[0]_i_1_n_0 ),
        .Q(stage_2_count_value_r[0]),
        .R(RESET));
  FDRE \stage_2_count_value_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[1]_i_1_n_0 ),
        .Q(stage_2_count_value_r[1]),
        .R(RESET));
  FDRE \stage_2_count_value_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[2]_i_1_n_0 ),
        .Q(stage_2_count_value_r[2]),
        .R(RESET));
  FDRE \stage_2_count_value_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[3]_i_1_n_0 ),
        .Q(stage_2_count_value_r[3]),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT4 #(
    .INIT(16'h01FE)) 
    stage_2_lane_mask_c
       (.I0(stage_2_count_value_r[3]),
        .I1(stage_2_count_value_r[2]),
        .I2(stage_2_count_value_r[1]),
        .I3(stage_2_count_value_r[0]),
        .O(stage_2_lane_mask_c__0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_OUTPUT_MUX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_MUX
   (M_AXI_UFC_RX_TDATA,
    D,
    user_clk,
    UFC_OUTPUT_SELECT_Buffer,
    \MUXED_DATA_Buffer_reg[16]_0 ,
    \MUXED_DATA_Buffer_reg[17]_0 ,
    \MUXED_DATA_Buffer_reg[18]_0 ,
    \MUXED_DATA_Buffer_reg[19]_0 ,
    \MUXED_DATA_Buffer_reg[20]_0 ,
    \MUXED_DATA_Buffer_reg[21]_0 ,
    \MUXED_DATA_Buffer_reg[22]_0 ,
    \MUXED_DATA_Buffer_reg[23]_0 ,
    \MUXED_DATA_Buffer_reg[24]_0 ,
    \MUXED_DATA_Buffer_reg[25]_0 ,
    \MUXED_DATA_Buffer_reg[26]_0 ,
    \MUXED_DATA_Buffer_reg[27]_0 ,
    \MUXED_DATA_Buffer_reg[28]_0 ,
    \MUXED_DATA_Buffer_reg[29]_0 ,
    \MUXED_DATA_Buffer_reg[30]_0 ,
    \MUXED_DATA_Buffer_reg[31]_0 );
  output [31:0]M_AXI_UFC_RX_TDATA;
  input [15:0]D;
  input user_clk;
  input [0:0]UFC_OUTPUT_SELECT_Buffer;
  input \MUXED_DATA_Buffer_reg[16]_0 ;
  input \MUXED_DATA_Buffer_reg[17]_0 ;
  input \MUXED_DATA_Buffer_reg[18]_0 ;
  input \MUXED_DATA_Buffer_reg[19]_0 ;
  input \MUXED_DATA_Buffer_reg[20]_0 ;
  input \MUXED_DATA_Buffer_reg[21]_0 ;
  input \MUXED_DATA_Buffer_reg[22]_0 ;
  input \MUXED_DATA_Buffer_reg[23]_0 ;
  input \MUXED_DATA_Buffer_reg[24]_0 ;
  input \MUXED_DATA_Buffer_reg[25]_0 ;
  input \MUXED_DATA_Buffer_reg[26]_0 ;
  input \MUXED_DATA_Buffer_reg[27]_0 ;
  input \MUXED_DATA_Buffer_reg[28]_0 ;
  input \MUXED_DATA_Buffer_reg[29]_0 ;
  input \MUXED_DATA_Buffer_reg[30]_0 ;
  input \MUXED_DATA_Buffer_reg[31]_0 ;

  wire [15:0]D;
  wire \MUXED_DATA_Buffer_reg[16]_0 ;
  wire \MUXED_DATA_Buffer_reg[17]_0 ;
  wire \MUXED_DATA_Buffer_reg[18]_0 ;
  wire \MUXED_DATA_Buffer_reg[19]_0 ;
  wire \MUXED_DATA_Buffer_reg[20]_0 ;
  wire \MUXED_DATA_Buffer_reg[21]_0 ;
  wire \MUXED_DATA_Buffer_reg[22]_0 ;
  wire \MUXED_DATA_Buffer_reg[23]_0 ;
  wire \MUXED_DATA_Buffer_reg[24]_0 ;
  wire \MUXED_DATA_Buffer_reg[25]_0 ;
  wire \MUXED_DATA_Buffer_reg[26]_0 ;
  wire \MUXED_DATA_Buffer_reg[27]_0 ;
  wire \MUXED_DATA_Buffer_reg[28]_0 ;
  wire \MUXED_DATA_Buffer_reg[29]_0 ;
  wire \MUXED_DATA_Buffer_reg[30]_0 ;
  wire \MUXED_DATA_Buffer_reg[31]_0 ;
  wire [31:0]M_AXI_UFC_RX_TDATA;
  wire [0:0]UFC_OUTPUT_SELECT_Buffer;
  wire user_clk;

  FDRE \MUXED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[15]),
        .Q(M_AXI_UFC_RX_TDATA[7]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[5]),
        .Q(M_AXI_UFC_RX_TDATA[13]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[4]),
        .Q(M_AXI_UFC_RX_TDATA[12]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(M_AXI_UFC_RX_TDATA[11]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(M_AXI_UFC_RX_TDATA[10]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(M_AXI_UFC_RX_TDATA[9]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(M_AXI_UFC_RX_TDATA[8]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[16]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[23]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[17]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[22]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[18]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[21]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[19]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[20]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[14]),
        .Q(M_AXI_UFC_RX_TDATA[6]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[20]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[19]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[21]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[18]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[22]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[17]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[23]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[16]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[24]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[31]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[25]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[30]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[26]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[29]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[27]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[28]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[28]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[27]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[29]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[26]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[13]),
        .Q(M_AXI_UFC_RX_TDATA[5]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[30]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[25]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[31]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[24]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[12]),
        .Q(M_AXI_UFC_RX_TDATA[4]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[11]),
        .Q(M_AXI_UFC_RX_TDATA[3]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[10]),
        .Q(M_AXI_UFC_RX_TDATA[2]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[9]),
        .Q(M_AXI_UFC_RX_TDATA[1]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[8]),
        .Q(M_AXI_UFC_RX_TDATA[0]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[7]),
        .Q(M_AXI_UFC_RX_TDATA[15]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[6]),
        .Q(M_AXI_UFC_RX_TDATA[14]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_OUTPUT_SWITCH_CONTROL
   (UFC_OUTPUT_SELECT_Buffer,
    Q,
    \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ,
    user_clk);
  output [1:0]UFC_OUTPUT_SELECT_Buffer;
  input [1:0]Q;
  input \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ;
  input user_clk;

  wire [1:0]Q;
  wire [1:0]UFC_OUTPUT_SELECT_Buffer;
  wire \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ;
  wire \UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ;
  wire user_clk;

  LUT2 #(
    .INIT(4'h4)) 
    \UFC_OUTPUT_SELECT_Buffer[5]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer_reg[4]_0 ),
        .Q(UFC_OUTPUT_SELECT_Buffer[1]),
        .R(1'b0));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ),
        .Q(UFC_OUTPUT_SELECT_Buffer[0]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_SIDEBAND_OUTPUT
   (\UFC_REM_Buffer_reg[0]_0 ,
    UFC_SRC_RDY_N_Buffer,
    UFC_EOF_N_Buffer,
    \UFC_REM_Buffer_reg[0]_1 ,
    user_clk,
    RESET,
    UFC_SRC_RDY_N_Buffer_reg_0,
    UFC_EOF_N_Buffer_reg_0);
  output \UFC_REM_Buffer_reg[0]_0 ;
  output UFC_SRC_RDY_N_Buffer;
  output UFC_EOF_N_Buffer;
  input \UFC_REM_Buffer_reg[0]_1 ;
  input user_clk;
  input RESET;
  input UFC_SRC_RDY_N_Buffer_reg_0;
  input UFC_EOF_N_Buffer_reg_0;

  wire RESET;
  wire UFC_EOF_N_Buffer;
  wire UFC_EOF_N_Buffer_reg_0;
  wire \UFC_REM_Buffer_reg[0]_0 ;
  wire \UFC_REM_Buffer_reg[0]_1 ;
  wire UFC_SRC_RDY_N_Buffer;
  wire UFC_SRC_RDY_N_Buffer_reg_0;
  wire user_clk;

  FDRE UFC_EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_EOF_N_Buffer_reg_0),
        .Q(UFC_EOF_N_Buffer),
        .R(1'b0));
  FDRE \UFC_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_REM_Buffer_reg[0]_1 ),
        .Q(\UFC_REM_Buffer_reg[0]_0 ),
        .R(1'b0));
  FDSE UFC_SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_SRC_RDY_N_Buffer_reg_0),
        .Q(UFC_SRC_RDY_N_Buffer),
        .S(RESET));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_COUNT_CONTROL
   (stage_1_ufc_start_r_reg,
    Q,
    \storage_count_r_reg[1]_0 ,
    \storage_count_r_reg[1]_1 ,
    D,
    \storage_count_r_reg[0]_0 ,
    stage_1_ufc_start_r_reg_0,
    stage_1_ufc_start_r,
    UFC_EOF_N_Buffer_reg,
    RESET,
    user_clk);
  output stage_1_ufc_start_r_reg;
  output [1:0]Q;
  output \storage_count_r_reg[1]_0 ;
  output \storage_count_r_reg[1]_1 ;
  output [0:0]D;
  output \storage_count_r_reg[0]_0 ;
  output stage_1_ufc_start_r_reg_0;
  input stage_1_ufc_start_r;
  input [1:0]UFC_EOF_N_Buffer_reg;
  input RESET;
  input user_clk;

  wire [0:0]D;
  wire [1:0]Q;
  wire RESET;
  wire [1:0]UFC_EOF_N_Buffer_reg;
  wire stage_1_ufc_start_r;
  wire stage_1_ufc_start_r_reg;
  wire stage_1_ufc_start_r_reg_0;
  wire [0:1]storage_count_c;
  wire \storage_count_r_reg[0]_0 ;
  wire \storage_count_r_reg[1]_0 ;
  wire \storage_count_r_reg[1]_1 ;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'h55547733)) 
    UFC_EOF_N_Buffer_i_1
       (.I0(stage_1_ufc_start_r),
        .I1(Q[0]),
        .I2(UFC_EOF_N_Buffer_reg[0]),
        .I3(UFC_EOF_N_Buffer_reg[1]),
        .I4(Q[1]),
        .O(stage_1_ufc_start_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT4 #(
    .INIT(16'h6433)) 
    \UFC_REM_Buffer[0]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(UFC_EOF_N_Buffer_reg[0]),
        .O(stage_1_ufc_start_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT2 #(
    .INIT(4'h1)) 
    UFC_SRC_RDY_N_Buffer_i_1
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\storage_count_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \UFC_STORAGE_SELECT_Buffer[0]_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\storage_count_r_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \UFC_STORAGE_SELECT_Buffer[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\storage_count_r_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'hABFF)) 
    \UFC_STORAGE_SELECT_Buffer[5]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(Q[1]),
        .I2(UFC_EOF_N_Buffer_reg[1]),
        .I3(Q[0]),
        .O(D));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT5 #(
    .INIT(32'h9CC8C8C8)) 
    \storage_count_r[0]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(UFC_EOF_N_Buffer_reg[1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(UFC_EOF_N_Buffer_reg[0]),
        .O(storage_count_c[0]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'hAAFE5400)) 
    \storage_count_r[1]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(UFC_EOF_N_Buffer_reg[1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(UFC_EOF_N_Buffer_reg[0]),
        .O(storage_count_c[1]));
  FDRE \storage_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(storage_count_c[0]),
        .Q(Q[1]),
        .R(RESET));
  FDRE \storage_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(storage_count_c[1]),
        .Q(Q[0]),
        .R(RESET));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_STORAGE_MUX" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_MUX
   (D,
    \MUXED_DATA_Buffer_reg[16]_0 ,
    \MUXED_DATA_Buffer_reg[17]_0 ,
    \MUXED_DATA_Buffer_reg[18]_0 ,
    \MUXED_DATA_Buffer_reg[19]_0 ,
    \MUXED_DATA_Buffer_reg[20]_0 ,
    \MUXED_DATA_Buffer_reg[21]_0 ,
    \MUXED_DATA_Buffer_reg[22]_0 ,
    \MUXED_DATA_Buffer_reg[23]_0 ,
    \MUXED_DATA_Buffer_reg[24]_0 ,
    \MUXED_DATA_Buffer_reg[25]_0 ,
    \MUXED_DATA_Buffer_reg[26]_0 ,
    \MUXED_DATA_Buffer_reg[27]_0 ,
    \MUXED_DATA_Buffer_reg[28]_0 ,
    \MUXED_DATA_Buffer_reg[29]_0 ,
    \MUXED_DATA_Buffer_reg[30]_0 ,
    \MUXED_DATA_Buffer_reg[31]_0 ,
    \MUXED_DATA_Buffer_reg[0]_0 ,
    user_clk,
    UFC_STORAGE_SELECT_Buffer,
    SHIFTED_DATA_Buffer);
  output [15:0]D;
  output \MUXED_DATA_Buffer_reg[16]_0 ;
  output \MUXED_DATA_Buffer_reg[17]_0 ;
  output \MUXED_DATA_Buffer_reg[18]_0 ;
  output \MUXED_DATA_Buffer_reg[19]_0 ;
  output \MUXED_DATA_Buffer_reg[20]_0 ;
  output \MUXED_DATA_Buffer_reg[21]_0 ;
  output \MUXED_DATA_Buffer_reg[22]_0 ;
  output \MUXED_DATA_Buffer_reg[23]_0 ;
  output \MUXED_DATA_Buffer_reg[24]_0 ;
  output \MUXED_DATA_Buffer_reg[25]_0 ;
  output \MUXED_DATA_Buffer_reg[26]_0 ;
  output \MUXED_DATA_Buffer_reg[27]_0 ;
  output \MUXED_DATA_Buffer_reg[28]_0 ;
  output \MUXED_DATA_Buffer_reg[29]_0 ;
  output \MUXED_DATA_Buffer_reg[30]_0 ;
  output \MUXED_DATA_Buffer_reg[31]_0 ;
  input \MUXED_DATA_Buffer_reg[0]_0 ;
  input user_clk;
  input [2:0]UFC_STORAGE_SELECT_Buffer;
  input [0:31]SHIFTED_DATA_Buffer;

  wire [15:0]D;
  wire \MUXED_DATA_Buffer[0]_i_2_n_0 ;
  wire \MUXED_DATA_Buffer[10]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[11]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[12]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[13]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[14]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[15]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[16]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[17]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[18]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[19]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[1]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[20]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[21]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[22]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[23]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[24]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[25]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[26]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[27]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[28]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[29]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[2]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[30]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[31]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[3]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[4]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[5]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[6]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[7]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[8]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer[9]_i_1_n_0 ;
  wire \MUXED_DATA_Buffer_reg[0]_0 ;
  wire \MUXED_DATA_Buffer_reg[16]_0 ;
  wire \MUXED_DATA_Buffer_reg[17]_0 ;
  wire \MUXED_DATA_Buffer_reg[18]_0 ;
  wire \MUXED_DATA_Buffer_reg[19]_0 ;
  wire \MUXED_DATA_Buffer_reg[20]_0 ;
  wire \MUXED_DATA_Buffer_reg[21]_0 ;
  wire \MUXED_DATA_Buffer_reg[22]_0 ;
  wire \MUXED_DATA_Buffer_reg[23]_0 ;
  wire \MUXED_DATA_Buffer_reg[24]_0 ;
  wire \MUXED_DATA_Buffer_reg[25]_0 ;
  wire \MUXED_DATA_Buffer_reg[26]_0 ;
  wire \MUXED_DATA_Buffer_reg[27]_0 ;
  wire \MUXED_DATA_Buffer_reg[28]_0 ;
  wire \MUXED_DATA_Buffer_reg[29]_0 ;
  wire \MUXED_DATA_Buffer_reg[30]_0 ;
  wire \MUXED_DATA_Buffer_reg[31]_0 ;
  wire [0:31]SHIFTED_DATA_Buffer;
  wire [2:0]UFC_STORAGE_SELECT_Buffer;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[0]_i_2 
       (.I0(SHIFTED_DATA_Buffer[16]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[0]),
        .O(\MUXED_DATA_Buffer[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[10]_i_1 
       (.I0(SHIFTED_DATA_Buffer[26]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[10]),
        .O(\MUXED_DATA_Buffer[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[11]_i_1 
       (.I0(SHIFTED_DATA_Buffer[27]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[11]),
        .O(\MUXED_DATA_Buffer[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[12]_i_1 
       (.I0(SHIFTED_DATA_Buffer[28]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[12]),
        .O(\MUXED_DATA_Buffer[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[13]_i_1 
       (.I0(SHIFTED_DATA_Buffer[29]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[13]),
        .O(\MUXED_DATA_Buffer[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[14]_i_1 
       (.I0(SHIFTED_DATA_Buffer[30]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[14]),
        .O(\MUXED_DATA_Buffer[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[15]_i_1 
       (.I0(SHIFTED_DATA_Buffer[31]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[15]),
        .O(\MUXED_DATA_Buffer[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[16]_i_1 
       (.I0(SHIFTED_DATA_Buffer[16]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[0]),
        .O(\MUXED_DATA_Buffer[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[17]_i_1 
       (.I0(SHIFTED_DATA_Buffer[17]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[1]),
        .O(\MUXED_DATA_Buffer[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[18]_i_1 
       (.I0(SHIFTED_DATA_Buffer[18]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[2]),
        .O(\MUXED_DATA_Buffer[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[19]_i_1 
       (.I0(SHIFTED_DATA_Buffer[19]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[3]),
        .O(\MUXED_DATA_Buffer[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[1]_i_1 
       (.I0(SHIFTED_DATA_Buffer[17]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[1]),
        .O(\MUXED_DATA_Buffer[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[20]_i_1 
       (.I0(SHIFTED_DATA_Buffer[20]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[4]),
        .O(\MUXED_DATA_Buffer[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[21]_i_1 
       (.I0(SHIFTED_DATA_Buffer[21]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[5]),
        .O(\MUXED_DATA_Buffer[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[22]_i_1 
       (.I0(SHIFTED_DATA_Buffer[22]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[6]),
        .O(\MUXED_DATA_Buffer[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[23]_i_1 
       (.I0(SHIFTED_DATA_Buffer[23]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[7]),
        .O(\MUXED_DATA_Buffer[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[24]_i_1 
       (.I0(SHIFTED_DATA_Buffer[24]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[8]),
        .O(\MUXED_DATA_Buffer[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[25]_i_1 
       (.I0(SHIFTED_DATA_Buffer[25]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[9]),
        .O(\MUXED_DATA_Buffer[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[26]_i_1 
       (.I0(SHIFTED_DATA_Buffer[26]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[10]),
        .O(\MUXED_DATA_Buffer[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[27]_i_1 
       (.I0(SHIFTED_DATA_Buffer[27]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[11]),
        .O(\MUXED_DATA_Buffer[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[28]_i_1 
       (.I0(SHIFTED_DATA_Buffer[28]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[12]),
        .O(\MUXED_DATA_Buffer[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[29]_i_1 
       (.I0(SHIFTED_DATA_Buffer[29]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[13]),
        .O(\MUXED_DATA_Buffer[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[2]_i_1 
       (.I0(SHIFTED_DATA_Buffer[18]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[2]),
        .O(\MUXED_DATA_Buffer[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[30]_i_1 
       (.I0(SHIFTED_DATA_Buffer[30]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[14]),
        .O(\MUXED_DATA_Buffer[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[31]_i_1 
       (.I0(SHIFTED_DATA_Buffer[31]),
        .I1(UFC_STORAGE_SELECT_Buffer[0]),
        .I2(SHIFTED_DATA_Buffer[15]),
        .O(\MUXED_DATA_Buffer[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[3]_i_1 
       (.I0(SHIFTED_DATA_Buffer[19]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[3]),
        .O(\MUXED_DATA_Buffer[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[4]_i_1 
       (.I0(SHIFTED_DATA_Buffer[20]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[4]),
        .O(\MUXED_DATA_Buffer[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[5]_i_1 
       (.I0(SHIFTED_DATA_Buffer[21]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[5]),
        .O(\MUXED_DATA_Buffer[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[6]_i_1 
       (.I0(SHIFTED_DATA_Buffer[22]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[6]),
        .O(\MUXED_DATA_Buffer[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[7]_i_1 
       (.I0(SHIFTED_DATA_Buffer[23]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[7]),
        .O(\MUXED_DATA_Buffer[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[8]_i_1 
       (.I0(SHIFTED_DATA_Buffer[24]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[8]),
        .O(\MUXED_DATA_Buffer[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[9]_i_1 
       (.I0(SHIFTED_DATA_Buffer[25]),
        .I1(UFC_STORAGE_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[9]),
        .O(\MUXED_DATA_Buffer[9]_i_1_n_0 ));
  FDRE \MUXED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[0]_i_2_n_0 ),
        .Q(D[15]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[10]_i_1_n_0 ),
        .Q(D[5]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[11]_i_1_n_0 ),
        .Q(D[4]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[12]_i_1_n_0 ),
        .Q(D[3]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[13]_i_1_n_0 ),
        .Q(D[2]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[14]_i_1_n_0 ),
        .Q(D[1]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[15]_i_1_n_0 ),
        .Q(D[0]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[16]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[16]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[17]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[17]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[18]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[18]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[19]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[19]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[1]_i_1_n_0 ),
        .Q(D[14]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[20]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[20]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[21]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[21]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[22]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[22]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[23]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[23]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[24]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[24]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[25]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[25]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[26]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[26]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[27]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[27]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[28]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[28]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[29]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[29]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[2]_i_1_n_0 ),
        .Q(D[13]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[30]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[30]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[31]_i_1_n_0 ),
        .Q(\MUXED_DATA_Buffer_reg[31]_0 ),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[3]_i_1_n_0 ),
        .Q(D[12]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[4]_i_1_n_0 ),
        .Q(D[11]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[5]_i_1_n_0 ),
        .Q(D[10]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[6]_i_1_n_0 ),
        .Q(D[9]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[7]_i_1_n_0 ),
        .Q(D[8]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[8]_i_1_n_0 ),
        .Q(D[7]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
  FDRE \MUXED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer[9]_i_1_n_0 ),
        .Q(D[6]),
        .R(\MUXED_DATA_Buffer_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_UFC_STORAGE_SWITCH_CONTROL
   (\UFC_STORAGE_SELECT_Buffer_reg[0]_0 ,
    \UFC_STORAGE_SELECT_Buffer_reg[2]_0 ,
    D,
    user_clk,
    \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ,
    \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ,
    Q,
    \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ,
    stage_1_ufc_start_r,
    \UFC_STORAGE_SELECT_Buffer_reg[4]_1 );
  output \UFC_STORAGE_SELECT_Buffer_reg[0]_0 ;
  output [2:0]\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ;
  input [0:0]D;
  input user_clk;
  input \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ;
  input \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
  input [1:0]Q;
  input \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ;
  input stage_1_ufc_start_r;
  input [1:0]\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ;

  wire [0:0]D;
  wire [1:0]Q;
  wire [0:1]UFC_STORAGE_SELECT_Buffer;
  wire \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[0]_0 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[0]_1 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
  wire [2:0]\UFC_STORAGE_SELECT_Buffer_reg[2]_0 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[4]_0 ;
  wire [1:0]\UFC_STORAGE_SELECT_Buffer_reg[4]_1 ;
  wire stage_1_ufc_start_r;
  wire user_clk;

  LUT2 #(
    .INIT(4'hE)) 
    \MUXED_DATA_Buffer[0]_i_1 
       (.I0(UFC_STORAGE_SELECT_Buffer[0]),
        .I1(UFC_STORAGE_SELECT_Buffer[1]),
        .O(\UFC_STORAGE_SELECT_Buffer_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hABABABBF)) 
    \UFC_STORAGE_SELECT_Buffer[0]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(Q[1]),
        .I2(\UFC_STORAGE_SELECT_Buffer_reg[4]_1 [1]),
        .I3(\UFC_STORAGE_SELECT_Buffer_reg[4]_1 [0]),
        .I4(Q[0]),
        .O(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_STORAGE_SELECT_Buffer_reg[0]_1 ),
        .Q(UFC_STORAGE_SELECT_Buffer[0]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_STORAGE_SELECT_Buffer_reg[1]_0 ),
        .Q(UFC_STORAGE_SELECT_Buffer[1]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[0]),
        .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [2]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_STORAGE_SELECT_Buffer_reg[4]_0 ),
        .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [1]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(\UFC_STORAGE_SELECT_Buffer_reg[2]_0 [0]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_VALID_DATA_COUNTER" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER
   (\COUNT_Buffer_reg[0]_0 ,
    Q,
    RESET,
    user_clk);
  output [1:0]\COUNT_Buffer_reg[0]_0 ;
  input [1:0]Q;
  input RESET;
  input user_clk;

  wire \COUNT_Buffer[0]_i_1_n_0 ;
  wire \COUNT_Buffer[1]_i_1_n_0 ;
  wire [1:0]\COUNT_Buffer_reg[0]_0 ;
  wire [1:0]Q;
  wire RESET;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \COUNT_Buffer[0]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\COUNT_Buffer[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \COUNT_Buffer[1]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\COUNT_Buffer[1]_i_1_n_0 ));
  FDRE \COUNT_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\COUNT_Buffer[0]_i_1_n_0 ),
        .Q(\COUNT_Buffer_reg[0]_0 [1]),
        .R(RESET));
  FDRE \COUNT_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\COUNT_Buffer[1]_i_1_n_0 ),
        .Q(\COUNT_Buffer_reg[0]_0 [0]),
        .R(RESET));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_VALID_DATA_COUNTER" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_VALID_DATA_COUNTER_15
   (D,
    Q,
    end_storage_r_reg,
    end_storage_r0,
    std_bool2_in,
    std_bool6_in,
    \STORAGE_CE_Buffer_reg[0] ,
    stage_3_end_storage_r,
    stage_2_start_with_data_r,
    stage_2_end_before_start_r,
    stage_2_end_after_start_r,
    RESET,
    \COUNT_Buffer_reg[0]_0 ,
    user_clk);
  output [1:0]D;
  output [0:0]Q;
  output [0:0]end_storage_r_reg;
  output end_storage_r0;
  output std_bool2_in;
  output std_bool6_in;
  input [1:0]\STORAGE_CE_Buffer_reg[0] ;
  input stage_3_end_storage_r;
  input stage_2_start_with_data_r;
  input stage_2_end_before_start_r;
  input stage_2_end_after_start_r;
  input RESET;
  input [1:0]\COUNT_Buffer_reg[0]_0 ;
  input user_clk;

  wire [1:0]\COUNT_Buffer_reg[0]_0 ;
  wire [1:0]D;
  wire [0:0]Q;
  wire RESET;
  wire [1:0]\STORAGE_CE_Buffer_reg[0] ;
  wire end_storage_r0;
  wire [0:0]end_storage_r_reg;
  wire [0:0]stage_2_data_v_count_r;
  wire stage_2_end_after_start_r;
  wire stage_2_end_before_start_r;
  wire stage_2_start_with_data_r;
  wire stage_3_end_storage_r;
  wire std_bool2_in;
  wire std_bool6_in;
  wire user_clk;

  FDRE \COUNT_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\COUNT_Buffer_reg[0]_0 [1]),
        .Q(stage_2_data_v_count_r),
        .R(RESET));
  FDRE \COUNT_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\COUNT_Buffer_reg[0]_0 [0]),
        .Q(Q),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'hFEE0)) 
    SRC_RDY_N_Buffer_i_3
       (.I0(Q),
        .I1(\STORAGE_CE_Buffer_reg[0] [0]),
        .I2(\STORAGE_CE_Buffer_reg[0] [1]),
        .I3(stage_2_data_v_count_r),
        .O(std_bool6_in));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFAEF)) 
    \STORAGE_CE_Buffer[0]_i_1 
       (.I0(stage_2_data_v_count_r),
        .I1(Q),
        .I2(\STORAGE_CE_Buffer_reg[0] [1]),
        .I3(\STORAGE_CE_Buffer_reg[0] [0]),
        .I4(stage_3_end_storage_r),
        .I5(stage_2_start_with_data_r),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \STORAGE_CE_Buffer[1]_i_1 
       (.I0(stage_2_data_v_count_r),
        .I1(\STORAGE_CE_Buffer_reg[0] [0]),
        .I2(Q),
        .I3(\STORAGE_CE_Buffer_reg[0] [1]),
        .I4(stage_3_end_storage_r),
        .I5(stage_2_start_with_data_r),
        .O(D[0]));
  LUT4 #(
    .INIT(16'hF404)) 
    end_storage_r_i_1
       (.I0(std_bool2_in),
        .I1(stage_2_end_before_start_r),
        .I2(stage_2_start_with_data_r),
        .I3(stage_2_end_after_start_r),
        .O(end_storage_r0));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    end_storage_r_i_2
       (.I0(Q),
        .I1(\STORAGE_CE_Buffer_reg[0] [0]),
        .I2(\STORAGE_CE_Buffer_reg[0] [1]),
        .I3(stage_2_data_v_count_r),
        .O(std_bool2_in));
  LUT6 #(
    .INIT(64'hEFFFFEEF10011000)) 
    \storage_count_r[0]_i_1 
       (.I0(stage_3_end_storage_r),
        .I1(stage_2_start_with_data_r),
        .I2(Q),
        .I3(\STORAGE_CE_Buffer_reg[0] [0]),
        .I4(\STORAGE_CE_Buffer_reg[0] [1]),
        .I5(stage_2_data_v_count_r),
        .O(end_storage_r_reg));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync
   (out,
    HPCNT_RESET,
    GT_RESET,
    init_clk_in,
    \hotplug_count_synth.count_for_reset_r_reg[0] );
  output out;
  output HPCNT_RESET;
  input GT_RESET;
  input init_clk_in;
  input \hotplug_count_synth.count_for_reset_r_reg[0] ;

  wire HPCNT_RESET;
  wire \hotplug_count_synth.count_for_reset_r_reg[0] ;
  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  assign out = s_level_out_d3;
  assign p_level_in_int = GT_RESET;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_2 
       (.I0(s_level_out_d3),
        .I1(\hotplug_count_synth.count_for_reset_r_reg[0] ),
        .O(HPCNT_RESET));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_0
   (out,
    RX_SYSTEM_RESET,
    init_clk_in);
  output out;
  input RX_SYSTEM_RESET;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  assign out = s_level_out_d3;
  assign p_level_in_int = RX_SYSTEM_RESET;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_1
   (out,
    RX_SYSTEM_RESET,
    user_clk);
  output out;
  input RX_SYSTEM_RESET;
  input user_clk;

  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  assign p_level_in_int = RX_SYSTEM_RESET;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_11
   (out,
    user_clk);
  output out;
  input user_clk;

  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(p_level_in_int));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_3
   (E,
    \FSM_sequential_rx_state_reg[1] ,
    TX_LOCK,
    init_clk_in,
    reset_time_out_reg,
    Q,
    \FSM_sequential_rx_state_reg[0] ,
    \FSM_sequential_rx_state_reg[0]_0 ,
    reset_time_out_reg_0,
    \FSM_sequential_rx_state_reg[0]_1 ,
    reset_time_out_reg_1,
    \FSM_sequential_rx_state_reg[0]_2 ,
    \FSM_sequential_rx_state_reg[0]_3 ,
    \FSM_sequential_rx_state_reg[0]_4 ,
    rxresetdone_s3,
    reset_time_out_reg_2);
  output [0:0]E;
  output \FSM_sequential_rx_state_reg[1] ;
  input TX_LOCK;
  input init_clk_in;
  input reset_time_out_reg;
  input [3:0]Q;
  input \FSM_sequential_rx_state_reg[0] ;
  input \FSM_sequential_rx_state_reg[0]_0 ;
  input reset_time_out_reg_0;
  input \FSM_sequential_rx_state_reg[0]_1 ;
  input reset_time_out_reg_1;
  input \FSM_sequential_rx_state_reg[0]_2 ;
  input \FSM_sequential_rx_state_reg[0]_3 ;
  input \FSM_sequential_rx_state_reg[0]_4 ;
  input rxresetdone_s3;
  input reset_time_out_reg_2;

  wire [0:0]E;
  wire \FSM_sequential_rx_state[3]_i_13_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_3_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_7_n_0 ;
  wire \FSM_sequential_rx_state_reg[0] ;
  wire \FSM_sequential_rx_state_reg[0]_0 ;
  wire \FSM_sequential_rx_state_reg[0]_1 ;
  wire \FSM_sequential_rx_state_reg[0]_2 ;
  wire \FSM_sequential_rx_state_reg[0]_3 ;
  wire \FSM_sequential_rx_state_reg[0]_4 ;
  wire \FSM_sequential_rx_state_reg[1] ;
  wire [3:0]Q;
  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire reset_time_out_i_2_n_0;
  wire reset_time_out_i_3_n_0;
  wire reset_time_out_i_4_n_0;
  wire reset_time_out_reg;
  wire reset_time_out_reg_0;
  wire reset_time_out_reg_1;
  wire reset_time_out_reg_2;
  wire rxresetdone_s3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  assign p_level_in_int = TX_LOCK;
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_rx_state[3]_i_1 
       (.I0(\FSM_sequential_rx_state[3]_i_3_n_0 ),
        .I1(\FSM_sequential_rx_state_reg[0] ),
        .I2(\FSM_sequential_rx_state_reg[0]_0 ),
        .I3(reset_time_out_reg_0),
        .I4(\FSM_sequential_rx_state[3]_i_7_n_0 ),
        .I5(\FSM_sequential_rx_state_reg[0]_1 ),
        .O(E));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_rx_state[3]_i_13 
       (.I0(reset_time_out_reg_2),
        .I1(s_level_out_d3),
        .O(\FSM_sequential_rx_state[3]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF000400040004)) 
    \FSM_sequential_rx_state[3]_i_3 
       (.I0(reset_time_out_reg_1),
        .I1(\FSM_sequential_rx_state_reg[0]_2 ),
        .I2(\FSM_sequential_rx_state_reg[0]_3 ),
        .I3(Q[3]),
        .I4(\FSM_sequential_rx_state_reg[0]_4 ),
        .I5(\FSM_sequential_rx_state[3]_i_13_n_0 ),
        .O(\FSM_sequential_rx_state[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5410000000000000)) 
    \FSM_sequential_rx_state[3]_i_7 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(s_level_out_d3),
        .I3(rxresetdone_s3),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(\FSM_sequential_rx_state[3]_i_7_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
  LUT6 #(
    .INIT(64'hFEEEFFFFFEEE0000)) 
    reset_time_out_i_1
       (.I0(reset_time_out_reg_0),
        .I1(reset_time_out_i_2_n_0),
        .I2(Q[1]),
        .I3(reset_time_out_i_3_n_0),
        .I4(reset_time_out_i_4_n_0),
        .I5(reset_time_out_reg_1),
        .O(\FSM_sequential_rx_state_reg[1] ));
  LUT5 #(
    .INIT(32'h00000004)) 
    reset_time_out_i_2
       (.I0(Q[1]),
        .I1(reset_time_out_reg_2),
        .I2(s_level_out_d3),
        .I3(Q[3]),
        .I4(Q[2]),
        .O(reset_time_out_i_2_n_0));
  LUT4 #(
    .INIT(16'h00AC)) 
    reset_time_out_i_3
       (.I0(rxresetdone_s3),
        .I1(s_level_out_d3),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(reset_time_out_i_3_n_0));
  LUT6 #(
    .INIT(64'h330233023FCC3CCC)) 
    reset_time_out_i_4
       (.I0(reset_time_out_reg),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\FSM_sequential_rx_state[3]_i_13_n_0 ),
        .I5(Q[2]),
        .O(reset_time_out_i_4_n_0));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_4
   (init_clk_in);
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(p_level_in_int));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_6
   (SR,
    mmcm_lock_reclocked_reg,
    init_clk_in,
    mmcm_lock_reclocked,
    mmcm_lock_reclocked_reg_0);
  output [0:0]SR;
  output mmcm_lock_reclocked_reg;
  input init_clk_in;
  input mmcm_lock_reclocked;
  input mmcm_lock_reclocked_reg_0;

  wire [0:0]SR;
  wire init_clk_in;
  wire mmcm_lock_reclocked;
  wire mmcm_lock_reclocked_reg;
  wire mmcm_lock_reclocked_reg_0;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(p_level_in_int));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(p_level_in_d1_cdc_from));
  LUT1 #(
    .INIT(2'h1)) 
    \mmcm_lock_count[9]_i_1 
       (.I0(s_level_out_d3),
        .O(SR));
  LUT3 #(
    .INIT(8'hE0)) 
    mmcm_lock_reclocked_i_1
       (.I0(mmcm_lock_reclocked),
        .I1(mmcm_lock_reclocked_reg_0),
        .I2(s_level_out_d3),
        .O(mmcm_lock_reclocked_reg));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2
   (out,
    GTRXRESET_OUT,
    user_clk,
    init_clk_in);
  output out;
  input GTRXRESET_OUT;
  input user_clk;
  input init_clk_in;

  wire GTRXRESET_OUT;
  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(GTRXRESET_OUT),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_10
   (rxpmaresetdone_i,
    user_clk,
    init_clk_in);
  input rxpmaresetdone_i;
  input user_clk;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire rxpmaresetdone_i;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rxpmaresetdone_i),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_12
   (out,
    time_out_wait_bypass,
    user_clk,
    init_clk_in);
  output out;
  input time_out_wait_bypass;
  input user_clk;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire time_out_wait_bypass;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(time_out_wait_bypass),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_13
   (out,
    link_reset_r,
    init_clk_in,
    user_clk);
  output out;
  input link_reset_r;
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  wire link_reset_r;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_14
   (out,
    tx_lock_comb_r,
    init_clk_in,
    user_clk);
  output out;
  input tx_lock_comb_r;
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire tx_lock_comb_r;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(tx_lock_comb_r),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_16
   (O,
    \hotplug_count_synth.count_for_reset_r_reg[7] ,
    \hotplug_count_synth.count_for_reset_r_reg[11] ,
    \hotplug_count_synth.count_for_reset_r_reg[15] ,
    \hotplug_count_synth.count_for_reset_r_reg[19] ,
    \hotplug_count_synth.count_for_reset_r_reg[23] ,
    \hotplug_count_synth.count_for_reset_r_reg[25] ,
    rx_cc_extend_r2,
    user_clk,
    init_clk_in,
    \hotplug_count_synth.count_for_reset_r_reg );
  output [3:0]O;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  output [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  input rx_cc_extend_r2;
  input user_clk;
  input init_clk_in;
  input [25:0]\hotplug_count_synth.count_for_reset_r_reg ;

  wire [3:0]O;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3 ;
  wire [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 ;
  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire rx_cc_extend_r2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;
  wire [3:1]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED ;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_3 
       (.I0(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_6 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_7 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I1(s_level_out_d3),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ));
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 }),
        .O(O),
        .S({\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 }));
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[12]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[15] ),
        .S({\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 }));
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[16]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[19] ),
        .S({\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 }));
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[20]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[23] ),
        .S({\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_5_n_0 }));
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[24]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0 ),
        .CO({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED [3:1],\hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED [3:2],\hotplug_count_synth.count_for_reset_r_reg[25] }),
        .S({1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[24]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[24]_i_3_n_0 }));
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[4]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[7] ),
        .S({\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 }));
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[8]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[11] ),
        .S({\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_2
   (out,
    fsm_gt_rx_reset_t,
    init_clk_in,
    user_clk);
  output out;
  input fsm_gt_rx_reset_t;
  input init_clk_in;
  input user_clk;

  wire fsm_gt_rx_reset_t;
  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(fsm_gt_rx_reset_t),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_5
   (out,
    rxfsm_rxresetdone_r,
    user_clk,
    init_clk_in);
  output out;
  input rxfsm_rxresetdone_r;
  input user_clk;
  input init_clk_in;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire rxfsm_rxresetdone_r;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rxfsm_rxresetdone_r),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_7
   (init_clk_in,
    user_clk);
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(1'b0),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_8
   (out,
    run_phase_alignment_int,
    init_clk_in,
    user_clk);
  output out;
  input run_phase_alignment_int;
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire run_phase_alignment_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(run_phase_alignment_int),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_cdc_sync" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_9
   (out,
    rx_fsm_reset_done_int,
    init_clk_in,
    user_clk);
  output out;
  input rx_fsm_reset_done_int;
  input init_clk_in;
  input user_clk;

  wire init_clk_in;
  (* RTL_KEEP = "true" *) wire p_level_in_d1_cdc_from;
  wire p_level_in_int;
  wire rx_fsm_reset_done_int;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d1_aurora_1ln_rx_lpm_cdc_to;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d2;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d3;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d4;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d5;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire s_level_out_d6;
  wire user_clk;

  assign out = s_level_out_d3;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_fsm_reset_done_int),
        .Q(p_level_in_d1_cdc_from),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_1ln_rx_lpm_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_level_in_int),
        .Q(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d1_aurora_1ln_rx_lpm_cdc_to),
        .Q(s_level_out_d2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d2),
        .Q(s_level_out_d3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d3),
        .Q(s_level_out_d4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d4),
        .Q(s_level_out_d5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_level_out_d5),
        .Q(s_level_out_d6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    p_level_in_d1_cdc_from_inst
       (.I0(p_level_in_d1_cdc_from),
        .O(p_level_in_int));
endmodule

(* EXAMPLE_SIMULATION = "0" *) (* ORIG_REF_NAME = "aurora_1ln_rx_lpm_core" *) (* SIM_GTRESET_SPEEDUP = "FALSE" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_core
   (M_AXI_RX_TDATA,
    M_AXI_RX_TKEEP,
    M_AXI_RX_TVALID,
    M_AXI_RX_TLAST,
    M_AXI_UFC_RX_TDATA,
    M_AXI_UFC_RX_TKEEP,
    M_AXI_UFC_RX_TVALID,
    M_AXI_UFC_RX_TLAST,
    RXP,
    RXN,
    gt_refclk1,
    RX_HARD_ERR,
    SOFT_ERR,
    FRAME_ERR,
    RX_CHANNEL_UP,
    RX_LANE_UP,
    user_clk,
    sync_clk,
    RX_SYSTEM_RESET,
    RX_RESETDONE_OUT,
    LINK_RESET_OUT,
    POWER_DOWN,
    GT_RESET,
    init_clk_in,
    PLL_NOT_LOCKED,
    drpclk_in,
    DRPADDR_IN,
    DRPDI_IN,
    DRPDO_OUT,
    DRPEN_IN,
    DRPRDY_OUT,
    DRPWE_IN,
    TX_OUT_CLK,
    gt0_qplllock_in,
    gt0_qpllrefclklost_in,
    gt0_qpllreset_out,
    gt_qpllclk_quad1_in,
    gt_qpllrefclk_quad1_in,
    gt0_cplllock_out,
    gt0_rxlpmen_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxmonitorout_out,
    gt0_rxmonitorsel_in,
    gt0_rxcdrhold_in,
    gt0_eyescanreset_in,
    gt0_eyescandataerror_out,
    gt0_eyescantrigger_in,
    gt0_rxbyteisaligned_out,
    gt0_rxcommadet_out,
    gt0_rxprbserr_out,
    gt0_rxprbssel_in,
    gt0_rxprbscntreset_in,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    gt0_rxpmaresetdone_out,
    gt0_dmonitorout_out,
    gt0_rxbufreset_in,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    gt0_rx_realign_out,
    gt0_rx_buf_err_out,
    gt0_rxresetdone_out,
    gt0_rxbufstatus_out,
    sys_reset_out,
    TX_LOCK,
    LOOPBACK);
  output [31:0]M_AXI_RX_TDATA;
  output [3:0]M_AXI_RX_TKEEP;
  output M_AXI_RX_TVALID;
  output M_AXI_RX_TLAST;
  output [31:0]M_AXI_UFC_RX_TDATA;
  output [3:0]M_AXI_UFC_RX_TKEEP;
  output M_AXI_UFC_RX_TVALID;
  output M_AXI_UFC_RX_TLAST;
  input RXP;
  input RXN;
  input gt_refclk1;
  output RX_HARD_ERR;
  output SOFT_ERR;
  output FRAME_ERR;
  output RX_CHANNEL_UP;
  output RX_LANE_UP;
  input user_clk;
  input sync_clk;
  input RX_SYSTEM_RESET;
  output RX_RESETDONE_OUT;
  output LINK_RESET_OUT;
  input POWER_DOWN;
  input GT_RESET;
  input init_clk_in;
  input PLL_NOT_LOCKED;
  input drpclk_in;
  input [8:0]DRPADDR_IN;
  input [15:0]DRPDI_IN;
  output [15:0]DRPDO_OUT;
  input DRPEN_IN;
  output DRPRDY_OUT;
  input DRPWE_IN;
  output TX_OUT_CLK;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt_qpllclk_quad1_in;
  input gt_qpllrefclk_quad1_in;
  output gt0_cplllock_out;
  input gt0_rxlpmen_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  output [6:0]gt0_rxmonitorout_out;
  input [1:0]gt0_rxmonitorsel_in;
  input gt0_rxcdrhold_in;
  input gt0_eyescanreset_in;
  output gt0_eyescandataerror_out;
  input gt0_eyescantrigger_in;
  output gt0_rxbyteisaligned_out;
  output gt0_rxcommadet_out;
  output gt0_rxprbserr_out;
  input [2:0]gt0_rxprbssel_in;
  input gt0_rxprbscntreset_in;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  output gt0_rxpmaresetdone_out;
  output [14:0]gt0_dmonitorout_out;
  input gt0_rxbufreset_in;
  output [3:0]gt0_rx_disp_err_out;
  output [3:0]gt0_rx_not_in_table_out;
  output gt0_rx_realign_out;
  output gt0_rx_buf_err_out;
  output gt0_rxresetdone_out;
  output [2:0]gt0_rxbufstatus_out;
  output sys_reset_out;
  output TX_LOCK;
  input [2:0]LOOPBACK;

  wire \<const0> ;
  wire \<const1> ;
  wire [8:0]DRPADDR_IN;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDO_OUT;
  wire DRPEN_IN;
  wire DRPRDY_OUT;
  wire DRPWE_IN;
  wire FRAME_ERR;
  wire GOT_V;
  wire GTRXRESET_OUT;
  wire GT_RESET;
  wire HPCNT_RESET;
  wire LINK_RESET_OUT;
  wire [2:0]LOOPBACK;
  wire [31:0]M_AXI_RX_TDATA;
  wire [3:1]\^M_AXI_RX_TKEEP ;
  wire M_AXI_RX_TLAST;
  wire M_AXI_RX_TVALID;
  wire [31:0]M_AXI_UFC_RX_TDATA;
  wire [3:3]\^M_AXI_UFC_RX_TKEEP ;
  wire M_AXI_UFC_RX_TLAST;
  wire M_AXI_UFC_RX_TVALID;
  wire POWER_DOWN;
  wire RESET;
  wire RXN;
  wire RXP;
  wire RX_CHANNEL_UP;
  wire RX_HARD_ERR;
  wire RX_LANE_UP;
  wire [8:26]RX_PE_DATA;
  wire [0:1]RX_PE_DATA_V;
  wire RX_RESETDONE_OUT;
  wire RX_SYSTEM_RESET;
  wire SOFT_ERR;
  wire START_RX;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_19;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_20;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_24;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_25;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_26;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_27;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_28;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_29;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_30;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_31;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_32;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_33;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_34;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_35;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_36;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_37;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_38;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_39;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_40;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_42;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_43;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_44;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_45;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_46;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_47;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_48;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_49;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_50;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_51;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_52;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_53;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_54;
  wire aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_55;
  wire \aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/hard_err_gt0 ;
  wire [3:1]\aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out ;
  wire \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/begin_r ;
  wire \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r ;
  wire \aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r0 ;
  wire aurora_1ln_rx_lpm_rx_ll_i_n_5;
  wire aurora_1ln_rx_lpm_rx_ll_i_n_6;
  wire [0:0]\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_0_in ;
  wire [1:0]\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_2_out ;
  wire [1:0]\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_8_out ;
  wire [1:0]\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_9_out ;
  wire drpclk_in;
  wire ena_comma_align_i;
  wire enable_err_detect_i;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire gt0_rx_buf_err_out;
  wire [3:0]gt0_rx_disp_err_out;
  wire [3:0]gt0_rx_not_in_table_out;
  wire gt0_rx_realign_out;
  wire gt0_rxbufreset_in;
  wire [1:0]\^gt0_rxbufstatus_out ;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt_qpllclk_quad1_in;
  wire gt_qpllrefclk_quad1_in;
  wire gt_refclk1;
  wire gt_reset_sync_init_clk;
  wire gt_wrapper_i_n_100;
  wire gt_wrapper_i_n_101;
  wire gt_wrapper_i_n_102;
  wire gt_wrapper_i_n_103;
  wire gt_wrapper_i_n_104;
  wire gt_wrapper_i_n_105;
  wire gt_wrapper_i_n_106;
  wire gt_wrapper_i_n_107;
  wire gt_wrapper_i_n_108;
  wire gt_wrapper_i_n_109;
  wire gt_wrapper_i_n_110;
  wire gt_wrapper_i_n_111;
  wire gt_wrapper_i_n_112;
  wire gt_wrapper_i_n_114;
  wire gt_wrapper_i_n_116;
  wire gt_wrapper_i_n_117;
  wire gt_wrapper_i_n_98;
  wire gt_wrapper_i_n_99;
  wire init_clk_in;
  wire link_reset_r;
  wire neqOp;
  wire [7:1]previous_cycle_data_r;
  wire reset_sync_init_clk;
  wire reset_sync_user_clk;
  wire [3:0]rx_char_is_k_i;
  wire [31:0]rx_data_i;
  wire rx_eof;
  wire rx_hard_err_i;
  wire rx_polarity_i;
  wire rx_reset_lanes_i;
  wire [0:1]rx_suf_i;
  wire sync_clk;
  wire sys_reset_out;
  wire user_clk;

  assign M_AXI_RX_TKEEP[3:1] = \^M_AXI_RX_TKEEP [3:1];
  assign M_AXI_RX_TKEEP[0] = \<const1> ;
  assign M_AXI_UFC_RX_TKEEP[3] = \^M_AXI_UFC_RX_TKEEP [3];
  assign M_AXI_UFC_RX_TKEEP[2] = \^M_AXI_UFC_RX_TKEEP [3];
  assign M_AXI_UFC_RX_TKEEP[1] = \<const1> ;
  assign M_AXI_UFC_RX_TKEEP[0] = \<const1> ;
  assign gt0_cplllock_out = TX_LOCK;
  assign gt0_qpllreset_out = \<const0> ;
  assign gt0_rxbufstatus_out[2] = gt0_rx_buf_err_out;
  assign gt0_rxbufstatus_out[1:0] = \^gt0_rxbufstatus_out [1:0];
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_AURORA_LANE_SIMPLEX_GTX_4BYTE aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i
       (.D({gt_wrapper_i_n_104,gt_wrapper_i_n_105,gt_wrapper_i_n_106,gt_wrapper_i_n_107,gt_wrapper_i_n_108,gt_wrapper_i_n_109,gt_wrapper_i_n_110,gt_wrapper_i_n_111}),
        .E(\aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r ),
        .GOT_V(GOT_V),
        .HPCNT_RESET(HPCNT_RESET),
        .LINK_RESET_OUT(LINK_RESET_OUT),
        .Q({previous_cycle_data_r[7],previous_cycle_data_r[5],previous_cycle_data_r[3],previous_cycle_data_r[1]}),
        .RXCHARISK(rx_char_is_k_i),
        .RXDATA(rx_data_i),
        .RX_CHANNEL_UP(RX_CHANNEL_UP),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_PE_DATA({RX_PE_DATA[8],RX_PE_DATA[9],RX_PE_DATA[10],RX_PE_DATA[24],RX_PE_DATA[25],RX_PE_DATA[26]}),
        .\RX_PE_DATA_Buffer_reg[25] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_26),
        .\RX_PE_DATA_Buffer_reg[26] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_24),
        .\RX_PE_DATA_Buffer_reg[26]_0 (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_25),
        .\RX_PE_DATA_V_Buffer_reg[0] ({RX_PE_DATA_V[0],RX_PE_DATA_V[1]}),
        .\RX_SUF_Buffer_reg[0] ({rx_suf_i[0],rx_suf_i[1]}),
        .\RX_SUF_Buffer_reg[1] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_27),
        .\SOFT_ERR_Buffer_reg[0] ({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_54,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_55}),
        .SR(rx_reset_lanes_i),
        .begin_r(\aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/begin_r ),
        .begin_r_reg(gt0_rx_realign_out),
        .ena_comma_align_i(ena_comma_align_i),
        .enable_err_detect_i(enable_err_detect_i),
        .hard_err_gt0(\aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/hard_err_gt0 ),
        .inc_count_r0(\aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r0 ),
        .init_clk_in(init_clk_in),
        .\left_align_select_r_reg[0] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_20),
        .\left_align_select_r_reg[1] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_19),
        .neqOp(neqOp),
        .p_2_out(\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_2_out ),
        .p_8_out(\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_8_out ),
        .p_9_out(\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_9_out ),
        .reset_count_r_reg(gt_wrapper_i_n_99),
        .reset_count_r_reg_0(gt_wrapper_i_n_98),
        .rx_hard_err_i(rx_hard_err_i),
        .rx_polarity_i(rx_polarity_i),
        .\soft_err_r_reg[0] ({\aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out [3],gt_wrapper_i_n_114,\aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out [1],gt_wrapper_i_n_116}),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[3] (gt_wrapper_i_n_112),
        .\word_aligned_data_r_reg[0] ({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_46,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_47,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_48,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_49,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_50,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_51,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_52,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_53}),
        .\word_aligned_data_r_reg[11] ({\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_0_in ,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_42,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_43,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_44,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_45}),
        .\word_aligned_data_r_reg[16] ({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_33,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_34,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_35,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_36,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_37,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_38,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_39,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_40}),
        .\word_aligned_data_r_reg[16]_0 ({gt_wrapper_i_n_100,gt_wrapper_i_n_101,gt_wrapper_i_n_102,gt_wrapper_i_n_103}),
        .\word_aligned_data_r_reg[27] ({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_28,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_29,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_30,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_31,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_32}));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_GLOBAL_LOGIC_SIMPLEX aurora_1ln_rx_lpm_rx_global_logic_simplex_i
       (.D({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_54,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_55}),
        .GOT_V(GOT_V),
        .GTRXRESET_OUT(GTRXRESET_OUT),
        .POWER_DOWN(POWER_DOWN),
        .RESET(RESET),
        .RX_CHANNEL_UP(RX_CHANNEL_UP),
        .RX_HARD_ERR(RX_HARD_ERR),
        .RX_LANE_UP(RX_LANE_UP),
        .SOFT_ERR(SOFT_ERR),
        .SR(rx_reset_lanes_i),
        .START_RX(START_RX),
        .START_RX_Buffer_reg(sys_reset_out),
        .rx_hard_err_i(rx_hard_err_i),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RX_LL aurora_1ln_rx_lpm_rx_ll_i
       (.D({RX_PE_DATA_V[0],RX_PE_DATA_V[1]}),
        .FRAME_ERR(FRAME_ERR),
        .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
        .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
        .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
        .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
        .M_AXI_UFC_RX_TKEEP(\^M_AXI_UFC_RX_TKEEP ),
        .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
        .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
        .Q({aurora_1ln_rx_lpm_rx_ll_i_n_5,aurora_1ln_rx_lpm_rx_ll_i_n_6}),
        .RESET(RESET),
        .RX_PE_DATA({RX_PE_DATA[8],RX_PE_DATA[9],RX_PE_DATA[10],RX_PE_DATA[24],RX_PE_DATA[25],RX_PE_DATA[26]}),
        .START_RX(START_RX),
        .neqOp(neqOp),
        .p_2_out(\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_2_out ),
        .p_8_out(\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_8_out ),
        .p_9_out(\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_9_out ),
        .rx_eof(rx_eof),
        .\rx_suf_r_reg[0] ({rx_suf_i[0],rx_suf_i[1]}),
        .\stage_1_count_value_r_reg[0] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_27),
        .\stage_1_count_value_r_reg[1] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_26),
        .\stage_1_count_value_r_reg[2] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_25),
        .\stage_1_count_value_r_reg[3] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_24),
        .\stage_1_data_r_reg[0] ({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_46,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_47,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_48,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_49,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_50,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_51,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_52,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_53}),
        .\stage_1_data_r_reg[11] ({\aurora_1ln_rx_lpm_sym_dec_4byte_i/p_0_in ,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_42,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_43,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_44,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_45}),
        .\stage_1_data_r_reg[16] ({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_33,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_34,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_35,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_36,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_37,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_38,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_39,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_40}),
        .\stage_1_data_r_reg[27] ({aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_28,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_29,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_30,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_31,aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_32}),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_RESET_LOGIC core_reset_logic_i
       (.LINK_RESET_OUT(LINK_RESET_OUT),
        .TX_LOCK(TX_LOCK),
        .gt_rxresetdone_r2_reg_0(gt_wrapper_i_n_117),
        .init_clk_in(init_clk_in),
        .link_reset_r(link_reset_r),
        .out(reset_sync_user_clk),
        .sys_reset_out(sys_reset_out),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync gt_reset_cdc_sync
       (.GT_RESET(GT_RESET),
        .HPCNT_RESET(HPCNT_RESET),
        .\hotplug_count_synth.count_for_reset_r_reg[0] (reset_sync_init_clk),
        .init_clk_in(init_clk_in),
        .out(gt_reset_sync_init_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_GT_WRAPPER gt_wrapper_i
       (.D({gt_wrapper_i_n_104,gt_wrapper_i_n_105,gt_wrapper_i_n_106,gt_wrapper_i_n_107,gt_wrapper_i_n_108,gt_wrapper_i_n_109,gt_wrapper_i_n_110,gt_wrapper_i_n_111}),
        .DRPADDR_IN(DRPADDR_IN),
        .DRPDI_IN(DRPDI_IN),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPEN_IN(DRPEN_IN),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPWE_IN(DRPWE_IN),
        .E(\aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r ),
        .ENABLE_ERR_DETECT_Buffer_reg({\aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out [3],gt_wrapper_i_n_114,\aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/p_6_out [1],gt_wrapper_i_n_116}),
        .GTRXRESET_OUT(GTRXRESET_OUT),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .Q({previous_cycle_data_r[7],previous_cycle_data_r[5],previous_cycle_data_r[3],previous_cycle_data_r[1]}),
        .RXCHARISK(rx_char_is_k_i),
        .RXDATA(rx_data_i),
        .RXN(RXN),
        .RXP(RXP),
        .RX_RESETDONE_OUT(RX_RESETDONE_OUT),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .begin_r(\aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/begin_r ),
        .drpclk_in(drpclk_in),
        .ena_comma_align_i(ena_comma_align_i),
        .enable_err_detect_i(enable_err_detect_i),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rx_realign_out(gt0_rx_realign_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out({gt0_rx_buf_err_out,\^gt0_rxbufstatus_out }),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt_qpllclk_quad1_in(gt_qpllclk_quad1_in),
        .gt_qpllrefclk_quad1_in(gt_qpllrefclk_quad1_in),
        .gt_refclk1(gt_refclk1),
        .hard_err_gt0(\aurora_1ln_rx_lpm_rx_err_detect_simplex_gtx_4byte_i/hard_err_gt0 ),
        .inc_count_r0(\aurora_1ln_rx_lpm_rx_lane_init_sm_simplex_4byte_i/inc_count_r0 ),
        .inc_count_r_reg(gt_wrapper_i_n_98),
        .init_clk_in(init_clk_in),
        .init_clk_in_0(gt_wrapper_i_n_99),
        .\left_align_select_r_reg[1] (gt_wrapper_i_n_112),
        .link_reset_r(link_reset_r),
        .out(gt_reset_sync_init_clk),
        .\previous_cycle_data_r_reg[7] ({gt_wrapper_i_n_100,gt_wrapper_i_n_101,gt_wrapper_i_n_102,gt_wrapper_i_n_103}),
        .rx_polarity_i(rx_polarity_i),
        .rxfsm_rxresetdone_r3_reg_0(gt_wrapper_i_n_117),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_data_r_reg[22] (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_19),
        .\word_aligned_data_r_reg[22]_0 (aurora_1ln_rx_lpm_rx_aurora_lane_simplex_gtx_4byte_0_i_n_20));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_0 hpcnt_reset_cdc_sync
       (.RX_SYSTEM_RESET(RX_SYSTEM_RESET),
        .init_clk_in(init_clk_in),
        .out(reset_sync_init_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_LL_TO_AXI ll_to_axi_pdu_i
       (.M_AXI_RX_TKEEP(\^M_AXI_RX_TKEEP ),
        .Q({aurora_1ln_rx_lpm_rx_ll_i_n_5,aurora_1ln_rx_lpm_rx_ll_i_n_6}),
        .rx_eof(rx_eof));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_1 reset_sync_user_clk_cdc_sync
       (.RX_SYSTEM_RESET(RX_SYSTEM_RESET),
        .out(reset_sync_user_clk),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_gt" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_gt
   (TX_LOCK,
    DRPRDY_OUT,
    gt0_eyescandataerror_out,
    gt0_rxbyteisaligned_out,
    gt0_rx_realign_out,
    gt0_rxcommadet_out,
    gt0_rxpmaresetdone_out,
    gt0_rxprbserr_out,
    gt0_rxresetdone_out,
    TX_OUT_CLK,
    gt0_dmonitorout_out,
    DRPDO_OUT,
    gt0_rxbufstatus_out,
    RXDATA,
    gt0_rxmonitorout_out,
    RXCHARISK,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    ack_flag,
    hard_err_gt0,
    inc_count_r0,
    inc_count_r_reg,
    init_clk_in_0,
    \previous_cycle_data_r_reg[7] ,
    D,
    \left_align_select_r_reg[1] ,
    ENABLE_ERR_DETECT_Buffer_reg,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt0_eyescanreset_in,
    gt0_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    SR,
    fsm_gt_rx_reset_t,
    gt_qpllclk_quad1_in,
    gt_qpllrefclk_quad1_in,
    gt0_rxbufreset_in,
    gt0_rxcdrhold_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxlpmen_in,
    ena_comma_align_i,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    rx_polarity_i,
    gt0_rxprbscntreset_in,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    DRPDI_IN,
    gt0_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt0_rxprbssel_in,
    DRPADDR_IN,
    flag2_reg_0,
    E,
    begin_r,
    Q,
    \word_aligned_data_r_reg[22] ,
    \word_aligned_data_r_reg[22]_0 ,
    enable_err_detect_i,
    cpll_reset_i);
  output TX_LOCK;
  output DRPRDY_OUT;
  output gt0_eyescandataerror_out;
  output gt0_rxbyteisaligned_out;
  output gt0_rx_realign_out;
  output gt0_rxcommadet_out;
  output gt0_rxpmaresetdone_out;
  output gt0_rxprbserr_out;
  output gt0_rxresetdone_out;
  output TX_OUT_CLK;
  output [14:0]gt0_dmonitorout_out;
  output [15:0]DRPDO_OUT;
  output [2:0]gt0_rxbufstatus_out;
  output [31:0]RXDATA;
  output [6:0]gt0_rxmonitorout_out;
  output [3:0]RXCHARISK;
  output [3:0]gt0_rx_disp_err_out;
  output [3:0]gt0_rx_not_in_table_out;
  output ack_flag;
  output hard_err_gt0;
  output inc_count_r0;
  output inc_count_r_reg;
  output init_clk_in_0;
  output [3:0]\previous_cycle_data_r_reg[7] ;
  output [7:0]D;
  output \left_align_select_r_reg[1] ;
  output [3:0]ENABLE_ERR_DETECT_Buffer_reg;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt0_eyescanreset_in;
  input gt0_eyescantrigger_in;
  input RXN;
  input RXP;
  input gt_refclk1;
  input [0:0]SR;
  input fsm_gt_rx_reset_t;
  input gt_qpllclk_quad1_in;
  input gt_qpllrefclk_quad1_in;
  input gt0_rxbufreset_in;
  input gt0_rxcdrhold_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  input gt0_rxlpmen_in;
  input ena_comma_align_i;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  input rx_polarity_i;
  input gt0_rxprbscntreset_in;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN;
  input [1:0]gt0_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_rxprbssel_in;
  input [8:0]DRPADDR_IN;
  input flag2_reg_0;
  input [0:0]E;
  input begin_r;
  input [3:0]Q;
  input \word_aligned_data_r_reg[22] ;
  input \word_aligned_data_r_reg[22]_0 ;
  input enable_err_detect_i;
  input cpll_reset_i;

  wire CPLLPD;
  wire CPLLRESET;
  wire [7:0]D;
  wire [8:0]DRPADDR_IN;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDO_OUT;
  wire DRPEN_IN;
  wire DRPRDY_OUT;
  wire DRPWE_IN;
  wire D_0;
  wire [0:0]E;
  wire [3:0]ENABLE_ERR_DETECT_Buffer_reg;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [3:0]Q;
  wire [3:0]RXCHARISK;
  wire [31:0]RXDATA;
  wire RXN;
  wire RXP;
  wire [0:0]SR;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire begin_r;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire ena_comma_align_i;
  wire enable_err_detect_i;
  wire flag2;
  wire flag2_reg_0;
  wire flag_i_1_n_0;
  wire fsm_gt_rx_reset_t;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire gt0_pllrefclklost_i;
  wire [3:0]gt0_rx_disp_err_out;
  wire [3:0]gt0_rx_not_in_table_out;
  wire gt0_rx_realign_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt_qpllclk_quad1_in;
  wire gt_qpllrefclk_quad1_in;
  wire gt_refclk1;
  wire gt_rxuserrdy_i;
  wire gthe2_i_n_0;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_112;
  wire gthe2_i_n_113;
  wire gthe2_i_n_12;
  wire gthe2_i_n_29;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_5;
  wire gthe2_i_n_54;
  wire gthe2_i_n_6;
  wire gthe2_i_n_624;
  wire gthe2_i_n_625;
  wire gthe2_i_n_626;
  wire gthe2_i_n_627;
  wire gthe2_i_n_628;
  wire gthe2_i_n_629;
  wire gthe2_i_n_630;
  wire gthe2_i_n_631;
  wire gthe2_i_n_632;
  wire gthe2_i_n_633;
  wire gthe2_i_n_634;
  wire gthe2_i_n_635;
  wire gthe2_i_n_636;
  wire gthe2_i_n_637;
  wire gthe2_i_n_638;
  wire gthe2_i_n_639;
  wire hard_err_gt0;
  wire inc_count_r0;
  wire inc_count_r_reg;
  wire init_clk_in;
  wire init_clk_in_0;
  wire \left_align_select_r_reg[1] ;
  wire [3:0]\previous_cycle_data_r_reg[7] ;
  wire [3:0]rx_char_is_comma_i;
  wire rx_polarity_i;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_data_r_reg[22] ;
  wire \word_aligned_data_r_reg[22]_0 ;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED;
  wire NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED;
  wire NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:4]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:4]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXCHBONDO_UNCONNECTED;
  wire [63:32]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:4]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:4]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_1ln_rx_lpm_multi_gt_i/gt0_aurora_1ln_rx_lpm_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D_0),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_reg_0),
        .Q(flag2),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D_0),
        .O(flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1_n_0),
        .Q(D_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(31),
    .CLK_COR_MIN_LAT(24),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0111110111),
    .CLK_COR_SEQ_1_4(10'b0111110111),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(4),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(40),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(1),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(40),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(1),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(TX_LOCK),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(gt0_pllrefclklost_i),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT(gt0_dmonitorout_out),
        .DRPADDR(DRPADDR_IN),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN),
        .DRPDO(DRPDO_OUT),
        .DRPEN(DRPEN_IN),
        .DRPRDY(DRPRDY_OUT),
        .DRPWE(DRPWE_IN),
        .EYESCANDATAERROR(gt0_eyescandataerror_out),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(gt0_eyescanreset_in),
        .EYESCANTRIGGER(gt0_eyescantrigger_in),
        .GTGREFCLK(1'b0),
        .GTHRXN(RXN),
        .GTHRXP(RXP),
        .GTHTXN(gthe2_i_n_5),
        .GTHTXP(gthe2_i_n_6),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(SR),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(fsm_gt_rx_reset_t),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad1_in),
        .QPLLREFCLK(gt_qpllrefclk_quad1_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(gt0_rxbufreset_in),
        .RXBUFSTATUS(gt0_rxbufstatus_out),
        .RXBYTEISALIGNED(gt0_rxbyteisaligned_out),
        .RXBYTEREALIGN(gt0_rx_realign_out),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(gt0_rxcdrhold_in),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(gt0_rxcdrovrden_in),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(NLW_gthe2_i_RXCHANBONDSEQ_UNCONNECTED),
        .RXCHANISALIGNED(NLW_gthe2_i_RXCHANISALIGNED_UNCONNECTED),
        .RXCHANREALIGN(NLW_gthe2_i_RXCHANREALIGN_UNCONNECTED),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:4],rx_char_is_comma_i}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:4],RXCHARISK}),
        .RXCHBONDEN(1'b0),
        .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO(NLW_gthe2_i_RXCHBONDO_UNCONNECTED[4:0]),
        .RXCHBONDSLAVE(1'b0),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gt0_rxcommadet_out),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:32],RXDATA}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(1'b0),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(gt0_rxdfelpmreset_in),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:4],gt0_rx_disp_err_out}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(gt0_rxlpmen_in),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(ena_comma_align_i),
        .RXMONITOROUT(gt0_rxmonitorout_out),
        .RXMONITORSEL(gt0_rxmonitorsel_in),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:4],gt0_rx_not_in_table_out}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(ena_comma_align_i),
        .RXPCSRESET(gt0_rxpcsreset_in),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(gt0_rxpmareset_in),
        .RXPMARESETDONE(gt0_rxpmaresetdone_out),
        .RXPOLARITY(rx_polarity_i),
        .RXPRBSCNTRESET(gt0_rxprbscntreset_in),
        .RXPRBSERR(gt0_rxprbserr_out),
        .RXPRBSSEL(gt0_rxprbssel_in),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gt0_rxresetdone_out),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS({gthe2_i_n_112,gthe2_i_n_113}),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gthe2_i_n_624,gthe2_i_n_625,gthe2_i_n_626,gthe2_i_n_627,gthe2_i_n_628,gthe2_i_n_629,gthe2_i_n_630,gthe2_i_n_631,gthe2_i_n_632,gthe2_i_n_633,gthe2_i_n_634,gthe2_i_n_635,gthe2_i_n_636,gthe2_i_n_637,gthe2_i_n_638,gthe2_i_n_639,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(1'b0),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(1'b0),
        .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(TX_OUT_CLK),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(1'b0),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gthe2_i_n_54),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(1'b1),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT2 #(
    .INIT(4'hE)) 
    hard_err_gt_i_1
       (.I0(gt0_rx_realign_out),
        .I1(gt0_rxbufstatus_out[2]),
        .O(hard_err_gt0));
  LUT5 #(
    .INIT(32'h0116FFFF)) 
    inc_count_r_i_1
       (.I0(rx_char_is_comma_i[0]),
        .I1(rx_char_is_comma_i[1]),
        .I2(rx_char_is_comma_i[3]),
        .I3(rx_char_is_comma_i[2]),
        .I4(ena_comma_align_i),
        .O(inc_count_r0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    reset_count_r_i_2
       (.I0(gt0_rx_disp_err_out[3]),
        .I1(gt0_rx_not_in_table_out[3]),
        .I2(gt0_rx_not_in_table_out[1]),
        .I3(gt0_rx_disp_err_out[1]),
        .I4(gt0_rx_disp_err_out[0]),
        .I5(gt0_rx_disp_err_out[2]),
        .O(init_clk_in_0));
  LUT4 #(
    .INIT(16'h0010)) 
    reset_count_r_i_3
       (.I0(gt0_rx_not_in_table_out[2]),
        .I1(gt0_rx_not_in_table_out[0]),
        .I2(E),
        .I3(begin_r),
        .O(inc_count_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \soft_err_r[0]_i_1 
       (.I0(enable_err_detect_i),
        .I1(gt0_rx_disp_err_out[0]),
        .I2(gt0_rx_not_in_table_out[0]),
        .O(ENABLE_ERR_DETECT_Buffer_reg[3]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \soft_err_r[1]_i_1 
       (.I0(gt0_rx_disp_err_out[1]),
        .I1(gt0_rx_not_in_table_out[1]),
        .I2(enable_err_detect_i),
        .O(ENABLE_ERR_DETECT_Buffer_reg[2]));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \soft_err_r[2]_i_1 
       (.I0(enable_err_detect_i),
        .I1(gt0_rx_disp_err_out[2]),
        .I2(gt0_rx_not_in_table_out[2]),
        .O(ENABLE_ERR_DETECT_Buffer_reg[1]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT3 #(
    .INIT(8'hE0)) 
    \soft_err_r[3]_i_1 
       (.I0(gt0_rx_disp_err_out[3]),
        .I1(gt0_rx_not_in_table_out[3]),
        .I2(enable_err_detect_i),
        .O(ENABLE_ERR_DETECT_Buffer_reg[0]));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \word_aligned_control_bits_r[3]_i_1 
       (.I0(RXCHARISK[0]),
        .I1(RXCHARISK[1]),
        .I2(RXCHARISK[3]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXCHARISK[2]),
        .O(\left_align_select_r_reg[1] ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[16]_i_1 
       (.I0(RXDATA[23]),
        .I1(Q[3]),
        .I2(RXDATA[15]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[7]),
        .O(\previous_cycle_data_r_reg[7] [3]));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[18]_i_1 
       (.I0(RXDATA[21]),
        .I1(Q[2]),
        .I2(RXDATA[13]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[5]),
        .O(\previous_cycle_data_r_reg[7] [2]));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_data_r[20]_i_1 
       (.I0(RXDATA[19]),
        .I1(Q[1]),
        .I2(RXDATA[3]),
        .I3(\word_aligned_data_r_reg[22]_0 ),
        .I4(\word_aligned_data_r_reg[22] ),
        .I5(RXDATA[11]),
        .O(\previous_cycle_data_r_reg[7] [1]));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[22]_i_1 
       (.I0(RXDATA[17]),
        .I1(Q[0]),
        .I2(RXDATA[9]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[1]),
        .O(\previous_cycle_data_r_reg[7] [0]));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \word_aligned_data_r[24]_i_1 
       (.I0(RXDATA[31]),
        .I1(RXDATA[7]),
        .I2(RXDATA[15]),
        .I3(\word_aligned_data_r_reg[22]_0 ),
        .I4(\word_aligned_data_r_reg[22] ),
        .I5(RXDATA[23]),
        .O(D[7]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[25]_i_1 
       (.I0(RXDATA[6]),
        .I1(RXDATA[22]),
        .I2(RXDATA[30]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[14]),
        .O(D[6]));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[26]_i_1 
       (.I0(RXDATA[29]),
        .I1(RXDATA[5]),
        .I2(RXDATA[21]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[13]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[27]_i_1 
       (.I0(RXDATA[4]),
        .I1(RXDATA[20]),
        .I2(RXDATA[28]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[12]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \word_aligned_data_r[28]_i_1 
       (.I0(RXDATA[3]),
        .I1(RXDATA[11]),
        .I2(RXDATA[27]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[19]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \word_aligned_data_r[29]_i_1 
       (.I0(RXDATA[2]),
        .I1(RXDATA[10]),
        .I2(RXDATA[26]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[18]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \word_aligned_data_r[30]_i_1 
       (.I0(RXDATA[25]),
        .I1(RXDATA[1]),
        .I2(RXDATA[17]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[9]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \word_aligned_data_r[31]_i_1 
       (.I0(RXDATA[0]),
        .I1(RXDATA[16]),
        .I2(RXDATA[24]),
        .I3(\word_aligned_data_r_reg[22] ),
        .I4(\word_aligned_data_r_reg[22]_0 ),
        .I5(RXDATA[8]),
        .O(D[0]));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_multi_gt" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_multi_gt
   (TX_LOCK,
    DRPRDY_OUT,
    gt0_eyescandataerror_out,
    gt0_rxbyteisaligned_out,
    gt0_rx_realign_out,
    gt0_rxcommadet_out,
    gt0_rxpmaresetdone_out,
    gt0_rxprbserr_out,
    gt0_rxresetdone_out,
    TX_OUT_CLK,
    gt0_dmonitorout_out,
    DRPDO_OUT,
    gt0_rxbufstatus_out,
    RXDATA,
    gt0_rxmonitorout_out,
    RXCHARISK,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    ack_flag,
    hard_err_gt0,
    inc_count_r0,
    inc_count_r_reg,
    init_clk_in_0,
    \previous_cycle_data_r_reg[7] ,
    D,
    \left_align_select_r_reg[1] ,
    ENABLE_ERR_DETECT_Buffer_reg,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt0_eyescanreset_in,
    gt0_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    SR,
    fsm_gt_rx_reset_t,
    gt_qpllclk_quad1_in,
    gt_qpllrefclk_quad1_in,
    gt0_rxbufreset_in,
    gt0_rxcdrhold_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxlpmen_in,
    ena_comma_align_i,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    rx_polarity_i,
    gt0_rxprbscntreset_in,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    DRPDI_IN,
    gt0_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt0_rxprbssel_in,
    DRPADDR_IN,
    flag2_reg,
    E,
    begin_r,
    Q,
    \word_aligned_data_r_reg[22] ,
    \word_aligned_data_r_reg[22]_0 ,
    enable_err_detect_i,
    cpll_reset_i);
  output TX_LOCK;
  output DRPRDY_OUT;
  output gt0_eyescandataerror_out;
  output gt0_rxbyteisaligned_out;
  output gt0_rx_realign_out;
  output gt0_rxcommadet_out;
  output gt0_rxpmaresetdone_out;
  output gt0_rxprbserr_out;
  output gt0_rxresetdone_out;
  output TX_OUT_CLK;
  output [14:0]gt0_dmonitorout_out;
  output [15:0]DRPDO_OUT;
  output [2:0]gt0_rxbufstatus_out;
  output [31:0]RXDATA;
  output [6:0]gt0_rxmonitorout_out;
  output [3:0]RXCHARISK;
  output [3:0]gt0_rx_disp_err_out;
  output [3:0]gt0_rx_not_in_table_out;
  output ack_flag;
  output hard_err_gt0;
  output inc_count_r0;
  output inc_count_r_reg;
  output init_clk_in_0;
  output [3:0]\previous_cycle_data_r_reg[7] ;
  output [7:0]D;
  output \left_align_select_r_reg[1] ;
  output [3:0]ENABLE_ERR_DETECT_Buffer_reg;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt0_eyescanreset_in;
  input gt0_eyescantrigger_in;
  input RXN;
  input RXP;
  input gt_refclk1;
  input [0:0]SR;
  input fsm_gt_rx_reset_t;
  input gt_qpllclk_quad1_in;
  input gt_qpllrefclk_quad1_in;
  input gt0_rxbufreset_in;
  input gt0_rxcdrhold_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  input gt0_rxlpmen_in;
  input ena_comma_align_i;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  input rx_polarity_i;
  input gt0_rxprbscntreset_in;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN;
  input [1:0]gt0_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_rxprbssel_in;
  input [8:0]DRPADDR_IN;
  input flag2_reg;
  input [0:0]E;
  input begin_r;
  input [3:0]Q;
  input \word_aligned_data_r_reg[22] ;
  input \word_aligned_data_r_reg[22]_0 ;
  input enable_err_detect_i;
  input cpll_reset_i;

  wire [7:0]D;
  wire [8:0]DRPADDR_IN;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDO_OUT;
  wire DRPEN_IN;
  wire DRPRDY_OUT;
  wire DRPWE_IN;
  wire [0:0]E;
  wire [3:0]ENABLE_ERR_DETECT_Buffer_reg;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [3:0]Q;
  wire [3:0]RXCHARISK;
  wire [31:0]RXDATA;
  wire RXN;
  wire RXP;
  wire [0:0]SR;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire ack_flag;
  wire begin_r;
  wire cpll_reset_i;
  wire drpclk_in;
  wire ena_comma_align_i;
  wire enable_err_detect_i;
  wire flag2_reg;
  wire fsm_gt_rx_reset_t;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire [3:0]gt0_rx_disp_err_out;
  wire [3:0]gt0_rx_not_in_table_out;
  wire gt0_rx_realign_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt_qpllclk_quad1_in;
  wire gt_qpllrefclk_quad1_in;
  wire gt_refclk1;
  wire gt_rxuserrdy_i;
  wire hard_err_gt0;
  wire inc_count_r0;
  wire inc_count_r_reg;
  wire init_clk_in;
  wire init_clk_in_0;
  wire \left_align_select_r_reg[1] ;
  wire [3:0]\previous_cycle_data_r_reg[7] ;
  wire rx_polarity_i;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_data_r_reg[22] ;
  wire \word_aligned_data_r_reg[22]_0 ;

  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_gt gt0_aurora_1ln_rx_lpm_i
       (.D(D),
        .DRPADDR_IN(DRPADDR_IN),
        .DRPDI_IN(DRPDI_IN),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPEN_IN(DRPEN_IN),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPWE_IN(DRPWE_IN),
        .E(E),
        .ENABLE_ERR_DETECT_Buffer_reg(ENABLE_ERR_DETECT_Buffer_reg),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .Q(Q),
        .RXCHARISK(RXCHARISK),
        .RXDATA(RXDATA),
        .RXN(RXN),
        .RXP(RXP),
        .SR(SR),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .ack_flag(ack_flag),
        .begin_r(begin_r),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .ena_comma_align_i(ena_comma_align_i),
        .enable_err_detect_i(enable_err_detect_i),
        .flag2_reg_0(flag2_reg),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rx_realign_out(gt0_rx_realign_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out(gt0_rxbufstatus_out),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt_qpllclk_quad1_in(gt_qpllclk_quad1_in),
        .gt_qpllrefclk_quad1_in(gt_qpllrefclk_quad1_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .hard_err_gt0(hard_err_gt0),
        .inc_count_r0(inc_count_r0),
        .inc_count_r_reg(inc_count_r_reg),
        .init_clk_in(init_clk_in),
        .init_clk_in_0(init_clk_in_0),
        .\left_align_select_r_reg[1] (\left_align_select_r_reg[1] ),
        .\previous_cycle_data_r_reg[7] (\previous_cycle_data_r_reg[7] ),
        .rx_polarity_i(rx_polarity_i),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_data_r_reg[22] (\word_aligned_data_r_reg[22] ),
        .\word_aligned_data_r_reg[22]_0 (\word_aligned_data_r_reg[22]_0 ));
endmodule

(* ORIG_REF_NAME = "aurora_1ln_rx_lpm_rx_startup_fsm" *) 
module aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_rx_startup_fsm
   (fsm_gt_rx_reset_t,
    gt_rxuserrdy_i,
    cpll_reset_i,
    CPLL_RESET_reg_0,
    TX_LOCK,
    init_clk_in,
    user_clk,
    rxfsm_rxresetdone_r,
    AR,
    reset_time_out_reg_0,
    ack_flag);
  output fsm_gt_rx_reset_t;
  output gt_rxuserrdy_i;
  output cpll_reset_i;
  output CPLL_RESET_reg_0;
  input TX_LOCK;
  input init_clk_in;
  input user_clk;
  input rxfsm_rxresetdone_r;
  input [0:0]AR;
  input reset_time_out_reg_0;
  input ack_flag;

  wire [0:0]AR;
  wire CPLL_RESET_i_1_n_0;
  wire CPLL_RESET_reg_0;
  wire \FSM_sequential_rx_state[0]_i_2_n_0 ;
  wire \FSM_sequential_rx_state[1]_i_2_n_0 ;
  wire \FSM_sequential_rx_state[2]_i_2_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_10_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_11_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_12_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_14_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_15_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_16_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_4_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_5_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_6_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_8_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_9_n_0 ;
  wire RXUSERRDY_i_1_n_0;
  wire TX_LOCK;
  wire ack_flag;
  wire check_tlock_max_i_1_n_0;
  wire check_tlock_max_reg_n_0;
  wire clear;
  wire cpll_reset_i;
  wire fsm_gt_rx_reset_t;
  wire gt_rxuserrdy_i;
  wire gtrxreset_i_i_1_n_0;
  wire init_clk_in;
  wire init_wait_count;
  wire \init_wait_count[6]_i_3_n_0 ;
  wire \init_wait_count[6]_i_4_n_0 ;
  wire [6:0]init_wait_count_reg;
  wire init_wait_done_i_1_n_0;
  wire init_wait_done_i_2_n_0;
  wire init_wait_done_reg_n_0;
  wire \mmcm_lock_count[9]_i_2_n_0 ;
  wire \mmcm_lock_count[9]_i_4_n_0 ;
  wire [9:0]mmcm_lock_count_reg;
  wire mmcm_lock_reclocked;
  wire mmcm_lock_reclocked_i_2_n_0;
  wire [6:0]p_0_in;
  wire [9:0]p_0_in__1;
  wire pll_reset_asserted_i_1_n_0;
  wire pll_reset_asserted_reg_n_0;
  wire reset_time_out_reg_0;
  wire reset_time_out_reg_n_0;
  wire run_phase_alignment_int;
  wire run_phase_alignment_int_i_1_n_0;
  wire run_phase_alignment_int_s2;
  wire run_phase_alignment_int_s3;
  wire rx_fsm_reset_done_int;
  wire rx_fsm_reset_done_int_0;
  wire rx_fsm_reset_done_int_i_1_n_0;
  wire rx_fsm_reset_done_int_i_3_n_0;
  wire rx_fsm_reset_done_int_i_4_n_0;
  wire rx_fsm_reset_done_int_i_5_n_0;
  wire rx_fsm_reset_done_int_s3;
  wire [3:0]rx_state;
  wire [3:0]rx_state__0;
  wire rxfsm_rxresetdone_r;
  wire rxpmaresetdone_i;
  wire rxpmaresetdone_rx_s;
  wire rxresetdone_s2;
  wire rxresetdone_s3;
  wire scndry_out;
  wire sel;
  wire sync_CPLLLOCK_cdc_sync_n_0;
  wire sync_CPLLLOCK_cdc_sync_n_1;
  wire sync_mmcm_lock_reclocked_cdc_sync_n_0;
  wire sync_mmcm_lock_reclocked_cdc_sync_n_1;
  wire sync_rx_fsm_reset_done_int_cdc_sync_n_0;
  wire time_out_100us_i_1_n_0;
  wire time_out_100us_i_2_n_0;
  wire time_out_100us_i_3_n_0;
  wire time_out_100us_i_4_n_0;
  wire time_out_100us_reg_n_0;
  wire time_out_1us_i_1_n_0;
  wire time_out_1us_i_2_n_0;
  wire time_out_1us_i_3_n_0;
  wire time_out_1us_i_4_n_0;
  wire time_out_1us_reg_n_0;
  wire time_out_2ms_i_1_n_0;
  wire time_out_2ms_i_2_n_0;
  wire time_out_2ms_i_3_n_0;
  wire time_out_2ms_reg_n_0;
  wire time_out_counter;
  wire \time_out_counter[0]_i_3_n_0 ;
  wire \time_out_counter[0]_i_4_n_0 ;
  wire \time_out_counter[0]_i_5_n_0 ;
  wire \time_out_counter[0]_i_6_n_0 ;
  wire \time_out_counter[0]_i_7_n_0 ;
  wire \time_out_counter[0]_i_8_n_0 ;
  wire [18:0]time_out_counter_reg;
  wire \time_out_counter_reg[0]_i_2_n_0 ;
  wire \time_out_counter_reg[0]_i_2_n_1 ;
  wire \time_out_counter_reg[0]_i_2_n_2 ;
  wire \time_out_counter_reg[0]_i_2_n_3 ;
  wire \time_out_counter_reg[0]_i_2_n_4 ;
  wire \time_out_counter_reg[0]_i_2_n_5 ;
  wire \time_out_counter_reg[0]_i_2_n_6 ;
  wire \time_out_counter_reg[0]_i_2_n_7 ;
  wire \time_out_counter_reg[12]_i_1_n_0 ;
  wire \time_out_counter_reg[12]_i_1_n_1 ;
  wire \time_out_counter_reg[12]_i_1_n_2 ;
  wire \time_out_counter_reg[12]_i_1_n_3 ;
  wire \time_out_counter_reg[12]_i_1_n_4 ;
  wire \time_out_counter_reg[12]_i_1_n_5 ;
  wire \time_out_counter_reg[12]_i_1_n_6 ;
  wire \time_out_counter_reg[12]_i_1_n_7 ;
  wire \time_out_counter_reg[16]_i_1_n_2 ;
  wire \time_out_counter_reg[16]_i_1_n_3 ;
  wire \time_out_counter_reg[16]_i_1_n_5 ;
  wire \time_out_counter_reg[16]_i_1_n_6 ;
  wire \time_out_counter_reg[16]_i_1_n_7 ;
  wire \time_out_counter_reg[4]_i_1_n_0 ;
  wire \time_out_counter_reg[4]_i_1_n_1 ;
  wire \time_out_counter_reg[4]_i_1_n_2 ;
  wire \time_out_counter_reg[4]_i_1_n_3 ;
  wire \time_out_counter_reg[4]_i_1_n_4 ;
  wire \time_out_counter_reg[4]_i_1_n_5 ;
  wire \time_out_counter_reg[4]_i_1_n_6 ;
  wire \time_out_counter_reg[4]_i_1_n_7 ;
  wire \time_out_counter_reg[8]_i_1_n_0 ;
  wire \time_out_counter_reg[8]_i_1_n_1 ;
  wire \time_out_counter_reg[8]_i_1_n_2 ;
  wire \time_out_counter_reg[8]_i_1_n_3 ;
  wire \time_out_counter_reg[8]_i_1_n_4 ;
  wire \time_out_counter_reg[8]_i_1_n_5 ;
  wire \time_out_counter_reg[8]_i_1_n_6 ;
  wire \time_out_counter_reg[8]_i_1_n_7 ;
  wire time_out_wait_bypass;
  wire time_out_wait_bypass_i_1_n_0;
  wire time_out_wait_bypass_s2;
  wire time_out_wait_bypass_s3;
  wire time_tlock_max;
  wire time_tlock_max1;
  wire time_tlock_max1_carry__0_i_1_n_0;
  wire time_tlock_max1_carry__0_i_2_n_0;
  wire time_tlock_max1_carry__0_i_3_n_0;
  wire time_tlock_max1_carry__0_i_4_n_0;
  wire time_tlock_max1_carry__0_i_5_n_0;
  wire time_tlock_max1_carry__0_i_6_n_0;
  wire time_tlock_max1_carry__0_i_7_n_0;
  wire time_tlock_max1_carry__0_n_0;
  wire time_tlock_max1_carry__0_n_1;
  wire time_tlock_max1_carry__0_n_2;
  wire time_tlock_max1_carry__0_n_3;
  wire time_tlock_max1_carry__1_i_1_n_0;
  wire time_tlock_max1_carry__1_i_2_n_0;
  wire time_tlock_max1_carry__1_i_3_n_0;
  wire time_tlock_max1_carry__1_n_3;
  wire time_tlock_max1_carry_i_1_n_0;
  wire time_tlock_max1_carry_i_2_n_0;
  wire time_tlock_max1_carry_i_3_n_0;
  wire time_tlock_max1_carry_i_4_n_0;
  wire time_tlock_max1_carry_i_5_n_0;
  wire time_tlock_max1_carry_n_0;
  wire time_tlock_max1_carry_n_1;
  wire time_tlock_max1_carry_n_2;
  wire time_tlock_max1_carry_n_3;
  wire time_tlock_max_i_1_n_0;
  wire user_clk;
  wire \wait_bypass_count[0]_i_2_n_0 ;
  wire \wait_bypass_count[0]_i_4_n_0 ;
  wire \wait_bypass_count[0]_i_5_n_0 ;
  wire \wait_bypass_count[0]_i_6_n_0 ;
  wire \wait_bypass_count[0]_i_7_n_0 ;
  wire [12:0]wait_bypass_count_reg;
  wire \wait_bypass_count_reg[0]_i_3_n_0 ;
  wire \wait_bypass_count_reg[0]_i_3_n_1 ;
  wire \wait_bypass_count_reg[0]_i_3_n_2 ;
  wire \wait_bypass_count_reg[0]_i_3_n_3 ;
  wire \wait_bypass_count_reg[0]_i_3_n_4 ;
  wire \wait_bypass_count_reg[0]_i_3_n_5 ;
  wire \wait_bypass_count_reg[0]_i_3_n_6 ;
  wire \wait_bypass_count_reg[0]_i_3_n_7 ;
  wire \wait_bypass_count_reg[12]_i_1_n_7 ;
  wire \wait_bypass_count_reg[4]_i_1_n_0 ;
  wire \wait_bypass_count_reg[4]_i_1_n_1 ;
  wire \wait_bypass_count_reg[4]_i_1_n_2 ;
  wire \wait_bypass_count_reg[4]_i_1_n_3 ;
  wire \wait_bypass_count_reg[4]_i_1_n_4 ;
  wire \wait_bypass_count_reg[4]_i_1_n_5 ;
  wire \wait_bypass_count_reg[4]_i_1_n_6 ;
  wire \wait_bypass_count_reg[4]_i_1_n_7 ;
  wire \wait_bypass_count_reg[8]_i_1_n_0 ;
  wire \wait_bypass_count_reg[8]_i_1_n_1 ;
  wire \wait_bypass_count_reg[8]_i_1_n_2 ;
  wire \wait_bypass_count_reg[8]_i_1_n_3 ;
  wire \wait_bypass_count_reg[8]_i_1_n_4 ;
  wire \wait_bypass_count_reg[8]_i_1_n_5 ;
  wire \wait_bypass_count_reg[8]_i_1_n_6 ;
  wire \wait_bypass_count_reg[8]_i_1_n_7 ;
  wire [6:0]wait_time_cnt0;
  wire \wait_time_cnt[6]_i_1_n_0 ;
  wire \wait_time_cnt[6]_i_4_n_0 ;
  wire [6:0]wait_time_cnt_reg;
  wire [3:2]\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED ;
  wire [3:0]NLW_time_tlock_max1_carry_O_UNCONNECTED;
  wire [3:0]NLW_time_tlock_max1_carry__0_O_UNCONNECTED;
  wire [3:2]NLW_time_tlock_max1_carry__1_CO_UNCONNECTED;
  wire [3:0]NLW_time_tlock_max1_carry__1_O_UNCONNECTED;
  wire [3:0]\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFFFFFDFF00000100)) 
    CPLL_RESET_i_1
       (.I0(pll_reset_asserted_reg_n_0),
        .I1(rx_state[3]),
        .I2(rx_state[2]),
        .I3(rx_state[0]),
        .I4(rx_state[1]),
        .I5(cpll_reset_i),
        .O(CPLL_RESET_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    CPLL_RESET_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(CPLL_RESET_i_1_n_0),
        .Q(cpll_reset_i),
        .R(AR));
  LUT5 #(
    .INIT(32'hFFEFEFEF)) 
    \FSM_sequential_rx_state[0]_i_1 
       (.I0(\FSM_sequential_rx_state[0]_i_2_n_0 ),
        .I1(\FSM_sequential_rx_state[3]_i_5_n_0 ),
        .I2(rx_state[0]),
        .I3(rx_state[1]),
        .I4(rx_state[3]),
        .O(rx_state__0[0]));
  LUT6 #(
    .INIT(64'h2222AAAA00300000)) 
    \FSM_sequential_rx_state[0]_i_2 
       (.I0(time_out_2ms_reg_n_0),
        .I1(reset_time_out_reg_n_0),
        .I2(time_tlock_max),
        .I3(rx_state[3]),
        .I4(rx_state[2]),
        .I5(rx_state[1]),
        .O(\FSM_sequential_rx_state[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00F00010)) 
    \FSM_sequential_rx_state[1]_i_1 
       (.I0(rx_state[3]),
        .I1(rx_state[2]),
        .I2(rx_state[0]),
        .I3(rx_state[1]),
        .I4(reset_time_out_reg_n_0),
        .I5(\FSM_sequential_rx_state[1]_i_2_n_0 ),
        .O(rx_state__0[1]));
  LUT6 #(
    .INIT(64'h303000301C1C1C1C)) 
    \FSM_sequential_rx_state[1]_i_2 
       (.I0(time_tlock_max),
        .I1(rx_state[1]),
        .I2(rx_state[0]),
        .I3(time_out_100us_reg_n_0),
        .I4(gt_rxuserrdy_i),
        .I5(rx_state[3]),
        .O(\FSM_sequential_rx_state[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h010C0C0C01000C0C)) 
    \FSM_sequential_rx_state[2]_i_1 
       (.I0(time_out_2ms_reg_n_0),
        .I1(rx_state[2]),
        .I2(rx_state[3]),
        .I3(rx_state[1]),
        .I4(rx_state[0]),
        .I5(\FSM_sequential_rx_state[2]_i_2_n_0 ),
        .O(rx_state__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_rx_state[2]_i_2 
       (.I0(reset_time_out_reg_n_0),
        .I1(time_tlock_max),
        .O(\FSM_sequential_rx_state[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_rx_state[3]_i_10 
       (.I0(time_out_100us_reg_n_0),
        .I1(gt_rxuserrdy_i),
        .I2(reset_time_out_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \FSM_sequential_rx_state[3]_i_11 
       (.I0(rx_state[0]),
        .I1(rx_state[1]),
        .O(\FSM_sequential_rx_state[3]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \FSM_sequential_rx_state[3]_i_12 
       (.I0(rx_state[3]),
        .I1(rx_state[2]),
        .I2(rx_state[0]),
        .I3(rx_state[1]),
        .O(\FSM_sequential_rx_state[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h000000008F888888)) 
    \FSM_sequential_rx_state[3]_i_14 
       (.I0(rx_state[3]),
        .I1(gt_rxuserrdy_i),
        .I2(rx_state[0]),
        .I3(rx_state[2]),
        .I4(reset_time_out_reg_0),
        .I5(rx_state[1]),
        .O(\FSM_sequential_rx_state[3]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_rx_state[3]_i_15 
       (.I0(rx_state[1]),
        .I1(rx_state[0]),
        .O(\FSM_sequential_rx_state[3]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h0100)) 
    \FSM_sequential_rx_state[3]_i_16 
       (.I0(rx_state[1]),
        .I1(rx_state[0]),
        .I2(rx_state[2]),
        .I3(init_wait_done_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAAAEAEFAAAA)) 
    \FSM_sequential_rx_state[3]_i_2 
       (.I0(\FSM_sequential_rx_state[3]_i_9_n_0 ),
        .I1(\FSM_sequential_rx_state[3]_i_10_n_0 ),
        .I2(rx_state[0]),
        .I3(time_out_wait_bypass_s3),
        .I4(rx_state[3]),
        .I5(rx_state[1]),
        .O(rx_state__0[3]));
  LUT6 #(
    .INIT(64'h000400C000040000)) 
    \FSM_sequential_rx_state[3]_i_4 
       (.I0(\FSM_sequential_rx_state[2]_i_2_n_0 ),
        .I1(rx_state[0]),
        .I2(rx_state[1]),
        .I3(rx_state[3]),
        .I4(rx_state[2]),
        .I5(time_out_2ms_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'h0200)) 
    \FSM_sequential_rx_state[3]_i_5 
       (.I0(rx_state[3]),
        .I1(reset_time_out_reg_n_0),
        .I2(gt_rxuserrdy_i),
        .I3(time_out_100us_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAEAFFAAAAEA)) 
    \FSM_sequential_rx_state[3]_i_6 
       (.I0(\FSM_sequential_rx_state[3]_i_14_n_0 ),
        .I1(mmcm_lock_reclocked),
        .I2(rx_state[2]),
        .I3(rx_state[3]),
        .I4(\FSM_sequential_rx_state[3]_i_15_n_0 ),
        .I5(gt_rxuserrdy_i),
        .O(\FSM_sequential_rx_state[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAABAAAA)) 
    \FSM_sequential_rx_state[3]_i_8 
       (.I0(\FSM_sequential_rx_state[3]_i_16_n_0 ),
        .I1(\wait_time_cnt[6]_i_4_n_0 ),
        .I2(wait_time_cnt_reg[6]),
        .I3(rx_state[3]),
        .I4(rx_state[1]),
        .I5(rx_state[0]),
        .O(\FSM_sequential_rx_state[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT5 #(
    .INIT(32'h80800080)) 
    \FSM_sequential_rx_state[3]_i_9 
       (.I0(rx_state[0]),
        .I1(rx_state[1]),
        .I2(rx_state[2]),
        .I3(time_out_2ms_reg_n_0),
        .I4(reset_time_out_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[0] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[0]),
        .Q(rx_state[0]),
        .R(AR));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[1] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[1]),
        .Q(rx_state[1]),
        .R(AR));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[2] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[2]),
        .Q(rx_state[2]),
        .R(AR));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[3] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[3]),
        .Q(rx_state[3]),
        .R(AR));
  LUT5 #(
    .INIT(32'hFFFB0080)) 
    RXUSERRDY_i_1
       (.I0(rx_state[1]),
        .I1(rx_state[0]),
        .I2(rx_state[2]),
        .I3(rx_state[3]),
        .I4(gt_rxuserrdy_i),
        .O(RXUSERRDY_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    RXUSERRDY_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(RXUSERRDY_i_1_n_0),
        .Q(gt_rxuserrdy_i),
        .R(AR));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    check_tlock_max_i_1
       (.I0(rx_state[2]),
        .I1(rx_state[0]),
        .I2(rx_state[1]),
        .I3(rx_state[3]),
        .I4(check_tlock_max_reg_n_0),
        .O(check_tlock_max_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    check_tlock_max_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(check_tlock_max_i_1_n_0),
        .Q(check_tlock_max_reg_n_0),
        .R(AR));
  LUT2 #(
    .INIT(4'h2)) 
    flag2_i_1
       (.I0(cpll_reset_i),
        .I1(ack_flag),
        .O(CPLL_RESET_reg_0));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_2 gtrxreset_cdc_sync
       (.fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .init_clk_in(init_clk_in),
        .out(scndry_out),
        .user_clk(user_clk));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT5 #(
    .INIT(32'hFFEF0004)) 
    gtrxreset_i_i_1
       (.I0(rx_state[1]),
        .I1(rx_state[0]),
        .I2(rx_state[2]),
        .I3(rx_state[3]),
        .I4(fsm_gt_rx_reset_t),
        .O(gtrxreset_i_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gtrxreset_i_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_i_i_1_n_0),
        .Q(fsm_gt_rx_reset_t),
        .R(AR));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \init_wait_count[0]_i_1 
       (.I0(init_wait_count_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \init_wait_count[1]_i_1 
       (.I0(init_wait_count_reg[0]),
        .I1(init_wait_count_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \init_wait_count[2]_i_1 
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \init_wait_count[3]_i_1 
       (.I0(init_wait_count_reg[2]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[1]),
        .I3(init_wait_count_reg[3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \init_wait_count[4]_i_1 
       (.I0(init_wait_count_reg[3]),
        .I1(init_wait_count_reg[1]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_count_reg[2]),
        .I4(init_wait_count_reg[4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \init_wait_count[5]_i_1 
       (.I0(init_wait_count_reg[4]),
        .I1(init_wait_count_reg[2]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_count_reg[1]),
        .I4(init_wait_count_reg[3]),
        .I5(init_wait_count_reg[5]),
        .O(p_0_in[5]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \init_wait_count[6]_i_1 
       (.I0(init_wait_count_reg[4]),
        .I1(\init_wait_count[6]_i_3_n_0 ),
        .I2(init_wait_count_reg[2]),
        .I3(init_wait_count_reg[3]),
        .I4(init_wait_count_reg[1]),
        .I5(init_wait_count_reg[0]),
        .O(init_wait_count));
  LUT3 #(
    .INIT(8'hC6)) 
    \init_wait_count[6]_i_2 
       (.I0(init_wait_count_reg[5]),
        .I1(init_wait_count_reg[6]),
        .I2(\init_wait_count[6]_i_4_n_0 ),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_wait_count[6]_i_3 
       (.I0(init_wait_count_reg[5]),
        .I1(init_wait_count_reg[6]),
        .O(\init_wait_count[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \init_wait_count[6]_i_4 
       (.I0(init_wait_count_reg[3]),
        .I1(init_wait_count_reg[1]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_count_reg[2]),
        .I4(init_wait_count_reg[4]),
        .O(\init_wait_count[6]_i_4_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[0] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[0]),
        .Q(init_wait_count_reg[0]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[1] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[1]),
        .Q(init_wait_count_reg[1]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[2] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[2]),
        .Q(init_wait_count_reg[2]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[3] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[3]),
        .Q(init_wait_count_reg[3]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[4] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[4]),
        .Q(init_wait_count_reg[4]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[5] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[5]),
        .Q(init_wait_count_reg[5]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[6] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[6]),
        .Q(init_wait_count_reg[6]));
  LUT5 #(
    .INIT(32'hFFFF0100)) 
    init_wait_done_i_1
       (.I0(init_wait_count_reg[2]),
        .I1(init_wait_count_reg[1]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_done_i_2_n_0),
        .I4(init_wait_done_reg_n_0),
        .O(init_wait_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    init_wait_done_i_2
       (.I0(init_wait_count_reg[4]),
        .I1(init_wait_count_reg[3]),
        .I2(init_wait_count_reg[6]),
        .I3(init_wait_count_reg[5]),
        .O(init_wait_done_i_2_n_0));
  FDCE #(
    .INIT(1'b0)) 
    init_wait_done_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(AR),
        .D(init_wait_done_i_1_n_0),
        .Q(init_wait_done_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \mmcm_lock_count[0]_i_1 
       (.I0(mmcm_lock_count_reg[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \mmcm_lock_count[1]_i_1 
       (.I0(mmcm_lock_count_reg[0]),
        .I1(mmcm_lock_count_reg[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \mmcm_lock_count[2]_i_1 
       (.I0(mmcm_lock_count_reg[1]),
        .I1(mmcm_lock_count_reg[0]),
        .I2(mmcm_lock_count_reg[2]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \mmcm_lock_count[3]_i_1 
       (.I0(mmcm_lock_count_reg[2]),
        .I1(mmcm_lock_count_reg[0]),
        .I2(mmcm_lock_count_reg[1]),
        .I3(mmcm_lock_count_reg[3]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \mmcm_lock_count[4]_i_1 
       (.I0(mmcm_lock_count_reg[3]),
        .I1(mmcm_lock_count_reg[1]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[2]),
        .I4(mmcm_lock_count_reg[4]),
        .O(p_0_in__1[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \mmcm_lock_count[5]_i_1 
       (.I0(mmcm_lock_count_reg[4]),
        .I1(mmcm_lock_count_reg[2]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[1]),
        .I4(mmcm_lock_count_reg[3]),
        .I5(mmcm_lock_count_reg[5]),
        .O(p_0_in__1[5]));
  LUT2 #(
    .INIT(4'h9)) 
    \mmcm_lock_count[6]_i_1 
       (.I0(\mmcm_lock_count[9]_i_4_n_0 ),
        .I1(mmcm_lock_count_reg[6]),
        .O(p_0_in__1[6]));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \mmcm_lock_count[7]_i_1 
       (.I0(mmcm_lock_count_reg[6]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[7]),
        .O(p_0_in__1[7]));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \mmcm_lock_count[8]_i_1 
       (.I0(mmcm_lock_count_reg[7]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[6]),
        .I3(mmcm_lock_count_reg[8]),
        .O(p_0_in__1[8]));
  LUT5 #(
    .INIT(32'hDFFFFFFF)) 
    \mmcm_lock_count[9]_i_2 
       (.I0(mmcm_lock_count_reg[7]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[6]),
        .I3(mmcm_lock_count_reg[8]),
        .I4(mmcm_lock_count_reg[9]),
        .O(\mmcm_lock_count[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \mmcm_lock_count[9]_i_3 
       (.I0(mmcm_lock_count_reg[8]),
        .I1(mmcm_lock_count_reg[6]),
        .I2(\mmcm_lock_count[9]_i_4_n_0 ),
        .I3(mmcm_lock_count_reg[7]),
        .I4(mmcm_lock_count_reg[9]),
        .O(p_0_in__1[9]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \mmcm_lock_count[9]_i_4 
       (.I0(mmcm_lock_count_reg[4]),
        .I1(mmcm_lock_count_reg[2]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[1]),
        .I4(mmcm_lock_count_reg[3]),
        .I5(mmcm_lock_count_reg[5]),
        .O(\mmcm_lock_count[9]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[0] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[0]),
        .Q(mmcm_lock_count_reg[0]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[1] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[1]),
        .Q(mmcm_lock_count_reg[1]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[2] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[2]),
        .Q(mmcm_lock_count_reg[2]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[3] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[3]),
        .Q(mmcm_lock_count_reg[3]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[4] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[4]),
        .Q(mmcm_lock_count_reg[4]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[5] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[5]),
        .Q(mmcm_lock_count_reg[5]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[6] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[6]),
        .Q(mmcm_lock_count_reg[6]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[7] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[7]),
        .Q(mmcm_lock_count_reg[7]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[8] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[8]),
        .Q(mmcm_lock_count_reg[8]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[9] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__1[9]),
        .Q(mmcm_lock_count_reg[9]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_0));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    mmcm_lock_reclocked_i_2
       (.I0(mmcm_lock_count_reg[9]),
        .I1(mmcm_lock_count_reg[8]),
        .I2(mmcm_lock_count_reg[6]),
        .I3(\mmcm_lock_count[9]_i_4_n_0 ),
        .I4(mmcm_lock_count_reg[7]),
        .O(mmcm_lock_reclocked_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mmcm_lock_reclocked_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(sync_mmcm_lock_reclocked_cdc_sync_n_1),
        .Q(mmcm_lock_reclocked),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFDFF0100)) 
    pll_reset_asserted_i_1
       (.I0(rx_state[1]),
        .I1(rx_state[2]),
        .I2(rx_state[3]),
        .I3(rx_state[0]),
        .I4(pll_reset_asserted_reg_n_0),
        .O(pll_reset_asserted_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pll_reset_asserted_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(pll_reset_asserted_i_1_n_0),
        .Q(pll_reset_asserted_reg_n_0),
        .R(AR));
  FDSE #(
    .INIT(1'b0)) 
    reset_time_out_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(sync_CPLLLOCK_cdc_sync_n_1),
        .Q(reset_time_out_reg_n_0),
        .S(AR));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT5 #(
    .INIT(32'hFFFB0100)) 
    run_phase_alignment_int_i_1
       (.I0(rx_state[1]),
        .I1(rx_state[0]),
        .I2(rx_state[2]),
        .I3(rx_state[3]),
        .I4(run_phase_alignment_int),
        .O(run_phase_alignment_int_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    run_phase_alignment_int_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(run_phase_alignment_int_i_1_n_0),
        .Q(run_phase_alignment_int),
        .R(AR));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    run_phase_alignment_int_s3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(run_phase_alignment_int_s2),
        .Q(run_phase_alignment_int_s3),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hABA8)) 
    rx_fsm_reset_done_int_i_1
       (.I0(rx_fsm_reset_done_int_0),
        .I1(rx_fsm_reset_done_int_i_3_n_0),
        .I2(rx_fsm_reset_done_int_i_4_n_0),
        .I3(rx_fsm_reset_done_int),
        .O(rx_fsm_reset_done_int_i_1_n_0));
  LUT5 #(
    .INIT(32'h00040000)) 
    rx_fsm_reset_done_int_i_2
       (.I0(rx_state[0]),
        .I1(time_out_1us_reg_n_0),
        .I2(rx_state[2]),
        .I3(reset_time_out_reg_n_0),
        .I4(gt_rxuserrdy_i),
        .O(rx_fsm_reset_done_int_0));
  LUT6 #(
    .INIT(64'h0400040004040400)) 
    rx_fsm_reset_done_int_i_3
       (.I0(\FSM_sequential_rx_state[3]_i_15_n_0 ),
        .I1(rx_state[3]),
        .I2(rx_state[2]),
        .I3(gt_rxuserrdy_i),
        .I4(time_out_100us_reg_n_0),
        .I5(reset_time_out_reg_n_0),
        .O(rx_fsm_reset_done_int_i_3_n_0));
  LUT6 #(
    .INIT(64'h0008000808080008)) 
    rx_fsm_reset_done_int_i_4
       (.I0(rx_fsm_reset_done_int_i_5_n_0),
        .I1(rx_state[1]),
        .I2(rx_state[0]),
        .I3(gt_rxuserrdy_i),
        .I4(time_out_1us_reg_n_0),
        .I5(reset_time_out_reg_n_0),
        .O(rx_fsm_reset_done_int_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rx_fsm_reset_done_int_i_5
       (.I0(rx_state[3]),
        .I1(rx_state[2]),
        .O(rx_fsm_reset_done_int_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rx_fsm_reset_done_int_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_fsm_reset_done_int_i_1_n_0),
        .Q(rx_fsm_reset_done_int),
        .R(AR));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    rx_fsm_reset_done_int_s3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
        .Q(rx_fsm_reset_done_int_s3),
        .R(1'b0));
  FDCE #(
    .INIT(1'b0)) 
    rxpmaresetdone_i_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(scndry_out),
        .D(rxpmaresetdone_rx_s),
        .Q(rxpmaresetdone_i));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    rxresetdone_s3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rxresetdone_s2),
        .Q(rxresetdone_s3),
        .R(1'b0));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_3 sync_CPLLLOCK_cdc_sync
       (.E(sync_CPLLLOCK_cdc_sync_n_0),
        .\FSM_sequential_rx_state_reg[0] (\FSM_sequential_rx_state[3]_i_4_n_0 ),
        .\FSM_sequential_rx_state_reg[0]_0 (\FSM_sequential_rx_state[3]_i_5_n_0 ),
        .\FSM_sequential_rx_state_reg[0]_1 (\FSM_sequential_rx_state[3]_i_8_n_0 ),
        .\FSM_sequential_rx_state_reg[0]_2 (time_out_2ms_reg_n_0),
        .\FSM_sequential_rx_state_reg[0]_3 (\FSM_sequential_rx_state[3]_i_11_n_0 ),
        .\FSM_sequential_rx_state_reg[0]_4 (\FSM_sequential_rx_state[3]_i_12_n_0 ),
        .\FSM_sequential_rx_state_reg[1] (sync_CPLLLOCK_cdc_sync_n_1),
        .Q(rx_state),
        .TX_LOCK(TX_LOCK),
        .init_clk_in(init_clk_in),
        .reset_time_out_reg(reset_time_out_reg_0),
        .reset_time_out_reg_0(\FSM_sequential_rx_state[3]_i_6_n_0 ),
        .reset_time_out_reg_1(reset_time_out_reg_n_0),
        .reset_time_out_reg_2(pll_reset_asserted_reg_n_0),
        .rxresetdone_s3(rxresetdone_s3));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_4 sync_QPLLLOCK_cdc_sync
       (.init_clk_in(init_clk_in));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_5 sync_RXRESETDONE_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(rxresetdone_s2),
        .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_6 sync_mmcm_lock_reclocked_cdc_sync
       (.SR(sync_mmcm_lock_reclocked_cdc_sync_n_0),
        .init_clk_in(init_clk_in),
        .mmcm_lock_reclocked(mmcm_lock_reclocked),
        .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_cdc_sync_n_1),
        .mmcm_lock_reclocked_reg_0(mmcm_lock_reclocked_i_2_n_0));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_7 sync_pmaresetdone_fallingedge_detect_cdc_sync
       (.init_clk_in(init_clk_in),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_8 sync_run_phase_alignment_int_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(run_phase_alignment_int_s2),
        .run_phase_alignment_int(run_phase_alignment_int),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_9 sync_rx_fsm_reset_done_int_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
        .rx_fsm_reset_done_int(rx_fsm_reset_done_int),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_10 sync_rxpmaresetdone_cdc_sync
       (.init_clk_in(init_clk_in),
        .rxpmaresetdone_i(rxpmaresetdone_i),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync_11 sync_rxpmaresetdone_rx_s_cdc_sync
       (.out(rxpmaresetdone_rx_s),
        .user_clk(user_clk));
  aurora_1ln_rx_lpm_aurora_1ln_rx_lpm_cdc_sync__parameterized2_12 sync_time_out_wait_bypass_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(time_out_wait_bypass_s2),
        .time_out_wait_bypass(time_out_wait_bypass),
        .user_clk(user_clk));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT5 #(
    .INIT(32'hFFFF0002)) 
    time_out_100us_i_1
       (.I0(time_out_100us_i_2_n_0),
        .I1(\time_out_counter[0]_i_3_n_0 ),
        .I2(time_out_counter_reg[11]),
        .I3(time_out_counter_reg[10]),
        .I4(time_out_100us_reg_n_0),
        .O(time_out_100us_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    time_out_100us_i_2
       (.I0(time_out_100us_i_3_n_0),
        .I1(time_out_100us_i_4_n_0),
        .I2(\time_out_counter[0]_i_5_n_0 ),
        .I3(time_out_counter_reg[2]),
        .I4(time_out_counter_reg[3]),
        .I5(time_out_counter_reg[18]),
        .O(time_out_100us_i_2_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    time_out_100us_i_3
       (.I0(time_out_counter_reg[16]),
        .I1(time_out_counter_reg[17]),
        .O(time_out_100us_i_3_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    time_out_100us_i_4
       (.I0(time_out_counter_reg[14]),
        .I1(time_out_counter_reg[15]),
        .O(time_out_100us_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_100us_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_100us_i_1_n_0),
        .Q(time_out_100us_reg_n_0),
        .R(reset_time_out_reg_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF02000000)) 
    time_out_1us_i_1
       (.I0(time_out_1us_i_2_n_0),
        .I1(time_out_1us_i_3_n_0),
        .I2(\time_out_counter[0]_i_5_n_0 ),
        .I3(time_out_counter_reg[3]),
        .I4(time_out_1us_i_4_n_0),
        .I5(time_out_1us_reg_n_0),
        .O(time_out_1us_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    time_out_1us_i_2
       (.I0(time_out_100us_i_4_n_0),
        .I1(time_out_100us_i_3_n_0),
        .I2(time_out_counter_reg[2]),
        .I3(time_out_counter_reg[4]),
        .I4(time_out_counter_reg[0]),
        .I5(time_out_counter_reg[1]),
        .O(time_out_1us_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT2 #(
    .INIT(4'hE)) 
    time_out_1us_i_3
       (.I0(time_out_counter_reg[10]),
        .I1(time_out_counter_reg[11]),
        .O(time_out_1us_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    time_out_1us_i_4
       (.I0(time_out_counter_reg[7]),
        .I1(time_out_counter_reg[12]),
        .I2(time_out_counter_reg[5]),
        .I3(time_out_counter_reg[6]),
        .I4(time_out_counter_reg[18]),
        .I5(time_out_counter_reg[13]),
        .O(time_out_1us_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_1us_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_1us_i_1_n_0),
        .Q(time_out_1us_reg_n_0),
        .R(reset_time_out_reg_n_0));
  LUT4 #(
    .INIT(16'hFF08)) 
    time_out_2ms_i_1
       (.I0(time_out_2ms_i_2_n_0),
        .I1(time_out_2ms_i_3_n_0),
        .I2(\time_out_counter[0]_i_3_n_0 ),
        .I3(time_out_2ms_reg_n_0),
        .O(time_out_2ms_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000008000000000)) 
    time_out_2ms_i_2
       (.I0(time_out_counter_reg[15]),
        .I1(time_out_counter_reg[16]),
        .I2(time_out_counter_reg[11]),
        .I3(time_out_counter_reg[14]),
        .I4(time_out_counter_reg[17]),
        .I5(time_out_counter_reg[18]),
        .O(time_out_2ms_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT5 #(
    .INIT(32'h00000010)) 
    time_out_2ms_i_3
       (.I0(time_out_counter_reg[10]),
        .I1(time_out_counter_reg[2]),
        .I2(time_out_counter_reg[3]),
        .I3(time_out_counter_reg[8]),
        .I4(time_out_counter_reg[9]),
        .O(time_out_2ms_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_2ms_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_2ms_i_1_n_0),
        .Q(time_out_2ms_reg_n_0),
        .R(reset_time_out_reg_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \time_out_counter[0]_i_1 
       (.I0(\time_out_counter[0]_i_3_n_0 ),
        .I1(\time_out_counter[0]_i_4_n_0 ),
        .I2(time_out_counter_reg[10]),
        .I3(time_out_counter_reg[2]),
        .I4(time_out_counter_reg[3]),
        .I5(\time_out_counter[0]_i_5_n_0 ),
        .O(time_out_counter));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF7FF)) 
    \time_out_counter[0]_i_3 
       (.I0(time_out_counter_reg[6]),
        .I1(time_out_counter_reg[7]),
        .I2(time_out_counter_reg[5]),
        .I3(time_out_counter_reg[4]),
        .I4(\time_out_counter[0]_i_7_n_0 ),
        .I5(\time_out_counter[0]_i_8_n_0 ),
        .O(\time_out_counter[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFDFFFFFFFFFFF)) 
    \time_out_counter[0]_i_4 
       (.I0(time_out_counter_reg[18]),
        .I1(time_out_counter_reg[17]),
        .I2(time_out_counter_reg[15]),
        .I3(time_out_counter_reg[16]),
        .I4(time_out_counter_reg[14]),
        .I5(time_out_counter_reg[11]),
        .O(\time_out_counter[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \time_out_counter[0]_i_5 
       (.I0(time_out_counter_reg[8]),
        .I1(time_out_counter_reg[9]),
        .O(\time_out_counter[0]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \time_out_counter[0]_i_6 
       (.I0(time_out_counter_reg[0]),
        .O(\time_out_counter[0]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \time_out_counter[0]_i_7 
       (.I0(time_out_counter_reg[0]),
        .I1(time_out_counter_reg[1]),
        .O(\time_out_counter[0]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \time_out_counter[0]_i_8 
       (.I0(time_out_counter_reg[12]),
        .I1(time_out_counter_reg[13]),
        .O(\time_out_counter[0]_i_8_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[0] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_7 ),
        .Q(time_out_counter_reg[0]),
        .R(reset_time_out_reg_n_0));
  CARRY4 \time_out_counter_reg[0]_i_2 
       (.CI(1'b0),
        .CO({\time_out_counter_reg[0]_i_2_n_0 ,\time_out_counter_reg[0]_i_2_n_1 ,\time_out_counter_reg[0]_i_2_n_2 ,\time_out_counter_reg[0]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\time_out_counter_reg[0]_i_2_n_4 ,\time_out_counter_reg[0]_i_2_n_5 ,\time_out_counter_reg[0]_i_2_n_6 ,\time_out_counter_reg[0]_i_2_n_7 }),
        .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[10] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_5 ),
        .Q(time_out_counter_reg[10]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[11] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_4 ),
        .Q(time_out_counter_reg[11]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[12] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_7 ),
        .Q(time_out_counter_reg[12]),
        .R(reset_time_out_reg_n_0));
  CARRY4 \time_out_counter_reg[12]_i_1 
       (.CI(\time_out_counter_reg[8]_i_1_n_0 ),
        .CO({\time_out_counter_reg[12]_i_1_n_0 ,\time_out_counter_reg[12]_i_1_n_1 ,\time_out_counter_reg[12]_i_1_n_2 ,\time_out_counter_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[12]_i_1_n_4 ,\time_out_counter_reg[12]_i_1_n_5 ,\time_out_counter_reg[12]_i_1_n_6 ,\time_out_counter_reg[12]_i_1_n_7 }),
        .S(time_out_counter_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[13] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_6 ),
        .Q(time_out_counter_reg[13]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[14] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_5 ),
        .Q(time_out_counter_reg[14]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[15] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_4 ),
        .Q(time_out_counter_reg[15]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[16] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[16]_i_1_n_7 ),
        .Q(time_out_counter_reg[16]),
        .R(reset_time_out_reg_n_0));
  CARRY4 \time_out_counter_reg[16]_i_1 
       (.CI(\time_out_counter_reg[12]_i_1_n_0 ),
        .CO({\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED [3:2],\time_out_counter_reg[16]_i_1_n_2 ,\time_out_counter_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED [3],\time_out_counter_reg[16]_i_1_n_5 ,\time_out_counter_reg[16]_i_1_n_6 ,\time_out_counter_reg[16]_i_1_n_7 }),
        .S({1'b0,time_out_counter_reg[18:16]}));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[17] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[16]_i_1_n_6 ),
        .Q(time_out_counter_reg[17]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[18] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[16]_i_1_n_5 ),
        .Q(time_out_counter_reg[18]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[1] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_6 ),
        .Q(time_out_counter_reg[1]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[2] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_5 ),
        .Q(time_out_counter_reg[2]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[3] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_4 ),
        .Q(time_out_counter_reg[3]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[4] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_7 ),
        .Q(time_out_counter_reg[4]),
        .R(reset_time_out_reg_n_0));
  CARRY4 \time_out_counter_reg[4]_i_1 
       (.CI(\time_out_counter_reg[0]_i_2_n_0 ),
        .CO({\time_out_counter_reg[4]_i_1_n_0 ,\time_out_counter_reg[4]_i_1_n_1 ,\time_out_counter_reg[4]_i_1_n_2 ,\time_out_counter_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[4]_i_1_n_4 ,\time_out_counter_reg[4]_i_1_n_5 ,\time_out_counter_reg[4]_i_1_n_6 ,\time_out_counter_reg[4]_i_1_n_7 }),
        .S(time_out_counter_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[5] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_6 ),
        .Q(time_out_counter_reg[5]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[6] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_5 ),
        .Q(time_out_counter_reg[6]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[7] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_4 ),
        .Q(time_out_counter_reg[7]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[8] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_7 ),
        .Q(time_out_counter_reg[8]),
        .R(reset_time_out_reg_n_0));
  CARRY4 \time_out_counter_reg[8]_i_1 
       (.CI(\time_out_counter_reg[4]_i_1_n_0 ),
        .CO({\time_out_counter_reg[8]_i_1_n_0 ,\time_out_counter_reg[8]_i_1_n_1 ,\time_out_counter_reg[8]_i_1_n_2 ,\time_out_counter_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[8]_i_1_n_4 ,\time_out_counter_reg[8]_i_1_n_5 ,\time_out_counter_reg[8]_i_1_n_6 ,\time_out_counter_reg[8]_i_1_n_7 }),
        .S(time_out_counter_reg[11:8]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[9] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_6 ),
        .Q(time_out_counter_reg[9]),
        .R(reset_time_out_reg_n_0));
  LUT4 #(
    .INIT(16'hAB00)) 
    time_out_wait_bypass_i_1
       (.I0(time_out_wait_bypass),
        .I1(rx_fsm_reset_done_int_s3),
        .I2(\wait_bypass_count[0]_i_4_n_0 ),
        .I3(run_phase_alignment_int_s3),
        .O(time_out_wait_bypass_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_wait_bypass_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(time_out_wait_bypass_i_1_n_0),
        .Q(time_out_wait_bypass),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    time_out_wait_bypass_s3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_wait_bypass_s2),
        .Q(time_out_wait_bypass_s3),
        .R(1'b0));
  CARRY4 time_tlock_max1_carry
       (.CI(1'b0),
        .CO({time_tlock_max1_carry_n_0,time_tlock_max1_carry_n_1,time_tlock_max1_carry_n_2,time_tlock_max1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,time_out_counter_reg[5],time_out_counter_reg[3],time_tlock_max1_carry_i_1_n_0}),
        .O(NLW_time_tlock_max1_carry_O_UNCONNECTED[3:0]),
        .S({time_tlock_max1_carry_i_2_n_0,time_tlock_max1_carry_i_3_n_0,time_tlock_max1_carry_i_4_n_0,time_tlock_max1_carry_i_5_n_0}));
  CARRY4 time_tlock_max1_carry__0
       (.CI(time_tlock_max1_carry_n_0),
        .CO({time_tlock_max1_carry__0_n_0,time_tlock_max1_carry__0_n_1,time_tlock_max1_carry__0_n_2,time_tlock_max1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({time_tlock_max1_carry__0_i_1_n_0,1'b0,time_tlock_max1_carry__0_i_2_n_0,time_tlock_max1_carry__0_i_3_n_0}),
        .O(NLW_time_tlock_max1_carry__0_O_UNCONNECTED[3:0]),
        .S({time_tlock_max1_carry__0_i_4_n_0,time_tlock_max1_carry__0_i_5_n_0,time_tlock_max1_carry__0_i_6_n_0,time_tlock_max1_carry__0_i_7_n_0}));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry__0_i_1
       (.I0(time_out_counter_reg[14]),
        .I1(time_out_counter_reg[15]),
        .O(time_tlock_max1_carry__0_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry__0_i_2
       (.I0(time_out_counter_reg[10]),
        .I1(time_out_counter_reg[11]),
        .O(time_tlock_max1_carry__0_i_2_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry__0_i_3
       (.I0(time_out_counter_reg[8]),
        .I1(time_out_counter_reg[9]),
        .O(time_tlock_max1_carry__0_i_3_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry__0_i_4
       (.I0(time_out_counter_reg[15]),
        .I1(time_out_counter_reg[14]),
        .O(time_tlock_max1_carry__0_i_4_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    time_tlock_max1_carry__0_i_5
       (.I0(time_out_counter_reg[13]),
        .I1(time_out_counter_reg[12]),
        .O(time_tlock_max1_carry__0_i_5_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry__0_i_6
       (.I0(time_out_counter_reg[11]),
        .I1(time_out_counter_reg[10]),
        .O(time_tlock_max1_carry__0_i_6_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry__0_i_7
       (.I0(time_out_counter_reg[9]),
        .I1(time_out_counter_reg[8]),
        .O(time_tlock_max1_carry__0_i_7_n_0));
  CARRY4 time_tlock_max1_carry__1
       (.CI(time_tlock_max1_carry__0_n_0),
        .CO({NLW_time_tlock_max1_carry__1_CO_UNCONNECTED[3:2],time_tlock_max1,time_tlock_max1_carry__1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,time_out_counter_reg[18],time_tlock_max1_carry__1_i_1_n_0}),
        .O(NLW_time_tlock_max1_carry__1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,time_tlock_max1_carry__1_i_2_n_0,time_tlock_max1_carry__1_i_3_n_0}));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry__1_i_1
       (.I0(time_out_counter_reg[16]),
        .I1(time_out_counter_reg[17]),
        .O(time_tlock_max1_carry__1_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    time_tlock_max1_carry__1_i_2
       (.I0(time_out_counter_reg[18]),
        .O(time_tlock_max1_carry__1_i_2_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry__1_i_3
       (.I0(time_out_counter_reg[17]),
        .I1(time_out_counter_reg[16]),
        .O(time_tlock_max1_carry__1_i_3_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry_i_1
       (.I0(time_out_counter_reg[0]),
        .I1(time_out_counter_reg[1]),
        .O(time_tlock_max1_carry_i_1_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    time_tlock_max1_carry_i_2
       (.I0(time_out_counter_reg[7]),
        .I1(time_out_counter_reg[6]),
        .O(time_tlock_max1_carry_i_2_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    time_tlock_max1_carry_i_3
       (.I0(time_out_counter_reg[4]),
        .I1(time_out_counter_reg[5]),
        .O(time_tlock_max1_carry_i_3_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    time_tlock_max1_carry_i_4
       (.I0(time_out_counter_reg[2]),
        .I1(time_out_counter_reg[3]),
        .O(time_tlock_max1_carry_i_4_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry_i_5
       (.I0(time_out_counter_reg[1]),
        .I1(time_out_counter_reg[0]),
        .O(time_tlock_max1_carry_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    time_tlock_max_i_1
       (.I0(check_tlock_max_reg_n_0),
        .I1(time_tlock_max1),
        .I2(time_tlock_max),
        .O(time_tlock_max_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_tlock_max_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_tlock_max_i_1_n_0),
        .Q(time_tlock_max),
        .R(reset_time_out_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_bypass_count[0]_i_1 
       (.I0(run_phase_alignment_int_s3),
        .O(clear));
  LUT2 #(
    .INIT(4'h2)) 
    \wait_bypass_count[0]_i_2 
       (.I0(\wait_bypass_count[0]_i_4_n_0 ),
        .I1(rx_fsm_reset_done_int_s3),
        .O(\wait_bypass_count[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFBFFFFFF)) 
    \wait_bypass_count[0]_i_4 
       (.I0(\wait_bypass_count[0]_i_6_n_0 ),
        .I1(wait_bypass_count_reg[1]),
        .I2(wait_bypass_count_reg[11]),
        .I3(wait_bypass_count_reg[0]),
        .I4(\wait_bypass_count[0]_i_7_n_0 ),
        .O(\wait_bypass_count[0]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_bypass_count[0]_i_5 
       (.I0(wait_bypass_count_reg[0]),
        .O(\wait_bypass_count[0]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'hDFFF)) 
    \wait_bypass_count[0]_i_6 
       (.I0(wait_bypass_count_reg[9]),
        .I1(wait_bypass_count_reg[4]),
        .I2(wait_bypass_count_reg[12]),
        .I3(wait_bypass_count_reg[2]),
        .O(\wait_bypass_count[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    \wait_bypass_count[0]_i_7 
       (.I0(wait_bypass_count_reg[5]),
        .I1(wait_bypass_count_reg[7]),
        .I2(wait_bypass_count_reg[3]),
        .I3(wait_bypass_count_reg[6]),
        .I4(wait_bypass_count_reg[10]),
        .I5(wait_bypass_count_reg[8]),
        .O(\wait_bypass_count[0]_i_7_n_0 ));
  FDRE \wait_bypass_count_reg[0] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_7 ),
        .Q(wait_bypass_count_reg[0]),
        .R(clear));
  CARRY4 \wait_bypass_count_reg[0]_i_3 
       (.CI(1'b0),
        .CO({\wait_bypass_count_reg[0]_i_3_n_0 ,\wait_bypass_count_reg[0]_i_3_n_1 ,\wait_bypass_count_reg[0]_i_3_n_2 ,\wait_bypass_count_reg[0]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\wait_bypass_count_reg[0]_i_3_n_4 ,\wait_bypass_count_reg[0]_i_3_n_5 ,\wait_bypass_count_reg[0]_i_3_n_6 ,\wait_bypass_count_reg[0]_i_3_n_7 }),
        .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5_n_0 }));
  FDRE \wait_bypass_count_reg[10] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_5 ),
        .Q(wait_bypass_count_reg[10]),
        .R(clear));
  FDRE \wait_bypass_count_reg[11] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_4 ),
        .Q(wait_bypass_count_reg[11]),
        .R(clear));
  FDRE \wait_bypass_count_reg[12] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[12]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[12]),
        .R(clear));
  CARRY4 \wait_bypass_count_reg[12]_i_1 
       (.CI(\wait_bypass_count_reg[8]_i_1_n_0 ),
        .CO(\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED [3:1],\wait_bypass_count_reg[12]_i_1_n_7 }),
        .S({1'b0,1'b0,1'b0,wait_bypass_count_reg[12]}));
  FDRE \wait_bypass_count_reg[1] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_6 ),
        .Q(wait_bypass_count_reg[1]),
        .R(clear));
  FDRE \wait_bypass_count_reg[2] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_5 ),
        .Q(wait_bypass_count_reg[2]),
        .R(clear));
  FDRE \wait_bypass_count_reg[3] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_4 ),
        .Q(wait_bypass_count_reg[3]),
        .R(clear));
  FDRE \wait_bypass_count_reg[4] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[4]),
        .R(clear));
  CARRY4 \wait_bypass_count_reg[4]_i_1 
       (.CI(\wait_bypass_count_reg[0]_i_3_n_0 ),
        .CO({\wait_bypass_count_reg[4]_i_1_n_0 ,\wait_bypass_count_reg[4]_i_1_n_1 ,\wait_bypass_count_reg[4]_i_1_n_2 ,\wait_bypass_count_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\wait_bypass_count_reg[4]_i_1_n_4 ,\wait_bypass_count_reg[4]_i_1_n_5 ,\wait_bypass_count_reg[4]_i_1_n_6 ,\wait_bypass_count_reg[4]_i_1_n_7 }),
        .S(wait_bypass_count_reg[7:4]));
  FDRE \wait_bypass_count_reg[5] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_6 ),
        .Q(wait_bypass_count_reg[5]),
        .R(clear));
  FDRE \wait_bypass_count_reg[6] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_5 ),
        .Q(wait_bypass_count_reg[6]),
        .R(clear));
  FDRE \wait_bypass_count_reg[7] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_4 ),
        .Q(wait_bypass_count_reg[7]),
        .R(clear));
  FDRE \wait_bypass_count_reg[8] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[8]),
        .R(clear));
  CARRY4 \wait_bypass_count_reg[8]_i_1 
       (.CI(\wait_bypass_count_reg[4]_i_1_n_0 ),
        .CO({\wait_bypass_count_reg[8]_i_1_n_0 ,\wait_bypass_count_reg[8]_i_1_n_1 ,\wait_bypass_count_reg[8]_i_1_n_2 ,\wait_bypass_count_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\wait_bypass_count_reg[8]_i_1_n_4 ,\wait_bypass_count_reg[8]_i_1_n_5 ,\wait_bypass_count_reg[8]_i_1_n_6 ,\wait_bypass_count_reg[8]_i_1_n_7 }),
        .S(wait_bypass_count_reg[11:8]));
  FDRE \wait_bypass_count_reg[9] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_6 ),
        .Q(wait_bypass_count_reg[9]),
        .R(clear));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wait_time_cnt[0]_i_1 
       (.I0(wait_time_cnt_reg[0]),
        .O(wait_time_cnt0[0]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_time_cnt[1]_i_1 
       (.I0(wait_time_cnt_reg[1]),
        .I1(wait_time_cnt_reg[0]),
        .O(wait_time_cnt0[1]));
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_time_cnt[2]_i_1 
       (.I0(wait_time_cnt_reg[2]),
        .I1(wait_time_cnt_reg[0]),
        .I2(wait_time_cnt_reg[1]),
        .O(wait_time_cnt0[2]));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_time_cnt[3]_i_1 
       (.I0(wait_time_cnt_reg[3]),
        .I1(wait_time_cnt_reg[1]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[2]),
        .O(wait_time_cnt0[3]));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \wait_time_cnt[4]_i_1 
       (.I0(wait_time_cnt_reg[4]),
        .I1(wait_time_cnt_reg[2]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[1]),
        .I4(wait_time_cnt_reg[3]),
        .O(wait_time_cnt0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \wait_time_cnt[5]_i_1 
       (.I0(wait_time_cnt_reg[5]),
        .I1(wait_time_cnt_reg[3]),
        .I2(wait_time_cnt_reg[1]),
        .I3(wait_time_cnt_reg[0]),
        .I4(wait_time_cnt_reg[2]),
        .I5(wait_time_cnt_reg[4]),
        .O(wait_time_cnt0[5]));
  LUT3 #(
    .INIT(8'h02)) 
    \wait_time_cnt[6]_i_1 
       (.I0(rx_state[0]),
        .I1(rx_state[1]),
        .I2(rx_state[3]),
        .O(\wait_time_cnt[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \wait_time_cnt[6]_i_2 
       (.I0(\wait_time_cnt[6]_i_4_n_0 ),
        .I1(wait_time_cnt_reg[6]),
        .O(sel));
  LUT2 #(
    .INIT(4'h9)) 
    \wait_time_cnt[6]_i_3 
       (.I0(wait_time_cnt_reg[6]),
        .I1(\wait_time_cnt[6]_i_4_n_0 ),
        .O(wait_time_cnt0[6]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wait_time_cnt[6]_i_4 
       (.I0(wait_time_cnt_reg[4]),
        .I1(wait_time_cnt_reg[2]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[1]),
        .I4(wait_time_cnt_reg[3]),
        .I5(wait_time_cnt_reg[5]),
        .O(\wait_time_cnt[6]_i_4_n_0 ));
  FDRE \wait_time_cnt_reg[0] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[0]),
        .Q(wait_time_cnt_reg[0]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[1] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[1]),
        .Q(wait_time_cnt_reg[1]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[2] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[2]),
        .Q(wait_time_cnt_reg[2]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[3] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[3]),
        .Q(wait_time_cnt_reg[3]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[4] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[4]),
        .Q(wait_time_cnt_reg[4]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[5] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[5]),
        .Q(wait_time_cnt_reg[5]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[6] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0[6]),
        .Q(wait_time_cnt_reg[6]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
