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Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------/ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use IEEE.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity aurora_rx_1q is port ( -- AXI RX Interface m_axi_rx_tdata : out std_logic_vector(63 downto 0); m_axi_rx_tvalid : out std_logic; m_axi_rx_tkeep : out std_logic_vector(7 downto 0); m_axi_rx_tlast : out std_logic; -- User Flow Control RX Inteface m_axi_ufc_rx_tdata : out std_logic_vector(63 downto 0); m_axi_ufc_rx_tkeep : out std_logic_vector(7 downto 0); m_axi_ufc_rx_tvalid : out std_logic; m_axi_ufc_rx_tlast : out std_logic; -- GT Serial I/O rxp : in std_logic_vector(0 to 3); rxn : in std_logic_vector(0 to 3); -- GT Reference Clock Interface gt_refclk1 : in std_logic; -- Error Detection Interface frame_err : out std_logic; rx_hard_err : out std_logic; soft_err : out std_logic; rx_lane_up : out std_logic_vector(0 to 3); rx_channel_up : out std_logic; -- System Interface user_clk : in std_logic; sync_clk : in std_logic; rx_system_reset : in std_logic; power_down : in std_logic; loopback : in std_logic_vector(2 downto 0); gt_reset : in std_logic; tx_lock : out std_logic; sys_reset_out : out std_logic; init_clk_in : in std_logic; rx_resetdone_out : out std_logic; link_reset_out : out std_logic; --DRP Ports drpclk_in : in std_logic; drpaddr_in : in std_logic_vector(8 downto 0); drpdi_in : in std_logic_vector(15 downto 0); drpdo_out : out std_logic_vector(15 downto 0); drpen_in : in std_logic; drprdy_out : out std_logic; drpwe_in : in std_logic; drpaddr_in_lane1 : in std_logic_vector(8 downto 0); drpdi_in_lane1 : in std_logic_vector(15 downto 0); drpdo_out_lane1 : out std_logic_vector(15 downto 0); drpen_in_lane1 : in std_logic; drprdy_out_lane1 : out std_logic; drpwe_in_lane1 : in std_logic; drpaddr_in_lane2 : in std_logic_vector(8 downto 0); drpdi_in_lane2 : in std_logic_vector(15 downto 0); drpdo_out_lane2 : out std_logic_vector(15 downto 0); drpen_in_lane2 : in std_logic; drprdy_out_lane2 : out std_logic; drpwe_in_lane2 : in std_logic; drpaddr_in_lane3 : in std_logic_vector(8 downto 0); drpdi_in_lane3 : in std_logic_vector(15 downto 0); drpdo_out_lane3 : out std_logic_vector(15 downto 0); drpen_in_lane3 : in std_logic; drprdy_out_lane3 : out std_logic; drpwe_in_lane3 : in std_logic; --____________________________COMMON PORTS ,_______________________________{ ------------------------- Common Block - QPLL Ports ------------------------ gt0_qplllock_in : in std_logic; gt0_qpllrefclklost_in : in std_logic; gt0_qpllreset_out : out std_logic; gt_qpllclk_quad4_in : in std_logic; gt_qpllrefclk_quad4_in : in std_logic; --____________________________COMMON PORTS _______________________________} tx_out_clk : out std_logic; pll_not_locked : in std_logic ); end aurora_rx_1q; architecture STRUCTURE of aurora_rx_1q is attribute core_generation_info : string; attribute core_generation_info of STRUCTURE : architecture is "aurora_rx_1q,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=right,c_gt_clock_1=GTHQ3,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=1,c_gt_loc_14=2,c_gt_loc_15=3,c_gt_loc_16=4,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=64130,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160325,c_simplex=true,c_simplex_mode=RX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=RX-only_Simplex}"; component aurora_rx_1q_core port ( -- RX Stream Interface M_AXI_RX_TDATA : out std_logic_vector(63 downto 0); M_AXI_RX_TKEEP : out std_logic_vector(7 downto 0); M_AXI_RX_TVALID : out std_logic; M_AXI_RX_TLAST : out std_logic; -- User Flow Control RX Inteface M_AXI_UFC_RX_TDATA : out std_logic_vector(63 downto 0); M_AXI_UFC_RX_TKEEP : out std_logic_vector(7 downto 0); M_AXI_UFC_RX_TVALID : out std_logic; M_AXI_UFC_RX_TLAST : out std_logic; -- GTX Serial I/O RXP : in std_logic_vector(0 to 3); RXN : in std_logic_vector(0 to 3); -- GT Reference Clock Interface gt_refclk1 : in std_logic; -- Error Detection Interface RX_HARD_ERR : out std_logic; SOFT_ERR : out std_logic; -- Status RX_CHANNEL_UP : out std_logic; RX_LANE_UP : out std_logic_vector(0 to 3); FRAME_ERR : out std_logic; -- System Interface USER_CLK : in std_logic; SYNC_CLK : in std_logic; GT_RESET : in std_logic; RX_SYSTEM_RESET : in std_logic; sys_reset_out : out std_logic; POWER_DOWN : in std_logic; LOOPBACK : in std_logic_vector(2 downto 0); TX_OUT_CLK : out std_logic; INIT_CLK_IN : in std_logic; PLL_NOT_LOCKED : in std_logic; RX_RESETDONE_OUT : out std_logic; LINK_RESET_OUT : out std_logic; drpclk_in : in std_logic; DRPADDR_IN : in std_logic_vector(8 downto 0); DRPDI_IN : in std_logic_vector(15 downto 0); DRPDO_OUT : out std_logic_vector(15 downto 0); DRPEN_IN : in std_logic; DRPRDY_OUT : out std_logic; DRPWE_IN : in std_logic; DRPADDR_IN_LANE1 : in std_logic_vector(8 downto 0); DRPDI_IN_LANE1 : in std_logic_vector(15 downto 0); DRPDO_OUT_LANE1 : out std_logic_vector(15 downto 0); DRPEN_IN_LANE1 : in std_logic; DRPRDY_OUT_LANE1 : out std_logic; DRPWE_IN_LANE1 : in std_logic; DRPADDR_IN_LANE2 : in std_logic_vector(8 downto 0); DRPDI_IN_LANE2 : in std_logic_vector(15 downto 0); DRPDO_OUT_LANE2 : out std_logic_vector(15 downto 0); DRPEN_IN_LANE2 : in std_logic; DRPRDY_OUT_LANE2 : out std_logic; DRPWE_IN_LANE2 : in std_logic; DRPADDR_IN_LANE3 : in std_logic_vector(8 downto 0); DRPDI_IN_LANE3 : in std_logic_vector(15 downto 0); DRPDO_OUT_LANE3 : out std_logic_vector(15 downto 0); DRPEN_IN_LANE3 : in std_logic; DRPRDY_OUT_LANE3 : out std_logic; DRPWE_IN_LANE3 : in std_logic; --____________________________COMMON PORTS ,_______________________________{ ------------------------- Common Block - QPLL Ports ------------------------ gt0_qplllock_in : in std_logic; gt0_qpllrefclklost_in : in std_logic; gt0_qpllreset_out : out std_logic; gt_qpllclk_quad4_in : in std_logic; gt_qpllrefclk_quad4_in : in std_logic; --____________________________COMMON PORTS _______________________________} TX_LOCK : out std_logic ); end component; begin --*********************************Main Body of Code********************************** U0 : aurora_rx_1q_core port map ( -- AXI TX Interface -- AXI RX Interface m_axi_rx_tdata => m_axi_rx_tdata, m_axi_rx_tkeep => m_axi_rx_tkeep, m_axi_rx_tvalid => m_axi_rx_tvalid, m_axi_rx_tlast => m_axi_rx_tlast, -- User Flow Control RX Inteface m_axi_ufc_rx_tdata => m_axi_ufc_rx_tdata, m_axi_ufc_rx_tkeep => m_axi_ufc_rx_tkeep, m_axi_ufc_rx_tvalid => m_axi_ufc_rx_tvalid, m_axi_ufc_rx_tlast => m_axi_ufc_rx_tlast, -- GT Serial I/O rxp => rxp, rxn => rxn, -- GT Reference Clock Interface gt_refclk1 => gt_refclk1, -- Error Detection Interface frame_err => frame_err, -- Error Detection Interface rx_hard_err => rx_hard_err, soft_err => soft_err, -- Status rx_channel_up => rx_channel_up, rx_lane_up => rx_lane_up, -- System Interface user_clk => user_clk, sync_clk => sync_clk, rx_system_reset => rx_system_reset, sys_reset_out => sys_reset_out, power_down => power_down, loopback => loopback, gt_reset => gt_reset, tx_lock => tx_lock, init_clk_in => init_clk_in, pll_not_locked => pll_not_locked, rx_resetdone_out => rx_resetdone_out, link_reset_out => link_reset_out, drpclk_in => drpclk_in, drpaddr_in => drpaddr_in, drpen_in => drpen_in, drpdi_in => drpdi_in, drprdy_out => drprdy_out, drpdo_out => drpdo_out, drpwe_in => drpwe_in, drpaddr_in_lane1 => drpaddr_in_lane1, drpen_in_lane1 => drpen_in_lane1, drpdi_in_lane1 => drpdi_in_lane1, drprdy_out_lane1 => drprdy_out_lane1, drpdo_out_lane1 => drpdo_out_lane1, drpwe_in_lane1 => drpwe_in_lane1, drpaddr_in_lane2 => drpaddr_in_lane2, drpen_in_lane2 => drpen_in_lane2, drpdi_in_lane2 => drpdi_in_lane2, drprdy_out_lane2 => drprdy_out_lane2, drpdo_out_lane2 => drpdo_out_lane2, drpwe_in_lane2 => drpwe_in_lane2, drpaddr_in_lane3 => drpaddr_in_lane3, drpen_in_lane3 => drpen_in_lane3, drpdi_in_lane3 => drpdi_in_lane3, drprdy_out_lane3 => drprdy_out_lane3, drpdo_out_lane3 => drpdo_out_lane3, drpwe_in_lane3 => drpwe_in_lane3, --------------------{ --____________________________COMMON PORTS INST_______________________________{ ------------------------- Common Block - QPLL Ports ------------------------ gt0_qplllock_in => gt0_qplllock_in, gt0_qpllrefclklost_in => gt0_qpllrefclklost_in, gt0_qpllreset_out => gt0_qpllreset_out, gt_qpllclk_quad4_in => gt_qpllclk_quad4_in , gt_qpllrefclk_quad4_in => gt_qpllrefclk_quad4_in , --____________________________COMMON PORTS INST_______________________________} --------------------} tx_out_clk => tx_out_clk ); end STRUCTURE;