xilinx.com customized_ip aurora_rx_1q 1.0 USER_DATA_S_AXI_TX USER_DATA_S_AXI_TX User data AXI-Stream TX interface TDATA s_axi_tx_tdata TKEEP s_axi_tx_tkeep TLAST s_axi_tx_tlast TREADY s_axi_tx_tready TVALID s_axi_tx_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false USER_DATA_M_AXI_RX USER_DATA_M_AXI_RX User data AXI-Stream RX interface TDATA m_axi_rx_tdata TKEEP m_axi_rx_tkeep TLAST m_axi_rx_tlast TVALID m_axi_rx_tvalid TDATA_NUM_BYTES 8 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl true UFC_S_AXI_TX UFC_S_AXI_TX UFC AXI-Stream TX interface TDATA s_axi_ufc_tx_tdata TREADY s_axi_ufc_tx_tready TVALID s_axi_ufc_tx_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false UFC_M_AXI_RX UFC_M_AXI_RX UFC AXI-Stream RX interface TDATA m_axi_ufc_rx_tdata TKEEP m_axi_ufc_rx_tkeep TLAST m_axi_ufc_rx_tlast TVALID m_axi_ufc_rx_tvalid TDATA_NUM_BYTES 8 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl true NFC_S_AXI_TX NFC_S_AXI_TX NFC AXI-Stream TX interface TDATA s_axi_nfc_tx_tdata TREADY s_axi_nfc_tx_tready TVALID s_axi_nfc_tx_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false NFC_M_AXI_RX NFC_M_AXI_RX NFC AXI-Stream RX interface TDATA m_axi_nfc_rx_tdata TVALID m_axi_nfc_rx_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false user_clk_out user_clk_out user_clk frequency depends on line rate and this clock is available when shared logic is in IP CLK user_clk_out ASSOCIATED_BUSIF USER_DATA_S_AXI_TX:USER_DATA_M_AXI_RX:UFC_S_AXI_TX:UFC_M_AXI_RX:NFC_S_AXI_TX:NFC_M_AXI_RX ASSOCIATED_RESET sys_reset_out FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none INSERT_VIP 0 simulation.rtl false sync_clk_out sync_clk_out sync_clk frequency depends on line rate and this clock is available when shared logic is in IP CLK sync_clk_out FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false gt0_qpllreset_out gt0_qpllreset_out GT0 qpll reset status RST gt0_qpllreset_out POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl true reset reset Active high reset required to be asserted for 6 clock cycles of USER_CLK RST reset POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl false tx_out_clk tx_out_clk tx_out_clk frequency depends on line rate CLK tx_out_clk FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true user_clk user_clk user_clk frequency depends on line rate CLK user_clk ASSOCIATED_BUSIF USER_DATA_S_AXI_TX:USER_DATA_M_AXI_RX:UFC_S_AXI_TX:UFC_M_AXI_RX:NFC_S_AXI_TX:NFC_M_AXI_RX ASSOCIATED_RESET sys_reset_out FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none INSERT_VIP 0 simulation.rtl true sync_clk sync_clk sync_clk frequency depends on line rate and user_clk should be shorted with sync_clk CLK sync_clk FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true init_clk_out init_clk_out 200 MHz independent system clock CLK init_clk_out FREQ_HZ 200000000 ASSOCIATED_BUSIF gt_reset_out PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false sys_reset_out sys_reset_out system reset available when shared logic is in IP RST sys_reset_out POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl gt_reset gt_reset GT reset sampled in INIT_CLK and asserted for 6 clock cycles and after assertion of reset RST gt_reset POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl gt_reset_out gt_reset_out GT reset generated when shared logic is in IP RST gt_reset_out POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl false link_reset_out link_reset_out Link reset is generated when IP is not receiving valid data for longer time RST link_reset_out POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl true init_clk_in init_clk_in Free running System clock CLK init_clk_in ASSOCIATED_BUSIF gt_reset FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true gt_refclk1_out gt_refclk1_out GT REFCLK1 when shared logic is in IP CLK gt_refclk1_out FREQ_HZ 200000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false gt_refclk2_out gt_refclk2_out GT REFCLK2 when shared logic is in IP CLK gt_refclk2_out FREQ_HZ 200000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false gt_refclk1 ~ GT REFCLK1 when shared logic is in example design CLK gt_refclk1 FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true gt_refclk2 ~ GT REFCLK2 when shared logic is in example design CLK gt_refclk2 FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false GT_DIFF_REFCLK1 GT_DIFF_REFCLK1 Differential GT REFCLK1 and depends on line rate true CLK_N gt_refclk1_n CLK_P gt_refclk1_p CAN_DEBUG false none FREQ_HZ 100000000 none false GT_DIFF_REFCLK2 GT_DIFF_REFCLK2 Differential GT REFCLK2 and depends on line rate true CLK_N gt_refclk2_n CLK_P gt_refclk2_p CAN_DEBUG false none FREQ_HZ 100000000 none false INIT_DIFF_CLK INIT_DIFF_CLK 200 MHz independent system clock true CLK_N init_clk_n CLK_P init_clk_p ASSOCIATED_RESET gt_reset CAN_DEBUG false none FREQ_HZ 100000000 none false rx_system_reset rx_system_reset Aurora IP reset for Simplex-RX config RST rx_system_reset POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl true tx_system_reset tx_system_reset Aurora IP reset for Simplex-TX config RST tx_system_reset POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl false gt_drp_clk_in gt_drp_clk_in DRP clock for 7-series transceiver CLK drpclk_in ASSOCIATED_BUSIF GT0_DRP_IF:GT1_DRP_IF:GT2_DRP_IF:GT3_DRP_IF:GT4_DRP_IF:GT5_DRP_IF:GT6_DRP_IF:GT7_DRP_IF:GT8_DRP_IF:GT9_DRP_IF:GT10_DRP_IF:GT11_DRP_IF:GT12_DRP_IF:GT13_DRP_IF:GT14_DRP_IF:GT15_DRP_IF FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl drpclk init_clk_in DRP clock for Ultrascale transceiver CLK init_clk_in ASSOCIATED_BUSIF GT0_DRP:GT1_DRP:GT2_DRP:GT3_DRP:GT4_DRP:GT5_DRP:GT6_DRP:GT7_DRP:GT8_DRP:GT9_DRP:GT10_DRP:GT11_DRP:GT12_DRP:GT13_DRP:GT14_DRP:GT15_DRP FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl GT0_DRP GT0_DRP DRP IF for Ultrascale GT0 DADDR gt0_drpaddr DEN gt0_drpen DI gt0_drpdi DO gt0_drpdo DRDY gt0_drprdy DWE gt0_drpwe false GT1_DRP GT1_DRP DRP IF for Ultrascale GT1 DADDR gt1_drpaddr DEN gt1_drpen DI gt1_drpdi DO gt1_drpdo DRDY gt1_drprdy DWE gt1_drpwe false GT2_DRP GT2_DRP DRP IF for Ultrascale GT2 DADDR gt2_drpaddr DEN gt2_drpen DI gt2_drpdi DO gt2_drpdo DRDY gt2_drprdy DWE gt2_drpwe false GT3_DRP GT3_DRP DRP IF for Ultrascale GT3 DADDR gt3_drpaddr DEN gt3_drpen DI gt3_drpdi DO gt3_drpdo DRDY gt3_drprdy DWE gt3_drpwe false GT4_DRP GT4_DRP DRP IF for Ultrascale GT4 DADDR gt4_drpaddr DEN gt4_drpen DI gt4_drpdi DO gt4_drpdo DRDY gt4_drprdy DWE gt4_drpwe false GT5_DRP GT5_DRP DRP IF for Ultrascale GT5 DADDR gt5_drpaddr DEN gt5_drpen DI gt5_drpdi DO gt5_drpdo DRDY gt5_drprdy DWE gt5_drpwe false GT6_DRP GT6_DRP DRP IF for Ultrascale GT6 DADDR gt6_drpaddr DEN gt6_drpen DI gt6_drpdi DO gt6_drpdo DRDY gt6_drprdy DWE gt6_drpwe false GT7_DRP GT7_DRP DRP IF for Ultrascale GT7 DADDR gt7_drpaddr DEN gt7_drpen DI gt7_drpdi DO gt7_drpdo DRDY gt7_drprdy DWE gt7_drpwe false GT8_DRP GT8_DRP DRP IF for Ultrascale GT8 DADDR gt8_drpaddr DEN gt8_drpen DI gt8_drpdi DO gt8_drpdo DRDY gt8_drprdy DWE gt8_drpwe false GT9_DRP GT9_DRP DRP IF for Ultrascale GT9 DADDR gt9_drpaddr DEN gt9_drpen DI gt9_drpdi DO gt9_drpdo DRDY gt9_drprdy DWE gt9_drpwe false GT10_DRP GT10_DRP DRP IF for Ultrascale GT10 DADDR gt10_drpaddr DEN gt10_drpen DI gt10_drpdi DO gt10_drpdo DRDY gt10_drprdy DWE gt10_drpwe false GT11_DRP GT11_DRP DRP IF for Ultrascale GT11 DADDR gt11_drpaddr DEN gt11_drpen DI gt11_drpdi DO gt11_drpdo DRDY gt11_drprdy DWE gt11_drpwe false GT12_DRP GT12_DRP DRP IF for Ultrascale GT12 DADDR gt12_drpaddr DEN gt12_drpen DI gt12_drpdi DO gt12_drpdo DRDY gt12_drprdy DWE gt12_drpwe false GT13_DRP GT13_DRP DRP IF for Ultrascale GT13 DADDR gt13_drpaddr DEN gt13_drpen DI gt13_drpdi DO gt13_drpdo DRDY gt13_drprdy DWE gt13_drpwe false GT14_DRP GT14_DRP DRP IF for Ultrascale GT14 DADDR gt14_drpaddr DEN gt14_drpen DI gt14_drpdi DO gt14_drpdo DRDY gt14_drprdy DWE gt14_drpwe false GT15_DRP GT15_DRP DRP IF for Ultrascale GT15 DADDR gt15_drpaddr DEN gt15_drpen DI gt15_drpdi DO gt15_drpdo DRDY gt15_drprdy DWE gt15_drpwe false GT0_DRP_IF GT0_DRP_IF DRP IF for GT0 DADDR drpaddr_in DEN drpen_in DI drpdi_in DO drpdo_out DRDY drprdy_out DWE drpwe_in true GT1_DRP_IF GT1_DRP_IF DRP IF for GT1 DADDR drpaddr_in_lane1 DEN drpen_in_lane1 DI drpdi_in_lane1 DO drpdo_out_lane1 DRDY drprdy_out_lane1 DWE drpwe_in_lane1 true GT2_DRP_IF GT2_DRP_IF DRP IF for GT2 DADDR drpaddr_in_lane2 DEN drpen_in_lane2 DI drpdi_in_lane2 DO drpdo_out_lane2 DRDY drprdy_out_lane2 DWE drpwe_in_lane2 true GT3_DRP_IF GT3_DRP_IF DRP IF for GT3 DADDR drpaddr_in_lane3 DEN drpen_in_lane3 DI drpdi_in_lane3 DO drpdo_out_lane3 DRDY drprdy_out_lane3 DWE drpwe_in_lane3 true GT4_DRP_IF GT4_DRP_IF DRP IF for GT4 DADDR drpaddr_in_lane4 DEN drpen_in_lane4 DI drpdi_in_lane4 DO drpdo_out_lane4 DRDY drprdy_out_lane4 DWE drpwe_in_lane4 false GT5_DRP_IF GT5_DRP_IF DRP IF for GT5 DADDR drpaddr_in_lane5 DEN drpen_in_lane5 DI drpdi_in_lane5 DO drpdo_out_lane5 DRDY drprdy_out_lane5 DWE drpwe_in_lane5 false GT6_DRP_IF GT6_DRP_IF DRP IF for GT6 DADDR drpaddr_in_lane6 DEN drpen_in_lane6 DI drpdi_in_lane6 DO drpdo_out_lane6 DRDY drprdy_out_lane6 DWE drpwe_in_lane6 false GT7_DRP_IF GT7_DRP_IF DRP IF for GT7 DADDR drpaddr_in_lane7 DEN drpen_in_lane7 DI drpdi_in_lane7 DO drpdo_out_lane7 DRDY drprdy_out_lane7 DWE drpwe_in_lane7 false GT8_DRP_IF GT8_DRP_IF DRP IF for GT8 DADDR drpaddr_in_lane8 DEN drpen_in_lane8 DI drpdi_in_lane8 DO drpdo_out_lane8 DRDY drprdy_out_lane8 DWE drpwe_in_lane8 false GT9_DRP_IF GT9_DRP_IF DRP IF for GT9 DADDR drpaddr_in_lane9 DEN drpen_in_lane9 DI drpdi_in_lane9 DO drpdo_out_lane9 DRDY drprdy_out_lane9 DWE drpwe_in_lane9 false GT10_DRP_IF GT10_DRP_IF DRP IF for GT10 DADDR drpaddr_in_lane10 DEN drpen_in_lane10 DI drpdi_in_lane10 DO drpdo_out_lane10 DRDY drprdy_out_lane10 DWE drpwe_in_lane10 false GT11_DRP_IF GT11_DRP_IF DRP IF for GT11 DADDR drpaddr_in_lane11 DEN drpen_in_lane11 DI drpdi_in_lane11 DO drpdo_out_lane11 DRDY drprdy_out_lane11 DWE drpwe_in_lane11 false GT12_DRP_IF GT12_DRP_IF DRP IF for GT12 DADDR drpaddr_in_lane12 DEN drpen_in_lane12 DI drpdi_in_lane12 DO drpdo_out_lane12 DRDY drprdy_out_lane12 DWE drpwe_in_lane12 false GT13_DRP_IF GT13_DRP_IF DRP IF for GT13 DADDR drpaddr_in_lane13 DEN drpen_in_lane13 DI drpdi_in_lane13 DO drpdo_out_lane13 DRDY drprdy_out_lane13 DWE drpwe_in_lane13 false GT14_DRP_IF GT14_DRP_IF DRP IF for GT14 DADDR drpaddr_in_lane14 DEN drpen_in_lane14 DI drpdi_in_lane14 DO drpdo_out_lane14 DRDY drprdy_out_lane14 DWE drpwe_in_lane14 false GT15_DRP_IF GT15_DRP_IF DRP IF for GT15 DADDR drpaddr_in_lane15 DEN drpen_in_lane15 DI drpdi_in_lane15 DO drpdo_out_lane15 DRDY drprdy_out_lane15 DWE drpwe_in_lane15 false TRANSCEIVER_DEBUG TRANSCEIVER_DEBUG Transceiver debug interface for Ultrascale cplllock gt_cplllock dmonitorout gt_dmonitorout eyescandataerror gt_eyescandataerror eyescanreset gt_eyescanreset eyescantrigger gt_eyescantrigger pcsrsvdin gt_pcsrsvdin rxbufreset gt_rxbufreset rxbufstatus gt_rxbufstatus rxcdrhold gt_rxcdrhold rxcdrovrden gt_rxcdrovrden rxcommadet gt_rxcommadet rxdfelpmreset gt_rxdfelpmreset rxdisperr gt_rxdisperr rxlpmen gt_rxlpmen rxnotintable gt_rxnotintable rxpcsreset gt_rxpcsreset rxpmareset gt_rxpmareset rxpmaresetdone gt_rxpmaresetdone rxprbscntreset gt_rxprbscntreset rxprbserr gt_rxprbserr rxprbssel gt_rxprbssel rxrate gt_rxrate rxresetdone gt_rxresetdone txbufstatus gt_txbufstatus txdiffctrl gt_txdiffctrl txinhibit gt_txinhibit txpcsreset gt_txpcsreset txpmareset gt_txpmareset txpolarity gt_txpolarity txpostcursor gt_txpostcursor txprbsforceerr gt_txprbsforceerr txprbssel gt_txprbssel txprecursor gt_txprecursor txresetdone gt_txresetdone false TRANSCEIVER_DEBUG0 TRANSCEIVER_DEBUG0 Transceiver debug interface for GT0 cplllock gt0_cplllock_out dmonitorout gt0_dmonitorout_out eyescandataerror gt0_eyescandataerror_out eyescanreset gt0_eyescanreset_in eyescantrigger gt0_eyescantrigger_in rxbuferr gt0_rx_buf_err_out rxbufreset gt0_rxbufreset_in rxbufstatus gt0_rxbufstatus_out rxbyteisaligned gt0_rxbyteisaligned_out rxcdrhold gt0_rxcdrhold_in rxcdrovrden gt0_rxcdrovrden_in rxcommadet gt0_rxcommadet_out rxdfelpmreset gt0_rxdfelpmreset_in rxdisperr gt0_rx_disp_err_out rxlpmen gt0_rxlpmen_in rxlpmhfhold gt0_rxlpmhfhold_in rxlpmhfovrden gt0_rxlpmhfovrden_in rxlpmlfhold gt0_rxlpmlfhold_in rxlpmreset gt0_rxlpmreset_in rxmonitorout gt0_rxmonitorout_out rxmonitorsel gt0_rxmonitorsel_in rxnotintable gt0_rx_not_in_table_out rxpcsreset gt0_rxpcsreset_in rxpmareset gt0_rxpmareset_in rxpmaresetdone gt0_rxpmaresetdone_out rxprbscntreset gt0_rxprbscntreset_in rxprbserr gt0_rxprbserr_out rxprbssel gt0_rxprbssel_in rxrealign gt0_rx_realign_out rxresetdone gt0_rxresetdone_out txbuferr gt0_tx_buf_err_out txbufstatus gt0_txbufstatus_out txchardispmode gt0_txchardispmode_in txchardispval gt0_txchardispval_in txdiffctrl gt0_txdiffctrl_in txinhibit gt0_txinhibit_in txmaincursor gt0_txmaincursor_in txpcsreset gt0_txpcsreset_in txpmareset gt0_txpmareset_in txpolarity gt0_txpolarity_in txpostcursor gt0_txpostcursor_in txprbsforceerr gt0_txprbsforceerr_in txprbssel gt0_txprbssel_in txprecursor gt0_txprecursor_in txresetdone gt0_txresetdone_out false TRANSCEIVER_DEBUG1 TRANSCEIVER_DEBUG1 Transceiver debug interface for GT1 cplllock gt1_cplllock_out dmonitorout gt1_dmonitorout_out eyescandataerror gt1_eyescandataerror_out eyescanreset gt1_eyescanreset_in eyescantrigger gt1_eyescantrigger_in rxbuferr gt1_rx_buf_err_out rxbufreset gt1_rxbufreset_in rxbufstatus gt1_rxbufstatus_out rxbyteisaligned gt1_rxbyteisaligned_out rxcdrhold gt1_rxcdrhold_in rxcdrovrden gt1_rxcdrovrden_in rxcommadet gt1_rxcommadet_out rxdfelpmreset gt1_rxdfelpmreset_in rxdisperr gt1_rx_disp_err_out rxlpmen gt1_rxlpmen_in rxlpmhfhold gt1_rxlpmhfhold_in rxlpmhfovrden gt1_rxlpmhfovrden_in rxlpmlfhold gt1_rxlpmlfhold_in rxlpmreset gt1_rxlpmreset_in rxmonitorout gt1_rxmonitorout_out rxmonitorsel gt1_rxmonitorsel_in rxnotintable gt1_rx_not_in_table_out rxpcsreset gt1_rxpcsreset_in rxpmareset gt1_rxpmareset_in rxpmaresetdone gt1_rxpmaresetdone_out rxprbscntreset gt1_rxprbscntreset_in rxprbserr gt1_rxprbserr_out rxprbssel gt1_rxprbssel_in rxrealign gt1_rx_realign_out rxresetdone gt1_rxresetdone_out txbuferr gt1_tx_buf_err_out txbufstatus gt1_txbufstatus_out txchardispmode gt1_txchardispmode_in txchardispval gt1_txchardispval_in txdiffctrl gt1_txdiffctrl_in txinhibit gt1_txinhibit_in txmaincursor gt1_txmaincursor_in txpcsreset gt1_txpcsreset_in txpmareset gt1_txpmareset_in txpolarity gt1_txpolarity_in txpostcursor gt1_txpostcursor_in txprbsforceerr gt1_txprbsforceerr_in txprbssel gt1_txprbssel_in txprecursor gt1_txprecursor_in txresetdone gt1_txresetdone_out false TRANSCEIVER_DEBUG2 TRANSCEIVER_DEBUG2 Transceiver debug interface for gt2 cplllock gt2_cplllock_out dmonitorout gt2_dmonitorout_out eyescandataerror gt2_eyescandataerror_out eyescanreset gt2_eyescanreset_in eyescantrigger gt2_eyescantrigger_in rxbuferr gt2_rx_buf_err_out rxbufreset gt2_rxbufreset_in rxbufstatus gt2_rxbufstatus_out rxbyteisaligned gt2_rxbyteisaligned_out rxcdrhold gt2_rxcdrhold_in rxcdrovrden gt2_rxcdrovrden_in rxcommadet gt2_rxcommadet_out rxdfelpmreset gt2_rxdfelpmreset_in rxdisperr gt2_rx_disp_err_out rxlpmen gt2_rxlpmen_in rxlpmhfhold gt2_rxlpmhfhold_in rxlpmhfovrden gt2_rxlpmhfovrden_in rxlpmlfhold gt2_rxlpmlfhold_in rxlpmreset gt2_rxlpmreset_in rxmonitorout gt2_rxmonitorout_out rxmonitorsel gt2_rxmonitorsel_in rxnotintable gt2_rx_not_in_table_out rxpcsreset gt2_rxpcsreset_in rxpmareset gt2_rxpmareset_in rxpmaresetdone gt2_rxpmaresetdone_out rxprbscntreset gt2_rxprbscntreset_in rxprbserr gt2_rxprbserr_out rxprbssel gt2_rxprbssel_in rxrealign gt2_rx_realign_out rxresetdone gt2_rxresetdone_out txbuferr gt2_tx_buf_err_out txbufstatus gt2_txbufstatus_out txchardispmode gt2_txchardispmode_in txchardispval gt2_txchardispval_in txdiffctrl gt2_txdiffctrl_in txinhibit gt2_txinhibit_in txmaincursor gt2_txmaincursor_in txpcsreset gt2_txpcsreset_in txpmareset gt2_txpmareset_in txpolarity gt2_txpolarity_in txpostcursor gt2_txpostcursor_in txprbsforceerr gt2_txprbsforceerr_in txprbssel gt2_txprbssel_in txprecursor gt2_txprecursor_in txresetdone gt2_txresetdone_out false TRANSCEIVER_DEBUG3 TRANSCEIVER_DEBUG3 Transceiver debug interface for gt3 cplllock gt3_cplllock_out dmonitorout gt3_dmonitorout_out eyescandataerror gt3_eyescandataerror_out eyescanreset gt3_eyescanreset_in eyescantrigger gt3_eyescantrigger_in rxbuferr gt3_rx_buf_err_out rxbufreset gt3_rxbufreset_in rxbufstatus gt3_rxbufstatus_out rxbyteisaligned gt3_rxbyteisaligned_out rxcdrhold gt3_rxcdrhold_in rxcdrovrden gt3_rxcdrovrden_in rxcommadet gt3_rxcommadet_out rxdfelpmreset gt3_rxdfelpmreset_in rxdisperr gt3_rx_disp_err_out rxlpmen gt3_rxlpmen_in rxlpmhfhold gt3_rxlpmhfhold_in rxlpmhfovrden gt3_rxlpmhfovrden_in rxlpmlfhold gt3_rxlpmlfhold_in rxlpmreset gt3_rxlpmreset_in rxmonitorout gt3_rxmonitorout_out rxmonitorsel gt3_rxmonitorsel_in rxnotintable gt3_rx_not_in_table_out rxpcsreset gt3_rxpcsreset_in rxpmareset gt3_rxpmareset_in rxpmaresetdone gt3_rxpmaresetdone_out rxprbscntreset gt3_rxprbscntreset_in rxprbserr gt3_rxprbserr_out rxprbssel gt3_rxprbssel_in rxrealign gt3_rx_realign_out rxresetdone gt3_rxresetdone_out txbuferr gt3_tx_buf_err_out txbufstatus gt3_txbufstatus_out txchardispmode gt3_txchardispmode_in txchardispval gt3_txchardispval_in txdiffctrl gt3_txdiffctrl_in txinhibit gt3_txinhibit_in txmaincursor gt3_txmaincursor_in txpcsreset gt3_txpcsreset_in txpmareset gt3_txpmareset_in txpolarity gt3_txpolarity_in txpostcursor gt3_txpostcursor_in txprbsforceerr gt3_txprbsforceerr_in txprbssel gt3_txprbssel_in txprecursor gt3_txprecursor_in txresetdone gt3_txresetdone_out false TRANSCEIVER_DEBUG4 TRANSCEIVER_DEBUG4 Transceiver debug interface for gt4 cplllock gt4_cplllock_out dmonitorout gt4_dmonitorout_out eyescandataerror gt4_eyescandataerror_out eyescanreset gt4_eyescanreset_in eyescantrigger gt4_eyescantrigger_in rxbuferr gt4_rx_buf_err_out rxbufreset gt4_rxbufreset_in rxbufstatus gt4_rxbufstatus_out rxbyteisaligned gt4_rxbyteisaligned_out rxcdrhold gt4_rxcdrhold_in rxcdrovrden gt4_rxcdrovrden_in rxcommadet gt4_rxcommadet_out rxdfelpmreset gt4_rxdfelpmreset_in rxdisperr gt4_rx_disp_err_out rxlpmen gt4_rxlpmen_in rxlpmhfhold gt4_rxlpmhfhold_in rxlpmhfovrden gt4_rxlpmhfovrden_in rxlpmlfhold gt4_rxlpmlfhold_in rxlpmreset gt4_rxlpmreset_in rxmonitorout gt4_rxmonitorout_out rxmonitorsel gt4_rxmonitorsel_in rxnotintable gt4_rx_not_in_table_out rxpcsreset gt4_rxpcsreset_in rxpmareset gt4_rxpmareset_in rxpmaresetdone gt4_rxpmaresetdone_out rxprbscntreset gt4_rxprbscntreset_in rxprbserr gt4_rxprbserr_out rxprbssel gt4_rxprbssel_in rxrealign gt4_rx_realign_out rxresetdone gt4_rxresetdone_out txbuferr gt4_tx_buf_err_out txbufstatus gt4_txbufstatus_out txchardispmode gt4_txchardispmode_in txchardispval gt4_txchardispval_in txdiffctrl gt4_txdiffctrl_in txinhibit gt4_txinhibit_in txmaincursor gt4_txmaincursor_in txpcsreset gt4_txpcsreset_in txpmareset gt4_txpmareset_in txpolarity gt4_txpolarity_in txpostcursor gt4_txpostcursor_in txprbsforceerr gt4_txprbsforceerr_in txprbssel gt4_txprbssel_in txprecursor gt4_txprecursor_in txresetdone gt4_txresetdone_out false TRANSCEIVER_DEBUG5 TRANSCEIVER_DEBUG5 Transceiver debug interface for gt5 cplllock gt5_cplllock_out dmonitorout gt5_dmonitorout_out eyescandataerror gt5_eyescandataerror_out eyescanreset gt5_eyescanreset_in eyescantrigger gt5_eyescantrigger_in rxbuferr gt5_rx_buf_err_out rxbufreset gt5_rxbufreset_in rxbufstatus gt5_rxbufstatus_out rxbyteisaligned gt5_rxbyteisaligned_out rxcdrhold gt5_rxcdrhold_in rxcdrovrden gt5_rxcdrovrden_in rxcommadet gt5_rxcommadet_out rxdfelpmreset gt5_rxdfelpmreset_in rxdisperr gt5_rx_disp_err_out rxlpmen gt5_rxlpmen_in rxlpmhfhold gt5_rxlpmhfhold_in rxlpmhfovrden gt5_rxlpmhfovrden_in rxlpmlfhold gt5_rxlpmlfhold_in rxlpmreset gt5_rxlpmreset_in rxmonitorout gt5_rxmonitorout_out rxmonitorsel gt5_rxmonitorsel_in rxnotintable gt5_rx_not_in_table_out rxpcsreset gt5_rxpcsreset_in rxpmareset gt5_rxpmareset_in rxpmaresetdone gt5_rxpmaresetdone_out rxprbscntreset gt5_rxprbscntreset_in rxprbserr gt5_rxprbserr_out rxprbssel gt5_rxprbssel_in rxrealign gt5_rx_realign_out rxresetdone gt5_rxresetdone_out txbuferr gt5_tx_buf_err_out txbufstatus gt5_txbufstatus_out txchardispmode gt5_txchardispmode_in txchardispval gt5_txchardispval_in txdiffctrl gt5_txdiffctrl_in txinhibit gt5_txinhibit_in txmaincursor gt5_txmaincursor_in txpcsreset gt5_txpcsreset_in txpmareset gt5_txpmareset_in txpolarity gt5_txpolarity_in txpostcursor gt5_txpostcursor_in txprbsforceerr gt5_txprbsforceerr_in txprbssel gt5_txprbssel_in txprecursor gt5_txprecursor_in txresetdone gt5_txresetdone_out false TRANSCEIVER_DEBUG6 TRANSCEIVER_DEBUG6 Transceiver debug interface for gt6 cplllock gt6_cplllock_out dmonitorout gt6_dmonitorout_out eyescandataerror gt6_eyescandataerror_out eyescanreset gt6_eyescanreset_in eyescantrigger gt6_eyescantrigger_in rxbuferr gt6_rx_buf_err_out rxbufreset gt6_rxbufreset_in rxbufstatus gt6_rxbufstatus_out rxbyteisaligned gt6_rxbyteisaligned_out rxcdrhold gt6_rxcdrhold_in rxcdrovrden gt6_rxcdrovrden_in rxcommadet gt6_rxcommadet_out rxdfelpmreset gt6_rxdfelpmreset_in rxdisperr gt6_rx_disp_err_out rxlpmen gt6_rxlpmen_in rxlpmhfhold gt6_rxlpmhfhold_in rxlpmhfovrden gt6_rxlpmhfovrden_in rxlpmlfhold gt6_rxlpmlfhold_in rxlpmreset gt6_rxlpmreset_in rxmonitorout gt6_rxmonitorout_out rxmonitorsel gt6_rxmonitorsel_in rxnotintable gt6_rx_not_in_table_out rxpcsreset gt6_rxpcsreset_in rxpmareset gt6_rxpmareset_in rxpmaresetdone gt6_rxpmaresetdone_out rxprbscntreset gt6_rxprbscntreset_in rxprbserr gt6_rxprbserr_out rxprbssel gt6_rxprbssel_in rxrealign gt6_rx_realign_out rxresetdone gt6_rxresetdone_out txbuferr gt6_tx_buf_err_out txbufstatus gt6_txbufstatus_out txchardispmode gt6_txchardispmode_in txchardispval gt6_txchardispval_in txdiffctrl gt6_txdiffctrl_in txinhibit gt6_txinhibit_in txmaincursor gt6_txmaincursor_in txpcsreset gt6_txpcsreset_in txpmareset gt6_txpmareset_in txpolarity gt6_txpolarity_in txpostcursor gt6_txpostcursor_in txprbsforceerr gt6_txprbsforceerr_in txprbssel gt6_txprbssel_in txprecursor gt6_txprecursor_in txresetdone gt6_txresetdone_out false TRANSCEIVER_DEBUG7 TRANSCEIVER_DEBUG7 Transceiver debug interface for gt7 cplllock gt7_cplllock_out dmonitorout gt7_dmonitorout_out eyescandataerror gt7_eyescandataerror_out eyescanreset gt7_eyescanreset_in eyescantrigger gt7_eyescantrigger_in rxbuferr gt7_rx_buf_err_out rxbufreset gt7_rxbufreset_in rxbufstatus gt7_rxbufstatus_out rxbyteisaligned gt7_rxbyteisaligned_out rxcdrhold gt7_rxcdrhold_in rxcdrovrden gt7_rxcdrovrden_in rxcommadet gt7_rxcommadet_out rxdfelpmreset gt7_rxdfelpmreset_in rxdisperr gt7_rx_disp_err_out rxlpmen gt7_rxlpmen_in rxlpmhfhold gt7_rxlpmhfhold_in rxlpmhfovrden gt7_rxlpmhfovrden_in rxlpmlfhold gt7_rxlpmlfhold_in rxlpmreset gt7_rxlpmreset_in rxmonitorout gt7_rxmonitorout_out rxmonitorsel gt7_rxmonitorsel_in rxnotintable gt7_rx_not_in_table_out rxpcsreset gt7_rxpcsreset_in rxpmareset gt7_rxpmareset_in rxpmaresetdone gt7_rxpmaresetdone_out rxprbscntreset gt7_rxprbscntreset_in rxprbserr gt7_rxprbserr_out rxprbssel gt7_rxprbssel_in rxrealign gt7_rx_realign_out rxresetdone gt7_rxresetdone_out txbuferr gt7_tx_buf_err_out txbufstatus gt7_txbufstatus_out txchardispmode gt7_txchardispmode_in txchardispval gt7_txchardispval_in txdiffctrl gt7_txdiffctrl_in txinhibit gt7_txinhibit_in txmaincursor gt7_txmaincursor_in txpcsreset gt7_txpcsreset_in txpmareset gt7_txpmareset_in txpolarity gt7_txpolarity_in txpostcursor gt7_txpostcursor_in txprbsforceerr gt7_txprbsforceerr_in txprbssel gt7_txprbssel_in txprecursor gt7_txprecursor_in txresetdone gt7_txresetdone_out false TRANSCEIVER_DEBUG8 TRANSCEIVER_DEBUG8 Transceiver debug interface for gt8 cplllock gt8_cplllock_out dmonitorout gt8_dmonitorout_out eyescandataerror gt8_eyescandataerror_out eyescanreset gt8_eyescanreset_in eyescantrigger gt8_eyescantrigger_in rxbuferr gt8_rx_buf_err_out rxbufreset gt8_rxbufreset_in rxbufstatus gt8_rxbufstatus_out rxbyteisaligned gt8_rxbyteisaligned_out rxcdrhold gt8_rxcdrhold_in rxcdrovrden gt8_rxcdrovrden_in rxcommadet gt8_rxcommadet_out rxdfelpmreset gt8_rxdfelpmreset_in rxdisperr gt8_rx_disp_err_out rxlpmen gt8_rxlpmen_in rxlpmhfhold gt8_rxlpmhfhold_in rxlpmhfovrden gt8_rxlpmhfovrden_in rxlpmlfhold gt8_rxlpmlfhold_in rxlpmreset gt8_rxlpmreset_in rxmonitorout gt8_rxmonitorout_out rxmonitorsel gt8_rxmonitorsel_in rxnotintable gt8_rx_not_in_table_out rxpcsreset gt8_rxpcsreset_in rxpmareset gt8_rxpmareset_in rxpmaresetdone gt8_rxpmaresetdone_out rxprbscntreset gt8_rxprbscntreset_in rxprbserr gt8_rxprbserr_out rxprbssel gt8_rxprbssel_in rxrealign gt8_rx_realign_out rxresetdone gt8_rxresetdone_out txbuferr gt8_tx_buf_err_out txbufstatus gt8_txbufstatus_out txchardispmode gt8_txchardispmode_in txchardispval gt8_txchardispval_in txdiffctrl gt8_txdiffctrl_in txinhibit gt8_txinhibit_in txmaincursor gt8_txmaincursor_in txpcsreset gt8_txpcsreset_in txpmareset gt8_txpmareset_in txpolarity gt8_txpolarity_in txpostcursor gt8_txpostcursor_in txprbsforceerr gt8_txprbsforceerr_in txprbssel gt8_txprbssel_in txprecursor gt8_txprecursor_in txresetdone gt8_txresetdone_out false TRANSCEIVER_DEBUG9 TRANSCEIVER_DEBUG9 Transceiver debug interface for gt9 cplllock gt9_cplllock_out dmonitorout gt9_dmonitorout_out eyescandataerror gt9_eyescandataerror_out eyescanreset gt9_eyescanreset_in eyescantrigger gt9_eyescantrigger_in rxbuferr gt9_rx_buf_err_out rxbufreset gt9_rxbufreset_in rxbufstatus gt9_rxbufstatus_out rxbyteisaligned gt9_rxbyteisaligned_out rxcdrhold gt9_rxcdrhold_in rxcdrovrden gt9_rxcdrovrden_in rxcommadet gt9_rxcommadet_out rxdfelpmreset gt9_rxdfelpmreset_in rxdisperr gt9_rx_disp_err_out rxlpmen gt9_rxlpmen_in rxlpmhfhold gt9_rxlpmhfhold_in rxlpmhfovrden gt9_rxlpmhfovrden_in rxlpmlfhold gt9_rxlpmlfhold_in rxlpmreset gt9_rxlpmreset_in rxmonitorout gt9_rxmonitorout_out rxmonitorsel gt9_rxmonitorsel_in rxnotintable gt9_rx_not_in_table_out rxpcsreset gt9_rxpcsreset_in rxpmareset gt9_rxpmareset_in rxpmaresetdone gt9_rxpmaresetdone_out rxprbscntreset gt9_rxprbscntreset_in rxprbserr gt9_rxprbserr_out rxprbssel gt9_rxprbssel_in rxrealign gt9_rx_realign_out rxresetdone gt9_rxresetdone_out txbuferr gt9_tx_buf_err_out txbufstatus gt9_txbufstatus_out txchardispmode gt9_txchardispmode_in txchardispval gt9_txchardispval_in txdiffctrl gt9_txdiffctrl_in txinhibit gt9_txinhibit_in txmaincursor gt9_txmaincursor_in txpcsreset gt9_txpcsreset_in txpmareset gt9_txpmareset_in txpolarity gt9_txpolarity_in txpostcursor gt9_txpostcursor_in txprbsforceerr gt9_txprbsforceerr_in txprbssel gt9_txprbssel_in txprecursor gt9_txprecursor_in txresetdone gt9_txresetdone_out false TRANSCEIVER_DEBUG10 TRANSCEIVER_DEBUG10 Transceiver debug interface for gt10 cplllock gt10_cplllock_out dmonitorout gt10_dmonitorout_out eyescandataerror gt10_eyescandataerror_out eyescanreset gt10_eyescanreset_in eyescantrigger gt10_eyescantrigger_in rxbuferr gt10_rx_buf_err_out rxbufreset gt10_rxbufreset_in rxbufstatus gt10_rxbufstatus_out rxbyteisaligned gt10_rxbyteisaligned_out rxcdrhold gt10_rxcdrhold_in rxcdrovrden gt10_rxcdrovrden_in rxcommadet gt10_rxcommadet_out rxdfelpmreset gt10_rxdfelpmreset_in rxdisperr gt10_rx_disp_err_out rxlpmen gt10_rxlpmen_in rxlpmhfhold gt10_rxlpmhfhold_in rxlpmhfovrden gt10_rxlpmhfovrden_in rxlpmlfhold gt10_rxlpmlfhold_in rxlpmreset gt10_rxlpmreset_in rxmonitorout gt10_rxmonitorout_out rxmonitorsel gt10_rxmonitorsel_in rxnotintable gt10_rx_not_in_table_out rxpcsreset gt10_rxpcsreset_in rxpmareset gt10_rxpmareset_in rxpmaresetdone gt10_rxpmaresetdone_out rxprbscntreset gt10_rxprbscntreset_in rxprbserr gt10_rxprbserr_out rxprbssel gt10_rxprbssel_in rxrealign gt10_rx_realign_out rxresetdone gt10_rxresetdone_out txbuferr gt10_tx_buf_err_out txbufstatus gt10_txbufstatus_out txchardispmode gt10_txchardispmode_in txchardispval gt10_txchardispval_in txdiffctrl gt10_txdiffctrl_in txinhibit gt10_txinhibit_in txmaincursor gt10_txmaincursor_in txpcsreset gt10_txpcsreset_in txpmareset gt10_txpmareset_in txpolarity gt10_txpolarity_in txpostcursor gt10_txpostcursor_in txprbsforceerr gt10_txprbsforceerr_in txprbssel gt10_txprbssel_in txprecursor gt10_txprecursor_in txresetdone gt10_txresetdone_out false TRANSCEIVER_DEBUG11 TRANSCEIVER_DEBUG11 Transceiver debug interface for gt11 cplllock gt11_cplllock_out dmonitorout gt11_dmonitorout_out eyescandataerror gt11_eyescandataerror_out eyescanreset gt11_eyescanreset_in eyescantrigger gt11_eyescantrigger_in rxbuferr gt11_rx_buf_err_out rxbufreset gt11_rxbufreset_in rxbufstatus gt11_rxbufstatus_out rxbyteisaligned gt11_rxbyteisaligned_out rxcdrhold gt11_rxcdrhold_in rxcdrovrden gt11_rxcdrovrden_in rxcommadet gt11_rxcommadet_out rxdfelpmreset gt11_rxdfelpmreset_in rxdisperr gt11_rx_disp_err_out rxlpmen gt11_rxlpmen_in rxlpmhfhold gt11_rxlpmhfhold_in rxlpmhfovrden gt11_rxlpmhfovrden_in rxlpmlfhold gt11_rxlpmlfhold_in rxlpmreset gt11_rxlpmreset_in rxmonitorout gt11_rxmonitorout_out rxmonitorsel gt11_rxmonitorsel_in rxnotintable gt11_rx_not_in_table_out rxpcsreset gt11_rxpcsreset_in rxpmareset gt11_rxpmareset_in rxpmaresetdone gt11_rxpmaresetdone_out rxprbscntreset gt11_rxprbscntreset_in rxprbserr gt11_rxprbserr_out rxprbssel gt11_rxprbssel_in rxrealign gt11_rx_realign_out rxresetdone gt11_rxresetdone_out txbuferr gt11_tx_buf_err_out txbufstatus gt11_txbufstatus_out txchardispmode gt11_txchardispmode_in txchardispval gt11_txchardispval_in txdiffctrl gt11_txdiffctrl_in txinhibit gt11_txinhibit_in txmaincursor gt11_txmaincursor_in txpcsreset gt11_txpcsreset_in txpmareset gt11_txpmareset_in txpolarity gt11_txpolarity_in txpostcursor gt11_txpostcursor_in txprbsforceerr gt11_txprbsforceerr_in txprbssel gt11_txprbssel_in txprecursor gt11_txprecursor_in txresetdone gt11_txresetdone_out false TRANSCEIVER_DEBUG12 TRANSCEIVER_DEBUG12 Transceiver debug interface for gt12 cplllock gt12_cplllock_out dmonitorout gt12_dmonitorout_out eyescandataerror gt12_eyescandataerror_out eyescanreset gt12_eyescanreset_in eyescantrigger gt12_eyescantrigger_in rxbuferr gt12_rx_buf_err_out rxbufreset gt12_rxbufreset_in rxbufstatus gt12_rxbufstatus_out rxbyteisaligned gt12_rxbyteisaligned_out rxcdrhold gt12_rxcdrhold_in rxcdrovrden gt12_rxcdrovrden_in rxcommadet gt12_rxcommadet_out rxdfelpmreset gt12_rxdfelpmreset_in rxdisperr gt12_rx_disp_err_out rxlpmen gt12_rxlpmen_in rxlpmhfhold gt12_rxlpmhfhold_in rxlpmhfovrden gt12_rxlpmhfovrden_in rxlpmlfhold gt12_rxlpmlfhold_in rxlpmreset gt12_rxlpmreset_in rxmonitorout gt12_rxmonitorout_out rxmonitorsel gt12_rxmonitorsel_in rxnotintable gt12_rx_not_in_table_out rxpcsreset gt12_rxpcsreset_in rxpmareset gt12_rxpmareset_in rxpmaresetdone gt12_rxpmaresetdone_out rxprbscntreset gt12_rxprbscntreset_in rxprbserr gt12_rxprbserr_out rxprbssel gt12_rxprbssel_in rxrealign gt12_rx_realign_out rxresetdone gt12_rxresetdone_out txbuferr gt12_tx_buf_err_out txbufstatus gt12_txbufstatus_out txchardispmode gt12_txchardispmode_in txchardispval gt12_txchardispval_in txdiffctrl gt12_txdiffctrl_in txinhibit gt12_txinhibit_in txmaincursor gt12_txmaincursor_in txpcsreset gt12_txpcsreset_in txpmareset gt12_txpmareset_in txpolarity gt12_txpolarity_in txpostcursor gt12_txpostcursor_in txprbsforceerr gt12_txprbsforceerr_in txprbssel gt12_txprbssel_in txprecursor gt12_txprecursor_in txresetdone gt12_txresetdone_out false TRANSCEIVER_DEBUG13 TRANSCEIVER_DEBUG13 Transceiver debug interface for gt13 cplllock gt13_cplllock_out dmonitorout gt13_dmonitorout_out eyescandataerror gt13_eyescandataerror_out eyescanreset gt13_eyescanreset_in eyescantrigger gt13_eyescantrigger_in rxbuferr gt13_rx_buf_err_out rxbufreset gt13_rxbufreset_in rxbufstatus gt13_rxbufstatus_out rxbyteisaligned gt13_rxbyteisaligned_out rxcdrhold gt13_rxcdrhold_in rxcdrovrden gt13_rxcdrovrden_in rxcommadet gt13_rxcommadet_out rxdfelpmreset gt13_rxdfelpmreset_in rxdisperr gt13_rx_disp_err_out rxlpmen gt13_rxlpmen_in rxlpmhfhold gt13_rxlpmhfhold_in rxlpmhfovrden gt13_rxlpmhfovrden_in rxlpmlfhold gt13_rxlpmlfhold_in rxlpmreset gt13_rxlpmreset_in rxmonitorout gt13_rxmonitorout_out rxmonitorsel gt13_rxmonitorsel_in rxnotintable gt13_rx_not_in_table_out rxpcsreset gt13_rxpcsreset_in rxpmareset gt13_rxpmareset_in rxpmaresetdone gt13_rxpmaresetdone_out rxprbscntreset gt13_rxprbscntreset_in rxprbserr gt13_rxprbserr_out rxprbssel gt13_rxprbssel_in rxrealign gt13_rx_realign_out rxresetdone gt13_rxresetdone_out txbuferr gt13_tx_buf_err_out txbufstatus gt13_txbufstatus_out txchardispmode gt13_txchardispmode_in txchardispval gt13_txchardispval_in txdiffctrl gt13_txdiffctrl_in txinhibit gt13_txinhibit_in txmaincursor gt13_txmaincursor_in txpcsreset gt13_txpcsreset_in txpmareset gt13_txpmareset_in txpolarity gt13_txpolarity_in txpostcursor gt13_txpostcursor_in txprbsforceerr gt13_txprbsforceerr_in txprbssel gt13_txprbssel_in txprecursor gt13_txprecursor_in txresetdone gt13_txresetdone_out false TRANSCEIVER_DEBUG14 TRANSCEIVER_DEBUG14 Transceiver debug interface for gt14 cplllock gt14_cplllock_out dmonitorout gt14_dmonitorout_out eyescandataerror gt14_eyescandataerror_out eyescanreset gt14_eyescanreset_in eyescantrigger gt14_eyescantrigger_in rxbuferr gt14_rx_buf_err_out rxbufreset gt14_rxbufreset_in rxbufstatus gt14_rxbufstatus_out rxbyteisaligned gt14_rxbyteisaligned_out rxcdrhold gt14_rxcdrhold_in rxcdrovrden gt14_rxcdrovrden_in rxcommadet gt14_rxcommadet_out rxdfelpmreset gt14_rxdfelpmreset_in rxdisperr gt14_rx_disp_err_out rxlpmen gt14_rxlpmen_in rxlpmhfhold gt14_rxlpmhfhold_in rxlpmhfovrden gt14_rxlpmhfovrden_in rxlpmlfhold gt14_rxlpmlfhold_in rxlpmreset gt14_rxlpmreset_in rxmonitorout gt14_rxmonitorout_out rxmonitorsel gt14_rxmonitorsel_in rxnotintable gt14_rx_not_in_table_out rxpcsreset gt14_rxpcsreset_in rxpmareset gt14_rxpmareset_in rxpmaresetdone gt14_rxpmaresetdone_out rxprbscntreset gt14_rxprbscntreset_in rxprbserr gt14_rxprbserr_out rxprbssel gt14_rxprbssel_in rxrealign gt14_rx_realign_out rxresetdone gt14_rxresetdone_out txbuferr gt14_tx_buf_err_out txbufstatus gt14_txbufstatus_out txchardispmode gt14_txchardispmode_in txchardispval gt14_txchardispval_in txdiffctrl gt14_txdiffctrl_in txinhibit gt14_txinhibit_in txmaincursor gt14_txmaincursor_in txpcsreset gt14_txpcsreset_in txpmareset gt14_txpmareset_in txpolarity gt14_txpolarity_in txpostcursor gt14_txpostcursor_in txprbsforceerr gt14_txprbsforceerr_in txprbssel gt14_txprbssel_in txprecursor gt14_txprecursor_in txresetdone gt14_txresetdone_out false TRANSCEIVER_DEBUG15 TRANSCEIVER_DEBUG15 Transceiver debug interface for gt15 cplllock gt15_cplllock_out dmonitorout gt15_dmonitorout_out eyescandataerror gt15_eyescandataerror_out eyescanreset gt15_eyescanreset_in eyescantrigger gt15_eyescantrigger_in rxbuferr gt15_rx_buf_err_out rxbufreset gt15_rxbufreset_in rxbufstatus gt15_rxbufstatus_out rxbyteisaligned gt15_rxbyteisaligned_out rxcdrhold gt15_rxcdrhold_in rxcdrovrden gt15_rxcdrovrden_in rxcommadet gt15_rxcommadet_out rxdfelpmreset gt15_rxdfelpmreset_in rxdisperr gt15_rx_disp_err_out rxlpmen gt15_rxlpmen_in rxlpmhfhold gt15_rxlpmhfhold_in rxlpmhfovrden gt15_rxlpmhfovrden_in rxlpmlfhold gt15_rxlpmlfhold_in rxlpmreset gt15_rxlpmreset_in rxmonitorout gt15_rxmonitorout_out rxmonitorsel gt15_rxmonitorsel_in rxnotintable gt15_rx_not_in_table_out rxpcsreset gt15_rxpcsreset_in rxpmareset gt15_rxpmareset_in rxpmaresetdone gt15_rxpmaresetdone_out rxprbscntreset gt15_rxprbscntreset_in rxprbserr gt15_rxprbserr_out rxprbssel gt15_rxprbssel_in rxrealign gt15_rx_realign_out rxresetdone gt15_rxresetdone_out txbuferr gt15_tx_buf_err_out txbufstatus gt15_txbufstatus_out txchardispmode gt15_txchardispmode_in txchardispval gt15_txchardispval_in txdiffctrl gt15_txdiffctrl_in txinhibit gt15_txinhibit_in txmaincursor gt15_txmaincursor_in txpcsreset gt15_txpcsreset_in txpmareset gt15_txpmareset_in txpolarity gt15_txpolarity_in txpostcursor gt15_txpostcursor_in txprbsforceerr gt15_txprbsforceerr_in txprbssel gt15_txprbssel_in txprecursor gt15_txprecursor_in txresetdone gt15_txresetdone_out false RX_SIDEBAND_SIGNALS RX_SIDEBAND_SIGNALS RX SIDEBAND Signals must be connected with TX_SIDEBAND_SIGNALS ALIGNED rx_aligned BONDED rx_bonded RESET rx_reset VERIFY rx_verify false CORE_STATUS CORE_STATUS Aurora Core Status pins BUFG_GT_CLR_OUT bufg_gt_clr_out CHANNEL_UP channel_up CRC_PASS_FAIL crc_pass_fail_n CRC_VALID crc_valid FRAME_ERR frame_err HARD_ERR hard_err LANE_UP lane_up PLL_NOT_LOCKED_OUT pll_not_locked_out RX_CHANNEL_UP rx_channel_up RX_HARD_ERR rx_hard_err RX_LANE_UP rx_lane_up RX_RESETDONE_OUT rx_resetdone_out SOFT_ERR soft_err TX_CHANNEL_UP tx_channel_up TX_HARD_ERR tx_hard_err TX_LANE_UP tx_lane_up TX_LOCK tx_lock TX_RESETDONE_OUT tx_resetdone_out TX_SIDEBAND_SIGNALS TX_SIDEBAND_SIGNALS Must be connected to RX_SIDEBAND_SIGNALS true ALIGNED tx_aligned BONDED tx_bonded RESET tx_reset VERIFY tx_verify false CORE_CONTROL CORE_CONTROL Aurora Core Control Pins LOOPBACK loopback PLL_NOT_LOCKED pll_not_locked Power_down power_down GT_SERIAL_TX GT_SERIAL_TX Serial GT Transceiver TX Pins interface TXN txn TXP txp false GT_SERIAL_RX GT_SERIAL_RX Serial GT Transceiver RX Pins interface RXN rxn RXP rxp true QPLL_CONTROL_IN QPLL_CONTROL_IN Clock inputs generated by active transceiver quad QPLLLOCK_QUAD1_IN gt0_qplllock_in QPLLLOCK_QUAD2_IN gt1_qplllock_in QPLLLOCK_QUAD3_IN gt2_qplllock_in QPLLLOCK_QUAD4_IN gt3_qplllock_in QPLLLOCK_QUAD5_IN gt4_qplllock_in QPLLLOCK_QUAD6_IN gt5_qplllock_in QPLLLOCK_QUAD7_IN gt6_qplllock_in QPLLLOCK_QUAD8_IN gt7_qplllock_in QPLLLOCK_QUAD9_IN gt8_qplllock_in QPLLLOCK_QUAD10_IN gt9_qplllock_in QPLLLOCK_QUAD11_IN gt10_qplllock_in QPLLLOCK_QUAD12_IN gt11_qplllock_in QPLLREFCLKLOST_QUAD1_IN gt0_qpllrefclklost_in QPLLREFCLKLOST_QUAD2_IN gt1_qpllrefclklost_in QPLLREFCLKLOST_QUAD3_IN gt2_qpllrefclklost_in QPLLREFCLKLOST_QUAD4_IN gt3_qpllrefclklost_in QPLLREFCLKLOST_QUAD5_IN gt4_qpllrefclklost_in QPLLREFCLKLOST_QUAD6_IN gt5_qpllrefclklost_in QPLLREFCLKLOST_QUAD7_IN gt6_qpllrefclklost_in QPLLREFCLKLOST_QUAD8_IN gt7_qpllrefclklost_in QPLLREFCLKLOST_QUAD9_IN gt8_qpllrefclklost_in QPLLREFCLKLOST_QUAD10_IN gt9_qpllrefclklost_in QPLLREFCLKLOST_QUAD11_IN gt10_qpllrefclklost_in QPLLREFCLKLOST_QUAD12_IN gt11_qpllrefclklost_in true QPLL_CONTROL_OUT QPLL_CONTROL_OUT Clock outputs generated by active transceiver quad QPLLLOCK_QUAD1_OUT gt0_qplllock_out QPLLLOCK_QUAD2_OUT gt1_qplllock_out QPLLLOCK_QUAD3_OUT gt2_qplllock_out QPLLLOCK_QUAD4_OUT gt3_qplllock_out QPLLLOCK_QUAD5_OUT gt4_qplllock_out QPLLLOCK_QUAD6_OUT gt5_qplllock_out QPLLLOCK_QUAD7_OUT gt6_qplllock_out QPLLLOCK_QUAD8_OUT gt7_qplllock_out QPLLLOCK_QUAD9_OUT gt8_qplllock_out QPLLLOCK_QUAD10_OUT gt9_qplllock_out QPLLLOCK_QUAD11_OUT gt10_qplllock_out QPLLLOCK_QUAD12_OUT gt11_qplllock_out QPLLREFCLKLOST_QUAD1_OUT gt0_qpllrefclklost_out QPLLREFCLKLOST_QUAD2_OUT gt1_qpllrefclklost_out QPLLREFCLKLOST_QUAD3_OUT gt2_qpllrefclklost_out QPLLREFCLKLOST_QUAD4_OUT gt3_qpllrefclklost_out QPLLREFCLKLOST_QUAD5_OUT gt4_qpllrefclklost_out QPLLREFCLKLOST_QUAD6_OUT gt5_qpllrefclklost_out QPLLREFCLKLOST_QUAD7_OUT gt6_qpllrefclklost_out QPLLREFCLKLOST_QUAD8_OUT gt7_qpllrefclklost_out QPLLREFCLKLOST_QUAD9_OUT gt8_qpllrefclklost_out QPLLREFCLKLOST_QUAD10_OUT gt9_qpllrefclklost_out QPLLREFCLKLOST_QUAD11_OUT gt10_qpllrefclklost_out QPLLREFCLKLOST_QUAD12_OUT gt11_qpllrefclklost_out false xilinx_elaboratesubcores Elaborate Sub-Cores :vivado.xilinx.com:elaborate.subcores outputProductCRC 9:7ee0c23f xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis aurora_8b10b_v11_1_8 xilinx_anylanguagesynthesis_view_fileset GENtimestamp Mon May 04 20:56:50 UTC 2020 outputProductCRC 9:90febf16 xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints outputProductCRC 9:90febf16 xilinx_vhdlsynthesiswrapper VHDL Synthesis Wrapper vhdlSource:vivado.xilinx.com:synthesis.wrapper vhdl aurora_rx_1q xilinx_vhdlsynthesiswrapper_view_fileset GENtimestamp Mon May 04 20:56:50 UTC 2020 outputProductCRC 9:90febf16 xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Mon May 04 21:08:41 UTC 2020 outputProductCRC 9:90febf16 s_axi_tx_tdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis 0 false s_axi_tx_tkeep in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 false s_axi_tx_tlast in std_logic xilinx_anylanguagesynthesis 0 false s_axi_tx_tvalid in std_logic xilinx_anylanguagesynthesis 0 false s_axi_tx_tready out std_logic xilinx_anylanguagesynthesis false s_axi_nfc_tx_tvalid in std_logic xilinx_anylanguagesynthesis 0 false s_axi_nfc_tx_tdata in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false s_axi_nfc_tx_tready out std_logic xilinx_anylanguagesynthesis false s_axi_ufc_tx_tvalid in std_logic xilinx_anylanguagesynthesis 0 false s_axi_ufc_tx_tdata in 2 0 std_logic_vector xilinx_anylanguagesynthesis 0 false s_axi_ufc_tx_tready out std_logic xilinx_anylanguagesynthesis false m_axi_rx_tdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis true m_axi_rx_tkeep out 7 0 std_logic_vector xilinx_anylanguagesynthesis true m_axi_rx_tlast out std_logic xilinx_anylanguagesynthesis true m_axi_rx_tvalid out std_logic xilinx_anylanguagesynthesis true m_axi_ufc_rx_tdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis true m_axi_ufc_rx_tkeep out 7 0 std_logic_vector xilinx_anylanguagesynthesis true m_axi_ufc_rx_tlast out std_logic xilinx_anylanguagesynthesis true m_axi_ufc_rx_tvalid out std_logic xilinx_anylanguagesynthesis true hard_err out std_logic xilinx_anylanguagesynthesis false rx_hard_err out std_logic xilinx_anylanguagesynthesis true tx_hard_err out std_logic xilinx_anylanguagesynthesis false soft_err out std_logic xilinx_anylanguagesynthesis true frame_err out std_logic xilinx_anylanguagesynthesis true channel_up out std_logic xilinx_anylanguagesynthesis false rx_channel_up out std_logic xilinx_anylanguagesynthesis true tx_channel_up out std_logic xilinx_anylanguagesynthesis false lane_up out 0 3 std_logic_vector xilinx_anylanguagesynthesis false rx_lane_up out 0 3 std_logic_vector xilinx_anylanguagesynthesis true tx_lane_up out 0 3 std_logic_vector xilinx_anylanguagesynthesis false txp out 0 3 std_logic_vector xilinx_anylanguagesynthesis false txn out 0 3 std_logic_vector xilinx_anylanguagesynthesis false rx_aligned out std_logic xilinx_anylanguagesynthesis false rx_bonded out std_logic xilinx_anylanguagesynthesis false rx_verify out std_logic xilinx_anylanguagesynthesis false rx_reset out std_logic xilinx_anylanguagesynthesis false rx_system_reset in std_logic xilinx_anylanguagesynthesis 0 true tx_system_reset in std_logic xilinx_anylanguagesynthesis 0 false reset in std_logic xilinx_anylanguagesynthesis 0 false gt_reset in std_logic xilinx_anylanguagesynthesis 0 loopback in 2 0 std_logic_vector xilinx_anylanguagesynthesis 0 true rxp in 0 3 std_logic_vector xilinx_anylanguagesynthesis 0 true rxn in 0 3 std_logic_vector xilinx_anylanguagesynthesis 0 true tx_aligned in std_logic xilinx_anylanguagesynthesis 0 false tx_bonded in std_logic xilinx_anylanguagesynthesis 0 false tx_verify in std_logic xilinx_anylanguagesynthesis 0 false tx_reset in std_logic xilinx_anylanguagesynthesis 0 false crc_valid out std_logic xilinx_anylanguagesynthesis false crc_pass_fail_n out std_logic xilinx_anylanguagesynthesis false drpclk_in in std_logic xilinx_anylanguagesynthesis 0 true gt0_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt0_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt0_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt0_drprdy out std_logic xilinx_anylanguagesynthesis false gt0_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt0_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt1_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt1_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_drprdy out std_logic xilinx_anylanguagesynthesis false gt1_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt1_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt2_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt2_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_drprdy out std_logic xilinx_anylanguagesynthesis false gt2_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt2_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt3_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt3_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_drprdy out std_logic xilinx_anylanguagesynthesis false gt3_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt3_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt4_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt4_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_drprdy out std_logic xilinx_anylanguagesynthesis false gt4_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt4_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt5_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt5_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt5_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt5_drprdy out std_logic xilinx_anylanguagesynthesis false gt5_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt5_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt6_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt6_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt6_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt6_drprdy out std_logic xilinx_anylanguagesynthesis false gt6_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt6_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt7_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt7_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt7_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt7_drprdy out std_logic xilinx_anylanguagesynthesis false gt7_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt7_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt8_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt8_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt8_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt8_drprdy out std_logic xilinx_anylanguagesynthesis false gt8_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt8_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt9_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt9_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt9_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt9_drprdy out std_logic xilinx_anylanguagesynthesis false gt9_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt9_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt10_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt10_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt10_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt10_drprdy out std_logic xilinx_anylanguagesynthesis false gt10_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt10_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt11_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt11_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt11_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt11_drprdy out std_logic xilinx_anylanguagesynthesis false gt11_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt11_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt12_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt12_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt12_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt12_drprdy out std_logic xilinx_anylanguagesynthesis false gt12_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt12_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt13_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt13_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt13_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt13_drprdy out std_logic xilinx_anylanguagesynthesis false gt13_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt13_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt14_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt14_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt14_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt14_drprdy out std_logic xilinx_anylanguagesynthesis false gt14_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt14_drpwe in std_logic xilinx_anylanguagesynthesis 0 false gt15_drpaddr in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt15_drpen in std_logic xilinx_anylanguagesynthesis 0 false gt15_drpdi in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt15_drprdy out std_logic xilinx_anylanguagesynthesis false gt15_drpdo out 15 0 std_logic_vector xilinx_anylanguagesynthesis false gt15_drpwe in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drpen_in in std_logic xilinx_anylanguagesynthesis 0 true drpdi_in in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drprdy_out out std_logic xilinx_anylanguagesynthesis true drpdo_out out 15 0 std_logic_vector xilinx_anylanguagesynthesis true drpwe_in in std_logic xilinx_anylanguagesynthesis 0 true drpaddr_in_lane1 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drpen_in_lane1 in std_logic xilinx_anylanguagesynthesis 0 true drpdi_in_lane1 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drprdy_out_lane1 out std_logic xilinx_anylanguagesynthesis true drpdo_out_lane1 out 15 0 std_logic_vector xilinx_anylanguagesynthesis true drpwe_in_lane1 in std_logic xilinx_anylanguagesynthesis 0 true drpaddr_in_lane2 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drpen_in_lane2 in std_logic xilinx_anylanguagesynthesis 0 true drpdi_in_lane2 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drprdy_out_lane2 out std_logic xilinx_anylanguagesynthesis true drpdo_out_lane2 out 15 0 std_logic_vector xilinx_anylanguagesynthesis true drpwe_in_lane2 in std_logic xilinx_anylanguagesynthesis 0 true drpaddr_in_lane3 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drpen_in_lane3 in std_logic xilinx_anylanguagesynthesis 0 true drpdi_in_lane3 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 true drprdy_out_lane3 out std_logic xilinx_anylanguagesynthesis true drpdo_out_lane3 out 15 0 std_logic_vector xilinx_anylanguagesynthesis true drpwe_in_lane3 in std_logic xilinx_anylanguagesynthesis 0 true drpaddr_in_lane4 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane4 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane4 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane4 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane4 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane4 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane5 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane5 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane5 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane5 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane5 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane5 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane6 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane6 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane6 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane6 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane6 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane6 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane7 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane7 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane7 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane7 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane7 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane7 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane8 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane8 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane8 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane8 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane8 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane8 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane9 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane9 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane9 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane9 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane9 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane9 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane10 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane10 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane10 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane10 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane10 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane10 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane11 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane11 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane11 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane11 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane11 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane11 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane12 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane12 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane12 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane12 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane12 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane12 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane13 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane13 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane13 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane13 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane13 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane13 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane14 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane14 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane14 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane14 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane14 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane14 in std_logic xilinx_anylanguagesynthesis 0 false drpaddr_in_lane15 in 8 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drpen_in_lane15 in std_logic xilinx_anylanguagesynthesis 0 false drpdi_in_lane15 in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false drprdy_out_lane15 out std_logic xilinx_anylanguagesynthesis false drpdo_out_lane15 out 15 0 std_logic_vector xilinx_anylanguagesynthesis false drpwe_in_lane15 in std_logic xilinx_anylanguagesynthesis 0 false m_axi_nfc_rx_tvalid out std_logic xilinx_anylanguagesynthesis false m_axi_nfc_rx_tdata out 3 0 std_logic_vector xilinx_anylanguagesynthesis false power_down in std_logic xilinx_anylanguagesynthesis 0 tx_lock out std_logic xilinx_anylanguagesynthesis tx_resetdone_out out std_logic xilinx_anylanguagesynthesis false rx_resetdone_out out std_logic xilinx_anylanguagesynthesis true link_reset_out out std_logic xilinx_anylanguagesynthesis true gt_common_reset_out out std_logic xilinx_anylanguagesynthesis false gt0_pll0outclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt0_pll1outclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt0_pll0outrefclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt0_pll1outrefclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_pll0outclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_pll1outclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_pll0outrefclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_pll1outrefclk_in in std_logic xilinx_anylanguagesynthesis 0 false gt0_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 true gt0_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 true gt0_qpllreset_out out std_logic xilinx_anylanguagesynthesis true gt1_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt2_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt3_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt4_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt5_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt5_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt5_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt6_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt6_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt6_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt7_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt7_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt7_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt8_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt8_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt8_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt9_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt9_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt9_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt10_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt10_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt10_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt11_qplllock_in in std_logic xilinx_anylanguagesynthesis 0 false gt11_qpllrefclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt11_qpllreset_out out std_logic xilinx_anylanguagesynthesis false gt_qpllclk_quad1_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad1_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad2_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad2_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad3_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad3_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad4_in in std_logic xilinx_anylanguagesynthesis 0 true gt_qpllrefclk_quad4_in in std_logic xilinx_anylanguagesynthesis 0 true gt_qpllclk_quad5_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad5_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad6_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad6_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad7_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad7_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad8_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad8_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad9_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad9_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad10_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad10_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad11_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad11_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllclk_quad12_in in std_logic xilinx_anylanguagesynthesis 0 false gt_qpllrefclk_quad12_in in std_logic xilinx_anylanguagesynthesis 0 false gt0_pll0refclklost_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_pll0refclklost_in in std_logic xilinx_anylanguagesynthesis 0 false quad1_common_lock_in in std_logic xilinx_anylanguagesynthesis 0 false quad2_common_lock_in in std_logic xilinx_anylanguagesynthesis 0 false init_clk_in in std_logic xilinx_anylanguagesynthesis 0 true pll_not_locked in std_logic xilinx_anylanguagesynthesis 0 true tx_out_clk out std_logic xilinx_anylanguagesynthesis true init_clk_p in std_logic xilinx_anylanguagesynthesis 0 false init_clk_n in std_logic xilinx_anylanguagesynthesis 0 false user_clk_out out std_logic xilinx_anylanguagesynthesis false pll_not_locked_out out std_logic xilinx_anylanguagesynthesis false bufg_gt_clr_out out std_logic xilinx_anylanguagesynthesis false sys_reset_out out std_logic xilinx_anylanguagesynthesis user_clk in std_logic xilinx_anylanguagesynthesis 0 true sync_clk in std_logic xilinx_anylanguagesynthesis 0 true gt_refclk1 in std_logic xilinx_anylanguagesynthesis 0 true gt_refclk2 in std_logic xilinx_anylanguagesynthesis 0 false gt_refclk1_p in std_logic xilinx_anylanguagesynthesis 0 false gt_refclk1_n in std_logic xilinx_anylanguagesynthesis 0 false gt_refclk2_p in std_logic xilinx_anylanguagesynthesis 0 false gt_refclk2_n in std_logic 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xilinx_anylanguagesynthesis false gt0_rx_not_in_table_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt0_tx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt0_txpolarity_in in std_logic xilinx_anylanguagesynthesis 0 false gt0_txchardispmode_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt0_txchardispval_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt0_txpostcursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt0_txprecursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt0_txdiffctrl_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt0_txmaincursor_in in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_rxlpmhfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_rxlpmlfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_rxlpmen_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_rxcdrovrden_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_rxdfelpmreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_rxmonitorout_out out 6 0 std_logic_vector xilinx_anylanguagesynthesis false gt1_rxmonitorsel_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_eyescanreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_eyescandataerror_out out std_logic xilinx_anylanguagesynthesis false gt1_rxbyteisaligned_out out std_logic xilinx_anylanguagesynthesis false gt1_rxcommadet_out out std_logic xilinx_anylanguagesynthesis false gt1_rx_realign_out out std_logic xilinx_anylanguagesynthesis false gt1_rx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt1_rx_disp_err_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt1_rx_not_in_table_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt1_tx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt1_txpolarity_in in std_logic xilinx_anylanguagesynthesis 0 false gt1_txchardispmode_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_txchardispval_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_txpostcursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_txprecursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_txdiffctrl_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt1_txmaincursor_in in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_rxlpmhfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_rxlpmlfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_rxlpmen_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_rxcdrovrden_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_rxdfelpmreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_rxmonitorout_out out 6 0 std_logic_vector xilinx_anylanguagesynthesis false gt2_rxmonitorsel_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_eyescanreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_eyescandataerror_out out std_logic xilinx_anylanguagesynthesis false gt2_rxbyteisaligned_out out std_logic xilinx_anylanguagesynthesis false gt2_rxcommadet_out out std_logic xilinx_anylanguagesynthesis false gt2_rx_realign_out out std_logic xilinx_anylanguagesynthesis false gt2_rx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt2_rx_disp_err_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt2_rx_not_in_table_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt2_tx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt2_txpolarity_in in std_logic xilinx_anylanguagesynthesis 0 false gt2_txchardispmode_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_txchardispval_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_txpostcursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_txprecursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_txdiffctrl_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt2_txmaincursor_in in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_rxlpmhfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_rxlpmlfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_rxlpmen_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_rxcdrovrden_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_rxdfelpmreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_rxmonitorout_out out 6 0 std_logic_vector xilinx_anylanguagesynthesis false gt3_rxmonitorsel_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_eyescanreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_eyescandataerror_out out std_logic xilinx_anylanguagesynthesis false gt3_rxbyteisaligned_out out std_logic xilinx_anylanguagesynthesis false gt3_rxcommadet_out out std_logic xilinx_anylanguagesynthesis false gt3_rx_realign_out out std_logic xilinx_anylanguagesynthesis false gt3_rx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt3_rx_disp_err_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt3_rx_not_in_table_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt3_tx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt3_txpolarity_in in std_logic xilinx_anylanguagesynthesis 0 false gt3_txchardispmode_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_txchardispval_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_txpostcursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_txprecursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_txdiffctrl_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt3_txmaincursor_in in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_rxlpmhfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_rxlpmlfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_rxlpmen_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_rxcdrovrden_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_rxdfelpmreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_rxmonitorout_out out 6 0 std_logic_vector xilinx_anylanguagesynthesis false gt4_rxmonitorsel_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_eyescanreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_eyescandataerror_out out std_logic xilinx_anylanguagesynthesis false gt4_rxbyteisaligned_out out std_logic xilinx_anylanguagesynthesis false gt4_rxcommadet_out out std_logic xilinx_anylanguagesynthesis false gt4_rx_realign_out out std_logic xilinx_anylanguagesynthesis false gt4_rx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt4_rx_disp_err_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt4_rx_not_in_table_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt4_tx_buf_err_out out std_logic xilinx_anylanguagesynthesis false gt4_txpolarity_in in std_logic xilinx_anylanguagesynthesis 0 false gt4_txchardispmode_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_txchardispval_in in 1 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_txpostcursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_txprecursor_in in 4 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_txdiffctrl_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt4_txmaincursor_in in 6 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt5_rxlpmhfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt5_rxlpmlfhold_in in std_logic xilinx_anylanguagesynthesis 0 false gt5_rxlpmen_in in std_logic xilinx_anylanguagesynthesis 0 false gt5_rxcdrovrden_in in std_logic xilinx_anylanguagesynthesis 0 false gt5_rxdfelpmreset_in in std_logic xilinx_anylanguagesynthesis 0 false gt5_rxmonitorout_out out 6 0 std_logic_vector xilinx_anylanguagesynthesis false gt5_rxmonitorsel_in in 1 0 std_logic_vector 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gt5_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt6_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt7_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt8_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt9_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt10_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt11_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt12_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt13_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt14_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt15_txbufstatus_out out 1 0 std_logic_vector xilinx_anylanguagesynthesis false gt0_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt1_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt2_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt3_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt4_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt5_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt6_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt7_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt8_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt9_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt10_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt11_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt12_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt13_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt14_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt15_rxbufstatus_out out 2 0 std_logic_vector xilinx_anylanguagesynthesis false gt0_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt1_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt2_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt3_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt4_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt5_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt6_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt7_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt8_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt9_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt10_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt11_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt12_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt13_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt14_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt15_rxpmaresetdone_out out std_logic xilinx_anylanguagesynthesis false gt_cplllock out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gt_rxdfelpmreset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxlpmen in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxcdrovrden in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxcdrhold in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_eyescanreset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_eyescandataerror out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gt_eyescantrigger in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxrate in 11 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxcommadet out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gt_rxdisperr out 7 0 std_logic_vector xilinx_anylanguagesynthesis false gt_rxnotintable out 7 0 std_logic_vector xilinx_anylanguagesynthesis false gt_rxprbserr out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gt_rxprbssel in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxprbscntreset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxpcsreset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxpmareset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxbufreset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxresetdone out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gt_rxbufstatus out 11 0 std_logic_vector xilinx_anylanguagesynthesis false gt_powergood out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gt_dmonitorout out 67 0 std_logic_vector xilinx_anylanguagesynthesis false gt_txresetdone out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gt_txbufstatus out 7 0 std_logic_vector xilinx_anylanguagesynthesis false gt_txprbsforceerr in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txprbssel in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txpcsreset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txinhibit in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_pcsrsvdin in 63 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txpmareset in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txpostcursor in 19 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txprecursor in 19 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txdiffctrl in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_txpolarity in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gt_rxpmaresetdone out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gttxresetdone_in in std_logic xilinx_anylanguagesynthesis 0 false gtrxresetdone_in in std_logic xilinx_anylanguagesynthesis 0 false rxdata_in in 63 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxnotintable_in in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxdisperr_in in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxchariscomma_in in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxcharisk_in in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxrealign_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxbuferr_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false txbuferr_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false chbonddone_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false txoutclk_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false txlock_in in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxfsm_datavalid_out out std_logic xilinx_anylanguagesynthesis false rxpolarity_out out 3 0 std_logic_vector xilinx_anylanguagesynthesis false rxreset_out out 3 0 std_logic_vector xilinx_anylanguagesynthesis false txcharisk_out out 7 0 std_logic_vector xilinx_anylanguagesynthesis false txdata_out out 63 0 std_logic_vector xilinx_anylanguagesynthesis false txreset_out out 3 0 std_logic_vector xilinx_anylanguagesynthesis false gtrxreset_out out std_logic xilinx_anylanguagesynthesis false enacommaalign_out out 3 0 std_logic_vector xilinx_anylanguagesynthesis false enchansync_out out std_logic xilinx_anylanguagesynthesis false component_name aurora_rx_1q channel_enable X0Y0 C_REFCLK_LOC_P BL8 C_REFCLK_LOC_N BL7 c_column_used right c_ucolumn_used right c_family virtex7 c_device xc7vx550t c_row_used None c_xpackage ffg1927 c_xspeedgrade -2 c_aurora_lanes 4 c_lane_width 2 C_active_transceiverquads 1 C_START_QUAD X0Y0 C_START_LANE X0Y0 C_REFCLK_SOURCE none interface_mode Framing c_stream false dataflow_config RX-only_Simplex backchannel_mode Timer c_simplex true c_simplex_mode RX flow_mode UFC c_nfc false c_nfc_mode IMM c_ufc true c_example_simulation false c_gtwiz_out false c_line_rate 64130 cc_line_rate 6.413 c_refclk_frequency 160325 cc_refclk_frequency 160.325 c_init_clk 125.0 drp_freq 125.0 c_gt_loc_1 X c_gt_loc_2 X c_gt_loc_3 X c_gt_loc_4 X c_gt_loc_5 X c_gt_loc_6 X c_gt_loc_7 X c_gt_loc_8 X c_gt_loc_9 X c_gt_loc_10 X c_gt_loc_11 X c_gt_loc_12 X c_gt_loc_13 1 c_gt_loc_14 2 c_gt_loc_15 3 c_gt_loc_16 4 c_gt_loc_17 X c_gt_loc_18 X c_gt_loc_19 X c_gt_loc_20 X c_gt_loc_21 X c_gt_loc_22 X c_gt_loc_23 X c_gt_loc_24 X c_gt_loc_25 X c_gt_loc_26 X c_gt_loc_27 X c_gt_loc_28 X c_gt_loc_29 X c_gt_loc_30 X c_gt_loc_31 X c_gt_loc_32 X c_gt_loc_33 X c_gt_loc_34 X c_gt_loc_35 X c_gt_loc_36 X c_gt_loc_37 X c_gt_loc_38 X c_gt_loc_39 X c_gt_loc_40 X c_gt_loc_41 X c_gt_loc_42 X c_gt_loc_43 X c_gt_loc_44 X c_gt_loc_45 X c_gt_loc_46 X c_gt_loc_47 X c_gt_loc_48 X c_gt_clock_1 GTHQ3 c_gt_clock_2 None c_use_scrambler false c_use_chipscope true c_drp_if true transceivercontrol false c_use_crc false supportlevel false c_use_byteswap true c_cpll_fbdiv 4 c_cpll_fbdiv_45 5 c_cpll_refclk_div 1 c_rxoutdiv 1 c_txoutdiv 1 user_interface AXI_4_Streaming c_ufcbuswidthselect 64 c_ufcrembuswidthselect 3 c_ufcstrbbuswidthselect 8 c_rembuswidthselect 3 isv7gth true gtquadcnt 1 port7dmonitorout 14 is_7series true SINGLEEND_INITCLK false SINGLEEND_GTREFCLK false C_DOUBLE_GTRXRESET false C_DOCCPORT_ENABLE false is_board None USDRPADDR_WIDTH 8 USDMON_WIDTH 16 TXDIFFCTRL_WIDTH 3 ins_loss_nyq 14 rx_eq_mode AUTO rx_coupling AC rx_termination PROGRAMMABLE rx_termination_prog_value 800 rx_ppm_offset 200 choice_list_08d477db 128.260 160.325 200.406 213.766 256.520 267.208 320.650 400.812 427.533 534.416 641.300 801.625 choice_list_0b665932 Framing Streaming choice_list_0be33969 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 choice_list_110bd32e 2 4 choice_list_22d9ca92 1 2 3 4 X choice_list_24871ac1 AC DC choice_list_28e29f26 GTHQ3 choice_list_4d962a2a none choice_list_57c4a416 None None choice_list_6f5507b7 None choice_list_78a13d1a Sidebands Timer choice_list_7985d6f3 3 4 X choice_list_8d492e3d X 1 2 3 4 choice_list_949abb3f X0Y0 choice_list_9ee63157 None UFC choice_list_a20f248a 2 3 4 X choice_list_adcb0610 left right choice_list_ddf7a1a5 X choice_list_f490bbca 260 260 306 345 388 430 520 563 610 700 800 830 875 915 960 1030 choice_list_f8520c83 4 X choice_pairs_1040277f AVTT FLOAT GND PROGRAMMABLE choice_pairs_27553a04 1 0 choice_pairs_8ad3042a Duplex RX-only_Simplex TX-only_Simplex choice_pairs_aa541099 AUTO DFE LPM xilinx_anylanguagesynthesis_view_fileset aurora_rx_1q/src/aurora_rx_1q_aurora_pkg.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_reset_logic.vhd vhdlSource aurora_rx_1q_core.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_axi_to_ll.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_chbond_count_dec.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_hotplug.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_left_align_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_left_align_mux.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ll_to_axi.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_output_mux.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_output_switch_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_aurora_lane_simplex.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_channel_err_detect_simplex.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_channel_init_sm_simplex.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_err_detect_simplex.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_global_logic_simplex.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_lane_init_sm_simplex.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_ll_deframer.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_ll_pdu_datapath.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_ll_ufc_datapath.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_rx_ll.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_sideband_output.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_storage_ce_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_storage_count_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_storage_mux.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_storage_switch_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_sym_dec.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_cdc_sync.vhd vhdlSource aurora_rx_1q/gt/aurora_rx_1q_tx_startup_fsm.vhd vhdlSource aurora_rx_1q/gt/aurora_rx_1q_rx_startup_fsm.vhd vhdlSource aurora_rx_1q/gt/aurora_rx_1q_gt.vhd vhdlSource aurora_rx_1q/gt/aurora_rx_1q_multi_gt.vhd vhdlSource aurora_rx_1q/gt/aurora_rx_1q_transceiver_wrapper.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_barrel_shifter_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_barrel_shifter.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_filter.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_output_mux.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_output_switch_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_sideband_output.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_storage_count_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_storage_mux.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_ufc_storage_switch_control.vhd vhdlSource aurora_rx_1q/src/aurora_rx_1q_valid_data_counter.vhd vhdlSource aurora_rx_1q_clocks.xdc xdc processing_order late aurora_rx_1q.xdc xdc aurora_rx_1q_ooc.xdc xdc USED_IN_implementation USED_IN_out_of_context USED_IN_synthesis xilinx_vhdlsynthesiswrapper_view_fileset aurora_rx_1q.vhd vhdlSource xilinx_externalfiles_view_fileset aurora_rx_1q.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib aurora_rx_1q_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib aurora_rx_1q_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib aurora_rx_1q_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib aurora_rx_1q_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib Customizable multi-lane gigabit serial link implementing the Aurora 8B10B protocol Component_Name aurora_rx_1q C_active_transceiverquads 1 true C_AURORA_LANES 4 true C_LANE_WIDTH 2 true C_LINE_RATE 6.413 true C_REFCLK_FREQUENCY C Refclk Frequency 160.325 true C_INIT_CLK 125 true DRP_FREQ 125 true Dataflow_Config Dataflow Config RX-only_Simplex true Interface_Mode Framing true Flow_Mode UFC true Backchannel_mode Timer true C_COLUMN_USED right true C_UCOLUMN_USED right true C_ROW_USED None false C_GT_LOC_48 X false C_GT_LOC_47 X false C_GT_LOC_46 X false C_GT_LOC_45 X false C_GT_LOC_44 X false C_GT_LOC_43 X false C_GT_LOC_42 X false C_GT_LOC_41 X false C_GT_LOC_40 X true C_GT_LOC_39 X true C_GT_LOC_38 X true C_GT_LOC_37 X true C_GT_LOC_36 X true C_GT_LOC_35 X true C_GT_LOC_34 X true C_GT_LOC_33 X true C_GT_LOC_32 X true C_GT_LOC_31 X true C_GT_LOC_30 X true C_GT_LOC_29 X true C_GT_LOC_28 X true C_GT_LOC_27 X true C_GT_LOC_26 X true C_GT_LOC_25 X true C_GT_LOC_24 X true C_GT_LOC_23 X true C_GT_LOC_22 X true C_GT_LOC_21 X true C_GT_LOC_20 X true C_GT_LOC_19 X true C_GT_LOC_18 X true C_GT_LOC_17 X true C_GT_LOC_16 4 true C_GT_LOC_15 3 true C_GT_LOC_14 2 true C_GT_LOC_13 1 true C_GT_LOC_12 X true C_GT_LOC_11 X true C_GT_LOC_10 X true C_GT_LOC_9 X true C_GT_LOC_8 X true C_GT_LOC_7 X true C_GT_LOC_6 X true C_GT_LOC_5 X true C_GT_LOC_4 X true C_GT_LOC_3 X true C_GT_LOC_2 X true C_GT_LOC_1 X true C_GT_CLOCK_1 GTHQ3 true C_GT_CLOCK_2 None false C_USE_CHIPSCOPE true true C_START_QUAD Starting GT Quad Select the quad from which lane assignment begins X0Y0 true C_START_LANE Starting GT Lane Select the starting lane location.Lane Assignment will begin from this Lane of the Quad selected earlier. X0Y0 true C_REFCLK_SOURCE GT Refclk Selection Select a reference clock input none true SINGLEEND_INITCLK false false SINGLEEND_GTREFCLK false false C_USE_SCRAMBLER false true C_USE_CRC false true SupportLevel 0 true TransceiverControl false true C_DOUBLE_GTRXRESET false true C_DOCCPORT_ENABLE false false C_EXAMPLE_SIMULATION false true C_USE_BYTESWAP true true CHANNEL_ENABLE Enable channel X0Y0 false C_DRP_IF true false INS_LOSS_NYQ Insertion loss at Nyquist (dB) Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB 14 RX_EQ_MODE Equalization mode Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. AUTO RX_COUPLING Link coupling Select the link coupling AC RX_TERMINATION Termination Select the receiver termination PROGRAMMABLE RX_TERMINATION_PROG_VALUE Programmable termination voltage (mV) Select the termination voltage (in mV) when in programmable mode 800 RX_PPM_OFFSET PPM offset between receiver and transmitter Specify the PPM offset between received data and transmitted data 200 C_GTWIZ_OUT false false Aurora 8B10B 8 2019.2