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---------------------------------------------------------------------------------------------
--  AURORA RESET LOGIC
--
--
--  Description: RESET logic using Debouncer
--
--        

library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_1164.all;

-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on

entity aurora_rx_4l_64b_RESET_LOGIC is
    port (
           RESET                  : in std_logic;
           USER_CLK               : in std_logic;
           INIT_CLK_IN            : in std_logic;
           TX_LOCK_IN             : in std_logic;
           PLL_NOT_LOCKED         : in std_logic;
           LINK_RESET_IN          : in std_logic;
           RX_RESETDONE_IN        : in std_logic;
           SYSTEM_RESET           : out std_logic
         );

end aurora_rx_4l_64b_RESET_LOGIC;

architecture MAPPED of aurora_rx_4l_64b_RESET_LOGIC is
  attribute DowngradeIPIdentifiedWarnings: string;
  attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
  attribute core_generation_info           : string;
  attribute core_generation_info of MAPPED : architecture is "aurora_rx_4l_64b,aurora_8b10b_v11_1_14,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=right,c_gt_clock_1=GTHQ2,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=4,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=1,c_gt_loc_8=2,c_gt_loc_9=3,c_lane_width=2,c_line_rate=64130,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160325,c_simplex=true,c_simplex_mode=RX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=RX-only_Simplex}";

-- Parameter Declarations --

    constant DLY : time := 1 ns;

-- Internal Register Declarations --

    signal link_reset_sync    : std_logic;
    signal link_reset_comb_r  : std_logic;
    signal tx_lock_sync       : std_logic;
    signal tx_lock_comb_r     : std_logic;
    signal gt_rxresetdone_r   : std_logic;
    signal gt_rxresetdone_r2  : std_logic;
    signal gt_rxresetdone_r3  : std_logic;
    signal tied_to_ground_i   : std_logic;     

-- Component Declarations --

  component  aurora_rx_4l_64b_cdc_sync is
    generic (
        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
                                    -- 0 is pulse synch
                                    -- 1 is level synch
                                    -- 2 is ack based level sync
        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
                                    -- 0 is reset not needed 
                                    -- 1 is reset needed 
        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
                                    -- 0 is bus input
                                    -- 1 is single bit input
        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
        C_VECTOR_WIDTH              : integer range 0 to 32 := 32                             ;
        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
            -- Vector Data witdth
    );

    port (
        prmry_aclk                  : in  std_logic                             ;               --
        prmry_resetn                : in  std_logic                             ;               --
        prmry_in                    : in  std_logic                             ;               --
        prmry_vect_in               : in  std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
        prmry_ack                   : out std_logic                             ;
                                                                                                --
        scndry_aclk                 : in  std_logic                             ;               --
        scndry_resetn               : in  std_logic                             ;               --
                                                                                                --
        -- Primary to Secondary Clock Crossing                                                  --
        scndry_out                  : out std_logic                             ;               --
                                                                                                --
        scndry_vect_out             : out std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)                           --

    );

   end component;


    component IBUFDS
        port (

                O : out std_ulogic;
                I : in std_ulogic;
                IB : in std_ulogic);

    end component;

begin

    -- Tie off top level constants.
    tied_to_ground_i     <= '0';

    -- ___________________________Debouncing circuit for GT_RESET_IN________________________

    process (USER_CLK, RX_RESETDONE_IN)
    begin
        if (RX_RESETDONE_IN = '0') then
            gt_rxresetdone_r  <= '0' after DLY;
            gt_rxresetdone_r2 <= '0' after DLY;
        elsif (USER_CLK 'event and USER_CLK = '1') then
            gt_rxresetdone_r  <= RX_RESETDONE_IN after DLY;
            gt_rxresetdone_r2 <= gt_rxresetdone_r after DLY;
        end if;
    end process;

    process(USER_CLK)
    begin
        if(USER_CLK'event and USER_CLK='1') then
            gt_rxresetdone_r3 <=  gt_rxresetdone_r2 after DLY;
        end if;
    end process;


    --This flop will pipeline wide-OR in case of multi-lane
    process(INIT_CLK_IN)
    begin
        if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
            link_reset_comb_r <=  LINK_RESET_IN after DLY;
        end if;
    end process;

      link_reset_cdc_sync : aurora_rx_4l_64b_cdc_sync
      generic map
        (
           c_cdc_type      => 1             ,   
           c_flop_input    => 1             ,  
           c_reset_state   => 0             ,  
           c_single_bit    => 1             ,  
           c_vector_width  => 2             ,  
           c_mtbf_stages   => 3                
         )
      port map
         (
           prmry_aclk      => INIT_CLK_IN        ,
           prmry_resetn    => '1'                ,
           prmry_in        => link_reset_comb_r  ,
           prmry_vect_in   => "00"               ,
           scndry_aclk     => USER_CLK           ,
           scndry_resetn   => '1'                ,
           prmry_ack       => open               ,
           scndry_out      => link_reset_sync    ,
           scndry_vect_out => open                    
          );


    --This flop will pipeline wide-OR in case of multi-lane
    process (INIT_CLK_IN)
    begin
      if (INIT_CLK_IN = '1' and INIT_CLK_IN'event) then
            tx_lock_comb_r   <=  TX_LOCK_IN after DLY;
      end if;
    end process;


      tx_lock_cdc_sync : aurora_rx_4l_64b_cdc_sync
      generic map
        (
           c_cdc_type      => 1             ,   
           c_flop_input    => 1             ,  
           c_reset_state   => 0             ,  
           c_single_bit    => 1             ,  
           c_vector_width  => 2             ,  
           c_mtbf_stages   => 3                
         )
      port map
         (
           prmry_aclk      => INIT_CLK_IN         ,
           prmry_resetn    => '1'                 ,
           prmry_in        => tx_lock_comb_r      ,
           prmry_vect_in   => "00"                ,
           scndry_aclk     => USER_CLK            ,
           scndry_resetn   => '1'                 ,
           prmry_ack       => open                ,
           scndry_out      => tx_lock_sync        ,
           scndry_vect_out => open                     
          );

process (USER_CLK)
begin
  if (USER_CLK = '1' and USER_CLK'event) then
    SYSTEM_RESET <=  (RESET or (not gt_rxresetdone_r3)) or link_reset_sync or (not tx_lock_sync);
  end if;
end process;

end MAPPED;
