-------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
-- Module aurora_rx_4l_64b_GT_WRAPPER
--------------------------------------------------------------------------------
library IEEE;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity aurora_rx_4l_64b_GT_WRAPPER is
generic
(
    QPLL_FBDIV_TOP                 : integer  := 40;
    -- Channel bond MASTER/SLAVE connection
    CHAN_BOND_MASTER : std_logic := '0';
    CHAN_BOND_SLAVE  : std_logic := '1';
    CHAN_BOND_LEVEL  : std_logic_vector := "001";
    CHAN_BOND_MASTER_LANE1 : std_logic := '1';
    CHAN_BOND_SLAVE_LANE1  : std_logic := '0';
    CHAN_BOND_LEVEL_LANE1  : std_logic_vector := "010";
    CHAN_BOND_MASTER_LANE2 : std_logic := '0';
    CHAN_BOND_SLAVE_LANE2  : std_logic := '1';
    CHAN_BOND_LEVEL_LANE2  : std_logic_vector := "001";
    CHAN_BOND_MASTER_LANE3 : std_logic := '0';
    CHAN_BOND_SLAVE_LANE3  : std_logic := '1';
    CHAN_BOND_LEVEL_LANE3  : std_logic_vector := "000";
    -- Simulation attribute
    EXAMPLE_SIMULATION  : integer :=  0;     
    SIM_GTRESET_SPEEDUP : string  :=   "FALSE"      -- Set to "TRUE" to speed up sim reset
);

port
(

---------------------- Loopback and Powerdown Ports ----------------------
LOOPBACK_IN                               : in    std_logic_vector (2 downto 0);
--------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE1 : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE2 : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE3 : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT     : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE1     : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE2     : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE3     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE1     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE2     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE3     : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT  : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE1  : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE2  : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE3  : out   std_logic_vector (1 downto 0);
----------------- Receive Ports - Channel Bonding Ports -----------------
ENCHANSYNC_IN     : in    std_logic;
ENCHANSYNC_IN_LANE1     : in    std_logic;
ENCHANSYNC_IN_LANE2     : in    std_logic;
ENCHANSYNC_IN_LANE3     : in    std_logic;
CHBONDDONE_OUT    : out   std_logic;
CHBONDDONE_OUT_LANE1    : out   std_logic;
CHBONDDONE_OUT_LANE2    : out   std_logic;
CHBONDDONE_OUT_LANE3    : out   std_logic;
----------------- Receive Ports - Clock Correction Ports -----------------
RXBUFERR_OUT      : out   std_logic;
RXBUFERR_OUT_LANE1      : out   std_logic;
RXBUFERR_OUT_LANE2      : out   std_logic;
RXBUFERR_OUT_LANE3      : out   std_logic;
------------- Receive Ports - Comma Detection and Alignment --------------
RXREALIGN_OUT     : out   std_logic;
RXREALIGN_OUT_LANE1     : out   std_logic;
RXREALIGN_OUT_LANE2     : out   std_logic;
RXREALIGN_OUT_LANE3     : out   std_logic;
ENMCOMMAALIGN_IN  : in    std_logic;
ENMCOMMAALIGN_IN_LANE1  : in    std_logic;
ENMCOMMAALIGN_IN_LANE2  : in    std_logic;
ENMCOMMAALIGN_IN_LANE3  : in    std_logic;
ENPCOMMAALIGN_IN  : in    std_logic;
ENPCOMMAALIGN_IN_LANE1  : in    std_logic;
ENPCOMMAALIGN_IN_LANE2  : in    std_logic;
ENPCOMMAALIGN_IN_LANE3  : in    std_logic;
----------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT        : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE1        : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE2        : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE3        : out   std_logic_vector (15 downto 0);
RXRESET_IN        : in    std_logic;
RXRESET_IN_LANE1        : in    std_logic;
RXRESET_IN_LANE2        : in    std_logic;
RXRESET_IN_LANE3        : in    std_logic;
RXUSRCLK_IN                               : in    std_logic;
RXUSRCLK2_IN                              : in    std_logic;
----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RX1N_IN           : in    std_logic;
RX1N_IN_LANE1           : in    std_logic;
RX1N_IN_LANE2           : in    std_logic;
RX1N_IN_LANE3           : in    std_logic;
RX1P_IN           : in    std_logic;
RX1P_IN_LANE1           : in    std_logic;
RX1P_IN_LANE2           : in    std_logic;
RX1P_IN_LANE3           : in    std_logic;
--------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY_IN     : in    std_logic;
RXPOLARITY_IN_LANE1     : in    std_logic;
RXPOLARITY_IN_LANE2     : in    std_logic;
RXPOLARITY_IN_LANE3     : in    std_logic;
------------------- Shared Ports - Tile and PLL Ports --------------------
REFCLK                                    : in    std_logic;
INIT_CLK_IN                               : in  std_logic;
PLL_NOT_LOCKED                            : in    std_logic;
GTRESET_IN                                : in    std_logic;
PLLLKDET_OUT      : out   std_logic;
PLLLKDET_OUT_LANE1      : out   std_logic;
PLLLKDET_OUT_LANE2      : out   std_logic;
PLLLKDET_OUT_LANE3      : out   std_logic;
    gt0_txresetdone_out         : out    std_logic;
    gt0_rxresetdone_out         : out    std_logic;
    gt0_rxpmaresetdone_out                      : out    std_logic;
    gt0_txbufstatus_out         : out    std_logic_vector(1 downto 0);
    gt0_rxbufstatus_out         : out    std_logic_vector(2 downto 0);
    gt1_txresetdone_out         : out    std_logic;
    gt1_rxresetdone_out         : out    std_logic;
    gt1_rxpmaresetdone_out                      : out    std_logic;
    gt1_txbufstatus_out         : out    std_logic_vector(1 downto 0);
    gt1_rxbufstatus_out         : out    std_logic_vector(2 downto 0);
    gt2_txresetdone_out         : out    std_logic;
    gt2_rxresetdone_out         : out    std_logic;
    gt2_rxpmaresetdone_out                      : out    std_logic;
    gt2_txbufstatus_out         : out    std_logic_vector(1 downto 0);
    gt2_rxbufstatus_out         : out    std_logic_vector(2 downto 0);
    gt3_txresetdone_out         : out    std_logic;
    gt3_rxresetdone_out         : out    std_logic;
    gt3_rxpmaresetdone_out                      : out    std_logic;
    gt3_txbufstatus_out         : out    std_logic_vector(1 downto 0);
    gt3_rxbufstatus_out         : out    std_logic_vector(2 downto 0);
TX_RESETDONE_OUT                          : out    std_logic;
RX_RESETDONE_OUT                          : out    std_logic;
-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARISK_IN      : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE1      : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE2      : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE3      : in    std_logic_vector (1 downto 0);
---------------- Transmit Ports - TX Data Path interface -----------------
TXDATA_IN         : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE1         : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE2         : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE3         : in    std_logic_vector (15 downto 0);
TXOUTCLK1_OUT     : out   std_logic;
TXOUTCLK1_OUT_LANE1     : out   std_logic;
TXOUTCLK1_OUT_LANE2     : out   std_logic;
TXOUTCLK1_OUT_LANE3     : out   std_logic;
TXRESET_IN        : in    std_logic;
TXRESET_IN_LANE1        : in    std_logic;
TXRESET_IN_LANE2        : in    std_logic;
TXRESET_IN_LANE3        : in    std_logic;
TXUSRCLK_IN                               : in    std_logic;  
TXUSRCLK2_IN                              : in    std_logic;
TXBUFERR_OUT      : out   std_logic;
TXBUFERR_OUT_LANE1      : out   std_logic;
TXBUFERR_OUT_LANE2      : out   std_logic;
TXBUFERR_OUT_LANE3      : out   std_logic;
------------- Transmit Ports - TX Driver and OOB signalling --------------
TX1N_OUT          : out   std_logic;
TX1N_OUT_LANE1          : out   std_logic;
TX1N_OUT_LANE2          : out   std_logic;
TX1N_OUT_LANE3          : out   std_logic;
TX1P_OUT          : out   std_logic;
TX1P_OUT_LANE1          : out   std_logic;
TX1P_OUT_LANE2          : out   std_logic;
TX1P_OUT_LANE3          : out   std_logic;
---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN                               : in   std_logic;
DRPDI_IN                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
DRPEN_IN                                : in   std_logic;
DRPRDY_OUT                              : out  std_logic;
DRPWE_IN                                : in   std_logic;
DRPADDR_IN_LANE1                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE1                               : in   std_logic;
DRPDI_IN_LANE1                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE1                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE1                                : in   std_logic;
DRPRDY_OUT_LANE1                              : out  std_logic;
DRPWE_IN_LANE1                                : in   std_logic;
DRPADDR_IN_LANE2                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE2                               : in   std_logic;
DRPDI_IN_LANE2                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE2                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE2                                : in   std_logic;
DRPRDY_OUT_LANE2                              : out  std_logic;
DRPWE_IN_LANE2                                : in   std_logic;
DRPADDR_IN_LANE3                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE3                               : in   std_logic;
DRPDI_IN_LANE3                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE3                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE3                                : in   std_logic;
DRPRDY_OUT_LANE3                              : out  std_logic;
DRPWE_IN_LANE3                                : in   std_logic;
--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
    ------------------------- Common Block - QPLL Ports ------------------------
      gt1_qplllock_in       :  in  std_logic;
      gt1_qpllrefclklost_in :  in  std_logic;
      gt1_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad2_in    : in  std_logic;
   gt_qpllrefclk_quad2_in : in  std_logic;
   gt_qpllclk_quad3_in    : in  std_logic;
   gt_qpllrefclk_quad3_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}


    gt0_rxlpmen_in                              : in   std_logic;
    gt0_rxcdrovrden_in                          : in   std_logic;
    gt0_rxdfelpmreset_in                        : in   std_logic;
    gt0_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt0_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt0_rxcdrhold_in                            : in   std_logic;

    gt0_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt0_eyescandataerror_out                    : out  std_logic;
    gt0_eyescantrigger_in                       : in   std_logic;
    gt0_rxbyteisaligned_out                     : out  std_logic;
    gt0_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt0_rxprbserr_out                           : out  std_logic;
    gt0_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt0_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt0_rxpcsreset_in                           : in   std_logic;
    gt0_rxpmareset_in                           : in   std_logic;
    gt0_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt0_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt0_txprbsforceerr_in                       : in   std_logic;
    gt0_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt0_txpcsreset_in                           : in   std_logic;
    gt0_txinhibit_in                            : in   std_logic;
    gt0_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt0_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt0_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt0_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt0_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt0_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt0_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt0_txpolarity_in                           : in   std_logic;

    gt1_rxlpmen_in                              : in   std_logic;
    gt1_rxcdrovrden_in                          : in   std_logic;
    gt1_rxdfelpmreset_in                        : in   std_logic;
    gt1_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt1_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt1_rxcdrhold_in                            : in   std_logic;

    gt1_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt1_eyescandataerror_out                    : out  std_logic;
    gt1_eyescantrigger_in                       : in   std_logic;
    gt1_rxbyteisaligned_out                     : out  std_logic;
    gt1_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt1_rxprbserr_out                           : out  std_logic;
    gt1_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt1_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt1_rxpcsreset_in                           : in   std_logic;
    gt1_rxpmareset_in                           : in   std_logic;
    gt1_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt1_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt1_txprbsforceerr_in                       : in   std_logic;
    gt1_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt1_txpcsreset_in                           : in   std_logic;
    gt1_txinhibit_in                            : in   std_logic;
    gt1_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt1_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt1_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt1_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt1_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt1_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt1_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt1_txpolarity_in                           : in   std_logic;

    gt2_rxlpmen_in                              : in   std_logic;
    gt2_rxcdrovrden_in                          : in   std_logic;
    gt2_rxdfelpmreset_in                        : in   std_logic;
    gt2_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt2_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt2_rxcdrhold_in                            : in   std_logic;

    gt2_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt2_eyescandataerror_out                    : out  std_logic;
    gt2_eyescantrigger_in                       : in   std_logic;
    gt2_rxbyteisaligned_out                     : out  std_logic;
    gt2_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt2_rxprbserr_out                           : out  std_logic;
    gt2_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt2_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt2_rxpcsreset_in                           : in   std_logic;
    gt2_rxpmareset_in                           : in   std_logic;
    gt2_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt2_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt2_txprbsforceerr_in                       : in   std_logic;
    gt2_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt2_txpcsreset_in                           : in   std_logic;
    gt2_txinhibit_in                            : in   std_logic;
    gt2_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt2_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt2_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt2_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt2_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt2_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt2_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt2_txpolarity_in                           : in   std_logic;

    gt3_rxlpmen_in                              : in   std_logic;
    gt3_rxcdrovrden_in                          : in   std_logic;
    gt3_rxdfelpmreset_in                        : in   std_logic;
    gt3_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt3_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt3_rxcdrhold_in                            : in   std_logic;

    gt3_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt3_eyescandataerror_out                    : out  std_logic;
    gt3_eyescantrigger_in                       : in   std_logic;
    gt3_rxbyteisaligned_out                     : out  std_logic;
    gt3_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt3_rxprbserr_out                           : out  std_logic;
    gt3_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt3_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt3_rxpcsreset_in                           : in   std_logic;
    gt3_rxpmareset_in                           : in   std_logic;
    gt3_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt3_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt3_txprbsforceerr_in                       : in   std_logic;
    gt3_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt3_txpcsreset_in                           : in   std_logic;
    gt3_txinhibit_in                            : in   std_logic;
    gt3_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt3_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt3_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt3_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt3_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt3_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt3_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt3_txpolarity_in                           : in   std_logic;

GTRXRESET_IN                            : in    std_logic;
LINK_RESET_IN                           : in    std_logic;
RXFSM_DATA_VALID                        : in    std_logic; 
POWERDOWN_IN                            : in    std_logic
);

end aurora_rx_4l_64b_GT_WRAPPER;


architecture MAPPED of aurora_rx_4l_64b_GT_WRAPPER is
  attribute DowngradeIPIdentifiedWarnings: string;
  attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
  attribute core_generation_info               : string;
attribute core_generation_info of MAPPED : architecture is "aurora_rx_4l_64b,aurora_8b10b_v11_1_14,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=right,c_gt_clock_1=GTHQ2,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=4,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=1,c_gt_loc_8=2,c_gt_loc_9=3,c_lane_width=2,c_line_rate=64130,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160325,c_simplex=true,c_simplex_mode=RX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=RX-only_Simplex}";

    -- Parameter Declarations --
    constant DLY : time := 1 ns;

  component  aurora_rx_4l_64b_cdc_sync is
    generic (
        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
                                    -- 0 is pulse synch
                                    -- 1 is level synch
                                    -- 2 is ack based level sync
        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
                                    -- 0 is reset not needed 
                                    -- 1 is reset needed 
        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
                                    -- 0 is bus input
                                    -- 1 is single bit input
        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
        C_VECTOR_WIDTH              : integer range 0 to 32 := 32                             ;
        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
            -- Vector Data witdth
    );

    port (
        prmry_aclk                  : in  std_logic                             ;               --
        prmry_resetn                : in  std_logic                             ;               --
        prmry_in                    : in  std_logic                             ;               --
        prmry_vect_in               : in  std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
        prmry_ack                   : out std_logic                             ;
                                                                                                --
        scndry_aclk                 : in  std_logic                             ;               --
        scndry_resetn               : in  std_logic                             ;               --
                                                                                                --
        -- Primary to Secondary Clock Crossing                                                  --
        scndry_out                  : out std_logic                             ;               --
                                                                                                --
        scndry_vect_out             : out std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)                           --

    );

   end component;

--***************************** Compopnent Declaration ****************************

component aurora_rx_4l_64b_tx_startup_fsm
  Generic(
           GT_TYPE                  : string := "GTX";
           STABLE_CLOCK_PERIOD      : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
            TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
           RX_QPLL_USED             : boolean := False;           -- share these two generic values
           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
                                                                  -- is enough. For single-lane applications the automatic alignment is 
                                                                  -- sufficient              
         );     
    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
                                                                  --or reference-clock present at startup.
           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
           TXRESETDONE              : in  STD_LOGIC;      
           MMCM_LOCK                : in  STD_LOGIC;      
           GTTXRESET                : out STD_LOGIC:='0';      
           MMCM_RESET               : out STD_LOGIC:='0';      
           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
           TX_FSM_RESET_DONE        : out STD_LOGIC:='0';        --Reset-sequence has sucessfully been finished.
           TXUSERRDY                : out STD_LOGIC:='0';
           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
           PHALIGNMENT_DONE         : in  STD_LOGIC;
           
           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
                                                            -- Retries it took to get the transceiver up and running
           );
end component;

component aurora_rx_4l_64b_rx_startup_fsm
  Generic(
           EXAMPLE_SIMULATION       : integer :=  0;     
           EQ_MODE                  : string := "DFE";
           GT_TYPE                  : string := "GTX";
           STABLE_CLOCK_PERIOD      : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
           RX_QPLL_USED             : boolean := False;           -- share these two generic values
           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
                                                                  -- is enough. For single-lane applications the automatic alignment is 
                                                                  -- sufficient                         
         );     
    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
                                                            --or reference-clock present at startup.
           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
           RXPMARESETDONE           : in  STD_LOGIC;        
           RXOUTCLK                 : in  STD_LOGIC;    
    
           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
           RXRESETDONE              : in  STD_LOGIC;
           MMCM_LOCK                : in  STD_LOGIC;
           RECCLK_STABLE            : in  STD_LOGIC;
           RECCLK_MONITOR_RESTART   : in  STD_LOGIC;
           DATA_VALID               : in  STD_LOGIC;
           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;
           GTRXRESET                : out STD_LOGIC:='0';
           MMCM_RESET               : out STD_LOGIC:='0';
           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
           RX_FSM_RESET_DONE        : out STD_LOGIC:='0';  --Reset-sequence has sucessfully been finished.
           RXUSERRDY                : out STD_LOGIC:='0';
           RUN_PHALIGNMENT          : out STD_LOGIC;
           PHALIGNMENT_DONE         : in  STD_LOGIC; 
           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
           RXDFEAGCHOLD             : out STD_LOGIC;
           RXDFELFHOLD              : out STD_LOGIC;
           RXLPMLFHOLD              : out STD_LOGIC;
           RXLPMHFHOLD              : out STD_LOGIC;
           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
                                                            -- Retries it took to get the transceiver up and running
           );
end component;



component aurora_rx_4l_64b_multi_gt is
generic
(
    QPLL_FBDIV_TOP                 : integer  := 40;

    -- Simulation attributes
    WRAPPER_SIM_GTRESET_SPEEDUP    : string   := "FALSE" -- Set to "TRUE" to speed up sim reset
);
port
(
--____________________________COMMON PORTS ,_______________________________{
   gt_qpllclk_quad2_i    : in  std_logic;
   gt_qpllrefclk_quad2_i : in  std_logic;
   gt_qpllclk_quad3_i    : in  std_logic;
   gt_qpllrefclk_quad3_i : in  std_logic;
--____________________________COMMON PORTS _______________________________}


    --_________________________________________________________________________
    --_________________________________________________________________________
    --GT0 
    --____________________________CHANNEL PORTS________________________________
    ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
    GT0_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
    GT0_DRPCLK_IN                           : in   std_logic;
    GT0_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
    GT0_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
    GT0_DRPEN_IN                            : in   std_logic;
    GT0_DRPRDY_OUT                          : out  std_logic;
    GT0_DRPWE_IN                            : in   std_logic;
    ------------------------- Channel - Ref Clock Ports ------------------------
    GT0_GTREFCLK0_IN                        : in   std_logic;
    -------------------------------- Channel PLL -------------------------------
    GT0_CPLLFBCLKLOST_OUT                   : out  std_logic;
    GT0_CPLLLOCK_OUT                        : out  std_logic;
    GT0_CPLLLOCKDETCLK_IN                   : in   std_logic;
    GT0_CPLLREFCLKLOST_OUT                  : out  std_logic;
    GT0_CPLLRESET_IN                        : in   std_logic;
    ------------------------ Loopback and Powerdown Ports ----------------------
    GT0_LOOPBACK_IN                         : in   std_logic_vector(2 downto 0);
    GT0_RXPD_IN                             : in   std_logic_vector(1 downto 0);
    GT0_TXPD_IN                             : in   std_logic_vector(1 downto 0);
    ------------------------------- Receive Ports ------------------------------
    GT0_eyescanreset_in                     : in   std_logic;
    GT0_RXUSERRDY_IN                        : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    GT0_eyescandataerror_out                : out  std_logic;
    GT0_eyescantrigger_in                   : in   std_logic;
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
    GT0_RXCHARISCOMMA_OUT                   : out  std_logic_vector(1 downto 0);
    GT0_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
    GT0_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
    GT0_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
    ------------------- Receive Ports - Pattern Checker Ports ------------------
    GT0_rxprbserr_out                       : out  std_logic;
    GT0_rxprbssel_in                        : in   std_logic_vector(2 downto 0);
    ------------------- Receive Ports - Pattern Checker ports ------------------
    GT0_rxprbscntreset_in                   : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports ------------------
    GT0_RXCHANBONDSEQ_OUT                   : out  std_logic;
    GT0_RXCHBONDEN_IN                       : in   std_logic;
    GT0_RXCHBONDI_IN                        : in   std_logic_vector(4 downto 0);
    GT0_RXCHBONDLEVEL_IN                    : in   std_logic_vector(2 downto 0);
    GT0_RXCHBONDMASTER_IN                   : in   std_logic;
    GT0_RXCHBONDO_OUT                       : out  std_logic_vector(4 downto 0);
    GT0_RXCHBONDSLAVE_IN                    : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports  -----------------
    GT0_RXCHANISALIGNED_OUT                 : out  std_logic;
    GT0_RXCHANREALIGN_OUT                   : out  std_logic;
    ------------------- Receive Ports - Clock Correction Ports -----------------
    GT0_RXCLKCORCNT_OUT                     : out  std_logic_vector(1 downto 0);
    --------------- Receive Ports - Comma Detection and Alignment --------------
    GT0_rxbyteisaligned_out                 : out  std_logic;
    GT0_RXBYTEREALIGN_OUT                   : out  std_logic;
    GT0_rxcommadet_out                      : out  std_logic;
    GT0_RXMCOMMAALIGNEN_IN                  : in   std_logic;
    GT0_RXPCOMMAALIGNEN_IN                  : in   std_logic;
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT0_RXDFEAGCHOLD_IN                     : in   std_logic;
    GT0_RXDFELFHOLD_IN                      : in   std_logic;
    GT0_rxdfelpmreset_in                    : in   std_logic;
    GT0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
    GT0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
    ------------------- Receive Ports - RX Data Path interface -----------------
    GT0_GTRXRESET_IN                        : in   std_logic;
    GT0_RXPCSRESET_IN                       : in   std_logic;
    GT0_RXPMARESET_IN                       : in   std_logic;
    GT0_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
    GT0_RXOUTCLK_OUT                        : out  std_logic;
    GT0_RXUSRCLK_IN                         : in   std_logic;
    GT0_RXUSRCLK2_IN                        : in   std_logic;
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    GT0_GTHRXN_IN                           : in   std_logic;
    GT0_GTHRXP_IN                           : in   std_logic;
    GT0_RXCDRLOCK_OUT                       : out  std_logic;
    gt0_rxpmaresetdone_out                  : out  std_logic;
    GT0_dmonitorout_out                     : out  std_logic_vector(14 downto 0);
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    GT0_rxbufreset_in                       : in   std_logic;
    GT0_RXBUFSTATUS_OUT                     : out  std_logic_vector(2 downto 0);
    ------------------------ Receive Ports - RX PLL Ports ----------------------
    GT0_RXRESETDONE_OUT                     : out  std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    GT0_txpostcursor_in                     : in   std_logic_vector(4 downto 0);
    GT0_txprecursor_in                      : in   std_logic_vector(4 downto 0);
    -------------------- Receive Ports - RX Margin Analysis ports ----------------
    GT0_rxlpmen_in                          : in   std_logic;
    GT0_rxcdrovrden_in                      : in   std_logic;
    GT0_rxcdrhold_in                        : in   std_logic;
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
    GT0_RXPOLARITY_IN                       : in   std_logic;
    ------------------------------- Transmit Ports -----------------------------
    GT0_TXUSERRDY_IN                        : in   std_logic;
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    GT0_txchardispmode_in                   : in   std_logic_vector(1 downto 0);
    GT0_txchardispval_in                    : in   std_logic_vector(1 downto 0);
    GT0_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
    ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
    GT0_TXBUFSTATUS_OUT                     : out  std_logic_vector(1 downto 0);
    ------------------ Transmit Ports - TX Data Path interface -----------------
    GT0_GTTXRESET_IN                        : in   std_logic;
    GT0_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
    GT0_TXOUTCLK_OUT                        : out  std_logic;
    GT0_TXOUTCLKFABRIC_OUT                  : out  std_logic;
    GT0_TXOUTCLKPCS_OUT                     : out  std_logic;
    GT0_TXUSRCLK_IN                         : in   std_logic;
    GT0_TXUSRCLK2_IN                        : in   std_logic;
    --------------------- Transmit Ports - PCI Express Ports -------------------
    GT0_txelecidle_in                       : in   std_logic;
    ------------------ Transmit Ports - Pattern Generator Ports ----------------
    GT0_txprbsforceerr_in                   : in   std_logic;
    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
    GT0_GTHTXN_OUT                          : out  std_logic;
    GT0_GTHTXP_OUT                          : out  std_logic;
    GT0_txdiffctrl_in                       : in   std_logic_vector(3 downto 0);
    GT0_txmaincursor_in                     : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    GT0_txpolarity_in                       : in   std_logic;
    ------------------ Transmit Ports - pattern Generator Ports ----------------
    GT0_txprbssel_in                        : in   std_logic_vector(2 downto 0);
    ----------------------- Transmit Ports - TX PLL Ports ----------------------
    GT0_txpcsreset_in                       : in   std_logic;
    GT0_txinhibit_in                        : in   std_logic;
    GT0_txpmareset_in                       : in   std_logic;
    GT0_TXRESETDONE_OUT                     : out  std_logic;

    --_________________________________________________________________________
    --_________________________________________________________________________
    --GT1 
    --____________________________CHANNEL PORTS________________________________
    ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
    GT1_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
    GT1_DRPCLK_IN                           : in   std_logic;
    GT1_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
    GT1_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
    GT1_DRPEN_IN                            : in   std_logic;
    GT1_DRPRDY_OUT                          : out  std_logic;
    GT1_DRPWE_IN                            : in   std_logic;
    ------------------------- Channel - Ref Clock Ports ------------------------
    GT1_GTREFCLK0_IN                        : in   std_logic;
    -------------------------------- Channel PLL -------------------------------
    GT1_CPLLFBCLKLOST_OUT                   : out  std_logic;
    GT1_CPLLLOCK_OUT                        : out  std_logic;
    GT1_CPLLLOCKDETCLK_IN                   : in   std_logic;
    GT1_CPLLREFCLKLOST_OUT                  : out  std_logic;
    GT1_CPLLRESET_IN                        : in   std_logic;
    ------------------------ Loopback and Powerdown Ports ----------------------
    GT1_LOOPBACK_IN                         : in   std_logic_vector(2 downto 0);
    GT1_RXPD_IN                             : in   std_logic_vector(1 downto 0);
    GT1_TXPD_IN                             : in   std_logic_vector(1 downto 0);
    ------------------------------- Receive Ports ------------------------------
    GT1_eyescanreset_in                     : in   std_logic;
    GT1_RXUSERRDY_IN                        : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    GT1_eyescandataerror_out                : out  std_logic;
    GT1_eyescantrigger_in                   : in   std_logic;
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
    GT1_RXCHARISCOMMA_OUT                   : out  std_logic_vector(1 downto 0);
    GT1_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
    GT1_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
    GT1_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
    ------------------- Receive Ports - Pattern Checker Ports ------------------
    GT1_rxprbserr_out                       : out  std_logic;
    GT1_rxprbssel_in                        : in   std_logic_vector(2 downto 0);
    ------------------- Receive Ports - Pattern Checker ports ------------------
    GT1_rxprbscntreset_in                   : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports ------------------
    GT1_RXCHANBONDSEQ_OUT                   : out  std_logic;
    GT1_RXCHBONDEN_IN                       : in   std_logic;
    GT1_RXCHBONDI_IN                        : in   std_logic_vector(4 downto 0);
    GT1_RXCHBONDLEVEL_IN                    : in   std_logic_vector(2 downto 0);
    GT1_RXCHBONDMASTER_IN                   : in   std_logic;
    GT1_RXCHBONDO_OUT                       : out  std_logic_vector(4 downto 0);
    GT1_RXCHBONDSLAVE_IN                    : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports  -----------------
    GT1_RXCHANISALIGNED_OUT                 : out  std_logic;
    GT1_RXCHANREALIGN_OUT                   : out  std_logic;
    ------------------- Receive Ports - Clock Correction Ports -----------------
    GT1_RXCLKCORCNT_OUT                     : out  std_logic_vector(1 downto 0);
    --------------- Receive Ports - Comma Detection and Alignment --------------
    GT1_rxbyteisaligned_out                 : out  std_logic;
    GT1_RXBYTEREALIGN_OUT                   : out  std_logic;
    GT1_rxcommadet_out                      : out  std_logic;
    GT1_RXMCOMMAALIGNEN_IN                  : in   std_logic;
    GT1_RXPCOMMAALIGNEN_IN                  : in   std_logic;
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT1_RXDFEAGCHOLD_IN                     : in   std_logic;
    GT1_RXDFELFHOLD_IN                      : in   std_logic;
    GT1_rxdfelpmreset_in                    : in   std_logic;
    GT1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
    GT1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
    ------------------- Receive Ports - RX Data Path interface -----------------
    GT1_GTRXRESET_IN                        : in   std_logic;
    GT1_RXPCSRESET_IN                       : in   std_logic;
    GT1_RXPMARESET_IN                       : in   std_logic;
    GT1_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
    GT1_RXOUTCLK_OUT                        : out  std_logic;
    GT1_RXUSRCLK_IN                         : in   std_logic;
    GT1_RXUSRCLK2_IN                        : in   std_logic;
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    GT1_GTHRXN_IN                           : in   std_logic;
    GT1_GTHRXP_IN                           : in   std_logic;
    GT1_RXCDRLOCK_OUT                       : out  std_logic;
    gt1_rxpmaresetdone_out                  : out  std_logic;
    GT1_dmonitorout_out                     : out  std_logic_vector(14 downto 0);
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    GT1_rxbufreset_in                       : in   std_logic;
    GT1_RXBUFSTATUS_OUT                     : out  std_logic_vector(2 downto 0);
    ------------------------ Receive Ports - RX PLL Ports ----------------------
    GT1_RXRESETDONE_OUT                     : out  std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    GT1_txpostcursor_in                     : in   std_logic_vector(4 downto 0);
    GT1_txprecursor_in                      : in   std_logic_vector(4 downto 0);
    -------------------- Receive Ports - RX Margin Analysis ports ----------------
    GT1_rxlpmen_in                          : in   std_logic;
    GT1_rxcdrovrden_in                      : in   std_logic;
    GT1_rxcdrhold_in                        : in   std_logic;
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
    GT1_RXPOLARITY_IN                       : in   std_logic;
    ------------------------------- Transmit Ports -----------------------------
    GT1_TXUSERRDY_IN                        : in   std_logic;
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    GT1_txchardispmode_in                   : in   std_logic_vector(1 downto 0);
    GT1_txchardispval_in                    : in   std_logic_vector(1 downto 0);
    GT1_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
    ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
    GT1_TXBUFSTATUS_OUT                     : out  std_logic_vector(1 downto 0);
    ------------------ Transmit Ports - TX Data Path interface -----------------
    GT1_GTTXRESET_IN                        : in   std_logic;
    GT1_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
    GT1_TXOUTCLK_OUT                        : out  std_logic;
    GT1_TXOUTCLKFABRIC_OUT                  : out  std_logic;
    GT1_TXOUTCLKPCS_OUT                     : out  std_logic;
    GT1_TXUSRCLK_IN                         : in   std_logic;
    GT1_TXUSRCLK2_IN                        : in   std_logic;
    --------------------- Transmit Ports - PCI Express Ports -------------------
    GT1_txelecidle_in                       : in   std_logic;
    ------------------ Transmit Ports - Pattern Generator Ports ----------------
    GT1_txprbsforceerr_in                   : in   std_logic;
    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
    GT1_GTHTXN_OUT                          : out  std_logic;
    GT1_GTHTXP_OUT                          : out  std_logic;
    GT1_txdiffctrl_in                       : in   std_logic_vector(3 downto 0);
    GT1_txmaincursor_in                     : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    GT1_txpolarity_in                       : in   std_logic;
    ------------------ Transmit Ports - pattern Generator Ports ----------------
    GT1_txprbssel_in                        : in   std_logic_vector(2 downto 0);
    ----------------------- Transmit Ports - TX PLL Ports ----------------------
    GT1_txpcsreset_in                       : in   std_logic;
    GT1_txinhibit_in                        : in   std_logic;
    GT1_txpmareset_in                       : in   std_logic;
    GT1_TXRESETDONE_OUT                     : out  std_logic;

    --_________________________________________________________________________
    --_________________________________________________________________________
    --GT2 
    --____________________________CHANNEL PORTS________________________________
    ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
    GT2_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
    GT2_DRPCLK_IN                           : in   std_logic;
    GT2_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
    GT2_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
    GT2_DRPEN_IN                            : in   std_logic;
    GT2_DRPRDY_OUT                          : out  std_logic;
    GT2_DRPWE_IN                            : in   std_logic;
    ------------------------- Channel - Ref Clock Ports ------------------------
    GT2_GTREFCLK0_IN                        : in   std_logic;
    -------------------------------- Channel PLL -------------------------------
    GT2_CPLLFBCLKLOST_OUT                   : out  std_logic;
    GT2_CPLLLOCK_OUT                        : out  std_logic;
    GT2_CPLLLOCKDETCLK_IN                   : in   std_logic;
    GT2_CPLLREFCLKLOST_OUT                  : out  std_logic;
    GT2_CPLLRESET_IN                        : in   std_logic;
    ------------------------ Loopback and Powerdown Ports ----------------------
    GT2_LOOPBACK_IN                         : in   std_logic_vector(2 downto 0);
    GT2_RXPD_IN                             : in   std_logic_vector(1 downto 0);
    GT2_TXPD_IN                             : in   std_logic_vector(1 downto 0);
    ------------------------------- Receive Ports ------------------------------
    GT2_eyescanreset_in                     : in   std_logic;
    GT2_RXUSERRDY_IN                        : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    GT2_eyescandataerror_out                : out  std_logic;
    GT2_eyescantrigger_in                   : in   std_logic;
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
    GT2_RXCHARISCOMMA_OUT                   : out  std_logic_vector(1 downto 0);
    GT2_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
    GT2_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
    GT2_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
    ------------------- Receive Ports - Pattern Checker Ports ------------------
    GT2_rxprbserr_out                       : out  std_logic;
    GT2_rxprbssel_in                        : in   std_logic_vector(2 downto 0);
    ------------------- Receive Ports - Pattern Checker ports ------------------
    GT2_rxprbscntreset_in                   : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports ------------------
    GT2_RXCHANBONDSEQ_OUT                   : out  std_logic;
    GT2_RXCHBONDEN_IN                       : in   std_logic;
    GT2_RXCHBONDI_IN                        : in   std_logic_vector(4 downto 0);
    GT2_RXCHBONDLEVEL_IN                    : in   std_logic_vector(2 downto 0);
    GT2_RXCHBONDMASTER_IN                   : in   std_logic;
    GT2_RXCHBONDO_OUT                       : out  std_logic_vector(4 downto 0);
    GT2_RXCHBONDSLAVE_IN                    : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports  -----------------
    GT2_RXCHANISALIGNED_OUT                 : out  std_logic;
    GT2_RXCHANREALIGN_OUT                   : out  std_logic;
    ------------------- Receive Ports - Clock Correction Ports -----------------
    GT2_RXCLKCORCNT_OUT                     : out  std_logic_vector(1 downto 0);
    --------------- Receive Ports - Comma Detection and Alignment --------------
    GT2_rxbyteisaligned_out                 : out  std_logic;
    GT2_RXBYTEREALIGN_OUT                   : out  std_logic;
    GT2_rxcommadet_out                      : out  std_logic;
    GT2_RXMCOMMAALIGNEN_IN                  : in   std_logic;
    GT2_RXPCOMMAALIGNEN_IN                  : in   std_logic;
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT2_RXDFEAGCHOLD_IN                     : in   std_logic;
    GT2_RXDFELFHOLD_IN                      : in   std_logic;
    GT2_rxdfelpmreset_in                    : in   std_logic;
    GT2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
    GT2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
    ------------------- Receive Ports - RX Data Path interface -----------------
    GT2_GTRXRESET_IN                        : in   std_logic;
    GT2_RXPCSRESET_IN                       : in   std_logic;
    GT2_RXPMARESET_IN                       : in   std_logic;
    GT2_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
    GT2_RXOUTCLK_OUT                        : out  std_logic;
    GT2_RXUSRCLK_IN                         : in   std_logic;
    GT2_RXUSRCLK2_IN                        : in   std_logic;
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    GT2_GTHRXN_IN                           : in   std_logic;
    GT2_GTHRXP_IN                           : in   std_logic;
    GT2_RXCDRLOCK_OUT                       : out  std_logic;
    gt2_rxpmaresetdone_out                  : out  std_logic;
    GT2_dmonitorout_out                     : out  std_logic_vector(14 downto 0);
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    GT2_rxbufreset_in                       : in   std_logic;
    GT2_RXBUFSTATUS_OUT                     : out  std_logic_vector(2 downto 0);
    ------------------------ Receive Ports - RX PLL Ports ----------------------
    GT2_RXRESETDONE_OUT                     : out  std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    GT2_txpostcursor_in                     : in   std_logic_vector(4 downto 0);
    GT2_txprecursor_in                      : in   std_logic_vector(4 downto 0);
    -------------------- Receive Ports - RX Margin Analysis ports ----------------
    GT2_rxlpmen_in                          : in   std_logic;
    GT2_rxcdrovrden_in                      : in   std_logic;
    GT2_rxcdrhold_in                        : in   std_logic;
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
    GT2_RXPOLARITY_IN                       : in   std_logic;
    ------------------------------- Transmit Ports -----------------------------
    GT2_TXUSERRDY_IN                        : in   std_logic;
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    GT2_txchardispmode_in                   : in   std_logic_vector(1 downto 0);
    GT2_txchardispval_in                    : in   std_logic_vector(1 downto 0);
    GT2_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
    ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
    GT2_TXBUFSTATUS_OUT                     : out  std_logic_vector(1 downto 0);
    ------------------ Transmit Ports - TX Data Path interface -----------------
    GT2_GTTXRESET_IN                        : in   std_logic;
    GT2_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
    GT2_TXOUTCLK_OUT                        : out  std_logic;
    GT2_TXOUTCLKFABRIC_OUT                  : out  std_logic;
    GT2_TXOUTCLKPCS_OUT                     : out  std_logic;
    GT2_TXUSRCLK_IN                         : in   std_logic;
    GT2_TXUSRCLK2_IN                        : in   std_logic;
    --------------------- Transmit Ports - PCI Express Ports -------------------
    GT2_txelecidle_in                       : in   std_logic;
    ------------------ Transmit Ports - Pattern Generator Ports ----------------
    GT2_txprbsforceerr_in                   : in   std_logic;
    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
    GT2_GTHTXN_OUT                          : out  std_logic;
    GT2_GTHTXP_OUT                          : out  std_logic;
    GT2_txdiffctrl_in                       : in   std_logic_vector(3 downto 0);
    GT2_txmaincursor_in                     : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    GT2_txpolarity_in                       : in   std_logic;
    ------------------ Transmit Ports - pattern Generator Ports ----------------
    GT2_txprbssel_in                        : in   std_logic_vector(2 downto 0);
    ----------------------- Transmit Ports - TX PLL Ports ----------------------
    GT2_txpcsreset_in                       : in   std_logic;
    GT2_txinhibit_in                        : in   std_logic;
    GT2_txpmareset_in                       : in   std_logic;
    GT2_TXRESETDONE_OUT                     : out  std_logic;

    --_________________________________________________________________________
    --_________________________________________________________________________
    --GT3 
    --____________________________CHANNEL PORTS________________________________
    ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
    GT3_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
    GT3_DRPCLK_IN                           : in   std_logic;
    GT3_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
    GT3_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
    GT3_DRPEN_IN                            : in   std_logic;
    GT3_DRPRDY_OUT                          : out  std_logic;
    GT3_DRPWE_IN                            : in   std_logic;
    ------------------------- Channel - Ref Clock Ports ------------------------
    GT3_GTREFCLK0_IN                        : in   std_logic;
    -------------------------------- Channel PLL -------------------------------
    GT3_CPLLFBCLKLOST_OUT                   : out  std_logic;
    GT3_CPLLLOCK_OUT                        : out  std_logic;
    GT3_CPLLLOCKDETCLK_IN                   : in   std_logic;
    GT3_CPLLREFCLKLOST_OUT                  : out  std_logic;
    GT3_CPLLRESET_IN                        : in   std_logic;
    ------------------------ Loopback and Powerdown Ports ----------------------
    GT3_LOOPBACK_IN                         : in   std_logic_vector(2 downto 0);
    GT3_RXPD_IN                             : in   std_logic_vector(1 downto 0);
    GT3_TXPD_IN                             : in   std_logic_vector(1 downto 0);
    ------------------------------- Receive Ports ------------------------------
    GT3_eyescanreset_in                     : in   std_logic;
    GT3_RXUSERRDY_IN                        : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    GT3_eyescandataerror_out                : out  std_logic;
    GT3_eyescantrigger_in                   : in   std_logic;
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
    GT3_RXCHARISCOMMA_OUT                   : out  std_logic_vector(1 downto 0);
    GT3_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
    GT3_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
    GT3_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
    ------------------- Receive Ports - Pattern Checker Ports ------------------
    GT3_rxprbserr_out                       : out  std_logic;
    GT3_rxprbssel_in                        : in   std_logic_vector(2 downto 0);
    ------------------- Receive Ports - Pattern Checker ports ------------------
    GT3_rxprbscntreset_in                   : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports ------------------
    GT3_RXCHANBONDSEQ_OUT                   : out  std_logic;
    GT3_RXCHBONDEN_IN                       : in   std_logic;
    GT3_RXCHBONDI_IN                        : in   std_logic_vector(4 downto 0);
    GT3_RXCHBONDLEVEL_IN                    : in   std_logic_vector(2 downto 0);
    GT3_RXCHBONDMASTER_IN                   : in   std_logic;
    GT3_RXCHBONDO_OUT                       : out  std_logic_vector(4 downto 0);
    GT3_RXCHBONDSLAVE_IN                    : in   std_logic;
    ------------------- Receive Ports - Channel Bonding Ports  -----------------
    GT3_RXCHANISALIGNED_OUT                 : out  std_logic;
    GT3_RXCHANREALIGN_OUT                   : out  std_logic;
    ------------------- Receive Ports - Clock Correction Ports -----------------
    GT3_RXCLKCORCNT_OUT                     : out  std_logic_vector(1 downto 0);
    --------------- Receive Ports - Comma Detection and Alignment --------------
    GT3_rxbyteisaligned_out                 : out  std_logic;
    GT3_RXBYTEREALIGN_OUT                   : out  std_logic;
    GT3_rxcommadet_out                      : out  std_logic;
    GT3_RXMCOMMAALIGNEN_IN                  : in   std_logic;
    GT3_RXPCOMMAALIGNEN_IN                  : in   std_logic;
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT3_RXDFEAGCHOLD_IN                     : in   std_logic;
    GT3_RXDFELFHOLD_IN                      : in   std_logic;
    GT3_rxdfelpmreset_in                    : in   std_logic;
    GT3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
    GT3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
    ------------------- Receive Ports - RX Data Path interface -----------------
    GT3_GTRXRESET_IN                        : in   std_logic;
    GT3_RXPCSRESET_IN                       : in   std_logic;
    GT3_RXPMARESET_IN                       : in   std_logic;
    GT3_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
    GT3_RXOUTCLK_OUT                        : out  std_logic;
    GT3_RXUSRCLK_IN                         : in   std_logic;
    GT3_RXUSRCLK2_IN                        : in   std_logic;
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    GT3_GTHRXN_IN                           : in   std_logic;
    GT3_GTHRXP_IN                           : in   std_logic;
    GT3_RXCDRLOCK_OUT                       : out  std_logic;
    gt3_rxpmaresetdone_out                  : out  std_logic;
    GT3_dmonitorout_out                     : out  std_logic_vector(14 downto 0);
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    GT3_rxbufreset_in                       : in   std_logic;
    GT3_RXBUFSTATUS_OUT                     : out  std_logic_vector(2 downto 0);
    ------------------------ Receive Ports - RX PLL Ports ----------------------
    GT3_RXRESETDONE_OUT                     : out  std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    GT3_txpostcursor_in                     : in   std_logic_vector(4 downto 0);
    GT3_txprecursor_in                      : in   std_logic_vector(4 downto 0);
    -------------------- Receive Ports - RX Margin Analysis ports ----------------
    GT3_rxlpmen_in                          : in   std_logic;
    GT3_rxcdrovrden_in                      : in   std_logic;
    GT3_rxcdrhold_in                        : in   std_logic;
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
    GT3_RXPOLARITY_IN                       : in   std_logic;
    ------------------------------- Transmit Ports -----------------------------
    GT3_TXUSERRDY_IN                        : in   std_logic;
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    GT3_txchardispmode_in                   : in   std_logic_vector(1 downto 0);
    GT3_txchardispval_in                    : in   std_logic_vector(1 downto 0);
    GT3_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
    ------------ Transmit Ports - TX Buffer and Phase Alignment Ports ----------
    GT3_TXBUFSTATUS_OUT                     : out  std_logic_vector(1 downto 0);
    ------------------ Transmit Ports - TX Data Path interface -----------------
    GT3_GTTXRESET_IN                        : in   std_logic;
    GT3_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
    GT3_TXOUTCLK_OUT                        : out  std_logic;
    GT3_TXOUTCLKFABRIC_OUT                  : out  std_logic;
    GT3_TXOUTCLKPCS_OUT                     : out  std_logic;
    GT3_TXUSRCLK_IN                         : in   std_logic;
    GT3_TXUSRCLK2_IN                        : in   std_logic;
    --------------------- Transmit Ports - PCI Express Ports -------------------
    GT3_txelecidle_in                       : in   std_logic;
    ------------------ Transmit Ports - Pattern Generator Ports ----------------
    GT3_txprbsforceerr_in                   : in   std_logic;
    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
    GT3_GTHTXN_OUT                          : out  std_logic;
    GT3_GTHTXP_OUT                          : out  std_logic;
    GT3_txdiffctrl_in                       : in   std_logic_vector(3 downto 0);
    GT3_txmaincursor_in                     : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    GT3_txpolarity_in                       : in   std_logic;
    ------------------ Transmit Ports - pattern Generator Ports ----------------
    GT3_txprbssel_in                        : in   std_logic_vector(2 downto 0);
    ----------------------- Transmit Ports - TX PLL Ports ----------------------
    GT3_txpcsreset_in                       : in   std_logic;
    GT3_txinhibit_in                        : in   std_logic;
    GT3_txpmareset_in                       : in   std_logic;
    GT3_TXRESETDONE_OUT                     : out  std_logic

);
end component;

  function get_cdrlock_time(is_sim : in integer) return integer is
    variable lock_time: integer;
  begin
    if (is_sim = 1) then
      lock_time := 1000;
    else
      lock_time := 50000 / integer(6.413); --Typical CDR lock time is 50,000UI as per DS182/DS182
    end if;
    return lock_time;
  end function;

--***********************************Parameter Declarations********************

    constant STABLE_CLOCK_PERIOD  : integer := 7;  --Period of the stable clock driving this state-machine, unit is [ns]
    constant RX_CDRLOCK_TIME      : integer := get_cdrlock_time(EXAMPLE_SIMULATION);       -- 200us
    constant WAIT_TIME_CDRLOCK    : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD;      -- 200 us time-out

   signal rx_cdrlock_counter              : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
   signal rx_cdrlocked                    : std_logic;
   signal gt_recclk_stable_i                 : std_logic;
   signal gt_pllrefclklost_i             : std_logic; 
   signal gt_pll_lock_i                   : std_logic; 
   signal gt0_txresetdone_i        : std_logic;
   signal gt0_rxresetdone_i        : std_logic;
   signal gt1_txresetdone_i        : std_logic;
   signal gt1_rxresetdone_i        : std_logic;
   signal gt2_txresetdone_i        : std_logic;
   signal gt2_rxresetdone_i        : std_logic;
   signal gt3_txresetdone_i        : std_logic;
   signal gt3_rxresetdone_i        : std_logic;
   signal txfsm_txresetdone_i                : std_logic;
   signal rxfsm_rxresetdone_i                : std_logic;
   signal txfsm_txresetdone_r                : std_logic;
   signal rxfsm_rxresetdone_r                : std_logic;
   signal rxfsm_rxresetdone_r1               : std_logic;
   signal rxfsm_rxresetdone_r2               : std_logic;
   signal rxfsm_rxresetdone_r3               : std_logic;
   signal gt_tx_reset_i                      : std_logic;
   signal gt_rx_reset_i                      : std_logic;
   signal cpll_reset_i                       : std_logic;  
   signal fsm_gt_rx_reset_t                  : std_logic;
   signal rxfsm_soft_reset_r                 : std_logic;
   signal gt_txuserrdy_i                     : std_logic;
   signal gt_rxuserrdy_i                     : std_logic;
   signal gt_rxdfeagchold_i                  : std_logic;
   signal gt_rxdfelfhold_i                   : std_logic;
 
   signal link_reset_r                       : std_logic;  
   signal link_reset_r2                      : std_logic;

   signal tied_to_ground_i                               : std_logic;
   signal tied_to_ground_vec_i                           : std_logic_vector (63 downto 0);
   signal tied_to_vcc_i                                  : std_logic;
signal chbondi                 : std_logic_vector (4 downto 0);
signal chbondo                 : std_logic_vector (4 downto 0);
signal chbondi_LANE1                 : std_logic_vector (4 downto 0);
signal chbondo_LANE1                 : std_logic_vector (4 downto 0);
signal chbondi_LANE2                 : std_logic_vector (4 downto 0);
signal chbondo_LANE2                 : std_logic_vector (4 downto 0);
signal chbondi_LANE3                 : std_logic_vector (4 downto 0);
signal chbondo_LANE3                 : std_logic_vector (4 downto 0);
   signal chbondi_unused_i                                    : std_logic_vector (4 downto 0);

   signal              gt0_txresetdone_r : std_logic;
   signal              gt0_txresetdone_r2 : std_logic;
   signal              gt0_txresetdone_r3 : std_logic;
   signal              gt0_rxresetdone_r : std_logic;
   signal              gt0_rxresetdone_r2 : std_logic;
   signal              gt0_rxresetdone_r3 : std_logic;
   signal              gt1_txresetdone_r : std_logic;
   signal              gt1_txresetdone_r2 : std_logic;
   signal              gt1_txresetdone_r3 : std_logic;
   signal              gt1_rxresetdone_r : std_logic;
   signal              gt1_rxresetdone_r2 : std_logic;
   signal              gt1_rxresetdone_r3 : std_logic;
   signal              gt2_txresetdone_r : std_logic;
   signal              gt2_txresetdone_r2 : std_logic;
   signal              gt2_txresetdone_r3 : std_logic;
   signal              gt2_rxresetdone_r : std_logic;
   signal              gt2_rxresetdone_r2 : std_logic;
   signal              gt2_rxresetdone_r3 : std_logic;
   signal              gt3_txresetdone_r : std_logic;
   signal              gt3_txresetdone_r2 : std_logic;
   signal              gt3_txresetdone_r3 : std_logic;
   signal              gt3_rxresetdone_r : std_logic;
   signal              gt3_rxresetdone_r2 : std_logic;
   signal              gt3_rxresetdone_r3 : std_logic;

   signal gtrxreset_sync                     : std_logic;
   signal gtrxreset_r1                       : std_logic;
   signal gtrxreset_r2                       : std_logic;
   signal gtrxreset_r3                       : std_logic;
   signal gtrxreset_pulse                    : std_logic;

   --concatenation or temp signals
   signal powerdown_i              : std_logic_vector(1 downto 0);
signal rx_buf_status_i    : std_logic_vector(2 downto 0);
signal tx_buf_status_i    : std_logic_vector(1 downto 0);
signal plllkdet_out_i     : std_logic;   
signal gt0_pllrefclklost_i            : std_logic; 
signal rx_buf_status_lane1_i    : std_logic_vector(2 downto 0);
signal tx_buf_status_lane1_i    : std_logic_vector(1 downto 0);
signal plllkdet_out_lane1_i     : std_logic;   
signal gt1_pllrefclklost_i            : std_logic; 
signal rx_buf_status_lane2_i    : std_logic_vector(2 downto 0);
signal tx_buf_status_lane2_i    : std_logic_vector(1 downto 0);
signal plllkdet_out_lane2_i     : std_logic;   
signal gt2_pllrefclklost_i            : std_logic; 
signal rx_buf_status_lane3_i    : std_logic_vector(2 downto 0);
signal tx_buf_status_lane3_i    : std_logic_vector(1 downto 0);
signal plllkdet_out_lane3_i     : std_logic;   
signal gt3_pllrefclklost_i            : std_logic; 


begin

  tied_to_ground_i                    <= '0';
  tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
  tied_to_vcc_i                       <= '1';


  powerdown_i               <=  POWERDOWN_IN & POWERDOWN_IN;
RXBUFERR_OUT        <=  rx_buf_status_i(2);
TXBUFERR_OUT        <=  tx_buf_status_i(1);
PLLLKDET_OUT        <=  plllkdet_out_i;
RXBUFERR_OUT_LANE1        <=  rx_buf_status_lane1_i(2);
TXBUFERR_OUT_LANE1        <=  tx_buf_status_lane1_i(1);
PLLLKDET_OUT_LANE1        <=  plllkdet_out_lane1_i;
RXBUFERR_OUT_LANE2        <=  rx_buf_status_lane2_i(2);
TXBUFERR_OUT_LANE2        <=  tx_buf_status_lane2_i(1);
PLLLKDET_OUT_LANE2        <=  plllkdet_out_lane2_i;
RXBUFERR_OUT_LANE3        <=  rx_buf_status_lane3_i(2);
TXBUFERR_OUT_LANE3        <=  tx_buf_status_lane3_i(1);
PLLLKDET_OUT_LANE3        <=  plllkdet_out_lane3_i;
  chbondi_unused_i          <= "00000";


   --Connect channel bonding bus

   chbondi <= chbondo_LANE1;

   chbondi_LANE1 <= chbondi_unused_i;

   chbondi_LANE2 <= chbondo_LANE1;

   chbondi_LANE3 <= chbondo_LANE2;

      -- QPLL Reset
      gt0_qpllreset_out  <= '0';
      -- QPLL Reset
      gt1_qpllreset_out  <= '0';

      gtrxreset_cdc_sync : aurora_rx_4l_64b_cdc_sync
      generic map
         ( 
           c_cdc_type      => 1             ,   
           c_flop_input    => 1             ,  
           c_reset_state   => 0             ,  
           c_single_bit    => 1             ,  
           c_vector_width  => 2             ,  
           c_mtbf_stages   => 3                
         )
      port map   
         (
           prmry_aclk      => RXUSRCLK2_IN  ,
           prmry_resetn     => '1'          ,
           prmry_in        => GTRXRESET_IN  ,
           prmry_vect_in   => "00"          ,
           scndry_aclk     => INIT_CLK_IN   ,
           scndry_resetn    => '1'          ,
           prmry_ack       => open          ,
           scndry_out      => gtrxreset_sync,
           scndry_vect_out => open  
          );

   process(INIT_CLK_IN)
   begin
     if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
      gtrxreset_r1    <=  gtrxreset_sync after DLY;
      gtrxreset_r2    <=  gtrxreset_r1 after DLY;
      gtrxreset_r3    <=  gtrxreset_r2 after DLY;
      gtrxreset_pulse <=  gtrxreset_r2 AND (NOT gtrxreset_r3) after DLY;        
     end if;
   end process;

    process(INIT_CLK_IN)
    begin
        if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
            link_reset_r           <=  LINK_RESET_IN after DLY;
            link_reset_r2          <=  link_reset_r after DLY;
            gt_rx_reset_i          <=  fsm_gt_rx_reset_t after DLY;
            rxfsm_soft_reset_r     <=  link_reset_r2 or GTRESET_IN or gtrxreset_pulse after DLY;
        end if;
    end process;

  gt_pllrefclklost_i  <= gt0_pllrefclklost_i and gt1_pllrefclklost_i and gt2_pllrefclklost_i and gt3_pllrefclklost_i ;
  gt_pll_lock_i       <= plllkdet_out_i and plllkdet_out_lane1_i and plllkdet_out_lane2_i and plllkdet_out_lane3_i ;
 
    gt0_txresetdone_out  <=   gt0_txresetdone_i;
    gt0_rxresetdone_out  <=   gt0_rxresetdone_i;
    gt0_txbufstatus_out  <=   tx_buf_status_i;
    gt0_rxbufstatus_out  <=   rx_buf_status_i;
    gt1_txresetdone_out  <=   gt1_txresetdone_i;
    gt1_rxresetdone_out  <=   gt1_rxresetdone_i;
    gt1_txbufstatus_out  <=   tx_buf_status_lane1_i;
    gt1_rxbufstatus_out  <=   rx_buf_status_lane1_i;
    gt2_txresetdone_out  <=   gt2_txresetdone_i;
    gt2_rxresetdone_out  <=   gt2_rxresetdone_i;
    gt2_txbufstatus_out  <=   tx_buf_status_lane2_i;
    gt2_rxbufstatus_out  <=   rx_buf_status_lane2_i;
    gt3_txresetdone_out  <=   gt3_txresetdone_i;
    gt3_rxresetdone_out  <=   gt3_rxresetdone_i;
    gt3_txbufstatus_out  <=   tx_buf_status_lane3_i;
    gt3_rxbufstatus_out  <=   rx_buf_status_lane3_i;

      --TXRESETDONE for lane0
    process(TXUSRCLK2_IN)
    begin
        if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
            gt0_txresetdone_r  <=  gt0_txresetdone_i after DLY;
            gt0_txresetdone_r2 <=  gt0_txresetdone_r after DLY;
            gt0_txresetdone_r3 <=  gt0_txresetdone_r2 after DLY;
        end if;
    end process;

      --TXRESETDONE for lane1
    process(TXUSRCLK2_IN)
    begin
        if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
            gt1_txresetdone_r  <=  gt1_txresetdone_i after DLY;
            gt1_txresetdone_r2 <=  gt1_txresetdone_r after DLY;
            gt1_txresetdone_r3 <=  gt1_txresetdone_r2 after DLY;
        end if;
    end process;

      --TXRESETDONE for lane2
    process(TXUSRCLK2_IN)
    begin
        if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
            gt2_txresetdone_r  <=  gt2_txresetdone_i after DLY;
            gt2_txresetdone_r2 <=  gt2_txresetdone_r after DLY;
            gt2_txresetdone_r3 <=  gt2_txresetdone_r2 after DLY;
        end if;
    end process;

      --TXRESETDONE for lane3
    process(TXUSRCLK2_IN)
    begin
        if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
            gt3_txresetdone_r  <=  gt3_txresetdone_i after DLY;
            gt3_txresetdone_r2 <=  gt3_txresetdone_r after DLY;
            gt3_txresetdone_r3 <=  gt3_txresetdone_r2 after DLY;
        end if;
    end process;

      --RXRESETDONE for lane0
    process(RXUSRCLK2_IN)
    begin
        if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
            gt0_rxresetdone_r  <=  gt0_rxresetdone_i after DLY;
            gt0_rxresetdone_r2 <=  gt0_rxresetdone_r after DLY;
            gt0_rxresetdone_r3 <=  gt0_rxresetdone_r2 after DLY;
        end if;
    end process;

      --RXRESETDONE for lane1
    process(RXUSRCLK2_IN)
    begin
        if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
            gt1_rxresetdone_r  <=  gt1_rxresetdone_i after DLY;
            gt1_rxresetdone_r2 <=  gt1_rxresetdone_r after DLY;
            gt1_rxresetdone_r3 <=  gt1_rxresetdone_r2 after DLY;
        end if;
    end process;

      --RXRESETDONE for lane2
    process(RXUSRCLK2_IN)
    begin
        if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
            gt2_rxresetdone_r  <=  gt2_rxresetdone_i after DLY;
            gt2_rxresetdone_r2 <=  gt2_rxresetdone_r after DLY;
            gt2_rxresetdone_r3 <=  gt2_rxresetdone_r2 after DLY;
        end if;
    end process;

      --RXRESETDONE for lane3
    process(RXUSRCLK2_IN)
    begin
        if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
            gt3_rxresetdone_r  <=  gt3_rxresetdone_i after DLY;
            gt3_rxresetdone_r2 <=  gt3_rxresetdone_r after DLY;
            gt3_rxresetdone_r3 <=  gt3_rxresetdone_r2 after DLY;
        end if;
    end process;

  
  txfsm_txresetdone_i  <= gt0_txresetdone_r3 and gt1_txresetdone_r3 and gt2_txresetdone_r3 and gt3_txresetdone_r3 ;
  rxfsm_rxresetdone_i  <= gt0_rxresetdone_r3 and gt1_rxresetdone_r3 and gt2_rxresetdone_r3 and gt3_rxresetdone_r3 ;

    process(TXUSRCLK2_IN)
    begin
        if(TXUSRCLK2_IN'event and TXUSRCLK2_IN='1') then
            txfsm_txresetdone_r   <=  txfsm_txresetdone_i after DLY;
        end if;
    end process;

    process(RXUSRCLK2_IN)
    begin
        if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
            rxfsm_rxresetdone_r   <=  rxfsm_rxresetdone_i after DLY;
            rxfsm_rxresetdone_r2  <=  rxfsm_rxresetdone_r after DLY;
            rxfsm_rxresetdone_r3  <=  rxfsm_rxresetdone_r2 after DLY;
        end if;
    end process;

    process(RXUSRCLK2_IN)
    begin
        if(RXUSRCLK2_IN'event and RXUSRCLK2_IN='1') then
            rxfsm_rxresetdone_r1  <=  rxfsm_rxresetdone_i after DLY;
        end if;
    end process;

  RX_RESETDONE_OUT <= rxfsm_rxresetdone_r3;



  gt_tx_reset_i  <= fsm_gt_rx_reset_t;
  gt_txuserrdy_i <= '1';

gt_rxresetfsm_i : aurora_rx_4l_64b_rx_startup_fsm

  generic map(
           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
           GT_TYPE                  => "GTH", --GTX or GTH or GTP
           EQ_MODE                  => "DFE",                 --Rx Equalization Mode - Set to DFE or LPM
           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           --Period of the stable clock driving this state-machine, unit is [ns]
           RETRY_COUNTER_BITWIDTH   => 8, 
           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
           RX_QPLL_USED             => FALSE,                        -- share these two generic values
           PHASE_ALIGNMENT_MANUAL   =>  FALSE                        -- Decision if a manual phase-alignment is necessary or the automatic 
                                                                     -- is enough. For single-lane applications the automatic alignment is 
                                                                     -- sufficient              
             )     
    port map ( 
        STABLE_CLOCK               =>    INIT_CLK_IN,
        RXUSERCLK                  =>    RXUSRCLK2_IN,
        SOFT_RESET                 =>    rxfsm_soft_reset_r,
        RXPMARESETDONE             =>    tied_to_vcc_i,               
        RXOUTCLK                   =>    RXUSRCLK2_IN, 
              
        DONT_RESET_ON_DATA_ERROR   =>    tied_to_ground_i,
        QPLLREFCLKLOST             =>    tied_to_ground_i,
        CPLLREFCLKLOST             =>    gt_pllrefclklost_i,
        QPLLLOCK                   =>    tied_to_vcc_i,
        CPLLLOCK                   =>    gt_pll_lock_i,
        RXRESETDONE                =>    rxfsm_rxresetdone_r1,
        MMCM_LOCK                  =>    tied_to_vcc_i,
        RECCLK_STABLE              =>    gt_recclk_stable_i,
        RECCLK_MONITOR_RESTART     =>    tied_to_ground_i,
        DATA_VALID                 =>    gt_rxuserrdy_i,
        TXUSERRDY                  =>    gt_txuserrdy_i,
        GTRXRESET                  =>    fsm_gt_rx_reset_t,
        MMCM_RESET                 =>    open,
        QPLL_RESET                 =>    open,
        CPLL_RESET                 =>    cpll_reset_i,
        RX_FSM_RESET_DONE          =>    open,
        RXUSERRDY                  =>    gt_rxuserrdy_i,
        RUN_PHALIGNMENT            =>    open,
        RESET_PHALIGNMENT          =>    open,
        PHALIGNMENT_DONE           =>    tied_to_vcc_i,
        RXDFEAGCHOLD               =>    gt_rxdfeagchold_i,
        RXDFELFHOLD                =>    gt_rxdfelfhold_i,
        RXLPMLFHOLD                =>    open,
        RXLPMHFHOLD                =>    open,
        RETRY_COUNTER              =>    open
           );

  cdrlock_timeout:process(INIT_CLK_IN)
  begin
    if rising_edge(INIT_CLK_IN) then
        if(gt_rx_reset_i = '1') then
          rx_cdrlocked       <= '0';
          rx_cdrlock_counter <=  0                        after DLY;
        elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
          rx_cdrlocked       <= '1';
          rx_cdrlock_counter <= rx_cdrlock_counter        after DLY;
        else
          rx_cdrlock_counter <= rx_cdrlock_counter + 1    after DLY;
        end if;
    end if;
  end process;

gt_recclk_stable_i                          <= rx_cdrlocked;


------------------------- GT Instantiations  -------------------------- 
   aurora_rx_4l_64b_multi_gt_i : aurora_rx_4l_64b_multi_gt
    generic map
    (
        -- Simulation attributes
        WRAPPER_SIM_GTRESET_SPEEDUP      => SIM_GTRESET_SPEEDUP

    )
    port map
    (
--____________________________COMMON PORTS INST_______________________________{
        gt_qpllclk_quad2_i     => gt_qpllclk_quad2_in    ,
        gt_qpllrefclk_quad2_i  => gt_qpllrefclk_quad2_in ,
        gt_qpllclk_quad3_i     => gt_qpllclk_quad3_in    ,
        gt_qpllrefclk_quad3_i  => gt_qpllrefclk_quad3_in ,
--____________________________COMMON PORTS INST_______________________________}


        --_________________________________________________________________________
        --_________________________________________________________________________
        --GT0 
        ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
GT0_DRPADDR_IN                     => DRPADDR_IN,
GT0_DRPCLK_IN                      => DRPCLK_IN,
GT0_DRPDI_IN                       => DRPDI_IN,
GT0_DRPDO_OUT                      => DRPDO_OUT,
GT0_DRPEN_IN                       => DRPEN_IN,
GT0_DRPRDY_OUT                     => DRPRDY_OUT,
GT0_DRPWE_IN                       => DRPWE_IN,
        ------------------------- Channel - Ref Clock Ports ------------------------
        GT0_GTREFCLK0_IN                   => REFCLK,
        -------------------------------- Channel PLL -------------------------------
        GT0_CPLLFBCLKLOST_OUT              => OPEN,
        GT0_CPLLLOCK_OUT                   => plllkdet_out_i,
        GT0_CPLLLOCKDETCLK_IN              => INIT_CLK_IN,
        GT0_CPLLREFCLKLOST_OUT             => gt0_pllrefclklost_i,
        GT0_CPLLRESET_IN                   => cpll_reset_i,
        ------------------------ Loopback and Powerdown Ports ----------------------
        GT0_LOOPBACK_IN                    => LOOPBACK_IN,
        GT0_RXPD_IN                        => powerdown_i,
        GT0_TXPD_IN                        => powerdown_i,
        ------------------------------- Receive Ports ------------------------------
        GT0_RXUSERRDY_IN                   => gt_rxuserrdy_i,
        ----------------------- Receive Ports - 8b10b Decoder ----------------------
GT0_RXCHARISCOMMA_OUT              => RXCHARISCOMMA_OUT,
GT0_RXCHARISK_OUT                  => RXCHARISK_OUT,
GT0_RXDISPERR_OUT                  => RXDISPERR_OUT,
GT0_RXNOTINTABLE_OUT               => RXNOTINTABLE_OUT,
        ------------------- Receive Ports - Channel Bonding Ports ------------------
        GT0_RXCHANBONDSEQ_OUT              => OPEN,
GT0_RXCHBONDEN_IN                  => ENCHANSYNC_IN,
GT0_RXCHBONDI_IN                   => chbondi,
GT0_RXCHBONDLEVEL_IN               => CHAN_BOND_LEVEL,
GT0_RXCHBONDMASTER_IN              => CHAN_BOND_MASTER,
GT0_RXCHBONDO_OUT                  => chbondo,
GT0_RXCHBONDSLAVE_IN               => CHAN_BOND_SLAVE,
GT0_RXCHANISALIGNED_OUT            => CHBONDDONE_OUT,
        GT0_RXCHANREALIGN_OUT              => OPEN,
        ------------------- Receive Ports - Clock Correction Ports -----------------
        GT0_RXCLKCORCNT_OUT                => OPEN,
        --------------- Receive Ports - Comma Detection and Alignment --------------
GT0_RXBYTEREALIGN_OUT              => RXREALIGN_OUT,
GT0_RXMCOMMAALIGNEN_IN             => ENMCOMMAALIGN_IN,
GT0_RXPCOMMAALIGNEN_IN             => ENPCOMMAALIGN_IN,
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT0_RXDFEAGCHOLD_IN          => gt_rxdfeagchold_i,
    GT0_RXDFELFHOLD_IN           => gt_rxdfelfhold_i,
        ------------------- Receive Ports - RX Data Path interface -----------------
        GT0_GTRXRESET_IN                   => gt_rx_reset_i,
GT0_RXDATA_OUT                     => RXDATA_OUT,
        GT0_RXOUTCLK_OUT                   => OPEN,
        GT0_RXUSRCLK_IN                    => RXUSRCLK_IN,
        GT0_RXUSRCLK2_IN                   => RXUSRCLK2_IN,
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GT0_GTHRXN_IN                      => RX1N_IN,
GT0_GTHRXP_IN                      => RX1P_IN,
        gt0_txelecidle_in        => tied_to_ground_i,
        GT0_RXCDRLOCK_OUT                  => OPEN,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GT0_RXBUFSTATUS_OUT                => rx_buf_status_i,
        ------------------------ Receive Ports - RX PLL Ports ----------------------
        GT0_RXRESETDONE_OUT                => gt0_rxresetdone_i,
        GT0_RXPMARESETDONE_OUT          => gt0_rxpmaresetdone_out,
        ------------------------------- Transmit Ports -----------------------------
        GT0_TXUSERRDY_IN                   => gt_txuserrdy_i,
        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GT0_TXCHARISK_IN                   => TXCHARISK_IN,
        ----------- Transmit Ports - TX Buffer and Phase Alignment ---------
GT0_TXBUFSTATUS_OUT                => tx_buf_status_i,
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
GT0_RXPOLARITY_IN                  => RXPOLARITY_IN,
        ------------------ Transmit Ports - TX Data Path interface -----------------
        GT0_GTTXRESET_IN                   => gt_tx_reset_i,
GT0_TXDATA_IN                      => TXDATA_IN,
GT0_TXOUTCLK_OUT                   => TXOUTCLK1_OUT,
        GT0_TXOUTCLKFABRIC_OUT             => OPEN,
        GT0_TXOUTCLKPCS_OUT                => OPEN,
        GT0_TXUSRCLK_IN                    => TXUSRCLK_IN,
        GT0_TXUSRCLK2_IN                   => TXUSRCLK2_IN,
        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
GT0_GTHTXN_OUT                     => TX1N_OUT,
GT0_GTHTXP_OUT                     => TX1P_OUT,
         gt0_rxlpmen_in                     => gt0_rxlpmen_in,
         gt0_rxcdrovrden_in                 => gt0_rxcdrovrden_in,
         gt0_rxcdrhold_in                   => gt0_rxcdrhold_in,
         gt0_rxdfelpmreset_in               => gt0_rxdfelpmreset_in,
         gt0_rxmonitorout_out               => gt0_rxmonitorout_out,
         gt0_rxmonitorsel_in                => gt0_rxmonitorsel_in,

         gt0_eyescanreset_in                => gt0_eyescanreset_in,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt0_eyescandataerror_out           => gt0_eyescandataerror_out,
         gt0_eyescantrigger_in              => gt0_eyescantrigger_in,
         gt0_rxbyteisaligned_out            => gt0_rxbyteisaligned_out,
         gt0_rxcommadet_out                 => gt0_rxcommadet_out,
        ------------------------ TX Configurable Driver Ports ----------------------
         gt0_txpostcursor_in                => gt0_txpostcursor_in,
         gt0_txprecursor_in                 => gt0_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt0_txchardispmode_in              => gt0_txchardispmode_in,
         gt0_txchardispval_in               => gt0_txchardispval_in,
         gt0_txdiffctrl_in                  => gt0_txdiffctrl_in,
         gt0_txmaincursor_in                => gt0_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt0_txpolarity_in                  => gt0_txpolarity_in,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
         gt0_rxprbserr_out               => gt0_rxprbserr_out,
         gt0_rxprbssel_in                => gt0_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
         gt0_rxprbscntreset_in           => gt0_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
         gt0_rxpcsreset_in               => gt0_rxpcsreset_in,
         gt0_rxpmareset_in               => gt0_rxpmareset_in,
         gt0_dmonitorout_out             => gt0_dmonitorout_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
         gt0_rxbufreset_in               => gt0_rxbufreset_in,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
         gt0_txprbsforceerr_in           => gt0_txprbsforceerr_in,
         gt0_txprbssel_in                => gt0_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
         gt0_txpcsreset_in               => gt0_txpcsreset_in,
         gt0_txinhibit_in                => gt0_txinhibit_in,
         gt0_txpmareset_in               => gt0_txpmareset_in,


        ----------------------- Transmit Ports - TX PLL Ports ----------------------
        GT0_TXRESETDONE_OUT                => gt0_txresetdone_i,

        --_________________________________________________________________________
        --_________________________________________________________________________
        --GT1 
        ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
GT1_DRPADDR_IN                     => DRPADDR_IN_LANE1,
GT1_DRPCLK_IN                      => DRPCLK_IN_LANE1,
GT1_DRPDI_IN                       => DRPDI_IN_LANE1,
GT1_DRPDO_OUT                      => DRPDO_OUT_LANE1,
GT1_DRPEN_IN                       => DRPEN_IN_LANE1,
GT1_DRPRDY_OUT                     => DRPRDY_OUT_LANE1,
GT1_DRPWE_IN                       => DRPWE_IN_LANE1,
        ------------------------- Channel - Ref Clock Ports ------------------------
        GT1_GTREFCLK0_IN                   => REFCLK,
        -------------------------------- Channel PLL -------------------------------
        GT1_CPLLFBCLKLOST_OUT              => OPEN,
        GT1_CPLLLOCK_OUT                   => plllkdet_out_lane1_i,
        GT1_CPLLLOCKDETCLK_IN              => INIT_CLK_IN,
        GT1_CPLLREFCLKLOST_OUT             => gt1_pllrefclklost_i,
        GT1_CPLLRESET_IN                   => cpll_reset_i,
        ------------------------ Loopback and Powerdown Ports ----------------------
        GT1_LOOPBACK_IN                    => LOOPBACK_IN,
        GT1_RXPD_IN                        => powerdown_i,
        GT1_TXPD_IN                        => powerdown_i,
        ------------------------------- Receive Ports ------------------------------
        GT1_RXUSERRDY_IN                   => gt_rxuserrdy_i,
        ----------------------- Receive Ports - 8b10b Decoder ----------------------
GT1_RXCHARISCOMMA_OUT              => RXCHARISCOMMA_OUT_LANE1,
GT1_RXCHARISK_OUT                  => RXCHARISK_OUT_LANE1,
GT1_RXDISPERR_OUT                  => RXDISPERR_OUT_LANE1,
GT1_RXNOTINTABLE_OUT               => RXNOTINTABLE_OUT_LANE1,
        ------------------- Receive Ports - Channel Bonding Ports ------------------
        GT1_RXCHANBONDSEQ_OUT              => OPEN,
GT1_RXCHBONDEN_IN                  => ENCHANSYNC_IN_LANE1,
GT1_RXCHBONDI_IN                   => chbondi_LANE1,
GT1_RXCHBONDLEVEL_IN               => CHAN_BOND_LEVEL_LANE1,
GT1_RXCHBONDMASTER_IN              => CHAN_BOND_MASTER_LANE1,
GT1_RXCHBONDO_OUT                  => chbondo_LANE1,
GT1_RXCHBONDSLAVE_IN               => CHAN_BOND_SLAVE_LANE1,
GT1_RXCHANISALIGNED_OUT            => CHBONDDONE_OUT_LANE1,
        GT1_RXCHANREALIGN_OUT              => OPEN,
        ------------------- Receive Ports - Clock Correction Ports -----------------
        GT1_RXCLKCORCNT_OUT                => OPEN,
        --------------- Receive Ports - Comma Detection and Alignment --------------
GT1_RXBYTEREALIGN_OUT              => RXREALIGN_OUT_LANE1,
GT1_RXMCOMMAALIGNEN_IN             => ENMCOMMAALIGN_IN_LANE1,
GT1_RXPCOMMAALIGNEN_IN             => ENPCOMMAALIGN_IN_LANE1,
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT1_RXDFEAGCHOLD_IN          => gt_rxdfeagchold_i,
    GT1_RXDFELFHOLD_IN           => gt_rxdfelfhold_i,
        ------------------- Receive Ports - RX Data Path interface -----------------
        GT1_GTRXRESET_IN                   => gt_rx_reset_i,
GT1_RXDATA_OUT                     => RXDATA_OUT_LANE1,
        GT1_RXOUTCLK_OUT                   => OPEN,
        GT1_RXUSRCLK_IN                    => RXUSRCLK_IN,
        GT1_RXUSRCLK2_IN                   => RXUSRCLK2_IN,
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GT1_GTHRXN_IN                      => RX1N_IN_LANE1,
GT1_GTHRXP_IN                      => RX1P_IN_LANE1,
        gt1_txelecidle_in        => tied_to_ground_i,
        GT1_RXCDRLOCK_OUT                  => OPEN,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GT1_RXBUFSTATUS_OUT                => rx_buf_status_lane1_i,
        ------------------------ Receive Ports - RX PLL Ports ----------------------
        GT1_RXRESETDONE_OUT                => gt1_rxresetdone_i,
        GT1_RXPMARESETDONE_OUT          => gt1_rxpmaresetdone_out,
        ------------------------------- Transmit Ports -----------------------------
        GT1_TXUSERRDY_IN                   => gt_txuserrdy_i,
        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GT1_TXCHARISK_IN                   => TXCHARISK_IN_LANE1,
        ----------- Transmit Ports - TX Buffer and Phase Alignment ---------
GT1_TXBUFSTATUS_OUT                => tx_buf_status_lane1_i,
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
GT1_RXPOLARITY_IN                  => RXPOLARITY_IN_LANE1,
        ------------------ Transmit Ports - TX Data Path interface -----------------
        GT1_GTTXRESET_IN                   => gt_tx_reset_i,
GT1_TXDATA_IN                      => TXDATA_IN_LANE1,
GT1_TXOUTCLK_OUT                   => TXOUTCLK1_OUT_LANE1,
        GT1_TXOUTCLKFABRIC_OUT             => OPEN,
        GT1_TXOUTCLKPCS_OUT                => OPEN,
        GT1_TXUSRCLK_IN                    => TXUSRCLK_IN,
        GT1_TXUSRCLK2_IN                   => TXUSRCLK2_IN,
        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
GT1_GTHTXN_OUT                     => TX1N_OUT_LANE1,
GT1_GTHTXP_OUT                     => TX1P_OUT_LANE1,
         gt1_rxlpmen_in                     => gt1_rxlpmen_in,
         gt1_rxcdrovrden_in                 => gt1_rxcdrovrden_in,
         gt1_rxcdrhold_in                   => gt1_rxcdrhold_in,
         gt1_rxdfelpmreset_in               => gt1_rxdfelpmreset_in,
         gt1_rxmonitorout_out               => gt1_rxmonitorout_out,
         gt1_rxmonitorsel_in                => gt1_rxmonitorsel_in,

         gt1_eyescanreset_in                => gt1_eyescanreset_in,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt1_eyescandataerror_out           => gt1_eyescandataerror_out,
         gt1_eyescantrigger_in              => gt1_eyescantrigger_in,
         gt1_rxbyteisaligned_out            => gt1_rxbyteisaligned_out,
         gt1_rxcommadet_out                 => gt1_rxcommadet_out,
        ------------------------ TX Configurable Driver Ports ----------------------
         gt1_txpostcursor_in                => gt1_txpostcursor_in,
         gt1_txprecursor_in                 => gt1_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt1_txchardispmode_in              => gt1_txchardispmode_in,
         gt1_txchardispval_in               => gt1_txchardispval_in,
         gt1_txdiffctrl_in                  => gt1_txdiffctrl_in,
         gt1_txmaincursor_in                => gt1_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt1_txpolarity_in                  => gt1_txpolarity_in,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
         gt1_rxprbserr_out               => gt1_rxprbserr_out,
         gt1_rxprbssel_in                => gt1_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
         gt1_rxprbscntreset_in           => gt1_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
         gt1_rxpcsreset_in               => gt1_rxpcsreset_in,
         gt1_rxpmareset_in               => gt1_rxpmareset_in,
         gt1_dmonitorout_out             => gt1_dmonitorout_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
         gt1_rxbufreset_in               => gt1_rxbufreset_in,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
         gt1_txprbsforceerr_in           => gt1_txprbsforceerr_in,
         gt1_txprbssel_in                => gt1_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
         gt1_txpcsreset_in               => gt1_txpcsreset_in,
         gt1_txinhibit_in                => gt1_txinhibit_in,
         gt1_txpmareset_in               => gt1_txpmareset_in,


        ----------------------- Transmit Ports - TX PLL Ports ----------------------
        GT1_TXRESETDONE_OUT                => gt1_txresetdone_i,

        --_________________________________________________________________________
        --_________________________________________________________________________
        --GT2 
        ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
GT2_DRPADDR_IN                     => DRPADDR_IN_LANE2,
GT2_DRPCLK_IN                      => DRPCLK_IN_LANE2,
GT2_DRPDI_IN                       => DRPDI_IN_LANE2,
GT2_DRPDO_OUT                      => DRPDO_OUT_LANE2,
GT2_DRPEN_IN                       => DRPEN_IN_LANE2,
GT2_DRPRDY_OUT                     => DRPRDY_OUT_LANE2,
GT2_DRPWE_IN                       => DRPWE_IN_LANE2,
        ------------------------- Channel - Ref Clock Ports ------------------------
        GT2_GTREFCLK0_IN                   => REFCLK,
        -------------------------------- Channel PLL -------------------------------
        GT2_CPLLFBCLKLOST_OUT              => OPEN,
        GT2_CPLLLOCK_OUT                   => plllkdet_out_lane2_i,
        GT2_CPLLLOCKDETCLK_IN              => INIT_CLK_IN,
        GT2_CPLLREFCLKLOST_OUT             => gt2_pllrefclklost_i,
        GT2_CPLLRESET_IN                   => cpll_reset_i,
        ------------------------ Loopback and Powerdown Ports ----------------------
        GT2_LOOPBACK_IN                    => LOOPBACK_IN,
        GT2_RXPD_IN                        => powerdown_i,
        GT2_TXPD_IN                        => powerdown_i,
        ------------------------------- Receive Ports ------------------------------
        GT2_RXUSERRDY_IN                   => gt_rxuserrdy_i,
        ----------------------- Receive Ports - 8b10b Decoder ----------------------
GT2_RXCHARISCOMMA_OUT              => RXCHARISCOMMA_OUT_LANE2,
GT2_RXCHARISK_OUT                  => RXCHARISK_OUT_LANE2,
GT2_RXDISPERR_OUT                  => RXDISPERR_OUT_LANE2,
GT2_RXNOTINTABLE_OUT               => RXNOTINTABLE_OUT_LANE2,
        ------------------- Receive Ports - Channel Bonding Ports ------------------
        GT2_RXCHANBONDSEQ_OUT              => OPEN,
GT2_RXCHBONDEN_IN                  => ENCHANSYNC_IN_LANE2,
GT2_RXCHBONDI_IN                   => chbondi_LANE2,
GT2_RXCHBONDLEVEL_IN               => CHAN_BOND_LEVEL_LANE2,
GT2_RXCHBONDMASTER_IN              => CHAN_BOND_MASTER_LANE2,
GT2_RXCHBONDO_OUT                  => chbondo_LANE2,
GT2_RXCHBONDSLAVE_IN               => CHAN_BOND_SLAVE_LANE2,
GT2_RXCHANISALIGNED_OUT            => CHBONDDONE_OUT_LANE2,
        GT2_RXCHANREALIGN_OUT              => OPEN,
        ------------------- Receive Ports - Clock Correction Ports -----------------
        GT2_RXCLKCORCNT_OUT                => OPEN,
        --------------- Receive Ports - Comma Detection and Alignment --------------
GT2_RXBYTEREALIGN_OUT              => RXREALIGN_OUT_LANE2,
GT2_RXMCOMMAALIGNEN_IN             => ENMCOMMAALIGN_IN_LANE2,
GT2_RXPCOMMAALIGNEN_IN             => ENPCOMMAALIGN_IN_LANE2,
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT2_RXDFEAGCHOLD_IN          => gt_rxdfeagchold_i,
    GT2_RXDFELFHOLD_IN           => gt_rxdfelfhold_i,
        ------------------- Receive Ports - RX Data Path interface -----------------
        GT2_GTRXRESET_IN                   => gt_rx_reset_i,
GT2_RXDATA_OUT                     => RXDATA_OUT_LANE2,
        GT2_RXOUTCLK_OUT                   => OPEN,
        GT2_RXUSRCLK_IN                    => RXUSRCLK_IN,
        GT2_RXUSRCLK2_IN                   => RXUSRCLK2_IN,
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GT2_GTHRXN_IN                      => RX1N_IN_LANE2,
GT2_GTHRXP_IN                      => RX1P_IN_LANE2,
        gt2_txelecidle_in        => tied_to_ground_i,
        GT2_RXCDRLOCK_OUT                  => OPEN,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GT2_RXBUFSTATUS_OUT                => rx_buf_status_lane2_i,
        ------------------------ Receive Ports - RX PLL Ports ----------------------
        GT2_RXRESETDONE_OUT                => gt2_rxresetdone_i,
        GT2_RXPMARESETDONE_OUT          => gt2_rxpmaresetdone_out,
        ------------------------------- Transmit Ports -----------------------------
        GT2_TXUSERRDY_IN                   => gt_txuserrdy_i,
        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GT2_TXCHARISK_IN                   => TXCHARISK_IN_LANE2,
        ----------- Transmit Ports - TX Buffer and Phase Alignment ---------
GT2_TXBUFSTATUS_OUT                => tx_buf_status_lane2_i,
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
GT2_RXPOLARITY_IN                  => RXPOLARITY_IN_LANE2,
        ------------------ Transmit Ports - TX Data Path interface -----------------
        GT2_GTTXRESET_IN                   => gt_tx_reset_i,
GT2_TXDATA_IN                      => TXDATA_IN_LANE2,
GT2_TXOUTCLK_OUT                   => TXOUTCLK1_OUT_LANE2,
        GT2_TXOUTCLKFABRIC_OUT             => OPEN,
        GT2_TXOUTCLKPCS_OUT                => OPEN,
        GT2_TXUSRCLK_IN                    => TXUSRCLK_IN,
        GT2_TXUSRCLK2_IN                   => TXUSRCLK2_IN,
        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
GT2_GTHTXN_OUT                     => TX1N_OUT_LANE2,
GT2_GTHTXP_OUT                     => TX1P_OUT_LANE2,
         gt2_rxlpmen_in                     => gt2_rxlpmen_in,
         gt2_rxcdrovrden_in                 => gt2_rxcdrovrden_in,
         gt2_rxcdrhold_in                   => gt2_rxcdrhold_in,
         gt2_rxdfelpmreset_in               => gt2_rxdfelpmreset_in,
         gt2_rxmonitorout_out               => gt2_rxmonitorout_out,
         gt2_rxmonitorsel_in                => gt2_rxmonitorsel_in,

         gt2_eyescanreset_in                => gt2_eyescanreset_in,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt2_eyescandataerror_out           => gt2_eyescandataerror_out,
         gt2_eyescantrigger_in              => gt2_eyescantrigger_in,
         gt2_rxbyteisaligned_out            => gt2_rxbyteisaligned_out,
         gt2_rxcommadet_out                 => gt2_rxcommadet_out,
        ------------------------ TX Configurable Driver Ports ----------------------
         gt2_txpostcursor_in                => gt2_txpostcursor_in,
         gt2_txprecursor_in                 => gt2_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt2_txchardispmode_in              => gt2_txchardispmode_in,
         gt2_txchardispval_in               => gt2_txchardispval_in,
         gt2_txdiffctrl_in                  => gt2_txdiffctrl_in,
         gt2_txmaincursor_in                => gt2_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt2_txpolarity_in                  => gt2_txpolarity_in,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
         gt2_rxprbserr_out               => gt2_rxprbserr_out,
         gt2_rxprbssel_in                => gt2_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
         gt2_rxprbscntreset_in           => gt2_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
         gt2_rxpcsreset_in               => gt2_rxpcsreset_in,
         gt2_rxpmareset_in               => gt2_rxpmareset_in,
         gt2_dmonitorout_out             => gt2_dmonitorout_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
         gt2_rxbufreset_in               => gt2_rxbufreset_in,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
         gt2_txprbsforceerr_in           => gt2_txprbsforceerr_in,
         gt2_txprbssel_in                => gt2_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
         gt2_txpcsreset_in               => gt2_txpcsreset_in,
         gt2_txinhibit_in                => gt2_txinhibit_in,
         gt2_txpmareset_in               => gt2_txpmareset_in,


        ----------------------- Transmit Ports - TX PLL Ports ----------------------
        GT2_TXRESETDONE_OUT                => gt2_txresetdone_i,

        --_________________________________________________________________________
        --_________________________________________________________________________
        --GT3 
        ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
GT3_DRPADDR_IN                     => DRPADDR_IN_LANE3,
GT3_DRPCLK_IN                      => DRPCLK_IN_LANE3,
GT3_DRPDI_IN                       => DRPDI_IN_LANE3,
GT3_DRPDO_OUT                      => DRPDO_OUT_LANE3,
GT3_DRPEN_IN                       => DRPEN_IN_LANE3,
GT3_DRPRDY_OUT                     => DRPRDY_OUT_LANE3,
GT3_DRPWE_IN                       => DRPWE_IN_LANE3,
        ------------------------- Channel - Ref Clock Ports ------------------------
        GT3_GTREFCLK0_IN                   => REFCLK,
        -------------------------------- Channel PLL -------------------------------
        GT3_CPLLFBCLKLOST_OUT              => OPEN,
        GT3_CPLLLOCK_OUT                   => plllkdet_out_lane3_i,
        GT3_CPLLLOCKDETCLK_IN              => INIT_CLK_IN,
        GT3_CPLLREFCLKLOST_OUT             => gt3_pllrefclklost_i,
        GT3_CPLLRESET_IN                   => cpll_reset_i,
        ------------------------ Loopback and Powerdown Ports ----------------------
        GT3_LOOPBACK_IN                    => LOOPBACK_IN,
        GT3_RXPD_IN                        => powerdown_i,
        GT3_TXPD_IN                        => powerdown_i,
        ------------------------------- Receive Ports ------------------------------
        GT3_RXUSERRDY_IN                   => gt_rxuserrdy_i,
        ----------------------- Receive Ports - 8b10b Decoder ----------------------
GT3_RXCHARISCOMMA_OUT              => RXCHARISCOMMA_OUT_LANE3,
GT3_RXCHARISK_OUT                  => RXCHARISK_OUT_LANE3,
GT3_RXDISPERR_OUT                  => RXDISPERR_OUT_LANE3,
GT3_RXNOTINTABLE_OUT               => RXNOTINTABLE_OUT_LANE3,
        ------------------- Receive Ports - Channel Bonding Ports ------------------
        GT3_RXCHANBONDSEQ_OUT              => OPEN,
GT3_RXCHBONDEN_IN                  => ENCHANSYNC_IN_LANE3,
GT3_RXCHBONDI_IN                   => chbondi_LANE3,
GT3_RXCHBONDLEVEL_IN               => CHAN_BOND_LEVEL_LANE3,
GT3_RXCHBONDMASTER_IN              => CHAN_BOND_MASTER_LANE3,
GT3_RXCHBONDO_OUT                  => chbondo_LANE3,
GT3_RXCHBONDSLAVE_IN               => CHAN_BOND_SLAVE_LANE3,
GT3_RXCHANISALIGNED_OUT            => CHBONDDONE_OUT_LANE3,
        GT3_RXCHANREALIGN_OUT              => OPEN,
        ------------------- Receive Ports - Clock Correction Ports -----------------
        GT3_RXCLKCORCNT_OUT                => OPEN,
        --------------- Receive Ports - Comma Detection and Alignment --------------
GT3_RXBYTEREALIGN_OUT              => RXREALIGN_OUT_LANE3,
GT3_RXMCOMMAALIGNEN_IN             => ENMCOMMAALIGN_IN_LANE3,
GT3_RXPCOMMAALIGNEN_IN             => ENPCOMMAALIGN_IN_LANE3,
    --------------------- Receive Ports - RX Equalizer Ports -------------------
    GT3_RXDFEAGCHOLD_IN          => gt_rxdfeagchold_i,
    GT3_RXDFELFHOLD_IN           => gt_rxdfelfhold_i,
        ------------------- Receive Ports - RX Data Path interface -----------------
        GT3_GTRXRESET_IN                   => gt_rx_reset_i,
GT3_RXDATA_OUT                     => RXDATA_OUT_LANE3,
        GT3_RXOUTCLK_OUT                   => OPEN,
        GT3_RXUSRCLK_IN                    => RXUSRCLK_IN,
        GT3_RXUSRCLK2_IN                   => RXUSRCLK2_IN,
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GT3_GTHRXN_IN                      => RX1N_IN_LANE3,
GT3_GTHRXP_IN                      => RX1P_IN_LANE3,
        gt3_txelecidle_in        => tied_to_ground_i,
        GT3_RXCDRLOCK_OUT                  => OPEN,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GT3_RXBUFSTATUS_OUT                => rx_buf_status_lane3_i,
        ------------------------ Receive Ports - RX PLL Ports ----------------------
        GT3_RXRESETDONE_OUT                => gt3_rxresetdone_i,
        GT3_RXPMARESETDONE_OUT          => gt3_rxpmaresetdone_out,
        ------------------------------- Transmit Ports -----------------------------
        GT3_TXUSERRDY_IN                   => gt_txuserrdy_i,
        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GT3_TXCHARISK_IN                   => TXCHARISK_IN_LANE3,
        ----------- Transmit Ports - TX Buffer and Phase Alignment ---------
GT3_TXBUFSTATUS_OUT                => tx_buf_status_lane3_i,
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
GT3_RXPOLARITY_IN                  => RXPOLARITY_IN_LANE3,
        ------------------ Transmit Ports - TX Data Path interface -----------------
        GT3_GTTXRESET_IN                   => gt_tx_reset_i,
GT3_TXDATA_IN                      => TXDATA_IN_LANE3,
GT3_TXOUTCLK_OUT                   => TXOUTCLK1_OUT_LANE3,
        GT3_TXOUTCLKFABRIC_OUT             => OPEN,
        GT3_TXOUTCLKPCS_OUT                => OPEN,
        GT3_TXUSRCLK_IN                    => TXUSRCLK_IN,
        GT3_TXUSRCLK2_IN                   => TXUSRCLK2_IN,
        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
GT3_GTHTXN_OUT                     => TX1N_OUT_LANE3,
GT3_GTHTXP_OUT                     => TX1P_OUT_LANE3,
         gt3_rxlpmen_in                     => gt3_rxlpmen_in,
         gt3_rxcdrovrden_in                 => gt3_rxcdrovrden_in,
         gt3_rxcdrhold_in                   => gt3_rxcdrhold_in,
         gt3_rxdfelpmreset_in               => gt3_rxdfelpmreset_in,
         gt3_rxmonitorout_out               => gt3_rxmonitorout_out,
         gt3_rxmonitorsel_in                => gt3_rxmonitorsel_in,

         gt3_eyescanreset_in                => gt3_eyescanreset_in,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt3_eyescandataerror_out           => gt3_eyescandataerror_out,
         gt3_eyescantrigger_in              => gt3_eyescantrigger_in,
         gt3_rxbyteisaligned_out            => gt3_rxbyteisaligned_out,
         gt3_rxcommadet_out                 => gt3_rxcommadet_out,
        ------------------------ TX Configurable Driver Ports ----------------------
         gt3_txpostcursor_in                => gt3_txpostcursor_in,
         gt3_txprecursor_in                 => gt3_txprecursor_in,
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
         gt3_txchardispmode_in              => gt3_txchardispmode_in,
         gt3_txchardispval_in               => gt3_txchardispval_in,
         gt3_txdiffctrl_in                  => gt3_txdiffctrl_in,
         gt3_txmaincursor_in                => gt3_txmaincursor_in,
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
         gt3_txpolarity_in                  => gt3_txpolarity_in,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
         gt3_rxprbserr_out               => gt3_rxprbserr_out,
         gt3_rxprbssel_in                => gt3_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
         gt3_rxprbscntreset_in           => gt3_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
         gt3_rxpcsreset_in               => gt3_rxpcsreset_in,
         gt3_rxpmareset_in               => gt3_rxpmareset_in,
         gt3_dmonitorout_out             => gt3_dmonitorout_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
         gt3_rxbufreset_in               => gt3_rxbufreset_in,
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
         gt3_txprbsforceerr_in           => gt3_txprbsforceerr_in,
         gt3_txprbssel_in                => gt3_txprbssel_in,
        ------------------- Transmit Ports - TX Data Path interface -----------------
         gt3_txpcsreset_in               => gt3_txpcsreset_in,
         gt3_txinhibit_in                => gt3_txinhibit_in,
         gt3_txpmareset_in               => gt3_txpmareset_in,


        ----------------------- Transmit Ports - TX PLL Ports ----------------------
        GT3_TXRESETDONE_OUT                => gt3_txresetdone_i
);

end MAPPED; 
 
