------------------------------------------------------------------------------/
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
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-- This file contains confidential and proprietary information
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-- international copyright and other intellectual property
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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------------------------------------------------------------------------------/
 library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_misc.all;
     use IEEE.numeric_std.all;
     use ieee.std_logic_arith.all;
     use ieee.std_logic_unsigned.all;

entity  aurora_rx_4l_64b is
 port (

    -- AXI RX Interface
    m_axi_rx_tdata         : out std_logic_vector(63 downto 0);
 
    m_axi_rx_tvalid        : out std_logic;
    m_axi_rx_tkeep         : out std_logic_vector(7 downto 0);
 
    m_axi_rx_tlast         : out std_logic;



    -- User Flow Control RX Inteface
    m_axi_ufc_rx_tdata     : out std_logic_vector(63 downto 0);
    m_axi_ufc_rx_tkeep     : out std_logic_vector(7 downto 0);
    m_axi_ufc_rx_tvalid    : out std_logic;
    m_axi_ufc_rx_tlast     : out std_logic;


 
    -- GT Serial I/O
    rxp                    : in std_logic_vector(0 to 3);
    rxn                    : in std_logic_vector(0 to 3);


    -- GT Reference Clock Interface
    gt_refclk1               : in  std_logic;

    -- Error Detection Interface
 
    frame_err              : out std_logic;
    rx_hard_err            : out std_logic;
    soft_err               : out std_logic;
    rx_lane_up             : out std_logic_vector(0 to 3);
    rx_channel_up          : out std_logic;




    -- System Interface
    user_clk               : in  std_logic;
    sync_clk               : in  std_logic;
    rx_system_reset        : in  std_logic;

    power_down             : in  std_logic;
    loopback               : in  std_logic_vector(2 downto 0);
    gt_reset               : in  std_logic;
    tx_lock                : out std_logic;
    sys_reset_out          : out std_logic;
    init_clk_in            : in  std_logic;
    rx_resetdone_out       : out std_logic;
    link_reset_out         : out std_logic;

    --DRP Ports
 
    drpclk_in                         : in   std_logic;
    drpaddr_in             : in   std_logic_vector(8 downto 0);
    drpdi_in               : in   std_logic_vector(15 downto 0);
    drpdo_out              : out  std_logic_vector(15 downto 0);
    drpen_in               : in   std_logic;
    drprdy_out             : out  std_logic;
    drpwe_in               : in   std_logic;
    drpaddr_in_lane1             : in   std_logic_vector(8 downto 0);
    drpdi_in_lane1               : in   std_logic_vector(15 downto 0);
    drpdo_out_lane1              : out  std_logic_vector(15 downto 0);
    drpen_in_lane1               : in   std_logic;
    drprdy_out_lane1             : out  std_logic;
    drpwe_in_lane1               : in   std_logic;
    drpaddr_in_lane2             : in   std_logic_vector(8 downto 0);
    drpdi_in_lane2               : in   std_logic_vector(15 downto 0);
    drpdo_out_lane2              : out  std_logic_vector(15 downto 0);
    drpen_in_lane2               : in   std_logic;
    drprdy_out_lane2             : out  std_logic;
    drpwe_in_lane2               : in   std_logic;
    drpaddr_in_lane3             : in   std_logic_vector(8 downto 0);
    drpdi_in_lane3               : in   std_logic_vector(15 downto 0);
    drpdo_out_lane3              : out  std_logic_vector(15 downto 0);
    drpen_in_lane3               : in   std_logic;
    drprdy_out_lane3             : out  std_logic;
    drpwe_in_lane3               : in   std_logic;
    gt0_cplllock_out                     : out std_logic;


    gt0_rxlpmen_in                              : in   std_logic;
    gt0_rxcdrovrden_in                          : in   std_logic;
    gt0_rxdfelpmreset_in                        : in   std_logic;
    gt0_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt0_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt0_rxcdrhold_in                            : in   std_logic;
    gt0_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt0_eyescandataerror_out                    : out  std_logic;
    gt0_eyescantrigger_in                       : in   std_logic;
    gt0_rxbyteisaligned_out                     : out  std_logic;
    gt0_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt0_rxprbserr_out                           : out  std_logic;
    gt0_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt0_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt0_rxpcsreset_in                           : in   std_logic;
    gt0_rxpmareset_in                           : in   std_logic;
    gt0_rxpmaresetdone_out                      : out    std_logic;
    gt0_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt0_rxbufreset_in                           : in   std_logic;
    gt0_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt0_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt0_rx_realign_out                          : out  std_logic;
    gt0_rx_buf_err_out                          : out  std_logic;
    gt0_rxresetdone_out                         : out std_logic;
    gt0_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt1_cplllock_out                     : out std_logic;


    gt1_rxlpmen_in                              : in   std_logic;
    gt1_rxcdrovrden_in                          : in   std_logic;
    gt1_rxdfelpmreset_in                        : in   std_logic;
    gt1_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt1_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt1_rxcdrhold_in                            : in   std_logic;
    gt1_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt1_eyescandataerror_out                    : out  std_logic;
    gt1_eyescantrigger_in                       : in   std_logic;
    gt1_rxbyteisaligned_out                     : out  std_logic;
    gt1_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt1_rxprbserr_out                           : out  std_logic;
    gt1_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt1_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt1_rxpcsreset_in                           : in   std_logic;
    gt1_rxpmareset_in                           : in   std_logic;
    gt1_rxpmaresetdone_out                      : out    std_logic;
    gt1_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt1_rxbufreset_in                           : in   std_logic;
    gt1_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt1_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt1_rx_realign_out                          : out  std_logic;
    gt1_rx_buf_err_out                          : out  std_logic;
    gt1_rxresetdone_out                         : out std_logic;
    gt1_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt2_cplllock_out                     : out std_logic;


    gt2_rxlpmen_in                              : in   std_logic;
    gt2_rxcdrovrden_in                          : in   std_logic;
    gt2_rxdfelpmreset_in                        : in   std_logic;
    gt2_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt2_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt2_rxcdrhold_in                            : in   std_logic;
    gt2_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt2_eyescandataerror_out                    : out  std_logic;
    gt2_eyescantrigger_in                       : in   std_logic;
    gt2_rxbyteisaligned_out                     : out  std_logic;
    gt2_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt2_rxprbserr_out                           : out  std_logic;
    gt2_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt2_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt2_rxpcsreset_in                           : in   std_logic;
    gt2_rxpmareset_in                           : in   std_logic;
    gt2_rxpmaresetdone_out                      : out    std_logic;
    gt2_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt2_rxbufreset_in                           : in   std_logic;
    gt2_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt2_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt2_rx_realign_out                          : out  std_logic;
    gt2_rx_buf_err_out                          : out  std_logic;
    gt2_rxresetdone_out                         : out std_logic;
    gt2_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt3_cplllock_out                     : out std_logic;


    gt3_rxlpmen_in                              : in   std_logic;
    gt3_rxcdrovrden_in                          : in   std_logic;
    gt3_rxdfelpmreset_in                        : in   std_logic;
    gt3_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt3_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt3_rxcdrhold_in                            : in   std_logic;
    gt3_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt3_eyescandataerror_out                    : out  std_logic;
    gt3_eyescantrigger_in                       : in   std_logic;
    gt3_rxbyteisaligned_out                     : out  std_logic;
    gt3_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt3_rxprbserr_out                           : out  std_logic;
    gt3_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt3_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt3_rxpcsreset_in                           : in   std_logic;
    gt3_rxpmareset_in                           : in   std_logic;
    gt3_rxpmaresetdone_out                      : out    std_logic;
    gt3_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt3_rxbufreset_in                           : in   std_logic;
    gt3_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt3_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt3_rx_realign_out                          : out  std_logic;
    gt3_rx_buf_err_out                          : out  std_logic;
    gt3_rxresetdone_out                         : out std_logic;
    gt3_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);

--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
    ------------------------- Common Block - QPLL Ports ------------------------
      gt1_qplllock_in       :  in  std_logic;
      gt1_qpllrefclklost_in :  in  std_logic;
      gt1_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad2_in    : in  std_logic;
   gt_qpllrefclk_quad2_in : in  std_logic;
   gt_qpllclk_quad3_in    : in  std_logic;
   gt_qpllrefclk_quad3_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}
    tx_out_clk             : out std_logic;
    pll_not_locked         : in  std_logic

 );

end aurora_rx_4l_64b;


architecture STRUCTURE of aurora_rx_4l_64b is
  attribute core_generation_info           : string;
  attribute core_generation_info of STRUCTURE : architecture is "aurora_rx_4l_64b,aurora_8b10b_v11_1_14,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=right,c_gt_clock_1=GTHQ2,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=4,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=1,c_gt_loc_8=2,c_gt_loc_9=3,c_lane_width=2,c_line_rate=64130,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160325,c_simplex=true,c_simplex_mode=RX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=RX-only_Simplex}";

    component aurora_rx_4l_64b_core
        port   (

         -- RX Stream Interface
         M_AXI_RX_TDATA         : out std_logic_vector(63 downto 0);
         M_AXI_RX_TKEEP         : out std_logic_vector(7 downto 0);
         M_AXI_RX_TVALID        : out std_logic;
         M_AXI_RX_TLAST         : out std_logic;

         -- User Flow Control RX Inteface

         M_AXI_UFC_RX_TDATA     : out std_logic_vector(63 downto 0);
         M_AXI_UFC_RX_TKEEP     : out std_logic_vector(7 downto 0);
         M_AXI_UFC_RX_TVALID    : out std_logic;
         M_AXI_UFC_RX_TLAST     : out std_logic;

         -- GTX Serial I/O
         RXP                    : in  std_logic_vector(0 to 3);
         RXN                    : in  std_logic_vector(0 to 3); 

         -- GT Reference Clock Interface

         gt_refclk1             : in std_logic;

         -- Error Detection Interface
         RX_HARD_ERR            : out std_logic;
         SOFT_ERR               : out std_logic;

         -- Status
         RX_CHANNEL_UP          : out std_logic;
         RX_LANE_UP             : out std_logic_vector(0 to 3);

               
         FRAME_ERR              : out std_logic;




         -- System Interface

         USER_CLK         : in std_logic;
         SYNC_CLK         : in std_logic;
         GT_RESET         : in std_logic;
         RX_SYSTEM_RESET  : in std_logic;
         sys_reset_out    : out std_logic;
         POWER_DOWN       : in std_logic;
         LOOPBACK         : in std_logic_vector(2 downto 0);
         TX_OUT_CLK       : out std_logic;
         INIT_CLK_IN         : in  std_logic; 
         PLL_NOT_LOCKED      : in  std_logic;
         RX_RESETDONE_OUT    : out std_logic;
         LINK_RESET_OUT      : out std_logic;

    gt0_cplllock_out                     : out std_logic;


    gt0_rxlpmen_in                              : in   std_logic;
    gt0_rxcdrovrden_in                          : in   std_logic;
    gt0_rxdfelpmreset_in                        : in   std_logic;
    gt0_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt0_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt0_rxcdrhold_in                            : in   std_logic;
    gt0_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt0_eyescandataerror_out                    : out  std_logic;
    gt0_eyescantrigger_in                       : in   std_logic;
    gt0_rxbyteisaligned_out                     : out  std_logic;
    gt0_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt0_rxprbserr_out                           : out  std_logic;
    gt0_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt0_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt0_rxpcsreset_in                           : in   std_logic;
    gt0_rxpmareset_in                           : in   std_logic;
    gt0_rxpmaresetdone_out                      : out    std_logic;
    gt0_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt0_rxbufreset_in                           : in   std_logic;
    gt0_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt0_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt0_rx_realign_out                          : out  std_logic;
    gt0_rx_buf_err_out                          : out  std_logic;
    gt0_rxresetdone_out                         : out std_logic;
    gt0_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt1_cplllock_out                     : out std_logic;


    gt1_rxlpmen_in                              : in   std_logic;
    gt1_rxcdrovrden_in                          : in   std_logic;
    gt1_rxdfelpmreset_in                        : in   std_logic;
    gt1_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt1_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt1_rxcdrhold_in                            : in   std_logic;
    gt1_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt1_eyescandataerror_out                    : out  std_logic;
    gt1_eyescantrigger_in                       : in   std_logic;
    gt1_rxbyteisaligned_out                     : out  std_logic;
    gt1_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt1_rxprbserr_out                           : out  std_logic;
    gt1_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt1_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt1_rxpcsreset_in                           : in   std_logic;
    gt1_rxpmareset_in                           : in   std_logic;
    gt1_rxpmaresetdone_out                      : out    std_logic;
    gt1_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt1_rxbufreset_in                           : in   std_logic;
    gt1_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt1_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt1_rx_realign_out                          : out  std_logic;
    gt1_rx_buf_err_out                          : out  std_logic;
    gt1_rxresetdone_out                         : out std_logic;
    gt1_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt2_cplllock_out                     : out std_logic;


    gt2_rxlpmen_in                              : in   std_logic;
    gt2_rxcdrovrden_in                          : in   std_logic;
    gt2_rxdfelpmreset_in                        : in   std_logic;
    gt2_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt2_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt2_rxcdrhold_in                            : in   std_logic;
    gt2_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt2_eyescandataerror_out                    : out  std_logic;
    gt2_eyescantrigger_in                       : in   std_logic;
    gt2_rxbyteisaligned_out                     : out  std_logic;
    gt2_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt2_rxprbserr_out                           : out  std_logic;
    gt2_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt2_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt2_rxpcsreset_in                           : in   std_logic;
    gt2_rxpmareset_in                           : in   std_logic;
    gt2_rxpmaresetdone_out                      : out    std_logic;
    gt2_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt2_rxbufreset_in                           : in   std_logic;
    gt2_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt2_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt2_rx_realign_out                          : out  std_logic;
    gt2_rx_buf_err_out                          : out  std_logic;
    gt2_rxresetdone_out                         : out std_logic;
    gt2_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt3_cplllock_out                     : out std_logic;


    gt3_rxlpmen_in                              : in   std_logic;
    gt3_rxcdrovrden_in                          : in   std_logic;
    gt3_rxdfelpmreset_in                        : in   std_logic;
    gt3_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt3_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt3_rxcdrhold_in                            : in   std_logic;
    gt3_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt3_eyescandataerror_out                    : out  std_logic;
    gt3_eyescantrigger_in                       : in   std_logic;
    gt3_rxbyteisaligned_out                     : out  std_logic;
    gt3_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt3_rxprbserr_out                           : out  std_logic;
    gt3_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt3_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt3_rxpcsreset_in                           : in   std_logic;
    gt3_rxpmareset_in                           : in   std_logic;
    gt3_rxpmaresetdone_out                      : out    std_logic;
    gt3_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt3_rxbufreset_in                           : in   std_logic;
    gt3_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt3_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt3_rx_realign_out                          : out  std_logic;
    gt3_rx_buf_err_out                          : out  std_logic;
    gt3_rxresetdone_out                         : out std_logic;
    gt3_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);

         drpclk_in                                    : in   std_logic;
         DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN                                : in   std_logic;
         DRPRDY_OUT                              : out  std_logic;
         DRPWE_IN                                : in   std_logic;
         DRPADDR_IN_LANE1                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN_LANE1                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT_LANE1                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN_LANE1                                : in   std_logic;
         DRPRDY_OUT_LANE1                              : out  std_logic;
         DRPWE_IN_LANE1                                : in   std_logic;
         DRPADDR_IN_LANE2                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN_LANE2                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT_LANE2                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN_LANE2                                : in   std_logic;
         DRPRDY_OUT_LANE2                              : out  std_logic;
         DRPWE_IN_LANE2                                : in   std_logic;
         DRPADDR_IN_LANE3                              : in   std_logic_vector(8 downto 0);
         DRPDI_IN_LANE3                                : in   std_logic_vector(15 downto 0);
         DRPDO_OUT_LANE3                               : out  std_logic_vector(15 downto 0);
         DRPEN_IN_LANE3                                : in   std_logic;
         DRPRDY_OUT_LANE3                              : out  std_logic;
         DRPWE_IN_LANE3                                : in   std_logic;
   	
--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
    ------------------------- Common Block - QPLL Ports ------------------------
      gt1_qplllock_in       :  in  std_logic;
      gt1_qpllrefclklost_in :  in  std_logic;
      gt1_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad2_in    : in  std_logic;
   gt_qpllrefclk_quad2_in : in  std_logic;
   gt_qpllclk_quad3_in    : in  std_logic;
   gt_qpllrefclk_quad3_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}
         TX_LOCK          : out std_logic
    );

    end component;

begin

 --*********************************Main Body of Code**********************************

     U0 : aurora_rx_4l_64b_core
     port map (
        -- AXI TX Interface

        -- AXI RX Interface
        m_axi_rx_tdata               => m_axi_rx_tdata,
        m_axi_rx_tkeep               => m_axi_rx_tkeep,
        m_axi_rx_tvalid              => m_axi_rx_tvalid,
        m_axi_rx_tlast               => m_axi_rx_tlast,


        -- User Flow Control RX Inteface
        m_axi_ufc_rx_tdata           => m_axi_ufc_rx_tdata,
        m_axi_ufc_rx_tkeep           => m_axi_ufc_rx_tkeep,
        m_axi_ufc_rx_tvalid          => m_axi_ufc_rx_tvalid,
        m_axi_ufc_rx_tlast           => m_axi_ufc_rx_tlast,

        -- GT Serial I/O
        rxp                          => rxp,
        rxn                          => rxn,

        -- GT Reference Clock Interface
        gt_refclk1                   => gt_refclk1,
        -- Error Detection Interface
        frame_err                    => frame_err,

        -- Error Detection Interface
        rx_hard_err                  => rx_hard_err,
        soft_err                     => soft_err,
        
        -- Status
        rx_channel_up                => rx_channel_up,
        rx_lane_up                   => rx_lane_up,




        -- System Interface
        user_clk                     => user_clk,
        sync_clk                     => sync_clk,
        rx_system_reset              => rx_system_reset,
        sys_reset_out                => sys_reset_out,
        power_down                   => power_down,
        loopback                     => loopback,
        gt_reset                     => gt_reset,
        tx_lock                      => tx_lock,
        init_clk_in                  => init_clk_in,
        pll_not_locked               => pll_not_locked,
	rx_resetdone_out             => rx_resetdone_out,
        link_reset_out               => link_reset_out,
         gt0_cplllock_out                   => gt0_cplllock_out, 


        -------------------------- RX Margin Analysis Ports ------------------------
         gt0_eyescanreset_in                => gt0_eyescanreset_in,
         gt0_eyescandataerror_out           => gt0_eyescandataerror_out,
         gt0_eyescantrigger_in              => gt0_eyescantrigger_in,

         gt0_rxlpmen_in                     => gt0_rxlpmen_in,
         gt0_rxcdrovrden_in                 => gt0_rxcdrovrden_in,
         gt0_rxdfelpmreset_in               => gt0_rxdfelpmreset_in,
         gt0_rxmonitorout_out               => gt0_rxmonitorout_out,
         gt0_rxmonitorsel_in                => gt0_rxmonitorsel_in,
         gt0_rxcdrhold_in                   => gt0_rxcdrhold_in,
         gt0_rxbyteisaligned_out            => gt0_rxbyteisaligned_out,
         gt0_rxcommadet_out                 => gt0_rxcommadet_out,
         gt0_rx_disp_err_out                => gt0_rx_disp_err_out,
         gt0_rx_not_in_table_out            => gt0_rx_not_in_table_out,
         gt0_rx_realign_out                 => gt0_rx_realign_out,
         gt0_rx_buf_err_out                 => gt0_rx_buf_err_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt0_rxprbserr_out               => gt0_rxprbserr_out,
        gt0_rxprbssel_in                => gt0_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt0_rxprbscntreset_in           => gt0_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt0_rxpcsreset_in               => gt0_rxpcsreset_in,
        gt0_rxpmareset_in               => gt0_rxpmareset_in,
        gt0_dmonitorout_out             => gt0_dmonitorout_out,
        gt0_rxpmaresetdone_out          => gt0_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt0_rxbufreset_in               => gt0_rxbufreset_in,
        gt0_rxresetdone_out             => gt0_rxresetdone_out,
        gt0_rxbufstatus_out             => gt0_rxbufstatus_out,
         gt1_cplllock_out                   => gt1_cplllock_out, 


        -------------------------- RX Margin Analysis Ports ------------------------
         gt1_eyescanreset_in                => gt1_eyescanreset_in,
         gt1_eyescandataerror_out           => gt1_eyescandataerror_out,
         gt1_eyescantrigger_in              => gt1_eyescantrigger_in,

         gt1_rxlpmen_in                     => gt1_rxlpmen_in,
         gt1_rxcdrovrden_in                 => gt1_rxcdrovrden_in,
         gt1_rxdfelpmreset_in               => gt1_rxdfelpmreset_in,
         gt1_rxmonitorout_out               => gt1_rxmonitorout_out,
         gt1_rxmonitorsel_in                => gt1_rxmonitorsel_in,
         gt1_rxcdrhold_in                   => gt1_rxcdrhold_in,
         gt1_rxbyteisaligned_out            => gt1_rxbyteisaligned_out,
         gt1_rxcommadet_out                 => gt1_rxcommadet_out,
         gt1_rx_disp_err_out                => gt1_rx_disp_err_out,
         gt1_rx_not_in_table_out            => gt1_rx_not_in_table_out,
         gt1_rx_realign_out                 => gt1_rx_realign_out,
         gt1_rx_buf_err_out                 => gt1_rx_buf_err_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt1_rxprbserr_out               => gt1_rxprbserr_out,
        gt1_rxprbssel_in                => gt1_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt1_rxprbscntreset_in           => gt1_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt1_rxpcsreset_in               => gt1_rxpcsreset_in,
        gt1_rxpmareset_in               => gt1_rxpmareset_in,
        gt1_dmonitorout_out             => gt1_dmonitorout_out,
        gt1_rxpmaresetdone_out          => gt1_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt1_rxbufreset_in               => gt1_rxbufreset_in,
        gt1_rxresetdone_out             => gt1_rxresetdone_out,
        gt1_rxbufstatus_out             => gt1_rxbufstatus_out,
         gt2_cplllock_out                   => gt2_cplllock_out, 


        -------------------------- RX Margin Analysis Ports ------------------------
         gt2_eyescanreset_in                => gt2_eyescanreset_in,
         gt2_eyescandataerror_out           => gt2_eyescandataerror_out,
         gt2_eyescantrigger_in              => gt2_eyescantrigger_in,

         gt2_rxlpmen_in                     => gt2_rxlpmen_in,
         gt2_rxcdrovrden_in                 => gt2_rxcdrovrden_in,
         gt2_rxdfelpmreset_in               => gt2_rxdfelpmreset_in,
         gt2_rxmonitorout_out               => gt2_rxmonitorout_out,
         gt2_rxmonitorsel_in                => gt2_rxmonitorsel_in,
         gt2_rxcdrhold_in                   => gt2_rxcdrhold_in,
         gt2_rxbyteisaligned_out            => gt2_rxbyteisaligned_out,
         gt2_rxcommadet_out                 => gt2_rxcommadet_out,
         gt2_rx_disp_err_out                => gt2_rx_disp_err_out,
         gt2_rx_not_in_table_out            => gt2_rx_not_in_table_out,
         gt2_rx_realign_out                 => gt2_rx_realign_out,
         gt2_rx_buf_err_out                 => gt2_rx_buf_err_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt2_rxprbserr_out               => gt2_rxprbserr_out,
        gt2_rxprbssel_in                => gt2_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt2_rxprbscntreset_in           => gt2_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt2_rxpcsreset_in               => gt2_rxpcsreset_in,
        gt2_rxpmareset_in               => gt2_rxpmareset_in,
        gt2_dmonitorout_out             => gt2_dmonitorout_out,
        gt2_rxpmaresetdone_out          => gt2_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt2_rxbufreset_in               => gt2_rxbufreset_in,
        gt2_rxresetdone_out             => gt2_rxresetdone_out,
        gt2_rxbufstatus_out             => gt2_rxbufstatus_out,
         gt3_cplllock_out                   => gt3_cplllock_out, 


        -------------------------- RX Margin Analysis Ports ------------------------
         gt3_eyescanreset_in                => gt3_eyescanreset_in,
         gt3_eyescandataerror_out           => gt3_eyescandataerror_out,
         gt3_eyescantrigger_in              => gt3_eyescantrigger_in,

         gt3_rxlpmen_in                     => gt3_rxlpmen_in,
         gt3_rxcdrovrden_in                 => gt3_rxcdrovrden_in,
         gt3_rxdfelpmreset_in               => gt3_rxdfelpmreset_in,
         gt3_rxmonitorout_out               => gt3_rxmonitorout_out,
         gt3_rxmonitorsel_in                => gt3_rxmonitorsel_in,
         gt3_rxcdrhold_in                   => gt3_rxcdrhold_in,
         gt3_rxbyteisaligned_out            => gt3_rxbyteisaligned_out,
         gt3_rxcommadet_out                 => gt3_rxcommadet_out,
         gt3_rx_disp_err_out                => gt3_rx_disp_err_out,
         gt3_rx_not_in_table_out            => gt3_rx_not_in_table_out,
         gt3_rx_realign_out                 => gt3_rx_realign_out,
         gt3_rx_buf_err_out                 => gt3_rx_buf_err_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt3_rxprbserr_out               => gt3_rxprbserr_out,
        gt3_rxprbssel_in                => gt3_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt3_rxprbscntreset_in           => gt3_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt3_rxpcsreset_in               => gt3_rxpcsreset_in,
        gt3_rxpmareset_in               => gt3_rxpmareset_in,
        gt3_dmonitorout_out             => gt3_dmonitorout_out,
        gt3_rxpmaresetdone_out          => gt3_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt3_rxbufreset_in               => gt3_rxbufreset_in,
        gt3_rxresetdone_out             => gt3_rxresetdone_out,
        gt3_rxbufstatus_out             => gt3_rxbufstatus_out,
        drpclk_in                    => drpclk_in,
        drpaddr_in                   => drpaddr_in,
        drpen_in                     => drpen_in,
        drpdi_in                     => drpdi_in,
        drprdy_out                   => drprdy_out, 
        drpdo_out                    => drpdo_out,
        drpwe_in                     => drpwe_in,
        drpaddr_in_lane1                   => drpaddr_in_lane1,
        drpen_in_lane1                     => drpen_in_lane1,
        drpdi_in_lane1                     => drpdi_in_lane1,
        drprdy_out_lane1                   => drprdy_out_lane1, 
        drpdo_out_lane1                    => drpdo_out_lane1,
        drpwe_in_lane1                     => drpwe_in_lane1,
        drpaddr_in_lane2                   => drpaddr_in_lane2,
        drpen_in_lane2                     => drpen_in_lane2,
        drpdi_in_lane2                     => drpdi_in_lane2,
        drprdy_out_lane2                   => drprdy_out_lane2, 
        drpdo_out_lane2                    => drpdo_out_lane2,
        drpwe_in_lane2                     => drpwe_in_lane2,
        drpaddr_in_lane3                   => drpaddr_in_lane3,
        drpen_in_lane3                     => drpen_in_lane3,
        drpdi_in_lane3                     => drpdi_in_lane3,
        drprdy_out_lane3                   => drprdy_out_lane3, 
        drpdo_out_lane3                    => drpdo_out_lane3,
        drpwe_in_lane3                     => drpwe_in_lane3,
--------------------{
--____________________________COMMON PORTS INST_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in        =>  gt0_qplllock_in,
      gt0_qpllrefclklost_in  =>  gt0_qpllrefclklost_in,
      gt0_qpllreset_out      =>  gt0_qpllreset_out,
    ------------------------- Common Block - QPLL Ports ------------------------
      gt1_qplllock_in        =>  gt1_qplllock_in,
      gt1_qpllrefclklost_in  =>  gt1_qpllrefclklost_in,
      gt1_qpllreset_out      =>  gt1_qpllreset_out,
        gt_qpllclk_quad2_in     => gt_qpllclk_quad2_in    ,
        gt_qpllrefclk_quad2_in  => gt_qpllrefclk_quad2_in ,
        gt_qpllclk_quad3_in     => gt_qpllclk_quad3_in    ,
        gt_qpllrefclk_quad3_in  => gt_qpllrefclk_quad3_in ,
--____________________________COMMON PORTS INST_______________________________}
--------------------}
        tx_out_clk                   => tx_out_clk

     );

 end STRUCTURE;
