-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
-- Date        : Mon May 13 11:36:00 2024
-- Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
-- Command     : write_vhdl -force -mode funcsim
--               /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_sim_netlist.vhdl
-- Design      : aurora_rx_4l_64b
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx550tffg1927-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_LEFT_ALIGN_CONTROL is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    D : in STD_LOGIC_VECTOR ( 4 downto 0 );
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_LEFT_ALIGN_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_LEFT_ALIGN_CONTROL is
begin
\MUX_SELECT_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(4),
      Q => Q(4),
      R => '0'
    );
\MUX_SELECT_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => Q(3),
      R => '0'
    );
\MUX_SELECT_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => Q(2),
      R => '0'
    );
\MUX_SELECT_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\MUX_SELECT_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_LEFT_ALIGN_MUX is
  port (
    \MUXED_DATA_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \MUXED_DATA_Buffer_reg[0]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_LEFT_ALIGN_MUX;

architecture STRUCTURE of aurora_rx_4l_64b_LEFT_ALIGN_MUX is
  signal muxed_data_c : STD_LOGIC_VECTOR ( 0 to 47 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[32]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[33]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[34]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[35]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[36]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[37]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[38]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[39]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[40]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[41]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[42]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[43]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[44]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[45]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[46]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \MUXED_DATA_Buffer[47]_i_1\ : label is "soft_lutpair99";
begin
\MUXED_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(47),
      I1 => Q(63),
      I2 => Q(15),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(31),
      O => muxed_data_c(0)
    );
\MUXED_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(37),
      I1 => Q(53),
      I2 => Q(5),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(21),
      O => muxed_data_c(10)
    );
\MUXED_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(36),
      I1 => Q(52),
      I2 => Q(4),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(20),
      O => muxed_data_c(11)
    );
\MUXED_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(35),
      I1 => Q(51),
      I2 => Q(3),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(19),
      O => muxed_data_c(12)
    );
\MUXED_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(34),
      I1 => Q(50),
      I2 => Q(2),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(18),
      O => muxed_data_c(13)
    );
\MUXED_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(33),
      I1 => Q(49),
      I2 => Q(1),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(17),
      O => muxed_data_c(14)
    );
\MUXED_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(32),
      I1 => Q(48),
      I2 => Q(0),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(16),
      O => muxed_data_c(15)
    );
\MUXED_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(31),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(15),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(47),
      O => muxed_data_c(16)
    );
\MUXED_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(30),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(14),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(46),
      O => muxed_data_c(17)
    );
\MUXED_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(29),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(13),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(45),
      O => muxed_data_c(18)
    );
\MUXED_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(28),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(12),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(44),
      O => muxed_data_c(19)
    );
\MUXED_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(46),
      I1 => Q(62),
      I2 => Q(14),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(30),
      O => muxed_data_c(1)
    );
\MUXED_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(27),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(11),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(43),
      O => muxed_data_c(20)
    );
\MUXED_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(26),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(10),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(42),
      O => muxed_data_c(21)
    );
\MUXED_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(25),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(9),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(41),
      O => muxed_data_c(22)
    );
\MUXED_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(24),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(8),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(40),
      O => muxed_data_c(23)
    );
\MUXED_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(23),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(7),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(39),
      O => muxed_data_c(24)
    );
\MUXED_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(22),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(6),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(38),
      O => muxed_data_c(25)
    );
\MUXED_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(21),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(5),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(37),
      O => muxed_data_c(26)
    );
\MUXED_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(20),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(4),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(36),
      O => muxed_data_c(27)
    );
\MUXED_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(19),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(3),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(35),
      O => muxed_data_c(28)
    );
\MUXED_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(18),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(2),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(34),
      O => muxed_data_c(29)
    );
\MUXED_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(45),
      I1 => Q(61),
      I2 => Q(13),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(29),
      O => muxed_data_c(2)
    );
\MUXED_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(17),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(1),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(33),
      O => muxed_data_c(30)
    );
\MUXED_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => Q(16),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(1),
      I2 => Q(0),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(2),
      I4 => Q(32),
      O => muxed_data_c(31)
    );
\MUXED_DATA_Buffer[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(15),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(31),
      O => muxed_data_c(32)
    );
\MUXED_DATA_Buffer[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(14),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(30),
      O => muxed_data_c(33)
    );
\MUXED_DATA_Buffer[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(13),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(29),
      O => muxed_data_c(34)
    );
\MUXED_DATA_Buffer[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(12),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(28),
      O => muxed_data_c(35)
    );
\MUXED_DATA_Buffer[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(11),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(27),
      O => muxed_data_c(36)
    );
\MUXED_DATA_Buffer[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(10),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(26),
      O => muxed_data_c(37)
    );
\MUXED_DATA_Buffer[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(9),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(25),
      O => muxed_data_c(38)
    );
\MUXED_DATA_Buffer[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(8),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(24),
      O => muxed_data_c(39)
    );
\MUXED_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(44),
      I1 => Q(60),
      I2 => Q(12),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(28),
      O => muxed_data_c(3)
    );
\MUXED_DATA_Buffer[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(7),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(23),
      O => muxed_data_c(40)
    );
\MUXED_DATA_Buffer[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(6),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(22),
      O => muxed_data_c(41)
    );
\MUXED_DATA_Buffer[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(5),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(21),
      O => muxed_data_c(42)
    );
\MUXED_DATA_Buffer[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(4),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(20),
      O => muxed_data_c(43)
    );
\MUXED_DATA_Buffer[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(3),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(19),
      O => muxed_data_c(44)
    );
\MUXED_DATA_Buffer[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(2),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(18),
      O => muxed_data_c(45)
    );
\MUXED_DATA_Buffer[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(17),
      O => muxed_data_c(46)
    );
\MUXED_DATA_Buffer[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => \MUXED_DATA_Buffer_reg[0]_1\(0),
      I2 => Q(16),
      O => muxed_data_c(47)
    );
\MUXED_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(43),
      I1 => Q(59),
      I2 => Q(11),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(27),
      O => muxed_data_c(4)
    );
\MUXED_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(42),
      I1 => Q(58),
      I2 => Q(10),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(26),
      O => muxed_data_c(5)
    );
\MUXED_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(41),
      I1 => Q(57),
      I2 => Q(9),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(25),
      O => muxed_data_c(6)
    );
\MUXED_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(40),
      I1 => Q(56),
      I2 => Q(8),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(24),
      O => muxed_data_c(7)
    );
\MUXED_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(39),
      I1 => Q(55),
      I2 => Q(7),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(23),
      O => muxed_data_c(8)
    );
\MUXED_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => Q(38),
      I1 => Q(54),
      I2 => Q(6),
      I3 => \MUXED_DATA_Buffer_reg[0]_1\(4),
      I4 => \MUXED_DATA_Buffer_reg[0]_1\(3),
      I5 => Q(22),
      O => muxed_data_c(9)
    );
\MUXED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(0),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(63),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(10),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(53),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(11),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(52),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(12),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(51),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(13),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(50),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(14),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(49),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(15),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(48),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(16),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(47),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(17),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(46),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(18),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(45),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(19),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(44),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(1),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(62),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(20),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(43),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(21),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(42),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(22),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(41),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(23),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(40),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(24),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(39),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(25),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(38),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(26),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(37),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(27),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(36),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(28),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(35),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(29),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(34),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(2),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(61),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(30),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(33),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(31),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(32),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(32),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(31),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(33),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(30),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(34),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(29),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(35),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(28),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(36),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(27),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(37),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(26),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(38),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(25),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(39),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(24),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(3),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(60),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(40),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(23),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(41),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(22),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(42),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(21),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(43),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(20),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(44),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(19),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(45),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(18),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(46),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(17),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(47),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(16),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(15),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(15),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(14),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(14),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(4),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(59),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(13),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(13),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(12),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(12),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(11),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(11),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(10),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(10),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(9),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(9),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(8),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(8),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(7),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(7),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(6),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(6),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(5),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(5),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(4),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(4),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(5),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(58),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(3),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(3),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(2),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(2),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(1),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(1),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(0),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(6),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(57),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(7),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(56),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(8),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(55),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => muxed_data_c(9),
      Q => \MUXED_DATA_Buffer_reg[0]_0\(54),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_LL_TO_AXI is
  port (
    M_AXI_RX_TKEEP : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RX_EOF_N : in STD_LOGIC;
    RX_REM : in STD_LOGIC_VECTOR ( 0 to 2 )
  );
end aurora_rx_4l_64b_LL_TO_AXI;

architecture STRUCTURE of aurora_rx_4l_64b_LL_TO_AXI is
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[1]_INST_0\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[2]_INST_0\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[3]_INST_0\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[5]_INST_0\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[6]_INST_0\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \M_AXI_RX_TKEEP[7]_INST_0\ : label is "soft_lutpair1";
begin
\M_AXI_RX_TKEEP[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => RX_EOF_N,
      I1 => RX_REM(0),
      I2 => RX_REM(1),
      I3 => RX_REM(2),
      O => M_AXI_RX_TKEEP(0)
    );
\M_AXI_RX_TKEEP[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => RX_EOF_N,
      I1 => RX_REM(0),
      I2 => RX_REM(1),
      O => M_AXI_RX_TKEEP(1)
    );
\M_AXI_RX_TKEEP[3]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEA"
    )
        port map (
      I0 => RX_EOF_N,
      I1 => RX_REM(2),
      I2 => RX_REM(1),
      I3 => RX_REM(0),
      O => M_AXI_RX_TKEEP(2)
    );
\M_AXI_RX_TKEEP[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => RX_EOF_N,
      I1 => RX_REM(0),
      O => M_AXI_RX_TKEEP(3)
    );
\M_AXI_RX_TKEEP[5]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEEA"
    )
        port map (
      I0 => RX_EOF_N,
      I1 => RX_REM(0),
      I2 => RX_REM(1),
      I3 => RX_REM(2),
      O => M_AXI_RX_TKEEP(4)
    );
\M_AXI_RX_TKEEP[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => RX_EOF_N,
      I1 => RX_REM(1),
      I2 => RX_REM(0),
      O => M_AXI_RX_TKEEP(5)
    );
\M_AXI_RX_TKEEP[7]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => RX_EOF_N,
      I1 => RX_REM(2),
      I2 => RX_REM(0),
      I3 => RX_REM(1),
      O => M_AXI_RX_TKEEP(6)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_LL_TO_AXI__parameterized1\ is
  port (
    M_AXI_UFC_RX_TKEEP : out STD_LOGIC_VECTOR ( 2 downto 0 );
    UFC_RX_EOF_N : in STD_LOGIC;
    UFC_RX_REM : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_LL_TO_AXI__parameterized1\ : entity is "aurora_rx_4l_64b_LL_TO_AXI";
end \aurora_rx_4l_64b_LL_TO_AXI__parameterized1\;

architecture STRUCTURE of \aurora_rx_4l_64b_LL_TO_AXI__parameterized1\ is
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \M_AXI_UFC_RX_TKEEP[2]_INST_0\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \M_AXI_UFC_RX_TKEEP[6]_INST_0\ : label is "soft_lutpair3";
begin
\M_AXI_UFC_RX_TKEEP[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => UFC_RX_EOF_N,
      I1 => UFC_RX_REM(0),
      I2 => UFC_RX_REM(1),
      O => M_AXI_UFC_RX_TKEEP(0)
    );
\M_AXI_UFC_RX_TKEEP[4]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => UFC_RX_EOF_N,
      I1 => UFC_RX_REM(1),
      O => M_AXI_UFC_RX_TKEEP(1)
    );
\M_AXI_UFC_RX_TKEEP[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => UFC_RX_EOF_N,
      I1 => UFC_RX_REM(1),
      I2 => UFC_RX_REM(0),
      O => M_AXI_UFC_RX_TKEEP(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_OUTPUT_MUX is
  port (
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk : in STD_LOGIC;
    \OUTPUT_DATA_Buffer_reg[48]_0\ : in STD_LOGIC_VECTOR ( 47 downto 0 );
    OUTPUT_SELECT_Buffer : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
end aurora_rx_4l_64b_OUTPUT_MUX;

architecture STRUCTURE of aurora_rx_4l_64b_OUTPUT_MUX is
  signal output_data_c : STD_LOGIC_VECTOR ( 16 to 63 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[16]_i_1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[17]_i_1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[18]_i_1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[19]_i_1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[20]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[21]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[22]_i_1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[23]_i_1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[24]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[25]_i_1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[26]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[27]_i_1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[28]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[29]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[30]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \OUTPUT_DATA_Buffer[31]_i_1\ : label is "soft_lutpair85";
begin
\OUTPUT_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(47),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(47),
      O => output_data_c(16)
    );
\OUTPUT_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(46),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(46),
      O => output_data_c(17)
    );
\OUTPUT_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(45),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(45),
      O => output_data_c(18)
    );
\OUTPUT_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(44),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(44),
      O => output_data_c(19)
    );
\OUTPUT_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(43),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(43),
      O => output_data_c(20)
    );
\OUTPUT_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(42),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(42),
      O => output_data_c(21)
    );
\OUTPUT_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(41),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(41),
      O => output_data_c(22)
    );
\OUTPUT_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(40),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(40),
      O => output_data_c(23)
    );
\OUTPUT_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(39),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(39),
      O => output_data_c(24)
    );
\OUTPUT_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(38),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(38),
      O => output_data_c(25)
    );
\OUTPUT_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(37),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(37),
      O => output_data_c(26)
    );
\OUTPUT_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(36),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(36),
      O => output_data_c(27)
    );
\OUTPUT_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(35),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(35),
      O => output_data_c(28)
    );
\OUTPUT_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(34),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(34),
      O => output_data_c(29)
    );
\OUTPUT_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(33),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(33),
      O => output_data_c(30)
    );
\OUTPUT_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(32),
      I1 => OUTPUT_SELECT_Buffer(3),
      I2 => Q(32),
      O => output_data_c(31)
    );
\OUTPUT_DATA_Buffer[32]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(47),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(31),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(31),
      O => output_data_c(32)
    );
\OUTPUT_DATA_Buffer[33]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(46),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(30),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(30),
      O => output_data_c(33)
    );
\OUTPUT_DATA_Buffer[34]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(45),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(29),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(29),
      O => output_data_c(34)
    );
\OUTPUT_DATA_Buffer[35]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(44),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(28),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(28),
      O => output_data_c(35)
    );
\OUTPUT_DATA_Buffer[36]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(43),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(27),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(27),
      O => output_data_c(36)
    );
\OUTPUT_DATA_Buffer[37]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(42),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(26),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(26),
      O => output_data_c(37)
    );
\OUTPUT_DATA_Buffer[38]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(41),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(25),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(25),
      O => output_data_c(38)
    );
\OUTPUT_DATA_Buffer[39]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(40),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(24),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(24),
      O => output_data_c(39)
    );
\OUTPUT_DATA_Buffer[40]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(39),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(23),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(23),
      O => output_data_c(40)
    );
\OUTPUT_DATA_Buffer[41]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(38),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(22),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(22),
      O => output_data_c(41)
    );
\OUTPUT_DATA_Buffer[42]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(37),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(21),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(21),
      O => output_data_c(42)
    );
\OUTPUT_DATA_Buffer[43]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(36),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(20),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(20),
      O => output_data_c(43)
    );
\OUTPUT_DATA_Buffer[44]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(35),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(19),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(19),
      O => output_data_c(44)
    );
\OUTPUT_DATA_Buffer[45]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(34),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(18),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(18),
      O => output_data_c(45)
    );
\OUTPUT_DATA_Buffer[46]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(33),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(17),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(17),
      O => output_data_c(46)
    );
\OUTPUT_DATA_Buffer[47]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(32),
      I1 => OUTPUT_SELECT_Buffer(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(16),
      I3 => OUTPUT_SELECT_Buffer(3),
      I4 => Q(16),
      O => output_data_c(47)
    );
\OUTPUT_DATA_Buffer[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(47),
      I1 => Q(15),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(15),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(31),
      O => output_data_c(48)
    );
\OUTPUT_DATA_Buffer[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(46),
      I1 => Q(14),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(14),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(30),
      O => output_data_c(49)
    );
\OUTPUT_DATA_Buffer[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(45),
      I1 => Q(13),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(13),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(29),
      O => output_data_c(50)
    );
\OUTPUT_DATA_Buffer[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(44),
      I1 => Q(12),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(12),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(28),
      O => output_data_c(51)
    );
\OUTPUT_DATA_Buffer[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(43),
      I1 => Q(11),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(11),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(27),
      O => output_data_c(52)
    );
\OUTPUT_DATA_Buffer[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(42),
      I1 => Q(10),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(10),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(26),
      O => output_data_c(53)
    );
\OUTPUT_DATA_Buffer[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(41),
      I1 => Q(9),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(9),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(25),
      O => output_data_c(54)
    );
\OUTPUT_DATA_Buffer[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(40),
      I1 => Q(8),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(8),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(24),
      O => output_data_c(55)
    );
\OUTPUT_DATA_Buffer[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(39),
      I1 => Q(7),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(7),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(23),
      O => output_data_c(56)
    );
\OUTPUT_DATA_Buffer[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(38),
      I1 => Q(6),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(6),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(22),
      O => output_data_c(57)
    );
\OUTPUT_DATA_Buffer[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(37),
      I1 => Q(5),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(5),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(21),
      O => output_data_c(58)
    );
\OUTPUT_DATA_Buffer[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(36),
      I1 => Q(4),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(4),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(20),
      O => output_data_c(59)
    );
\OUTPUT_DATA_Buffer[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(35),
      I1 => Q(3),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(3),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(19),
      O => output_data_c(60)
    );
\OUTPUT_DATA_Buffer[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(34),
      I1 => Q(2),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(2),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(18),
      O => output_data_c(61)
    );
\OUTPUT_DATA_Buffer[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(33),
      I1 => Q(1),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(1),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(17),
      O => output_data_c(62)
    );
\OUTPUT_DATA_Buffer[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \OUTPUT_DATA_Buffer_reg[48]_0\(32),
      I1 => Q(0),
      I2 => \OUTPUT_DATA_Buffer_reg[48]_0\(0),
      I3 => OUTPUT_SELECT_Buffer(1),
      I4 => OUTPUT_SELECT_Buffer(0),
      I5 => \OUTPUT_DATA_Buffer_reg[48]_0\(16),
      O => output_data_c(63)
    );
\OUTPUT_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(63),
      Q => M_AXI_RX_TDATA(7),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(53),
      Q => M_AXI_RX_TDATA(13),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(52),
      Q => M_AXI_RX_TDATA(12),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(51),
      Q => M_AXI_RX_TDATA(11),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(50),
      Q => M_AXI_RX_TDATA(10),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(49),
      Q => M_AXI_RX_TDATA(9),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(48),
      Q => M_AXI_RX_TDATA(8),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(16),
      Q => M_AXI_RX_TDATA(23),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(17),
      Q => M_AXI_RX_TDATA(22),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(18),
      Q => M_AXI_RX_TDATA(21),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(19),
      Q => M_AXI_RX_TDATA(20),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(62),
      Q => M_AXI_RX_TDATA(6),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(20),
      Q => M_AXI_RX_TDATA(19),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(21),
      Q => M_AXI_RX_TDATA(18),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(22),
      Q => M_AXI_RX_TDATA(17),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(23),
      Q => M_AXI_RX_TDATA(16),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(24),
      Q => M_AXI_RX_TDATA(31),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(25),
      Q => M_AXI_RX_TDATA(30),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(26),
      Q => M_AXI_RX_TDATA(29),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(27),
      Q => M_AXI_RX_TDATA(28),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(28),
      Q => M_AXI_RX_TDATA(27),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(29),
      Q => M_AXI_RX_TDATA(26),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(61),
      Q => M_AXI_RX_TDATA(5),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(30),
      Q => M_AXI_RX_TDATA(25),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(31),
      Q => M_AXI_RX_TDATA(24),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(32),
      Q => M_AXI_RX_TDATA(39),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(33),
      Q => M_AXI_RX_TDATA(38),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(34),
      Q => M_AXI_RX_TDATA(37),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(35),
      Q => M_AXI_RX_TDATA(36),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(36),
      Q => M_AXI_RX_TDATA(35),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(37),
      Q => M_AXI_RX_TDATA(34),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(38),
      Q => M_AXI_RX_TDATA(33),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(39),
      Q => M_AXI_RX_TDATA(32),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(60),
      Q => M_AXI_RX_TDATA(4),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(40),
      Q => M_AXI_RX_TDATA(47),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(41),
      Q => M_AXI_RX_TDATA(46),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(42),
      Q => M_AXI_RX_TDATA(45),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(43),
      Q => M_AXI_RX_TDATA(44),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(44),
      Q => M_AXI_RX_TDATA(43),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(45),
      Q => M_AXI_RX_TDATA(42),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(46),
      Q => M_AXI_RX_TDATA(41),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(47),
      Q => M_AXI_RX_TDATA(40),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(48),
      Q => M_AXI_RX_TDATA(55),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(49),
      Q => M_AXI_RX_TDATA(54),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(59),
      Q => M_AXI_RX_TDATA(3),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(50),
      Q => M_AXI_RX_TDATA(53),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(51),
      Q => M_AXI_RX_TDATA(52),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(52),
      Q => M_AXI_RX_TDATA(51),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(53),
      Q => M_AXI_RX_TDATA(50),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(54),
      Q => M_AXI_RX_TDATA(49),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(55),
      Q => M_AXI_RX_TDATA(48),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(56),
      Q => M_AXI_RX_TDATA(63),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(57),
      Q => M_AXI_RX_TDATA(62),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(58),
      Q => M_AXI_RX_TDATA(61),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(59),
      Q => M_AXI_RX_TDATA(60),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(58),
      Q => M_AXI_RX_TDATA(2),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(60),
      Q => M_AXI_RX_TDATA(59),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(61),
      Q => M_AXI_RX_TDATA(58),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(62),
      Q => M_AXI_RX_TDATA(57),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => output_data_c(63),
      Q => M_AXI_RX_TDATA(56),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(57),
      Q => M_AXI_RX_TDATA(1),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(56),
      Q => M_AXI_RX_TDATA(0),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(55),
      Q => M_AXI_RX_TDATA(15),
      R => '0'
    );
\OUTPUT_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(54),
      Q => M_AXI_RX_TDATA(14),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL is
  port (
    OUTPUT_SELECT_Buffer : out STD_LOGIC_VECTOR ( 3 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
end aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL is
begin
\OUTPUT_SELECT_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => OUTPUT_SELECT_Buffer(3),
      R => SR(0)
    );
\OUTPUT_SELECT_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => OUTPUT_SELECT_Buffer(2),
      R => SR(0)
    );
\OUTPUT_SELECT_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => OUTPUT_SELECT_Buffer(1),
      R => SR(0)
    );
\OUTPUT_SELECT_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => OUTPUT_SELECT_Buffer(0),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX is
  port (
    SOFT_ERR : out STD_LOGIC;
    RX_HARD_ERR : out STD_LOGIC;
    reset_channel_i : out STD_LOGIC;
    wait_for_lane_up_r0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    \soft_err_r_reg[0]_0\ : in STD_LOGIC;
    \soft_err_r_reg[1]_0\ : in STD_LOGIC;
    \soft_err_r_reg[2]_0\ : in STD_LOGIC;
    \soft_err_r_reg[3]_0\ : in STD_LOGIC;
    wait_for_lane_up_r_reg : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    \hard_err_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    RX_LANE_UP : in STD_LOGIC_VECTOR ( 0 to 3 )
  );
end aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX;

architecture STRUCTURE of aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX is
  signal RESET_CHANNEL_Buffer0 : STD_LOGIC;
  signal \channel_hard_err_c__0\ : STD_LOGIC;
  signal \channel_soft_err_c__0\ : STD_LOGIC;
  signal \hard_err_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \hard_err_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \lane_up_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \lane_up_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \lane_up_r_reg_n_0_[3]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_1_in2_in : STD_LOGIC;
  signal p_1_in5_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal \^reset_channel_i\ : STD_LOGIC;
  signal \soft_err_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \soft_err_r_reg_n_0_[3]\ : STD_LOGIC;
begin
  reset_channel_i <= \^reset_channel_i\;
CHANNEL_HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \channel_hard_err_c__0\,
      Q => RX_HARD_ERR,
      R => '0'
    );
CHANNEL_SOFT_ERR_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \channel_soft_err_c__0\,
      Q => SOFT_ERR,
      R => '0'
    );
RESET_CHANNEL_Buffer_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => \lane_up_r_reg_n_0_[2]\,
      I1 => p_2_in,
      I2 => \lane_up_r_reg_n_0_[0]\,
      I3 => \lane_up_r_reg_n_0_[3]\,
      I4 => POWER_DOWN,
      O => RESET_CHANNEL_Buffer0
    );
RESET_CHANNEL_Buffer_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => RESET_CHANNEL_Buffer0,
      Q => \^reset_channel_i\,
      R => '0'
    );
channel_hard_err_c: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \hard_err_r_reg_n_0_[3]\,
      I1 => \hard_err_r_reg_n_0_[0]\,
      I2 => p_0_in,
      I3 => p_1_in2_in,
      O => \channel_hard_err_c__0\
    );
channel_soft_err_c: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \soft_err_r_reg_n_0_[3]\,
      I1 => \soft_err_r_reg_n_0_[0]\,
      I2 => p_0_in4_in,
      I3 => p_1_in5_in,
      O => \channel_soft_err_c__0\
    );
\hard_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \hard_err_r_reg[0]_0\(3),
      Q => \hard_err_r_reg_n_0_[0]\,
      R => '0'
    );
\hard_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \hard_err_r_reg[0]_0\(2),
      Q => p_0_in,
      R => '0'
    );
\hard_err_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \hard_err_r_reg[0]_0\(1),
      Q => p_1_in2_in,
      R => '0'
    );
\hard_err_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \hard_err_r_reg[0]_0\(0),
      Q => \hard_err_r_reg_n_0_[3]\,
      R => '0'
    );
\lane_up_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_LANE_UP(0),
      Q => \lane_up_r_reg_n_0_[0]\,
      R => '0'
    );
\lane_up_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_LANE_UP(1),
      Q => p_2_in,
      R => '0'
    );
\lane_up_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_LANE_UP(2),
      Q => \lane_up_r_reg_n_0_[2]\,
      R => '0'
    );
\lane_up_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_LANE_UP(3),
      Q => \lane_up_r_reg_n_0_[3]\,
      R => '0'
    );
\soft_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\,
      Q => \soft_err_r_reg_n_0_[0]\,
      R => '0'
    );
\soft_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[1]_0\,
      Q => p_0_in4_in,
      R => '0'
    );
\soft_err_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[2]_0\,
      Q => p_1_in5_in,
      R => '0'
    );
\soft_err_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[3]_0\,
      Q => \soft_err_r_reg_n_0_[3]\,
      R => '0'
    );
wait_for_lane_up_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^reset_channel_i\,
      I1 => wait_for_lane_up_r_reg,
      O => wait_for_lane_up_r0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_1_i_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_2_i_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_3_i_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    en_chan_sync_i : out STD_LOGIC;
    CHANNEL_UP_Buffer_reg_0 : out STD_LOGIC;
    start_rx_i : out STD_LOGIC;
    gtrxreset_i : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    START_RX_Buffer_reg_0 : out STD_LOGIC;
    RESET : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    GOT_V : in STD_LOGIC;
    all_lanes_v_r_reg_0 : in STD_LOGIC;
    all_lanes_v_r_reg_1 : in STD_LOGIC;
    all_lanes_v_r_reg_2 : in STD_LOGIC;
    bad_as_r0 : in STD_LOGIC;
    wait_for_lane_up_r0 : in STD_LOGIC;
    good_as_r0 : in STD_LOGIC;
    START_RX_Buffer_reg_1 : in STD_LOGIC;
    CHBONDDONE_OUT_LANE3 : in STD_LOGIC;
    CHBONDDONE_OUT : in STD_LOGIC;
    CHBONDDONE_OUT_LANE2 : in STD_LOGIC;
    CHBONDDONE_OUT_LANE1 : in STD_LOGIC;
    RX_SUF : in STD_LOGIC;
    reset_channel_i : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
end aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX;

architecture STRUCTURE of aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX is
  signal \^d\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal D_1 : STD_LOGIC;
  signal GTRXRESET_OUT_i_1_n_0 : STD_LOGIC;
  signal GTRXRESET_OUT_i_2_n_0 : STD_LOGIC;
  signal Q_0 : STD_LOGIC;
  signal START_RX_Buffer0 : STD_LOGIC;
  signal \a_count_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \a_count_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \a_count_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \a_count_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \a_count_r_reg_n_0_[2]\ : STD_LOGIC;
  signal all_ch_bond_done_r : STD_LOGIC;
  signal all_ch_bond_done_r_i_1_n_0 : STD_LOGIC;
  signal \all_channel_bond_load_c__0\ : STD_LOGIC;
  signal all_channel_bond_load_r : STD_LOGIC;
  signal \all_lanes_v_c__0\ : STD_LOGIC;
  signal all_lanes_v_r : STD_LOGIC;
  signal bad_as_r : STD_LOGIC;
  signal bad_v_r : STD_LOGIC;
  signal bad_v_r0 : STD_LOGIC;
  signal bond_passed_r : STD_LOGIC;
  signal bonding_watchdog_r0 : STD_LOGIC;
  signal \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\ : STD_LOGIC;
  signal \bonding_watchdog_r_reg[14]_srl15_i_3_n_0\ : STD_LOGIC;
  signal \bonding_watchdog_r_reg[14]_srl15_i_4_n_0\ : STD_LOGIC;
  signal \bonding_watchdog_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \bonding_watchdog_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \channel_bond_load_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \channel_bond_load_r_reg_n_0_[3]\ : STD_LOGIC;
  signal channel_bond_r : STD_LOGIC;
  signal check_bond_r : STD_LOGIC;
  signal four_as_r : STD_LOGIC;
  signal \free_count_r[13]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[13]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[13]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[13]_i_5_n_0\ : STD_LOGIC;
  signal \free_count_r[1]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[1]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[5]_i_5_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_2_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_3_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_4_n_0\ : STD_LOGIC;
  signal \free_count_r[9]_i_5_n_0\ : STD_LOGIC;
  signal free_count_r_reg : STD_LOGIC_VECTOR ( 0 to 13 );
  signal \free_count_r_reg[13]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[13]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[1]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[1]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[1]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[5]_i_1_n_7\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_4\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_5\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_6\ : STD_LOGIC;
  signal \free_count_r_reg[9]_i_1_n_7\ : STD_LOGIC;
  signal good_as_r : STD_LOGIC;
  signal got_first_v_r : STD_LOGIC;
  signal got_first_v_r_i_1_n_0 : STD_LOGIC;
  signal gtreset_flop_0_i_i_2_n_0 : STD_LOGIC;
  signal gtrxreset_extend_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal next_channel_bond_c : STD_LOGIC;
  signal next_check_bond_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_verify_c : STD_LOGIC;
  signal p_0_in7_in : STD_LOGIC;
  signal p_1_in8_in : STD_LOGIC;
  signal p_2_out : STD_LOGIC_VECTOR ( 31 to 31 );
  signal p_5_in6_in : STD_LOGIC;
  signal ready_r : STD_LOGIC;
  signal ready_r2 : STD_LOGIC;
  signal \rxver_count_r_reg[1]_srl2_i_1_n_0\ : STD_LOGIC;
  signal \rxver_count_r_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \rxver_count_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \^start_rx_i\ : STD_LOGIC;
  signal \v_count_r_reg[30]_srl31_n_0\ : STD_LOGIC;
  signal \v_count_r_reg_n_0_[31]\ : STD_LOGIC;
  signal verify_r : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_i_1_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \verify_watchdog_r_reg_n_0_[15]\ : STD_LOGIC;
  signal wait_for_lane_up_r : STD_LOGIC;
  signal \NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_v_count_r_reg[30]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \a_count_r[0]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \a_count_r[1]_i_1\ : label is "soft_lutpair84";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \bonding_watchdog_r_reg[14]_srl15\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/bonding_watchdog_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \bonding_watchdog_r_reg[14]_srl15\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/bonding_watchdog_r_reg[14]_srl15 ";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of en_chan_sync_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of en_chan_sync_flop_i : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of en_chan_sync_flop_i : label is "VCC:CE GND:R";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \free_count_r_reg[13]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \free_count_r_reg[1]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \free_count_r_reg[5]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \free_count_r_reg[9]_i_1\ : label is 11;
  attribute BOX_TYPE of gtreset_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of gtreset_flop_0_i : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of gtreset_flop_0_i : label is "VCC:CE GND:R";
  attribute BOX_TYPE of reset_lanes_flop_0_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_0_i : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of reset_lanes_flop_0_i : label is "VCC:CE GND:R";
  attribute BOX_TYPE of reset_lanes_flop_1_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_1_i : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of reset_lanes_flop_1_i : label is "VCC:CE GND:R";
  attribute BOX_TYPE of reset_lanes_flop_2_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_2_i : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of reset_lanes_flop_2_i : label is "VCC:CE GND:R";
  attribute BOX_TYPE of reset_lanes_flop_3_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM of reset_lanes_flop_3_i : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of reset_lanes_flop_3_i : label is "VCC:CE GND:R";
  attribute srl_bus_name of \rxver_count_r_reg[1]_srl2\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg ";
  attribute srl_name of \rxver_count_r_reg[1]_srl2\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg[1]_srl2 ";
  attribute srl_bus_name of \v_count_r_reg[30]_srl31\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg ";
  attribute srl_name of \v_count_r_reg[30]_srl31\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg[30]_srl31 ";
  attribute srl_bus_name of \verify_watchdog_r_reg[14]_srl15\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg ";
  attribute srl_name of \verify_watchdog_r_reg[14]_srl15\ : label is "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg[14]_srl15 ";
begin
  D(3 downto 0) <= \^d\(3 downto 0);
  start_rx_i <= \^start_rx_i\;
CHANNEL_UP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ready_r2,
      Q => CHANNEL_UP_Buffer_reg_0,
      R => '0'
    );
FRAME_ERR_Buffer_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^start_rx_i\,
      O => RESET
    );
GTRXRESET_OUT_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => gtrxreset_extend_r(2),
      I1 => gtrxreset_extend_r(3),
      I2 => gtrxreset_extend_r(0),
      I3 => gtrxreset_extend_r(1),
      I4 => GTRXRESET_OUT_i_2_n_0,
      O => GTRXRESET_OUT_i_1_n_0
    );
GTRXRESET_OUT_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => gtrxreset_extend_r(5),
      I1 => gtrxreset_extend_r(4),
      I2 => gtrxreset_extend_r(7),
      I3 => gtrxreset_extend_r(6),
      O => GTRXRESET_OUT_i_2_n_0
    );
GTRXRESET_OUT_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => GTRXRESET_OUT_i_1_n_0,
      Q => gtrxreset_i,
      R => '0'
    );
START_RX_Buffer_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_for_lane_up_r,
      O => START_RX_Buffer0
    );
START_RX_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => START_RX_Buffer0,
      Q => \^start_rx_i\,
      R => START_RX_Buffer_reg_1
    );
\a_count_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => four_as_r,
      I1 => good_as_r,
      I2 => \a_count_r_reg_n_0_[2]\,
      I3 => \a_count_r_reg_n_0_[1]\,
      I4 => check_bond_r,
      O => \a_count_r[0]_i_1_n_0\
    );
\a_count_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => \a_count_r_reg_n_0_[1]\,
      I1 => good_as_r,
      I2 => \a_count_r_reg_n_0_[2]\,
      I3 => check_bond_r,
      O => \a_count_r[1]_i_1_n_0\
    );
\a_count_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \a_count_r_reg_n_0_[2]\,
      I1 => good_as_r,
      I2 => check_bond_r,
      O => \a_count_r[2]_i_1_n_0\
    );
\a_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \a_count_r[0]_i_1_n_0\,
      Q => four_as_r,
      R => '0'
    );
\a_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \a_count_r[1]_i_1_n_0\,
      Q => \a_count_r_reg_n_0_[1]\,
      R => '0'
    );
\a_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \a_count_r[2]_i_1_n_0\,
      Q => \a_count_r_reg_n_0_[2]\,
      R => '0'
    );
all_ch_bond_done_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^d\(2),
      I1 => channel_bond_r,
      I2 => \^d\(1),
      I3 => \^d\(3),
      I4 => \^d\(0),
      O => all_ch_bond_done_r_i_1_n_0
    );
all_ch_bond_done_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => all_ch_bond_done_r_i_1_n_0,
      Q => all_ch_bond_done_r,
      R => '0'
    );
all_channel_bond_load_c: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \channel_bond_load_r_reg_n_0_[3]\,
      I1 => \channel_bond_load_r_reg_n_0_[0]\,
      I2 => p_1_in8_in,
      I3 => p_0_in7_in,
      O => \all_channel_bond_load_c__0\
    );
all_channel_bond_load_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \all_channel_bond_load_c__0\,
      Q => all_channel_bond_load_r,
      R => '0'
    );
all_lanes_v_c: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => GOT_V,
      I1 => all_lanes_v_r_reg_0,
      I2 => all_lanes_v_r_reg_1,
      I3 => all_lanes_v_r_reg_2,
      O => \all_lanes_v_c__0\
    );
all_lanes_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \all_lanes_v_c__0\,
      Q => all_lanes_v_r,
      R => '0'
    );
bad_as_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => bad_as_r0,
      Q => bad_as_r,
      R => '0'
    );
bad_v_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => got_first_v_r,
      I1 => all_lanes_v_r,
      I2 => \v_count_r_reg_n_0_[31]\,
      O => bad_v_r0
    );
bad_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => bad_v_r0,
      Q => bad_v_r,
      R => '0'
    );
bond_passed_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => all_ch_bond_done_r,
      Q => bond_passed_r,
      R => '0'
    );
\bonding_watchdog_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => bonding_watchdog_r0,
      CLK => user_clk,
      D => channel_bond_r,
      Q => \bonding_watchdog_r_reg[14]_srl15_n_0\
    );
\bonding_watchdog_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAB"
    )
        port map (
      I0 => \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\,
      I1 => check_bond_r,
      I2 => channel_bond_r,
      I3 => all_channel_bond_load_r,
      O => bonding_watchdog_r0
    );
\bonding_watchdog_r_reg[14]_srl15_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \bonding_watchdog_r_reg[14]_srl15_i_3_n_0\,
      I1 => \bonding_watchdog_r_reg[14]_srl15_i_4_n_0\,
      I2 => free_count_r_reg(0),
      I3 => free_count_r_reg(10),
      I4 => free_count_r_reg(3),
      I5 => free_count_r_reg(6),
      O => \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\
    );
\bonding_watchdog_r_reg[14]_srl15_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => free_count_r_reg(11),
      I1 => free_count_r_reg(13),
      I2 => free_count_r_reg(9),
      I3 => free_count_r_reg(1),
      I4 => free_count_r_reg(8),
      I5 => free_count_r_reg(7),
      O => \bonding_watchdog_r_reg[14]_srl15_i_3_n_0\
    );
\bonding_watchdog_r_reg[14]_srl15_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => free_count_r_reg(4),
      I1 => free_count_r_reg(5),
      I2 => free_count_r_reg(2),
      I3 => free_count_r_reg(12),
      O => \bonding_watchdog_r_reg[14]_srl15_i_4_n_0\
    );
\bonding_watchdog_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => bonding_watchdog_r0,
      D => \bonding_watchdog_r_reg[14]_srl15_n_0\,
      Q => \bonding_watchdog_r_reg_n_0_[15]\,
      R => '0'
    );
\ch_bond_done_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => CHBONDDONE_OUT_LANE3,
      Q => \^d\(3),
      R => '0'
    );
\ch_bond_done_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => CHBONDDONE_OUT_LANE2,
      Q => \^d\(2),
      R => '0'
    );
\ch_bond_done_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => CHBONDDONE_OUT_LANE1,
      Q => \^d\(1),
      R => '0'
    );
\ch_bond_done_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => CHBONDDONE_OUT,
      Q => \^d\(0),
      R => '0'
    );
\channel_bond_load_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(3),
      Q => \channel_bond_load_r_reg_n_0_[0]\,
      R => '0'
    );
\channel_bond_load_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(2),
      Q => p_0_in7_in,
      R => '0'
    );
\channel_bond_load_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(1),
      Q => p_1_in8_in,
      R => '0'
    );
\channel_bond_load_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => \channel_bond_load_r_reg_n_0_[3]\,
      R => '0'
    );
channel_bond_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF444"
    )
        port map (
      I0 => bond_passed_r,
      I1 => channel_bond_r,
      I2 => bad_as_r,
      I3 => check_bond_r,
      I4 => wait_for_lane_up_r,
      O => next_channel_bond_c
    );
channel_bond_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_channel_bond_c,
      Q => channel_bond_r,
      R => wait_for_lane_up_r0
    );
check_bond_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040404"
    )
        port map (
      I0 => bad_as_r,
      I1 => check_bond_r,
      I2 => four_as_r,
      I3 => bond_passed_r,
      I4 => channel_bond_r,
      O => next_check_bond_c
    );
check_bond_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_check_bond_c,
      Q => check_bond_r,
      R => wait_for_lane_up_r0
    );
en_chan_sync_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => channel_bond_r,
      Q => en_chan_sync_i,
      R => '0'
    );
\free_count_r[13]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(10),
      O => \free_count_r[13]_i_2_n_0\
    );
\free_count_r[13]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(11),
      O => \free_count_r[13]_i_3_n_0\
    );
\free_count_r[13]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(12),
      O => \free_count_r[13]_i_4_n_0\
    );
\free_count_r[13]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(13),
      O => \free_count_r[13]_i_5_n_0\
    );
\free_count_r[1]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(0),
      O => \free_count_r[1]_i_2_n_0\
    );
\free_count_r[1]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(1),
      O => \free_count_r[1]_i_3_n_0\
    );
\free_count_r[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(2),
      O => \free_count_r[5]_i_2_n_0\
    );
\free_count_r[5]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(3),
      O => \free_count_r[5]_i_3_n_0\
    );
\free_count_r[5]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(4),
      O => \free_count_r[5]_i_4_n_0\
    );
\free_count_r[5]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(5),
      O => \free_count_r[5]_i_5_n_0\
    );
\free_count_r[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(6),
      O => \free_count_r[9]_i_2_n_0\
    );
\free_count_r[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(7),
      O => \free_count_r[9]_i_3_n_0\
    );
\free_count_r[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(8),
      O => \free_count_r[9]_i_4_n_0\
    );
\free_count_r[9]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => free_count_r_reg(9),
      O => \free_count_r[9]_i_5_n_0\
    );
\free_count_r_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[1]_i_1_n_6\,
      Q => free_count_r_reg(0),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_4\,
      Q => free_count_r_reg(10),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[11]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_5\,
      Q => free_count_r_reg(11),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[12]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_6\,
      Q => free_count_r_reg(12),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[13]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[13]_i_1_n_7\,
      Q => free_count_r_reg(13),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[13]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \free_count_r_reg[13]_i_1_n_0\,
      CO(2) => \free_count_r_reg[13]_i_1_n_1\,
      CO(1) => \free_count_r_reg[13]_i_1_n_2\,
      CO(0) => \free_count_r_reg[13]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[13]_i_1_n_4\,
      O(2) => \free_count_r_reg[13]_i_1_n_5\,
      O(1) => \free_count_r_reg[13]_i_1_n_6\,
      O(0) => \free_count_r_reg[13]_i_1_n_7\,
      S(3) => \free_count_r[13]_i_2_n_0\,
      S(2) => \free_count_r[13]_i_3_n_0\,
      S(1) => \free_count_r[13]_i_4_n_0\,
      S(0) => \free_count_r[13]_i_5_n_0\
    );
\free_count_r_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[1]_i_1_n_7\,
      Q => free_count_r_reg(1),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[1]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[5]_i_1_n_0\,
      CO(3 downto 1) => \NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \free_count_r_reg[1]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3 downto 2) => \NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1) => \free_count_r_reg[1]_i_1_n_6\,
      O(0) => \free_count_r_reg[1]_i_1_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \free_count_r[1]_i_2_n_0\,
      S(0) => \free_count_r[1]_i_3_n_0\
    );
\free_count_r_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_4\,
      Q => free_count_r_reg(2),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_5\,
      Q => free_count_r_reg(3),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_6\,
      Q => free_count_r_reg(4),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[5]_i_1_n_7\,
      Q => free_count_r_reg(5),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[9]_i_1_n_0\,
      CO(3) => \free_count_r_reg[5]_i_1_n_0\,
      CO(2) => \free_count_r_reg[5]_i_1_n_1\,
      CO(1) => \free_count_r_reg[5]_i_1_n_2\,
      CO(0) => \free_count_r_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[5]_i_1_n_4\,
      O(2) => \free_count_r_reg[5]_i_1_n_5\,
      O(1) => \free_count_r_reg[5]_i_1_n_6\,
      O(0) => \free_count_r_reg[5]_i_1_n_7\,
      S(3) => \free_count_r[5]_i_2_n_0\,
      S(2) => \free_count_r[5]_i_3_n_0\,
      S(1) => \free_count_r[5]_i_4_n_0\,
      S(0) => \free_count_r[5]_i_5_n_0\
    );
\free_count_r_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_4\,
      Q => free_count_r_reg(6),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_5\,
      Q => free_count_r_reg(7),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_6\,
      Q => free_count_r_reg(8),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[9]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => \free_count_r_reg[9]_i_1_n_7\,
      Q => free_count_r_reg(9),
      S => wait_for_lane_up_r0
    );
\free_count_r_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \free_count_r_reg[13]_i_1_n_0\,
      CO(3) => \free_count_r_reg[9]_i_1_n_0\,
      CO(2) => \free_count_r_reg[9]_i_1_n_1\,
      CO(1) => \free_count_r_reg[9]_i_1_n_2\,
      CO(0) => \free_count_r_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \free_count_r_reg[9]_i_1_n_4\,
      O(2) => \free_count_r_reg[9]_i_1_n_5\,
      O(1) => \free_count_r_reg[9]_i_1_n_6\,
      O(0) => \free_count_r_reg[9]_i_1_n_7\,
      S(3) => \free_count_r[9]_i_2_n_0\,
      S(2) => \free_count_r[9]_i_3_n_0\,
      S(1) => \free_count_r[9]_i_4_n_0\,
      S(0) => \free_count_r[9]_i_5_n_0\
    );
good_as_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => good_as_r0,
      Q => good_as_r,
      R => '0'
    );
got_first_v_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => verify_r,
      I1 => got_first_v_r,
      I2 => all_lanes_v_r,
      O => got_first_v_r_i_1_n_0
    );
got_first_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_first_v_r_i_1_n_0,
      Q => got_first_v_r,
      R => '0'
    );
gtreset_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_5_in6_in,
      Q => Q_0,
      R => '0'
    );
gtreset_flop_0_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F444F444F4F4F444"
    )
        port map (
      I0 => gtreset_flop_0_i_i_2_n_0,
      I1 => \bonding_watchdog_r_reg_n_0_[15]\,
      I2 => verify_r,
      I3 => \verify_watchdog_r_reg_n_0_[15]\,
      I4 => bad_v_r,
      I5 => \rxver_count_r_reg_n_0_[2]\,
      O => p_5_in6_in
    );
gtreset_flop_0_i_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => check_bond_r,
      I1 => channel_bond_r,
      O => gtreset_flop_0_i_i_2_n_0
    );
\gtrxreset_extend_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(1),
      Q => gtrxreset_extend_r(0),
      R => START_RX_Buffer_reg_1
    );
\gtrxreset_extend_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(2),
      Q => gtrxreset_extend_r(1),
      R => START_RX_Buffer_reg_1
    );
\gtrxreset_extend_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(3),
      Q => gtrxreset_extend_r(2),
      R => START_RX_Buffer_reg_1
    );
\gtrxreset_extend_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(4),
      Q => gtrxreset_extend_r(3),
      R => START_RX_Buffer_reg_1
    );
\gtrxreset_extend_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(5),
      Q => gtrxreset_extend_r(4),
      R => START_RX_Buffer_reg_1
    );
\gtrxreset_extend_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(6),
      Q => gtrxreset_extend_r(5),
      R => START_RX_Buffer_reg_1
    );
\gtrxreset_extend_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_extend_r(7),
      Q => gtrxreset_extend_r(6),
      R => START_RX_Buffer_reg_1
    );
\gtrxreset_extend_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => Q_0,
      Q => gtrxreset_extend_r(7),
      R => START_RX_Buffer_reg_1
    );
ready_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ready_r,
      Q => ready_r2,
      R => '0'
    );
\ready_r_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => ready_r,
      I1 => verify_r,
      I2 => \rxver_count_r_reg_n_0_[2]\,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => ready_r,
      R => wait_for_lane_up_r0
    );
reset_lanes_flop_0_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_1,
      Q => SR(0),
      R => '0'
    );
reset_lanes_flop_0_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFAE"
    )
        port map (
      I0 => p_5_in6_in,
      I1 => reset_channel_i,
      I2 => wait_for_lane_up_r,
      I3 => START_RX_Buffer_reg_1,
      O => D_1
    );
reset_lanes_flop_1_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_1,
      Q => reset_lanes_flop_1_i_0(0),
      R => '0'
    );
reset_lanes_flop_2_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_1,
      Q => reset_lanes_flop_2_i_0(0),
      R => '0'
    );
reset_lanes_flop_3_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D_1,
      Q => reset_lanes_flop_3_i_0(0),
      R => '0'
    );
\rxver_count_r_reg[1]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => \rxver_count_r_reg[1]_srl2_i_1_n_0\,
      CLK => user_clk,
      D => verify_r,
      Q => \rxver_count_r_reg[1]_srl2_n_0\
    );
\rxver_count_r_reg[1]_srl2_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => all_lanes_v_r,
      I1 => \v_count_r_reg_n_0_[31]\,
      I2 => verify_r,
      O => \rxver_count_r_reg[1]_srl2_i_1_n_0\
    );
\rxver_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \rxver_count_r_reg[1]_srl2_i_1_n_0\,
      D => \rxver_count_r_reg[1]_srl2_n_0\,
      Q => \rxver_count_r_reg_n_0_[2]\,
      R => '0'
    );
\stage_1_lane_mask_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^start_rx_i\,
      I1 => RX_SUF,
      O => START_RX_Buffer_reg_0
    );
\v_count_r_reg[30]_srl31\: unisim.vcomponents.SRLC32E
     port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => user_clk,
      D => p_2_out(31),
      Q => \v_count_r_reg[30]_srl31_n_0\,
      Q31 => \NLW_v_count_r_reg[30]_srl31_Q31_UNCONNECTED\
    );
\v_count_r_reg[30]_srl31_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => \v_count_r_reg_n_0_[31]\,
      I1 => verify_r,
      I2 => got_first_v_r,
      I3 => all_lanes_v_r,
      O => p_2_out(31)
    );
\v_count_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \v_count_r_reg[30]_srl31_n_0\,
      Q => \v_count_r_reg_n_0_[31]\,
      R => '0'
    );
verify_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22F22222"
    )
        port map (
      I0 => verify_r,
      I1 => \rxver_count_r_reg_n_0_[2]\,
      I2 => four_as_r,
      I3 => bad_as_r,
      I4 => check_bond_r,
      O => next_verify_c
    );
verify_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_verify_c,
      Q => verify_r,
      R => wait_for_lane_up_r0
    );
\verify_watchdog_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => \verify_watchdog_r_reg[14]_srl15_i_1_n_0\,
      CLK => user_clk,
      D => verify_r,
      Q => \verify_watchdog_r_reg[14]_srl15_n_0\
    );
\verify_watchdog_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \bonding_watchdog_r_reg[14]_srl15_i_2_n_0\,
      I1 => verify_r,
      O => \verify_watchdog_r_reg[14]_srl15_i_1_n_0\
    );
\verify_watchdog_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \verify_watchdog_r_reg[14]_srl15_i_1_n_0\,
      D => \verify_watchdog_r_reg[14]_srl15_n_0\,
      Q => \verify_watchdog_r_reg_n_0_[15]\,
      R => '0'
    );
wait_for_lane_up_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => wait_for_lane_up_r0,
      Q => wait_for_lane_up_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5 is
  port (
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    begin_r0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \soft_err_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    enable_err_detect_i : in STD_LOGIC
  );
end aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5;

architecture STRUCTURE of aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5 is
  signal \bucket_full_r_i_1__2_n_0\ : STD_LOGIC;
  signal count_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \count_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \count_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \good_count_r[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \good_count_r[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \good_count_r_reg_n_0_[1]\ : STD_LOGIC;
  signal hard_err_reset_i : STD_LOGIC;
  signal p_0_in6_in : STD_LOGIC;
  signal soft_err_flop_r0 : STD_LOGIC;
  signal soft_err_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \soft_err_r_reg_n_0_[1]\ : STD_LOGIC;
  attribute srl_name : string;
  attribute srl_name of SOFT_ERR_Buffer_reg_srl2 : label is "U0/\rx_aurora_lane_simplex_v5_3_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \good_count_r[0]_i_1__2\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \good_count_r[1]_i_1__2\ : label is "soft_lutpair69";
begin
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_reset_i,
      Q => D(0),
      R => hard_err_flop_r_reg_0
    );
SOFT_ERR_Buffer_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => soft_err_flop_r0,
      Q => user_clk_0
    );
\SOFT_ERR_Buffer_reg_srl2_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => soft_err_r(1),
      I1 => \soft_err_r_reg_n_0_[1]\,
      O => soft_err_flop_r0
    );
\align_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => hard_err_reset_i,
      I1 => SR(0),
      O => begin_r0
    );
\bucket_full_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      O => \bucket_full_r_i_1__2_n_0\
    );
bucket_full_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \bucket_full_r_i_1__2_n_0\,
      Q => bucket_full_r,
      R => '0'
    );
\count_r[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEECE8CFFEEEE8C"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[0]_i_1__2_n_0\
    );
\count_r[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEDDAD4AEEDDDD4A"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[1]_i_1__2_n_0\
    );
\count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[0]_i_1__2_n_0\,
      Q => count_r(0),
      R => hard_err_flop_r_reg_0
    );
\count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[1]_i_1__2_n_0\,
      Q => count_r(1),
      R => hard_err_flop_r_reg_0
    );
\good_count_r[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => p_0_in6_in,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[0]_i_1__2_n_0\
    );
\good_count_r[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"32FF"
    )
        port map (
      I0 => \good_count_r_reg_n_0_[1]\,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[1]_i_1__2_n_0\
    );
\good_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[0]_i_1__2_n_0\,
      Q => p_0_in6_in,
      R => '0'
    );
\good_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[1]_i_1__2_n_0\,
      Q => \good_count_r_reg_n_0_[1]\,
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r0,
      Q => hard_err_reset_i,
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(1),
      Q => soft_err_r(1),
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(0),
      Q => \soft_err_r_reg_n_0_[1]\,
      R => hard_err_flop_r_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12 is
  port (
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    begin_r0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \soft_err_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    enable_err_detect_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12 : entity is "aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5";
end aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12;

architecture STRUCTURE of aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12 is
  signal \bucket_full_r_i_1__0_n_0\ : STD_LOGIC;
  signal count_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \count_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \count_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \good_count_r[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \good_count_r[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \good_count_r_reg_n_0_[1]\ : STD_LOGIC;
  signal hard_err_reset_i : STD_LOGIC;
  signal p_0_in6_in : STD_LOGIC;
  signal soft_err_flop_r0 : STD_LOGIC;
  signal soft_err_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \soft_err_r_reg_n_0_[1]\ : STD_LOGIC;
  attribute srl_name : string;
  attribute srl_name of SOFT_ERR_Buffer_reg_srl2 : label is "U0/\rx_aurora_lane_simplex_v5_1_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \good_count_r[0]_i_1__0\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \good_count_r[1]_i_1__0\ : label is "soft_lutpair39";
begin
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_reset_i,
      Q => D(0),
      R => hard_err_flop_r_reg_0
    );
SOFT_ERR_Buffer_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => soft_err_flop_r0,
      Q => user_clk_0
    );
\SOFT_ERR_Buffer_reg_srl2_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => soft_err_r(1),
      I1 => \soft_err_r_reg_n_0_[1]\,
      O => soft_err_flop_r0
    );
\align_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => hard_err_reset_i,
      I1 => SR(0),
      O => begin_r0
    );
\bucket_full_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      O => \bucket_full_r_i_1__0_n_0\
    );
bucket_full_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \bucket_full_r_i_1__0_n_0\,
      Q => bucket_full_r,
      R => '0'
    );
\count_r[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEECE8CFFEEEE8C"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[0]_i_1__0_n_0\
    );
\count_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEDDAD4AEEDDDD4A"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[1]_i_1__0_n_0\
    );
\count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[0]_i_1__0_n_0\,
      Q => count_r(0),
      R => hard_err_flop_r_reg_0
    );
\count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[1]_i_1__0_n_0\,
      Q => count_r(1),
      R => hard_err_flop_r_reg_0
    );
\good_count_r[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => p_0_in6_in,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[0]_i_1__0_n_0\
    );
\good_count_r[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"32FF"
    )
        port map (
      I0 => \good_count_r_reg_n_0_[1]\,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[1]_i_1__0_n_0\
    );
\good_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[0]_i_1__0_n_0\,
      Q => p_0_in6_in,
      R => '0'
    );
\good_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[1]_i_1__0_n_0\,
      Q => \good_count_r_reg_n_0_[1]\,
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r0,
      Q => hard_err_reset_i,
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(1),
      Q => soft_err_r(1),
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(0),
      Q => \soft_err_r_reg_n_0_[1]\,
      R => hard_err_flop_r_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17 is
  port (
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    begin_r0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \soft_err_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    enable_err_detect_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17 : entity is "aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5";
end aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17;

architecture STRUCTURE of aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17 is
  signal bucket_full_r_i_1_n_0 : STD_LOGIC;
  signal count_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \count_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \good_count_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \good_count_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \good_count_r_reg_n_0_[1]\ : STD_LOGIC;
  signal hard_err_reset_i : STD_LOGIC;
  signal p_0_in6_in : STD_LOGIC;
  signal soft_err_flop_r0 : STD_LOGIC;
  signal soft_err_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \soft_err_r_reg_n_0_[1]\ : STD_LOGIC;
  attribute srl_name : string;
  attribute srl_name of SOFT_ERR_Buffer_reg_srl2 : label is "U0/\rx_aurora_lane_simplex_v5_0_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \good_count_r[0]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \good_count_r[1]_i_1\ : label is "soft_lutpair24";
begin
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_reset_i,
      Q => D(0),
      R => hard_err_flop_r_reg_0
    );
SOFT_ERR_Buffer_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => soft_err_flop_r0,
      Q => user_clk_0
    );
SOFT_ERR_Buffer_reg_srl2_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => soft_err_r(1),
      I1 => \soft_err_r_reg_n_0_[1]\,
      O => soft_err_flop_r0
    );
align_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => hard_err_reset_i,
      I1 => SR(0),
      O => begin_r0
    );
bucket_full_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      O => bucket_full_r_i_1_n_0
    );
bucket_full_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => bucket_full_r_i_1_n_0,
      Q => bucket_full_r,
      R => '0'
    );
\count_r[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEECE8CFFEEEE8C"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[0]_i_1_n_0\
    );
\count_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEDDAD4AEEDDDD4A"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[1]_i_1_n_0\
    );
\count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[0]_i_1_n_0\,
      Q => count_r(0),
      R => hard_err_flop_r_reg_0
    );
\count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[1]_i_1_n_0\,
      Q => count_r(1),
      R => hard_err_flop_r_reg_0
    );
\good_count_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => p_0_in6_in,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[0]_i_1_n_0\
    );
\good_count_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"32FF"
    )
        port map (
      I0 => \good_count_r_reg_n_0_[1]\,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[1]_i_1_n_0\
    );
\good_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[0]_i_1_n_0\,
      Q => p_0_in6_in,
      R => '0'
    );
\good_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[1]_i_1_n_0\,
      Q => \good_count_r_reg_n_0_[1]\,
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r0,
      Q => hard_err_reset_i,
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(1),
      Q => soft_err_r(1),
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(0),
      Q => \soft_err_r_reg_n_0_[1]\,
      R => hard_err_flop_r_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7 is
  port (
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    begin_r0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    hard_err_flop_r_reg_0 : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \soft_err_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    enable_err_detect_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7 : entity is "aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5";
end aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7;

architecture STRUCTURE of aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7 is
  signal \bucket_full_r_i_1__1_n_0\ : STD_LOGIC;
  signal count_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \count_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \count_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \good_count_r[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \good_count_r[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \good_count_r_reg_n_0_[1]\ : STD_LOGIC;
  signal hard_err_reset_i : STD_LOGIC;
  signal p_0_in6_in : STD_LOGIC;
  signal soft_err_flop_r0 : STD_LOGIC;
  signal soft_err_r : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \soft_err_r_reg_n_0_[1]\ : STD_LOGIC;
  attribute srl_name : string;
  attribute srl_name of SOFT_ERR_Buffer_reg_srl2 : label is "U0/\rx_aurora_lane_simplex_v5_2_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \good_count_r[0]_i_1__1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \good_count_r[1]_i_1__1\ : label is "soft_lutpair54";
begin
HARD_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_reset_i,
      Q => D(0),
      R => hard_err_flop_r_reg_0
    );
SOFT_ERR_Buffer_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => soft_err_flop_r0,
      Q => user_clk_0
    );
\SOFT_ERR_Buffer_reg_srl2_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => soft_err_r(1),
      I1 => \soft_err_r_reg_n_0_[1]\,
      O => soft_err_flop_r0
    );
\align_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => hard_err_reset_i,
      I1 => SR(0),
      O => begin_r0
    );
\bucket_full_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      O => \bucket_full_r_i_1__1_n_0\
    );
bucket_full_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \bucket_full_r_i_1__1_n_0\,
      Q => bucket_full_r,
      R => '0'
    );
\count_r[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEECE8CFFEEEE8C"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[0]_i_1__1_n_0\
    );
\count_r[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEDDAD4AEEDDDD4A"
    )
        port map (
      I0 => count_r(1),
      I1 => count_r(0),
      I2 => p_0_in6_in,
      I3 => \soft_err_r_reg_n_0_[1]\,
      I4 => soft_err_r(1),
      I5 => \good_count_r_reg_n_0_[1]\,
      O => \count_r[1]_i_1__1_n_0\
    );
\count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[0]_i_1__1_n_0\,
      Q => count_r(0),
      R => hard_err_flop_r_reg_0
    );
\count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \count_r[1]_i_1__1_n_0\,
      Q => count_r(1),
      R => hard_err_flop_r_reg_0
    );
\good_count_r[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => p_0_in6_in,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[0]_i_1__1_n_0\
    );
\good_count_r[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"32FF"
    )
        port map (
      I0 => \good_count_r_reg_n_0_[1]\,
      I1 => \soft_err_r_reg_n_0_[1]\,
      I2 => soft_err_r(1),
      I3 => enable_err_detect_i,
      O => \good_count_r[1]_i_1__1_n_0\
    );
\good_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[0]_i_1__1_n_0\,
      Q => p_0_in6_in,
      R => '0'
    );
\good_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \good_count_r[1]_i_1__1_n_0\,
      Q => \good_count_r_reg_n_0_[1]\,
      R => '0'
    );
hard_err_flop_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => hard_err_flop_r0,
      Q => hard_err_reset_i,
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(1),
      Q => soft_err_r(1),
      R => hard_err_flop_r_reg_0
    );
\soft_err_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \soft_err_r_reg[0]_0\(0),
      Q => \soft_err_r_reg_n_0_[1]\,
      R => hard_err_flop_r_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    align_r_reg_0 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    rst_r_reg_0 : out STD_LOGIC;
    enable_err_detect_i : out STD_LOGIC;
    rx_polarity_i_3 : out STD_LOGIC;
    gthe2_i : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    begin_r0 : in STD_LOGIC;
    begin_r_reg_0 : in STD_LOGIC;
    RX_NEG_Buffer : in STD_LOGIC;
    reset_count_r_reg_0 : in STD_LOGIC;
    rx_sp_i : in STD_LOGIC;
    \counter2_r_reg[15]_0\ : in STD_LOGIC;
    \RX_CHAR_IS_COMMA_R_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg : in STD_LOGIC;
    left_aligned_r_reg_0 : in STD_LOGIC
  );
end aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX is
  signal D : STD_LOGIC;
  signal RX_CHAR_IS_COMMA_R : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^align_r_reg_0\ : STD_LOGIC;
  signal begin_r : STD_LOGIC;
  signal comma_over_two_cycles_r0 : STD_LOGIC;
  signal counter1_r0 : STD_LOGIC;
  signal \counter1_r[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \counter1_r[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal counter2_r0 : STD_LOGIC;
  signal \counter2_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \counter2_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \^enable_err_detect_i\ : STD_LOGIC;
  signal inc_count_c : STD_LOGIC;
  signal inc_count_c1 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_begin_c : STD_LOGIC;
  signal next_polarity_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_realign_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal polarity_r : STD_LOGIC;
  signal prev_char_was_comma_r : STD_LOGIC;
  signal realign_r : STD_LOGIC;
  signal reset_count_r : STD_LOGIC;
  signal reset_count_r0 : STD_LOGIC;
  signal \^rst_r_reg_0\ : STD_LOGIC;
  signal \^rx_polarity_i_3\ : STD_LOGIC;
  signal \rx_polarity_r_i_1__2_n_0\ : STD_LOGIC;
  signal std_bool : STD_LOGIC;
  signal std_bool0_in : STD_LOGIC;
  signal std_bool0_in3_in : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \counter1_r[0]_i_4__2\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \counter1_r[3]_i_1__2\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \counter1_r[4]_i_1__2\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \counter1_r[5]_i_1__2\ : label is "soft_lutpair71";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_3_i/rx_lane_init_sm_simplex_i/counter2_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_3_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 ";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of lane_up_flop_i : label is "VCC:CE";
begin
  align_r_reg_0 <= \^align_r_reg_0\;
  enable_err_detect_i <= \^enable_err_detect_i\;
  rst_r_reg_0 <= \^rst_r_reg_0\;
  rx_polarity_i_3 <= \^rx_polarity_i_3\;
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => \^enable_err_detect_i\,
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      Q => RX_CHAR_IS_COMMA_R(0),
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(1),
      Q => RX_CHAR_IS_COMMA_R(1),
      R => '0'
    );
\align_r_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => std_bool0_in,
      I1 => \^align_r_reg_0\,
      I2 => std_bool0_in3_in,
      I3 => \^rst_r_reg_0\,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => \^align_r_reg_0\,
      R => begin_r0
    );
\begin_r_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => realign_r,
      I1 => begin_r_reg_0,
      I2 => D,
      I3 => \counter2_r_reg_n_0_[15]\,
      I4 => polarity_r,
      I5 => RX_NEG_Buffer,
      O => next_begin_c
    );
begin_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_begin_c,
      Q => begin_r,
      S => begin_r0
    );
\comma_over_two_cycles_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(0),
      I2 => RX_CHAR_IS_COMMA_R(1),
      I3 => prev_char_was_comma_r,
      O => comma_over_two_cycles_r0
    );
comma_over_two_cycles_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => comma_over_two_cycles_r0,
      Q => comma_over_two_cycles_r,
      R => '0'
    );
\counter1_r[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => D,
      I1 => reset_count_r,
      O => counter1_r0
    );
\counter1_r[0]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(1),
      I2 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c
    );
\counter1_r[0]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool0_in,
      I1 => std_bool,
      I2 => std_bool0_in3_in,
      I3 => \counter1_r[0]_i_4__2_n_0\,
      I4 => \counter1_r_reg_n_0_[3]\,
      I5 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(7)
    );
\counter1_r[0]_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[5]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[7]\,
      O => \counter1_r[0]_i_4__2_n_0\
    );
\counter1_r[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[1]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r[0]_i_4__2_n_0\,
      I3 => std_bool0_in3_in,
      I4 => std_bool,
      O => p_0_in(6)
    );
\counter1_r[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool,
      I1 => std_bool0_in3_in,
      I2 => \counter1_r_reg_n_0_[7]\,
      I3 => \counter1_r_reg_n_0_[6]\,
      I4 => \counter1_r_reg_n_0_[5]\,
      I5 => \counter1_r_reg_n_0_[3]\,
      O => \counter1_r[2]_i_1__2_n_0\
    );
\counter1_r[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[5]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[7]\,
      I4 => std_bool0_in3_in,
      O => p_0_in(4)
    );
\counter1_r[4]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => std_bool0_in3_in,
      I1 => \counter1_r_reg_n_0_[7]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(3)
    );
\counter1_r[5]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(2)
    );
\counter1_r[6]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      O => p_0_in(1)
    );
\counter1_r[7]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(7),
      Q => std_bool0_in,
      R => counter1_r0
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(6),
      Q => \counter1_r_reg_n_0_[1]\,
      R => counter1_r0
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => \counter1_r[2]_i_1__2_n_0\,
      Q => std_bool,
      R => counter1_r0
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(4),
      Q => \counter1_r_reg_n_0_[3]\,
      R => counter1_r0
    );
\counter1_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(3),
      Q => std_bool0_in3_in,
      R => counter1_r0
    );
\counter1_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[5]\,
      R => counter1_r0
    );
\counter1_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[6]\,
      R => counter1_r0
    );
\counter1_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[7]\,
      S => counter1_r0
    );
\counter2_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => counter2_r0,
      CLK => user_clk,
      D => D,
      Q => \counter2_r_reg[14]_srl15_n_0\
    );
\counter2_r_reg[14]_srl15_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => D,
      I1 => rx_sp_i,
      I2 => \counter2_r_reg[15]_0\,
      O => counter2_r0
    );
\counter2_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => counter2_r0,
      D => \counter2_r_reg[14]_srl15_n_0\,
      Q => \counter2_r_reg_n_0_[15]\,
      R => '0'
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => RX_LANE_UP(0),
      R => SR(0)
    );
\left_aligned_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAB00A8"
    )
        port map (
      I0 => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      I1 => \^align_r_reg_0\,
      I2 => D,
      I3 => left_aligned_r_reg,
      I4 => left_aligned_r_reg_0,
      O => gthe2_i
    );
\polarity_r_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => std_bool,
      I1 => realign_r,
      I2 => begin_r_reg_0,
      O => next_polarity_c
    );
polarity_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_polarity_c,
      Q => polarity_r,
      R => begin_r0
    );
\prev_char_was_comma_r_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => RX_CHAR_IS_COMMA_R(1),
      I1 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c1
    );
prev_char_was_comma_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => inc_count_c1,
      Q => prev_char_was_comma_r,
      R => '0'
    );
\ready_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \counter2_r_reg_n_0_[15]\,
      I1 => D,
      I2 => RX_NEG_Buffer,
      I3 => polarity_r,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D,
      R => begin_r0
    );
\realign_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040404"
    )
        port map (
      I0 => begin_r_reg_0,
      I1 => realign_r,
      I2 => std_bool,
      I3 => std_bool0_in,
      I4 => \^align_r_reg_0\,
      O => next_realign_c
    );
realign_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_realign_c,
      Q => realign_r,
      R => begin_r0
    );
\reset_count_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF04F5"
    )
        port map (
      I0 => reset_count_r_reg_0,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      I3 => \^rst_r_reg_0\,
      I4 => SR(0),
      O => reset_count_r0
    );
reset_count_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => reset_count_r0,
      Q => reset_count_r,
      R => '0'
    );
\rst_r_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F2"
    )
        port map (
      I0 => \^rst_r_reg_0\,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => \^rst_r_reg_0\,
      R => begin_r0
    );
\rx_polarity_r_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RX_NEG_Buffer,
      I1 => polarity_r,
      I2 => \^rx_polarity_i_3\,
      O => \rx_polarity_r_i_1__2_n_0\
    );
rx_polarity_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \rx_polarity_r_i_1__2_n_0\,
      Q => \^rx_polarity_i_3\,
      R => '0'
    );
\soft_err_r[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^enable_err_detect_i\,
      O => ENABLE_ERR_DETECT_Buffer_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13 is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    align_r_reg_0 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    rst_r_reg_0 : out STD_LOGIC;
    enable_err_detect_i : out STD_LOGIC;
    rx_polarity_i_1 : out STD_LOGIC;
    gthe2_i : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    begin_r0 : in STD_LOGIC;
    begin_r_reg_0 : in STD_LOGIC;
    RX_NEG_Buffer : in STD_LOGIC;
    reset_count_r_reg_0 : in STD_LOGIC;
    rx_sp_i : in STD_LOGIC;
    \counter2_r_reg[15]_0\ : in STD_LOGIC;
    \RX_CHAR_IS_COMMA_R_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg : in STD_LOGIC;
    left_aligned_r_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13 : entity is "aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX";
end aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13 is
  signal D : STD_LOGIC;
  signal RX_CHAR_IS_COMMA_R : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^align_r_reg_0\ : STD_LOGIC;
  signal begin_r : STD_LOGIC;
  signal comma_over_two_cycles_r0 : STD_LOGIC;
  signal counter1_r0 : STD_LOGIC;
  signal \counter1_r[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \counter1_r[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal counter2_r0 : STD_LOGIC;
  signal \counter2_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \counter2_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \^enable_err_detect_i\ : STD_LOGIC;
  signal inc_count_c : STD_LOGIC;
  signal inc_count_c1 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_begin_c : STD_LOGIC;
  signal next_polarity_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_realign_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal polarity_r : STD_LOGIC;
  signal prev_char_was_comma_r : STD_LOGIC;
  signal realign_r : STD_LOGIC;
  signal reset_count_r : STD_LOGIC;
  signal reset_count_r0 : STD_LOGIC;
  signal \^rst_r_reg_0\ : STD_LOGIC;
  signal \^rx_polarity_i_1\ : STD_LOGIC;
  signal \rx_polarity_r_i_1__0_n_0\ : STD_LOGIC;
  signal std_bool : STD_LOGIC;
  signal std_bool0_in : STD_LOGIC;
  signal std_bool0_in3_in : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \counter1_r[0]_i_4__0\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \counter1_r[3]_i_1__0\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \counter1_r[4]_i_1__0\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \counter1_r[5]_i_1__0\ : label is "soft_lutpair41";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_1_i/rx_lane_init_sm_simplex_i/counter2_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_1_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 ";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of lane_up_flop_i : label is "VCC:CE";
begin
  align_r_reg_0 <= \^align_r_reg_0\;
  enable_err_detect_i <= \^enable_err_detect_i\;
  rst_r_reg_0 <= \^rst_r_reg_0\;
  rx_polarity_i_1 <= \^rx_polarity_i_1\;
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => \^enable_err_detect_i\,
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      Q => RX_CHAR_IS_COMMA_R(0),
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(1),
      Q => RX_CHAR_IS_COMMA_R(1),
      R => '0'
    );
\align_r_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => std_bool0_in,
      I1 => \^align_r_reg_0\,
      I2 => std_bool0_in3_in,
      I3 => \^rst_r_reg_0\,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => \^align_r_reg_0\,
      R => begin_r0
    );
\begin_r_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => realign_r,
      I1 => begin_r_reg_0,
      I2 => D,
      I3 => \counter2_r_reg_n_0_[15]\,
      I4 => polarity_r,
      I5 => RX_NEG_Buffer,
      O => next_begin_c
    );
begin_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_begin_c,
      Q => begin_r,
      S => begin_r0
    );
\comma_over_two_cycles_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(0),
      I2 => RX_CHAR_IS_COMMA_R(1),
      I3 => prev_char_was_comma_r,
      O => comma_over_two_cycles_r0
    );
comma_over_two_cycles_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => comma_over_two_cycles_r0,
      Q => comma_over_two_cycles_r,
      R => '0'
    );
\counter1_r[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => D,
      I1 => reset_count_r,
      O => counter1_r0
    );
\counter1_r[0]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(1),
      I2 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c
    );
\counter1_r[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool0_in,
      I1 => std_bool,
      I2 => std_bool0_in3_in,
      I3 => \counter1_r[0]_i_4__0_n_0\,
      I4 => \counter1_r_reg_n_0_[3]\,
      I5 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(7)
    );
\counter1_r[0]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[5]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[7]\,
      O => \counter1_r[0]_i_4__0_n_0\
    );
\counter1_r[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[1]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r[0]_i_4__0_n_0\,
      I3 => std_bool0_in3_in,
      I4 => std_bool,
      O => p_0_in(6)
    );
\counter1_r[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool,
      I1 => std_bool0_in3_in,
      I2 => \counter1_r_reg_n_0_[7]\,
      I3 => \counter1_r_reg_n_0_[6]\,
      I4 => \counter1_r_reg_n_0_[5]\,
      I5 => \counter1_r_reg_n_0_[3]\,
      O => \counter1_r[2]_i_1__0_n_0\
    );
\counter1_r[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[5]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[7]\,
      I4 => std_bool0_in3_in,
      O => p_0_in(4)
    );
\counter1_r[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => std_bool0_in3_in,
      I1 => \counter1_r_reg_n_0_[7]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(3)
    );
\counter1_r[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(2)
    );
\counter1_r[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      O => p_0_in(1)
    );
\counter1_r[7]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(7),
      Q => std_bool0_in,
      R => counter1_r0
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(6),
      Q => \counter1_r_reg_n_0_[1]\,
      R => counter1_r0
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => \counter1_r[2]_i_1__0_n_0\,
      Q => std_bool,
      R => counter1_r0
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(4),
      Q => \counter1_r_reg_n_0_[3]\,
      R => counter1_r0
    );
\counter1_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(3),
      Q => std_bool0_in3_in,
      R => counter1_r0
    );
\counter1_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[5]\,
      R => counter1_r0
    );
\counter1_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[6]\,
      R => counter1_r0
    );
\counter1_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[7]\,
      S => counter1_r0
    );
\counter2_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => counter2_r0,
      CLK => user_clk,
      D => D,
      Q => \counter2_r_reg[14]_srl15_n_0\
    );
\counter2_r_reg[14]_srl15_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => D,
      I1 => rx_sp_i,
      I2 => \counter2_r_reg[15]_0\,
      O => counter2_r0
    );
\counter2_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => counter2_r0,
      D => \counter2_r_reg[14]_srl15_n_0\,
      Q => \counter2_r_reg_n_0_[15]\,
      R => '0'
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => RX_LANE_UP(0),
      R => SR(0)
    );
\left_aligned_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAB00A8"
    )
        port map (
      I0 => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      I1 => \^align_r_reg_0\,
      I2 => D,
      I3 => left_aligned_r_reg,
      I4 => left_aligned_r_reg_0,
      O => gthe2_i
    );
\polarity_r_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => std_bool,
      I1 => realign_r,
      I2 => begin_r_reg_0,
      O => next_polarity_c
    );
polarity_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_polarity_c,
      Q => polarity_r,
      R => begin_r0
    );
\prev_char_was_comma_r_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => RX_CHAR_IS_COMMA_R(1),
      I1 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c1
    );
prev_char_was_comma_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => inc_count_c1,
      Q => prev_char_was_comma_r,
      R => '0'
    );
\ready_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \counter2_r_reg_n_0_[15]\,
      I1 => D,
      I2 => RX_NEG_Buffer,
      I3 => polarity_r,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D,
      R => begin_r0
    );
\realign_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040404"
    )
        port map (
      I0 => begin_r_reg_0,
      I1 => realign_r,
      I2 => std_bool,
      I3 => std_bool0_in,
      I4 => \^align_r_reg_0\,
      O => next_realign_c
    );
realign_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_realign_c,
      Q => realign_r,
      R => begin_r0
    );
\reset_count_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF04F5"
    )
        port map (
      I0 => reset_count_r_reg_0,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      I3 => \^rst_r_reg_0\,
      I4 => SR(0),
      O => reset_count_r0
    );
reset_count_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => reset_count_r0,
      Q => reset_count_r,
      R => '0'
    );
\rst_r_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F2"
    )
        port map (
      I0 => \^rst_r_reg_0\,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => \^rst_r_reg_0\,
      R => begin_r0
    );
\rx_polarity_r_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RX_NEG_Buffer,
      I1 => polarity_r,
      I2 => \^rx_polarity_i_1\,
      O => \rx_polarity_r_i_1__0_n_0\
    );
rx_polarity_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \rx_polarity_r_i_1__0_n_0\,
      Q => \^rx_polarity_i_1\,
      R => '0'
    );
\soft_err_r[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^enable_err_detect_i\,
      O => ENABLE_ERR_DETECT_Buffer_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18 is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    align_r_reg_0 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    rst_r_reg_0 : out STD_LOGIC;
    enable_err_detect_i : out STD_LOGIC;
    rx_polarity_i_0 : out STD_LOGIC;
    gthe2_i : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    begin_r0 : in STD_LOGIC;
    begin_r_reg_0 : in STD_LOGIC;
    RX_NEG_Buffer : in STD_LOGIC;
    reset_count_r_reg_0 : in STD_LOGIC;
    \counter2_r_reg[15]_0\ : in STD_LOGIC;
    rx_sp_i : in STD_LOGIC;
    \RX_CHAR_IS_COMMA_R_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg : in STD_LOGIC;
    left_aligned_r_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18 : entity is "aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX";
end aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18 is
  signal D : STD_LOGIC;
  signal RX_CHAR_IS_COMMA_R : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^align_r_reg_0\ : STD_LOGIC;
  signal begin_r : STD_LOGIC;
  signal comma_over_two_cycles_r0 : STD_LOGIC;
  signal counter1_r0 : STD_LOGIC;
  signal \counter1_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \counter1_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal counter2_r0 : STD_LOGIC;
  signal \counter2_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \counter2_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \^enable_err_detect_i\ : STD_LOGIC;
  signal inc_count_c : STD_LOGIC;
  signal inc_count_c1 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_begin_c : STD_LOGIC;
  signal next_polarity_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_realign_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal polarity_r : STD_LOGIC;
  signal prev_char_was_comma_r : STD_LOGIC;
  signal realign_r : STD_LOGIC;
  signal reset_count_r : STD_LOGIC;
  signal reset_count_r0 : STD_LOGIC;
  signal \^rst_r_reg_0\ : STD_LOGIC;
  signal \^rx_polarity_i_0\ : STD_LOGIC;
  signal rx_polarity_r_i_1_n_0 : STD_LOGIC;
  signal std_bool : STD_LOGIC;
  signal std_bool0_in : STD_LOGIC;
  signal std_bool0_in3_in : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \counter1_r[0]_i_4\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \counter1_r[3]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \counter1_r[4]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \counter1_r[5]_i_1\ : label is "soft_lutpair26";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_0_i/rx_lane_init_sm_simplex_i/counter2_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_0_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 ";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of lane_up_flop_i : label is "VCC:CE";
begin
  align_r_reg_0 <= \^align_r_reg_0\;
  enable_err_detect_i <= \^enable_err_detect_i\;
  rst_r_reg_0 <= \^rst_r_reg_0\;
  rx_polarity_i_0 <= \^rx_polarity_i_0\;
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => \^enable_err_detect_i\,
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      Q => RX_CHAR_IS_COMMA_R(0),
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(1),
      Q => RX_CHAR_IS_COMMA_R(1),
      R => '0'
    );
align_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => std_bool0_in,
      I1 => \^align_r_reg_0\,
      I2 => std_bool0_in3_in,
      I3 => \^rst_r_reg_0\,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => \^align_r_reg_0\,
      R => begin_r0
    );
begin_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => realign_r,
      I1 => begin_r_reg_0,
      I2 => D,
      I3 => \counter2_r_reg_n_0_[15]\,
      I4 => polarity_r,
      I5 => RX_NEG_Buffer,
      O => next_begin_c
    );
begin_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_begin_c,
      Q => begin_r,
      S => begin_r0
    );
comma_over_two_cycles_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(0),
      I2 => RX_CHAR_IS_COMMA_R(1),
      I3 => prev_char_was_comma_r,
      O => comma_over_two_cycles_r0
    );
comma_over_two_cycles_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => comma_over_two_cycles_r0,
      Q => comma_over_two_cycles_r,
      R => '0'
    );
\counter1_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => D,
      I1 => reset_count_r,
      O => counter1_r0
    );
\counter1_r[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(1),
      I2 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c
    );
\counter1_r[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool0_in,
      I1 => std_bool,
      I2 => std_bool0_in3_in,
      I3 => \counter1_r[0]_i_4_n_0\,
      I4 => \counter1_r_reg_n_0_[3]\,
      I5 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(7)
    );
\counter1_r[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[5]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[7]\,
      O => \counter1_r[0]_i_4_n_0\
    );
\counter1_r[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[1]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r[0]_i_4_n_0\,
      I3 => std_bool0_in3_in,
      I4 => std_bool,
      O => p_0_in(6)
    );
\counter1_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool,
      I1 => std_bool0_in3_in,
      I2 => \counter1_r_reg_n_0_[7]\,
      I3 => \counter1_r_reg_n_0_[6]\,
      I4 => \counter1_r_reg_n_0_[5]\,
      I5 => \counter1_r_reg_n_0_[3]\,
      O => \counter1_r[2]_i_1_n_0\
    );
\counter1_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[5]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[7]\,
      I4 => std_bool0_in3_in,
      O => p_0_in(4)
    );
\counter1_r[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => std_bool0_in3_in,
      I1 => \counter1_r_reg_n_0_[7]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(3)
    );
\counter1_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(2)
    );
\counter1_r[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      O => p_0_in(1)
    );
\counter1_r[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(7),
      Q => std_bool0_in,
      R => counter1_r0
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(6),
      Q => \counter1_r_reg_n_0_[1]\,
      R => counter1_r0
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => \counter1_r[2]_i_1_n_0\,
      Q => std_bool,
      R => counter1_r0
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(4),
      Q => \counter1_r_reg_n_0_[3]\,
      R => counter1_r0
    );
\counter1_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(3),
      Q => std_bool0_in3_in,
      R => counter1_r0
    );
\counter1_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[5]\,
      R => counter1_r0
    );
\counter1_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[6]\,
      R => counter1_r0
    );
\counter1_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[7]\,
      S => counter1_r0
    );
\counter2_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => counter2_r0,
      CLK => user_clk,
      D => D,
      Q => \counter2_r_reg[14]_srl15_n_0\
    );
\counter2_r_reg[14]_srl15_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => D,
      I1 => \counter2_r_reg[15]_0\,
      I2 => rx_sp_i,
      O => counter2_r0
    );
\counter2_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => counter2_r0,
      D => \counter2_r_reg[14]_srl15_n_0\,
      Q => \counter2_r_reg_n_0_[15]\,
      R => '0'
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => RX_LANE_UP(0),
      R => SR(0)
    );
left_aligned_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAB00A8"
    )
        port map (
      I0 => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      I1 => \^align_r_reg_0\,
      I2 => D,
      I3 => left_aligned_r_reg,
      I4 => left_aligned_r_reg_0,
      O => gthe2_i
    );
polarity_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => std_bool,
      I1 => realign_r,
      I2 => begin_r_reg_0,
      O => next_polarity_c
    );
polarity_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_polarity_c,
      Q => polarity_r,
      R => begin_r0
    );
prev_char_was_comma_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => RX_CHAR_IS_COMMA_R(1),
      I1 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c1
    );
prev_char_was_comma_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => inc_count_c1,
      Q => prev_char_was_comma_r,
      R => '0'
    );
ready_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \counter2_r_reg_n_0_[15]\,
      I1 => D,
      I2 => RX_NEG_Buffer,
      I3 => polarity_r,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D,
      R => begin_r0
    );
realign_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040404"
    )
        port map (
      I0 => begin_r_reg_0,
      I1 => realign_r,
      I2 => std_bool,
      I3 => std_bool0_in,
      I4 => \^align_r_reg_0\,
      O => next_realign_c
    );
realign_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_realign_c,
      Q => realign_r,
      R => begin_r0
    );
reset_count_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF04F5"
    )
        port map (
      I0 => reset_count_r_reg_0,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      I3 => \^rst_r_reg_0\,
      I4 => SR(0),
      O => reset_count_r0
    );
reset_count_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => reset_count_r0,
      Q => reset_count_r,
      R => '0'
    );
rst_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F2"
    )
        port map (
      I0 => \^rst_r_reg_0\,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => \^rst_r_reg_0\,
      R => begin_r0
    );
rx_polarity_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RX_NEG_Buffer,
      I1 => polarity_r,
      I2 => \^rx_polarity_i_0\,
      O => rx_polarity_r_i_1_n_0
    );
rx_polarity_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_polarity_r_i_1_n_0,
      Q => \^rx_polarity_i_0\,
      R => '0'
    );
\soft_err_r[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^enable_err_detect_i\,
      O => ENABLE_ERR_DETECT_Buffer_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8 is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    align_r_reg_0 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    rst_r_reg_0 : out STD_LOGIC;
    enable_err_detect_i : out STD_LOGIC;
    rx_polarity_i_2 : out STD_LOGIC;
    gthe2_i : out STD_LOGIC;
    ENABLE_ERR_DETECT_Buffer_reg_0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    begin_r0 : in STD_LOGIC;
    begin_r_reg_0 : in STD_LOGIC;
    RX_NEG_Buffer : in STD_LOGIC;
    reset_count_r_reg_0 : in STD_LOGIC;
    rx_sp_i : in STD_LOGIC;
    \counter2_r_reg[15]_0\ : in STD_LOGIC;
    \RX_CHAR_IS_COMMA_R_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg : in STD_LOGIC;
    left_aligned_r_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8 : entity is "aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX";
end aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8 is
  signal D : STD_LOGIC;
  signal RX_CHAR_IS_COMMA_R : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^align_r_reg_0\ : STD_LOGIC;
  signal begin_r : STD_LOGIC;
  signal comma_over_two_cycles_r0 : STD_LOGIC;
  signal counter1_r0 : STD_LOGIC;
  signal \counter1_r[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \counter1_r[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \counter1_r_reg_n_0_[7]\ : STD_LOGIC;
  signal counter2_r0 : STD_LOGIC;
  signal \counter2_r_reg[14]_srl15_n_0\ : STD_LOGIC;
  signal \counter2_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \^enable_err_detect_i\ : STD_LOGIC;
  signal inc_count_c : STD_LOGIC;
  signal inc_count_c1 : STD_LOGIC;
  signal next_align_c : STD_LOGIC;
  signal next_begin_c : STD_LOGIC;
  signal next_polarity_c : STD_LOGIC;
  signal next_ready_c : STD_LOGIC;
  signal next_realign_c : STD_LOGIC;
  signal next_rst_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal polarity_r : STD_LOGIC;
  signal prev_char_was_comma_r : STD_LOGIC;
  signal realign_r : STD_LOGIC;
  signal reset_count_r : STD_LOGIC;
  signal reset_count_r0 : STD_LOGIC;
  signal \^rst_r_reg_0\ : STD_LOGIC;
  signal \^rx_polarity_i_2\ : STD_LOGIC;
  signal \rx_polarity_r_i_1__1_n_0\ : STD_LOGIC;
  signal std_bool : STD_LOGIC;
  signal std_bool0_in : STD_LOGIC;
  signal std_bool0_in3_in : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \counter1_r[0]_i_4__1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \counter1_r[3]_i_1__1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \counter1_r[4]_i_1__1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \counter1_r[5]_i_1__1\ : label is "soft_lutpair56";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_2_i/rx_lane_init_sm_simplex_i/counter2_r_reg ";
  attribute srl_name : string;
  attribute srl_name of \counter2_r_reg[14]_srl15\ : label is "U0/\rx_aurora_lane_simplex_v5_2_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 ";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of lane_up_flop_i : label is "VCC:CE";
begin
  align_r_reg_0 <= \^align_r_reg_0\;
  enable_err_detect_i <= \^enable_err_detect_i\;
  rst_r_reg_0 <= \^rst_r_reg_0\;
  rx_polarity_i_2 <= \^rx_polarity_i_2\;
ENABLE_ERR_DETECT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => \^enable_err_detect_i\,
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      Q => RX_CHAR_IS_COMMA_R(0),
      R => '0'
    );
\RX_CHAR_IS_COMMA_R_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CHAR_IS_COMMA_R_reg[1]_0\(1),
      Q => RX_CHAR_IS_COMMA_R(1),
      R => '0'
    );
\align_r_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => std_bool0_in,
      I1 => \^align_r_reg_0\,
      I2 => std_bool0_in3_in,
      I3 => \^rst_r_reg_0\,
      O => next_align_c
    );
align_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_align_c,
      Q => \^align_r_reg_0\,
      R => begin_r0
    );
\begin_r_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
        port map (
      I0 => realign_r,
      I1 => begin_r_reg_0,
      I2 => D,
      I3 => \counter2_r_reg_n_0_[15]\,
      I4 => polarity_r,
      I5 => RX_NEG_Buffer,
      O => next_begin_c
    );
begin_r_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => next_begin_c,
      Q => begin_r,
      S => begin_r0
    );
\comma_over_two_cycles_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"57FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(0),
      I2 => RX_CHAR_IS_COMMA_R(1),
      I3 => prev_char_was_comma_r,
      O => comma_over_two_cycles_r0
    );
comma_over_two_cycles_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => comma_over_two_cycles_r0,
      Q => comma_over_two_cycles_r,
      R => '0'
    );
\counter1_r[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => D,
      I1 => reset_count_r,
      O => counter1_r0
    );
\counter1_r[0]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \^align_r_reg_0\,
      I1 => RX_CHAR_IS_COMMA_R(1),
      I2 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c
    );
\counter1_r[0]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool0_in,
      I1 => std_bool,
      I2 => std_bool0_in3_in,
      I3 => \counter1_r[0]_i_4__1_n_0\,
      I4 => \counter1_r_reg_n_0_[3]\,
      I5 => \counter1_r_reg_n_0_[1]\,
      O => p_0_in(7)
    );
\counter1_r[0]_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[5]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[7]\,
      O => \counter1_r[0]_i_4__1_n_0\
    );
\counter1_r[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[1]\,
      I1 => \counter1_r_reg_n_0_[3]\,
      I2 => \counter1_r[0]_i_4__1_n_0\,
      I3 => std_bool0_in3_in,
      I4 => std_bool,
      O => p_0_in(6)
    );
\counter1_r[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => std_bool,
      I1 => std_bool0_in3_in,
      I2 => \counter1_r_reg_n_0_[7]\,
      I3 => \counter1_r_reg_n_0_[6]\,
      I4 => \counter1_r_reg_n_0_[5]\,
      I5 => \counter1_r_reg_n_0_[3]\,
      O => \counter1_r[2]_i_1__1_n_0\
    );
\counter1_r[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[3]\,
      I1 => \counter1_r_reg_n_0_[5]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[7]\,
      I4 => std_bool0_in3_in,
      O => p_0_in(4)
    );
\counter1_r[4]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => std_bool0_in3_in,
      I1 => \counter1_r_reg_n_0_[7]\,
      I2 => \counter1_r_reg_n_0_[6]\,
      I3 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(3)
    );
\counter1_r[5]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      I2 => \counter1_r_reg_n_0_[5]\,
      O => p_0_in(2)
    );
\counter1_r[6]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      I1 => \counter1_r_reg_n_0_[6]\,
      O => p_0_in(1)
    );
\counter1_r[7]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \counter1_r_reg_n_0_[7]\,
      O => p_0_in(0)
    );
\counter1_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(7),
      Q => std_bool0_in,
      R => counter1_r0
    );
\counter1_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(6),
      Q => \counter1_r_reg_n_0_[1]\,
      R => counter1_r0
    );
\counter1_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => \counter1_r[2]_i_1__1_n_0\,
      Q => std_bool,
      R => counter1_r0
    );
\counter1_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(4),
      Q => \counter1_r_reg_n_0_[3]\,
      R => counter1_r0
    );
\counter1_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(3),
      Q => std_bool0_in3_in,
      R => counter1_r0
    );
\counter1_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(2),
      Q => \counter1_r_reg_n_0_[5]\,
      R => counter1_r0
    );
\counter1_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(1),
      Q => \counter1_r_reg_n_0_[6]\,
      R => counter1_r0
    );
\counter1_r_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => user_clk,
      CE => inc_count_c,
      D => p_0_in(0),
      Q => \counter1_r_reg_n_0_[7]\,
      S => counter1_r0
    );
\counter2_r_reg[14]_srl15\: unisim.vcomponents.SRL16E
     port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '1',
      CE => counter2_r0,
      CLK => user_clk,
      D => D,
      Q => \counter2_r_reg[14]_srl15_n_0\
    );
\counter2_r_reg[14]_srl15_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D5"
    )
        port map (
      I0 => D,
      I1 => rx_sp_i,
      I2 => \counter2_r_reg[15]_0\,
      O => counter2_r0
    );
\counter2_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => counter2_r0,
      D => \counter2_r_reg[14]_srl15_n_0\,
      Q => \counter2_r_reg_n_0_[15]\,
      R => '0'
    );
lane_up_flop_i: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D,
      Q => RX_LANE_UP(0),
      R => SR(0)
    );
\left_aligned_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAB00A8"
    )
        port map (
      I0 => \RX_CHAR_IS_COMMA_R_reg[1]_0\(0),
      I1 => \^align_r_reg_0\,
      I2 => D,
      I3 => left_aligned_r_reg,
      I4 => left_aligned_r_reg_0,
      O => gthe2_i
    );
\polarity_r_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => std_bool,
      I1 => realign_r,
      I2 => begin_r_reg_0,
      O => next_polarity_c
    );
polarity_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_polarity_c,
      Q => polarity_r,
      R => begin_r0
    );
\prev_char_was_comma_r_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => RX_CHAR_IS_COMMA_R(1),
      I1 => RX_CHAR_IS_COMMA_R(0),
      O => inc_count_c1
    );
prev_char_was_comma_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => inc_count_c1,
      Q => prev_char_was_comma_r,
      R => '0'
    );
\ready_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \counter2_r_reg_n_0_[15]\,
      I1 => D,
      I2 => RX_NEG_Buffer,
      I3 => polarity_r,
      O => next_ready_c
    );
ready_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_ready_c,
      Q => D,
      R => begin_r0
    );
\realign_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040404"
    )
        port map (
      I0 => begin_r_reg_0,
      I1 => realign_r,
      I2 => std_bool,
      I3 => std_bool0_in,
      I4 => \^align_r_reg_0\,
      O => next_realign_c
    );
realign_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_realign_c,
      Q => realign_r,
      R => begin_r0
    );
\reset_count_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF04F5"
    )
        port map (
      I0 => reset_count_r_reg_0,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      I3 => \^rst_r_reg_0\,
      I4 => SR(0),
      O => reset_count_r0
    );
reset_count_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => reset_count_r0,
      Q => reset_count_r,
      R => '0'
    );
\rst_r_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F2"
    )
        port map (
      I0 => \^rst_r_reg_0\,
      I1 => std_bool0_in3_in,
      I2 => begin_r,
      O => next_rst_c
    );
rst_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => next_rst_c,
      Q => \^rst_r_reg_0\,
      R => begin_r0
    );
\rx_polarity_r_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => RX_NEG_Buffer,
      I1 => polarity_r,
      I2 => \^rx_polarity_i_2\,
      O => \rx_polarity_r_i_1__1_n_0\
    );
rx_polarity_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \rx_polarity_r_i_1__1_n_0\,
      Q => \^rx_polarity_i_2\,
      R => '0'
    );
\soft_err_r[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^enable_err_detect_i\,
      O => ENABLE_ERR_DETECT_Buffer_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LL_DEFRAMER is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \DEFRAMED_DATA_V_Buffer_reg[2]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \AFTER_SCP_Buffer_reg[3]_0\ : out STD_LOGIC;
    std_bool : out STD_LOGIC;
    \AFTER_SCP_Buffer_reg[3]_1\ : out STD_LOGIC;
    \stage_1_ecp_r_reg[3]\ : out STD_LOGIC;
    in_frame_muxcy_0_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    in_frame_muxcy_1_0 : in STD_LOGIC;
    in_frame_muxcy_2_0 : in STD_LOGIC;
    in_frame_muxcy_3_0 : in STD_LOGIC;
    S5_in : in STD_LOGIC;
    S3_in : in STD_LOGIC;
    S1_in : in STD_LOGIC;
    data_after_start_muxcy_3_0 : in STD_LOGIC;
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    stage_2_frame_err_r_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
    stage_2_frame_err_r_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \DEFRAMED_DATA_V_Buffer_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
end aurora_rx_4l_64b_RX_LL_DEFRAMER;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LL_DEFRAMER is
  signal CI : STD_LOGIC;
  signal \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal \DEFRAMED_DATA_V_Buffer[2]_i_1_n_0\ : STD_LOGIC;
  signal \DEFRAMED_DATA_V_Buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal after_scp_c_1 : STD_LOGIC;
  signal after_scp_c_2 : STD_LOGIC;
  signal after_scp_c_3 : STD_LOGIC;
  signal data_after_start_muxcy_3_n_0 : STD_LOGIC;
  signal in_frame_c_0 : STD_LOGIC;
  signal in_frame_c_1 : STD_LOGIC;
  signal in_frame_c_2 : STD_LOGIC;
  signal in_frame_c_3 : STD_LOGIC;
  signal stage_1_after_scp_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal stage_1_data_v_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal stage_1_in_frame_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal stage_2_end_after_start_r_i_2_n_0 : STD_LOGIC;
  signal stage_2_end_before_start_r_i_2_n_0 : STD_LOGIC;
  signal stage_2_frame_err_r_i_2_n_0 : STD_LOGIC;
  signal stage_2_frame_err_r_i_3_n_0 : STD_LOGIC;
  signal stage_2_start_with_data_r_i_2_n_0 : STD_LOGIC;
  signal NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \COUNT_Buffer[0]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \COUNT_Buffer[1]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \COUNT_Buffer[2]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \MUX_SELECT_Buffer[1]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \MUX_SELECT_Buffer[2]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \MUX_SELECT_Buffer[4]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \MUX_SELECT_Buffer[5]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \MUX_SELECT_Buffer[8]_i_1\ : label is "soft_lutpair98";
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of data_after_start_muxcy_0_CARRY4 : label is "PRIMITIVE";
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of data_after_start_muxcy_0_CARRY4 : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of data_after_start_muxcy_0_CARRY4 : label is "(MUXCY,XORCY)";
  attribute BOX_TYPE of in_frame_muxcy_0_CARRY4 : label is "PRIMITIVE";
  attribute OPT_MODIFIED of in_frame_muxcy_0_CARRY4 : label is "MLO";
  attribute XILINX_LEGACY_PRIM of in_frame_muxcy_0_CARRY4 : label is "(MUXCY,XORCY)";
  attribute SOFT_HLUTNM of stage_2_end_after_start_r_i_2 : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of stage_2_end_before_start_r_i_2 : label is "soft_lutpair94";
begin
\AFTER_SCP_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => after_scp_c_3,
      Q => stage_1_after_scp_r(0),
      R => RESET
    );
\AFTER_SCP_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => after_scp_c_2,
      Q => stage_1_after_scp_r(1),
      R => RESET
    );
\AFTER_SCP_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => after_scp_c_1,
      Q => stage_1_after_scp_r(2),
      R => RESET
    );
\AFTER_SCP_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => data_after_start_muxcy_3_n_0,
      Q => stage_1_after_scp_r(3),
      R => RESET
    );
\COUNT_Buffer[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => stage_1_data_v_r(3),
      I1 => stage_1_data_v_r(1),
      I2 => stage_1_data_v_r(2),
      I3 => stage_1_data_v_r(0),
      O => D(2)
    );
\COUNT_Buffer[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => stage_1_data_v_r(3),
      I1 => stage_1_data_v_r(1),
      I2 => stage_1_data_v_r(2),
      I3 => stage_1_data_v_r(0),
      O => D(1)
    );
\COUNT_Buffer[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => stage_1_data_v_r(0),
      I1 => stage_1_data_v_r(2),
      I2 => stage_1_data_v_r(1),
      I3 => stage_1_data_v_r(3),
      O => D(0)
    );
\DEFRAMED_DATA_V_Buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => in_frame_c_3,
      I1 => \DEFRAMED_DATA_V_Buffer_reg[0]_0\(3),
      O => \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0\
    );
\DEFRAMED_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => in_frame_c_2,
      I1 => \DEFRAMED_DATA_V_Buffer_reg[0]_0\(2),
      O => \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0\
    );
\DEFRAMED_DATA_V_Buffer[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => in_frame_c_1,
      I1 => \DEFRAMED_DATA_V_Buffer_reg[0]_0\(1),
      O => \DEFRAMED_DATA_V_Buffer[2]_i_1_n_0\
    );
\DEFRAMED_DATA_V_Buffer[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => in_frame_c_0,
      I1 => \DEFRAMED_DATA_V_Buffer_reg[0]_0\(0),
      O => \DEFRAMED_DATA_V_Buffer[3]_i_1_n_0\
    );
\DEFRAMED_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0\,
      Q => stage_1_data_v_r(0),
      R => RESET
    );
\DEFRAMED_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0\,
      Q => stage_1_data_v_r(1),
      R => RESET
    );
\DEFRAMED_DATA_V_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \DEFRAMED_DATA_V_Buffer[2]_i_1_n_0\,
      Q => stage_1_data_v_r(2),
      R => RESET
    );
\DEFRAMED_DATA_V_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \DEFRAMED_DATA_V_Buffer[3]_i_1_n_0\,
      Q => stage_1_data_v_r(3),
      R => RESET
    );
\IN_FRAME_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => CI,
      Q => stage_1_in_frame_r(0),
      R => RESET
    );
\IN_FRAME_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => in_frame_c_3,
      Q => stage_1_in_frame_r(1),
      R => RESET
    );
\IN_FRAME_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => in_frame_c_2,
      Q => stage_1_in_frame_r(2),
      R => RESET
    );
\IN_FRAME_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => in_frame_c_1,
      Q => stage_1_in_frame_r(3),
      R => RESET
    );
\MUX_SELECT_Buffer[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => stage_1_data_v_r(2),
      I1 => stage_1_data_v_r(3),
      I2 => stage_1_data_v_r(0),
      I3 => stage_1_data_v_r(1),
      O => \DEFRAMED_DATA_V_Buffer_reg[2]_0\(4)
    );
\MUX_SELECT_Buffer[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5504"
    )
        port map (
      I0 => stage_1_data_v_r(0),
      I1 => stage_1_data_v_r(3),
      I2 => stage_1_data_v_r(2),
      I3 => stage_1_data_v_r(1),
      O => \DEFRAMED_DATA_V_Buffer_reg[2]_0\(3)
    );
\MUX_SELECT_Buffer[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1060"
    )
        port map (
      I0 => stage_1_data_v_r(1),
      I1 => stage_1_data_v_r(0),
      I2 => stage_1_data_v_r(3),
      I3 => stage_1_data_v_r(2),
      O => \DEFRAMED_DATA_V_Buffer_reg[2]_0\(2)
    );
\MUX_SELECT_Buffer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => stage_1_data_v_r(0),
      I1 => stage_1_data_v_r(1),
      I2 => stage_1_data_v_r(2),
      O => \DEFRAMED_DATA_V_Buffer_reg[2]_0\(1)
    );
\MUX_SELECT_Buffer[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6800"
    )
        port map (
      I0 => stage_1_data_v_r(0),
      I1 => stage_1_data_v_r(1),
      I2 => stage_1_data_v_r(2),
      I3 => stage_1_data_v_r(3),
      O => \DEFRAMED_DATA_V_Buffer_reg[2]_0\(0)
    );
data_after_start_muxcy_0_CARRY4: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => data_after_start_muxcy_3_n_0,
      CO(2) => after_scp_c_1,
      CO(1) => after_scp_c_2,
      CO(0) => after_scp_c_3,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3 downto 0) => NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED(3 downto 0),
      S(3) => data_after_start_muxcy_3_0,
      S(2) => S1_in,
      S(1) => S3_in,
      S(0) => S5_in
    );
in_frame_muxcy_0_CARRY4: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => in_frame_c_0,
      CO(2) => in_frame_c_1,
      CO(1) => in_frame_c_2,
      CO(0) => in_frame_c_3,
      CYINIT => CI,
      DI(3) => Q(0),
      DI(2) => Q(1),
      DI(1) => Q(2),
      DI(0) => Q(3),
      O(3 downto 0) => NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED(3 downto 0),
      S(3) => in_frame_muxcy_3_0,
      S(2) => in_frame_muxcy_2_0,
      S(1) => in_frame_muxcy_1_0,
      S(0) => in_frame_muxcy_0_0
    );
in_frame_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => in_frame_c_0,
      Q => CI,
      R => RESET
    );
stage_2_end_after_start_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => stage_1_after_scp_r(3),
      I1 => stage_2_frame_err_r_reg_0(0),
      I2 => stage_1_after_scp_r(2),
      I3 => stage_2_frame_err_r_reg_0(1),
      I4 => stage_2_end_after_start_r_i_2_n_0,
      O => \AFTER_SCP_Buffer_reg[3]_1\
    );
stage_2_end_after_start_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => stage_2_frame_err_r_reg_0(2),
      I1 => stage_1_after_scp_r(1),
      I2 => stage_2_frame_err_r_reg_0(3),
      I3 => stage_1_after_scp_r(0),
      O => stage_2_end_after_start_r_i_2_n_0
    );
stage_2_end_before_start_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF22F2"
    )
        port map (
      I0 => stage_2_frame_err_r_reg_0(0),
      I1 => stage_1_after_scp_r(3),
      I2 => stage_2_frame_err_r_reg_0(1),
      I3 => stage_1_after_scp_r(2),
      I4 => stage_2_end_before_start_r_i_2_n_0,
      O => std_bool
    );
stage_2_end_before_start_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => stage_1_after_scp_r(1),
      I1 => stage_2_frame_err_r_reg_0(2),
      I2 => stage_1_after_scp_r(0),
      I3 => stage_2_frame_err_r_reg_0(3),
      O => stage_2_end_before_start_r_i_2_n_0
    );
stage_2_frame_err_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => stage_2_frame_err_r_i_2_n_0,
      I1 => stage_2_frame_err_r_i_3_n_0,
      O => \stage_1_ecp_r_reg[3]\
    );
stage_2_frame_err_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFE2E2E2FFE2"
    )
        port map (
      I0 => stage_2_frame_err_r_reg_0(0),
      I1 => stage_1_in_frame_r(3),
      I2 => stage_2_frame_err_r_reg(0),
      I3 => stage_2_frame_err_r_reg_0(1),
      I4 => stage_1_in_frame_r(2),
      I5 => stage_2_frame_err_r_reg(1),
      O => stage_2_frame_err_r_i_2_n_0
    );
stage_2_frame_err_r_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEFAEEFAFFFFCCF0"
    )
        port map (
      I0 => stage_2_frame_err_r_reg(3),
      I1 => stage_2_frame_err_r_reg(2),
      I2 => stage_2_frame_err_r_reg_0(2),
      I3 => stage_1_in_frame_r(1),
      I4 => stage_2_frame_err_r_reg_0(3),
      I5 => stage_1_in_frame_r(0),
      O => stage_2_frame_err_r_i_3_n_0
    );
stage_2_start_with_data_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => stage_1_after_scp_r(3),
      I1 => stage_1_data_v_r(3),
      I2 => stage_1_after_scp_r(2),
      I3 => stage_1_data_v_r(2),
      I4 => stage_2_start_with_data_r_i_2_n_0,
      O => \AFTER_SCP_Buffer_reg[3]_0\
    );
stage_2_start_with_data_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F888"
    )
        port map (
      I0 => stage_1_data_v_r(0),
      I1 => stage_1_after_scp_r(0),
      I2 => stage_1_data_v_r(1),
      I3 => stage_1_after_scp_r(1),
      O => stage_2_start_with_data_r_i_2_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_SIDEBAND_OUTPUT is
  port (
    stage_3_end_storage_r : out STD_LOGIC;
    stage_2_frame_err_r_reg : out STD_LOGIC;
    SRC_RDY_N_Buffer : out STD_LOGIC;
    EOF_N_Buffer : out STD_LOGIC;
    FRAME_ERR_RESULT_Buffer : out STD_LOGIC;
    stage_2_start_with_data_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_REM_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    end_storage_r0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    EOF_N_Buffer_reg_0 : in STD_LOGIC;
    FRAME_ERR_RESULT_Buffer0 : in STD_LOGIC;
    stage_2_end_before_start_r : in STD_LOGIC;
    stage_2_start_with_data_r : in STD_LOGIC;
    pad_storage_r_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_REM_Buffer_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    stage_2_pad_r : in STD_LOGIC;
    stage_2_frame_err_r : in STD_LOGIC;
    start_rx_i : in STD_LOGIC
  );
end aurora_rx_4l_64b_SIDEBAND_OUTPUT;

architecture STRUCTURE of aurora_rx_4l_64b_SIDEBAND_OUTPUT is
  signal SRC_RDY_N_Buffer_i_1_n_0 : STD_LOGIC;
  signal pad_storage_r : STD_LOGIC;
  signal pad_storage_r_i_1_n_0 : STD_LOGIC;
  signal rx_rem_c : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^stage_2_frame_err_r_reg\ : STD_LOGIC;
  signal \^stage_3_end_storage_r\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \RX_REM_Buffer[1]_i_1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \storage_count_r[2]_i_1__0\ : label is "soft_lutpair93";
begin
  stage_2_frame_err_r_reg <= \^stage_2_frame_err_r_reg\;
  stage_3_end_storage_r <= \^stage_3_end_storage_r\;
EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EOF_N_Buffer_reg_0,
      Q => EOF_N_Buffer,
      R => '0'
    );
FRAME_ERR_RESULT_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => FRAME_ERR_RESULT_Buffer0,
      Q => FRAME_ERR_RESULT_Buffer,
      R => '0'
    );
\OUTPUT_SELECT_Buffer[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => stage_2_start_with_data_r,
      I1 => \^stage_3_end_storage_r\,
      O => SR(0)
    );
\RX_REM_Buffer[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"10EF"
    )
        port map (
      I0 => stage_2_start_with_data_r,
      I1 => \^stage_3_end_storage_r\,
      I2 => Q(0),
      I3 => \RX_REM_Buffer_reg[1]_0\(0),
      O => rx_rem_c(1)
    );
\RX_REM_Buffer[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FD"
    )
        port map (
      I0 => stage_2_pad_r,
      I1 => stage_2_start_with_data_r,
      I2 => \^stage_3_end_storage_r\,
      I3 => pad_storage_r,
      O => rx_rem_c(0)
    );
\RX_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => \RX_REM_Buffer_reg[0]_0\(2),
      R => '0'
    );
\RX_REM_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_rem_c(1),
      Q => \RX_REM_Buffer_reg[0]_0\(1),
      R => '0'
    );
\RX_REM_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_rem_c(0),
      Q => \RX_REM_Buffer_reg[0]_0\(0),
      R => '0'
    );
SRC_RDY_N_Buffer_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"04FF"
    )
        port map (
      I0 => stage_2_end_before_start_r,
      I1 => stage_2_start_with_data_r,
      I2 => \^stage_3_end_storage_r\,
      I3 => pad_storage_r_reg_0,
      O => SRC_RDY_N_Buffer_i_1_n_0
    );
SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => SRC_RDY_N_Buffer_i_1_n_0,
      Q => SRC_RDY_N_Buffer,
      S => \^stage_2_frame_err_r_reg\
    );
end_storage_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => end_storage_r0,
      Q => \^stage_3_end_storage_r\,
      R => \^stage_2_frame_err_r_reg\
    );
pad_storage_r_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBFBBAAAAAAAA"
    )
        port map (
      I0 => stage_2_pad_r,
      I1 => pad_storage_r_reg_0,
      I2 => \^stage_3_end_storage_r\,
      I3 => stage_2_start_with_data_r,
      I4 => stage_2_end_before_start_r,
      I5 => pad_storage_r,
      O => pad_storage_r_i_1_n_0
    );
pad_storage_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => pad_storage_r_i_1_n_0,
      Q => pad_storage_r,
      R => \^stage_2_frame_err_r_reg\
    );
\storage_count_r[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => stage_2_frame_err_r,
      I1 => start_rx_i,
      O => \^stage_2_frame_err_r_reg\
    );
\storage_count_r[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF10"
    )
        port map (
      I0 => stage_2_start_with_data_r,
      I1 => \^stage_3_end_storage_r\,
      I2 => \RX_REM_Buffer_reg[1]_0\(0),
      I3 => Q(0),
      O => stage_2_start_with_data_r_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_STORAGE_CE_CONTROL is
  port (
    Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
    RESET : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_STORAGE_CE_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_STORAGE_CE_CONTROL is
begin
\STORAGE_CE_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => Q(3),
      R => RESET
    );
\STORAGE_CE_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => Q(2),
      R => RESET
    );
\STORAGE_CE_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => RESET
    );
\STORAGE_CE_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_STORAGE_COUNT_CONTROL is
  port (
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    end_storage_r_reg : out STD_LOGIC;
    stage_2_start_with_data_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    FRAME_ERR_RESULT_Buffer0 : out STD_LOGIC;
    end_storage_r0 : out STD_LOGIC;
    \storage_count_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \storage_count_r_reg[2]_0\ : out STD_LOGIC;
    \storage_count_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \storage_count_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \storage_count_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    stage_3_end_storage_r : in STD_LOGIC;
    stage_2_start_with_data_r : in STD_LOGIC;
    stage_2_frame_err_r : in STD_LOGIC;
    stage_2_end_after_start_r : in STD_LOGIC;
    stage_2_end_before_start_r : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_STORAGE_COUNT_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_STORAGE_COUNT_CONTROL is
  signal FRAME_ERR_RESULT_Buffer_i_2_n_0 : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal end_storage_r_i_2_n_0 : STD_LOGIC;
  signal \^end_storage_r_reg\ : STD_LOGIC;
  signal stage_3_storage_count_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal storage_count_c : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \storage_count_r[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \storage_count_r[0]_i_5_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of FRAME_ERR_RESULT_Buffer_i_2 : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \OUTPUT_SELECT_Buffer[18]_i_1\ : label is "soft_lutpair107";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
  end_storage_r_reg <= \^end_storage_r_reg\;
EOF_N_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001FFFFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => stage_3_storage_count_r(0),
      I2 => \^q\(1),
      I3 => stage_2_start_with_data_r,
      I4 => stage_2_end_before_start_r,
      I5 => stage_3_end_storage_r,
      O => \storage_count_r_reg[2]_0\
    );
FRAME_ERR_RESULT_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CFCECFCCFFFECFCC"
    )
        port map (
      I0 => end_storage_r_i_2_n_0,
      I1 => stage_2_frame_err_r,
      I2 => stage_2_start_with_data_r,
      I3 => stage_2_end_after_start_r,
      I4 => stage_2_end_before_start_r,
      I5 => FRAME_ERR_RESULT_Buffer_i_2_n_0,
      O => FRAME_ERR_RESULT_Buffer0
    );
FRAME_ERR_RESULT_Buffer_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^q\(0),
      I1 => stage_3_storage_count_r(0),
      I2 => \^q\(1),
      O => FRAME_ERR_RESULT_Buffer_i_2_n_0
    );
\OUTPUT_SELECT_Buffer[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => stage_3_storage_count_r(0),
      I1 => \^q\(1),
      O => \storage_count_r_reg[0]_0\(2)
    );
\OUTPUT_SELECT_Buffer[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      I1 => stage_3_storage_count_r(0),
      O => \storage_count_r_reg[0]_0\(1)
    );
\OUTPUT_SELECT_Buffer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"13"
    )
        port map (
      I0 => \^q\(0),
      I1 => stage_3_storage_count_r(0),
      I2 => \^q\(1),
      O => \storage_count_r_reg[0]_0\(0)
    );
\RX_REM_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E1F00F1EE1F01E0F"
    )
        port map (
      I0 => stage_2_start_with_data_r,
      I1 => stage_3_end_storage_r,
      I2 => \^q\(1),
      I3 => \storage_count_r_reg[0]_1\(1),
      I4 => \^q\(0),
      I5 => \storage_count_r_reg[0]_1\(0),
      O => stage_2_start_with_data_r_reg(0)
    );
\STORAGE_CE_Buffer[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => \^end_storage_r_reg\,
      I1 => \^q\(1),
      I2 => stage_3_storage_count_r(0),
      I3 => \^q\(0),
      O => D(3)
    );
\STORAGE_CE_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"AB"
    )
        port map (
      I0 => \^end_storage_r_reg\,
      I1 => stage_3_storage_count_r(0),
      I2 => \^q\(1),
      O => D(2)
    );
\STORAGE_CE_Buffer[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF07"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => stage_3_storage_count_r(0),
      I3 => \^end_storage_r_reg\,
      O => D(1)
    );
\STORAGE_CE_Buffer[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^end_storage_r_reg\,
      I1 => stage_3_storage_count_r(0),
      O => D(0)
    );
\STORAGE_SELECT_Buffer[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      O => \storage_count_r_reg[1]_0\(2)
    );
\STORAGE_SELECT_Buffer[18]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(1),
      O => \storage_count_r_reg[1]_0\(1)
    );
\STORAGE_SELECT_Buffer[19]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(0),
      O => \storage_count_r_reg[1]_0\(0)
    );
\STORAGE_SELECT_Buffer[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \storage_count_r_reg[1]_0\(3)
    );
end_storage_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88B8"
    )
        port map (
      I0 => stage_2_end_after_start_r,
      I1 => stage_2_start_with_data_r,
      I2 => stage_2_end_before_start_r,
      I3 => end_storage_r_i_2_n_0,
      O => end_storage_r0
    );
end_storage_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \^q\(1),
      I1 => \storage_count_r_reg[0]_1\(1),
      I2 => \^q\(0),
      I3 => \storage_count_r_reg[0]_1\(0),
      I4 => stage_3_storage_count_r(0),
      I5 => \storage_count_r_reg[0]_1\(2),
      O => end_storage_r_i_2_n_0
    );
\storage_count_r[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F1F4F1F4F1D771"
    )
        port map (
      I0 => \^end_storage_r_reg\,
      I1 => \storage_count_r[0]_i_4__0_n_0\,
      I2 => \storage_count_r_reg[0]_1\(2),
      I3 => stage_3_storage_count_r(0),
      I4 => stage_3_end_storage_r,
      I5 => stage_2_start_with_data_r,
      O => storage_count_c(0)
    );
\storage_count_r[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFFFEFFFEFFFF"
    )
        port map (
      I0 => stage_3_end_storage_r,
      I1 => stage_2_start_with_data_r,
      I2 => stage_3_storage_count_r(0),
      I3 => \storage_count_r_reg[0]_1\(2),
      I4 => \storage_count_r[0]_i_4__0_n_0\,
      I5 => \storage_count_r[0]_i_5_n_0\,
      O => \^end_storage_r_reg\
    );
\storage_count_r[0]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1777"
    )
        port map (
      I0 => \^q\(1),
      I1 => \storage_count_r_reg[0]_1\(1),
      I2 => \^q\(0),
      I3 => \storage_count_r_reg[0]_1\(0),
      O => \storage_count_r[0]_i_4__0_n_0\
    );
\storage_count_r[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6009"
    )
        port map (
      I0 => \^q\(1),
      I1 => \storage_count_r_reg[0]_1\(1),
      I2 => \^q\(0),
      I3 => \storage_count_r_reg[0]_1\(0),
      O => \storage_count_r[0]_i_5_n_0\
    );
\storage_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => storage_count_c(0),
      Q => stage_3_storage_count_r(0),
      R => SR(0)
    );
\storage_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \storage_count_r_reg[1]_1\(1),
      Q => \^q\(1),
      R => SR(0)
    );
\storage_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \storage_count_r_reg[1]_1\(0),
      Q => \^q\(0),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_STORAGE_MUX is
  port (
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    E : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D : in STD_LOGIC_VECTOR ( 63 downto 0 );
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_STORAGE_MUX;

architecture STRUCTURE of aurora_rx_4l_64b_STORAGE_MUX is
begin
\STORAGE_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(63),
      Q => Q(63),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(53),
      Q => Q(53),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(52),
      Q => Q(52),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(51),
      Q => Q(51),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(50),
      Q => Q(50),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(49),
      Q => Q(49),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(48),
      Q => Q(48),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(47),
      Q => Q(47),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(46),
      Q => Q(46),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(45),
      Q => Q(45),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(44),
      Q => Q(44),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(62),
      Q => Q(62),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(43),
      Q => Q(43),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(42),
      Q => Q(42),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(41),
      Q => Q(41),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(40),
      Q => Q(40),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(39),
      Q => Q(39),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(38),
      Q => Q(38),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(37),
      Q => Q(37),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(36),
      Q => Q(36),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(35),
      Q => Q(35),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(34),
      Q => Q(34),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(61),
      Q => Q(61),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(33),
      Q => Q(33),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(2),
      D => D(32),
      Q => Q(32),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(31),
      Q => Q(31),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(30),
      Q => Q(30),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(29),
      Q => Q(29),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(28),
      Q => Q(28),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(27),
      Q => Q(27),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(26),
      Q => Q(26),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(25),
      Q => Q(25),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(24),
      Q => Q(24),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(60),
      Q => Q(60),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(23),
      Q => Q(23),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(22),
      Q => Q(22),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(21),
      Q => Q(21),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(20),
      Q => Q(20),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(19),
      Q => Q(19),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(18),
      Q => Q(18),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(17),
      Q => Q(17),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(1),
      D => D(16),
      Q => Q(16),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(15),
      Q => Q(15),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(14),
      Q => Q(14),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(59),
      Q => Q(59),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(13),
      Q => Q(13),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(12),
      Q => Q(12),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(11),
      Q => Q(11),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(10),
      Q => Q(10),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(9),
      Q => Q(9),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(8),
      Q => Q(8),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(7),
      Q => Q(7),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(6),
      Q => Q(6),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(5),
      Q => Q(5),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(4),
      Q => Q(4),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(58),
      Q => Q(58),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(3),
      Q => Q(3),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(2),
      Q => Q(2),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(0),
      D => D(0),
      Q => Q(0),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(57),
      Q => Q(57),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(56),
      Q => Q(56),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(55),
      Q => Q(55),
      R => '0'
    );
\STORAGE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => E(3),
      D => D(54),
      Q => Q(54),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 4 downto 0 );
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL is
begin
\STORAGE_SELECT_Buffer_reg[13]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => Q(2),
      S => SR(0)
    );
\STORAGE_SELECT_Buffer_reg[18]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      S => SR(0)
    );
\STORAGE_SELECT_Buffer_reg[19]\: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      S => SR(0)
    );
\STORAGE_SELECT_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(4),
      Q => Q(4),
      R => SR(0)
    );
\STORAGE_SELECT_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => Q(3),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_SYM_DEC is
  port (
    RX_NEG_Buffer : out STD_LOGIC;
    rx_sp_i : out STD_LOGIC;
    GOT_V_Buffer_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[9]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_0\ : out STD_LOGIC;
    RX_SCP_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    left_aligned_r_reg_0 : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg_1 : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]_1\ : out STD_LOGIC;
    bad_as_r0 : out STD_LOGIC;
    \GOT_A_Buffer_reg[0]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[9]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_0\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    left_aligned_r_reg_1 : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    RX_PE_DATA : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stage_1_count_value_r_reg[2]_0\ : in STD_LOGIC;
    GOT_A : in STD_LOGIC_VECTOR ( 0 to 1 );
    bad_as_r_reg : in STD_LOGIC;
    bad_as_r_reg_0 : in STD_LOGIC;
    bad_as_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    bad_as_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \word_aligned_data_r_reg[8]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
end aurora_rx_4l_64b_SYM_DEC;

architecture STRUCTURE of aurora_rx_4l_64b_SYM_DEC is
  signal \EXP_IN_inferred__0/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__1/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__14/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__15/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__16/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__17/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__18/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__19/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__20/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__24/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__25/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__26/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__27/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__28/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__29/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__4/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__6/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__7/i__n_0\ : STD_LOGIC;
  signal EXP_IN_n_0 : STD_LOGIC;
  signal \GOT_A_Buffer[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \^got_a_buffer_reg[0]_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \RX_CC_Buffer_i_1__2_n_0\ : STD_LOGIC;
  signal RX_NEG_Buffer0 : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[10]_0\ : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[8]_0\ : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[9]_0\ : STD_LOGIC;
  signal \RX_PE_DATA_V_Buffer_i_1__2_n_0\ : STD_LOGIC;
  signal \RX_SCP_Buffer_i_1__2_n_0\ : STD_LOGIC;
  signal \RX_SP_Buffer_i_2__2_n_0\ : STD_LOGIC;
  signal \^rx_suf_buffer_reg_0\ : STD_LOGIC;
  signal bad_as_r_i_2_n_0 : STD_LOGIC;
  signal \^first_v_received_r\ : STD_LOGIC;
  signal \first_v_received_r_i_1__2_n_0\ : STD_LOGIC;
  signal \first_v_received_r_i_2__2_n_0\ : STD_LOGIC;
  signal got_a_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal got_v_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal p_15_in : STD_LOGIC;
  signal p_18_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_out : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal prev_beat_sp_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal prev_beat_sp_r : STD_LOGIC;
  signal \prev_beat_sp_r_i_1__2_n_0\ : STD_LOGIC;
  signal prev_beat_v_r : STD_LOGIC;
  signal \prev_beat_v_r_i_1__2_n_0\ : STD_LOGIC;
  signal rx_cc_r : STD_LOGIC_VECTOR ( 1 to 3 );
  signal \rx_ecp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_pad_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rx_pe_control_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rx_pe_data_r : STD_LOGIC_VECTOR ( 8 to 10 );
  signal \rx_scp_d_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rx_scp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_sp_c : STD_LOGIC;
  signal rx_sp_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal rx_sp_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal rx_spa_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \rx_suf_d_r_reg_n_0_[0]\ : STD_LOGIC;
  signal rx_v_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal std_bool : STD_LOGIC;
  signal std_bool10_in : STD_LOGIC;
  signal std_bool12_out : STD_LOGIC;
  signal std_bool4_in : STD_LOGIC;
  signal std_bool7_in : STD_LOGIC;
  signal std_bool9_out : STD_LOGIC;
  signal word_aligned_control_bits_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \^word_aligned_data_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^word_aligned_data_r_reg[11]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EXP_IN : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__0/i_\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__1/i_\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__10/i_\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__11/i_\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__12/i_\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__14/i_\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__15/i_\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__16/i_\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__17/i_\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__18/i_\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__19/i_\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__2/i_\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__20/i_\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__24/i_\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__25/i_\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__28/i_\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__3/i_\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__4/i_\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__6/i_\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__7/i_\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__9/i_\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \rx_sp_d_r[0]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \rx_sp_d_r[1]_i_1\ : label is "soft_lutpair80";
begin
  \GOT_A_Buffer_reg[0]_0\ <= \^got_a_buffer_reg[0]_0\;
  Q(0) <= \^q\(0);
  \RX_PE_DATA_Buffer_reg[10]_0\ <= \^rx_pe_data_buffer_reg[10]_0\;
  \RX_PE_DATA_Buffer_reg[8]_0\ <= \^rx_pe_data_buffer_reg[8]_0\;
  \RX_PE_DATA_Buffer_reg[9]_0\ <= \^rx_pe_data_buffer_reg[9]_0\;
  RX_SUF_Buffer_reg_0 <= \^rx_suf_buffer_reg_0\;
  first_v_received_r <= \^first_v_received_r\;
  \word_aligned_data_r_reg[0]_0\(7 downto 0) <= \^word_aligned_data_r_reg[0]_0\(7 downto 0);
  \word_aligned_data_r_reg[11]_0\(4 downto 0) <= \^word_aligned_data_r_reg[11]_0\(4 downto 0);
EXP_IN: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(1),
      I2 => \^word_aligned_data_r_reg[11]_0\(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => EXP_IN_n_0
    );
\EXP_IN_inferred__0/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(4),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => p_0_in(1),
      O => \EXP_IN_inferred__0/i__n_0\
    );
\EXP_IN_inferred__1/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(1),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__1/i__n_0\
    );
\EXP_IN_inferred__10/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(0),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(3),
      O => std_bool9_out
    );
\EXP_IN_inferred__11/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(3),
      I2 => p_0_in(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => std_bool10_in
    );
\EXP_IN_inferred__12/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(4),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => p_0_in(2),
      O => std_bool12_out
    );
\EXP_IN_inferred__14/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(3),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__14/i__n_0\
    );
\EXP_IN_inferred__15/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \^word_aligned_data_r_reg[11]_0\(4),
      I2 => p_0_in(2),
      I3 => p_0_in(3),
      O => \EXP_IN_inferred__15/i__n_0\
    );
\EXP_IN_inferred__16/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__16/i__n_0\
    );
\EXP_IN_inferred__17/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(0),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(1),
      O => \EXP_IN_inferred__17/i__n_0\
    );
\EXP_IN_inferred__18/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__18/i__n_0\
    );
\EXP_IN_inferred__19/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(5),
      I1 => \^word_aligned_data_r_reg[0]_0\(4),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(7),
      O => \EXP_IN_inferred__19/i__n_0\
    );
\EXP_IN_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(5),
      O => std_bool
    );
\EXP_IN_inferred__20/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__20/i__n_0\
    );
\EXP_IN_inferred__24/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(3),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__24/i__n_0\
    );
\EXP_IN_inferred__25/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__25/i__n_0\
    );
\EXP_IN_inferred__26/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(3),
      I1 => p_0_in(2),
      I2 => p_0_in(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__26/i__n_0\
    );
\EXP_IN_inferred__27/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__27/i__n_0\
    );
\EXP_IN_inferred__28/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(3),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__28/i__n_0\
    );
\EXP_IN_inferred__29/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(3),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__29/i__n_0\
    );
\EXP_IN_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(7),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => std_bool4_in
    );
\EXP_IN_inferred__4/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(2),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => \EXP_IN_inferred__4/i__n_0\
    );
\EXP_IN_inferred__6/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(1),
      I1 => \^word_aligned_data_r_reg[11]_0\(0),
      I2 => \^word_aligned_data_r_reg[11]_0\(2),
      I3 => \^word_aligned_data_r_reg[11]_0\(3),
      O => \EXP_IN_inferred__6/i__n_0\
    );
\EXP_IN_inferred__7/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__7/i__n_0\
    );
\EXP_IN_inferred__9/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(3),
      I1 => \^word_aligned_data_r_reg[11]_0\(1),
      I2 => \^word_aligned_data_r_reg[11]_0\(2),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => std_bool7_in
    );
\GOT_A_Buffer[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => got_a_d_r(1),
      I1 => p_2_in,
      O => \GOT_A_Buffer[0]_i_1__2_n_0\
    );
\GOT_A_Buffer[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => got_a_d_r(3),
      I2 => got_a_d_r(2),
      O => p_3_out(0)
    );
\GOT_A_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_a_d_r(0),
      Q => \^got_a_buffer_reg[0]_0\,
      R => \GOT_A_Buffer[0]_i_1__2_n_0\
    );
\GOT_A_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_3_out(0),
      Q => \^q\(0),
      R => '0'
    );
\GOT_V_Buffer_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => \first_v_received_r_i_2__2_n_0\,
      O => got_v_c
    );
GOT_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_v_c,
      Q => GOT_V_Buffer_reg_0,
      R => '0'
    );
\RX_CC_Buffer_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => rx_cc_r(1),
      I1 => p_15_in,
      I2 => rx_cc_r(3),
      I3 => \rx_scp_d_r_reg_n_0_[2]\,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => \RX_CC_Buffer_i_1__2_n_0\
    );
RX_CC_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CC_Buffer_i_1__2_n_0\,
      Q => D(0),
      R => '0'
    );
\RX_NEG_Buffer_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F080808"
    )
        port map (
      I0 => rx_sp_neg_d_r(1),
      I1 => rx_sp_neg_d_r(0),
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => rx_spa_neg_d_r(1),
      I4 => rx_spa_neg_d_r(0),
      O => RX_NEG_Buffer0
    );
RX_NEG_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_NEG_Buffer0,
      Q => RX_NEG_Buffer,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(10),
      Q => \^rx_pe_data_buffer_reg[10]_0\,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(8),
      Q => \^rx_pe_data_buffer_reg[8]_0\,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(9),
      Q => \^rx_pe_data_buffer_reg[9]_0\,
      R => '0'
    );
\RX_PE_DATA_V_Buffer_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F08"
    )
        port map (
      I0 => \RX_SP_Buffer_i_2__2_n_0\,
      I1 => \first_v_received_r_i_2__2_n_0\,
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => \RX_PE_DATA_V_Buffer_i_1__2_n_0\
    );
RX_PE_DATA_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_PE_DATA_V_Buffer_i_1__2_n_0\,
      Q => RX_PE_DATA_V_Buffer_reg_0(0),
      R => '0'
    );
\RX_SCP_Buffer_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[3]\,
      I1 => \rx_scp_d_r_reg_n_0_[2]\,
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => p_18_in,
      O => \RX_SCP_Buffer_i_1__2_n_0\
    );
RX_SCP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_SCP_Buffer_i_1__2_n_0\,
      Q => RX_SCP_Buffer_reg_0(0),
      R => \GOT_A_Buffer[0]_i_1__2_n_0\
    );
\RX_SP_Buffer_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => \RX_SP_Buffer_i_2__2_n_0\,
      O => rx_sp_c
    );
\RX_SP_Buffer_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_sp_r,
      I1 => rx_sp_d_r(3),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(0),
      I4 => rx_sp_d_r(1),
      O => \RX_SP_Buffer_i_2__2_n_0\
    );
RX_SP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_sp_c,
      Q => rx_sp_i,
      R => '0'
    );
RX_SUF_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_d_r_reg_n_0_[0]\,
      Q => \^rx_suf_buffer_reg_0\,
      R => \GOT_A_Buffer[0]_i_1__2_n_0\
    );
bad_as_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFE"
    )
        port map (
      I0 => GOT_A(0),
      I1 => bad_as_r_reg,
      I2 => bad_as_r_reg_0,
      I3 => \^got_a_buffer_reg[0]_0\,
      I4 => bad_as_r_i_2_n_0,
      O => bad_as_r0
    );
bad_as_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFE"
    )
        port map (
      I0 => \^q\(0),
      I1 => bad_as_r_reg_1(0),
      I2 => bad_as_r_reg_2(0),
      I3 => GOT_A(1),
      O => bad_as_r_i_2_n_0
    );
\first_v_received_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF01"
    )
        port map (
      I0 => \first_v_received_r_i_2__2_n_0\,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => p_2_in,
      I3 => \^first_v_received_r\,
      O => \first_v_received_r_i_1__2_n_0\
    );
\first_v_received_r_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_v_r,
      I1 => rx_v_d_r(3),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(0),
      I4 => rx_v_d_r(1),
      O => \first_v_received_r_i_2__2_n_0\
    );
first_v_received_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \first_v_received_r_i_1__2_n_0\,
      Q => \^first_v_received_r\,
      R => SR(0)
    );
\got_a_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__27/i__n_0\,
      Q => got_a_d_r(0),
      R => '0'
    );
\got_a_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__4/i__n_0\,
      Q => got_a_d_r(1),
      R => '0'
    );
\got_a_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__26/i__n_0\,
      Q => got_a_d_r(2),
      R => '0'
    );
\got_a_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__6/i__n_0\,
      Q => got_a_d_r(3),
      R => '0'
    );
left_aligned_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => left_aligned_r_reg_1,
      Q => left_aligned_r_reg_0,
      R => SR(0)
    );
\prev_beat_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool4_in,
      Q => prev_beat_sp_d_r(0),
      R => '0'
    );
\prev_beat_sp_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(3),
      O => \prev_beat_sp_r_i_1__2_n_0\
    );
prev_beat_sp_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \prev_beat_sp_r_i_1__2_n_0\,
      Q => prev_beat_sp_r,
      R => \GOT_A_Buffer[0]_i_1__2_n_0\
    );
\prev_beat_v_r_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(3),
      O => \prev_beat_v_r_i_1__2_n_0\
    );
prev_beat_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \prev_beat_v_r_i_1__2_n_0\,
      Q => prev_beat_v_r,
      R => \GOT_A_Buffer[0]_i_1__2_n_0\
    );
\rx_cc_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__29/i__n_0\,
      Q => rx_cc_r(1),
      R => '0'
    );
\rx_cc_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__28/i__n_0\,
      Q => rx_cc_r(3),
      R => '0'
    );
\rx_ecp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__19/i__n_0\,
      Q => p_15_in,
      R => '0'
    );
\rx_ecp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__18/i__n_0\,
      Q => p_1_in,
      R => '0'
    );
\rx_ecp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__17/i__n_0\,
      Q => \rx_ecp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_ecp_r_reg[3]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[2]\,
      I1 => p_15_in,
      I2 => \rx_ecp_d_r_reg_n_0_[3]\,
      I3 => p_1_in,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => RX_ECP_Buffer0
    );
\rx_pad_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__7/i__n_0\,
      Q => rx_pad_d_r(0),
      R => '0'
    );
\rx_pad_r_reg[3]_srl2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => rx_pad_d_r(0),
      I1 => got_a_d_r(3),
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => std_bool26_out
    );
\rx_pe_control_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(0),
      Q => p_2_in,
      R => '0'
    );
\rx_pe_control_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(1),
      Q => \rx_pe_control_r_reg_n_0_[1]\,
      R => '0'
    );
\rx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => rx_pe_data_r(10),
      R => '0'
    );
\rx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => rx_pe_data_r(8),
      R => '0'
    );
\rx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => rx_pe_data_r(9),
      R => '0'
    );
\rx_scp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__16/i__n_0\,
      Q => p_18_in,
      R => '0'
    );
\rx_scp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__15/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[2]\,
      R => '0'
    );
\rx_scp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__14/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_sp_d_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(6),
      O => p_4_out(3)
    );
\rx_sp_d_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => p_4_out(2)
    );
\rx_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(3),
      Q => rx_sp_d_r(0),
      R => '0'
    );
\rx_sp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(2),
      Q => rx_sp_d_r(1),
      R => '0'
    );
\rx_sp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool12_out,
      Q => rx_sp_d_r(2),
      R => '0'
    );
\rx_sp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool9_out,
      Q => rx_sp_d_r(3),
      R => '0'
    );
\rx_sp_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool10_in,
      Q => rx_sp_neg_d_r(0),
      R => '0'
    );
\rx_sp_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool7_in,
      Q => rx_sp_neg_d_r(1),
      R => '0'
    );
\rx_spa_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__25/i__n_0\,
      Q => rx_spa_neg_d_r(0),
      R => '0'
    );
\rx_spa_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__24/i__n_0\,
      Q => rx_spa_neg_d_r(1),
      R => '0'
    );
\rx_suf_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__20/i__n_0\,
      Q => \rx_suf_d_r_reg_n_0_[0]\,
      R => '0'
    );
\rx_v_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool,
      Q => rx_v_d_r(0),
      R => '0'
    );
\rx_v_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__1/i__n_0\,
      Q => rx_v_d_r(1),
      R => '0'
    );
\rx_v_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__0/i__n_0\,
      Q => rx_v_d_r(2),
      R => '0'
    );
\rx_v_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EXP_IN_n_0,
      Q => rx_v_d_r(3),
      R => '0'
    );
\stage_1_count_value_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^rx_pe_data_buffer_reg[9]_0\,
      I1 => \^rx_pe_data_buffer_reg[10]_0\,
      I2 => \^rx_pe_data_buffer_reg[8]_0\,
      I3 => \^rx_suf_buffer_reg_0\,
      O => \RX_PE_DATA_Buffer_reg[9]_2\
    );
\stage_1_count_value_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0BFBFBFBFB0B0B0B"
    )
        port map (
      I0 => \stage_1_count_value_r_reg[1]\,
      I1 => \stage_1_count_value_r_reg[1]_0\,
      I2 => \^rx_suf_buffer_reg_0\,
      I3 => \^rx_pe_data_buffer_reg[10]_0\,
      I4 => \^rx_pe_data_buffer_reg[9]_0\,
      I5 => \^rx_pe_data_buffer_reg[8]_0\,
      O => RX_SUF_Buffer_reg_1
    );
\stage_1_count_value_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00ABFFABFFAB00AB"
    )
        port map (
      I0 => \stage_1_count_value_r_reg[2]\,
      I1 => RX_PE_DATA(0),
      I2 => \stage_1_count_value_r_reg[2]_0\,
      I3 => \^rx_suf_buffer_reg_0\,
      I4 => \^rx_pe_data_buffer_reg[10]_0\,
      I5 => \^rx_pe_data_buffer_reg[9]_0\,
      O => \RX_PE_DATA_Buffer_reg[9]_1\
    );
\word_aligned_control_bits_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[0]_0\,
      Q => word_aligned_control_bits_r(0),
      R => '0'
    );
\word_aligned_control_bits_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[1]_0\,
      Q => word_aligned_control_bits_r(1),
      R => '0'
    );
\word_aligned_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(7),
      Q => \^word_aligned_data_r_reg[0]_0\(7),
      R => '0'
    );
\word_aligned_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(5),
      Q => p_0_in(1),
      R => '0'
    );
\word_aligned_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(4),
      Q => \^word_aligned_data_r_reg[11]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(3),
      Q => \^word_aligned_data_r_reg[11]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(2),
      Q => \^word_aligned_data_r_reg[11]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(1),
      Q => \^word_aligned_data_r_reg[11]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(0),
      Q => \^word_aligned_data_r_reg[11]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(6),
      Q => \^word_aligned_data_r_reg[0]_0\(6),
      R => '0'
    );
\word_aligned_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(5),
      Q => \^word_aligned_data_r_reg[0]_0\(5),
      R => '0'
    );
\word_aligned_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(4),
      Q => \^word_aligned_data_r_reg[0]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(3),
      Q => \^word_aligned_data_r_reg[0]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(2),
      Q => \^word_aligned_data_r_reg[0]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(1),
      Q => \^word_aligned_data_r_reg[0]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(0),
      Q => \^word_aligned_data_r_reg[0]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(7),
      Q => p_0_in(3),
      R => '0'
    );
\word_aligned_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(6),
      Q => p_0_in(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_SYM_DEC_14 is
  port (
    RX_NEG_Buffer : out STD_LOGIC;
    rx_sp_i : out STD_LOGIC;
    GOT_V_Buffer_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[9]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_0\ : out STD_LOGIC;
    RX_SCP_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    left_aligned_r_reg_0 : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[10]_1\ : out STD_LOGIC;
    RX_SUF_Buffer_reg_1 : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_2\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_3\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    \GOT_A_Buffer_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \GOT_A_Buffer_reg[0]_0\ : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_0\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    left_aligned_r_reg_1 : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    RX_SUF : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    \word_aligned_data_r_reg[8]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_SYM_DEC_14 : entity is "aurora_rx_4l_64b_SYM_DEC";
end aurora_rx_4l_64b_SYM_DEC_14;

architecture STRUCTURE of aurora_rx_4l_64b_SYM_DEC_14 is
  signal \EXP_IN_inferred__0/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__1/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__14/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__15/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__16/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__17/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__18/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__19/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__20/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__24/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__25/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__26/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__27/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__28/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__29/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__4/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__6/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__7/i__n_0\ : STD_LOGIC;
  signal EXP_IN_n_0 : STD_LOGIC;
  signal \GOT_A_Buffer[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \RX_CC_Buffer_i_1__0_n_0\ : STD_LOGIC;
  signal RX_NEG_Buffer0 : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[10]_0\ : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[8]_0\ : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[9]_0\ : STD_LOGIC;
  signal \RX_PE_DATA_V_Buffer_i_1__0_n_0\ : STD_LOGIC;
  signal \RX_SCP_Buffer_i_1__0_n_0\ : STD_LOGIC;
  signal \RX_SP_Buffer_i_2__0_n_0\ : STD_LOGIC;
  signal \^rx_suf_buffer_reg_0\ : STD_LOGIC;
  signal \^first_v_received_r\ : STD_LOGIC;
  signal \first_v_received_r_i_1__0_n_0\ : STD_LOGIC;
  signal \first_v_received_r_i_2__0_n_0\ : STD_LOGIC;
  signal got_a_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal got_v_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal p_15_in : STD_LOGIC;
  signal p_18_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_out : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal prev_beat_sp_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal prev_beat_sp_r : STD_LOGIC;
  signal \prev_beat_sp_r_i_1__0_n_0\ : STD_LOGIC;
  signal prev_beat_v_r : STD_LOGIC;
  signal \prev_beat_v_r_i_1__0_n_0\ : STD_LOGIC;
  signal rx_cc_r : STD_LOGIC_VECTOR ( 1 to 3 );
  signal \rx_ecp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_pad_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rx_pe_control_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rx_pe_data_r : STD_LOGIC_VECTOR ( 8 to 10 );
  signal \rx_scp_d_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rx_scp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_sp_c : STD_LOGIC;
  signal rx_sp_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal rx_sp_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal rx_spa_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \rx_suf_d_r_reg_n_0_[0]\ : STD_LOGIC;
  signal rx_v_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal std_bool : STD_LOGIC;
  signal std_bool10_in : STD_LOGIC;
  signal std_bool12_out : STD_LOGIC;
  signal std_bool4_in : STD_LOGIC;
  signal std_bool7_in : STD_LOGIC;
  signal std_bool9_out : STD_LOGIC;
  signal word_aligned_control_bits_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \^word_aligned_data_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EXP_IN : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__0/i_\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__1/i_\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__10/i_\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__11/i_\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__12/i_\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__14/i_\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__15/i_\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__16/i_\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__17/i_\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__18/i_\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__19/i_\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__2/i_\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__20/i_\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__24/i_\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__25/i_\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__28/i_\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__3/i_\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__4/i_\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__6/i_\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__7/i_\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__9/i_\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \rx_sp_d_r[0]_i_1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \rx_sp_d_r[1]_i_1\ : label is "soft_lutpair50";
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
  \RX_PE_DATA_Buffer_reg[10]_0\ <= \^rx_pe_data_buffer_reg[10]_0\;
  \RX_PE_DATA_Buffer_reg[8]_0\ <= \^rx_pe_data_buffer_reg[8]_0\;
  \RX_PE_DATA_Buffer_reg[9]_0\ <= \^rx_pe_data_buffer_reg[9]_0\;
  RX_SUF_Buffer_reg_0 <= \^rx_suf_buffer_reg_0\;
  first_v_received_r <= \^first_v_received_r\;
  \word_aligned_data_r_reg[0]_0\(7 downto 0) <= \^word_aligned_data_r_reg[0]_0\(7 downto 0);
EXP_IN: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(3),
      I3 => \^q\(0),
      O => EXP_IN_n_0
    );
\EXP_IN_inferred__0/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(4),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => p_0_in(1),
      O => \EXP_IN_inferred__0/i__n_0\
    );
\EXP_IN_inferred__1/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(1),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__1/i__n_0\
    );
\EXP_IN_inferred__10/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(3),
      O => std_bool9_out
    );
\EXP_IN_inferred__11/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(3),
      I2 => p_0_in(1),
      I3 => \^q\(4),
      O => std_bool10_in
    );
\EXP_IN_inferred__12/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^q\(4),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => p_0_in(2),
      O => std_bool12_out
    );
\EXP_IN_inferred__14/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \EXP_IN_inferred__14/i__n_0\
    );
\EXP_IN_inferred__15/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \^q\(4),
      I2 => p_0_in(2),
      I3 => p_0_in(3),
      O => \EXP_IN_inferred__15/i__n_0\
    );
\EXP_IN_inferred__16/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__16/i__n_0\
    );
\EXP_IN_inferred__17/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => \^q\(1),
      O => \EXP_IN_inferred__17/i__n_0\
    );
\EXP_IN_inferred__18/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__18/i__n_0\
    );
\EXP_IN_inferred__19/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(5),
      I1 => \^word_aligned_data_r_reg[0]_0\(4),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(7),
      O => \EXP_IN_inferred__19/i__n_0\
    );
\EXP_IN_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(5),
      O => std_bool
    );
\EXP_IN_inferred__20/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__20/i__n_0\
    );
\EXP_IN_inferred__24/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \EXP_IN_inferred__24/i__n_0\
    );
\EXP_IN_inferred__25/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => \^q\(4),
      O => \EXP_IN_inferred__25/i__n_0\
    );
\EXP_IN_inferred__26/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(3),
      I1 => p_0_in(2),
      I2 => p_0_in(1),
      I3 => \^q\(4),
      O => \EXP_IN_inferred__26/i__n_0\
    );
\EXP_IN_inferred__27/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__27/i__n_0\
    );
\EXP_IN_inferred__28/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \EXP_IN_inferred__28/i__n_0\
    );
\EXP_IN_inferred__29/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(3),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__29/i__n_0\
    );
\EXP_IN_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(7),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => std_bool4_in
    );
\EXP_IN_inferred__4/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(2),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => \EXP_IN_inferred__4/i__n_0\
    );
\EXP_IN_inferred__6/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \EXP_IN_inferred__6/i__n_0\
    );
\EXP_IN_inferred__7/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => \^q\(4),
      O => \EXP_IN_inferred__7/i__n_0\
    );
\EXP_IN_inferred__9/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(0),
      O => std_bool7_in
    );
\GOT_A_Buffer[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => got_a_d_r(1),
      I1 => p_2_in,
      O => \GOT_A_Buffer[0]_i_1__0_n_0\
    );
\GOT_A_Buffer[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => got_a_d_r(3),
      I2 => got_a_d_r(2),
      O => p_3_out(0)
    );
\GOT_A_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_a_d_r(0),
      Q => \GOT_A_Buffer_reg[0]_0\,
      R => \GOT_A_Buffer[0]_i_1__0_n_0\
    );
\GOT_A_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_3_out(0),
      Q => \GOT_A_Buffer_reg[1]_0\(0),
      R => '0'
    );
\GOT_V_Buffer_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => \first_v_received_r_i_2__0_n_0\,
      O => got_v_c
    );
GOT_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_v_c,
      Q => GOT_V_Buffer_reg_0,
      R => '0'
    );
\RX_CC_Buffer_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => rx_cc_r(1),
      I1 => p_15_in,
      I2 => rx_cc_r(3),
      I3 => \rx_scp_d_r_reg_n_0_[2]\,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => \RX_CC_Buffer_i_1__0_n_0\
    );
RX_CC_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CC_Buffer_i_1__0_n_0\,
      Q => D(0),
      R => '0'
    );
\RX_NEG_Buffer_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F080808"
    )
        port map (
      I0 => rx_sp_neg_d_r(1),
      I1 => rx_sp_neg_d_r(0),
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => rx_spa_neg_d_r(1),
      I4 => rx_spa_neg_d_r(0),
      O => RX_NEG_Buffer0
    );
RX_NEG_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_NEG_Buffer0,
      Q => RX_NEG_Buffer,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(10),
      Q => \^rx_pe_data_buffer_reg[10]_0\,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(8),
      Q => \^rx_pe_data_buffer_reg[8]_0\,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(9),
      Q => \^rx_pe_data_buffer_reg[9]_0\,
      R => '0'
    );
\RX_PE_DATA_V_Buffer_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F08"
    )
        port map (
      I0 => \RX_SP_Buffer_i_2__0_n_0\,
      I1 => \first_v_received_r_i_2__0_n_0\,
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => \RX_PE_DATA_V_Buffer_i_1__0_n_0\
    );
RX_PE_DATA_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_PE_DATA_V_Buffer_i_1__0_n_0\,
      Q => RX_PE_DATA_V_Buffer_reg_0(0),
      R => '0'
    );
\RX_SCP_Buffer_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[3]\,
      I1 => \rx_scp_d_r_reg_n_0_[2]\,
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => p_18_in,
      O => \RX_SCP_Buffer_i_1__0_n_0\
    );
RX_SCP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_SCP_Buffer_i_1__0_n_0\,
      Q => RX_SCP_Buffer_reg_0(0),
      R => \GOT_A_Buffer[0]_i_1__0_n_0\
    );
\RX_SP_Buffer_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => \RX_SP_Buffer_i_2__0_n_0\,
      O => rx_sp_c
    );
\RX_SP_Buffer_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_sp_r,
      I1 => rx_sp_d_r(3),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(0),
      I4 => rx_sp_d_r(1),
      O => \RX_SP_Buffer_i_2__0_n_0\
    );
RX_SP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_sp_c,
      Q => rx_sp_i,
      R => '0'
    );
RX_SUF_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_d_r_reg_n_0_[0]\,
      Q => \^rx_suf_buffer_reg_0\,
      R => \GOT_A_Buffer[0]_i_1__0_n_0\
    );
\first_v_received_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF01"
    )
        port map (
      I0 => \first_v_received_r_i_2__0_n_0\,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => p_2_in,
      I3 => \^first_v_received_r\,
      O => \first_v_received_r_i_1__0_n_0\
    );
\first_v_received_r_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_v_r,
      I1 => rx_v_d_r(3),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(0),
      I4 => rx_v_d_r(1),
      O => \first_v_received_r_i_2__0_n_0\
    );
first_v_received_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \first_v_received_r_i_1__0_n_0\,
      Q => \^first_v_received_r\,
      R => SR(0)
    );
\got_a_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__27/i__n_0\,
      Q => got_a_d_r(0),
      R => '0'
    );
\got_a_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__4/i__n_0\,
      Q => got_a_d_r(1),
      R => '0'
    );
\got_a_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__26/i__n_0\,
      Q => got_a_d_r(2),
      R => '0'
    );
\got_a_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__6/i__n_0\,
      Q => got_a_d_r(3),
      R => '0'
    );
left_aligned_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => left_aligned_r_reg_1,
      Q => left_aligned_r_reg_0,
      R => SR(0)
    );
\prev_beat_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool4_in,
      Q => prev_beat_sp_d_r(0),
      R => '0'
    );
\prev_beat_sp_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(3),
      O => \prev_beat_sp_r_i_1__0_n_0\
    );
prev_beat_sp_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \prev_beat_sp_r_i_1__0_n_0\,
      Q => prev_beat_sp_r,
      R => \GOT_A_Buffer[0]_i_1__0_n_0\
    );
\prev_beat_v_r_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(3),
      O => \prev_beat_v_r_i_1__0_n_0\
    );
prev_beat_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \prev_beat_v_r_i_1__0_n_0\,
      Q => prev_beat_v_r,
      R => \GOT_A_Buffer[0]_i_1__0_n_0\
    );
\rx_cc_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__29/i__n_0\,
      Q => rx_cc_r(1),
      R => '0'
    );
\rx_cc_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__28/i__n_0\,
      Q => rx_cc_r(3),
      R => '0'
    );
\rx_ecp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__19/i__n_0\,
      Q => p_15_in,
      R => '0'
    );
\rx_ecp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__18/i__n_0\,
      Q => p_1_in,
      R => '0'
    );
\rx_ecp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__17/i__n_0\,
      Q => \rx_ecp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_ecp_r_reg[1]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[2]\,
      I1 => p_15_in,
      I2 => \rx_ecp_d_r_reg_n_0_[3]\,
      I3 => p_1_in,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => RX_ECP_Buffer0
    );
\rx_pad_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__7/i__n_0\,
      Q => rx_pad_d_r(0),
      R => '0'
    );
\rx_pad_r_reg[1]_srl2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => rx_pad_d_r(0),
      I1 => got_a_d_r(3),
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => std_bool26_out
    );
\rx_pe_control_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(0),
      Q => p_2_in,
      R => '0'
    );
\rx_pe_control_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(1),
      Q => \rx_pe_control_r_reg_n_0_[1]\,
      R => '0'
    );
\rx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => rx_pe_data_r(10),
      R => '0'
    );
\rx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => rx_pe_data_r(8),
      R => '0'
    );
\rx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => rx_pe_data_r(9),
      R => '0'
    );
\rx_scp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__16/i__n_0\,
      Q => p_18_in,
      R => '0'
    );
\rx_scp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__15/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[2]\,
      R => '0'
    );
\rx_scp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__14/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_sp_d_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(6),
      O => p_4_out(3)
    );
\rx_sp_d_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => p_4_out(2)
    );
\rx_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(3),
      Q => rx_sp_d_r(0),
      R => '0'
    );
\rx_sp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(2),
      Q => rx_sp_d_r(1),
      R => '0'
    );
\rx_sp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool12_out,
      Q => rx_sp_d_r(2),
      R => '0'
    );
\rx_sp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool9_out,
      Q => rx_sp_d_r(3),
      R => '0'
    );
\rx_sp_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool10_in,
      Q => rx_sp_neg_d_r(0),
      R => '0'
    );
\rx_sp_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool7_in,
      Q => rx_sp_neg_d_r(1),
      R => '0'
    );
\rx_spa_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__25/i__n_0\,
      Q => rx_spa_neg_d_r(0),
      R => '0'
    );
\rx_spa_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__24/i__n_0\,
      Q => rx_spa_neg_d_r(1),
      R => '0'
    );
\rx_suf_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__20/i__n_0\,
      Q => \rx_suf_d_r_reg_n_0_[0]\,
      R => '0'
    );
\rx_v_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool,
      Q => rx_v_d_r(0),
      R => '0'
    );
\rx_v_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__1/i__n_0\,
      Q => rx_v_d_r(1),
      R => '0'
    );
\rx_v_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__0/i__n_0\,
      Q => rx_v_d_r(2),
      R => '0'
    );
\rx_v_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EXP_IN_n_0,
      Q => rx_v_d_r(3),
      R => '0'
    );
\stage_1_count_value_r[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1FFF"
    )
        port map (
      I0 => \^rx_pe_data_buffer_reg[10]_0\,
      I1 => \^rx_pe_data_buffer_reg[9]_0\,
      I2 => \^rx_pe_data_buffer_reg[8]_0\,
      I3 => \^rx_suf_buffer_reg_0\,
      I4 => \stage_1_count_value_r_reg[1]\,
      O => \RX_PE_DATA_Buffer_reg[10]_2\
    );
\stage_1_count_value_r[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000088208820"
    )
        port map (
      I0 => \^rx_suf_buffer_reg_0\,
      I1 => \^rx_pe_data_buffer_reg[9]_0\,
      I2 => \^rx_pe_data_buffer_reg[8]_0\,
      I3 => \^rx_pe_data_buffer_reg[10]_0\,
      I4 => \stage_1_count_value_r_reg[2]\,
      I5 => \stage_1_count_value_r_reg[1]\,
      O => RX_SUF_Buffer_reg_1
    );
\stage_1_count_value_r[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00540000"
    )
        port map (
      I0 => \^rx_pe_data_buffer_reg[10]_0\,
      I1 => \^rx_pe_data_buffer_reg[8]_0\,
      I2 => \^rx_pe_data_buffer_reg[9]_0\,
      I3 => \stage_1_count_value_r_reg[1]\,
      I4 => \^rx_suf_buffer_reg_0\,
      O => \RX_PE_DATA_Buffer_reg[10]_3\
    );
\stage_1_lane_mask_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEFFFE00"
    )
        port map (
      I0 => \^rx_pe_data_buffer_reg[10]_0\,
      I1 => \^rx_pe_data_buffer_reg[8]_0\,
      I2 => \^rx_pe_data_buffer_reg[9]_0\,
      I3 => \^rx_suf_buffer_reg_0\,
      I4 => \stage_1_count_value_r_reg[1]\,
      I5 => RX_SUF,
      O => \RX_PE_DATA_Buffer_reg[10]_1\
    );
\word_aligned_control_bits_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[0]_0\,
      Q => word_aligned_control_bits_r(0),
      R => '0'
    );
\word_aligned_control_bits_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[1]_0\,
      Q => word_aligned_control_bits_r(1),
      R => '0'
    );
\word_aligned_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(7),
      Q => \^word_aligned_data_r_reg[0]_0\(7),
      R => '0'
    );
\word_aligned_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(5),
      Q => p_0_in(1),
      R => '0'
    );
\word_aligned_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(4),
      Q => \^q\(4),
      R => '0'
    );
\word_aligned_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(3),
      Q => \^q\(3),
      R => '0'
    );
\word_aligned_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(2),
      Q => \^q\(2),
      R => '0'
    );
\word_aligned_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(1),
      Q => \^q\(1),
      R => '0'
    );
\word_aligned_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(0),
      Q => \^q\(0),
      R => '0'
    );
\word_aligned_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(6),
      Q => \^word_aligned_data_r_reg[0]_0\(6),
      R => '0'
    );
\word_aligned_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(5),
      Q => \^word_aligned_data_r_reg[0]_0\(5),
      R => '0'
    );
\word_aligned_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(4),
      Q => \^word_aligned_data_r_reg[0]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(3),
      Q => \^word_aligned_data_r_reg[0]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(2),
      Q => \^word_aligned_data_r_reg[0]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(1),
      Q => \^word_aligned_data_r_reg[0]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(0),
      Q => \^word_aligned_data_r_reg[0]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(7),
      Q => p_0_in(3),
      R => '0'
    );
\word_aligned_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(6),
      Q => p_0_in(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_SYM_DEC_19 is
  port (
    RX_NEG_Buffer : out STD_LOGIC;
    rx_sp_i : out STD_LOGIC;
    GOT_V : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[9]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_0\ : out STD_LOGIC;
    RX_PE_DATA : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SCP_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    left_aligned_r_reg_0 : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[10]_0\ : out STD_LOGIC;
    RX_SUF_Buffer_reg_1 : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_1\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_2\ : out STD_LOGIC;
    RX_SUF_Buffer_reg_2 : out STD_LOGIC;
    good_as_r0 : out STD_LOGIC;
    GOT_A : out STD_LOGIC_VECTOR ( 0 to 1 );
    \word_aligned_data_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_0\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    left_aligned_r_reg_1 : in STD_LOGIC;
    start_rx_i : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[2]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[3]\ : in STD_LOGIC;
    good_as_r_reg : in STD_LOGIC;
    good_as_r_reg_0 : in STD_LOGIC;
    good_as_r_reg_1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    good_as_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    good_as_r_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \word_aligned_data_r_reg[8]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_SYM_DEC_19 : entity is "aurora_rx_4l_64b_SYM_DEC";
end aurora_rx_4l_64b_SYM_DEC_19;

architecture STRUCTURE of aurora_rx_4l_64b_SYM_DEC_19 is
  signal \EXP_IN_inferred__0/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__1/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__14/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__15/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__16/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__17/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__18/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__19/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__20/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__24/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__25/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__26/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__27/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__28/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__29/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__4/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__6/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__7/i__n_0\ : STD_LOGIC;
  signal EXP_IN_n_0 : STD_LOGIC;
  signal \^got_a\ : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \GOT_A_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal RX_CC_Buffer_i_1_n_0 : STD_LOGIC;
  signal RX_NEG_Buffer0 : STD_LOGIC;
  signal \^rx_pe_data\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rx_pe_data_buffer_reg[8]_0\ : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[9]_0\ : STD_LOGIC;
  signal RX_PE_DATA_V_Buffer_i_1_n_0 : STD_LOGIC;
  signal RX_SCP_Buffer_i_1_n_0 : STD_LOGIC;
  signal RX_SP_Buffer_i_2_n_0 : STD_LOGIC;
  signal \^rx_suf_buffer_reg_0\ : STD_LOGIC;
  signal \^first_v_received_r\ : STD_LOGIC;
  signal first_v_received_r_i_1_n_0 : STD_LOGIC;
  signal first_v_received_r_i_2_n_0 : STD_LOGIC;
  signal got_a_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal got_v_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal p_15_in : STD_LOGIC;
  signal p_18_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_out : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal prev_beat_sp_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal prev_beat_sp_r : STD_LOGIC;
  signal prev_beat_sp_r_i_1_n_0 : STD_LOGIC;
  signal prev_beat_v_r : STD_LOGIC;
  signal prev_beat_v_r_i_1_n_0 : STD_LOGIC;
  signal rx_cc_r : STD_LOGIC_VECTOR ( 1 to 3 );
  signal \rx_ecp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/all_as_c_2__2\ : STD_LOGIC;
  signal rx_pad_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rx_pe_control_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rx_pe_data_r : STD_LOGIC_VECTOR ( 8 to 10 );
  signal \rx_scp_d_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rx_scp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_sp_c : STD_LOGIC;
  signal rx_sp_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal rx_sp_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal rx_spa_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \rx_suf_d_r_reg_n_0_[0]\ : STD_LOGIC;
  signal rx_v_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal std_bool : STD_LOGIC;
  signal std_bool10_in : STD_LOGIC;
  signal std_bool12_out : STD_LOGIC;
  signal std_bool4_in : STD_LOGIC;
  signal std_bool7_in : STD_LOGIC;
  signal std_bool9_out : STD_LOGIC;
  signal word_aligned_control_bits_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \^word_aligned_data_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^word_aligned_data_r_reg[11]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EXP_IN : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__0/i_\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__1/i_\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__10/i_\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__11/i_\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__12/i_\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__14/i_\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__15/i_\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__16/i_\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__17/i_\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__18/i_\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__19/i_\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__2/i_\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__20/i_\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__24/i_\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__25/i_\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__28/i_\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__3/i_\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__4/i_\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__6/i_\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__7/i_\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__9/i_\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \rx_sp_d_r[0]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \rx_sp_d_r[1]_i_1\ : label is "soft_lutpair35";
begin
  GOT_A(0 to 1) <= \^got_a\(0 to 1);
  RX_PE_DATA(0) <= \^rx_pe_data\(0);
  \RX_PE_DATA_Buffer_reg[8]_0\ <= \^rx_pe_data_buffer_reg[8]_0\;
  \RX_PE_DATA_Buffer_reg[9]_0\ <= \^rx_pe_data_buffer_reg[9]_0\;
  RX_SUF_Buffer_reg_0 <= \^rx_suf_buffer_reg_0\;
  first_v_received_r <= \^first_v_received_r\;
  \word_aligned_data_r_reg[0]_0\(7 downto 0) <= \^word_aligned_data_r_reg[0]_0\(7 downto 0);
  \word_aligned_data_r_reg[11]_0\(4 downto 0) <= \^word_aligned_data_r_reg[11]_0\(4 downto 0);
EXP_IN: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(1),
      I2 => \^word_aligned_data_r_reg[11]_0\(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => EXP_IN_n_0
    );
\EXP_IN_inferred__0/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(4),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => p_0_in(1),
      O => \EXP_IN_inferred__0/i__n_0\
    );
\EXP_IN_inferred__1/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(1),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__1/i__n_0\
    );
\EXP_IN_inferred__10/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(0),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(3),
      O => std_bool9_out
    );
\EXP_IN_inferred__11/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(3),
      I2 => p_0_in(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => std_bool10_in
    );
\EXP_IN_inferred__12/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(4),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => p_0_in(2),
      O => std_bool12_out
    );
\EXP_IN_inferred__14/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(3),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__14/i__n_0\
    );
\EXP_IN_inferred__15/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \^word_aligned_data_r_reg[11]_0\(4),
      I2 => p_0_in(2),
      I3 => p_0_in(3),
      O => \EXP_IN_inferred__15/i__n_0\
    );
\EXP_IN_inferred__16/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__16/i__n_0\
    );
\EXP_IN_inferred__17/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(0),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(1),
      O => \EXP_IN_inferred__17/i__n_0\
    );
\EXP_IN_inferred__18/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__18/i__n_0\
    );
\EXP_IN_inferred__19/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(5),
      I1 => \^word_aligned_data_r_reg[0]_0\(4),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(7),
      O => \EXP_IN_inferred__19/i__n_0\
    );
\EXP_IN_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(5),
      O => std_bool
    );
\EXP_IN_inferred__20/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__20/i__n_0\
    );
\EXP_IN_inferred__24/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(2),
      I1 => \^word_aligned_data_r_reg[11]_0\(3),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__24/i__n_0\
    );
\EXP_IN_inferred__25/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__25/i__n_0\
    );
\EXP_IN_inferred__26/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(3),
      I1 => p_0_in(2),
      I2 => p_0_in(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__26/i__n_0\
    );
\EXP_IN_inferred__27/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__27/i__n_0\
    );
\EXP_IN_inferred__28/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(3),
      I1 => \^word_aligned_data_r_reg[11]_0\(2),
      I2 => \^word_aligned_data_r_reg[11]_0\(1),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => \EXP_IN_inferred__28/i__n_0\
    );
\EXP_IN_inferred__29/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(3),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__29/i__n_0\
    );
\EXP_IN_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(7),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => std_bool4_in
    );
\EXP_IN_inferred__4/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(2),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => \EXP_IN_inferred__4/i__n_0\
    );
\EXP_IN_inferred__6/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(1),
      I1 => \^word_aligned_data_r_reg[11]_0\(0),
      I2 => \^word_aligned_data_r_reg[11]_0\(2),
      I3 => \^word_aligned_data_r_reg[11]_0\(3),
      O => \EXP_IN_inferred__6/i__n_0\
    );
\EXP_IN_inferred__7/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => \^word_aligned_data_r_reg[11]_0\(4),
      O => \EXP_IN_inferred__7/i__n_0\
    );
\EXP_IN_inferred__9/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[11]_0\(3),
      I1 => \^word_aligned_data_r_reg[11]_0\(1),
      I2 => \^word_aligned_data_r_reg[11]_0\(2),
      I3 => \^word_aligned_data_r_reg[11]_0\(0),
      O => std_bool7_in
    );
\GOT_A_Buffer[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => got_a_d_r(1),
      I1 => p_2_in,
      O => \GOT_A_Buffer[0]_i_1_n_0\
    );
\GOT_A_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => got_a_d_r(3),
      I2 => got_a_d_r(2),
      O => p_3_out(0)
    );
\GOT_A_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_a_d_r(0),
      Q => \^got_a\(0),
      R => \GOT_A_Buffer[0]_i_1_n_0\
    );
\GOT_A_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_3_out(0),
      Q => \^got_a\(1),
      R => '0'
    );
GOT_V_Buffer_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => first_v_received_r_i_2_n_0,
      O => got_v_c
    );
GOT_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_v_c,
      Q => GOT_V,
      R => '0'
    );
RX_CC_Buffer_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => rx_cc_r(1),
      I1 => p_15_in,
      I2 => rx_cc_r(3),
      I3 => \rx_scp_d_r_reg_n_0_[2]\,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => RX_CC_Buffer_i_1_n_0
    );
RX_CC_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_CC_Buffer_i_1_n_0,
      Q => D(0),
      R => '0'
    );
RX_NEG_Buffer_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F080808"
    )
        port map (
      I0 => rx_sp_neg_d_r(1),
      I1 => rx_sp_neg_d_r(0),
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => rx_spa_neg_d_r(1),
      I4 => rx_spa_neg_d_r(0),
      O => RX_NEG_Buffer0
    );
RX_NEG_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_NEG_Buffer0,
      Q => RX_NEG_Buffer,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(10),
      Q => \^rx_pe_data\(0),
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(8),
      Q => \^rx_pe_data_buffer_reg[8]_0\,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(9),
      Q => \^rx_pe_data_buffer_reg[9]_0\,
      R => '0'
    );
RX_PE_DATA_V_Buffer_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F08"
    )
        port map (
      I0 => RX_SP_Buffer_i_2_n_0,
      I1 => first_v_received_r_i_2_n_0,
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => RX_PE_DATA_V_Buffer_i_1_n_0
    );
RX_PE_DATA_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_PE_DATA_V_Buffer_i_1_n_0,
      Q => RX_PE_DATA_V_Buffer_reg_0(0),
      R => '0'
    );
RX_SCP_Buffer_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[3]\,
      I1 => \rx_scp_d_r_reg_n_0_[2]\,
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => p_18_in,
      O => RX_SCP_Buffer_i_1_n_0
    );
RX_SCP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_SCP_Buffer_i_1_n_0,
      Q => RX_SCP_Buffer_reg_0(0),
      R => \GOT_A_Buffer[0]_i_1_n_0\
    );
RX_SP_Buffer_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => RX_SP_Buffer_i_2_n_0,
      O => rx_sp_c
    );
RX_SP_Buffer_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_sp_r,
      I1 => rx_sp_d_r(3),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(0),
      I4 => rx_sp_d_r(1),
      O => RX_SP_Buffer_i_2_n_0
    );
RX_SP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_sp_c,
      Q => rx_sp_i,
      R => '0'
    );
RX_SUF_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_d_r_reg_n_0_[0]\,
      Q => \^rx_suf_buffer_reg_0\,
      R => \GOT_A_Buffer[0]_i_1_n_0\
    );
first_v_received_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF01"
    )
        port map (
      I0 => first_v_received_r_i_2_n_0,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => p_2_in,
      I3 => \^first_v_received_r\,
      O => first_v_received_r_i_1_n_0
    );
first_v_received_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_v_r,
      I1 => rx_v_d_r(3),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(0),
      I4 => rx_v_d_r(1),
      O => first_v_received_r_i_2_n_0
    );
first_v_received_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => first_v_received_r_i_1_n_0,
      Q => \^first_v_received_r\,
      R => SR(0)
    );
good_as_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF8000"
    )
        port map (
      I0 => good_as_r_reg,
      I1 => good_as_r_reg_0,
      I2 => good_as_r_reg_1,
      I3 => \^got_a\(0),
      I4 => \rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/all_as_c_2__2\,
      O => good_as_r0
    );
good_as_r_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^got_a\(1),
      I1 => Q(0),
      I2 => good_as_r_reg_2(0),
      I3 => good_as_r_reg_3(0),
      O => \rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/all_as_c_2__2\
    );
\got_a_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__27/i__n_0\,
      Q => got_a_d_r(0),
      R => '0'
    );
\got_a_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__4/i__n_0\,
      Q => got_a_d_r(1),
      R => '0'
    );
\got_a_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__26/i__n_0\,
      Q => got_a_d_r(2),
      R => '0'
    );
\got_a_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__6/i__n_0\,
      Q => got_a_d_r(3),
      R => '0'
    );
left_aligned_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => left_aligned_r_reg_1,
      Q => left_aligned_r_reg_0,
      R => SR(0)
    );
\prev_beat_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool4_in,
      Q => prev_beat_sp_d_r(0),
      R => '0'
    );
prev_beat_sp_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(3),
      O => prev_beat_sp_r_i_1_n_0
    );
prev_beat_sp_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => prev_beat_sp_r_i_1_n_0,
      Q => prev_beat_sp_r,
      R => \GOT_A_Buffer[0]_i_1_n_0\
    );
prev_beat_v_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(3),
      O => prev_beat_v_r_i_1_n_0
    );
prev_beat_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => prev_beat_v_r_i_1_n_0,
      Q => prev_beat_v_r,
      R => \GOT_A_Buffer[0]_i_1_n_0\
    );
\rx_cc_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__29/i__n_0\,
      Q => rx_cc_r(1),
      R => '0'
    );
\rx_cc_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__28/i__n_0\,
      Q => rx_cc_r(3),
      R => '0'
    );
\rx_ecp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__19/i__n_0\,
      Q => p_15_in,
      R => '0'
    );
\rx_ecp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__18/i__n_0\,
      Q => p_1_in,
      R => '0'
    );
\rx_ecp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__17/i__n_0\,
      Q => \rx_ecp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_ecp_r_reg[0]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[2]\,
      I1 => p_15_in,
      I2 => \rx_ecp_d_r_reg_n_0_[3]\,
      I3 => p_1_in,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => RX_ECP_Buffer0
    );
\rx_pad_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__7/i__n_0\,
      Q => rx_pad_d_r(0),
      R => '0'
    );
\rx_pad_r_reg[0]_srl2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => rx_pad_d_r(0),
      I1 => got_a_d_r(3),
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => std_bool26_out
    );
\rx_pe_control_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(0),
      Q => p_2_in,
      R => '0'
    );
\rx_pe_control_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(1),
      Q => \rx_pe_control_r_reg_n_0_[1]\,
      R => '0'
    );
\rx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => rx_pe_data_r(10),
      R => '0'
    );
\rx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => rx_pe_data_r(8),
      R => '0'
    );
\rx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => rx_pe_data_r(9),
      R => '0'
    );
\rx_scp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__16/i__n_0\,
      Q => p_18_in,
      R => '0'
    );
\rx_scp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__15/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[2]\,
      R => '0'
    );
\rx_scp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__14/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_sp_d_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(6),
      O => p_4_out(3)
    );
\rx_sp_d_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => p_4_out(2)
    );
\rx_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(3),
      Q => rx_sp_d_r(0),
      R => '0'
    );
\rx_sp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(2),
      Q => rx_sp_d_r(1),
      R => '0'
    );
\rx_sp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool12_out,
      Q => rx_sp_d_r(2),
      R => '0'
    );
\rx_sp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool9_out,
      Q => rx_sp_d_r(3),
      R => '0'
    );
\rx_sp_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool10_in,
      Q => rx_sp_neg_d_r(0),
      R => '0'
    );
\rx_sp_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool7_in,
      Q => rx_sp_neg_d_r(1),
      R => '0'
    );
\rx_spa_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__25/i__n_0\,
      Q => rx_spa_neg_d_r(0),
      R => '0'
    );
\rx_spa_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__24/i__n_0\,
      Q => rx_spa_neg_d_r(1),
      R => '0'
    );
\rx_suf_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__20/i__n_0\,
      Q => \rx_suf_d_r_reg_n_0_[0]\,
      R => '0'
    );
\rx_v_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool,
      Q => rx_v_d_r(0),
      R => '0'
    );
\rx_v_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__1/i__n_0\,
      Q => rx_v_d_r(1),
      R => '0'
    );
\rx_v_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__0/i__n_0\,
      Q => rx_v_d_r(2),
      R => '0'
    );
\rx_v_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EXP_IN_n_0,
      Q => rx_v_d_r(3),
      R => '0'
    );
\stage_1_count_value_r[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000008000800"
    )
        port map (
      I0 => \^rx_suf_buffer_reg_0\,
      I1 => \^rx_pe_data_buffer_reg[8]_0\,
      I2 => \stage_1_lane_mask_r_reg[2]\,
      I3 => \^rx_pe_data_buffer_reg[9]_0\,
      I4 => \stage_1_count_value_r_reg[1]\,
      I5 => \stage_1_count_value_r_reg[2]\,
      O => RX_SUF_Buffer_reg_1
    );
\stage_1_count_value_r[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \^rx_suf_buffer_reg_0\,
      I1 => \^rx_pe_data_buffer_reg[8]_0\,
      I2 => \stage_1_count_value_r_reg[2]\,
      I3 => \stage_1_lane_mask_r_reg[2]\,
      O => RX_SUF_Buffer_reg_2
    );
\stage_1_count_value_r[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000E000"
    )
        port map (
      I0 => \^rx_pe_data_buffer_reg[8]_0\,
      I1 => \^rx_pe_data_buffer_reg[9]_0\,
      I2 => \^rx_suf_buffer_reg_0\,
      I3 => \^rx_pe_data\(0),
      I4 => \stage_1_lane_mask_r_reg[2]\,
      I5 => \stage_1_count_value_r_reg[2]\,
      O => \RX_PE_DATA_Buffer_reg[8]_2\
    );
\stage_1_lane_mask_r[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FF00FE000000"
    )
        port map (
      I0 => \^rx_pe_data\(0),
      I1 => \^rx_pe_data_buffer_reg[8]_0\,
      I2 => \^rx_pe_data_buffer_reg[9]_0\,
      I3 => start_rx_i,
      I4 => \^rx_suf_buffer_reg_0\,
      I5 => \stage_1_lane_mask_r_reg[2]\,
      O => \RX_PE_DATA_Buffer_reg[10]_0\
    );
\stage_1_lane_mask_r[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFE0"
    )
        port map (
      I0 => \^rx_pe_data_buffer_reg[8]_0\,
      I1 => \^rx_pe_data_buffer_reg[9]_0\,
      I2 => \^rx_suf_buffer_reg_0\,
      I3 => \stage_1_lane_mask_r_reg[3]\,
      O => \RX_PE_DATA_Buffer_reg[8]_1\
    );
\word_aligned_control_bits_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[0]_0\,
      Q => word_aligned_control_bits_r(0),
      R => '0'
    );
\word_aligned_control_bits_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[1]_0\,
      Q => word_aligned_control_bits_r(1),
      R => '0'
    );
\word_aligned_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(7),
      Q => \^word_aligned_data_r_reg[0]_0\(7),
      R => '0'
    );
\word_aligned_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(5),
      Q => p_0_in(1),
      R => '0'
    );
\word_aligned_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(4),
      Q => \^word_aligned_data_r_reg[11]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(3),
      Q => \^word_aligned_data_r_reg[11]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(2),
      Q => \^word_aligned_data_r_reg[11]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(1),
      Q => \^word_aligned_data_r_reg[11]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(0),
      Q => \^word_aligned_data_r_reg[11]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(6),
      Q => \^word_aligned_data_r_reg[0]_0\(6),
      R => '0'
    );
\word_aligned_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(5),
      Q => \^word_aligned_data_r_reg[0]_0\(5),
      R => '0'
    );
\word_aligned_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(4),
      Q => \^word_aligned_data_r_reg[0]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(3),
      Q => \^word_aligned_data_r_reg[0]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(2),
      Q => \^word_aligned_data_r_reg[0]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(1),
      Q => \^word_aligned_data_r_reg[0]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(0),
      Q => \^word_aligned_data_r_reg[0]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(7),
      Q => p_0_in(3),
      R => '0'
    );
\word_aligned_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(6),
      Q => p_0_in(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_SYM_DEC_9 is
  port (
    RX_NEG_Buffer : out STD_LOGIC;
    rx_sp_i : out STD_LOGIC;
    GOT_V_Buffer_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[8]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]_0\ : out STD_LOGIC;
    RX_SCP_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    left_aligned_r_reg_0 : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    neqOp : out STD_LOGIC;
    RX_SUF_Buffer_reg_1 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    \GOT_A_Buffer_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \GOT_A_Buffer_reg[0]_0\ : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_0\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]_0\ : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    left_aligned_r_reg_1 : in STD_LOGIC;
    load_ufc_control_code_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \stage_1_count_value_r_reg[3]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]_1\ : in STD_LOGIC;
    \word_aligned_data_r_reg[8]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_SYM_DEC_9 : entity is "aurora_rx_4l_64b_SYM_DEC";
end aurora_rx_4l_64b_SYM_DEC_9;

architecture STRUCTURE of aurora_rx_4l_64b_SYM_DEC_9 is
  signal \EXP_IN_inferred__0/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__1/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__14/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__15/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__16/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__17/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__18/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__19/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__20/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__24/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__25/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__26/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__27/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__28/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__29/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__4/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__6/i__n_0\ : STD_LOGIC;
  signal \EXP_IN_inferred__7/i__n_0\ : STD_LOGIC;
  signal EXP_IN_n_0 : STD_LOGIC;
  signal \GOT_A_Buffer[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \RX_CC_Buffer_i_1__1_n_0\ : STD_LOGIC;
  signal RX_NEG_Buffer0 : STD_LOGIC;
  signal \^rx_pe_data_buffer_reg[10]_0\ : STD_LOGIC;
  signal \RX_PE_DATA_V_Buffer_i_1__1_n_0\ : STD_LOGIC;
  signal \RX_SCP_Buffer_i_1__1_n_0\ : STD_LOGIC;
  signal \RX_SP_Buffer_i_2__1_n_0\ : STD_LOGIC;
  signal \^rx_suf_buffer_reg_0\ : STD_LOGIC;
  signal \^first_v_received_r\ : STD_LOGIC;
  signal \first_v_received_r_i_1__1_n_0\ : STD_LOGIC;
  signal \first_v_received_r_i_2__1_n_0\ : STD_LOGIC;
  signal got_a_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal got_v_c : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal p_15_in : STD_LOGIC;
  signal p_18_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_3_out : STD_LOGIC_VECTOR ( 0 to 0 );
  signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal prev_beat_sp_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal prev_beat_sp_r : STD_LOGIC;
  signal \prev_beat_sp_r_i_1__1_n_0\ : STD_LOGIC;
  signal prev_beat_v_r : STD_LOGIC;
  signal \prev_beat_v_r_i_1__1_n_0\ : STD_LOGIC;
  signal rx_cc_r : STD_LOGIC_VECTOR ( 1 to 3 );
  signal \rx_ecp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_pad_d_r : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \rx_pe_control_r_reg_n_0_[1]\ : STD_LOGIC;
  signal rx_pe_data_r : STD_LOGIC_VECTOR ( 8 to 10 );
  signal \rx_scp_d_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rx_scp_d_r_reg_n_0_[3]\ : STD_LOGIC;
  signal rx_sp_c : STD_LOGIC;
  signal rx_sp_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal rx_sp_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal rx_spa_neg_d_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \rx_suf_d_r_reg_n_0_[0]\ : STD_LOGIC;
  signal rx_v_d_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal std_bool : STD_LOGIC;
  signal std_bool10_in : STD_LOGIC;
  signal std_bool12_out : STD_LOGIC;
  signal std_bool4_in : STD_LOGIC;
  signal std_bool7_in : STD_LOGIC;
  signal std_bool9_out : STD_LOGIC;
  signal word_aligned_control_bits_r : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \^word_aligned_data_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EXP_IN : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__0/i_\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__1/i_\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__10/i_\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__11/i_\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__12/i_\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__14/i_\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__15/i_\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__16/i_\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__17/i_\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__18/i_\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__19/i_\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__2/i_\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__20/i_\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__24/i_\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__25/i_\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__28/i_\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__3/i_\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__4/i_\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__6/i_\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__7/i_\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \EXP_IN_inferred__9/i_\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \rx_sp_d_r[0]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \rx_sp_d_r[1]_i_1\ : label is "soft_lutpair65";
begin
  Q(4 downto 0) <= \^q\(4 downto 0);
  \RX_PE_DATA_Buffer_reg[10]_0\ <= \^rx_pe_data_buffer_reg[10]_0\;
  RX_SUF_Buffer_reg_0 <= \^rx_suf_buffer_reg_0\;
  first_v_received_r <= \^first_v_received_r\;
  \word_aligned_data_r_reg[0]_0\(7 downto 0) <= \^word_aligned_data_r_reg[0]_0\(7 downto 0);
EXP_IN: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(3),
      I3 => \^q\(0),
      O => EXP_IN_n_0
    );
\EXP_IN_inferred__0/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(4),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => p_0_in(1),
      O => \EXP_IN_inferred__0/i__n_0\
    );
\EXP_IN_inferred__1/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(1),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__1/i__n_0\
    );
\EXP_IN_inferred__10/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(3),
      O => std_bool9_out
    );
\EXP_IN_inferred__11/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(3),
      I2 => p_0_in(1),
      I3 => \^q\(4),
      O => std_bool10_in
    );
\EXP_IN_inferred__12/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^q\(4),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => p_0_in(2),
      O => std_bool12_out
    );
\EXP_IN_inferred__14/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \EXP_IN_inferred__14/i__n_0\
    );
\EXP_IN_inferred__15/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => \^q\(4),
      I2 => p_0_in(2),
      I3 => p_0_in(3),
      O => \EXP_IN_inferred__15/i__n_0\
    );
\EXP_IN_inferred__16/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__16/i__n_0\
    );
\EXP_IN_inferred__17/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(3),
      I3 => \^q\(1),
      O => \EXP_IN_inferred__17/i__n_0\
    );
\EXP_IN_inferred__18/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(3),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__18/i__n_0\
    );
\EXP_IN_inferred__19/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(5),
      I1 => \^word_aligned_data_r_reg[0]_0\(4),
      I2 => \^word_aligned_data_r_reg[0]_0\(6),
      I3 => \^word_aligned_data_r_reg[0]_0\(7),
      O => \EXP_IN_inferred__19/i__n_0\
    );
\EXP_IN_inferred__2/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(5),
      O => std_bool
    );
\EXP_IN_inferred__20/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__20/i__n_0\
    );
\EXP_IN_inferred__24/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \EXP_IN_inferred__24/i__n_0\
    );
\EXP_IN_inferred__25/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(1),
      I1 => p_0_in(2),
      I2 => p_0_in(3),
      I3 => \^q\(4),
      O => \EXP_IN_inferred__25/i__n_0\
    );
\EXP_IN_inferred__26/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => p_0_in(3),
      I1 => p_0_in(2),
      I2 => p_0_in(1),
      I3 => \^q\(4),
      O => \EXP_IN_inferred__26/i__n_0\
    );
\EXP_IN_inferred__27/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(7),
      I1 => \^word_aligned_data_r_reg[0]_0\(6),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => \EXP_IN_inferred__27/i__n_0\
    );
\EXP_IN_inferred__28/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \EXP_IN_inferred__28/i__n_0\
    );
\EXP_IN_inferred__29/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(3),
      I1 => \^word_aligned_data_r_reg[0]_0\(2),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(0),
      O => \EXP_IN_inferred__29/i__n_0\
    );
\EXP_IN_inferred__3/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(6),
      I1 => \^word_aligned_data_r_reg[0]_0\(7),
      I2 => \^word_aligned_data_r_reg[0]_0\(5),
      I3 => \^word_aligned_data_r_reg[0]_0\(4),
      O => std_bool4_in
    );
\EXP_IN_inferred__4/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(1),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(2),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => \EXP_IN_inferred__4/i__n_0\
    );
\EXP_IN_inferred__6/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(3),
      O => \EXP_IN_inferred__6/i__n_0\
    );
\EXP_IN_inferred__7/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => p_0_in(2),
      I1 => p_0_in(1),
      I2 => p_0_in(3),
      I3 => \^q\(4),
      O => \EXP_IN_inferred__7/i__n_0\
    );
\EXP_IN_inferred__9/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(0),
      O => std_bool7_in
    );
\GOT_A_Buffer[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => got_a_d_r(1),
      I1 => p_2_in,
      O => \GOT_A_Buffer[0]_i_1__1_n_0\
    );
\GOT_A_Buffer[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => got_a_d_r(3),
      I2 => got_a_d_r(2),
      O => p_3_out(0)
    );
\GOT_A_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_a_d_r(0),
      Q => \GOT_A_Buffer_reg[0]_0\,
      R => \GOT_A_Buffer[0]_i_1__1_n_0\
    );
\GOT_A_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_3_out(0),
      Q => \GOT_A_Buffer_reg[1]_0\(0),
      R => '0'
    );
\GOT_V_Buffer_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => \first_v_received_r_i_2__1_n_0\,
      O => got_v_c
    );
GOT_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => got_v_c,
      Q => GOT_V_Buffer_reg_0,
      R => '0'
    );
\RX_CC_Buffer_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => rx_cc_r(1),
      I1 => p_15_in,
      I2 => rx_cc_r(3),
      I3 => \rx_scp_d_r_reg_n_0_[2]\,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => \RX_CC_Buffer_i_1__1_n_0\
    );
RX_CC_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_CC_Buffer_i_1__1_n_0\,
      Q => D(0),
      R => '0'
    );
\RX_NEG_Buffer_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F080808"
    )
        port map (
      I0 => rx_sp_neg_d_r(1),
      I1 => rx_sp_neg_d_r(0),
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => rx_spa_neg_d_r(1),
      I4 => rx_spa_neg_d_r(0),
      O => RX_NEG_Buffer0
    );
RX_NEG_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_NEG_Buffer0,
      Q => RX_NEG_Buffer,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(10),
      Q => \^rx_pe_data_buffer_reg[10]_0\,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(8),
      Q => \RX_PE_DATA_Buffer_reg[8]_0\,
      R => '0'
    );
\RX_PE_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_pe_data_r(9),
      Q => \RX_PE_DATA_Buffer_reg[9]_0\,
      R => '0'
    );
\RX_PE_DATA_V_Buffer_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F08"
    )
        port map (
      I0 => \RX_SP_Buffer_i_2__1_n_0\,
      I1 => \first_v_received_r_i_2__1_n_0\,
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => \RX_PE_DATA_V_Buffer_i_1__1_n_0\
    );
RX_PE_DATA_V_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_PE_DATA_V_Buffer_i_1__1_n_0\,
      Q => RX_PE_DATA_V_Buffer_reg_0(0),
      R => '0'
    );
\RX_SCP_Buffer_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[3]\,
      I1 => \rx_scp_d_r_reg_n_0_[2]\,
      I2 => \rx_pe_control_r_reg_n_0_[1]\,
      I3 => p_18_in,
      O => \RX_SCP_Buffer_i_1__1_n_0\
    );
RX_SCP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \RX_SCP_Buffer_i_1__1_n_0\,
      Q => RX_SCP_Buffer_reg_0(0),
      R => \GOT_A_Buffer[0]_i_1__1_n_0\
    );
\RX_SP_Buffer_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => p_2_in,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => \RX_SP_Buffer_i_2__1_n_0\,
      O => rx_sp_c
    );
\RX_SP_Buffer_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_sp_r,
      I1 => rx_sp_d_r(3),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(0),
      I4 => rx_sp_d_r(1),
      O => \RX_SP_Buffer_i_2__1_n_0\
    );
RX_SP_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_sp_c,
      Q => rx_sp_i,
      R => '0'
    );
RX_SUF_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_d_r_reg_n_0_[0]\,
      Q => \^rx_suf_buffer_reg_0\,
      R => \GOT_A_Buffer[0]_i_1__1_n_0\
    );
\first_v_received_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF01"
    )
        port map (
      I0 => \first_v_received_r_i_2__1_n_0\,
      I1 => \rx_pe_control_r_reg_n_0_[1]\,
      I2 => p_2_in,
      I3 => \^first_v_received_r\,
      O => \first_v_received_r_i_1__1_n_0\
    );
\first_v_received_r_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => prev_beat_v_r,
      I1 => rx_v_d_r(3),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(0),
      I4 => rx_v_d_r(1),
      O => \first_v_received_r_i_2__1_n_0\
    );
first_v_received_r_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \first_v_received_r_i_1__1_n_0\,
      Q => \^first_v_received_r\,
      R => SR(0)
    );
\got_a_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__27/i__n_0\,
      Q => got_a_d_r(0),
      R => '0'
    );
\got_a_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__4/i__n_0\,
      Q => got_a_d_r(1),
      R => '0'
    );
\got_a_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__26/i__n_0\,
      Q => got_a_d_r(2),
      R => '0'
    );
\got_a_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__6/i__n_0\,
      Q => got_a_d_r(3),
      R => '0'
    );
left_aligned_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => left_aligned_r_reg_1,
      Q => left_aligned_r_reg_0,
      R => SR(0)
    );
load_ufc_control_code_r_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^rx_suf_buffer_reg_0\,
      I1 => load_ufc_control_code_r_reg(1),
      I2 => load_ufc_control_code_r_reg(2),
      I3 => load_ufc_control_code_r_reg(0),
      O => neqOp
    );
\prev_beat_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool4_in,
      Q => prev_beat_sp_d_r(0),
      R => '0'
    );
\prev_beat_sp_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_sp_d_r(2),
      I3 => rx_sp_d_r(3),
      O => \prev_beat_sp_r_i_1__1_n_0\
    );
prev_beat_sp_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \prev_beat_sp_r_i_1__1_n_0\,
      Q => prev_beat_sp_r,
      R => \GOT_A_Buffer[0]_i_1__1_n_0\
    );
\prev_beat_v_r_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \rx_pe_control_r_reg_n_0_[1]\,
      I1 => prev_beat_sp_d_r(0),
      I2 => rx_v_d_r(2),
      I3 => rx_v_d_r(3),
      O => \prev_beat_v_r_i_1__1_n_0\
    );
prev_beat_v_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \prev_beat_v_r_i_1__1_n_0\,
      Q => prev_beat_v_r,
      R => \GOT_A_Buffer[0]_i_1__1_n_0\
    );
\rx_cc_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__29/i__n_0\,
      Q => rx_cc_r(1),
      R => '0'
    );
\rx_cc_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__28/i__n_0\,
      Q => rx_cc_r(3),
      R => '0'
    );
\rx_ecp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__19/i__n_0\,
      Q => p_15_in,
      R => '0'
    );
\rx_ecp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__18/i__n_0\,
      Q => p_1_in,
      R => '0'
    );
\rx_ecp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__17/i__n_0\,
      Q => \rx_ecp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_ecp_r_reg[2]_srl2_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \rx_scp_d_r_reg_n_0_[2]\,
      I1 => p_15_in,
      I2 => \rx_ecp_d_r_reg_n_0_[3]\,
      I3 => p_1_in,
      I4 => p_2_in,
      I5 => \rx_pe_control_r_reg_n_0_[1]\,
      O => RX_ECP_Buffer0
    );
\rx_pad_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__7/i__n_0\,
      Q => rx_pad_d_r(0),
      R => '0'
    );
\rx_pad_r_reg[2]_srl2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => rx_pad_d_r(0),
      I1 => got_a_d_r(3),
      I2 => p_2_in,
      I3 => \rx_pe_control_r_reg_n_0_[1]\,
      O => std_bool26_out
    );
\rx_pe_control_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(0),
      Q => p_2_in,
      R => '0'
    );
\rx_pe_control_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => word_aligned_control_bits_r(1),
      Q => \rx_pe_control_r_reg_n_0_[1]\,
      R => '0'
    );
\rx_pe_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(1),
      Q => rx_pe_data_r(10),
      R => '0'
    );
\rx_pe_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(3),
      Q => rx_pe_data_r(8),
      R => '0'
    );
\rx_pe_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_0_in(2),
      Q => rx_pe_data_r(9),
      R => '0'
    );
\rx_scp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__16/i__n_0\,
      Q => p_18_in,
      R => '0'
    );
\rx_scp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__15/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[2]\,
      R => '0'
    );
\rx_scp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__14/i__n_0\,
      Q => \rx_scp_d_r_reg_n_0_[3]\,
      R => '0'
    );
\rx_sp_d_r[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0180"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(4),
      I1 => \^word_aligned_data_r_reg[0]_0\(5),
      I2 => \^word_aligned_data_r_reg[0]_0\(7),
      I3 => \^word_aligned_data_r_reg[0]_0\(6),
      O => p_4_out(3)
    );
\rx_sp_d_r[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1008"
    )
        port map (
      I0 => \^word_aligned_data_r_reg[0]_0\(2),
      I1 => \^word_aligned_data_r_reg[0]_0\(0),
      I2 => \^word_aligned_data_r_reg[0]_0\(1),
      I3 => \^word_aligned_data_r_reg[0]_0\(3),
      O => p_4_out(2)
    );
\rx_sp_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(3),
      Q => rx_sp_d_r(0),
      R => '0'
    );
\rx_sp_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => p_4_out(2),
      Q => rx_sp_d_r(1),
      R => '0'
    );
\rx_sp_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool12_out,
      Q => rx_sp_d_r(2),
      R => '0'
    );
\rx_sp_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool9_out,
      Q => rx_sp_d_r(3),
      R => '0'
    );
\rx_sp_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool10_in,
      Q => rx_sp_neg_d_r(0),
      R => '0'
    );
\rx_sp_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool7_in,
      Q => rx_sp_neg_d_r(1),
      R => '0'
    );
\rx_spa_neg_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__25/i__n_0\,
      Q => rx_spa_neg_d_r(0),
      R => '0'
    );
\rx_spa_neg_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__24/i__n_0\,
      Q => rx_spa_neg_d_r(1),
      R => '0'
    );
\rx_suf_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__20/i__n_0\,
      Q => \rx_suf_d_r_reg_n_0_[0]\,
      R => '0'
    );
\rx_v_d_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool,
      Q => rx_v_d_r(0),
      R => '0'
    );
\rx_v_d_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__1/i__n_0\,
      Q => rx_v_d_r(1),
      R => '0'
    );
\rx_v_d_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \EXP_IN_inferred__0/i__n_0\,
      Q => rx_v_d_r(2),
      R => '0'
    );
\rx_v_d_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EXP_IN_n_0,
      Q => rx_v_d_r(3),
      R => '0'
    );
\stage_1_count_value_r[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFF8FFFFFFF8"
    )
        port map (
      I0 => \^rx_suf_buffer_reg_0\,
      I1 => \^rx_pe_data_buffer_reg[10]_0\,
      I2 => \stage_1_count_value_r_reg[3]\,
      I3 => \stage_1_count_value_r_reg[3]_0\,
      I4 => load_ufc_control_code_r_reg(0),
      I5 => \stage_1_count_value_r_reg[3]_1\,
      O => RX_SUF_Buffer_reg_1
    );
\word_aligned_control_bits_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[0]_0\,
      Q => word_aligned_control_bits_r(0),
      R => '0'
    );
\word_aligned_control_bits_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_control_bits_r_reg[1]_0\,
      Q => word_aligned_control_bits_r(1),
      R => '0'
    );
\word_aligned_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(7),
      Q => \^word_aligned_data_r_reg[0]_0\(7),
      R => '0'
    );
\word_aligned_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(5),
      Q => p_0_in(1),
      R => '0'
    );
\word_aligned_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(4),
      Q => \^q\(4),
      R => '0'
    );
\word_aligned_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(3),
      Q => \^q\(3),
      R => '0'
    );
\word_aligned_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(2),
      Q => \^q\(2),
      R => '0'
    );
\word_aligned_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(1),
      Q => \^q\(1),
      R => '0'
    );
\word_aligned_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(0),
      Q => \^q\(0),
      R => '0'
    );
\word_aligned_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(6),
      Q => \^word_aligned_data_r_reg[0]_0\(6),
      R => '0'
    );
\word_aligned_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(5),
      Q => \^word_aligned_data_r_reg[0]_0\(5),
      R => '0'
    );
\word_aligned_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(4),
      Q => \^word_aligned_data_r_reg[0]_0\(4),
      R => '0'
    );
\word_aligned_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(3),
      Q => \^word_aligned_data_r_reg[0]_0\(3),
      R => '0'
    );
\word_aligned_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(2),
      Q => \^word_aligned_data_r_reg[0]_0\(2),
      R => '0'
    );
\word_aligned_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(1),
      Q => \^word_aligned_data_r_reg[0]_0\(1),
      R => '0'
    );
\word_aligned_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[0]_1\(0),
      Q => \^word_aligned_data_r_reg[0]_0\(0),
      R => '0'
    );
\word_aligned_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(7),
      Q => p_0_in(3),
      R => '0'
    );
\word_aligned_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \word_aligned_data_r_reg[8]_0\(6),
      Q => p_0_in(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_BARREL_SHIFTER is
  port (
    \SHIFTED_DATA_Buffer_reg[48]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \SHIFTED_DATA_Buffer_reg[48]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[49]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[49]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[50]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[50]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[51]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[51]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[52]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[52]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[53]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[53]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[54]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[54]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[55]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[55]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[56]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[56]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[57]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[57]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[58]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[58]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[59]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[59]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[60]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[60]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[61]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[61]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[62]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[62]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[63]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[63]_1\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[48]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[48]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[49]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[49]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[50]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[50]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[51]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[51]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[52]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[52]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[53]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[53]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[54]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[54]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[55]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[55]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[56]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[56]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[57]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[57]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[58]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[58]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[59]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[59]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[60]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[60]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[61]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[61]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[62]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[62]_3\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[63]_2\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[63]_3\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \SHIFTED_DATA_Buffer_reg[32]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[33]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[34]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[35]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[36]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[37]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[38]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[39]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[40]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[41]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[42]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[43]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[44]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[45]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[46]_0\ : out STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[47]_0\ : out STD_LOGIC;
    UFC_STORAGE_SELECT_Buffer : in STD_LOGIC_VECTOR ( 5 downto 0 );
    UFC_OUTPUT_SELECT_Buffer : in STD_LOGIC_VECTOR ( 3 downto 0 );
    MUXED_DATA_Buffer : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \SHIFTED_DATA_Buffer_reg[63]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[47]_1\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[15]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[62]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[14]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[61]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[13]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[60]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[12]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[59]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[11]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[58]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[10]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[57]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[9]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[56]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[8]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[55]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[7]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[54]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[6]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[53]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[5]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[52]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[4]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[51]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[3]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[50]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[2]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[49]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[1]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[48]_4\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[0]_0\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[32]_1\ : in STD_LOGIC;
    \SHIFTED_DATA_Buffer_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_UFC_BARREL_SHIFTER;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_BARREL_SHIFTER is
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal SHIFTED_DATA_Buffer : STD_LOGIC_VECTOR ( 16 to 63 );
  signal \SHIFTED_DATA_Buffer[32]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[33]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[34]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[35]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[36]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[37]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[38]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[39]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[40]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[41]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[42]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[43]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[44]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[45]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[46]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[47]_i_1_n_0\ : STD_LOGIC;
  signal \SHIFTED_DATA_Buffer[48]_i_1_n_0\ : STD_LOGIC;
  signal shifted_data_c : STD_LOGIC_VECTOR ( 0 to 31 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[32]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[33]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[34]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[35]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[36]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[37]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[38]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[39]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[40]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[41]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[42]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[43]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[44]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[45]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[46]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \SHIFTED_DATA_Buffer[47]_i_1\ : label is "soft_lutpair108";
begin
  Q(15 downto 0) <= \^q\(15 downto 0);
\MUXED_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(48),
      I1 => SHIFTED_DATA_Buffer(32),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(16),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(15),
      O => \SHIFTED_DATA_Buffer_reg[48]_1\
    );
\MUXED_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(58),
      I1 => SHIFTED_DATA_Buffer(42),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(26),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(5),
      O => \SHIFTED_DATA_Buffer_reg[58]_1\
    );
\MUXED_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(59),
      I1 => SHIFTED_DATA_Buffer(43),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(27),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(4),
      O => \SHIFTED_DATA_Buffer_reg[59]_1\
    );
\MUXED_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(60),
      I1 => SHIFTED_DATA_Buffer(44),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(28),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(3),
      O => \SHIFTED_DATA_Buffer_reg[60]_1\
    );
\MUXED_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(61),
      I1 => SHIFTED_DATA_Buffer(45),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(29),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(2),
      O => \SHIFTED_DATA_Buffer_reg[61]_1\
    );
\MUXED_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(62),
      I1 => SHIFTED_DATA_Buffer(46),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(30),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(1),
      O => \SHIFTED_DATA_Buffer_reg[62]_1\
    );
\MUXED_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(63),
      I1 => SHIFTED_DATA_Buffer(47),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(31),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(0),
      O => \SHIFTED_DATA_Buffer_reg[63]_1\
    );
\MUXED_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(48),
      I1 => SHIFTED_DATA_Buffer(32),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(16),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(15),
      O => \SHIFTED_DATA_Buffer_reg[48]_3\
    );
\MUXED_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(49),
      I1 => SHIFTED_DATA_Buffer(33),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(17),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(14),
      O => \SHIFTED_DATA_Buffer_reg[49]_3\
    );
\MUXED_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(50),
      I1 => SHIFTED_DATA_Buffer(34),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(18),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(13),
      O => \SHIFTED_DATA_Buffer_reg[50]_3\
    );
\MUXED_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(51),
      I1 => SHIFTED_DATA_Buffer(35),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(19),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(12),
      O => \SHIFTED_DATA_Buffer_reg[51]_3\
    );
\MUXED_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(49),
      I1 => SHIFTED_DATA_Buffer(33),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(17),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(14),
      O => \SHIFTED_DATA_Buffer_reg[49]_1\
    );
\MUXED_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(52),
      I1 => SHIFTED_DATA_Buffer(36),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(20),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(11),
      O => \SHIFTED_DATA_Buffer_reg[52]_3\
    );
\MUXED_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(53),
      I1 => SHIFTED_DATA_Buffer(37),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(21),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(10),
      O => \SHIFTED_DATA_Buffer_reg[53]_3\
    );
\MUXED_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(54),
      I1 => SHIFTED_DATA_Buffer(38),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(22),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(9),
      O => \SHIFTED_DATA_Buffer_reg[54]_3\
    );
\MUXED_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(55),
      I1 => SHIFTED_DATA_Buffer(39),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(23),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(8),
      O => \SHIFTED_DATA_Buffer_reg[55]_3\
    );
\MUXED_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(56),
      I1 => SHIFTED_DATA_Buffer(40),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(24),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(7),
      O => \SHIFTED_DATA_Buffer_reg[56]_3\
    );
\MUXED_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(57),
      I1 => SHIFTED_DATA_Buffer(41),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(25),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(6),
      O => \SHIFTED_DATA_Buffer_reg[57]_3\
    );
\MUXED_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(58),
      I1 => SHIFTED_DATA_Buffer(42),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(26),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(5),
      O => \SHIFTED_DATA_Buffer_reg[58]_3\
    );
\MUXED_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(59),
      I1 => SHIFTED_DATA_Buffer(43),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(27),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(4),
      O => \SHIFTED_DATA_Buffer_reg[59]_3\
    );
\MUXED_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(60),
      I1 => SHIFTED_DATA_Buffer(44),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(28),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(3),
      O => \SHIFTED_DATA_Buffer_reg[60]_3\
    );
\MUXED_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(61),
      I1 => SHIFTED_DATA_Buffer(45),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(29),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(2),
      O => \SHIFTED_DATA_Buffer_reg[61]_3\
    );
\MUXED_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(50),
      I1 => SHIFTED_DATA_Buffer(34),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(18),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(13),
      O => \SHIFTED_DATA_Buffer_reg[50]_1\
    );
\MUXED_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(62),
      I1 => SHIFTED_DATA_Buffer(46),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(30),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(1),
      O => \SHIFTED_DATA_Buffer_reg[62]_3\
    );
\MUXED_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(63),
      I1 => SHIFTED_DATA_Buffer(47),
      I2 => UFC_STORAGE_SELECT_Buffer(4),
      I3 => SHIFTED_DATA_Buffer(31),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(0),
      O => \SHIFTED_DATA_Buffer_reg[63]_3\
    );
\MUXED_DATA_Buffer[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(48),
      I1 => SHIFTED_DATA_Buffer(32),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(16),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(15),
      O => \SHIFTED_DATA_Buffer_reg[48]_0\
    );
\MUXED_DATA_Buffer[32]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(15),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(16),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(31),
      O => D(15)
    );
\MUXED_DATA_Buffer[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(49),
      I1 => SHIFTED_DATA_Buffer(33),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(17),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(14),
      O => \SHIFTED_DATA_Buffer_reg[49]_0\
    );
\MUXED_DATA_Buffer[33]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(14),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(17),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(30),
      O => D(14)
    );
\MUXED_DATA_Buffer[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(50),
      I1 => SHIFTED_DATA_Buffer(34),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(18),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(13),
      O => \SHIFTED_DATA_Buffer_reg[50]_0\
    );
\MUXED_DATA_Buffer[34]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(13),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(18),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(29),
      O => D(13)
    );
\MUXED_DATA_Buffer[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(51),
      I1 => SHIFTED_DATA_Buffer(35),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(19),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(12),
      O => \SHIFTED_DATA_Buffer_reg[51]_0\
    );
\MUXED_DATA_Buffer[35]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(12),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(19),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(28),
      O => D(12)
    );
\MUXED_DATA_Buffer[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(52),
      I1 => SHIFTED_DATA_Buffer(36),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(20),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(11),
      O => \SHIFTED_DATA_Buffer_reg[52]_0\
    );
\MUXED_DATA_Buffer[36]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(11),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(20),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(27),
      O => D(11)
    );
\MUXED_DATA_Buffer[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(53),
      I1 => SHIFTED_DATA_Buffer(37),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(21),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(10),
      O => \SHIFTED_DATA_Buffer_reg[53]_0\
    );
\MUXED_DATA_Buffer[37]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(10),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(21),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(26),
      O => D(10)
    );
\MUXED_DATA_Buffer[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(54),
      I1 => SHIFTED_DATA_Buffer(38),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(22),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(9),
      O => \SHIFTED_DATA_Buffer_reg[54]_0\
    );
\MUXED_DATA_Buffer[38]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(9),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(22),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(25),
      O => D(9)
    );
\MUXED_DATA_Buffer[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(55),
      I1 => SHIFTED_DATA_Buffer(39),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(23),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(8),
      O => \SHIFTED_DATA_Buffer_reg[55]_0\
    );
\MUXED_DATA_Buffer[39]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(8),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(23),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(24),
      O => D(8)
    );
\MUXED_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(51),
      I1 => SHIFTED_DATA_Buffer(35),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(19),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(12),
      O => \SHIFTED_DATA_Buffer_reg[51]_1\
    );
\MUXED_DATA_Buffer[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(56),
      I1 => SHIFTED_DATA_Buffer(40),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(24),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(7),
      O => \SHIFTED_DATA_Buffer_reg[56]_0\
    );
\MUXED_DATA_Buffer[40]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(7),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(24),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(23),
      O => D(7)
    );
\MUXED_DATA_Buffer[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(57),
      I1 => SHIFTED_DATA_Buffer(41),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(25),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(6),
      O => \SHIFTED_DATA_Buffer_reg[57]_0\
    );
\MUXED_DATA_Buffer[41]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(6),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(25),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(22),
      O => D(6)
    );
\MUXED_DATA_Buffer[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(58),
      I1 => SHIFTED_DATA_Buffer(42),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(26),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(5),
      O => \SHIFTED_DATA_Buffer_reg[58]_0\
    );
\MUXED_DATA_Buffer[42]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(5),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(26),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(21),
      O => D(5)
    );
\MUXED_DATA_Buffer[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(59),
      I1 => SHIFTED_DATA_Buffer(43),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(27),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(4),
      O => \SHIFTED_DATA_Buffer_reg[59]_0\
    );
\MUXED_DATA_Buffer[43]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(4),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(27),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(20),
      O => D(4)
    );
\MUXED_DATA_Buffer[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(60),
      I1 => SHIFTED_DATA_Buffer(44),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(28),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(3),
      O => \SHIFTED_DATA_Buffer_reg[60]_0\
    );
\MUXED_DATA_Buffer[44]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(3),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(28),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(19),
      O => D(3)
    );
\MUXED_DATA_Buffer[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(61),
      I1 => SHIFTED_DATA_Buffer(45),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(29),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(2),
      O => \SHIFTED_DATA_Buffer_reg[61]_0\
    );
\MUXED_DATA_Buffer[45]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(2),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(29),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(18),
      O => D(2)
    );
\MUXED_DATA_Buffer[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(62),
      I1 => SHIFTED_DATA_Buffer(46),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(30),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(1),
      O => \SHIFTED_DATA_Buffer_reg[62]_0\
    );
\MUXED_DATA_Buffer[46]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(1),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(30),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(17),
      O => D(1)
    );
\MUXED_DATA_Buffer[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(63),
      I1 => SHIFTED_DATA_Buffer(47),
      I2 => UFC_STORAGE_SELECT_Buffer(3),
      I3 => SHIFTED_DATA_Buffer(31),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(0),
      O => \SHIFTED_DATA_Buffer_reg[63]_0\
    );
\MUXED_DATA_Buffer[47]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \^q\(0),
      I1 => UFC_OUTPUT_SELECT_Buffer(2),
      I2 => SHIFTED_DATA_Buffer(31),
      I3 => UFC_OUTPUT_SELECT_Buffer(3),
      I4 => MUXED_DATA_Buffer(16),
      O => D(0)
    );
\MUXED_DATA_Buffer[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(48),
      I1 => SHIFTED_DATA_Buffer(32),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(16),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(15),
      O => \SHIFTED_DATA_Buffer_reg[48]_2\
    );
\MUXED_DATA_Buffer[48]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(32),
      I1 => SHIFTED_DATA_Buffer(16),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(15),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(15),
      O => \SHIFTED_DATA_Buffer_reg[32]_0\
    );
\MUXED_DATA_Buffer[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(49),
      I1 => SHIFTED_DATA_Buffer(33),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(17),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(14),
      O => \SHIFTED_DATA_Buffer_reg[49]_2\
    );
\MUXED_DATA_Buffer[49]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(33),
      I1 => SHIFTED_DATA_Buffer(17),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(14),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(14),
      O => \SHIFTED_DATA_Buffer_reg[33]_0\
    );
\MUXED_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(52),
      I1 => SHIFTED_DATA_Buffer(36),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(20),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(11),
      O => \SHIFTED_DATA_Buffer_reg[52]_1\
    );
\MUXED_DATA_Buffer[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(50),
      I1 => SHIFTED_DATA_Buffer(34),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(18),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(13),
      O => \SHIFTED_DATA_Buffer_reg[50]_2\
    );
\MUXED_DATA_Buffer[50]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(34),
      I1 => SHIFTED_DATA_Buffer(18),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(13),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(13),
      O => \SHIFTED_DATA_Buffer_reg[34]_0\
    );
\MUXED_DATA_Buffer[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(51),
      I1 => SHIFTED_DATA_Buffer(35),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(19),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(12),
      O => \SHIFTED_DATA_Buffer_reg[51]_2\
    );
\MUXED_DATA_Buffer[51]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(35),
      I1 => SHIFTED_DATA_Buffer(19),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(12),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(12),
      O => \SHIFTED_DATA_Buffer_reg[35]_0\
    );
\MUXED_DATA_Buffer[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(52),
      I1 => SHIFTED_DATA_Buffer(36),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(20),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(11),
      O => \SHIFTED_DATA_Buffer_reg[52]_2\
    );
\MUXED_DATA_Buffer[52]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(36),
      I1 => SHIFTED_DATA_Buffer(20),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(11),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(11),
      O => \SHIFTED_DATA_Buffer_reg[36]_0\
    );
\MUXED_DATA_Buffer[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(53),
      I1 => SHIFTED_DATA_Buffer(37),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(21),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(10),
      O => \SHIFTED_DATA_Buffer_reg[53]_2\
    );
\MUXED_DATA_Buffer[53]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(37),
      I1 => SHIFTED_DATA_Buffer(21),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(10),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(10),
      O => \SHIFTED_DATA_Buffer_reg[37]_0\
    );
\MUXED_DATA_Buffer[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(54),
      I1 => SHIFTED_DATA_Buffer(38),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(22),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(9),
      O => \SHIFTED_DATA_Buffer_reg[54]_2\
    );
\MUXED_DATA_Buffer[54]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(38),
      I1 => SHIFTED_DATA_Buffer(22),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(9),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(9),
      O => \SHIFTED_DATA_Buffer_reg[38]_0\
    );
\MUXED_DATA_Buffer[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(55),
      I1 => SHIFTED_DATA_Buffer(39),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(23),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(8),
      O => \SHIFTED_DATA_Buffer_reg[55]_2\
    );
\MUXED_DATA_Buffer[55]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(39),
      I1 => SHIFTED_DATA_Buffer(23),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(8),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(8),
      O => \SHIFTED_DATA_Buffer_reg[39]_0\
    );
\MUXED_DATA_Buffer[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(56),
      I1 => SHIFTED_DATA_Buffer(40),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(24),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(7),
      O => \SHIFTED_DATA_Buffer_reg[56]_2\
    );
\MUXED_DATA_Buffer[56]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(40),
      I1 => SHIFTED_DATA_Buffer(24),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(7),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(7),
      O => \SHIFTED_DATA_Buffer_reg[40]_0\
    );
\MUXED_DATA_Buffer[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(57),
      I1 => SHIFTED_DATA_Buffer(41),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(25),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(6),
      O => \SHIFTED_DATA_Buffer_reg[57]_2\
    );
\MUXED_DATA_Buffer[57]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(41),
      I1 => SHIFTED_DATA_Buffer(25),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(6),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(6),
      O => \SHIFTED_DATA_Buffer_reg[41]_0\
    );
\MUXED_DATA_Buffer[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(58),
      I1 => SHIFTED_DATA_Buffer(42),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(26),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(5),
      O => \SHIFTED_DATA_Buffer_reg[58]_2\
    );
\MUXED_DATA_Buffer[58]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(42),
      I1 => SHIFTED_DATA_Buffer(26),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(5),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(5),
      O => \SHIFTED_DATA_Buffer_reg[42]_0\
    );
\MUXED_DATA_Buffer[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(59),
      I1 => SHIFTED_DATA_Buffer(43),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(27),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(4),
      O => \SHIFTED_DATA_Buffer_reg[59]_2\
    );
\MUXED_DATA_Buffer[59]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(43),
      I1 => SHIFTED_DATA_Buffer(27),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(4),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(4),
      O => \SHIFTED_DATA_Buffer_reg[43]_0\
    );
\MUXED_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(53),
      I1 => SHIFTED_DATA_Buffer(37),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(21),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(10),
      O => \SHIFTED_DATA_Buffer_reg[53]_1\
    );
\MUXED_DATA_Buffer[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(60),
      I1 => SHIFTED_DATA_Buffer(44),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(28),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(3),
      O => \SHIFTED_DATA_Buffer_reg[60]_2\
    );
\MUXED_DATA_Buffer[60]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(44),
      I1 => SHIFTED_DATA_Buffer(28),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(3),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(3),
      O => \SHIFTED_DATA_Buffer_reg[44]_0\
    );
\MUXED_DATA_Buffer[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(61),
      I1 => SHIFTED_DATA_Buffer(45),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(29),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(2),
      O => \SHIFTED_DATA_Buffer_reg[61]_2\
    );
\MUXED_DATA_Buffer[61]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(45),
      I1 => SHIFTED_DATA_Buffer(29),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(2),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(2),
      O => \SHIFTED_DATA_Buffer_reg[45]_0\
    );
\MUXED_DATA_Buffer[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(62),
      I1 => SHIFTED_DATA_Buffer(46),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(30),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(1),
      O => \SHIFTED_DATA_Buffer_reg[62]_2\
    );
\MUXED_DATA_Buffer[62]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(46),
      I1 => SHIFTED_DATA_Buffer(30),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(1),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(1),
      O => \SHIFTED_DATA_Buffer_reg[46]_0\
    );
\MUXED_DATA_Buffer[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(63),
      I1 => SHIFTED_DATA_Buffer(47),
      I2 => UFC_STORAGE_SELECT_Buffer(1),
      I3 => SHIFTED_DATA_Buffer(31),
      I4 => UFC_STORAGE_SELECT_Buffer(0),
      I5 => \^q\(0),
      O => \SHIFTED_DATA_Buffer_reg[63]_2\
    );
\MUXED_DATA_Buffer[63]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(47),
      I1 => SHIFTED_DATA_Buffer(31),
      I2 => UFC_OUTPUT_SELECT_Buffer(1),
      I3 => \^q\(0),
      I4 => UFC_OUTPUT_SELECT_Buffer(0),
      I5 => MUXED_DATA_Buffer(0),
      O => \SHIFTED_DATA_Buffer_reg[47]_0\
    );
\MUXED_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(54),
      I1 => SHIFTED_DATA_Buffer(38),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(22),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(9),
      O => \SHIFTED_DATA_Buffer_reg[54]_1\
    );
\MUXED_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(55),
      I1 => SHIFTED_DATA_Buffer(39),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(23),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(8),
      O => \SHIFTED_DATA_Buffer_reg[55]_1\
    );
\MUXED_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(56),
      I1 => SHIFTED_DATA_Buffer(40),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(24),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(7),
      O => \SHIFTED_DATA_Buffer_reg[56]_1\
    );
\MUXED_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => SHIFTED_DATA_Buffer(57),
      I1 => SHIFTED_DATA_Buffer(41),
      I2 => UFC_STORAGE_SELECT_Buffer(5),
      I3 => SHIFTED_DATA_Buffer(25),
      I4 => UFC_STORAGE_SELECT_Buffer(2),
      I5 => \^q\(6),
      O => \SHIFTED_DATA_Buffer_reg[57]_1\
    );
\SHIFTED_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(15),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(31),
      I2 => \SHIFTED_DATA_Buffer_reg[48]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[0]_0\,
      O => shifted_data_c(0)
    );
\SHIFTED_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(5),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(21),
      I2 => \SHIFTED_DATA_Buffer_reg[58]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[10]_0\,
      O => shifted_data_c(10)
    );
\SHIFTED_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(4),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(20),
      I2 => \SHIFTED_DATA_Buffer_reg[59]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[11]_0\,
      O => shifted_data_c(11)
    );
\SHIFTED_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(3),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(19),
      I2 => \SHIFTED_DATA_Buffer_reg[60]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[12]_0\,
      O => shifted_data_c(12)
    );
\SHIFTED_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(2),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(18),
      I2 => \SHIFTED_DATA_Buffer_reg[61]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[13]_0\,
      O => shifted_data_c(13)
    );
\SHIFTED_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(1),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(17),
      I2 => \SHIFTED_DATA_Buffer_reg[62]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[14]_0\,
      O => shifted_data_c(14)
    );
\SHIFTED_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(0),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(16),
      I2 => \SHIFTED_DATA_Buffer_reg[63]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[15]_0\,
      O => shifted_data_c(15)
    );
\SHIFTED_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[48]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(15),
      O => shifted_data_c(16)
    );
\SHIFTED_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[1]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[49]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(14),
      O => shifted_data_c(17)
    );
\SHIFTED_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[2]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[50]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(13),
      O => shifted_data_c(18)
    );
\SHIFTED_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[3]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[51]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(12),
      O => shifted_data_c(19)
    );
\SHIFTED_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(14),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(30),
      I2 => \SHIFTED_DATA_Buffer_reg[49]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[1]_0\,
      O => shifted_data_c(1)
    );
\SHIFTED_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[4]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[52]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(11),
      O => shifted_data_c(20)
    );
\SHIFTED_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[5]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[53]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(10),
      O => shifted_data_c(21)
    );
\SHIFTED_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[6]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[54]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(9),
      O => shifted_data_c(22)
    );
\SHIFTED_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[7]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[55]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(8),
      O => shifted_data_c(23)
    );
\SHIFTED_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[8]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[56]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(7),
      O => shifted_data_c(24)
    );
\SHIFTED_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[9]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[57]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(6),
      O => shifted_data_c(25)
    );
\SHIFTED_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[10]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[58]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(5),
      O => shifted_data_c(26)
    );
\SHIFTED_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[11]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[59]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(4),
      O => shifted_data_c(27)
    );
\SHIFTED_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[12]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[60]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(3),
      O => shifted_data_c(28)
    );
\SHIFTED_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[13]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[61]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(2),
      O => shifted_data_c(29)
    );
\SHIFTED_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(13),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(29),
      I2 => \SHIFTED_DATA_Buffer_reg[50]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[2]_0\,
      O => shifted_data_c(2)
    );
\SHIFTED_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[14]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[62]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(1),
      O => shifted_data_c(30)
    );
\SHIFTED_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[15]_0\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[63]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[0]_1\(0),
      O => shifted_data_c(31)
    );
\SHIFTED_DATA_Buffer[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[48]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[0]_0\,
      O => \SHIFTED_DATA_Buffer[32]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[49]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[1]_0\,
      O => \SHIFTED_DATA_Buffer[33]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[50]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[2]_0\,
      O => \SHIFTED_DATA_Buffer[34]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[51]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[3]_0\,
      O => \SHIFTED_DATA_Buffer[35]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[52]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[4]_0\,
      O => \SHIFTED_DATA_Buffer[36]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[53]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[5]_0\,
      O => \SHIFTED_DATA_Buffer[37]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[54]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[6]_0\,
      O => \SHIFTED_DATA_Buffer[38]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[55]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[7]_0\,
      O => \SHIFTED_DATA_Buffer[39]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(12),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(28),
      I2 => \SHIFTED_DATA_Buffer_reg[51]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[3]_0\,
      O => shifted_data_c(3)
    );
\SHIFTED_DATA_Buffer[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[56]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[8]_0\,
      O => \SHIFTED_DATA_Buffer[40]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[57]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[9]_0\,
      O => \SHIFTED_DATA_Buffer[41]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[58]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[10]_0\,
      O => \SHIFTED_DATA_Buffer[42]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[59]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[11]_0\,
      O => \SHIFTED_DATA_Buffer[43]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[60]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[12]_0\,
      O => \SHIFTED_DATA_Buffer[44]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[61]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[13]_0\,
      O => \SHIFTED_DATA_Buffer[45]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[62]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[14]_0\,
      O => \SHIFTED_DATA_Buffer[46]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[63]_4\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I2 => \SHIFTED_DATA_Buffer_reg[15]_0\,
      O => \SHIFTED_DATA_Buffer[47]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[48]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I1 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      O => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(11),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(27),
      I2 => \SHIFTED_DATA_Buffer_reg[52]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[4]_0\,
      O => shifted_data_c(4)
    );
\SHIFTED_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(10),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(26),
      I2 => \SHIFTED_DATA_Buffer_reg[53]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[5]_0\,
      O => shifted_data_c(5)
    );
\SHIFTED_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(9),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(25),
      I2 => \SHIFTED_DATA_Buffer_reg[54]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[6]_0\,
      O => shifted_data_c(6)
    );
\SHIFTED_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(8),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(24),
      I2 => \SHIFTED_DATA_Buffer_reg[55]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[7]_0\,
      O => shifted_data_c(7)
    );
\SHIFTED_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(7),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(23),
      I2 => \SHIFTED_DATA_Buffer_reg[56]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[8]_0\,
      O => shifted_data_c(8)
    );
\SHIFTED_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \SHIFTED_DATA_Buffer_reg[0]_1\(6),
      I1 => \SHIFTED_DATA_Buffer_reg[0]_1\(22),
      I2 => \SHIFTED_DATA_Buffer_reg[57]_4\,
      I3 => \SHIFTED_DATA_Buffer_reg[32]_1\,
      I4 => \SHIFTED_DATA_Buffer_reg[47]_1\,
      I5 => \SHIFTED_DATA_Buffer_reg[9]_0\,
      O => shifted_data_c(9)
    );
\SHIFTED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(0),
      Q => \^q\(15),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(10),
      Q => \^q\(5),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(11),
      Q => \^q\(4),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(12),
      Q => \^q\(3),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(13),
      Q => \^q\(2),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(14),
      Q => \^q\(1),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(15),
      Q => \^q\(0),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(16),
      Q => SHIFTED_DATA_Buffer(16),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(17),
      Q => SHIFTED_DATA_Buffer(17),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(18),
      Q => SHIFTED_DATA_Buffer(18),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(19),
      Q => SHIFTED_DATA_Buffer(19),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(1),
      Q => \^q\(14),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(20),
      Q => SHIFTED_DATA_Buffer(20),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(21),
      Q => SHIFTED_DATA_Buffer(21),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(22),
      Q => SHIFTED_DATA_Buffer(22),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(23),
      Q => SHIFTED_DATA_Buffer(23),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(24),
      Q => SHIFTED_DATA_Buffer(24),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(25),
      Q => SHIFTED_DATA_Buffer(25),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(26),
      Q => SHIFTED_DATA_Buffer(26),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(27),
      Q => SHIFTED_DATA_Buffer(27),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(28),
      Q => SHIFTED_DATA_Buffer(28),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(29),
      Q => SHIFTED_DATA_Buffer(29),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(2),
      Q => \^q\(13),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(30),
      Q => SHIFTED_DATA_Buffer(30),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(31),
      Q => SHIFTED_DATA_Buffer(31),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[32]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(32),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[33]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(33),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[34]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(34),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[35]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(35),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[36]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(36),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[37]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(37),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[38]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(38),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[39]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(39),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(3),
      Q => \^q\(12),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[40]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(40),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[41]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(41),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[42]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(42),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[43]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(43),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[44]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(44),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[45]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(45),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[46]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(46),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer[47]_i_1_n_0\,
      Q => SHIFTED_DATA_Buffer(47),
      R => \SHIFTED_DATA_Buffer_reg[32]_1\
    );
\SHIFTED_DATA_Buffer_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[48]_4\,
      Q => SHIFTED_DATA_Buffer(48),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[49]_4\,
      Q => SHIFTED_DATA_Buffer(49),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(4),
      Q => \^q\(11),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[50]_4\,
      Q => SHIFTED_DATA_Buffer(50),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[51]_4\,
      Q => SHIFTED_DATA_Buffer(51),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[52]_4\,
      Q => SHIFTED_DATA_Buffer(52),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[53]_4\,
      Q => SHIFTED_DATA_Buffer(53),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[54]_4\,
      Q => SHIFTED_DATA_Buffer(54),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[55]_4\,
      Q => SHIFTED_DATA_Buffer(55),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[56]_4\,
      Q => SHIFTED_DATA_Buffer(56),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[57]_4\,
      Q => SHIFTED_DATA_Buffer(57),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[58]_4\,
      Q => SHIFTED_DATA_Buffer(58),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[59]_4\,
      Q => SHIFTED_DATA_Buffer(59),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(5),
      Q => \^q\(10),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[60]_4\,
      Q => SHIFTED_DATA_Buffer(60),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[61]_4\,
      Q => SHIFTED_DATA_Buffer(61),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[62]_4\,
      Q => SHIFTED_DATA_Buffer(62),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \SHIFTED_DATA_Buffer_reg[63]_4\,
      Q => SHIFTED_DATA_Buffer(63),
      R => \SHIFTED_DATA_Buffer[48]_i_1_n_0\
    );
\SHIFTED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(6),
      Q => \^q\(9),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(7),
      Q => \^q\(8),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(8),
      Q => \^q\(7),
      R => '0'
    );
\SHIFTED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => shifted_data_c(9),
      Q => \^q\(6),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL is
  port (
    \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0\ : out STD_LOGIC;
    \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0\ : out STD_LOGIC;
    \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1\ : in STD_LOGIC
  );
end aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL is
begin
\BARREL_SHIFTER_CONTROL_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1\,
      Q => \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0\,
      R => '0'
    );
\BARREL_SHIFTER_CONTROL_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1\,
      Q => \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_FILTER is
  port (
    ufc_start_i : out STD_LOGIC;
    pdu_pad_i : out STD_LOGIC_VECTOR ( 0 to 3 );
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \word_aligned_data_r_reg[7]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[7]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[7]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[7]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[6]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[6]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[6]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[6]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[5]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[5]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[5]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[5]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[4]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[4]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[4]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[4]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[3]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[3]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[3]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[3]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[2]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[2]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[2]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[2]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[1]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[1]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[1]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[1]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[0]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[0]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[0]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[0]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[15]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[15]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[15]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[15]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[14]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[14]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[14]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[14]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[13]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[13]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[13]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[13]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[12]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[12]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[12]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[12]_2\ : out STD_LOGIC;
    \word_aligned_data_r_reg[11]\ : out STD_LOGIC;
    \word_aligned_data_r_reg[11]_0\ : out STD_LOGIC;
    \word_aligned_data_r_reg[11]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[11]_2\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_1\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_2\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]_1\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]_2\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_0\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_1\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_2\ : out STD_LOGIC;
    \PDU_ECP_Buffer_reg[3]_0\ : out STD_LOGIC;
    \PDU_SCP_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \PDU_ECP_Buffer_reg[2]_0\ : out STD_LOGIC;
    \PDU_ECP_Buffer_reg[1]_0\ : out STD_LOGIC;
    \PDU_ECP_Buffer_reg[0]_0\ : out STD_LOGIC;
    \UFC_MESSAGE_START_Buffer_reg[1]_0\ : out STD_LOGIC;
    \UFC_MESSAGE_START_Buffer_reg[1]_1\ : out STD_LOGIC;
    \PDU_DATA_V_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \UFC_DATA_V_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \PDU_SCP_Buffer_reg[3]_0\ : out STD_LOGIC;
    S1_in : out STD_LOGIC;
    S3_in : out STD_LOGIC;
    S5_in : out STD_LOGIC;
    RESET : in STD_LOGIC;
    neqOp : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[3]_0\ : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[1]_0\ : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[2]_0\ : in STD_LOGIC;
    std_bool26_out : in STD_LOGIC;
    std_bool26_out_0 : in STD_LOGIC;
    std_bool26_out_1 : in STD_LOGIC;
    std_bool26_out_2 : in STD_LOGIC;
    RX_ECP_Buffer0 : in STD_LOGIC;
    RX_ECP_Buffer0_3 : in STD_LOGIC;
    RX_ECP_Buffer0_4 : in STD_LOGIC;
    RX_ECP_Buffer0_5 : in STD_LOGIC;
    \stage_1_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[16]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[48]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[32]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[11]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \stage_1_data_r_reg[59]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \stage_1_data_r_reg[43]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    RX_PE_DATA : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \stage_1_data_r_reg[26]\ : in STD_LOGIC;
    \stage_1_data_r_reg[58]\ : in STD_LOGIC;
    \stage_1_data_r_reg[42]\ : in STD_LOGIC;
    \stage_1_data_r_reg[25]\ : in STD_LOGIC;
    \stage_1_data_r_reg[57]\ : in STD_LOGIC;
    \stage_1_data_r_reg[41]\ : in STD_LOGIC;
    \stage_1_data_r_reg[24]\ : in STD_LOGIC;
    \stage_1_data_r_reg[56]\ : in STD_LOGIC;
    \stage_1_data_r_reg[40]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[0]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]_0\ : in STD_LOGIC;
    \rx_data_v_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rx_scp_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rx_suf_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
end aurora_rx_4l_64b_UFC_FILTER;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_FILTER is
  signal \^d\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \PDU_DATA_V_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \PDU_DATA_V_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal \PDU_DATA_V_Buffer[2]_i_1_n_0\ : STD_LOGIC;
  signal \PDU_DATA_V_Buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal \^pdu_scp_buffer_reg[0]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \UFC_DATA_V_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal \UFC_DATA_V_Buffer[2]_i_1_n_0\ : STD_LOGIC;
  signal \UFC_DATA_V_Buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal load_ufc_control_code_r : STD_LOGIC;
  signal \neqOp_inferred__0/i__n_0\ : STD_LOGIC;
  signal rx_data_v_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \rx_ecp_r_reg[0]_srl2_n_0\ : STD_LOGIC;
  signal \rx_ecp_r_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \rx_ecp_r_reg[2]_srl2_n_0\ : STD_LOGIC;
  signal \rx_ecp_r_reg[3]_srl2_n_0\ : STD_LOGIC;
  signal \rx_pad_r_reg[0]_srl2_n_0\ : STD_LOGIC;
  signal \rx_pad_r_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \rx_pad_r_reg[2]_srl2_n_0\ : STD_LOGIC;
  signal \rx_pad_r_reg[3]_srl2_n_0\ : STD_LOGIC;
  signal rx_scp_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \rx_suf_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \rx_suf_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \rx_suf_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \rx_suf_r_reg_n_0_[3]\ : STD_LOGIC;
  signal save_start_r : STD_LOGIC;
  signal stage_1_count_value_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \stage_1_lane_mask_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \stage_1_lane_mask_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \stage_1_lane_mask_r_reg_n_0_[3]\ : STD_LOGIC;
  signal stage_2_count_value_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \stage_2_count_value_r[0]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_count_value_r[1]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_count_value_r[2]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_count_value_r[3]_i_1_n_0\ : STD_LOGIC;
  signal \stage_2_lane_mask_c__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ufc_message_start_i : STD_LOGIC_VECTOR ( 0 to 2 );
  attribute srl_bus_name : string;
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[0]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name : string;
  attribute srl_name of \PDU_DATA_Buffer_reg[0]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[0]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[10]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[10]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[10]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[11]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[11]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[11]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[12]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[12]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[12]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[13]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[13]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[13]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[14]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[14]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[14]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[15]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[15]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[15]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[16]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[16]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[16]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[17]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[17]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[17]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[18]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[18]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[18]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[19]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[19]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[19]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[1]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[1]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[1]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[20]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[20]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[20]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[21]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[21]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[21]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[22]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[22]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[22]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[23]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[23]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[23]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[24]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[24]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[24]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[25]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[25]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[25]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[26]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[26]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[26]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[27]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[27]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[27]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[28]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[28]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[28]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[29]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[29]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[29]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[2]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[2]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[2]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[30]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[30]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[30]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[31]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[31]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[31]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[32]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[32]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[32]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[33]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[33]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[33]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[34]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[34]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[34]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[35]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[35]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[35]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[36]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[36]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[36]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[37]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[37]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[37]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[38]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[38]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[38]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[39]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[39]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[39]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[3]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[3]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[3]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[40]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[40]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[40]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[41]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[41]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[41]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[42]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[42]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[42]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[43]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[43]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[43]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[44]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[44]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[44]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[45]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[45]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[45]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[46]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[46]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[46]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[47]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[47]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[47]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[48]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[48]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[48]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[49]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[49]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[49]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[4]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[4]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[4]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[50]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[50]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[50]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[51]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[51]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[51]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[52]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[52]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[52]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[53]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[53]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[53]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[54]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[54]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[54]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[55]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[55]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[55]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[56]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[56]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[56]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[57]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[57]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[57]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[58]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[58]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[58]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[59]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[59]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[59]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[5]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[5]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[5]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[60]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[60]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[60]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[61]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[61]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[61]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[62]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[62]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[62]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[63]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[63]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[63]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[6]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[6]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[6]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[7]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[7]_srl4\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[7]_srl4 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[8]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[8]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[8]_srl2 ";
  attribute srl_bus_name of \PDU_DATA_Buffer_reg[9]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg ";
  attribute srl_name of \PDU_DATA_Buffer_reg[9]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[9]_srl2 ";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \PDU_DATA_V_Buffer[0]_i_1\ : label is "soft_lutpair122";
  attribute srl_bus_name of \rx_ecp_r_reg[0]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg ";
  attribute srl_name of \rx_ecp_r_reg[0]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[0]_srl2 ";
  attribute srl_bus_name of \rx_ecp_r_reg[1]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg ";
  attribute srl_name of \rx_ecp_r_reg[1]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[1]_srl2 ";
  attribute srl_bus_name of \rx_ecp_r_reg[2]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg ";
  attribute srl_name of \rx_ecp_r_reg[2]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[2]_srl2 ";
  attribute srl_bus_name of \rx_ecp_r_reg[3]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg ";
  attribute srl_name of \rx_ecp_r_reg[3]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[3]_srl2 ";
  attribute srl_bus_name of \rx_pad_r_reg[0]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg ";
  attribute srl_name of \rx_pad_r_reg[0]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[0]_srl2 ";
  attribute srl_bus_name of \rx_pad_r_reg[1]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg ";
  attribute srl_name of \rx_pad_r_reg[1]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[1]_srl2 ";
  attribute srl_bus_name of \rx_pad_r_reg[2]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg ";
  attribute srl_name of \rx_pad_r_reg[2]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[2]_srl2 ";
  attribute srl_bus_name of \rx_pad_r_reg[3]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg ";
  attribute srl_name of \rx_pad_r_reg[3]_srl2\ : label is "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[3]_srl2 ";
  attribute SOFT_HLUTNM of stage_2_lane_mask_c : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \ufc_barrel_shifter_control_i/BARREL_SHIFTER_CONTROL_Buffer[1]_i_1\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \ufc_barrel_shifter_control_i/BARREL_SHIFTER_CONTROL_Buffer[2]_i_1\ : label is "soft_lutpair123";
begin
  D(3 downto 0) <= \^d\(3 downto 0);
  \PDU_SCP_Buffer_reg[0]_0\(3 downto 0) <= \^pdu_scp_buffer_reg[0]_0\(3 downto 0);
\PDU_DATA_Buffer_reg[0]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(7),
      Q => \word_aligned_data_r_reg[0]\
    );
\PDU_DATA_Buffer_reg[10]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(0),
      Q => \RX_PE_DATA_Buffer_reg[10]\
    );
\PDU_DATA_Buffer_reg[11]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(4),
      Q => \word_aligned_data_r_reg[11]\
    );
\PDU_DATA_Buffer_reg[12]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(3),
      Q => \word_aligned_data_r_reg[12]\
    );
\PDU_DATA_Buffer_reg[13]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(2),
      Q => \word_aligned_data_r_reg[13]\
    );
\PDU_DATA_Buffer_reg[14]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(1),
      Q => \word_aligned_data_r_reg[14]\
    );
\PDU_DATA_Buffer_reg[15]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[11]\(0),
      Q => \word_aligned_data_r_reg[15]\
    );
\PDU_DATA_Buffer_reg[16]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(7),
      Q => \word_aligned_data_r_reg[0]_0\
    );
\PDU_DATA_Buffer_reg[17]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(6),
      Q => \word_aligned_data_r_reg[1]_0\
    );
\PDU_DATA_Buffer_reg[18]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(5),
      Q => \word_aligned_data_r_reg[2]_0\
    );
\PDU_DATA_Buffer_reg[19]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(4),
      Q => \word_aligned_data_r_reg[3]_0\
    );
\PDU_DATA_Buffer_reg[1]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(6),
      Q => \word_aligned_data_r_reg[1]\
    );
\PDU_DATA_Buffer_reg[20]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(3),
      Q => \word_aligned_data_r_reg[4]_0\
    );
\PDU_DATA_Buffer_reg[21]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(2),
      Q => \word_aligned_data_r_reg[5]_0\
    );
\PDU_DATA_Buffer_reg[22]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(1),
      Q => \word_aligned_data_r_reg[6]_0\
    );
\PDU_DATA_Buffer_reg[23]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[16]\(0),
      Q => \word_aligned_data_r_reg[7]_0\
    );
\PDU_DATA_Buffer_reg[24]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[24]\,
      Q => \RX_PE_DATA_Buffer_reg[8]_0\
    );
\PDU_DATA_Buffer_reg[25]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[25]\,
      Q => \RX_PE_DATA_Buffer_reg[9]_0\
    );
\PDU_DATA_Buffer_reg[26]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[26]\,
      Q => \RX_PE_DATA_Buffer_reg[10]_0\
    );
\PDU_DATA_Buffer_reg[27]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => Q(4),
      Q => \word_aligned_data_r_reg[11]_0\
    );
\PDU_DATA_Buffer_reg[28]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => Q(3),
      Q => \word_aligned_data_r_reg[12]_0\
    );
\PDU_DATA_Buffer_reg[29]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => Q(2),
      Q => \word_aligned_data_r_reg[13]_0\
    );
\PDU_DATA_Buffer_reg[2]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(5),
      Q => \word_aligned_data_r_reg[2]\
    );
\PDU_DATA_Buffer_reg[30]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => Q(1),
      Q => \word_aligned_data_r_reg[14]_0\
    );
\PDU_DATA_Buffer_reg[31]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => Q(0),
      Q => \word_aligned_data_r_reg[15]_0\
    );
\PDU_DATA_Buffer_reg[32]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(7),
      Q => \word_aligned_data_r_reg[0]_2\
    );
\PDU_DATA_Buffer_reg[33]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(6),
      Q => \word_aligned_data_r_reg[1]_2\
    );
\PDU_DATA_Buffer_reg[34]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(5),
      Q => \word_aligned_data_r_reg[2]_2\
    );
\PDU_DATA_Buffer_reg[35]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(4),
      Q => \word_aligned_data_r_reg[3]_2\
    );
\PDU_DATA_Buffer_reg[36]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(3),
      Q => \word_aligned_data_r_reg[4]_2\
    );
\PDU_DATA_Buffer_reg[37]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(2),
      Q => \word_aligned_data_r_reg[5]_2\
    );
\PDU_DATA_Buffer_reg[38]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(1),
      Q => \word_aligned_data_r_reg[6]_2\
    );
\PDU_DATA_Buffer_reg[39]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[32]\(0),
      Q => \word_aligned_data_r_reg[7]_2\
    );
\PDU_DATA_Buffer_reg[3]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(4),
      Q => \word_aligned_data_r_reg[3]\
    );
\PDU_DATA_Buffer_reg[40]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[40]\,
      Q => \RX_PE_DATA_Buffer_reg[8]_2\
    );
\PDU_DATA_Buffer_reg[41]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[41]\,
      Q => \RX_PE_DATA_Buffer_reg[9]_2\
    );
\PDU_DATA_Buffer_reg[42]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[42]\,
      Q => \RX_PE_DATA_Buffer_reg[10]_2\
    );
\PDU_DATA_Buffer_reg[43]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[43]\(4),
      Q => \word_aligned_data_r_reg[11]_2\
    );
\PDU_DATA_Buffer_reg[44]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[43]\(3),
      Q => \word_aligned_data_r_reg[12]_2\
    );
\PDU_DATA_Buffer_reg[45]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[43]\(2),
      Q => \word_aligned_data_r_reg[13]_2\
    );
\PDU_DATA_Buffer_reg[46]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[43]\(1),
      Q => \word_aligned_data_r_reg[14]_2\
    );
\PDU_DATA_Buffer_reg[47]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[43]\(0),
      Q => \word_aligned_data_r_reg[15]_2\
    );
\PDU_DATA_Buffer_reg[48]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(7),
      Q => \word_aligned_data_r_reg[0]_1\
    );
\PDU_DATA_Buffer_reg[49]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(6),
      Q => \word_aligned_data_r_reg[1]_1\
    );
\PDU_DATA_Buffer_reg[4]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(3),
      Q => \word_aligned_data_r_reg[4]\
    );
\PDU_DATA_Buffer_reg[50]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(5),
      Q => \word_aligned_data_r_reg[2]_1\
    );
\PDU_DATA_Buffer_reg[51]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(4),
      Q => \word_aligned_data_r_reg[3]_1\
    );
\PDU_DATA_Buffer_reg[52]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(3),
      Q => \word_aligned_data_r_reg[4]_1\
    );
\PDU_DATA_Buffer_reg[53]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(2),
      Q => \word_aligned_data_r_reg[5]_1\
    );
\PDU_DATA_Buffer_reg[54]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(1),
      Q => \word_aligned_data_r_reg[6]_1\
    );
\PDU_DATA_Buffer_reg[55]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[48]\(0),
      Q => \word_aligned_data_r_reg[7]_1\
    );
\PDU_DATA_Buffer_reg[56]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[56]\,
      Q => \RX_PE_DATA_Buffer_reg[8]_1\
    );
\PDU_DATA_Buffer_reg[57]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[57]\,
      Q => \RX_PE_DATA_Buffer_reg[9]_1\
    );
\PDU_DATA_Buffer_reg[58]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[58]\,
      Q => \RX_PE_DATA_Buffer_reg[10]_1\
    );
\PDU_DATA_Buffer_reg[59]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[59]\(4),
      Q => \word_aligned_data_r_reg[11]_1\
    );
\PDU_DATA_Buffer_reg[5]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(2),
      Q => \word_aligned_data_r_reg[5]\
    );
\PDU_DATA_Buffer_reg[60]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[59]\(3),
      Q => \word_aligned_data_r_reg[12]_1\
    );
\PDU_DATA_Buffer_reg[61]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[59]\(2),
      Q => \word_aligned_data_r_reg[13]_1\
    );
\PDU_DATA_Buffer_reg[62]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[59]\(1),
      Q => \word_aligned_data_r_reg[14]_1\
    );
\PDU_DATA_Buffer_reg[63]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[59]\(0),
      Q => \word_aligned_data_r_reg[15]_1\
    );
\PDU_DATA_Buffer_reg[6]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(1),
      Q => \word_aligned_data_r_reg[6]\
    );
\PDU_DATA_Buffer_reg[7]_srl4\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \stage_1_data_r_reg[0]\(0),
      Q => \word_aligned_data_r_reg[7]\
    );
\PDU_DATA_Buffer_reg[8]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(2),
      Q => \RX_PE_DATA_Buffer_reg[8]\
    );
\PDU_DATA_Buffer_reg[9]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_PE_DATA(1),
      Q => \RX_PE_DATA_Buffer_reg[9]\
    );
\PDU_DATA_V_Buffer[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888882"
    )
        port map (
      I0 => rx_data_v_r(0),
      I1 => stage_2_count_value_r(0),
      I2 => stage_2_count_value_r(1),
      I3 => stage_2_count_value_r(2),
      I4 => stage_2_count_value_r(3),
      O => \PDU_DATA_V_Buffer[0]_i_1_n_0\
    );
\PDU_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AA02A802"
    )
        port map (
      I0 => rx_data_v_r(1),
      I1 => stage_2_count_value_r(2),
      I2 => stage_2_count_value_r(1),
      I3 => stage_2_count_value_r(0),
      I4 => stage_2_count_value_r(3),
      I5 => \stage_1_lane_mask_r_reg_n_0_[1]\,
      O => \PDU_DATA_V_Buffer[1]_i_1_n_0\
    );
\PDU_DATA_V_Buffer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000888A8A82"
    )
        port map (
      I0 => rx_data_v_r(2),
      I1 => stage_2_count_value_r(0),
      I2 => stage_2_count_value_r(1),
      I3 => stage_2_count_value_r(2),
      I4 => stage_2_count_value_r(3),
      I5 => \stage_1_lane_mask_r_reg_n_0_[2]\,
      O => \PDU_DATA_V_Buffer[2]_i_1_n_0\
    );
\PDU_DATA_V_Buffer[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000A2A2A282"
    )
        port map (
      I0 => rx_data_v_r(3),
      I1 => stage_2_count_value_r(1),
      I2 => stage_2_count_value_r(0),
      I3 => stage_2_count_value_r(3),
      I4 => stage_2_count_value_r(2),
      I5 => \stage_1_lane_mask_r_reg_n_0_[3]\,
      O => \PDU_DATA_V_Buffer[3]_i_1_n_0\
    );
\PDU_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \PDU_DATA_V_Buffer[0]_i_1_n_0\,
      Q => \PDU_DATA_V_Buffer_reg[0]_0\(3),
      R => RESET
    );
\PDU_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \PDU_DATA_V_Buffer[1]_i_1_n_0\,
      Q => \PDU_DATA_V_Buffer_reg[0]_0\(2),
      R => RESET
    );
\PDU_DATA_V_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \PDU_DATA_V_Buffer[2]_i_1_n_0\,
      Q => \PDU_DATA_V_Buffer_reg[0]_0\(1),
      R => RESET
    );
\PDU_DATA_V_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \PDU_DATA_V_Buffer[3]_i_1_n_0\,
      Q => \PDU_DATA_V_Buffer_reg[0]_0\(0),
      R => RESET
    );
\PDU_ECP_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_ecp_r_reg[0]_srl2_n_0\,
      Q => \^d\(3),
      R => '0'
    );
\PDU_ECP_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_ecp_r_reg[1]_srl2_n_0\,
      Q => \^d\(2),
      R => '0'
    );
\PDU_ECP_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_ecp_r_reg[2]_srl2_n_0\,
      Q => \^d\(1),
      R => '0'
    );
\PDU_ECP_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_ecp_r_reg[3]_srl2_n_0\,
      Q => \^d\(0),
      R => '0'
    );
\PDU_PAD_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_pad_r_reg[0]_srl2_n_0\,
      Q => pdu_pad_i(0),
      R => '0'
    );
\PDU_PAD_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_pad_r_reg[1]_srl2_n_0\,
      Q => pdu_pad_i(1),
      R => '0'
    );
\PDU_PAD_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_pad_r_reg[2]_srl2_n_0\,
      Q => pdu_pad_i(2),
      R => '0'
    );
\PDU_PAD_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_pad_r_reg[3]_srl2_n_0\,
      Q => pdu_pad_i(3),
      R => '0'
    );
\PDU_SCP_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_scp_r(0),
      Q => \^pdu_scp_buffer_reg[0]_0\(3),
      R => '0'
    );
\PDU_SCP_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_scp_r(1),
      Q => \^pdu_scp_buffer_reg[0]_0\(2),
      R => '0'
    );
\PDU_SCP_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_scp_r(2),
      Q => \^pdu_scp_buffer_reg[0]_0\(1),
      R => '0'
    );
\PDU_SCP_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_scp_r(3),
      Q => \^pdu_scp_buffer_reg[0]_0\(0),
      R => '0'
    );
\UFC_DATA_V_Buffer[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AFAFAFBA"
    )
        port map (
      I0 => \stage_1_lane_mask_r_reg_n_0_[1]\,
      I1 => stage_2_count_value_r(3),
      I2 => stage_2_count_value_r(0),
      I3 => stage_2_count_value_r(1),
      I4 => stage_2_count_value_r(2),
      O => \UFC_DATA_V_Buffer[1]_i_1_n_0\
    );
\UFC_DATA_V_Buffer[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABFFEA"
    )
        port map (
      I0 => \stage_1_lane_mask_r_reg_n_0_[2]\,
      I1 => stage_2_count_value_r(3),
      I2 => stage_2_count_value_r(2),
      I3 => stage_2_count_value_r(1),
      I4 => stage_2_count_value_r(0),
      O => \UFC_DATA_V_Buffer[2]_i_1_n_0\
    );
\UFC_DATA_V_Buffer[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAFFABAA"
    )
        port map (
      I0 => \stage_1_lane_mask_r_reg_n_0_[3]\,
      I1 => stage_2_count_value_r(2),
      I2 => stage_2_count_value_r(3),
      I3 => stage_2_count_value_r(0),
      I4 => stage_2_count_value_r(1),
      O => \UFC_DATA_V_Buffer[3]_i_1_n_0\
    );
\UFC_DATA_V_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_lane_mask_c__0\(0),
      Q => \UFC_DATA_V_Buffer_reg[0]_0\(3),
      R => RESET
    );
\UFC_DATA_V_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_DATA_V_Buffer[1]_i_1_n_0\,
      Q => \UFC_DATA_V_Buffer_reg[0]_0\(2),
      R => RESET
    );
\UFC_DATA_V_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_DATA_V_Buffer[2]_i_1_n_0\,
      Q => \UFC_DATA_V_Buffer_reg[0]_0\(1),
      R => RESET
    );
\UFC_DATA_V_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_DATA_V_Buffer[3]_i_1_n_0\,
      Q => \UFC_DATA_V_Buffer_reg[0]_0\(0),
      R => RESET
    );
\UFC_MESSAGE_START_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg_n_0_[0]\,
      Q => ufc_message_start_i(0),
      R => RESET
    );
\UFC_MESSAGE_START_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg_n_0_[1]\,
      Q => ufc_message_start_i(1),
      R => RESET
    );
\UFC_MESSAGE_START_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg_n_0_[2]\,
      Q => ufc_message_start_i(2),
      R => RESET
    );
UFC_START_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \neqOp_inferred__0/i__n_0\,
      Q => ufc_start_i,
      R => RESET
    );
data_after_start_muxcy_0_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^pdu_scp_buffer_reg[0]_0\(3),
      O => S5_in
    );
data_after_start_muxcy_1_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^pdu_scp_buffer_reg[0]_0\(2),
      O => S3_in
    );
data_after_start_muxcy_2_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^pdu_scp_buffer_reg[0]_0\(1),
      O => S1_in
    );
data_after_start_muxcy_3_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^pdu_scp_buffer_reg[0]_0\(0),
      O => \PDU_SCP_Buffer_reg[3]_0\
    );
in_frame_muxcy_0_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d\(3),
      I1 => \^pdu_scp_buffer_reg[0]_0\(3),
      O => \PDU_ECP_Buffer_reg[0]_0\
    );
in_frame_muxcy_1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d\(2),
      I1 => \^pdu_scp_buffer_reg[0]_0\(2),
      O => \PDU_ECP_Buffer_reg[1]_0\
    );
in_frame_muxcy_2_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d\(1),
      I1 => \^pdu_scp_buffer_reg[0]_0\(1),
      O => \PDU_ECP_Buffer_reg[2]_0\
    );
in_frame_muxcy_3_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d\(0),
      I1 => \^pdu_scp_buffer_reg[0]_0\(0),
      O => \PDU_ECP_Buffer_reg[3]_0\
    );
load_ufc_control_code_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => neqOp,
      Q => load_ufc_control_code_r,
      R => RESET
    );
\neqOp_inferred__0/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \rx_suf_r_reg_n_0_[2]\,
      I1 => save_start_r,
      I2 => \rx_suf_r_reg_n_0_[1]\,
      I3 => \rx_suf_r_reg_n_0_[0]\,
      O => \neqOp_inferred__0/i__n_0\
    );
\rx_data_v_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_data_v_r_reg[0]_0\(3),
      Q => rx_data_v_r(0),
      R => RESET
    );
\rx_data_v_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_data_v_r_reg[0]_0\(2),
      Q => rx_data_v_r(1),
      R => RESET
    );
\rx_data_v_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_data_v_r_reg[0]_0\(1),
      Q => rx_data_v_r(2),
      R => RESET
    );
\rx_data_v_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_data_v_r_reg[0]_0\(0),
      Q => rx_data_v_r(3),
      R => RESET
    );
\rx_ecp_r_reg[0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_ECP_Buffer0,
      Q => \rx_ecp_r_reg[0]_srl2_n_0\
    );
\rx_ecp_r_reg[1]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_ECP_Buffer0_3,
      Q => \rx_ecp_r_reg[1]_srl2_n_0\
    );
\rx_ecp_r_reg[2]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_ECP_Buffer0_4,
      Q => \rx_ecp_r_reg[2]_srl2_n_0\
    );
\rx_ecp_r_reg[3]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => RX_ECP_Buffer0_5,
      Q => \rx_ecp_r_reg[3]_srl2_n_0\
    );
\rx_pad_r_reg[0]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => std_bool26_out,
      Q => \rx_pad_r_reg[0]_srl2_n_0\
    );
\rx_pad_r_reg[1]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => std_bool26_out_0,
      Q => \rx_pad_r_reg[1]_srl2_n_0\
    );
\rx_pad_r_reg[2]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => std_bool26_out_1,
      Q => \rx_pad_r_reg[2]_srl2_n_0\
    );
\rx_pad_r_reg[3]_srl2\: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => std_bool26_out_2,
      Q => \rx_pad_r_reg[3]_srl2_n_0\
    );
\rx_scp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_scp_r_reg[0]_0\(3),
      Q => rx_scp_r(0),
      R => '0'
    );
\rx_scp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_scp_r_reg[0]_0\(2),
      Q => rx_scp_r(1),
      R => '0'
    );
\rx_scp_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_scp_r_reg[0]_0\(1),
      Q => rx_scp_r(2),
      R => '0'
    );
\rx_scp_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_scp_r_reg[0]_0\(0),
      Q => rx_scp_r(3),
      R => '0'
    );
\rx_suf_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg[0]_0\(3),
      Q => \rx_suf_r_reg_n_0_[0]\,
      R => RESET
    );
\rx_suf_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg[0]_0\(2),
      Q => \rx_suf_r_reg_n_0_[1]\,
      R => RESET
    );
\rx_suf_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg[0]_0\(1),
      Q => \rx_suf_r_reg_n_0_[2]\,
      R => RESET
    );
\rx_suf_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg[0]_0\(0),
      Q => \rx_suf_r_reg_n_0_[3]\,
      R => RESET
    );
save_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_suf_r_reg_n_0_[3]\,
      Q => save_start_r,
      R => RESET
    );
\stage_1_count_value_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[0]_0\,
      Q => stage_1_count_value_r(0),
      R => RESET
    );
\stage_1_count_value_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[1]_0\,
      Q => stage_1_count_value_r(1),
      R => RESET
    );
\stage_1_count_value_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[2]_0\,
      Q => stage_1_count_value_r(2),
      R => RESET
    );
\stage_1_count_value_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_count_value_r_reg[3]_0\,
      Q => stage_1_count_value_r(3),
      R => RESET
    );
\stage_1_lane_mask_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_lane_mask_r_reg[1]_0\,
      Q => \stage_1_lane_mask_r_reg_n_0_[1]\,
      R => '0'
    );
\stage_1_lane_mask_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_lane_mask_r_reg[2]_0\,
      Q => \stage_1_lane_mask_r_reg_n_0_[2]\,
      R => '0'
    );
\stage_1_lane_mask_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_lane_mask_r_reg[3]_0\,
      Q => \stage_1_lane_mask_r_reg_n_0_[3]\,
      R => RESET
    );
\stage_2_count_value_r[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => load_ufc_control_code_r,
      I1 => stage_1_count_value_r(0),
      O => \stage_2_count_value_r[0]_i_1_n_0\
    );
\stage_2_count_value_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888888B8888"
    )
        port map (
      I0 => stage_1_count_value_r(1),
      I1 => load_ufc_control_code_r,
      I2 => stage_2_count_value_r(3),
      I3 => stage_2_count_value_r(1),
      I4 => stage_2_count_value_r(0),
      I5 => stage_2_count_value_r(2),
      O => \stage_2_count_value_r[1]_i_1_n_0\
    );
\stage_2_count_value_r[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8B888888"
    )
        port map (
      I0 => stage_1_count_value_r(2),
      I1 => load_ufc_control_code_r,
      I2 => stage_2_count_value_r(0),
      I3 => stage_2_count_value_r(2),
      I4 => stage_2_count_value_r(1),
      O => \stage_2_count_value_r[2]_i_1_n_0\
    );
\stage_2_count_value_r[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8B888888"
    )
        port map (
      I0 => stage_1_count_value_r(3),
      I1 => load_ufc_control_code_r,
      I2 => stage_2_count_value_r(0),
      I3 => stage_2_count_value_r(3),
      I4 => stage_2_count_value_r(1),
      O => \stage_2_count_value_r[3]_i_1_n_0\
    );
\stage_2_count_value_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[0]_i_1_n_0\,
      Q => stage_2_count_value_r(0),
      R => RESET
    );
\stage_2_count_value_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[1]_i_1_n_0\,
      Q => stage_2_count_value_r(1),
      R => RESET
    );
\stage_2_count_value_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[2]_i_1_n_0\,
      Q => stage_2_count_value_r(2),
      R => RESET
    );
\stage_2_count_value_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_count_value_r[3]_i_1_n_0\,
      Q => stage_2_count_value_r(3),
      R => RESET
    );
stage_2_lane_mask_c: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FE"
    )
        port map (
      I0 => stage_2_count_value_r(3),
      I1 => stage_2_count_value_r(2),
      I2 => stage_2_count_value_r(1),
      I3 => stage_2_count_value_r(0),
      O => \stage_2_lane_mask_c__0\(0)
    );
\ufc_barrel_shifter_control_i/BARREL_SHIFTER_CONTROL_Buffer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => ufc_message_start_i(1),
      I1 => ufc_message_start_i(2),
      I2 => ufc_message_start_i(0),
      O => \UFC_MESSAGE_START_Buffer_reg[1]_0\
    );
\ufc_barrel_shifter_control_i/BARREL_SHIFTER_CONTROL_Buffer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => ufc_message_start_i(1),
      I1 => ufc_message_start_i(2),
      I2 => ufc_message_start_i(0),
      O => \UFC_MESSAGE_START_Buffer_reg[1]_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_OUTPUT_MUX is
  port (
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    D : in STD_LOGIC_VECTOR ( 31 downto 0 );
    user_clk : in STD_LOGIC;
    UFC_OUTPUT_SELECT_Buffer : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MUXED_DATA_Buffer_reg[48]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[49]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[50]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[51]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[52]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[53]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[54]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[55]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[56]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[57]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[58]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[59]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[60]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[61]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[62]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[63]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[16]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[17]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[18]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[19]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[20]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[21]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[22]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[23]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[24]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[25]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[26]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[27]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[28]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[29]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[30]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[31]_0\ : in STD_LOGIC
  );
end aurora_rx_4l_64b_UFC_OUTPUT_MUX;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_OUTPUT_MUX is
begin
\MUXED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(31),
      Q => M_AXI_UFC_RX_TDATA(7),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(21),
      Q => M_AXI_UFC_RX_TDATA(13),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(20),
      Q => M_AXI_UFC_RX_TDATA(12),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(19),
      Q => M_AXI_UFC_RX_TDATA(11),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(18),
      Q => M_AXI_UFC_RX_TDATA(10),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(17),
      Q => M_AXI_UFC_RX_TDATA(9),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(16),
      Q => M_AXI_UFC_RX_TDATA(8),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[16]_0\,
      Q => M_AXI_UFC_RX_TDATA(23),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[17]_0\,
      Q => M_AXI_UFC_RX_TDATA(22),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[18]_0\,
      Q => M_AXI_UFC_RX_TDATA(21),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[19]_0\,
      Q => M_AXI_UFC_RX_TDATA(20),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(30),
      Q => M_AXI_UFC_RX_TDATA(6),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[20]_0\,
      Q => M_AXI_UFC_RX_TDATA(19),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[21]_0\,
      Q => M_AXI_UFC_RX_TDATA(18),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[22]_0\,
      Q => M_AXI_UFC_RX_TDATA(17),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[23]_0\,
      Q => M_AXI_UFC_RX_TDATA(16),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[24]_0\,
      Q => M_AXI_UFC_RX_TDATA(31),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[25]_0\,
      Q => M_AXI_UFC_RX_TDATA(30),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[26]_0\,
      Q => M_AXI_UFC_RX_TDATA(29),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[27]_0\,
      Q => M_AXI_UFC_RX_TDATA(28),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[28]_0\,
      Q => M_AXI_UFC_RX_TDATA(27),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[29]_0\,
      Q => M_AXI_UFC_RX_TDATA(26),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(29),
      Q => M_AXI_UFC_RX_TDATA(5),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[30]_0\,
      Q => M_AXI_UFC_RX_TDATA(25),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[31]_0\,
      Q => M_AXI_UFC_RX_TDATA(24),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(15),
      Q => M_AXI_UFC_RX_TDATA(39),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(14),
      Q => M_AXI_UFC_RX_TDATA(38),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(13),
      Q => M_AXI_UFC_RX_TDATA(37),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(12),
      Q => M_AXI_UFC_RX_TDATA(36),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(11),
      Q => M_AXI_UFC_RX_TDATA(35),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(10),
      Q => M_AXI_UFC_RX_TDATA(34),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(9),
      Q => M_AXI_UFC_RX_TDATA(33),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(8),
      Q => M_AXI_UFC_RX_TDATA(32),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(28),
      Q => M_AXI_UFC_RX_TDATA(4),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(7),
      Q => M_AXI_UFC_RX_TDATA(47),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(6),
      Q => M_AXI_UFC_RX_TDATA(46),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(5),
      Q => M_AXI_UFC_RX_TDATA(45),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(4),
      Q => M_AXI_UFC_RX_TDATA(44),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => M_AXI_UFC_RX_TDATA(43),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => M_AXI_UFC_RX_TDATA(42),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => M_AXI_UFC_RX_TDATA(41),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => M_AXI_UFC_RX_TDATA(40),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[48]_0\,
      Q => M_AXI_UFC_RX_TDATA(55),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[49]_0\,
      Q => M_AXI_UFC_RX_TDATA(54),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(27),
      Q => M_AXI_UFC_RX_TDATA(3),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[50]_0\,
      Q => M_AXI_UFC_RX_TDATA(53),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[51]_0\,
      Q => M_AXI_UFC_RX_TDATA(52),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[52]_0\,
      Q => M_AXI_UFC_RX_TDATA(51),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[53]_0\,
      Q => M_AXI_UFC_RX_TDATA(50),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[54]_0\,
      Q => M_AXI_UFC_RX_TDATA(49),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[55]_0\,
      Q => M_AXI_UFC_RX_TDATA(48),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[56]_0\,
      Q => M_AXI_UFC_RX_TDATA(63),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[57]_0\,
      Q => M_AXI_UFC_RX_TDATA(62),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[58]_0\,
      Q => M_AXI_UFC_RX_TDATA(61),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[59]_0\,
      Q => M_AXI_UFC_RX_TDATA(60),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(26),
      Q => M_AXI_UFC_RX_TDATA(2),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[60]_0\,
      Q => M_AXI_UFC_RX_TDATA(59),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[61]_0\,
      Q => M_AXI_UFC_RX_TDATA(58),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[62]_0\,
      Q => M_AXI_UFC_RX_TDATA(57),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[63]_0\,
      Q => M_AXI_UFC_RX_TDATA(56),
      R => UFC_OUTPUT_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(25),
      Q => M_AXI_UFC_RX_TDATA(1),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(24),
      Q => M_AXI_UFC_RX_TDATA(0),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(23),
      Q => M_AXI_UFC_RX_TDATA(15),
      R => '0'
    );
\MUXED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(22),
      Q => M_AXI_UFC_RX_TDATA(14),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_OUTPUT_SWITCH_CONTROL is
  port (
    \MUXED_DATA_Buffer_reg[16]\ : out STD_LOGIC;
    \UFC_OUTPUT_SELECT_Buffer_reg[7]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \MUXED_DATA_Buffer_reg[17]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[18]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[19]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[20]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[21]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[22]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[23]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[24]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[25]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[26]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[27]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[28]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[29]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[30]\ : out STD_LOGIC;
    \MUXED_DATA_Buffer_reg[31]\ : out STD_LOGIC;
    MUXED_DATA_Buffer : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    user_clk : in STD_LOGIC;
    \UFC_OUTPUT_SELECT_Buffer_reg[9]_0\ : in STD_LOGIC
  );
end aurora_rx_4l_64b_UFC_OUTPUT_SWITCH_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_OUTPUT_SWITCH_CONTROL is
  signal UFC_OUTPUT_SELECT_Buffer : STD_LOGIC_VECTOR ( 7 downto 6 );
  signal \UFC_OUTPUT_SELECT_Buffer[10]_i_1_n_0\ : STD_LOGIC;
  signal \UFC_OUTPUT_SELECT_Buffer[11]_i_1_n_0\ : STD_LOGIC;
  signal \UFC_OUTPUT_SELECT_Buffer[4]_i_1_n_0\ : STD_LOGIC;
  signal \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0\ : STD_LOGIC;
  signal \UFC_OUTPUT_SELECT_Buffer[7]_i_1_n_0\ : STD_LOGIC;
  signal \UFC_OUTPUT_SELECT_Buffer[8]_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \UFC_OUTPUT_SELECT_Buffer[10]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \UFC_OUTPUT_SELECT_Buffer[11]_i_1\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \UFC_OUTPUT_SELECT_Buffer[4]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \UFC_OUTPUT_SELECT_Buffer[5]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \UFC_OUTPUT_SELECT_Buffer[7]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \UFC_OUTPUT_SELECT_Buffer[8]_i_1\ : label is "soft_lutpair118";
begin
\MUXED_DATA_Buffer[16]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(15),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(15),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[16]\
    );
\MUXED_DATA_Buffer[17]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(14),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(14),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[17]\
    );
\MUXED_DATA_Buffer[18]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(13),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(13),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[18]\
    );
\MUXED_DATA_Buffer[19]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(12),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(12),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[19]\
    );
\MUXED_DATA_Buffer[20]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(11),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(11),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[20]\
    );
\MUXED_DATA_Buffer[21]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(10),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(10),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[21]\
    );
\MUXED_DATA_Buffer[22]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(9),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(9),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[22]\
    );
\MUXED_DATA_Buffer[23]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(8),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(8),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[23]\
    );
\MUXED_DATA_Buffer[24]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(7),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(7),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[24]\
    );
\MUXED_DATA_Buffer[25]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(6),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(6),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[25]\
    );
\MUXED_DATA_Buffer[26]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(5),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(5),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[26]\
    );
\MUXED_DATA_Buffer[27]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(4),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(4),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[27]\
    );
\MUXED_DATA_Buffer[28]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(3),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(3),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[28]\
    );
\MUXED_DATA_Buffer[29]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(2),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(2),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[29]\
    );
\MUXED_DATA_Buffer[30]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(1),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(1),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[30]\
    );
\MUXED_DATA_Buffer[31]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => MUXED_DATA_Buffer(0),
      I1 => UFC_OUTPUT_SELECT_Buffer(6),
      I2 => Q(0),
      I3 => UFC_OUTPUT_SELECT_Buffer(7),
      O => \MUXED_DATA_Buffer_reg[31]\
    );
\UFC_OUTPUT_SELECT_Buffer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"14"
    )
        port map (
      I0 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(2),
      I1 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(1),
      I2 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(0),
      O => \UFC_OUTPUT_SELECT_Buffer[10]_i_1_n_0\
    );
\UFC_OUTPUT_SELECT_Buffer[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(2),
      I1 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(0),
      O => \UFC_OUTPUT_SELECT_Buffer[11]_i_1_n_0\
    );
\UFC_OUTPUT_SELECT_Buffer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(1),
      I1 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(0),
      I2 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(2),
      O => \UFC_OUTPUT_SELECT_Buffer[4]_i_1_n_0\
    );
\UFC_OUTPUT_SELECT_Buffer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(1),
      I1 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(0),
      I2 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(2),
      O => \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0\
    );
\UFC_OUTPUT_SELECT_Buffer[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(1),
      I1 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(2),
      O => \UFC_OUTPUT_SELECT_Buffer[7]_i_1_n_0\
    );
\UFC_OUTPUT_SELECT_Buffer[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(0),
      I1 => \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(2),
      O => \UFC_OUTPUT_SELECT_Buffer[8]_i_1_n_0\
    );
\UFC_OUTPUT_SELECT_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer[10]_i_1_n_0\,
      Q => \UFC_OUTPUT_SELECT_Buffer_reg[7]_0\(1),
      R => '0'
    );
\UFC_OUTPUT_SELECT_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer[11]_i_1_n_0\,
      Q => \UFC_OUTPUT_SELECT_Buffer_reg[7]_0\(0),
      R => '0'
    );
\UFC_OUTPUT_SELECT_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer[4]_i_1_n_0\,
      Q => UFC_OUTPUT_SELECT_Buffer(7),
      R => '0'
    );
\UFC_OUTPUT_SELECT_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0\,
      Q => UFC_OUTPUT_SELECT_Buffer(6),
      R => '0'
    );
\UFC_OUTPUT_SELECT_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer[7]_i_1_n_0\,
      Q => \UFC_OUTPUT_SELECT_Buffer_reg[7]_0\(4),
      R => '0'
    );
\UFC_OUTPUT_SELECT_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer[8]_i_1_n_0\,
      Q => \UFC_OUTPUT_SELECT_Buffer_reg[7]_0\(3),
      R => '0'
    );
\UFC_OUTPUT_SELECT_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_OUTPUT_SELECT_Buffer_reg[9]_0\,
      Q => \UFC_OUTPUT_SELECT_Buffer_reg[7]_0\(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT is
  port (
    UFC_SRC_RDY_N_Buffer : out STD_LOGIC;
    UFC_EOF_N_Buffer : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    RESET : in STD_LOGIC;
    UFC_SRC_RDY_N_Buffer_reg_0 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    UFC_EOF_N_Buffer_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
end aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT is
begin
UFC_EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_EOF_N_Buffer_reg_0,
      Q => UFC_EOF_N_Buffer,
      R => '0'
    );
\UFC_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => Q(1),
      R => '0'
    );
\UFC_REM_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => Q(0),
      R => '0'
    );
UFC_SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_SRC_RDY_N_Buffer_reg_0,
      Q => UFC_SRC_RDY_N_Buffer,
      S => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL is
  port (
    \storage_count_r_reg[1]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \storage_count_r_reg[0]_0\ : out STD_LOGIC;
    ufc_output_select_c0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \storage_count_r_reg[0]_1\ : out STD_LOGIC;
    \storage_count_r_reg[0]_2\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \storage_count_r_reg[0]_3\ : out STD_LOGIC;
    \storage_count_r_reg[0]_4\ : out STD_LOGIC;
    \storage_count_r_reg[0]_5\ : out STD_LOGIC;
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \storage_count_r_reg[0]_6\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    stage_1_ufc_start_r : in STD_LOGIC
  );
end aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal storage_count_c : STD_LOGIC_VECTOR ( 0 to 2 );
  signal \storage_count_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \storage_count_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \^storage_count_r_reg[0]_1\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \UFC_REM_Buffer[1]_i_1\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of UFC_SRC_RDY_N_Buffer_i_1 : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \UFC_STORAGE_SELECT_Buffer[0]_i_2\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \UFC_STORAGE_SELECT_Buffer[6]_i_1\ : label is "soft_lutpair120";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
  \storage_count_r_reg[0]_1\ <= \^storage_count_r_reg[0]_1\;
UFC_EOF_N_Buffer_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => \^storage_count_r_reg[0]_1\,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \storage_count_r_reg[0]_3\
    );
\UFC_REM_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C3C35A69C2C15A69"
    )
        port map (
      I0 => \storage_count_r_reg[0]_6\(1),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \storage_count_r_reg[0]_6\(0),
      I4 => stage_1_ufc_start_r,
      I5 => \^q\(2),
      O => D(1)
    );
\UFC_REM_Buffer[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0EF00F0F"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => stage_1_ufc_start_r,
      I4 => \storage_count_r_reg[0]_6\(0),
      O => D(0)
    );
UFC_SRC_RDY_N_Buffer_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \storage_count_r_reg[0]_0\
    );
\UFC_STORAGE_SELECT_Buffer[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => ufc_output_select_c0_in(0)
    );
\UFC_STORAGE_SELECT_Buffer[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^storage_count_r_reg[0]_1\,
      I1 => \^q\(1),
      O => \storage_count_r_reg[0]_2\(1)
    );
\UFC_STORAGE_SELECT_Buffer[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^storage_count_r_reg[0]_1\,
      I1 => \^q\(0),
      O => \storage_count_r_reg[0]_2\(0)
    );
\UFC_STORAGE_SELECT_Buffer[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      O => \storage_count_r_reg[1]_0\
    );
\UFC_STORAGE_SELECT_Buffer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \^storage_count_r_reg[0]_1\,
      I1 => \^q\(2),
      I2 => \^q\(1),
      O => \storage_count_r_reg[0]_2\(5)
    );
\UFC_STORAGE_SELECT_Buffer[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^storage_count_r_reg[0]_1\,
      O => \storage_count_r_reg[0]_2\(4)
    );
\UFC_STORAGE_SELECT_Buffer[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"95"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \storage_count_r_reg[0]_4\
    );
\UFC_STORAGE_SELECT_Buffer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9F"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^storage_count_r_reg[0]_1\,
      O => \storage_count_r_reg[0]_2\(3)
    );
\UFC_STORAGE_SELECT_Buffer[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^storage_count_r_reg[0]_1\,
      O => \storage_count_r_reg[0]_2\(2)
    );
\UFC_STORAGE_SELECT_Buffer[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\(2),
      O => \storage_count_r_reg[0]_5\
    );
\storage_count_r[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BEC3AA00"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => \storage_count_r[0]_i_2_n_0\,
      I2 => \^q\(2),
      I3 => \storage_count_r_reg[0]_6\(2),
      I4 => \^storage_count_r_reg[0]_1\,
      O => storage_count_c(0)
    );
\storage_count_r[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EA80"
    )
        port map (
      I0 => \^q\(1),
      I1 => \storage_count_r_reg[0]_6\(0),
      I2 => \^q\(0),
      I3 => \storage_count_r_reg[0]_6\(1),
      O => \storage_count_r[0]_i_2_n_0\
    );
\storage_count_r[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FEE8"
    )
        port map (
      I0 => \storage_count_r[0]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => \storage_count_r_reg[0]_6\(2),
      I3 => \storage_count_r[0]_i_4_n_0\,
      I4 => stage_1_ufc_start_r,
      O => \^storage_count_r_reg[0]_1\
    );
\storage_count_r[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9FF6"
    )
        port map (
      I0 => \^q\(1),
      I1 => \storage_count_r_reg[0]_6\(1),
      I2 => \^q\(0),
      I3 => \storage_count_r_reg[0]_6\(0),
      O => \storage_count_r[0]_i_4_n_0\
    );
\storage_count_r[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CBBCBBCC88888888"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => \storage_count_r_reg[0]_6\(1),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \storage_count_r_reg[0]_6\(0),
      I5 => \^storage_count_r_reg[0]_1\,
      O => storage_count_c(1)
    );
\storage_count_r[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC88"
    )
        port map (
      I0 => stage_1_ufc_start_r,
      I1 => \storage_count_r_reg[0]_6\(0),
      I2 => \^q\(0),
      I3 => \^storage_count_r_reg[0]_1\,
      O => storage_count_c(2)
    );
\storage_count_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => storage_count_c(0),
      Q => \^q\(2),
      R => RESET
    );
\storage_count_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => storage_count_c(1),
      Q => \^q\(1),
      R => RESET
    );
\storage_count_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => storage_count_c(2),
      Q => \^q\(0),
      R => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_STORAGE_MUX is
  port (
    MUXED_DATA_Buffer : out STD_LOGIC_VECTOR ( 0 to 63 );
    UFC_STORAGE_SELECT_Buffer : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \MUXED_DATA_Buffer_reg[0]_0\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[1]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[2]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[3]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[4]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[5]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[6]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[7]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[8]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[9]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[10]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[11]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[12]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[13]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[14]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[15]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[16]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[17]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[18]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[19]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[20]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[21]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[22]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[23]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[24]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[25]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[26]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[27]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[28]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[29]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[30]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[31]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[32]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[33]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[34]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[35]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[36]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[37]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[38]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[39]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[40]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[41]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[42]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[43]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[44]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[45]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[46]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[47]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[48]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[49]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[50]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[51]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[52]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[53]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[54]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[55]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[56]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[57]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[58]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[59]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[60]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[61]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[62]_0\ : in STD_LOGIC;
    \MUXED_DATA_Buffer_reg[63]_0\ : in STD_LOGIC
  );
end aurora_rx_4l_64b_UFC_STORAGE_MUX;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_STORAGE_MUX is
begin
\MUXED_DATA_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[0]_0\,
      Q => MUXED_DATA_Buffer(0),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[10]_0\,
      Q => MUXED_DATA_Buffer(10),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[11]_0\,
      Q => MUXED_DATA_Buffer(11),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[12]_0\,
      Q => MUXED_DATA_Buffer(12),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[13]_0\,
      Q => MUXED_DATA_Buffer(13),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[14]_0\,
      Q => MUXED_DATA_Buffer(14),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[15]_0\,
      Q => MUXED_DATA_Buffer(15),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[16]_0\,
      Q => MUXED_DATA_Buffer(16),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[17]_0\,
      Q => MUXED_DATA_Buffer(17),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[18]_0\,
      Q => MUXED_DATA_Buffer(18),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[19]_0\,
      Q => MUXED_DATA_Buffer(19),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[1]_0\,
      Q => MUXED_DATA_Buffer(1),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[20]_0\,
      Q => MUXED_DATA_Buffer(20),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[21]_0\,
      Q => MUXED_DATA_Buffer(21),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[22]_0\,
      Q => MUXED_DATA_Buffer(22),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[23]_0\,
      Q => MUXED_DATA_Buffer(23),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[24]_0\,
      Q => MUXED_DATA_Buffer(24),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[25]_0\,
      Q => MUXED_DATA_Buffer(25),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[26]_0\,
      Q => MUXED_DATA_Buffer(26),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[27]_0\,
      Q => MUXED_DATA_Buffer(27),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[28]_0\,
      Q => MUXED_DATA_Buffer(28),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[29]_0\,
      Q => MUXED_DATA_Buffer(29),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[2]_0\,
      Q => MUXED_DATA_Buffer(2),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[30]_0\,
      Q => MUXED_DATA_Buffer(30),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[31]_0\,
      Q => MUXED_DATA_Buffer(31),
      R => UFC_STORAGE_SELECT_Buffer(2)
    );
\MUXED_DATA_Buffer_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[32]_0\,
      Q => MUXED_DATA_Buffer(32),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[33]_0\,
      Q => MUXED_DATA_Buffer(33),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[34]_0\,
      Q => MUXED_DATA_Buffer(34),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[35]_0\,
      Q => MUXED_DATA_Buffer(35),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[36]_0\,
      Q => MUXED_DATA_Buffer(36),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[37]_0\,
      Q => MUXED_DATA_Buffer(37),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[38]_0\,
      Q => MUXED_DATA_Buffer(38),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[39]_0\,
      Q => MUXED_DATA_Buffer(39),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[3]_0\,
      Q => MUXED_DATA_Buffer(3),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[40]_0\,
      Q => MUXED_DATA_Buffer(40),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[41]_0\,
      Q => MUXED_DATA_Buffer(41),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[42]_0\,
      Q => MUXED_DATA_Buffer(42),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[43]_0\,
      Q => MUXED_DATA_Buffer(43),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[44]_0\,
      Q => MUXED_DATA_Buffer(44),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[45]_0\,
      Q => MUXED_DATA_Buffer(45),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[46]_0\,
      Q => MUXED_DATA_Buffer(46),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[47]_0\,
      Q => MUXED_DATA_Buffer(47),
      R => UFC_STORAGE_SELECT_Buffer(1)
    );
\MUXED_DATA_Buffer_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[48]_0\,
      Q => MUXED_DATA_Buffer(48),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[49]_0\,
      Q => MUXED_DATA_Buffer(49),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[4]_0\,
      Q => MUXED_DATA_Buffer(4),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[50]_0\,
      Q => MUXED_DATA_Buffer(50),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[51]_0\,
      Q => MUXED_DATA_Buffer(51),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[52]_0\,
      Q => MUXED_DATA_Buffer(52),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[53]_0\,
      Q => MUXED_DATA_Buffer(53),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[54]_0\,
      Q => MUXED_DATA_Buffer(54),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[55]_0\,
      Q => MUXED_DATA_Buffer(55),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[56]_0\,
      Q => MUXED_DATA_Buffer(56),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[57]_0\,
      Q => MUXED_DATA_Buffer(57),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[58]_0\,
      Q => MUXED_DATA_Buffer(58),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[59]_0\,
      Q => MUXED_DATA_Buffer(59),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[5]_0\,
      Q => MUXED_DATA_Buffer(5),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[60]_0\,
      Q => MUXED_DATA_Buffer(60),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[61]_0\,
      Q => MUXED_DATA_Buffer(61),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[62]_0\,
      Q => MUXED_DATA_Buffer(62),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[63]_0\,
      Q => MUXED_DATA_Buffer(63),
      R => UFC_STORAGE_SELECT_Buffer(0)
    );
\MUXED_DATA_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[6]_0\,
      Q => MUXED_DATA_Buffer(6),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[7]_0\,
      Q => MUXED_DATA_Buffer(7),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[8]_0\,
      Q => MUXED_DATA_Buffer(8),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
\MUXED_DATA_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \MUXED_DATA_Buffer_reg[9]_0\,
      Q => MUXED_DATA_Buffer(9),
      R => UFC_STORAGE_SELECT_Buffer(3)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL is
  port (
    UFC_STORAGE_SELECT_Buffer : out STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 5 downto 0 );
    user_clk : in STD_LOGIC;
    ufc_output_select_c0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
    \UFC_STORAGE_SELECT_Buffer_reg[1]_0\ : in STD_LOGIC;
    \UFC_STORAGE_SELECT_Buffer_reg[6]_0\ : in STD_LOGIC;
    \UFC_STORAGE_SELECT_Buffer_reg[9]_0\ : in STD_LOGIC;
    \UFC_STORAGE_SELECT_Buffer_reg[9]_1\ : in STD_LOGIC
  );
end aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL;

architecture STRUCTURE of aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL is
  signal \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\ : STD_LOGIC;
begin
\UFC_STORAGE_SELECT_Buffer[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \UFC_STORAGE_SELECT_Buffer_reg[9]_1\,
      O => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ufc_output_select_c0_in(0),
      Q => UFC_STORAGE_SELECT_Buffer(9),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => UFC_STORAGE_SELECT_Buffer(1),
      R => '0'
    );
\UFC_STORAGE_SELECT_Buffer_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => UFC_STORAGE_SELECT_Buffer(0),
      R => '0'
    );
\UFC_STORAGE_SELECT_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_STORAGE_SELECT_Buffer_reg[1]_0\,
      Q => UFC_STORAGE_SELECT_Buffer(8),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(5),
      Q => UFC_STORAGE_SELECT_Buffer(7),
      R => '0'
    );
\UFC_STORAGE_SELECT_Buffer_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(4),
      Q => UFC_STORAGE_SELECT_Buffer(6),
      R => '0'
    );
\UFC_STORAGE_SELECT_Buffer_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_STORAGE_SELECT_Buffer_reg[6]_0\,
      Q => UFC_STORAGE_SELECT_Buffer(5),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
\UFC_STORAGE_SELECT_Buffer_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => UFC_STORAGE_SELECT_Buffer(4),
      R => '0'
    );
\UFC_STORAGE_SELECT_Buffer_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => UFC_STORAGE_SELECT_Buffer(3),
      R => '0'
    );
\UFC_STORAGE_SELECT_Buffer_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \UFC_STORAGE_SELECT_Buffer_reg[9]_0\,
      Q => UFC_STORAGE_SELECT_Buffer(2),
      R => \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_VALID_DATA_COUNTER is
  port (
    \COUNT_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
end aurora_rx_4l_64b_VALID_DATA_COUNTER;

architecture STRUCTURE of aurora_rx_4l_64b_VALID_DATA_COUNTER is
  signal plusOp : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \COUNT_Buffer[0]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \COUNT_Buffer[1]_i_1\ : label is "soft_lutpair121";
begin
\COUNT_Buffer[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => Q(0),
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(3),
      O => plusOp(2)
    );
\COUNT_Buffer[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7EE8"
    )
        port map (
      I0 => Q(3),
      I1 => Q(0),
      I2 => Q(1),
      I3 => Q(2),
      O => plusOp(1)
    );
\COUNT_Buffer[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => Q(1),
      I1 => Q(2),
      I2 => Q(0),
      I3 => Q(3),
      O => plusOp(0)
    );
\COUNT_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => plusOp(2),
      Q => \COUNT_Buffer_reg[0]_0\(2),
      R => RESET
    );
\COUNT_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => plusOp(1),
      Q => \COUNT_Buffer_reg[0]_0\(1),
      R => RESET
    );
\COUNT_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => plusOp(0),
      Q => \COUNT_Buffer_reg[0]_0\(0),
      R => RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_VALID_DATA_COUNTER_5 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    stage_2_start_with_data_r : in STD_LOGIC;
    stage_3_end_storage_r : in STD_LOGIC;
    \storage_count_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RESET : in STD_LOGIC;
    \COUNT_Buffer_reg[0]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_VALID_DATA_COUNTER_5 : entity is "aurora_rx_4l_64b_VALID_DATA_COUNTER";
end aurora_rx_4l_64b_VALID_DATA_COUNTER_5;

architecture STRUCTURE of aurora_rx_4l_64b_VALID_DATA_COUNTER_5 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\COUNT_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \COUNT_Buffer_reg[0]_0\(2),
      Q => \^q\(2),
      R => RESET
    );
\COUNT_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \COUNT_Buffer_reg[0]_0\(1),
      Q => \^q\(1),
      R => RESET
    );
\COUNT_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \COUNT_Buffer_reg[0]_0\(0),
      Q => \^q\(0),
      R => RESET
    );
\storage_count_r[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEE0111EFFF1000"
    )
        port map (
      I0 => stage_2_start_with_data_r,
      I1 => stage_3_end_storage_r,
      I2 => \^q\(0),
      I3 => \storage_count_r_reg[1]\(0),
      I4 => \^q\(1),
      I5 => \storage_count_r_reg[1]\(1),
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_cdc_sync is
  port (
    \out\ : out STD_LOGIC;
    HPCNT_RESET : out STD_LOGIC;
    GT_RESET : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    \hotplug_count_synth.count_for_reset_r_reg[0]\ : in STD_LOGIC
  );
end aurora_rx_4l_64b_cdc_sync;

architecture STRUCTURE of aurora_rx_4l_64b_cdc_sync is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ <= GT_RESET;
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
\hotplug_count_synth.count_for_reset_r[0]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      I1 => \hotplug_count_synth.count_for_reset_r_reg[0]\,
      O => HPCNT_RESET
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_cdc_sync_0 is
  port (
    \out\ : out STD_LOGIC;
    RX_SYSTEM_RESET : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_cdc_sync_0 : entity is "aurora_rx_4l_64b_cdc_sync";
end aurora_rx_4l_64b_cdc_sync_0;

architecture STRUCTURE of aurora_rx_4l_64b_cdc_sync_0 is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ <= RX_SYSTEM_RESET;
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_cdc_sync_1 is
  port (
    \out\ : out STD_LOGIC;
    RX_SYSTEM_RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_cdc_sync_1 : entity is "aurora_rx_4l_64b_cdc_sync";
end aurora_rx_4l_64b_cdc_sync_1;

architecture STRUCTURE of aurora_rx_4l_64b_cdc_sync_1 is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ <= RX_SYSTEM_RESET;
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_cdc_sync_23 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC;
    in0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    reset_time_out_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC;
    reset_time_out_reg_0 : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_1\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_2\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_3\ : in STD_LOGIC;
    \FSM_sequential_rx_state_reg[0]_4\ : in STD_LOGIC;
    rxresetdone_s3 : in STD_LOGIC;
    reset_time_out_reg_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_cdc_sync_23 : entity is "aurora_rx_4l_64b_cdc_sync";
end aurora_rx_4l_64b_cdc_sync_23;

architecture STRUCTURE of aurora_rx_4l_64b_cdc_sync_23 is
  signal \FSM_sequential_rx_state[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_7_n_0\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  signal reset_time_out_i_2_n_0 : STD_LOGIC;
  signal reset_time_out_i_3_n_0 : STD_LOGIC;
  signal reset_time_out_i_4_n_0 : STD_LOGIC;
  signal reset_time_out_i_5_n_0 : STD_LOGIC;
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ <= in0;
\FSM_sequential_rx_state[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]\,
      I1 => \FSM_sequential_rx_state[3]_i_4_n_0\,
      I2 => reset_time_out_reg_0,
      I3 => \FSM_sequential_rx_state_reg[0]_0\,
      I4 => \FSM_sequential_rx_state[3]_i_7_n_0\,
      O => E(0)
    );
\FSM_sequential_rx_state[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222000003000000"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_1\,
      I1 => \FSM_sequential_rx_state_reg[0]_2\,
      I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      I3 => \FSM_sequential_rx_state_reg[0]_3\,
      I4 => Q(0),
      I5 => Q(1),
      O => \FSM_sequential_rx_state[3]_i_4_n_0\
    );
\FSM_sequential_rx_state[3]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88880300"
    )
        port map (
      I0 => reset_time_out_i_3_n_0,
      I1 => Q(1),
      I2 => Q(2),
      I3 => \FSM_sequential_rx_state_reg[0]_4\,
      I4 => Q(0),
      O => \FSM_sequential_rx_state[3]_i_7_n_0\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\
    );
reset_time_out_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEEEFFFFFEEE0000"
    )
        port map (
      I0 => reset_time_out_reg_0,
      I1 => reset_time_out_i_2_n_0,
      I2 => Q(1),
      I3 => reset_time_out_i_3_n_0,
      I4 => reset_time_out_i_4_n_0,
      I5 => reset_time_out_reg_1,
      O => \FSM_sequential_rx_state_reg[1]\
    );
reset_time_out_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => Q(1),
      I1 => \FSM_sequential_rx_state_reg[0]_3\,
      I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      I3 => Q(3),
      I4 => Q(2),
      O => reset_time_out_i_2_n_0
    );
reset_time_out_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B08"
    )
        port map (
      I0 => rxresetdone_s3,
      I1 => Q(2),
      I2 => Q(3),
      I3 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => reset_time_out_i_3_n_0
    );
reset_time_out_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00333333FF00FC88"
    )
        port map (
      I0 => reset_time_out_reg,
      I1 => Q(2),
      I2 => reset_time_out_i_5_n_0,
      I3 => Q(0),
      I4 => Q(1),
      I5 => Q(3),
      O => reset_time_out_i_4_n_0
    );
reset_time_out_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_sequential_rx_state_reg[0]_3\,
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => reset_time_out_i_5_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_cdc_sync_24 is
  port (
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_cdc_sync_24 : entity is "aurora_rx_4l_64b_cdc_sync";
end aurora_rx_4l_64b_cdc_sync_24;

architecture STRUCTURE of aurora_rx_4l_64b_cdc_sync_24 is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_cdc_sync_26 is
  port (
    \out\ : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_cdc_sync_26 : entity is "aurora_rx_4l_64b_cdc_sync";
end aurora_rx_4l_64b_cdc_sync_26;

architecture STRUCTURE of aurora_rx_4l_64b_cdc_sync_26 is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\
    );
\mmcm_lock_count[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_cdc_sync_31 is
  port (
    \out\ : out STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_cdc_sync_31 : entity is "aurora_rx_4l_64b_cdc_sync";
end aurora_rx_4l_64b_cdc_sync_31;

architecture STRUCTURE of aurora_rx_4l_64b_cdc_sync_31 is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '1',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2\ is
  port (
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[23]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[25]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rx_cc_extend_r2 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    \hotplug_count_synth.count_for_reset_r_reg\ : in STD_LOGIC_VECTOR ( 25 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  signal \hotplug_count_synth.count_for_reset_r[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_3__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_5__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_6__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_2__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_3__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_4__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_5__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_2__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_3__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_4__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_5__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_2__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_3__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_4__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_5__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_2__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_3__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_4__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_5__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_2__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_3__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_4__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_5__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_3\ : STD_LOGIC;
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2\ : label is 11;
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
\hotplug_count_synth.count_for_reset_r[0]_i_2__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_2__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_4__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_6__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_6__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_2__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_4__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_2__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_4__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_2__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_4__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_2__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_2__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_4__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_2__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_4__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \hotplug_count_synth.count_for_reset_r[0]_i_2__1_n_0\,
      O(3 downto 0) => O(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[0]_i_3__2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[0]_i_4__2_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[0]_i_5__2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[0]_i_6__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[15]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[12]_i_2__2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[12]_i_3__2_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[12]_i_4__2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[12]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[19]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[16]_i_2__2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[16]_i_3__2_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[16]_i_4__2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[16]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[23]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[20]_i_2__2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[20]_i_3__2_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[20]_i_4__2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[20]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_0\,
      CO(3 downto 1) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[25]\(1 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \hotplug_count_synth.count_for_reset_r[24]_i_2__2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[24]_i_3__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[7]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[4]_i_2__2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[4]_i_3__2_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[4]_i_4__2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[4]_i_5__2_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[11]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[8]_i_2__2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[8]_i_3__2_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[8]_i_4__2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[8]_i_5__2_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_10\ is
  port (
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[23]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[25]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rx_cc_extend_r2 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    \hotplug_count_synth.count_for_reset_r_reg\ : in STD_LOGIC_VECTOR ( 25 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_10\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_10\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_10\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  signal \hotplug_count_synth.count_for_reset_r[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_5__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_6__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_2__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_3__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_4__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_5__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_2__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_3__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_4__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_5__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_2__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_3__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_4__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_5__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_2__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_3__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_4__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_5__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_2__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_3__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_4__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_5__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_3\ : STD_LOGIC;
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1\ : label is 11;
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
\hotplug_count_synth.count_for_reset_r[0]_i_2__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_2__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_4__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_6__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_6__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_2__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_4__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_2__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_4__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_2__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_4__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_2__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_2__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_4__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_2__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_4__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \hotplug_count_synth.count_for_reset_r[0]_i_2__0_n_0\,
      O(3 downto 0) => O(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[0]_i_3__1_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[0]_i_4__1_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[0]_i_5__1_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[0]_i_6__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[15]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[12]_i_2__1_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[12]_i_3__1_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[12]_i_4__1_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[12]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[19]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[16]_i_2__1_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[16]_i_3__1_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[16]_i_4__1_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[16]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[23]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[20]_i_2__1_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[20]_i_3__1_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[20]_i_4__1_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[20]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_0\,
      CO(3 downto 1) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[25]\(1 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \hotplug_count_synth.count_for_reset_r[24]_i_2__1_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[24]_i_3__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[7]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[4]_i_2__1_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[4]_i_3__1_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[4]_i_4__1_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[4]_i_5__1_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[11]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[8]_i_2__1_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[8]_i_3__1_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[8]_i_4__1_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[8]_i_5__1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_15\ is
  port (
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[23]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[25]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rx_cc_extend_r2 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    \hotplug_count_synth.count_for_reset_r_reg\ : in STD_LOGIC_VECTOR ( 25 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_15\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_15\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_15\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  signal \hotplug_count_synth.count_for_reset_r[0]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_3__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_4__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_5__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_3__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_4__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_5__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_2__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_3__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_4__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_5__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_2__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_3__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_5__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_3__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_4__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_5__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_3\ : STD_LOGIC;
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0\ : label is 11;
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
\hotplug_count_synth.count_for_reset_r[0]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_4__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_6__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_2__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_4__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_2__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_4__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_2__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_4__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_2__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_2__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_4__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_2__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_4__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \hotplug_count_synth.count_for_reset_r[0]_i_2_n_0\,
      O(3 downto 0) => O(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[0]_i_3__0_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[0]_i_4__0_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[0]_i_5__0_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[0]_i_6__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[15]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[12]_i_2__0_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[12]_i_3__0_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[12]_i_4__0_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[12]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[19]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[16]_i_2__0_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[16]_i_3__0_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[16]_i_4__0_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[16]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[23]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[20]_i_2__0_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[20]_i_3__0_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[20]_i_4__0_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[20]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_0\,
      CO(3 downto 1) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[25]\(1 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \hotplug_count_synth.count_for_reset_r[24]_i_2__0_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[24]_i_3__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[7]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[4]_i_2__0_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[4]_i_3__0_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[4]_i_4__0_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[4]_i_5__0_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[11]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[8]_i_2__0_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[8]_i_3__0_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[8]_i_4__0_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[8]_i_5__0_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_20\ is
  port (
    O : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[23]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \hotplug_count_synth.count_for_reset_r_reg[25]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    rx_cc_extend_r2 : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    \hotplug_count_synth.count_for_reset_r_reg\ : in STD_LOGIC_VECTOR ( 25 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_20\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_20\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_20\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  signal \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[0]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[20]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[24]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \hotplug_count_synth.count_for_reset_r_reg[8]_i_1\ : label is 11;
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
\hotplug_count_synth.count_for_reset_r[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0\
    );
\hotplug_count_synth.count_for_reset_r[0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[12]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[16]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[20]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[24]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0\
    );
\hotplug_count_synth.count_for_reset_r[8]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      O => \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0\,
      O(3 downto 0) => O(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[15]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[19]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[23]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0\,
      CO(3 downto 1) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[25]\(1 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[7]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0\
    );
\hotplug_count_synth.count_for_reset_r_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0\,
      CO(3) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0\,
      CO(2) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1\,
      CO(1) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2\,
      CO(0) => \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \hotplug_count_synth.count_for_reset_r_reg[11]\(3 downto 0),
      S(3) => \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0\,
      S(2) => \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0\,
      S(1) => \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0\,
      S(0) => \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_21\ is
  port (
    \out\ : out STD_LOGIC;
    gtrxreset_i : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_21\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_21\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_21\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => gtrxreset_i,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_22\ is
  port (
    \out\ : out STD_LOGIC;
    fsm_gt_rx_reset_t : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_22\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_22\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_22\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => fsm_gt_rx_reset_t,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_25\ is
  port (
    \out\ : out STD_LOGIC;
    rxfsm_rxresetdone_r : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_25\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_25\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_25\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rxfsm_rxresetdone_r,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_27\ is
  port (
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_27\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_27\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_27\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => '0',
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_28\ is
  port (
    \out\ : out STD_LOGIC;
    run_phase_alignment_int : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_28\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_28\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_28\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => run_phase_alignment_int,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_29\ is
  port (
    \out\ : out STD_LOGIC;
    rx_fsm_reset_done_int : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_29\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_29\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_29\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_fsm_reset_done_int,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_30\ is
  port (
    rxpmaresetdone_i : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_30\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_30\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_30\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rxpmaresetdone_i,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_32\ is
  port (
    \out\ : out STD_LOGIC;
    time_out_wait_bypass : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_32\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_32\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_32\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => time_out_wait_bypass,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_36\ is
  port (
    \out\ : out STD_LOGIC;
    link_reset_r : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_36\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_36\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_36\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \aurora_rx_4l_64b_cdc_sync__parameterized2_37\ is
  port (
    \out\ : out STD_LOGIC;
    tx_lock_comb_r : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \aurora_rx_4l_64b_cdc_sync__parameterized2_37\ : entity is "aurora_rx_4l_64b_cdc_sync";
end \aurora_rx_4l_64b_cdc_sync__parameterized2_37\;

architecture STRUCTURE of \aurora_rx_4l_64b_cdc_sync__parameterized2_37\ is
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\ : signal is "true";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\ : STD_LOGIC;
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : STD_LOGIC;
  attribute async_reg : string;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "true";
  attribute shift_extract : string;
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\ : signal is "no";
  signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : STD_LOGIC;
  attribute async_reg of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "true";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\ : signal is "no";
  attribute KEEP : string;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\ : label is "no";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\ : label is "no";
  attribute ASYNC_REG_boolean of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is std.standard.true;
  attribute KEEP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "yes";
  attribute shift_extract of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\ : label is "no";
begin
  \out\ <= \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => tx_lock_comb_r,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from\,
      O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      R => '0'
    );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5\,
      Q => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_gt is
  port (
    gt0_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_0 : out STD_LOGIC;
    CHBONDDONE_OUT : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gthe2_i_1 : out STD_LOGIC;
    gthe2_i_2 : out STD_LOGIC;
    gthe2_i_3 : out STD_LOGIC;
    gthe2_i_4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg : out STD_LOGIC;
    hard_err_flop_r0 : out STD_LOGIC;
    gthe2_i_5 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC_VECTOR ( 0 to 0 );
    RXP : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_refclk1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    fsm_gt_rx_reset_t : in STD_LOGIC;
    gt_qpllclk_quad2_in : in STD_LOGIC;
    gt_qpllrefclk_quad2_in : in STD_LOGIC;
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_0 : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_0 : in STD_LOGIC;
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    gtp_rx_reset_i_0 : in STD_LOGIC;
    comma_over_two_cycles_r : in STD_LOGIC;
    first_v_received_r : in STD_LOGIC;
    bucket_full_r : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
end aurora_rx_4l_64b_gt;

architecture STRUCTURE of aurora_rx_4l_64b_gt is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal D_0 : STD_LOGIC;
  signal GT0_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal flag2 : STD_LOGIC;
  signal flag2_i_2_n_0 : STD_LOGIC;
  signal flag_i_1_n_0 : STD_LOGIC;
  signal \^gt0_rx_disp_err_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt0_rx_not_in_table_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt0_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^gthe2_i_0\ : STD_LOGIC;
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_112 : STD_LOGIC;
  signal gthe2_i_n_113 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_120 : STD_LOGIC;
  signal gthe2_i_n_121 : STD_LOGIC;
  signal gthe2_i_n_122 : STD_LOGIC;
  signal gthe2_i_n_123 : STD_LOGIC;
  signal gthe2_i_n_124 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_45 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_5 : STD_LOGIC;
  signal gthe2_i_n_54 : STD_LOGIC;
  signal gthe2_i_n_6 : STD_LOGIC;
  signal rx_char_is_k_i_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_data_i_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg6 : label is "VCC:CE GND:R";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg6 : label is "VCC:CE GND:R";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  D(1 downto 0) <= \^d\(1 downto 0);
  gt0_rx_disp_err_out(1 downto 0) <= \^gt0_rx_disp_err_out\(1 downto 0);
  gt0_rx_not_in_table_out(1 downto 0) <= \^gt0_rx_not_in_table_out\(1 downto 0);
  gt0_rxbufstatus_out(2 downto 0) <= \^gt0_rxbufstatus_out\(2 downto 0);
  gthe2_i_0 <= \^gthe2_i_0\;
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D_0,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
flag2_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => flag2_i_2_n_0
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag2_i_2_n_0,
      Q => flag2,
      R => flag2_reg_0
    );
flag_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D_0,
      O => flag_i_1_n_0
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag_i_1_n_0,
      Q => D_0,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => gt0_cplllock_out,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT0_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN => DRPEN_IN,
      DRPRDY => DRPRDY_OUT,
      DRPWE => DRPWE_IN,
      EYESCANDATAERROR => gt0_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt0_eyescanreset_in,
      EYESCANTRIGGER => gt0_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => RXN(0),
      GTHRXP => RXP(0),
      GTHTXN => gthe2_i_n_5,
      GTHTXP => gthe2_i_n_6,
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => SR(0),
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => fsm_gt_rx_reset_t,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad2_in,
      QPLLREFCLK => gt_qpllrefclk_quad2_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => gt0_rxbufreset_in,
      RXBUFSTATUS(2 downto 0) => \^gt0_rxbufstatus_out\(2 downto 0),
      RXBYTEISALIGNED => gt0_rxbyteisaligned_out,
      RXBYTEREALIGN => \^gthe2_i_0\,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => gt0_rxcdrhold_in,
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => gt0_rxcdrovrden_in,
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => CHBONDDONE_OUT,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1 downto 0) => \^d\(1 downto 0),
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1 downto 0) => rx_char_is_k_i_0(1 downto 0),
      RXCHBONDEN => '1',
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"001",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => gthe2_i_n_120,
      RXCHBONDO(3) => gthe2_i_n_121,
      RXCHBONDO(2) => gthe2_i_n_122,
      RXCHBONDO(1) => gthe2_i_n_123,
      RXCHBONDO(0) => gthe2_i_n_124,
      RXCHBONDSLAVE => '1',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt0_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15 downto 0) => rx_data_i_0(15 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => gt0_rxdfelpmreset_in,
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1 downto 0) => \^gt0_rx_disp_err_out\(1 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => gt0_rxlpmen_in,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => ena_comma_align_i_0,
      RXMONITOROUT(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1 downto 0) => \^gt0_rx_not_in_table_out\(1 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => ena_comma_align_i_0,
      RXPCSRESET => gt0_rxpcsreset_in,
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => gt0_rxpmareset_in,
      RXPMARESETDONE => gt0_rxpmaresetdone_out,
      RXPOLARITY => rx_polarity_i_0,
      RXPRBSCNTRESET => gt0_rxprbscntreset_in,
      RXPRBSERR => gt0_rxprbserr_out,
      RXPRBSSEL(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt0_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1) => gthe2_i_n_112,
      TXBUFSTATUS(0) => gthe2_i_n_113,
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 0) => B"00000000",
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gthe2_i_n_45,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => '0',
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gthe2_i_n_54,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => '1',
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
hard_err_flop_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^gt0_rxbufstatus_out\(2),
      I1 => bucket_full_r,
      I2 => \^gthe2_i_0\,
      O => hard_err_flop_r0
    );
left_aligned_r_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFBEFFF"
    )
        port map (
      I0 => first_v_received_r,
      I1 => \^d\(0),
      I2 => \^d\(1),
      I3 => rx_char_is_k_i_0(1),
      I4 => rx_char_is_k_i_0(0),
      O => first_v_received_r_reg
    );
reset_count_r_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \^gt0_rx_not_in_table_out\(1),
      I1 => \^gt0_rx_disp_err_out\(1),
      I2 => gtp_rx_reset_i_0,
      I3 => comma_over_two_cycles_r,
      I4 => \^gt0_rx_not_in_table_out\(0),
      I5 => \^gt0_rx_disp_err_out\(0),
      O => gthe2_i_3
    );
\soft_err_r[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt0_rx_not_in_table_out\(0),
      I1 => \^gt0_rx_disp_err_out\(0),
      O => gthe2_i_4(1)
    );
\soft_err_r[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt0_rx_not_in_table_out\(1),
      I1 => \^gt0_rx_disp_err_out\(1),
      O => gthe2_i_4(0)
    );
\word_aligned_control_bits_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_0(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_0(1),
      O => gthe2_i_2
    );
\word_aligned_control_bits_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_0(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_0(0),
      O => gthe2_i_1
    );
\word_aligned_data_r[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(7),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(15),
      O => gthe2_i_6(7)
    );
\word_aligned_data_r[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(13),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(5),
      O => gthe2_i_5(5)
    );
\word_aligned_data_r[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(12),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(4),
      O => gthe2_i_5(4)
    );
\word_aligned_data_r[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(11),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(3),
      O => gthe2_i_5(3)
    );
\word_aligned_data_r[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(10),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(2),
      O => gthe2_i_5(2)
    );
\word_aligned_data_r[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(9),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(1),
      O => gthe2_i_5(1)
    );
\word_aligned_data_r[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(8),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(0),
      O => gthe2_i_5(0)
    );
\word_aligned_data_r[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(6),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(14),
      O => gthe2_i_6(6)
    );
\word_aligned_data_r[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(5),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(13),
      O => gthe2_i_6(5)
    );
\word_aligned_data_r[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(4),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(12),
      O => gthe2_i_6(4)
    );
\word_aligned_data_r[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(3),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(11),
      O => gthe2_i_6(3)
    );
\word_aligned_data_r[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(2),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(10),
      O => gthe2_i_6(2)
    );
\word_aligned_data_r[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(9),
      O => gthe2_i_6(1)
    );
\word_aligned_data_r[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(8),
      O => gthe2_i_6(0)
    );
\word_aligned_data_r[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(15),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(7),
      O => gthe2_i_5(7)
    );
\word_aligned_data_r[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_0(14),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_0(6),
      O => gthe2_i_5(6)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_gt_33 is
  port (
    gt1_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_0 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE1 : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxpmaresetdone_out : out STD_LOGIC;
    gt1_rxprbserr_out : out STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RXCHBONDO : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gthe2_i_2 : out STD_LOGIC;
    gthe2_i_3 : out STD_LOGIC;
    gthe2_i_4 : out STD_LOGIC;
    gthe2_i_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg : out STD_LOGIC;
    hard_err_flop_r0_0 : out STD_LOGIC;
    gthe2_i_6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_7 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC_VECTOR ( 0 to 0 );
    RXP : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_refclk1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    fsm_gt_rx_reset_t : in STD_LOGIC;
    gt_qpllclk_quad2_in : in STD_LOGIC;
    gt_qpllrefclk_quad2_in : in STD_LOGIC;
    gt1_rxbufreset_in : in STD_LOGIC;
    gt1_rxcdrhold_in : in STD_LOGIC;
    gt1_rxcdrovrden_in : in STD_LOGIC;
    en_chan_sync_i : in STD_LOGIC;
    gt1_rxdfelpmreset_in : in STD_LOGIC;
    gt1_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_1 : in STD_LOGIC;
    gt1_rxpcsreset_in : in STD_LOGIC;
    gt1_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_1 : in STD_LOGIC;
    gt1_rxprbscntreset_in : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    gtp_rx_reset_i_1 : in STD_LOGIC;
    comma_over_two_cycles_r_3 : in STD_LOGIC;
    first_v_received_r_4 : in STD_LOGIC;
    bucket_full_r_5 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_gt_33 : entity is "aurora_rx_4l_64b_gt";
end aurora_rx_4l_64b_gt_33;

architecture STRUCTURE of aurora_rx_4l_64b_gt_33 is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D : STD_LOGIC;
  signal GT1_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal flag2_i_1_n_0 : STD_LOGIC;
  signal flag2_reg_n_0 : STD_LOGIC;
  signal \flag_i_1__0_n_0\ : STD_LOGIC;
  signal \^gt1_rx_disp_err_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt1_rx_not_in_table_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt1_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^gthe2_i_0\ : STD_LOGIC;
  signal \^gthe2_i_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_112 : STD_LOGIC;
  signal gthe2_i_n_113 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_45 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_5 : STD_LOGIC;
  signal gthe2_i_n_54 : STD_LOGIC;
  signal gthe2_i_n_6 : STD_LOGIC;
  signal rx_char_is_k_i_2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_data_i_16 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg6 : label is "VCC:CE GND:R";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg6 : label is "VCC:CE GND:R";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  gt1_rx_disp_err_out(1 downto 0) <= \^gt1_rx_disp_err_out\(1 downto 0);
  gt1_rx_not_in_table_out(1 downto 0) <= \^gt1_rx_not_in_table_out\(1 downto 0);
  gt1_rxbufstatus_out(2 downto 0) <= \^gt1_rxbufstatus_out\(2 downto 0);
  gthe2_i_0 <= \^gthe2_i_0\;
  gthe2_i_1(1 downto 0) <= \^gthe2_i_1\(1 downto 0);
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2_reg_n_0,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
flag2_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => flag2_i_1_n_0
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => flag2_i_1_n_0,
      Q => flag2_reg_n_0,
      R => flag2_reg_0
    );
\flag_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D,
      O => \flag_i_1__0_n_0\
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag_i_1__0_n_0\,
      Q => D,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => gt1_cplllock_out,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT1_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPEN => DRPEN_IN_LANE1,
      DRPRDY => DRPRDY_OUT_LANE1,
      DRPWE => DRPWE_IN_LANE1,
      EYESCANDATAERROR => gt1_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt1_eyescanreset_in,
      EYESCANTRIGGER => gt1_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => RXN(0),
      GTHRXP => RXP(0),
      GTHTXN => gthe2_i_n_5,
      GTHTXP => gthe2_i_n_6,
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => SR(0),
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => fsm_gt_rx_reset_t,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad2_in,
      QPLLREFCLK => gt_qpllrefclk_quad2_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => gt1_rxbufreset_in,
      RXBUFSTATUS(2 downto 0) => \^gt1_rxbufstatus_out\(2 downto 0),
      RXBYTEISALIGNED => gt1_rxbyteisaligned_out,
      RXBYTEREALIGN => \^gthe2_i_0\,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => gt1_rxcdrhold_in,
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => gt1_rxcdrovrden_in,
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => CHBONDDONE_OUT_LANE1,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1 downto 0) => \^gthe2_i_1\(1 downto 0),
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1 downto 0) => rx_char_is_k_i_2(1 downto 0),
      RXCHBONDEN => en_chan_sync_i,
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"010",
      RXCHBONDMASTER => '1',
      RXCHBONDO(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt1_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15 downto 0) => rx_data_i_16(15 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => gt1_rxdfelpmreset_in,
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1 downto 0) => \^gt1_rx_disp_err_out\(1 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => gt1_rxlpmen_in,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => ena_comma_align_i_1,
      RXMONITOROUT(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1 downto 0) => \^gt1_rx_not_in_table_out\(1 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => ena_comma_align_i_1,
      RXPCSRESET => gt1_rxpcsreset_in,
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => gt1_rxpmareset_in,
      RXPMARESETDONE => gt1_rxpmaresetdone_out,
      RXPOLARITY => rx_polarity_i_1,
      RXPRBSCNTRESET => gt1_rxprbscntreset_in,
      RXPRBSERR => gt1_rxprbserr_out,
      RXPRBSSEL(2 downto 0) => gt1_rxprbssel_in(2 downto 0),
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt1_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1) => gthe2_i_n_112,
      TXBUFSTATUS(0) => gthe2_i_n_113,
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 0) => B"00000000",
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gthe2_i_n_45,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => '0',
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gthe2_i_n_54,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => '1',
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
\hard_err_flop_r_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^gt1_rxbufstatus_out\(2),
      I1 => bucket_full_r_5,
      I2 => \^gthe2_i_0\,
      O => hard_err_flop_r0_0
    );
\left_aligned_r_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFBEFFF"
    )
        port map (
      I0 => first_v_received_r_4,
      I1 => \^gthe2_i_1\(0),
      I2 => \^gthe2_i_1\(1),
      I3 => rx_char_is_k_i_2(1),
      I4 => rx_char_is_k_i_2(0),
      O => first_v_received_r_reg
    );
\reset_count_r_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \^gt1_rx_not_in_table_out\(1),
      I1 => \^gt1_rx_disp_err_out\(1),
      I2 => gtp_rx_reset_i_1,
      I3 => comma_over_two_cycles_r_3,
      I4 => \^gt1_rx_not_in_table_out\(0),
      I5 => \^gt1_rx_disp_err_out\(0),
      O => gthe2_i_4
    );
\soft_err_r[0]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt1_rx_not_in_table_out\(0),
      I1 => \^gt1_rx_disp_err_out\(0),
      O => gthe2_i_5(1)
    );
\soft_err_r[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt1_rx_not_in_table_out\(1),
      I1 => \^gt1_rx_disp_err_out\(1),
      O => gthe2_i_5(0)
    );
\word_aligned_control_bits_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_2(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_2(1),
      O => gthe2_i_3
    );
\word_aligned_control_bits_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_2(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_2(0),
      O => gthe2_i_2
    );
\word_aligned_data_r[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(7),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(15),
      O => gthe2_i_7(7)
    );
\word_aligned_data_r[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(13),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(5),
      O => gthe2_i_6(5)
    );
\word_aligned_data_r[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(12),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(4),
      O => gthe2_i_6(4)
    );
\word_aligned_data_r[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(11),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(3),
      O => gthe2_i_6(3)
    );
\word_aligned_data_r[13]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(10),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(2),
      O => gthe2_i_6(2)
    );
\word_aligned_data_r[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(9),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(1),
      O => gthe2_i_6(1)
    );
\word_aligned_data_r[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(8),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(0),
      O => gthe2_i_6(0)
    );
\word_aligned_data_r[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(6),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(14),
      O => gthe2_i_7(6)
    );
\word_aligned_data_r[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(5),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(13),
      O => gthe2_i_7(5)
    );
\word_aligned_data_r[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(4),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(12),
      O => gthe2_i_7(4)
    );
\word_aligned_data_r[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(3),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(11),
      O => gthe2_i_7(3)
    );
\word_aligned_data_r[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(2),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(10),
      O => gthe2_i_7(2)
    );
\word_aligned_data_r[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(9),
      O => gthe2_i_7(1)
    );
\word_aligned_data_r[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(8),
      O => gthe2_i_7(0)
    );
\word_aligned_data_r[8]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(15),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(7),
      O => gthe2_i_6(7)
    );
\word_aligned_data_r[9]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_16(14),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_16(6),
      O => gthe2_i_6(6)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_gt_34 is
  port (
    gt2_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_0 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE2 : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxpmaresetdone_out : out STD_LOGIC;
    gt2_rxprbserr_out : out STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RXCHBONDO : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gthe2_i_2 : out STD_LOGIC;
    gthe2_i_3 : out STD_LOGIC;
    gthe2_i_4 : out STD_LOGIC;
    gthe2_i_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg : out STD_LOGIC;
    hard_err_flop_r0_1 : out STD_LOGIC;
    gthe2_i_6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_7 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC_VECTOR ( 0 to 0 );
    RXP : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_refclk1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    fsm_gt_rx_reset_t : in STD_LOGIC;
    gt_qpllclk_quad3_in : in STD_LOGIC;
    gt_qpllrefclk_quad3_in : in STD_LOGIC;
    gt2_rxbufreset_in : in STD_LOGIC;
    gt2_rxcdrhold_in : in STD_LOGIC;
    gt2_rxcdrovrden_in : in STD_LOGIC;
    gt2_rxdfelpmreset_in : in STD_LOGIC;
    gt2_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_2 : in STD_LOGIC;
    gt2_rxpcsreset_in : in STD_LOGIC;
    gt2_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_2 : in STD_LOGIC;
    gt2_rxprbscntreset_in : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gthe2_i_8 : in STD_LOGIC_VECTOR ( 4 downto 0 );
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    gtp_rx_reset_i_2 : in STD_LOGIC;
    comma_over_two_cycles_r_6 : in STD_LOGIC;
    first_v_received_r_7 : in STD_LOGIC;
    bucket_full_r_8 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC;
    gt3_cplllock_out : in STD_LOGIC;
    gt0_cplllock_out : in STD_LOGIC;
    gt1_cplllock_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_gt_34 : entity is "aurora_rx_4l_64b_gt";
end aurora_rx_4l_64b_gt_34;

architecture STRUCTURE of aurora_rx_4l_64b_gt_34 is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D : STD_LOGIC;
  signal GT2_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal \flag2_i_1__0_n_0\ : STD_LOGIC;
  signal flag2_reg_n_0 : STD_LOGIC;
  signal \flag_i_1__1_n_0\ : STD_LOGIC;
  signal \^gt2_cplllock_out\ : STD_LOGIC;
  signal \^gt2_rx_disp_err_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt2_rx_not_in_table_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt2_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^gthe2_i_0\ : STD_LOGIC;
  signal \^gthe2_i_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_112 : STD_LOGIC;
  signal gthe2_i_n_113 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_5 : STD_LOGIC;
  signal gthe2_i_n_54 : STD_LOGIC;
  signal gthe2_i_n_6 : STD_LOGIC;
  signal rx_char_is_k_i_4 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_data_i_32 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg6 : label is "VCC:CE GND:R";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg6 : label is "VCC:CE GND:R";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  gt2_cplllock_out <= \^gt2_cplllock_out\;
  gt2_rx_disp_err_out(1 downto 0) <= \^gt2_rx_disp_err_out\(1 downto 0);
  gt2_rx_not_in_table_out(1 downto 0) <= \^gt2_rx_not_in_table_out\(1 downto 0);
  gt2_rxbufstatus_out(2 downto 0) <= \^gt2_rxbufstatus_out\(2 downto 0);
  gthe2_i_0 <= \^gthe2_i_0\;
  gthe2_i_1(1 downto 0) <= \^gthe2_i_1\(1 downto 0);
TX_LOCK_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^gt2_cplllock_out\,
      I1 => gt3_cplllock_out,
      I2 => gt0_cplllock_out,
      I3 => gt1_cplllock_out,
      O => TX_LOCK
    );
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2_reg_n_0,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
\flag2_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => \flag2_i_1__0_n_0\
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag2_i_1__0_n_0\,
      Q => flag2_reg_n_0,
      R => flag2_reg_0
    );
\flag_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D,
      O => \flag_i_1__1_n_0\
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag_i_1__1_n_0\,
      Q => D,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => \^gt2_cplllock_out\,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT2_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPEN => DRPEN_IN_LANE2,
      DRPRDY => DRPRDY_OUT_LANE2,
      DRPWE => DRPWE_IN_LANE2,
      EYESCANDATAERROR => gt2_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt2_eyescanreset_in,
      EYESCANTRIGGER => gt2_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => RXN(0),
      GTHRXP => RXP(0),
      GTHTXN => gthe2_i_n_5,
      GTHTXP => gthe2_i_n_6,
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => SR(0),
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => fsm_gt_rx_reset_t,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad3_in,
      QPLLREFCLK => gt_qpllrefclk_quad3_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => gt2_rxbufreset_in,
      RXBUFSTATUS(2 downto 0) => \^gt2_rxbufstatus_out\(2 downto 0),
      RXBYTEISALIGNED => gt2_rxbyteisaligned_out,
      RXBYTEREALIGN => \^gthe2_i_0\,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => gt2_rxcdrhold_in,
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => gt2_rxcdrovrden_in,
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => CHBONDDONE_OUT_LANE2,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1 downto 0) => \^gthe2_i_1\(1 downto 0),
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1 downto 0) => rx_char_is_k_i_4(1 downto 0),
      RXCHBONDEN => '1',
      RXCHBONDI(4 downto 0) => gthe2_i_8(4 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"001",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDSLAVE => '1',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt2_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15 downto 0) => rx_data_i_32(15 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => gt2_rxdfelpmreset_in,
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1 downto 0) => \^gt2_rx_disp_err_out\(1 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => gt2_rxlpmen_in,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => ena_comma_align_i_2,
      RXMONITOROUT(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1 downto 0) => \^gt2_rx_not_in_table_out\(1 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => ena_comma_align_i_2,
      RXPCSRESET => gt2_rxpcsreset_in,
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => gt2_rxpmareset_in,
      RXPMARESETDONE => gt2_rxpmaresetdone_out,
      RXPOLARITY => rx_polarity_i_2,
      RXPRBSCNTRESET => gt2_rxprbscntreset_in,
      RXPRBSERR => gt2_rxprbserr_out,
      RXPRBSSEL(2 downto 0) => gt2_rxprbssel_in(2 downto 0),
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt2_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1) => gthe2_i_n_112,
      TXBUFSTATUS(0) => gthe2_i_n_113,
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 0) => B"00000000",
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => TX_OUT_CLK,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => '0',
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gthe2_i_n_54,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => '1',
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
\hard_err_flop_r_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^gt2_rxbufstatus_out\(2),
      I1 => bucket_full_r_8,
      I2 => \^gthe2_i_0\,
      O => hard_err_flop_r0_1
    );
\left_aligned_r_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFBEFFF"
    )
        port map (
      I0 => first_v_received_r_7,
      I1 => \^gthe2_i_1\(0),
      I2 => \^gthe2_i_1\(1),
      I3 => rx_char_is_k_i_4(1),
      I4 => rx_char_is_k_i_4(0),
      O => first_v_received_r_reg
    );
\reset_count_r_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \^gt2_rx_not_in_table_out\(1),
      I1 => \^gt2_rx_disp_err_out\(1),
      I2 => gtp_rx_reset_i_2,
      I3 => comma_over_two_cycles_r_6,
      I4 => \^gt2_rx_not_in_table_out\(0),
      I5 => \^gt2_rx_disp_err_out\(0),
      O => gthe2_i_4
    );
\soft_err_r[0]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt2_rx_not_in_table_out\(0),
      I1 => \^gt2_rx_disp_err_out\(0),
      O => gthe2_i_5(1)
    );
\soft_err_r[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt2_rx_not_in_table_out\(1),
      I1 => \^gt2_rx_disp_err_out\(1),
      O => gthe2_i_5(0)
    );
\word_aligned_control_bits_r[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_4(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_4(1),
      O => gthe2_i_3
    );
\word_aligned_control_bits_r[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_4(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_4(0),
      O => gthe2_i_2
    );
\word_aligned_data_r[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(7),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(15),
      O => gthe2_i_7(7)
    );
\word_aligned_data_r[10]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(13),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(5),
      O => gthe2_i_6(5)
    );
\word_aligned_data_r[11]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(12),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(4),
      O => gthe2_i_6(4)
    );
\word_aligned_data_r[12]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(11),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(3),
      O => gthe2_i_6(3)
    );
\word_aligned_data_r[13]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(10),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(2),
      O => gthe2_i_6(2)
    );
\word_aligned_data_r[14]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(9),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(1),
      O => gthe2_i_6(1)
    );
\word_aligned_data_r[15]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(8),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(0),
      O => gthe2_i_6(0)
    );
\word_aligned_data_r[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(6),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(14),
      O => gthe2_i_7(6)
    );
\word_aligned_data_r[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(5),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(13),
      O => gthe2_i_7(5)
    );
\word_aligned_data_r[3]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(4),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(12),
      O => gthe2_i_7(4)
    );
\word_aligned_data_r[4]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(3),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(11),
      O => gthe2_i_7(3)
    );
\word_aligned_data_r[5]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(2),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(10),
      O => gthe2_i_7(2)
    );
\word_aligned_data_r[6]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(9),
      O => gthe2_i_7(1)
    );
\word_aligned_data_r[7]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(8),
      O => gthe2_i_7(0)
    );
\word_aligned_data_r[8]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(15),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(7),
      O => gthe2_i_6(7)
    );
\word_aligned_data_r[9]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_32(14),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_32(6),
      O => gthe2_i_6(6)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_gt_35 is
  port (
    gt3_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_0 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE3 : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxpmaresetdone_out : out STD_LOGIC;
    gt3_rxprbserr_out : out STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gthe2_i_2 : out STD_LOGIC;
    gthe2_i_3 : out STD_LOGIC;
    gthe2_i_4 : out STD_LOGIC;
    gthe2_i_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg : out STD_LOGIC;
    hard_err_flop_r0_2 : out STD_LOGIC;
    gthe2_i_6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_7 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC_VECTOR ( 0 to 0 );
    RXP : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_refclk1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    fsm_gt_rx_reset_t : in STD_LOGIC;
    gt_qpllclk_quad3_in : in STD_LOGIC;
    gt_qpllrefclk_quad3_in : in STD_LOGIC;
    gt3_rxbufreset_in : in STD_LOGIC;
    gt3_rxcdrhold_in : in STD_LOGIC;
    gt3_rxcdrovrden_in : in STD_LOGIC;
    gt3_rxdfelpmreset_in : in STD_LOGIC;
    gt3_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_3 : in STD_LOGIC;
    gt3_rxpcsreset_in : in STD_LOGIC;
    gt3_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_3 : in STD_LOGIC;
    gt3_rxprbscntreset_in : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg_0 : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    gtp_rx_reset_i_3 : in STD_LOGIC;
    comma_over_two_cycles_r_9 : in STD_LOGIC;
    first_v_received_r_10 : in STD_LOGIC;
    bucket_full_r_11 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_gt_35 : entity is "aurora_rx_4l_64b_gt";
end aurora_rx_4l_64b_gt_35;

architecture STRUCTURE of aurora_rx_4l_64b_gt_35 is
  signal CPLLPD : STD_LOGIC;
  signal CPLLRESET : STD_LOGIC;
  signal D : STD_LOGIC;
  signal GT3_CPLLREFCLKLOST_OUT : STD_LOGIC;
  signal ack_flag : STD_LOGIC;
  signal ack_flag_i_1_n_0 : STD_LOGIC;
  signal ack_sync1 : STD_LOGIC;
  signal ack_sync2 : STD_LOGIC;
  signal ack_sync3 : STD_LOGIC;
  signal ack_sync4 : STD_LOGIC;
  signal ack_sync5 : STD_LOGIC;
  signal ack_sync6 : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal cpllreset_ovrd_i : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal data_sync1 : STD_LOGIC;
  signal data_sync2 : STD_LOGIC;
  signal data_sync3 : STD_LOGIC;
  signal data_sync4 : STD_LOGIC;
  signal data_sync5 : STD_LOGIC;
  signal data_sync6 : STD_LOGIC;
  signal \flag2_i_1__1_n_0\ : STD_LOGIC;
  signal flag2_reg_n_0 : STD_LOGIC;
  signal \flag_i_1__2_n_0\ : STD_LOGIC;
  signal \^gt3_rx_disp_err_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt3_rx_not_in_table_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt3_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^gthe2_i_0\ : STD_LOGIC;
  signal \^gthe2_i_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gthe2_i_n_0 : STD_LOGIC;
  signal gthe2_i_n_104 : STD_LOGIC;
  signal gthe2_i_n_105 : STD_LOGIC;
  signal gthe2_i_n_112 : STD_LOGIC;
  signal gthe2_i_n_113 : STD_LOGIC;
  signal gthe2_i_n_12 : STD_LOGIC;
  signal gthe2_i_n_120 : STD_LOGIC;
  signal gthe2_i_n_121 : STD_LOGIC;
  signal gthe2_i_n_122 : STD_LOGIC;
  signal gthe2_i_n_123 : STD_LOGIC;
  signal gthe2_i_n_124 : STD_LOGIC;
  signal gthe2_i_n_13 : STD_LOGIC;
  signal gthe2_i_n_15 : STD_LOGIC;
  signal gthe2_i_n_29 : STD_LOGIC;
  signal gthe2_i_n_45 : STD_LOGIC;
  signal gthe2_i_n_46 : STD_LOGIC;
  signal gthe2_i_n_47 : STD_LOGIC;
  signal gthe2_i_n_5 : STD_LOGIC;
  signal gthe2_i_n_54 : STD_LOGIC;
  signal gthe2_i_n_6 : STD_LOGIC;
  signal rx_char_is_k_i_6 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_data_i_48 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RSOSINTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_RXVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_TXSYNCOUT_UNCONNECTED : STD_LOGIC;
  signal NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 );
  signal NLW_gthe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_gthe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_gthe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_gthe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE : string;
  attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT : string;
  attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of ack_sync_reg6 : label is "VCC:CE GND:R";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 ";
  attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg1 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg1 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg2 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg2 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg3 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg3 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg4 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg4 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg5 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg5 : label is "VCC:CE GND:R";
  attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true;
  attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE";
  attribute SHREG_EXTRACT of data_sync_reg6 : label is "no";
  attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD";
  attribute XILINX_TRANSFORM_PINMAP of data_sync_reg6 : label is "VCC:CE GND:R";
  attribute BOX_TYPE of gthe2_i : label is "PRIMITIVE";
begin
  gt3_rx_disp_err_out(1 downto 0) <= \^gt3_rx_disp_err_out\(1 downto 0);
  gt3_rx_not_in_table_out(1 downto 0) <= \^gt3_rx_not_in_table_out\(1 downto 0);
  gt3_rxbufstatus_out(2 downto 0) <= \^gt3_rxbufstatus_out\(2 downto 0);
  gthe2_i_0 <= \^gthe2_i_0\;
  gthe2_i_1(1 downto 0) <= \^gthe2_i_1\(1 downto 0);
ack_flag_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF90"
    )
        port map (
      I0 => ack_sync6,
      I1 => ack_sync5,
      I2 => ack_flag,
      I3 => flag2_reg_n_0,
      O => ack_flag_i_1_n_0
    );
ack_flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_flag_i_1_n_0,
      Q => ack_flag,
      R => '0'
    );
ack_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => data_sync6,
      Q => ack_sync1,
      R => '0'
    );
ack_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync1,
      Q => ack_sync2,
      R => '0'
    );
ack_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync2,
      Q => ack_sync3,
      R => '0'
    );
ack_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync3,
      Q => ack_sync4,
      R => '0'
    );
ack_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync4,
      Q => ack_sync5,
      R => '0'
    );
ack_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => ack_sync5,
      Q => ack_sync6,
      R => '0'
    );
\cpll_reset_i__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F6"
    )
        port map (
      I0 => data_sync6,
      I1 => data_sync5,
      I2 => cpllreset_ovrd_i,
      O => CPLLRESET
    );
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => CPLLPD,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllreset_ovrd_i,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_refclk1,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
data_sync_reg1: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => D,
      Q => data_sync1,
      R => '0'
    );
data_sync_reg2: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync1,
      Q => data_sync2,
      R => '0'
    );
data_sync_reg3: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync2,
      Q => data_sync3,
      R => '0'
    );
data_sync_reg4: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync3,
      Q => data_sync4,
      R => '0'
    );
data_sync_reg5: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync4,
      Q => data_sync5,
      R => '0'
    );
data_sync_reg6: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_refclk1,
      CE => '1',
      D => data_sync5,
      Q => data_sync6,
      R => '0'
    );
\flag2_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ack_flag,
      O => \flag2_i_1__1_n_0\
    );
flag2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag2_i_1__1_n_0\,
      Q => flag2_reg_n_0,
      R => flag2_reg_0
    );
\flag_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => ack_flag,
      I1 => cpll_reset_i,
      I2 => D,
      O => \flag_i_1__2_n_0\
    );
flag_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => \flag_i_1__2_n_0\,
      Q => D,
      R => '0'
    );
gthe2_i: unisim.vcomponents.GTHE2_CHANNEL
    generic map(
      ACJTAG_DEBUG_MODE => '0',
      ACJTAG_MODE => '0',
      ACJTAG_RESET => '0',
      ADAPT_CFG0 => X"00C10",
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 2,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      A_RXOSCALRESET => '0',
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CFOK_CFG => X"24800040E80",
      CFOK_CFG2 => B"100000",
      CFOK_CFG3 => B"100000",
      CHAN_BOND_KEEP_ALIGN => "FALSE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0101111100",
      CHAN_BOND_SEQ_1_2 => B"0000000000",
      CHAN_BOND_SEQ_1_3 => B"0000000000",
      CHAN_BOND_SEQ_1_4 => B"0000000000",
      CHAN_BOND_SEQ_1_ENABLE => B"0001",
      CHAN_BOND_SEQ_2_1 => B"0000000000",
      CHAN_BOND_SEQ_2_2 => B"0000000000",
      CHAN_BOND_SEQ_2_3 => B"0000000000",
      CHAN_BOND_SEQ_2_4 => B"0000000000",
      CHAN_BOND_SEQ_2_ENABLE => B"0000",
      CHAN_BOND_SEQ_2_USE => "FALSE",
      CHAN_BOND_SEQ_LEN => 1,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "FALSE",
      CLK_COR_MAX_LAT => 21,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0111110111",
      CLK_COR_SEQ_1_2 => B"0111110111",
      CLK_COR_SEQ_1_3 => B"0100000000",
      CLK_COR_SEQ_1_4 => B"0100000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0100000000",
      CLK_COR_SEQ_2_2 => B"0100000000",
      CLK_COR_SEQ_2_3 => B"0100000000",
      CLK_COR_SEQ_2_4 => B"0100000000",
      CLK_COR_SEQ_2_ENABLE => B"1111",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 2,
      CPLL_CFG => X"00BC07DC",
      CPLL_FBDIV => 4,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000A00",
      ES_CLK_PHASE_SEL => '0',
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "TRUE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "FALSE",
      GEARBOX_MODE => B"000",
      IS_CLKRSVD0_INVERTED => '0',
      IS_CLKRSVD1_INVERTED => '0',
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DMONITORCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_SIGVALIDCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      LOOPBACK_CFG => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "FALSE",
      PCS_RSVD_ATTR => X"000000000000",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"19",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => B"00000000000000000000000010000000",
      PMA_RSV2 => B"00011100000000000000000000001010",
      PMA_RSV3 => B"00",
      PMA_RSV4 => B"000000000001000",
      PMA_RSV5 => B"0000",
      RESET_POWERSAVE_DISABLE => '0',
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"1000",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "FALSE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"0002007FE2000C2080018",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '0',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00001000000000",
      RXLPM_LF_CFG => B"001001000000000000",
      RXOOB_CFG => B"0000110",
      RXOOB_CLK_CFG => "PMA",
      RXOSCALRESET_TIME => B"00011",
      RXOSCALRESET_TIMEOUT => B"00000",
      RXOUT_DIV => 1,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"084020",
      RXPH_CFG => X"C00002",
      RXPH_MONITOR_SEL => B"00000",
      RXPI_CFG0 => B"00",
      RXPI_CFG1 => B"00",
      RXPI_CFG2 => B"00",
      RXPI_CFG3 => B"00",
      RXPI_CFG4 => '0',
      RXPI_CFG5 => '0',
      RXPI_CFG6 => B"100",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "OFF",
      RXSYNC_MULTILANE => '0',
      RXSYNC_OVRD => '0',
      RXSYNC_SKIP_DA => '0',
      RX_BIAS_CFG => B"000011000000000000010000",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 7,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"1010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"00000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFELPM_CFG0 => B"0110",
      RX_DFELPM_CFG1 => '0',
      RX_DFELPM_KLKH_AGC_STUP_EN => '1',
      RX_DFE_AGC_CFG0 => B"00",
      RX_DFE_AGC_CFG1 => B"100",
      RX_DFE_AGC_CFG2 => B"0000",
      RX_DFE_AGC_OVRDEN => '1',
      RX_DFE_GAIN_CFG => X"0020C0",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011100000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_H6_CFG => B"00000100000",
      RX_DFE_H7_CFG => B"00000100000",
      RX_DFE_KL_CFG => B"001000001000000000000001100010000",
      RX_DFE_KL_LPM_KH_CFG0 => B"01",
      RX_DFE_KL_LPM_KH_CFG1 => B"010",
      RX_DFE_KL_LPM_KH_CFG2 => B"0010",
      RX_DFE_KL_LPM_KH_OVRDEN => '1',
      RX_DFE_KL_LPM_KL_CFG0 => B"10",
      RX_DFE_KL_LPM_KL_CFG1 => B"010",
      RX_DFE_KL_LPM_KL_CFG2 => B"0010",
      RX_DFE_KL_LPM_KL_OVRDEN => '1',
      RX_DFE_LPM_CFG => X"0080",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '0',
      RX_DFE_ST_CFG => X"00E100000C003F",
      RX_DFE_UT_CFG => B"00011100000000000",
      RX_DFE_VP_CFG => B"00011101010100011",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 10,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"0101",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "TRUE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "X",
      SIM_VERSION => "2.0",
      TERM_RCAL_CFG => B"100001000010000",
      TERM_RCAL_OVRD => B"000",
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "TRUE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOOB_CFG => '0',
      TXOUT_DIV => 1,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPI_CFG0 => B"00",
      TXPI_CFG1 => B"00",
      TXPI_CFG2 => B"00",
      TXPI_CFG3 => '0',
      TXPI_CFG4 => '0',
      TXPI_CFG5 => B"100",
      TXPI_GREY_SEL => '0',
      TXPI_INVSTROBE_SEL => '0',
      TXPI_PPMCLK_SEL => "TXUSRCLK2",
      TXPI_PPM_CFG => B"00000000",
      TXPI_SYNFREQ_PPM => B"000",
      TXPMARESET_TIME => B"00001",
      TXSYNC_MULTILANE => '0',
      TXSYNC_OVRD => '0',
      TXSYNC_SKIP_DA => '0',
      TX_CLK25_DIV => 7,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"000000",
      TX_DEEMPH1 => B"000000",
      TX_DRIVE_MODE => "DIRECT",
      TX_EIDLE_ASSERT_DELAY => B"110",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001110",
      TX_MARGIN_FULL_1 => B"1001001",
      TX_MARGIN_FULL_2 => B"1000101",
      TX_MARGIN_FULL_3 => B"1000010",
      TX_MARGIN_FULL_4 => B"1000000",
      TX_MARGIN_LOW_0 => B"1000110",
      TX_MARGIN_LOW_1 => B"1000100",
      TX_MARGIN_LOW_2 => B"1000010",
      TX_MARGIN_LOW_3 => B"1000000",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"1832",
      TX_RXDETECT_PRECHARGE_TIME => X"155CC",
      TX_RXDETECT_REF => B"100",
      TX_XCLK_SEL => "TXOUT",
      UCODEER_CLR => '0',
      USE_PCS_CLK_PHASE_SEL => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD0 => '0',
      CLKRSVD1 => '0',
      CPLLFBCLKLOST => gthe2_i_n_0,
      CPLLLOCK => gt3_cplllock_out,
      CPLLLOCKDETCLK => init_clk_in,
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD,
      CPLLREFCLKLOST => GT3_CPLLREFCLKLOST_OUT,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET,
      DMONFIFORESET => '0',
      DMONITORCLK => '0',
      DMONITOROUT(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      DRPADDR(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPCLK => drpclk_in,
      DRPDI(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN => DRPEN_IN_LANE3,
      DRPRDY => DRPRDY_OUT_LANE3,
      DRPWE => DRPWE_IN_LANE3,
      EYESCANDATAERROR => gt3_eyescandataerror_out,
      EYESCANMODE => '0',
      EYESCANRESET => gt3_eyescanreset_in,
      EYESCANTRIGGER => gt3_eyescantrigger_in,
      GTGREFCLK => '0',
      GTHRXN => RXN(0),
      GTHRXP => RXP(0),
      GTHTXN => gthe2_i_n_5,
      GTHTXP => gthe2_i_n_6,
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => gt_refclk1,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => SR(0),
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => fsm_gt_rx_reset_t,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0),
      PHYSTATUS => NLW_gthe2_i_PHYSTATUS_UNCONNECTED,
      PMARSVDIN(4 downto 0) => B"00000",
      QPLLCLK => gt_qpllclk_quad3_in,
      QPLLREFCLK => gt_qpllrefclk_quad3_in,
      RESETOVRD => '0',
      RSOSINTDONE => NLW_gthe2_i_RSOSINTDONE_UNCONNECTED,
      RX8B10BEN => '1',
      RXADAPTSELTEST(13 downto 0) => B"00000000000000",
      RXBUFRESET => gt3_rxbufreset_in,
      RXBUFSTATUS(2 downto 0) => \^gt3_rxbufstatus_out\(2 downto 0),
      RXBYTEISALIGNED => gt3_rxbyteisaligned_out,
      RXBYTEREALIGN => \^gthe2_i_0\,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => gt3_rxcdrhold_in,
      RXCDRLOCK => gthe2_i_n_12,
      RXCDROVRDEN => gt3_rxcdrovrden_in,
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => gthe2_i_n_13,
      RXCHANISALIGNED => CHBONDDONE_OUT_LANE3,
      RXCHANREALIGN => gthe2_i_n_15,
      RXCHARISCOMMA(7 downto 2) => NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2),
      RXCHARISCOMMA(1 downto 0) => \^gthe2_i_1\(1 downto 0),
      RXCHARISK(7 downto 2) => NLW_gthe2_i_RXCHARISK_UNCONNECTED(7 downto 2),
      RXCHARISK(1 downto 0) => rx_char_is_k_i_6(1 downto 0),
      RXCHBONDEN => '1',
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => gthe2_i_n_120,
      RXCHBONDO(3) => gthe2_i_n_121,
      RXCHBONDO(2) => gthe2_i_n_122,
      RXCHBONDO(1) => gthe2_i_n_123,
      RXCHBONDO(0) => gthe2_i_n_124,
      RXCHBONDSLAVE => '1',
      RXCLKCORCNT(1) => gthe2_i_n_104,
      RXCLKCORCNT(0) => gthe2_i_n_105,
      RXCOMINITDET => NLW_gthe2_i_RXCOMINITDET_UNCONNECTED,
      RXCOMMADET => gt3_rxcommadet_out,
      RXCOMMADETEN => '1',
      RXCOMSASDET => NLW_gthe2_i_RXCOMSASDET_UNCONNECTED,
      RXCOMWAKEDET => NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED,
      RXDATA(63 downto 16) => NLW_gthe2_i_RXDATA_UNCONNECTED(63 downto 16),
      RXDATA(15 downto 0) => rx_data_i_48(15 downto 0),
      RXDATAVALID(1 downto 0) => NLW_gthe2_i_RXDATAVALID_UNCONNECTED(1 downto 0),
      RXDDIEN => '0',
      RXDFEAGCHOLD => '0',
      RXDFEAGCOVRDEN => '0',
      RXDFEAGCTRL(4 downto 0) => B"10000",
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '0',
      RXDFELPMRESET => gt3_rxdfelpmreset_in,
      RXDFESLIDETAP(4 downto 0) => B"00000",
      RXDFESLIDETAPADAPTEN => '0',
      RXDFESLIDETAPHOLD => '0',
      RXDFESLIDETAPID(5 downto 0) => B"000000",
      RXDFESLIDETAPINITOVRDEN => '0',
      RXDFESLIDETAPONLYADAPTEN => '0',
      RXDFESLIDETAPOVRDEN => '0',
      RXDFESLIDETAPSTARTED => NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED,
      RXDFESLIDETAPSTROBE => '0',
      RXDFESLIDETAPSTROBEDONE => NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED,
      RXDFESLIDETAPSTROBESTARTED => NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED,
      RXDFESTADAPTDONE => NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFETAP6HOLD => '0',
      RXDFETAP6OVRDEN => '0',
      RXDFETAP7HOLD => '0',
      RXDFETAP7OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '1',
      RXDISPERR(7 downto 2) => NLW_gthe2_i_RXDISPERR_UNCONNECTED(7 downto 2),
      RXDISPERR(1 downto 0) => \^gt3_rx_disp_err_out\(1 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED,
      RXELECIDLE => NLW_gthe2_i_RXELECIDLE_UNCONNECTED,
      RXELECIDLEMODE(1 downto 0) => B"11",
      RXGEARBOXSLIP => '0',
      RXHEADER(5 downto 0) => NLW_gthe2_i_RXHEADER_UNCONNECTED(5 downto 0),
      RXHEADERVALID(1 downto 0) => NLW_gthe2_i_RXHEADERVALID_UNCONNECTED(1 downto 0),
      RXLPMEN => gt3_rxlpmen_in,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => ena_comma_align_i_3,
      RXMONITOROUT(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      RXMONITORSEL(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      RXNOTINTABLE(7 downto 2) => NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2),
      RXNOTINTABLE(1 downto 0) => \^gt3_rx_not_in_table_out\(1 downto 0),
      RXOOBRESET => '0',
      RXOSCALRESET => '0',
      RXOSHOLD => '0',
      RXOSINTCFG(3 downto 0) => B"0110",
      RXOSINTEN => '0',
      RXOSINTHOLD => '1',
      RXOSINTID0(3 downto 0) => B"0000",
      RXOSINTNTRLEN => '0',
      RXOSINTOVRDEN => '0',
      RXOSINTSTARTED => NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED,
      RXOSINTSTROBE => '0',
      RXOSINTSTROBEDONE => NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED,
      RXOSINTSTROBESTARTED => NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED,
      RXOSINTTESTOVRDEN => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => gthe2_i_n_29,
      RXOUTCLKFABRIC => NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED,
      RXOUTCLKPCS => NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED,
      RXOUTCLKSEL(2 downto 0) => B"010",
      RXPCOMMAALIGNEN => ena_comma_align_i_3,
      RXPCSRESET => gt3_rxpcsreset_in,
      RXPD(1) => POWER_DOWN,
      RXPD(0) => POWER_DOWN,
      RXPHALIGN => '0',
      RXPHALIGNDONE => NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => NLW_gthe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0),
      RXPMARESET => gt3_rxpmareset_in,
      RXPMARESETDONE => gt3_rxpmaresetdone_out,
      RXPOLARITY => rx_polarity_i_3,
      RXPRBSCNTRESET => gt3_rxprbscntreset_in,
      RXPRBSERR => gt3_rxprbserr_out,
      RXPRBSSEL(2 downto 0) => gt3_rxprbssel_in(2 downto 0),
      RXQPIEN => '0',
      RXQPISENN => NLW_gthe2_i_RXQPISENN_UNCONNECTED,
      RXQPISENP => NLW_gthe2_i_RXQPISENP_UNCONNECTED,
      RXRATE(2 downto 0) => B"000",
      RXRATEDONE => NLW_gthe2_i_RXRATEDONE_UNCONNECTED,
      RXRATEMODE => '0',
      RXRESETDONE => gt3_rxresetdone_out,
      RXSLIDE => '0',
      RXSTARTOFSEQ(1 downto 0) => NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED(1 downto 0),
      RXSTATUS(2 downto 0) => NLW_gthe2_i_RXSTATUS_UNCONNECTED(2 downto 0),
      RXSYNCALLIN => '0',
      RXSYNCDONE => NLW_gthe2_i_RXSYNCDONE_UNCONNECTED,
      RXSYNCIN => '0',
      RXSYNCMODE => '0',
      RXSYNCOUT => NLW_gthe2_i_RXSYNCOUT_UNCONNECTED,
      RXSYSCLKSEL(1 downto 0) => B"00",
      RXUSERRDY => gt_rxuserrdy_i,
      RXUSRCLK => sync_clk,
      RXUSRCLK2 => user_clk,
      RXVALID => NLW_gthe2_i_RXVALID_UNCONNECTED,
      SETERRSTATUS => '0',
      SIGVALIDCLK => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => '1',
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1) => gthe2_i_n_112,
      TXBUFSTATUS(0) => gthe2_i_n_113,
      TXCHARDISPMODE(7 downto 0) => B"00000000",
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 0) => B"00000000",
      TXCOMFINISH => NLW_gthe2_i_TXCOMFINISH_UNCONNECTED,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      TXDEEMPH => '0',
      TXDETECTRX => '0',
      TXDIFFCTRL(3 downto 0) => B"1000",
      TXDIFFPD => '0',
      TXDLYBYPASS => '1',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => '0',
      TXDLYSRESETDONE => NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED,
      TXDLYUPDOWN => '0',
      TXELECIDLE => '0',
      TXGEARBOXREADY => NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => '0',
      TXMAINCURSOR(6 downto 0) => B"0000000",
      TXMARGIN(2 downto 0) => B"000",
      TXOUTCLK => gthe2_i_n_45,
      TXOUTCLKFABRIC => gthe2_i_n_46,
      TXOUTCLKPCS => gthe2_i_n_47,
      TXOUTCLKSEL(2 downto 0) => B"010",
      TXPCSRESET => '0',
      TXPD(1) => POWER_DOWN,
      TXPD(0) => POWER_DOWN,
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => '0',
      TXPHALIGNDONE => NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED,
      TXPHALIGNEN => '0',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => '0',
      TXPHINITDONE => NLW_gthe2_i_TXPHINITDONE_UNCONNECTED,
      TXPHOVRDEN => '0',
      TXPIPPMEN => '0',
      TXPIPPMOVRDEN => '0',
      TXPIPPMPD => '0',
      TXPIPPMSEL => '1',
      TXPIPPMSTEPSIZE(4 downto 0) => B"00000",
      TXPISOPD => '0',
      TXPMARESET => '0',
      TXPMARESETDONE => NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => B"00000",
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => B"00000",
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => NLW_gthe2_i_TXQPISENN_UNCONNECTED,
      TXQPISENP => NLW_gthe2_i_TXQPISENP_UNCONNECTED,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => B"000",
      TXRATEDONE => NLW_gthe2_i_TXRATEDONE_UNCONNECTED,
      TXRATEMODE => '0',
      TXRESETDONE => gthe2_i_n_54,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYNCALLIN => '0',
      TXSYNCDONE => NLW_gthe2_i_TXSYNCDONE_UNCONNECTED,
      TXSYNCIN => '0',
      TXSYNCMODE => '0',
      TXSYNCOUT => NLW_gthe2_i_TXSYNCOUT_UNCONNECTED,
      TXSYSCLKSEL(1 downto 0) => B"00",
      TXUSERRDY => '1',
      TXUSRCLK => sync_clk,
      TXUSRCLK2 => user_clk
    );
\hard_err_flop_r_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^gt3_rxbufstatus_out\(2),
      I1 => bucket_full_r_11,
      I2 => \^gthe2_i_0\,
      O => hard_err_flop_r0_2
    );
\left_aligned_r_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFBEFFF"
    )
        port map (
      I0 => first_v_received_r_10,
      I1 => \^gthe2_i_1\(0),
      I2 => \^gthe2_i_1\(1),
      I3 => rx_char_is_k_i_6(1),
      I4 => rx_char_is_k_i_6(0),
      O => first_v_received_r_reg
    );
\reset_count_r_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \^gt3_rx_not_in_table_out\(1),
      I1 => \^gt3_rx_disp_err_out\(1),
      I2 => gtp_rx_reset_i_3,
      I3 => comma_over_two_cycles_r_9,
      I4 => \^gt3_rx_not_in_table_out\(0),
      I5 => \^gt3_rx_disp_err_out\(0),
      O => gthe2_i_4
    );
\soft_err_r[0]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt3_rx_not_in_table_out\(0),
      I1 => \^gt3_rx_disp_err_out\(0),
      O => gthe2_i_5(1)
    );
\soft_err_r[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^gt3_rx_not_in_table_out\(1),
      I1 => \^gt3_rx_disp_err_out\(1),
      O => gthe2_i_5(0)
    );
\word_aligned_control_bits_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_6(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_6(1),
      O => gthe2_i_3
    );
\word_aligned_control_bits_r[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_char_is_k_i_6(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_char_is_k_i_6(0),
      O => gthe2_i_2
    );
\word_aligned_data_r[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(7),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(15),
      O => gthe2_i_7(7)
    );
\word_aligned_data_r[10]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(13),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(5),
      O => gthe2_i_6(5)
    );
\word_aligned_data_r[11]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(12),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(4),
      O => gthe2_i_6(4)
    );
\word_aligned_data_r[12]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(11),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(3),
      O => gthe2_i_6(3)
    );
\word_aligned_data_r[13]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(10),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(2),
      O => gthe2_i_6(2)
    );
\word_aligned_data_r[14]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(9),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(1),
      O => gthe2_i_6(1)
    );
\word_aligned_data_r[15]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(8),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(0),
      O => gthe2_i_6(0)
    );
\word_aligned_data_r[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(6),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(14),
      O => gthe2_i_7(6)
    );
\word_aligned_data_r[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(5),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(13),
      O => gthe2_i_7(5)
    );
\word_aligned_data_r[3]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(4),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(12),
      O => gthe2_i_7(4)
    );
\word_aligned_data_r[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(3),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(11),
      O => gthe2_i_7(3)
    );
\word_aligned_data_r[5]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(2),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(10),
      O => gthe2_i_7(2)
    );
\word_aligned_data_r[6]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(1),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(9),
      O => gthe2_i_7(1)
    );
\word_aligned_data_r[7]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(0),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(8),
      O => gthe2_i_7(0)
    );
\word_aligned_data_r[8]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(15),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(7),
      O => gthe2_i_6(7)
    );
\word_aligned_data_r[9]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => rx_data_i_48(14),
      I1 => \word_aligned_control_bits_r_reg[1]\,
      I2 => rx_data_i_48(6),
      O => gthe2_i_6(6)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_HOTPLUG is
  port (
    LINK_RESET_OUT : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    link_reset_lane0_i : in STD_LOGIC;
    link_reset_lane1_i : in STD_LOGIC;
    link_reset_lane2_i : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end aurora_rx_4l_64b_HOTPLUG;

architecture STRUCTURE of aurora_rx_4l_64b_HOTPLUG is
  signal \hotplug_count_synth.count_for_reset_r_reg\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal link_reset_0 : STD_LOGIC;
  signal link_reset_lane3_i : STD_LOGIC;
  signal link_reset_r : STD_LOGIC;
  signal \link_reset_r_i_2__2_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_3__2_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_4__2_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_5__2_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_6__2_n_0\ : STD_LOGIC;
  signal rx_cc_cdc_sync_n_0 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_1 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_10 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_11 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_12 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_13 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_14 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_15 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_16 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_17 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_18 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_19 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_2 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_20 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_21 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_22 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_23 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_24 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_25 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_3 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_4 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_5 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_6 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_7 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_8 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_9 : STD_LOGIC;
  signal rx_cc_extend_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_cc_extend_r2 : STD_LOGIC;
  signal rx_cc_extend_r2_i_1_n_0 : STD_LOGIC;
  signal rx_cc_extend_r2_i_2_n_0 : STD_LOGIC;
begin
LINK_RESET_OUT_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => link_reset_lane3_i,
      I1 => link_reset_lane0_i,
      I2 => link_reset_lane1_i,
      I3 => link_reset_lane2_i,
      O => LINK_RESET_OUT
    );
\hotplug_count_synth.count_for_reset_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_3,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(0)
    );
\hotplug_count_synth.count_for_reset_r_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_9,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(10)
    );
\hotplug_count_synth.count_for_reset_r_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_8,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(11)
    );
\hotplug_count_synth.count_for_reset_r_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_15,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(12)
    );
\hotplug_count_synth.count_for_reset_r_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_14,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(13)
    );
\hotplug_count_synth.count_for_reset_r_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_13,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(14)
    );
\hotplug_count_synth.count_for_reset_r_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_12,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(15)
    );
\hotplug_count_synth.count_for_reset_r_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_19,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(16)
    );
\hotplug_count_synth.count_for_reset_r_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_18,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(17)
    );
\hotplug_count_synth.count_for_reset_r_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_17,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(18)
    );
\hotplug_count_synth.count_for_reset_r_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_16,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(19)
    );
\hotplug_count_synth.count_for_reset_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_2,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(1)
    );
\hotplug_count_synth.count_for_reset_r_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_23,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(20)
    );
\hotplug_count_synth.count_for_reset_r_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_22,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(21)
    );
\hotplug_count_synth.count_for_reset_r_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_21,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(22)
    );
\hotplug_count_synth.count_for_reset_r_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_20,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(23)
    );
\hotplug_count_synth.count_for_reset_r_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_25,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(24)
    );
\hotplug_count_synth.count_for_reset_r_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_24,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(25)
    );
\hotplug_count_synth.count_for_reset_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_1,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(2)
    );
\hotplug_count_synth.count_for_reset_r_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_0,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(3)
    );
\hotplug_count_synth.count_for_reset_r_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_7,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(4)
    );
\hotplug_count_synth.count_for_reset_r_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_6,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(5)
    );
\hotplug_count_synth.count_for_reset_r_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_5,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(6)
    );
\hotplug_count_synth.count_for_reset_r_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_4,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(7)
    );
\hotplug_count_synth.count_for_reset_r_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_11,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(8)
    );
\hotplug_count_synth.count_for_reset_r_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_10,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(9)
    );
\hotplug_enable.LINK_RESET_OUT_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r,
      Q => link_reset_lane3_i,
      R => '0'
    );
\link_reset_r_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \link_reset_r_i_2__2_n_0\,
      I1 => \link_reset_r_i_3__2_n_0\,
      I2 => \link_reset_r_i_4__2_n_0\,
      I3 => \link_reset_r_i_5__2_n_0\,
      I4 => \link_reset_r_i_6__2_n_0\,
      O => link_reset_0
    );
\link_reset_r_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      O => \link_reset_r_i_2__2_n_0\
    );
\link_reset_r_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78F8F8F8"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      O => \link_reset_r_i_3__2_n_0\
    );
\link_reset_r_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      O => \link_reset_r_i_4__2_n_0\
    );
\link_reset_r_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      O => \link_reset_r_i_5__2_n_0\
    );
\link_reset_r_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      O => \link_reset_r_i_6__2_n_0\
    );
link_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_0,
      Q => link_reset_r,
      R => '0'
    );
rx_cc_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2\
     port map (
      O(3) => rx_cc_cdc_sync_n_0,
      O(2) => rx_cc_cdc_sync_n_1,
      O(1) => rx_cc_cdc_sync_n_2,
      O(0) => rx_cc_cdc_sync_n_3,
      \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0) => \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0),
      \hotplug_count_synth.count_for_reset_r_reg[11]\(3) => rx_cc_cdc_sync_n_8,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(2) => rx_cc_cdc_sync_n_9,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(1) => rx_cc_cdc_sync_n_10,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(0) => rx_cc_cdc_sync_n_11,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(3) => rx_cc_cdc_sync_n_12,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(2) => rx_cc_cdc_sync_n_13,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(1) => rx_cc_cdc_sync_n_14,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(0) => rx_cc_cdc_sync_n_15,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(3) => rx_cc_cdc_sync_n_16,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(2) => rx_cc_cdc_sync_n_17,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(1) => rx_cc_cdc_sync_n_18,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(0) => rx_cc_cdc_sync_n_19,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(3) => rx_cc_cdc_sync_n_20,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(2) => rx_cc_cdc_sync_n_21,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(1) => rx_cc_cdc_sync_n_22,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(0) => rx_cc_cdc_sync_n_23,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(1) => rx_cc_cdc_sync_n_24,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(0) => rx_cc_cdc_sync_n_25,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(3) => rx_cc_cdc_sync_n_4,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(2) => rx_cc_cdc_sync_n_5,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(1) => rx_cc_cdc_sync_n_6,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(0) => rx_cc_cdc_sync_n_7,
      init_clk_in => init_clk_in,
      rx_cc_extend_r2 => rx_cc_extend_r2,
      user_clk => user_clk
    );
rx_cc_extend_r2_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => rx_cc_extend_r(2),
      I1 => rx_cc_extend_r(3),
      I2 => rx_cc_extend_r(0),
      I3 => rx_cc_extend_r(1),
      I4 => rx_cc_extend_r2_i_2_n_0,
      O => rx_cc_extend_r2_i_1_n_0
    );
rx_cc_extend_r2_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rx_cc_extend_r(5),
      I1 => rx_cc_extend_r(4),
      I2 => rx_cc_extend_r(7),
      I3 => rx_cc_extend_r(6),
      O => rx_cc_extend_r2_i_2_n_0
    );
rx_cc_extend_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2_i_1_n_0,
      Q => rx_cc_extend_r2,
      R => '0'
    );
\rx_cc_extend_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(1),
      Q => rx_cc_extend_r(0),
      R => SR(0)
    );
\rx_cc_extend_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(2),
      Q => rx_cc_extend_r(1),
      R => SR(0)
    );
\rx_cc_extend_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(3),
      Q => rx_cc_extend_r(2),
      R => SR(0)
    );
\rx_cc_extend_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(4),
      Q => rx_cc_extend_r(3),
      R => SR(0)
    );
\rx_cc_extend_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(5),
      Q => rx_cc_extend_r(4),
      R => SR(0)
    );
\rx_cc_extend_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(6),
      Q => rx_cc_extend_r(5),
      R => SR(0)
    );
\rx_cc_extend_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(7),
      Q => rx_cc_extend_r(6),
      R => SR(0)
    );
\rx_cc_extend_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => rx_cc_extend_r(7),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_HOTPLUG_11 is
  port (
    link_reset_lane1_i : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_HOTPLUG_11 : entity is "aurora_rx_4l_64b_HOTPLUG";
end aurora_rx_4l_64b_HOTPLUG_11;

architecture STRUCTURE of aurora_rx_4l_64b_HOTPLUG_11 is
  signal \hotplug_count_synth.count_for_reset_r_reg\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal link_reset_0 : STD_LOGIC;
  signal link_reset_r : STD_LOGIC;
  signal \link_reset_r_i_2__0_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_3__0_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_4__0_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_5__0_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_6__0_n_0\ : STD_LOGIC;
  signal rx_cc_cdc_sync_n_0 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_1 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_10 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_11 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_12 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_13 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_14 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_15 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_16 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_17 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_18 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_19 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_2 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_20 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_21 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_22 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_23 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_24 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_25 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_3 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_4 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_5 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_6 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_7 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_8 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_9 : STD_LOGIC;
  signal rx_cc_extend_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_cc_extend_r2 : STD_LOGIC;
  signal rx_cc_extend_r2_i_1_n_0 : STD_LOGIC;
  signal rx_cc_extend_r2_i_2_n_0 : STD_LOGIC;
begin
\hotplug_count_synth.count_for_reset_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_3,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(0)
    );
\hotplug_count_synth.count_for_reset_r_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_9,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(10)
    );
\hotplug_count_synth.count_for_reset_r_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_8,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(11)
    );
\hotplug_count_synth.count_for_reset_r_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_15,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(12)
    );
\hotplug_count_synth.count_for_reset_r_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_14,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(13)
    );
\hotplug_count_synth.count_for_reset_r_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_13,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(14)
    );
\hotplug_count_synth.count_for_reset_r_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_12,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(15)
    );
\hotplug_count_synth.count_for_reset_r_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_19,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(16)
    );
\hotplug_count_synth.count_for_reset_r_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_18,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(17)
    );
\hotplug_count_synth.count_for_reset_r_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_17,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(18)
    );
\hotplug_count_synth.count_for_reset_r_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_16,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(19)
    );
\hotplug_count_synth.count_for_reset_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_2,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(1)
    );
\hotplug_count_synth.count_for_reset_r_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_23,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(20)
    );
\hotplug_count_synth.count_for_reset_r_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_22,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(21)
    );
\hotplug_count_synth.count_for_reset_r_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_21,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(22)
    );
\hotplug_count_synth.count_for_reset_r_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_20,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(23)
    );
\hotplug_count_synth.count_for_reset_r_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_25,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(24)
    );
\hotplug_count_synth.count_for_reset_r_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_24,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(25)
    );
\hotplug_count_synth.count_for_reset_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_1,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(2)
    );
\hotplug_count_synth.count_for_reset_r_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_0,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(3)
    );
\hotplug_count_synth.count_for_reset_r_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_7,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(4)
    );
\hotplug_count_synth.count_for_reset_r_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_6,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(5)
    );
\hotplug_count_synth.count_for_reset_r_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_5,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(6)
    );
\hotplug_count_synth.count_for_reset_r_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_4,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(7)
    );
\hotplug_count_synth.count_for_reset_r_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_11,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(8)
    );
\hotplug_count_synth.count_for_reset_r_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_10,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(9)
    );
\hotplug_enable.LINK_RESET_OUT_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r,
      Q => link_reset_lane1_i,
      R => '0'
    );
\link_reset_r_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \link_reset_r_i_2__0_n_0\,
      I1 => \link_reset_r_i_3__0_n_0\,
      I2 => \link_reset_r_i_4__0_n_0\,
      I3 => \link_reset_r_i_5__0_n_0\,
      I4 => \link_reset_r_i_6__0_n_0\,
      O => link_reset_0
    );
\link_reset_r_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      O => \link_reset_r_i_2__0_n_0\
    );
\link_reset_r_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78F8F8F8"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      O => \link_reset_r_i_3__0_n_0\
    );
\link_reset_r_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      O => \link_reset_r_i_4__0_n_0\
    );
\link_reset_r_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      O => \link_reset_r_i_5__0_n_0\
    );
\link_reset_r_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      O => \link_reset_r_i_6__0_n_0\
    );
link_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_0,
      Q => link_reset_r,
      R => '0'
    );
rx_cc_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_15\
     port map (
      O(3) => rx_cc_cdc_sync_n_0,
      O(2) => rx_cc_cdc_sync_n_1,
      O(1) => rx_cc_cdc_sync_n_2,
      O(0) => rx_cc_cdc_sync_n_3,
      \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0) => \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0),
      \hotplug_count_synth.count_for_reset_r_reg[11]\(3) => rx_cc_cdc_sync_n_8,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(2) => rx_cc_cdc_sync_n_9,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(1) => rx_cc_cdc_sync_n_10,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(0) => rx_cc_cdc_sync_n_11,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(3) => rx_cc_cdc_sync_n_12,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(2) => rx_cc_cdc_sync_n_13,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(1) => rx_cc_cdc_sync_n_14,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(0) => rx_cc_cdc_sync_n_15,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(3) => rx_cc_cdc_sync_n_16,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(2) => rx_cc_cdc_sync_n_17,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(1) => rx_cc_cdc_sync_n_18,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(0) => rx_cc_cdc_sync_n_19,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(3) => rx_cc_cdc_sync_n_20,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(2) => rx_cc_cdc_sync_n_21,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(1) => rx_cc_cdc_sync_n_22,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(0) => rx_cc_cdc_sync_n_23,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(1) => rx_cc_cdc_sync_n_24,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(0) => rx_cc_cdc_sync_n_25,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(3) => rx_cc_cdc_sync_n_4,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(2) => rx_cc_cdc_sync_n_5,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(1) => rx_cc_cdc_sync_n_6,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(0) => rx_cc_cdc_sync_n_7,
      init_clk_in => init_clk_in,
      rx_cc_extend_r2 => rx_cc_extend_r2,
      user_clk => user_clk
    );
rx_cc_extend_r2_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => rx_cc_extend_r(2),
      I1 => rx_cc_extend_r(3),
      I2 => rx_cc_extend_r(0),
      I3 => rx_cc_extend_r(1),
      I4 => rx_cc_extend_r2_i_2_n_0,
      O => rx_cc_extend_r2_i_1_n_0
    );
rx_cc_extend_r2_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rx_cc_extend_r(5),
      I1 => rx_cc_extend_r(4),
      I2 => rx_cc_extend_r(7),
      I3 => rx_cc_extend_r(6),
      O => rx_cc_extend_r2_i_2_n_0
    );
rx_cc_extend_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2_i_1_n_0,
      Q => rx_cc_extend_r2,
      R => '0'
    );
\rx_cc_extend_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(1),
      Q => rx_cc_extend_r(0),
      R => SR(0)
    );
\rx_cc_extend_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(2),
      Q => rx_cc_extend_r(1),
      R => SR(0)
    );
\rx_cc_extend_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(3),
      Q => rx_cc_extend_r(2),
      R => SR(0)
    );
\rx_cc_extend_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(4),
      Q => rx_cc_extend_r(3),
      R => SR(0)
    );
\rx_cc_extend_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(5),
      Q => rx_cc_extend_r(4),
      R => SR(0)
    );
\rx_cc_extend_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(6),
      Q => rx_cc_extend_r(5),
      R => SR(0)
    );
\rx_cc_extend_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(7),
      Q => rx_cc_extend_r(6),
      R => SR(0)
    );
\rx_cc_extend_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => rx_cc_extend_r(7),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_HOTPLUG_16 is
  port (
    link_reset_lane0_i : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_HOTPLUG_16 : entity is "aurora_rx_4l_64b_HOTPLUG";
end aurora_rx_4l_64b_HOTPLUG_16;

architecture STRUCTURE of aurora_rx_4l_64b_HOTPLUG_16 is
  signal \hotplug_count_synth.count_for_reset_r_reg\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal link_reset_0 : STD_LOGIC;
  signal link_reset_r : STD_LOGIC;
  signal link_reset_r_i_2_n_0 : STD_LOGIC;
  signal link_reset_r_i_3_n_0 : STD_LOGIC;
  signal link_reset_r_i_4_n_0 : STD_LOGIC;
  signal link_reset_r_i_5_n_0 : STD_LOGIC;
  signal link_reset_r_i_6_n_0 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_0 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_1 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_10 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_11 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_12 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_13 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_14 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_15 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_16 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_17 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_18 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_19 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_2 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_20 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_21 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_22 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_23 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_24 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_25 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_3 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_4 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_5 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_6 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_7 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_8 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_9 : STD_LOGIC;
  signal rx_cc_extend_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_cc_extend_r2 : STD_LOGIC;
  signal rx_cc_extend_r2_i_1_n_0 : STD_LOGIC;
  signal rx_cc_extend_r2_i_2_n_0 : STD_LOGIC;
begin
\hotplug_count_synth.count_for_reset_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_3,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(0)
    );
\hotplug_count_synth.count_for_reset_r_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_9,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(10)
    );
\hotplug_count_synth.count_for_reset_r_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_8,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(11)
    );
\hotplug_count_synth.count_for_reset_r_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_15,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(12)
    );
\hotplug_count_synth.count_for_reset_r_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_14,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(13)
    );
\hotplug_count_synth.count_for_reset_r_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_13,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(14)
    );
\hotplug_count_synth.count_for_reset_r_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_12,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(15)
    );
\hotplug_count_synth.count_for_reset_r_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_19,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(16)
    );
\hotplug_count_synth.count_for_reset_r_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_18,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(17)
    );
\hotplug_count_synth.count_for_reset_r_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_17,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(18)
    );
\hotplug_count_synth.count_for_reset_r_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_16,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(19)
    );
\hotplug_count_synth.count_for_reset_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_2,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(1)
    );
\hotplug_count_synth.count_for_reset_r_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_23,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(20)
    );
\hotplug_count_synth.count_for_reset_r_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_22,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(21)
    );
\hotplug_count_synth.count_for_reset_r_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_21,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(22)
    );
\hotplug_count_synth.count_for_reset_r_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_20,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(23)
    );
\hotplug_count_synth.count_for_reset_r_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_25,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(24)
    );
\hotplug_count_synth.count_for_reset_r_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_24,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(25)
    );
\hotplug_count_synth.count_for_reset_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_1,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(2)
    );
\hotplug_count_synth.count_for_reset_r_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_0,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(3)
    );
\hotplug_count_synth.count_for_reset_r_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_7,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(4)
    );
\hotplug_count_synth.count_for_reset_r_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_6,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(5)
    );
\hotplug_count_synth.count_for_reset_r_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_5,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(6)
    );
\hotplug_count_synth.count_for_reset_r_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_4,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(7)
    );
\hotplug_count_synth.count_for_reset_r_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_11,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(8)
    );
\hotplug_count_synth.count_for_reset_r_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_10,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(9)
    );
\hotplug_enable.LINK_RESET_OUT_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r,
      Q => link_reset_lane0_i,
      R => '0'
    );
link_reset_r_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => link_reset_r_i_2_n_0,
      I1 => link_reset_r_i_3_n_0,
      I2 => link_reset_r_i_4_n_0,
      I3 => link_reset_r_i_5_n_0,
      I4 => link_reset_r_i_6_n_0,
      O => link_reset_0
    );
link_reset_r_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      O => link_reset_r_i_2_n_0
    );
link_reset_r_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78F8F8F8"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      O => link_reset_r_i_3_n_0
    );
link_reset_r_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      O => link_reset_r_i_4_n_0
    );
link_reset_r_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      O => link_reset_r_i_5_n_0
    );
link_reset_r_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      O => link_reset_r_i_6_n_0
    );
link_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_0,
      Q => link_reset_r,
      R => '0'
    );
rx_cc_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_20\
     port map (
      O(3) => rx_cc_cdc_sync_n_0,
      O(2) => rx_cc_cdc_sync_n_1,
      O(1) => rx_cc_cdc_sync_n_2,
      O(0) => rx_cc_cdc_sync_n_3,
      \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0) => \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0),
      \hotplug_count_synth.count_for_reset_r_reg[11]\(3) => rx_cc_cdc_sync_n_8,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(2) => rx_cc_cdc_sync_n_9,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(1) => rx_cc_cdc_sync_n_10,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(0) => rx_cc_cdc_sync_n_11,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(3) => rx_cc_cdc_sync_n_12,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(2) => rx_cc_cdc_sync_n_13,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(1) => rx_cc_cdc_sync_n_14,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(0) => rx_cc_cdc_sync_n_15,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(3) => rx_cc_cdc_sync_n_16,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(2) => rx_cc_cdc_sync_n_17,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(1) => rx_cc_cdc_sync_n_18,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(0) => rx_cc_cdc_sync_n_19,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(3) => rx_cc_cdc_sync_n_20,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(2) => rx_cc_cdc_sync_n_21,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(1) => rx_cc_cdc_sync_n_22,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(0) => rx_cc_cdc_sync_n_23,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(1) => rx_cc_cdc_sync_n_24,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(0) => rx_cc_cdc_sync_n_25,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(3) => rx_cc_cdc_sync_n_4,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(2) => rx_cc_cdc_sync_n_5,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(1) => rx_cc_cdc_sync_n_6,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(0) => rx_cc_cdc_sync_n_7,
      init_clk_in => init_clk_in,
      rx_cc_extend_r2 => rx_cc_extend_r2,
      user_clk => user_clk
    );
rx_cc_extend_r2_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => rx_cc_extend_r(2),
      I1 => rx_cc_extend_r(3),
      I2 => rx_cc_extend_r(0),
      I3 => rx_cc_extend_r(1),
      I4 => rx_cc_extend_r2_i_2_n_0,
      O => rx_cc_extend_r2_i_1_n_0
    );
rx_cc_extend_r2_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rx_cc_extend_r(5),
      I1 => rx_cc_extend_r(4),
      I2 => rx_cc_extend_r(7),
      I3 => rx_cc_extend_r(6),
      O => rx_cc_extend_r2_i_2_n_0
    );
rx_cc_extend_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2_i_1_n_0,
      Q => rx_cc_extend_r2,
      R => '0'
    );
\rx_cc_extend_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(1),
      Q => rx_cc_extend_r(0),
      R => SR(0)
    );
\rx_cc_extend_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(2),
      Q => rx_cc_extend_r(1),
      R => SR(0)
    );
\rx_cc_extend_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(3),
      Q => rx_cc_extend_r(2),
      R => SR(0)
    );
\rx_cc_extend_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(4),
      Q => rx_cc_extend_r(3),
      R => SR(0)
    );
\rx_cc_extend_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(5),
      Q => rx_cc_extend_r(4),
      R => SR(0)
    );
\rx_cc_extend_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(6),
      Q => rx_cc_extend_r(5),
      R => SR(0)
    );
\rx_cc_extend_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(7),
      Q => rx_cc_extend_r(6),
      R => SR(0)
    );
\rx_cc_extend_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => rx_cc_extend_r(7),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_HOTPLUG_6 is
  port (
    link_reset_lane2_i : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_HOTPLUG_6 : entity is "aurora_rx_4l_64b_HOTPLUG";
end aurora_rx_4l_64b_HOTPLUG_6;

architecture STRUCTURE of aurora_rx_4l_64b_HOTPLUG_6 is
  signal \hotplug_count_synth.count_for_reset_r_reg\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal link_reset_0 : STD_LOGIC;
  signal link_reset_r : STD_LOGIC;
  signal \link_reset_r_i_2__1_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_3__1_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_4__1_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_5__1_n_0\ : STD_LOGIC;
  signal \link_reset_r_i_6__1_n_0\ : STD_LOGIC;
  signal rx_cc_cdc_sync_n_0 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_1 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_10 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_11 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_12 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_13 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_14 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_15 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_16 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_17 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_18 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_19 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_2 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_20 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_21 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_22 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_23 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_24 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_25 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_3 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_4 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_5 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_6 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_7 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_8 : STD_LOGIC;
  signal rx_cc_cdc_sync_n_9 : STD_LOGIC;
  signal rx_cc_extend_r : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_cc_extend_r2 : STD_LOGIC;
  signal rx_cc_extend_r2_i_1_n_0 : STD_LOGIC;
  signal rx_cc_extend_r2_i_2_n_0 : STD_LOGIC;
begin
\hotplug_count_synth.count_for_reset_r_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_3,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(0)
    );
\hotplug_count_synth.count_for_reset_r_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_9,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(10)
    );
\hotplug_count_synth.count_for_reset_r_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_8,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(11)
    );
\hotplug_count_synth.count_for_reset_r_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_15,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(12)
    );
\hotplug_count_synth.count_for_reset_r_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_14,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(13)
    );
\hotplug_count_synth.count_for_reset_r_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_13,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(14)
    );
\hotplug_count_synth.count_for_reset_r_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_12,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(15)
    );
\hotplug_count_synth.count_for_reset_r_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_19,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(16)
    );
\hotplug_count_synth.count_for_reset_r_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_18,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(17)
    );
\hotplug_count_synth.count_for_reset_r_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_17,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(18)
    );
\hotplug_count_synth.count_for_reset_r_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_16,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(19)
    );
\hotplug_count_synth.count_for_reset_r_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_2,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(1)
    );
\hotplug_count_synth.count_for_reset_r_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_23,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(20)
    );
\hotplug_count_synth.count_for_reset_r_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_22,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(21)
    );
\hotplug_count_synth.count_for_reset_r_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_21,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(22)
    );
\hotplug_count_synth.count_for_reset_r_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_20,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(23)
    );
\hotplug_count_synth.count_for_reset_r_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_25,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(24)
    );
\hotplug_count_synth.count_for_reset_r_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_24,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(25)
    );
\hotplug_count_synth.count_for_reset_r_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_1,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(2)
    );
\hotplug_count_synth.count_for_reset_r_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_0,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(3)
    );
\hotplug_count_synth.count_for_reset_r_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_7,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(4)
    );
\hotplug_count_synth.count_for_reset_r_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_6,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(5)
    );
\hotplug_count_synth.count_for_reset_r_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_5,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(6)
    );
\hotplug_count_synth.count_for_reset_r_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_4,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(7)
    );
\hotplug_count_synth.count_for_reset_r_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_11,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(8)
    );
\hotplug_count_synth.count_for_reset_r_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => HPCNT_RESET,
      D => rx_cc_cdc_sync_n_10,
      Q => \hotplug_count_synth.count_for_reset_r_reg\(9)
    );
\hotplug_enable.LINK_RESET_OUT_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_r,
      Q => link_reset_lane2_i,
      R => '0'
    );
\link_reset_r_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \link_reset_r_i_2__1_n_0\,
      I1 => \link_reset_r_i_3__1_n_0\,
      I2 => \link_reset_r_i_4__1_n_0\,
      I3 => \link_reset_r_i_5__1_n_0\,
      I4 => \link_reset_r_i_6__1_n_0\,
      O => link_reset_0
    );
\link_reset_r_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(7),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(6),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(5),
      O => \link_reset_r_i_2__1_n_0\
    );
\link_reset_r_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78F8F8F8"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(2),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(3),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(4),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(1),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(0),
      O => \link_reset_r_i_3__1_n_0\
    );
\link_reset_r_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(16),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(17),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(14),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(15),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(19),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(18),
      O => \link_reset_r_i_4__1_n_0\
    );
\link_reset_r_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(10),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(11),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(8),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(9),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(13),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(12),
      O => \link_reset_r_i_5__1_n_0\
    );
\link_reset_r_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \hotplug_count_synth.count_for_reset_r_reg\(22),
      I1 => \hotplug_count_synth.count_for_reset_r_reg\(23),
      I2 => \hotplug_count_synth.count_for_reset_r_reg\(20),
      I3 => \hotplug_count_synth.count_for_reset_r_reg\(21),
      I4 => \hotplug_count_synth.count_for_reset_r_reg\(25),
      I5 => \hotplug_count_synth.count_for_reset_r_reg\(24),
      O => \link_reset_r_i_6__1_n_0\
    );
link_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => link_reset_0,
      Q => link_reset_r,
      R => '0'
    );
rx_cc_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_10\
     port map (
      O(3) => rx_cc_cdc_sync_n_0,
      O(2) => rx_cc_cdc_sync_n_1,
      O(1) => rx_cc_cdc_sync_n_2,
      O(0) => rx_cc_cdc_sync_n_3,
      \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0) => \hotplug_count_synth.count_for_reset_r_reg\(25 downto 0),
      \hotplug_count_synth.count_for_reset_r_reg[11]\(3) => rx_cc_cdc_sync_n_8,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(2) => rx_cc_cdc_sync_n_9,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(1) => rx_cc_cdc_sync_n_10,
      \hotplug_count_synth.count_for_reset_r_reg[11]\(0) => rx_cc_cdc_sync_n_11,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(3) => rx_cc_cdc_sync_n_12,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(2) => rx_cc_cdc_sync_n_13,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(1) => rx_cc_cdc_sync_n_14,
      \hotplug_count_synth.count_for_reset_r_reg[15]\(0) => rx_cc_cdc_sync_n_15,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(3) => rx_cc_cdc_sync_n_16,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(2) => rx_cc_cdc_sync_n_17,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(1) => rx_cc_cdc_sync_n_18,
      \hotplug_count_synth.count_for_reset_r_reg[19]\(0) => rx_cc_cdc_sync_n_19,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(3) => rx_cc_cdc_sync_n_20,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(2) => rx_cc_cdc_sync_n_21,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(1) => rx_cc_cdc_sync_n_22,
      \hotplug_count_synth.count_for_reset_r_reg[23]\(0) => rx_cc_cdc_sync_n_23,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(1) => rx_cc_cdc_sync_n_24,
      \hotplug_count_synth.count_for_reset_r_reg[25]\(0) => rx_cc_cdc_sync_n_25,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(3) => rx_cc_cdc_sync_n_4,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(2) => rx_cc_cdc_sync_n_5,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(1) => rx_cc_cdc_sync_n_6,
      \hotplug_count_synth.count_for_reset_r_reg[7]\(0) => rx_cc_cdc_sync_n_7,
      init_clk_in => init_clk_in,
      rx_cc_extend_r2 => rx_cc_extend_r2,
      user_clk => user_clk
    );
rx_cc_extend_r2_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => rx_cc_extend_r(2),
      I1 => rx_cc_extend_r(3),
      I2 => rx_cc_extend_r(0),
      I3 => rx_cc_extend_r(1),
      I4 => rx_cc_extend_r2_i_2_n_0,
      O => rx_cc_extend_r2_i_1_n_0
    );
rx_cc_extend_r2_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rx_cc_extend_r(5),
      I1 => rx_cc_extend_r(4),
      I2 => rx_cc_extend_r(7),
      I3 => rx_cc_extend_r(6),
      O => rx_cc_extend_r2_i_2_n_0
    );
rx_cc_extend_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r2_i_1_n_0,
      Q => rx_cc_extend_r2,
      R => '0'
    );
\rx_cc_extend_r_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(1),
      Q => rx_cc_extend_r(0),
      R => SR(0)
    );
\rx_cc_extend_r_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(2),
      Q => rx_cc_extend_r(1),
      R => SR(0)
    );
\rx_cc_extend_r_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(3),
      Q => rx_cc_extend_r(2),
      R => SR(0)
    );
\rx_cc_extend_r_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(4),
      Q => rx_cc_extend_r(3),
      R => SR(0)
    );
\rx_cc_extend_r_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(5),
      Q => rx_cc_extend_r(4),
      R => SR(0)
    );
\rx_cc_extend_r_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(6),
      Q => rx_cc_extend_r(5),
      R => SR(0)
    );
\rx_cc_extend_r_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => rx_cc_extend_r(7),
      Q => rx_cc_extend_r(6),
      R => SR(0)
    );
\rx_cc_extend_r_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => rx_cc_extend_r(7),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RESET_LOGIC is
  port (
    SYSTEM_RESET_reg_0 : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    link_reset_r : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    TX_LOCK : in STD_LOGIC;
    gt_rxresetdone_r2_reg_0 : in STD_LOGIC;
    en_chan_sync_i : in STD_LOGIC
  );
end aurora_rx_4l_64b_RESET_LOGIC;

architecture STRUCTURE of aurora_rx_4l_64b_RESET_LOGIC is
  signal SYSTEM_RESET0_n_0 : STD_LOGIC;
  signal \^system_reset_reg_0\ : STD_LOGIC;
  signal gt_rxresetdone_r : STD_LOGIC;
  signal gt_rxresetdone_r2 : STD_LOGIC;
  signal gt_rxresetdone_r3 : STD_LOGIC;
  signal scndry_out : STD_LOGIC;
  signal tx_lock_comb_r : STD_LOGIC;
  signal tx_lock_sync : STD_LOGIC;
begin
  SYSTEM_RESET_reg_0 <= \^system_reset_reg_0\;
SYSTEM_RESET0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => tx_lock_sync,
      I1 => \out\,
      I2 => gt_rxresetdone_r3,
      I3 => scndry_out,
      O => SYSTEM_RESET0_n_0
    );
SYSTEM_RESET_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => SYSTEM_RESET0_n_0,
      Q => \^system_reset_reg_0\,
      R => '0'
    );
\ch_bond_done_dly_i[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^system_reset_reg_0\,
      I1 => en_chan_sync_i,
      O => SR(0)
    );
gt_rxresetdone_r2_reg: unisim.vcomponents.FDCE
     port map (
      C => user_clk,
      CE => '1',
      CLR => gt_rxresetdone_r2_reg_0,
      D => gt_rxresetdone_r,
      Q => gt_rxresetdone_r2
    );
gt_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt_rxresetdone_r2,
      Q => gt_rxresetdone_r3,
      R => '0'
    );
gt_rxresetdone_r_reg: unisim.vcomponents.FDCE
     port map (
      C => user_clk,
      CE => '1',
      CLR => gt_rxresetdone_r2_reg_0,
      D => '1',
      Q => gt_rxresetdone_r
    );
link_reset_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_36\
     port map (
      init_clk_in => init_clk_in,
      link_reset_r => link_reset_r,
      \out\ => scndry_out,
      user_clk => user_clk
    );
tx_lock_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_37\
     port map (
      init_clk_in => init_clk_in,
      \out\ => tx_lock_sync,
      tx_lock_comb_r => tx_lock_comb_r,
      user_clk => user_clk
    );
tx_lock_comb_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => TX_LOCK,
      Q => tx_lock_comb_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX is
  port (
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_1_i : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_2_i : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_lanes_flop_3_i : out STD_LOGIC_VECTOR ( 0 to 0 );
    en_chan_sync_i : out STD_LOGIC;
    CHANNEL_UP_Buffer_reg : out STD_LOGIC;
    start_rx_i : out STD_LOGIC;
    gtrxreset_i : out STD_LOGIC;
    SOFT_ERR : out STD_LOGIC;
    RX_HARD_ERR : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    START_RX_Buffer_reg : out STD_LOGIC;
    RESET : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    GOT_V : in STD_LOGIC;
    all_lanes_v_r_reg : in STD_LOGIC;
    all_lanes_v_r_reg_0 : in STD_LOGIC;
    all_lanes_v_r_reg_1 : in STD_LOGIC;
    bad_as_r0 : in STD_LOGIC;
    good_as_r0 : in STD_LOGIC;
    START_RX_Buffer_reg_0 : in STD_LOGIC;
    CHBONDDONE_OUT_LANE3 : in STD_LOGIC;
    CHBONDDONE_OUT : in STD_LOGIC;
    CHBONDDONE_OUT_LANE2 : in STD_LOGIC;
    CHBONDDONE_OUT_LANE1 : in STD_LOGIC;
    \soft_err_r_reg[0]\ : in STD_LOGIC;
    \soft_err_r_reg[1]\ : in STD_LOGIC;
    \soft_err_r_reg[2]\ : in STD_LOGIC;
    \soft_err_r_reg[3]\ : in STD_LOGIC;
    RX_SUF : in STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \hard_err_r_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    RX_LANE_UP : in STD_LOGIC_VECTOR ( 0 to 3 )
  );
end aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX;

architecture STRUCTURE of aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX is
  signal reset_channel_i : STD_LOGIC;
  signal wait_for_lane_up_r0 : STD_LOGIC;
begin
rx_channel_err_detect_simplex_i: entity work.aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX
     port map (
      POWER_DOWN => POWER_DOWN,
      RX_HARD_ERR => RX_HARD_ERR,
      RX_LANE_UP(0 to 3) => RX_LANE_UP(0 to 3),
      SOFT_ERR => SOFT_ERR,
      \hard_err_r_reg[0]_0\(3 downto 0) => \hard_err_r_reg[0]\(3 downto 0),
      reset_channel_i => reset_channel_i,
      \soft_err_r_reg[0]_0\ => \soft_err_r_reg[0]\,
      \soft_err_r_reg[1]_0\ => \soft_err_r_reg[1]\,
      \soft_err_r_reg[2]_0\ => \soft_err_r_reg[2]\,
      \soft_err_r_reg[3]_0\ => \soft_err_r_reg[3]\,
      user_clk => user_clk,
      wait_for_lane_up_r0 => wait_for_lane_up_r0,
      wait_for_lane_up_r_reg => START_RX_Buffer_reg_0
    );
rx_channel_init_sm_simplex_i: entity work.aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX
     port map (
      CHANNEL_UP_Buffer_reg_0 => CHANNEL_UP_Buffer_reg,
      CHBONDDONE_OUT => CHBONDDONE_OUT,
      CHBONDDONE_OUT_LANE1 => CHBONDDONE_OUT_LANE1,
      CHBONDDONE_OUT_LANE2 => CHBONDDONE_OUT_LANE2,
      CHBONDDONE_OUT_LANE3 => CHBONDDONE_OUT_LANE3,
      D(3 downto 0) => D(3 downto 0),
      GOT_V => GOT_V,
      Q(3 downto 0) => Q(3 downto 0),
      RESET => RESET,
      RX_SUF => RX_SUF,
      SR(0) => SR(0),
      START_RX_Buffer_reg_0 => START_RX_Buffer_reg,
      START_RX_Buffer_reg_1 => START_RX_Buffer_reg_0,
      all_lanes_v_r_reg_0 => all_lanes_v_r_reg,
      all_lanes_v_r_reg_1 => all_lanes_v_r_reg_0,
      all_lanes_v_r_reg_2 => all_lanes_v_r_reg_1,
      bad_as_r0 => bad_as_r0,
      en_chan_sync_i => en_chan_sync_i,
      good_as_r0 => good_as_r0,
      gtrxreset_i => gtrxreset_i,
      reset_channel_i => reset_channel_i,
      reset_lanes_flop_1_i_0(0) => reset_lanes_flop_1_i(0),
      reset_lanes_flop_2_i_0(0) => reset_lanes_flop_2_i(0),
      reset_lanes_flop_3_i_0(0) => reset_lanes_flop_3_i(0),
      start_rx_i => start_rx_i,
      user_clk => user_clk,
      wait_for_lane_up_r0 => wait_for_lane_up_r0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LL_PDU_DATAPATH is
  port (
    RX_EOF_N : out STD_LOGIC;
    FRAME_ERR : out STD_LOGIC;
    M_AXI_RX_TLAST : out STD_LOGIC;
    M_AXI_RX_TVALID : out STD_LOGIC;
    \RX_REM_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    in_frame_muxcy_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    in_frame_muxcy_1 : in STD_LOGIC;
    in_frame_muxcy_2 : in STD_LOGIC;
    in_frame_muxcy_3 : in STD_LOGIC;
    S5_in : in STD_LOGIC;
    S3_in : in STD_LOGIC;
    S1_in : in STD_LOGIC;
    data_after_start_muxcy_3 : in STD_LOGIC;
    RESET : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    pdu_pad_i : in STD_LOGIC_VECTOR ( 0 to 3 );
    start_rx_i : in STD_LOGIC;
    \DEFRAMED_DATA_V_Buffer_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \stage_2_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
end aurora_rx_4l_64b_RX_LL_PDU_DATAPATH;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LL_PDU_DATAPATH is
  signal EOF_N_Buffer : STD_LOGIC;
  signal FRAME_ERR_RESULT_Buffer : STD_LOGIC;
  signal FRAME_ERR_RESULT_Buffer0 : STD_LOGIC;
  signal \L__0\ : STD_LOGIC_VECTOR ( 1 to 3 );
  signal OUTPUT_SELECT_Buffer : STD_LOGIC_VECTOR ( 13 to 19 );
  signal \^rx_eof_n\ : STD_LOGIC;
  signal RX_REM_Buffer : STD_LOGIC_VECTOR ( 0 to 2 );
  signal SRC_RDY_N_Buffer : STD_LOGIC;
  signal STORAGE_DATA : STD_LOGIC_VECTOR ( 0 to 63 );
  signal \STORAGE_DATA_Buffer[0]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[10]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[11]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[12]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[13]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[14]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[15]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[16]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[17]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[18]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[19]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[1]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[20]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[21]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[22]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[23]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[24]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[25]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[26]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[27]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[28]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[29]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[2]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[30]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[31]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[32]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[33]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[34]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[35]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[36]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[37]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[38]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[39]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[3]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[40]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[41]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[42]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[43]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[44]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[45]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[46]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[47]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[48]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[49]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[4]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[50]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[51]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[52]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[53]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[54]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[55]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[56]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[57]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[58]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[59]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[5]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[60]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[61]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[62]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[63]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[6]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[7]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[8]_i_1_n_0\ : STD_LOGIC;
  signal \STORAGE_DATA_Buffer[9]_i_1_n_0\ : STD_LOGIC;
  signal STORAGE_SELECT_Buffer : STD_LOGIC_VECTOR ( 3 to 19 );
  signal ce_command_c : STD_LOGIC_VECTOR ( 0 to 2 );
  signal end_storage_r0 : STD_LOGIC;
  signal mux_select_c : STD_LOGIC_VECTOR ( 1 to 4 );
  signal \neqOp_inferred__0/i__n_0\ : STD_LOGIC;
  signal output_select_c : STD_LOGIC_VECTOR ( 13 to 18 );
  signal p_0_in0 : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_3_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_5_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal plusOp : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal rx_rem_c : STD_LOGIC_VECTOR ( 2 to 2 );
  signal rx_src_rdy : STD_LOGIC;
  signal sideband_output_i_n_1 : STD_LOGIC;
  signal stage_1_ecp_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal stage_1_pad_r : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_10 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_11 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_2 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_4 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_6 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_7 : STD_LOGIC;
  signal stage_1_rx_ll_deframer_i_n_8 : STD_LOGIC;
  signal stage_1_scp_r : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \stage_2_data_r_reg_n_0_[0]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[10]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[11]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[12]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[13]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[14]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[15]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[1]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[2]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[3]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[48]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[49]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[4]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[50]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[51]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[52]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[53]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[54]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[55]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[56]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[57]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[58]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[59]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[5]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[60]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[61]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[62]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[63]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[6]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[7]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[8]\ : STD_LOGIC;
  signal \stage_2_data_r_reg_n_0_[9]\ : STD_LOGIC;
  signal stage_2_end_after_start_r : STD_LOGIC;
  signal stage_2_end_before_start_r : STD_LOGIC;
  signal stage_2_frame_err_r : STD_LOGIC;
  signal stage_2_left_align_control_i_n_0 : STD_LOGIC;
  signal stage_2_left_align_control_i_n_1 : STD_LOGIC;
  signal stage_2_left_align_control_i_n_2 : STD_LOGIC;
  signal stage_2_left_align_control_i_n_3 : STD_LOGIC;
  signal stage_2_left_align_control_i_n_4 : STD_LOGIC;
  signal stage_2_pad_r : STD_LOGIC;
  signal stage_2_start_with_data_r : STD_LOGIC;
  signal stage_3_end_storage_r : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_0 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_1 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_10 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_11 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_12 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_13 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_14 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_15 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_16 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_17 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_18 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_19 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_2 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_20 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_21 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_22 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_23 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_24 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_25 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_26 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_27 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_28 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_29 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_3 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_30 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_31 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_4 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_48 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_49 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_5 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_50 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_51 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_52 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_53 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_54 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_55 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_56 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_57 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_58 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_59 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_6 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_60 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_61 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_62 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_63 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_7 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_8 : STD_LOGIC;
  signal stage_3_left_align_datapath_mux_i_n_9 : STD_LOGIC;
  signal stage_3_storage_ce_control_i_n_0 : STD_LOGIC;
  signal stage_3_storage_ce_control_i_n_1 : STD_LOGIC;
  signal stage_3_storage_ce_control_i_n_3 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_1 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_10 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_11 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_12 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_13 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_14 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_3 : STD_LOGIC;
  signal stage_3_storage_count_control_i_n_6 : STD_LOGIC;
  signal stage_3_storage_count_r : STD_LOGIC_VECTOR ( 1 to 2 );
  signal std_bool : STD_LOGIC;
  signal storage_count_c : STD_LOGIC_VECTOR ( 1 to 2 );
  signal take_storage_c : STD_LOGIC;
begin
  RX_EOF_N <= \^rx_eof_n\;
FRAME_ERR_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => FRAME_ERR_RESULT_Buffer,
      Q => FRAME_ERR,
      R => RESET
    );
M_AXI_RX_TLAST_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rx_eof_n\,
      O => M_AXI_RX_TLAST
    );
M_AXI_RX_TVALID_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_src_rdy,
      O => M_AXI_RX_TVALID
    );
RX_EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => EOF_N_Buffer,
      Q => \^rx_eof_n\,
      R => '0'
    );
\RX_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_REM_Buffer(0),
      Q => \RX_REM_Buffer_reg[0]_0\(2),
      R => '0'
    );
\RX_REM_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_REM_Buffer(1),
      Q => \RX_REM_Buffer_reg[0]_0\(1),
      R => '0'
    );
\RX_REM_Buffer_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => RX_REM_Buffer(2),
      Q => \RX_REM_Buffer_reg[0]_0\(0),
      R => '0'
    );
RX_SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => SRC_RDY_N_Buffer,
      Q => rx_src_rdy,
      S => RESET
    );
\STORAGE_DATA_Buffer[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_16,
      I1 => stage_3_left_align_datapath_mux_i_n_0,
      I2 => stage_3_left_align_datapath_mux_i_n_48,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(15),
      O => \STORAGE_DATA_Buffer[0]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_26,
      I1 => stage_3_left_align_datapath_mux_i_n_10,
      I2 => stage_3_left_align_datapath_mux_i_n_58,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(5),
      O => \STORAGE_DATA_Buffer[10]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_27,
      I1 => stage_3_left_align_datapath_mux_i_n_11,
      I2 => stage_3_left_align_datapath_mux_i_n_59,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(4),
      O => \STORAGE_DATA_Buffer[11]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_28,
      I1 => stage_3_left_align_datapath_mux_i_n_12,
      I2 => stage_3_left_align_datapath_mux_i_n_60,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(3),
      O => \STORAGE_DATA_Buffer[12]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_29,
      I1 => stage_3_left_align_datapath_mux_i_n_13,
      I2 => stage_3_left_align_datapath_mux_i_n_61,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(2),
      O => \STORAGE_DATA_Buffer[13]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_30,
      I1 => stage_3_left_align_datapath_mux_i_n_14,
      I2 => stage_3_left_align_datapath_mux_i_n_62,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(1),
      O => \STORAGE_DATA_Buffer[14]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_31,
      I1 => stage_3_left_align_datapath_mux_i_n_15,
      I2 => stage_3_left_align_datapath_mux_i_n_63,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(0),
      O => \STORAGE_DATA_Buffer[15]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_16,
      I1 => stage_3_left_align_datapath_mux_i_n_0,
      I2 => stage_3_left_align_datapath_mux_i_n_48,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(15),
      O => \STORAGE_DATA_Buffer[16]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_17,
      I1 => stage_3_left_align_datapath_mux_i_n_1,
      I2 => stage_3_left_align_datapath_mux_i_n_49,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(14),
      O => \STORAGE_DATA_Buffer[17]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_18,
      I1 => stage_3_left_align_datapath_mux_i_n_2,
      I2 => stage_3_left_align_datapath_mux_i_n_50,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(13),
      O => \STORAGE_DATA_Buffer[18]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_19,
      I1 => stage_3_left_align_datapath_mux_i_n_3,
      I2 => stage_3_left_align_datapath_mux_i_n_51,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(12),
      O => \STORAGE_DATA_Buffer[19]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_17,
      I1 => stage_3_left_align_datapath_mux_i_n_1,
      I2 => stage_3_left_align_datapath_mux_i_n_49,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(14),
      O => \STORAGE_DATA_Buffer[1]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_20,
      I1 => stage_3_left_align_datapath_mux_i_n_4,
      I2 => stage_3_left_align_datapath_mux_i_n_52,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(11),
      O => \STORAGE_DATA_Buffer[20]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_21,
      I1 => stage_3_left_align_datapath_mux_i_n_5,
      I2 => stage_3_left_align_datapath_mux_i_n_53,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(10),
      O => \STORAGE_DATA_Buffer[21]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_22,
      I1 => stage_3_left_align_datapath_mux_i_n_6,
      I2 => stage_3_left_align_datapath_mux_i_n_54,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(9),
      O => \STORAGE_DATA_Buffer[22]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_23,
      I1 => stage_3_left_align_datapath_mux_i_n_7,
      I2 => stage_3_left_align_datapath_mux_i_n_55,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(8),
      O => \STORAGE_DATA_Buffer[23]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_24,
      I1 => stage_3_left_align_datapath_mux_i_n_8,
      I2 => stage_3_left_align_datapath_mux_i_n_56,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(7),
      O => \STORAGE_DATA_Buffer[24]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_25,
      I1 => stage_3_left_align_datapath_mux_i_n_9,
      I2 => stage_3_left_align_datapath_mux_i_n_57,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(6),
      O => \STORAGE_DATA_Buffer[25]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_26,
      I1 => stage_3_left_align_datapath_mux_i_n_10,
      I2 => stage_3_left_align_datapath_mux_i_n_58,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(5),
      O => \STORAGE_DATA_Buffer[26]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_27,
      I1 => stage_3_left_align_datapath_mux_i_n_11,
      I2 => stage_3_left_align_datapath_mux_i_n_59,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(4),
      O => \STORAGE_DATA_Buffer[27]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_28,
      I1 => stage_3_left_align_datapath_mux_i_n_12,
      I2 => stage_3_left_align_datapath_mux_i_n_60,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(3),
      O => \STORAGE_DATA_Buffer[28]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_29,
      I1 => stage_3_left_align_datapath_mux_i_n_13,
      I2 => stage_3_left_align_datapath_mux_i_n_61,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(2),
      O => \STORAGE_DATA_Buffer[29]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_18,
      I1 => stage_3_left_align_datapath_mux_i_n_2,
      I2 => stage_3_left_align_datapath_mux_i_n_50,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(13),
      O => \STORAGE_DATA_Buffer[2]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_30,
      I1 => stage_3_left_align_datapath_mux_i_n_14,
      I2 => stage_3_left_align_datapath_mux_i_n_62,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(1),
      O => \STORAGE_DATA_Buffer[30]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_31,
      I1 => stage_3_left_align_datapath_mux_i_n_15,
      I2 => stage_3_left_align_datapath_mux_i_n_63,
      I3 => STORAGE_SELECT_Buffer(8),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(0),
      O => \STORAGE_DATA_Buffer[31]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_16,
      I1 => stage_3_left_align_datapath_mux_i_n_0,
      I2 => stage_3_left_align_datapath_mux_i_n_48,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(15),
      O => \STORAGE_DATA_Buffer[32]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_17,
      I1 => stage_3_left_align_datapath_mux_i_n_1,
      I2 => stage_3_left_align_datapath_mux_i_n_49,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(14),
      O => \STORAGE_DATA_Buffer[33]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_18,
      I1 => stage_3_left_align_datapath_mux_i_n_2,
      I2 => stage_3_left_align_datapath_mux_i_n_50,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(13),
      O => \STORAGE_DATA_Buffer[34]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_19,
      I1 => stage_3_left_align_datapath_mux_i_n_3,
      I2 => stage_3_left_align_datapath_mux_i_n_51,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(12),
      O => \STORAGE_DATA_Buffer[35]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_20,
      I1 => stage_3_left_align_datapath_mux_i_n_4,
      I2 => stage_3_left_align_datapath_mux_i_n_52,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(11),
      O => \STORAGE_DATA_Buffer[36]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_21,
      I1 => stage_3_left_align_datapath_mux_i_n_5,
      I2 => stage_3_left_align_datapath_mux_i_n_53,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(10),
      O => \STORAGE_DATA_Buffer[37]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_22,
      I1 => stage_3_left_align_datapath_mux_i_n_6,
      I2 => stage_3_left_align_datapath_mux_i_n_54,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(9),
      O => \STORAGE_DATA_Buffer[38]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_23,
      I1 => stage_3_left_align_datapath_mux_i_n_7,
      I2 => stage_3_left_align_datapath_mux_i_n_55,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(8),
      O => \STORAGE_DATA_Buffer[39]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_19,
      I1 => stage_3_left_align_datapath_mux_i_n_3,
      I2 => stage_3_left_align_datapath_mux_i_n_51,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(12),
      O => \STORAGE_DATA_Buffer[3]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_24,
      I1 => stage_3_left_align_datapath_mux_i_n_8,
      I2 => stage_3_left_align_datapath_mux_i_n_56,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(7),
      O => \STORAGE_DATA_Buffer[40]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_25,
      I1 => stage_3_left_align_datapath_mux_i_n_9,
      I2 => stage_3_left_align_datapath_mux_i_n_57,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(6),
      O => \STORAGE_DATA_Buffer[41]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_26,
      I1 => stage_3_left_align_datapath_mux_i_n_10,
      I2 => stage_3_left_align_datapath_mux_i_n_58,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(5),
      O => \STORAGE_DATA_Buffer[42]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_27,
      I1 => stage_3_left_align_datapath_mux_i_n_11,
      I2 => stage_3_left_align_datapath_mux_i_n_59,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(4),
      O => \STORAGE_DATA_Buffer[43]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_28,
      I1 => stage_3_left_align_datapath_mux_i_n_12,
      I2 => stage_3_left_align_datapath_mux_i_n_60,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(3),
      O => \STORAGE_DATA_Buffer[44]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_29,
      I1 => stage_3_left_align_datapath_mux_i_n_13,
      I2 => stage_3_left_align_datapath_mux_i_n_61,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(2),
      O => \STORAGE_DATA_Buffer[45]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_30,
      I1 => stage_3_left_align_datapath_mux_i_n_14,
      I2 => stage_3_left_align_datapath_mux_i_n_62,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(1),
      O => \STORAGE_DATA_Buffer[46]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_31,
      I1 => stage_3_left_align_datapath_mux_i_n_15,
      I2 => stage_3_left_align_datapath_mux_i_n_63,
      I3 => STORAGE_SELECT_Buffer(13),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(0),
      O => \STORAGE_DATA_Buffer[47]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[48]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_16,
      I1 => stage_3_left_align_datapath_mux_i_n_0,
      I2 => stage_3_left_align_datapath_mux_i_n_48,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(15),
      O => \STORAGE_DATA_Buffer[48]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[49]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_17,
      I1 => stage_3_left_align_datapath_mux_i_n_1,
      I2 => stage_3_left_align_datapath_mux_i_n_49,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(14),
      O => \STORAGE_DATA_Buffer[49]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_20,
      I1 => stage_3_left_align_datapath_mux_i_n_4,
      I2 => stage_3_left_align_datapath_mux_i_n_52,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(11),
      O => \STORAGE_DATA_Buffer[4]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[50]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_18,
      I1 => stage_3_left_align_datapath_mux_i_n_2,
      I2 => stage_3_left_align_datapath_mux_i_n_50,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(13),
      O => \STORAGE_DATA_Buffer[50]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[51]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_19,
      I1 => stage_3_left_align_datapath_mux_i_n_3,
      I2 => stage_3_left_align_datapath_mux_i_n_51,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(12),
      O => \STORAGE_DATA_Buffer[51]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[52]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_20,
      I1 => stage_3_left_align_datapath_mux_i_n_4,
      I2 => stage_3_left_align_datapath_mux_i_n_52,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(11),
      O => \STORAGE_DATA_Buffer[52]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[53]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_21,
      I1 => stage_3_left_align_datapath_mux_i_n_5,
      I2 => stage_3_left_align_datapath_mux_i_n_53,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(10),
      O => \STORAGE_DATA_Buffer[53]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[54]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_22,
      I1 => stage_3_left_align_datapath_mux_i_n_6,
      I2 => stage_3_left_align_datapath_mux_i_n_54,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(9),
      O => \STORAGE_DATA_Buffer[54]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[55]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_23,
      I1 => stage_3_left_align_datapath_mux_i_n_7,
      I2 => stage_3_left_align_datapath_mux_i_n_55,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(8),
      O => \STORAGE_DATA_Buffer[55]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[56]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_24,
      I1 => stage_3_left_align_datapath_mux_i_n_8,
      I2 => stage_3_left_align_datapath_mux_i_n_56,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(7),
      O => \STORAGE_DATA_Buffer[56]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[57]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_25,
      I1 => stage_3_left_align_datapath_mux_i_n_9,
      I2 => stage_3_left_align_datapath_mux_i_n_57,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(6),
      O => \STORAGE_DATA_Buffer[57]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[58]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_26,
      I1 => stage_3_left_align_datapath_mux_i_n_10,
      I2 => stage_3_left_align_datapath_mux_i_n_58,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(5),
      O => \STORAGE_DATA_Buffer[58]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[59]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_27,
      I1 => stage_3_left_align_datapath_mux_i_n_11,
      I2 => stage_3_left_align_datapath_mux_i_n_59,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(4),
      O => \STORAGE_DATA_Buffer[59]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_21,
      I1 => stage_3_left_align_datapath_mux_i_n_5,
      I2 => stage_3_left_align_datapath_mux_i_n_53,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(10),
      O => \STORAGE_DATA_Buffer[5]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[60]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_28,
      I1 => stage_3_left_align_datapath_mux_i_n_12,
      I2 => stage_3_left_align_datapath_mux_i_n_60,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(3),
      O => \STORAGE_DATA_Buffer[60]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[61]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_29,
      I1 => stage_3_left_align_datapath_mux_i_n_13,
      I2 => stage_3_left_align_datapath_mux_i_n_61,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(2),
      O => \STORAGE_DATA_Buffer[61]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[62]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_30,
      I1 => stage_3_left_align_datapath_mux_i_n_14,
      I2 => stage_3_left_align_datapath_mux_i_n_62,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(1),
      O => \STORAGE_DATA_Buffer[62]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[63]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_31,
      I1 => stage_3_left_align_datapath_mux_i_n_15,
      I2 => stage_3_left_align_datapath_mux_i_n_63,
      I3 => STORAGE_SELECT_Buffer(18),
      I4 => STORAGE_SELECT_Buffer(19),
      I5 => p_1_in(0),
      O => \STORAGE_DATA_Buffer[63]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_22,
      I1 => stage_3_left_align_datapath_mux_i_n_6,
      I2 => stage_3_left_align_datapath_mux_i_n_54,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(9),
      O => \STORAGE_DATA_Buffer[6]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_23,
      I1 => stage_3_left_align_datapath_mux_i_n_7,
      I2 => stage_3_left_align_datapath_mux_i_n_55,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(8),
      O => \STORAGE_DATA_Buffer[7]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_24,
      I1 => stage_3_left_align_datapath_mux_i_n_8,
      I2 => stage_3_left_align_datapath_mux_i_n_56,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(7),
      O => \STORAGE_DATA_Buffer[8]_i_1_n_0\
    );
\STORAGE_DATA_Buffer[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => stage_3_left_align_datapath_mux_i_n_25,
      I1 => stage_3_left_align_datapath_mux_i_n_9,
      I2 => stage_3_left_align_datapath_mux_i_n_57,
      I3 => STORAGE_SELECT_Buffer(3),
      I4 => OUTPUT_SELECT_Buffer(19),
      I5 => p_1_in(6),
      O => \STORAGE_DATA_Buffer[9]_i_1_n_0\
    );
\neqOp_inferred__0/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => pdu_pad_i(2),
      I1 => pdu_pad_i(3),
      I2 => pdu_pad_i(1),
      I3 => pdu_pad_i(0),
      O => \neqOp_inferred__0/i__n_0\
    );
output_mux_i: entity work.aurora_rx_4l_64b_OUTPUT_MUX
     port map (
      M_AXI_RX_TDATA(63 downto 0) => M_AXI_RX_TDATA(63 downto 0),
      \OUTPUT_DATA_Buffer_reg[48]_0\(47) => stage_3_left_align_datapath_mux_i_n_0,
      \OUTPUT_DATA_Buffer_reg[48]_0\(46) => stage_3_left_align_datapath_mux_i_n_1,
      \OUTPUT_DATA_Buffer_reg[48]_0\(45) => stage_3_left_align_datapath_mux_i_n_2,
      \OUTPUT_DATA_Buffer_reg[48]_0\(44) => stage_3_left_align_datapath_mux_i_n_3,
      \OUTPUT_DATA_Buffer_reg[48]_0\(43) => stage_3_left_align_datapath_mux_i_n_4,
      \OUTPUT_DATA_Buffer_reg[48]_0\(42) => stage_3_left_align_datapath_mux_i_n_5,
      \OUTPUT_DATA_Buffer_reg[48]_0\(41) => stage_3_left_align_datapath_mux_i_n_6,
      \OUTPUT_DATA_Buffer_reg[48]_0\(40) => stage_3_left_align_datapath_mux_i_n_7,
      \OUTPUT_DATA_Buffer_reg[48]_0\(39) => stage_3_left_align_datapath_mux_i_n_8,
      \OUTPUT_DATA_Buffer_reg[48]_0\(38) => stage_3_left_align_datapath_mux_i_n_9,
      \OUTPUT_DATA_Buffer_reg[48]_0\(37) => stage_3_left_align_datapath_mux_i_n_10,
      \OUTPUT_DATA_Buffer_reg[48]_0\(36) => stage_3_left_align_datapath_mux_i_n_11,
      \OUTPUT_DATA_Buffer_reg[48]_0\(35) => stage_3_left_align_datapath_mux_i_n_12,
      \OUTPUT_DATA_Buffer_reg[48]_0\(34) => stage_3_left_align_datapath_mux_i_n_13,
      \OUTPUT_DATA_Buffer_reg[48]_0\(33) => stage_3_left_align_datapath_mux_i_n_14,
      \OUTPUT_DATA_Buffer_reg[48]_0\(32) => stage_3_left_align_datapath_mux_i_n_15,
      \OUTPUT_DATA_Buffer_reg[48]_0\(31) => stage_3_left_align_datapath_mux_i_n_16,
      \OUTPUT_DATA_Buffer_reg[48]_0\(30) => stage_3_left_align_datapath_mux_i_n_17,
      \OUTPUT_DATA_Buffer_reg[48]_0\(29) => stage_3_left_align_datapath_mux_i_n_18,
      \OUTPUT_DATA_Buffer_reg[48]_0\(28) => stage_3_left_align_datapath_mux_i_n_19,
      \OUTPUT_DATA_Buffer_reg[48]_0\(27) => stage_3_left_align_datapath_mux_i_n_20,
      \OUTPUT_DATA_Buffer_reg[48]_0\(26) => stage_3_left_align_datapath_mux_i_n_21,
      \OUTPUT_DATA_Buffer_reg[48]_0\(25) => stage_3_left_align_datapath_mux_i_n_22,
      \OUTPUT_DATA_Buffer_reg[48]_0\(24) => stage_3_left_align_datapath_mux_i_n_23,
      \OUTPUT_DATA_Buffer_reg[48]_0\(23) => stage_3_left_align_datapath_mux_i_n_24,
      \OUTPUT_DATA_Buffer_reg[48]_0\(22) => stage_3_left_align_datapath_mux_i_n_25,
      \OUTPUT_DATA_Buffer_reg[48]_0\(21) => stage_3_left_align_datapath_mux_i_n_26,
      \OUTPUT_DATA_Buffer_reg[48]_0\(20) => stage_3_left_align_datapath_mux_i_n_27,
      \OUTPUT_DATA_Buffer_reg[48]_0\(19) => stage_3_left_align_datapath_mux_i_n_28,
      \OUTPUT_DATA_Buffer_reg[48]_0\(18) => stage_3_left_align_datapath_mux_i_n_29,
      \OUTPUT_DATA_Buffer_reg[48]_0\(17) => stage_3_left_align_datapath_mux_i_n_30,
      \OUTPUT_DATA_Buffer_reg[48]_0\(16) => stage_3_left_align_datapath_mux_i_n_31,
      \OUTPUT_DATA_Buffer_reg[48]_0\(15 downto 0) => p_1_in(15 downto 0),
      OUTPUT_SELECT_Buffer(3) => OUTPUT_SELECT_Buffer(13),
      OUTPUT_SELECT_Buffer(2) => OUTPUT_SELECT_Buffer(14),
      OUTPUT_SELECT_Buffer(1) => OUTPUT_SELECT_Buffer(18),
      OUTPUT_SELECT_Buffer(0) => OUTPUT_SELECT_Buffer(19),
      Q(63) => STORAGE_DATA(0),
      Q(62) => STORAGE_DATA(1),
      Q(61) => STORAGE_DATA(2),
      Q(60) => STORAGE_DATA(3),
      Q(59) => STORAGE_DATA(4),
      Q(58) => STORAGE_DATA(5),
      Q(57) => STORAGE_DATA(6),
      Q(56) => STORAGE_DATA(7),
      Q(55) => STORAGE_DATA(8),
      Q(54) => STORAGE_DATA(9),
      Q(53) => STORAGE_DATA(10),
      Q(52) => STORAGE_DATA(11),
      Q(51) => STORAGE_DATA(12),
      Q(50) => STORAGE_DATA(13),
      Q(49) => STORAGE_DATA(14),
      Q(48) => STORAGE_DATA(15),
      Q(47) => STORAGE_DATA(16),
      Q(46) => STORAGE_DATA(17),
      Q(45) => STORAGE_DATA(18),
      Q(44) => STORAGE_DATA(19),
      Q(43) => STORAGE_DATA(20),
      Q(42) => STORAGE_DATA(21),
      Q(41) => STORAGE_DATA(22),
      Q(40) => STORAGE_DATA(23),
      Q(39) => STORAGE_DATA(24),
      Q(38) => STORAGE_DATA(25),
      Q(37) => STORAGE_DATA(26),
      Q(36) => STORAGE_DATA(27),
      Q(35) => STORAGE_DATA(28),
      Q(34) => STORAGE_DATA(29),
      Q(33) => STORAGE_DATA(30),
      Q(32) => STORAGE_DATA(31),
      Q(31) => STORAGE_DATA(32),
      Q(30) => STORAGE_DATA(33),
      Q(29) => STORAGE_DATA(34),
      Q(28) => STORAGE_DATA(35),
      Q(27) => STORAGE_DATA(36),
      Q(26) => STORAGE_DATA(37),
      Q(25) => STORAGE_DATA(38),
      Q(24) => STORAGE_DATA(39),
      Q(23) => STORAGE_DATA(40),
      Q(22) => STORAGE_DATA(41),
      Q(21) => STORAGE_DATA(42),
      Q(20) => STORAGE_DATA(43),
      Q(19) => STORAGE_DATA(44),
      Q(18) => STORAGE_DATA(45),
      Q(17) => STORAGE_DATA(46),
      Q(16) => STORAGE_DATA(47),
      Q(15) => STORAGE_DATA(48),
      Q(14) => STORAGE_DATA(49),
      Q(13) => STORAGE_DATA(50),
      Q(12) => STORAGE_DATA(51),
      Q(11) => STORAGE_DATA(52),
      Q(10) => STORAGE_DATA(53),
      Q(9) => STORAGE_DATA(54),
      Q(8) => STORAGE_DATA(55),
      Q(7) => STORAGE_DATA(56),
      Q(6) => STORAGE_DATA(57),
      Q(5) => STORAGE_DATA(58),
      Q(4) => STORAGE_DATA(59),
      Q(3) => STORAGE_DATA(60),
      Q(2) => STORAGE_DATA(61),
      Q(1) => STORAGE_DATA(62),
      Q(0) => STORAGE_DATA(63),
      user_clk => user_clk
    );
sideband_output_i: entity work.aurora_rx_4l_64b_SIDEBAND_OUTPUT
     port map (
      D(0) => rx_rem_c(2),
      EOF_N_Buffer => EOF_N_Buffer,
      EOF_N_Buffer_reg_0 => stage_3_storage_count_control_i_n_14,
      FRAME_ERR_RESULT_Buffer => FRAME_ERR_RESULT_Buffer,
      FRAME_ERR_RESULT_Buffer0 => FRAME_ERR_RESULT_Buffer0,
      Q(0) => \L__0\(3),
      \RX_REM_Buffer_reg[0]_0\(2) => RX_REM_Buffer(0),
      \RX_REM_Buffer_reg[0]_0\(1) => RX_REM_Buffer(1),
      \RX_REM_Buffer_reg[0]_0\(0) => RX_REM_Buffer(2),
      \RX_REM_Buffer_reg[1]_0\(0) => stage_3_storage_count_r(2),
      SR(0) => take_storage_c,
      SRC_RDY_N_Buffer => SRC_RDY_N_Buffer,
      end_storage_r0 => end_storage_r0,
      pad_storage_r_reg_0 => stage_3_storage_count_control_i_n_6,
      stage_2_end_before_start_r => stage_2_end_before_start_r,
      stage_2_frame_err_r => stage_2_frame_err_r,
      stage_2_frame_err_r_reg => sideband_output_i_n_1,
      stage_2_pad_r => stage_2_pad_r,
      stage_2_start_with_data_r => stage_2_start_with_data_r,
      stage_2_start_with_data_r_reg(0) => storage_count_c(2),
      stage_3_end_storage_r => stage_3_end_storage_r,
      start_rx_i => start_rx_i,
      user_clk => user_clk
    );
\stage_1_ecp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(3),
      Q => stage_1_ecp_r(0),
      R => '0'
    );
\stage_1_ecp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(2),
      Q => stage_1_ecp_r(1),
      R => '0'
    );
\stage_1_ecp_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(1),
      Q => stage_1_ecp_r(2),
      R => '0'
    );
\stage_1_ecp_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => D(0),
      Q => stage_1_ecp_r(3),
      R => '0'
    );
stage_1_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \neqOp_inferred__0/i__n_0\,
      Q => stage_1_pad_r,
      R => '0'
    );
stage_1_rx_ll_deframer_i: entity work.aurora_rx_4l_64b_RX_LL_DEFRAMER
     port map (
      \AFTER_SCP_Buffer_reg[3]_0\ => stage_1_rx_ll_deframer_i_n_8,
      \AFTER_SCP_Buffer_reg[3]_1\ => stage_1_rx_ll_deframer_i_n_10,
      D(2 downto 1) => plusOp(2 downto 1),
      D(0) => stage_1_rx_ll_deframer_i_n_2,
      \DEFRAMED_DATA_V_Buffer_reg[0]_0\(3 downto 0) => \DEFRAMED_DATA_V_Buffer_reg[0]\(3 downto 0),
      \DEFRAMED_DATA_V_Buffer_reg[2]_0\(4) => mux_select_c(1),
      \DEFRAMED_DATA_V_Buffer_reg[2]_0\(3) => stage_1_rx_ll_deframer_i_n_4,
      \DEFRAMED_DATA_V_Buffer_reg[2]_0\(2) => mux_select_c(4),
      \DEFRAMED_DATA_V_Buffer_reg[2]_0\(1) => stage_1_rx_ll_deframer_i_n_6,
      \DEFRAMED_DATA_V_Buffer_reg[2]_0\(0) => stage_1_rx_ll_deframer_i_n_7,
      Q(3 downto 0) => Q(3 downto 0),
      RESET => RESET,
      S1_in => S1_in,
      S3_in => S3_in,
      S5_in => S5_in,
      data_after_start_muxcy_3_0 => data_after_start_muxcy_3,
      in_frame_muxcy_0_0 => in_frame_muxcy_0,
      in_frame_muxcy_1_0 => in_frame_muxcy_1,
      in_frame_muxcy_2_0 => in_frame_muxcy_2,
      in_frame_muxcy_3_0 => in_frame_muxcy_3,
      \stage_1_ecp_r_reg[3]\ => stage_1_rx_ll_deframer_i_n_11,
      stage_2_frame_err_r_reg(3) => stage_1_scp_r(0),
      stage_2_frame_err_r_reg(2) => stage_1_scp_r(1),
      stage_2_frame_err_r_reg(1) => stage_1_scp_r(2),
      stage_2_frame_err_r_reg(0) => stage_1_scp_r(3),
      stage_2_frame_err_r_reg_0(3) => stage_1_ecp_r(0),
      stage_2_frame_err_r_reg_0(2) => stage_1_ecp_r(1),
      stage_2_frame_err_r_reg_0(1) => stage_1_ecp_r(2),
      stage_2_frame_err_r_reg_0(0) => stage_1_ecp_r(3),
      std_bool => std_bool,
      user_clk => user_clk
    );
\stage_1_scp_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(3),
      Q => stage_1_scp_r(0),
      R => '0'
    );
\stage_1_scp_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(2),
      Q => stage_1_scp_r(1),
      R => '0'
    );
\stage_1_scp_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(1),
      Q => stage_1_scp_r(2),
      R => '0'
    );
\stage_1_scp_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => Q(0),
      Q => stage_1_scp_r(3),
      R => '0'
    );
\stage_2_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(63),
      Q => \stage_2_data_r_reg_n_0_[0]\,
      R => '0'
    );
\stage_2_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(53),
      Q => \stage_2_data_r_reg_n_0_[10]\,
      R => '0'
    );
\stage_2_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(52),
      Q => \stage_2_data_r_reg_n_0_[11]\,
      R => '0'
    );
\stage_2_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(51),
      Q => \stage_2_data_r_reg_n_0_[12]\,
      R => '0'
    );
\stage_2_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(50),
      Q => \stage_2_data_r_reg_n_0_[13]\,
      R => '0'
    );
\stage_2_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(49),
      Q => \stage_2_data_r_reg_n_0_[14]\,
      R => '0'
    );
\stage_2_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(48),
      Q => \stage_2_data_r_reg_n_0_[15]\,
      R => '0'
    );
\stage_2_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(47),
      Q => p_5_in(15),
      R => '0'
    );
\stage_2_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(46),
      Q => p_5_in(14),
      R => '0'
    );
\stage_2_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(45),
      Q => p_5_in(13),
      R => '0'
    );
\stage_2_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(44),
      Q => p_5_in(12),
      R => '0'
    );
\stage_2_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(62),
      Q => \stage_2_data_r_reg_n_0_[1]\,
      R => '0'
    );
\stage_2_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(43),
      Q => p_5_in(11),
      R => '0'
    );
\stage_2_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(42),
      Q => p_5_in(10),
      R => '0'
    );
\stage_2_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(41),
      Q => p_5_in(9),
      R => '0'
    );
\stage_2_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(40),
      Q => p_5_in(8),
      R => '0'
    );
\stage_2_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(39),
      Q => p_5_in(7),
      R => '0'
    );
\stage_2_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(38),
      Q => p_5_in(6),
      R => '0'
    );
\stage_2_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(37),
      Q => p_5_in(5),
      R => '0'
    );
\stage_2_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(36),
      Q => p_5_in(4),
      R => '0'
    );
\stage_2_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(35),
      Q => p_5_in(3),
      R => '0'
    );
\stage_2_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(34),
      Q => p_5_in(2),
      R => '0'
    );
\stage_2_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(61),
      Q => \stage_2_data_r_reg_n_0_[2]\,
      R => '0'
    );
\stage_2_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(33),
      Q => p_5_in(1),
      R => '0'
    );
\stage_2_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(32),
      Q => p_5_in(0),
      R => '0'
    );
\stage_2_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(31),
      Q => p_3_in(15),
      R => '0'
    );
\stage_2_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(30),
      Q => p_3_in(14),
      R => '0'
    );
\stage_2_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(29),
      Q => p_3_in(13),
      R => '0'
    );
\stage_2_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(28),
      Q => p_3_in(12),
      R => '0'
    );
\stage_2_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(27),
      Q => p_3_in(11),
      R => '0'
    );
\stage_2_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(26),
      Q => p_3_in(10),
      R => '0'
    );
\stage_2_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(25),
      Q => p_3_in(9),
      R => '0'
    );
\stage_2_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(24),
      Q => p_3_in(8),
      R => '0'
    );
\stage_2_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(60),
      Q => \stage_2_data_r_reg_n_0_[3]\,
      R => '0'
    );
\stage_2_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(23),
      Q => p_3_in(7),
      R => '0'
    );
\stage_2_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(22),
      Q => p_3_in(6),
      R => '0'
    );
\stage_2_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(21),
      Q => p_3_in(5),
      R => '0'
    );
\stage_2_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(20),
      Q => p_3_in(4),
      R => '0'
    );
\stage_2_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(19),
      Q => p_3_in(3),
      R => '0'
    );
\stage_2_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(18),
      Q => p_3_in(2),
      R => '0'
    );
\stage_2_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(17),
      Q => p_3_in(1),
      R => '0'
    );
\stage_2_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(16),
      Q => p_3_in(0),
      R => '0'
    );
\stage_2_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(15),
      Q => \stage_2_data_r_reg_n_0_[48]\,
      R => '0'
    );
\stage_2_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(14),
      Q => \stage_2_data_r_reg_n_0_[49]\,
      R => '0'
    );
\stage_2_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(59),
      Q => \stage_2_data_r_reg_n_0_[4]\,
      R => '0'
    );
\stage_2_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(13),
      Q => \stage_2_data_r_reg_n_0_[50]\,
      R => '0'
    );
\stage_2_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(12),
      Q => \stage_2_data_r_reg_n_0_[51]\,
      R => '0'
    );
\stage_2_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(11),
      Q => \stage_2_data_r_reg_n_0_[52]\,
      R => '0'
    );
\stage_2_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(10),
      Q => \stage_2_data_r_reg_n_0_[53]\,
      R => '0'
    );
\stage_2_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(9),
      Q => \stage_2_data_r_reg_n_0_[54]\,
      R => '0'
    );
\stage_2_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(8),
      Q => \stage_2_data_r_reg_n_0_[55]\,
      R => '0'
    );
\stage_2_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(7),
      Q => \stage_2_data_r_reg_n_0_[56]\,
      R => '0'
    );
\stage_2_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(6),
      Q => \stage_2_data_r_reg_n_0_[57]\,
      R => '0'
    );
\stage_2_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(5),
      Q => \stage_2_data_r_reg_n_0_[58]\,
      R => '0'
    );
\stage_2_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(4),
      Q => \stage_2_data_r_reg_n_0_[59]\,
      R => '0'
    );
\stage_2_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(58),
      Q => \stage_2_data_r_reg_n_0_[5]\,
      R => '0'
    );
\stage_2_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(3),
      Q => \stage_2_data_r_reg_n_0_[60]\,
      R => '0'
    );
\stage_2_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(2),
      Q => \stage_2_data_r_reg_n_0_[61]\,
      R => '0'
    );
\stage_2_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(1),
      Q => \stage_2_data_r_reg_n_0_[62]\,
      R => '0'
    );
\stage_2_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(0),
      Q => \stage_2_data_r_reg_n_0_[63]\,
      R => '0'
    );
\stage_2_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(57),
      Q => \stage_2_data_r_reg_n_0_[6]\,
      R => '0'
    );
\stage_2_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(56),
      Q => \stage_2_data_r_reg_n_0_[7]\,
      R => '0'
    );
\stage_2_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(55),
      Q => \stage_2_data_r_reg_n_0_[8]\,
      R => '0'
    );
\stage_2_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_2_data_r_reg[0]_0\(54),
      Q => \stage_2_data_r_reg_n_0_[9]\,
      R => '0'
    );
stage_2_end_after_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_rx_ll_deframer_i_n_10,
      Q => stage_2_end_after_start_r,
      R => RESET
    );
stage_2_end_before_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => std_bool,
      Q => stage_2_end_before_start_r,
      R => RESET
    );
stage_2_frame_err_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_rx_ll_deframer_i_n_11,
      Q => stage_2_frame_err_r,
      R => RESET
    );
stage_2_left_align_control_i: entity work.aurora_rx_4l_64b_LEFT_ALIGN_CONTROL
     port map (
      D(4) => mux_select_c(1),
      D(3) => stage_1_rx_ll_deframer_i_n_4,
      D(2) => mux_select_c(4),
      D(1) => stage_1_rx_ll_deframer_i_n_6,
      D(0) => stage_1_rx_ll_deframer_i_n_7,
      Q(4) => stage_2_left_align_control_i_n_0,
      Q(3) => stage_2_left_align_control_i_n_1,
      Q(2) => stage_2_left_align_control_i_n_2,
      Q(1) => stage_2_left_align_control_i_n_3,
      Q(0) => stage_2_left_align_control_i_n_4,
      user_clk => user_clk
    );
stage_2_pad_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_pad_r,
      Q => stage_2_pad_r,
      R => '0'
    );
stage_2_start_with_data_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => stage_1_rx_ll_deframer_i_n_8,
      Q => stage_2_start_with_data_r,
      R => RESET
    );
stage_2_valid_data_counter_i: entity work.aurora_rx_4l_64b_VALID_DATA_COUNTER_5
     port map (
      \COUNT_Buffer_reg[0]_0\(2 downto 1) => plusOp(2 downto 1),
      \COUNT_Buffer_reg[0]_0\(0) => stage_1_rx_ll_deframer_i_n_2,
      D(0) => storage_count_c(1),
      Q(2) => \L__0\(1),
      Q(1) => \L__0\(2),
      Q(0) => \L__0\(3),
      RESET => RESET,
      stage_2_start_with_data_r => stage_2_start_with_data_r,
      stage_3_end_storage_r => stage_3_end_storage_r,
      \storage_count_r_reg[1]\(1) => stage_3_storage_count_r(1),
      \storage_count_r_reg[1]\(0) => stage_3_storage_count_r(2),
      user_clk => user_clk
    );
stage_3_left_align_datapath_mux_i: entity work.aurora_rx_4l_64b_LEFT_ALIGN_MUX
     port map (
      \MUXED_DATA_Buffer_reg[0]_0\(63) => stage_3_left_align_datapath_mux_i_n_0,
      \MUXED_DATA_Buffer_reg[0]_0\(62) => stage_3_left_align_datapath_mux_i_n_1,
      \MUXED_DATA_Buffer_reg[0]_0\(61) => stage_3_left_align_datapath_mux_i_n_2,
      \MUXED_DATA_Buffer_reg[0]_0\(60) => stage_3_left_align_datapath_mux_i_n_3,
      \MUXED_DATA_Buffer_reg[0]_0\(59) => stage_3_left_align_datapath_mux_i_n_4,
      \MUXED_DATA_Buffer_reg[0]_0\(58) => stage_3_left_align_datapath_mux_i_n_5,
      \MUXED_DATA_Buffer_reg[0]_0\(57) => stage_3_left_align_datapath_mux_i_n_6,
      \MUXED_DATA_Buffer_reg[0]_0\(56) => stage_3_left_align_datapath_mux_i_n_7,
      \MUXED_DATA_Buffer_reg[0]_0\(55) => stage_3_left_align_datapath_mux_i_n_8,
      \MUXED_DATA_Buffer_reg[0]_0\(54) => stage_3_left_align_datapath_mux_i_n_9,
      \MUXED_DATA_Buffer_reg[0]_0\(53) => stage_3_left_align_datapath_mux_i_n_10,
      \MUXED_DATA_Buffer_reg[0]_0\(52) => stage_3_left_align_datapath_mux_i_n_11,
      \MUXED_DATA_Buffer_reg[0]_0\(51) => stage_3_left_align_datapath_mux_i_n_12,
      \MUXED_DATA_Buffer_reg[0]_0\(50) => stage_3_left_align_datapath_mux_i_n_13,
      \MUXED_DATA_Buffer_reg[0]_0\(49) => stage_3_left_align_datapath_mux_i_n_14,
      \MUXED_DATA_Buffer_reg[0]_0\(48) => stage_3_left_align_datapath_mux_i_n_15,
      \MUXED_DATA_Buffer_reg[0]_0\(47) => stage_3_left_align_datapath_mux_i_n_16,
      \MUXED_DATA_Buffer_reg[0]_0\(46) => stage_3_left_align_datapath_mux_i_n_17,
      \MUXED_DATA_Buffer_reg[0]_0\(45) => stage_3_left_align_datapath_mux_i_n_18,
      \MUXED_DATA_Buffer_reg[0]_0\(44) => stage_3_left_align_datapath_mux_i_n_19,
      \MUXED_DATA_Buffer_reg[0]_0\(43) => stage_3_left_align_datapath_mux_i_n_20,
      \MUXED_DATA_Buffer_reg[0]_0\(42) => stage_3_left_align_datapath_mux_i_n_21,
      \MUXED_DATA_Buffer_reg[0]_0\(41) => stage_3_left_align_datapath_mux_i_n_22,
      \MUXED_DATA_Buffer_reg[0]_0\(40) => stage_3_left_align_datapath_mux_i_n_23,
      \MUXED_DATA_Buffer_reg[0]_0\(39) => stage_3_left_align_datapath_mux_i_n_24,
      \MUXED_DATA_Buffer_reg[0]_0\(38) => stage_3_left_align_datapath_mux_i_n_25,
      \MUXED_DATA_Buffer_reg[0]_0\(37) => stage_3_left_align_datapath_mux_i_n_26,
      \MUXED_DATA_Buffer_reg[0]_0\(36) => stage_3_left_align_datapath_mux_i_n_27,
      \MUXED_DATA_Buffer_reg[0]_0\(35) => stage_3_left_align_datapath_mux_i_n_28,
      \MUXED_DATA_Buffer_reg[0]_0\(34) => stage_3_left_align_datapath_mux_i_n_29,
      \MUXED_DATA_Buffer_reg[0]_0\(33) => stage_3_left_align_datapath_mux_i_n_30,
      \MUXED_DATA_Buffer_reg[0]_0\(32) => stage_3_left_align_datapath_mux_i_n_31,
      \MUXED_DATA_Buffer_reg[0]_0\(31 downto 16) => p_1_in(15 downto 0),
      \MUXED_DATA_Buffer_reg[0]_0\(15) => stage_3_left_align_datapath_mux_i_n_48,
      \MUXED_DATA_Buffer_reg[0]_0\(14) => stage_3_left_align_datapath_mux_i_n_49,
      \MUXED_DATA_Buffer_reg[0]_0\(13) => stage_3_left_align_datapath_mux_i_n_50,
      \MUXED_DATA_Buffer_reg[0]_0\(12) => stage_3_left_align_datapath_mux_i_n_51,
      \MUXED_DATA_Buffer_reg[0]_0\(11) => stage_3_left_align_datapath_mux_i_n_52,
      \MUXED_DATA_Buffer_reg[0]_0\(10) => stage_3_left_align_datapath_mux_i_n_53,
      \MUXED_DATA_Buffer_reg[0]_0\(9) => stage_3_left_align_datapath_mux_i_n_54,
      \MUXED_DATA_Buffer_reg[0]_0\(8) => stage_3_left_align_datapath_mux_i_n_55,
      \MUXED_DATA_Buffer_reg[0]_0\(7) => stage_3_left_align_datapath_mux_i_n_56,
      \MUXED_DATA_Buffer_reg[0]_0\(6) => stage_3_left_align_datapath_mux_i_n_57,
      \MUXED_DATA_Buffer_reg[0]_0\(5) => stage_3_left_align_datapath_mux_i_n_58,
      \MUXED_DATA_Buffer_reg[0]_0\(4) => stage_3_left_align_datapath_mux_i_n_59,
      \MUXED_DATA_Buffer_reg[0]_0\(3) => stage_3_left_align_datapath_mux_i_n_60,
      \MUXED_DATA_Buffer_reg[0]_0\(2) => stage_3_left_align_datapath_mux_i_n_61,
      \MUXED_DATA_Buffer_reg[0]_0\(1) => stage_3_left_align_datapath_mux_i_n_62,
      \MUXED_DATA_Buffer_reg[0]_0\(0) => stage_3_left_align_datapath_mux_i_n_63,
      \MUXED_DATA_Buffer_reg[0]_1\(4) => stage_2_left_align_control_i_n_0,
      \MUXED_DATA_Buffer_reg[0]_1\(3) => stage_2_left_align_control_i_n_1,
      \MUXED_DATA_Buffer_reg[0]_1\(2) => stage_2_left_align_control_i_n_2,
      \MUXED_DATA_Buffer_reg[0]_1\(1) => stage_2_left_align_control_i_n_3,
      \MUXED_DATA_Buffer_reg[0]_1\(0) => stage_2_left_align_control_i_n_4,
      Q(63) => \stage_2_data_r_reg_n_0_[0]\,
      Q(62) => \stage_2_data_r_reg_n_0_[1]\,
      Q(61) => \stage_2_data_r_reg_n_0_[2]\,
      Q(60) => \stage_2_data_r_reg_n_0_[3]\,
      Q(59) => \stage_2_data_r_reg_n_0_[4]\,
      Q(58) => \stage_2_data_r_reg_n_0_[5]\,
      Q(57) => \stage_2_data_r_reg_n_0_[6]\,
      Q(56) => \stage_2_data_r_reg_n_0_[7]\,
      Q(55) => \stage_2_data_r_reg_n_0_[8]\,
      Q(54) => \stage_2_data_r_reg_n_0_[9]\,
      Q(53) => \stage_2_data_r_reg_n_0_[10]\,
      Q(52) => \stage_2_data_r_reg_n_0_[11]\,
      Q(51) => \stage_2_data_r_reg_n_0_[12]\,
      Q(50) => \stage_2_data_r_reg_n_0_[13]\,
      Q(49) => \stage_2_data_r_reg_n_0_[14]\,
      Q(48) => \stage_2_data_r_reg_n_0_[15]\,
      Q(47 downto 32) => p_5_in(15 downto 0),
      Q(31 downto 16) => p_3_in(15 downto 0),
      Q(15) => \stage_2_data_r_reg_n_0_[48]\,
      Q(14) => \stage_2_data_r_reg_n_0_[49]\,
      Q(13) => \stage_2_data_r_reg_n_0_[50]\,
      Q(12) => \stage_2_data_r_reg_n_0_[51]\,
      Q(11) => \stage_2_data_r_reg_n_0_[52]\,
      Q(10) => \stage_2_data_r_reg_n_0_[53]\,
      Q(9) => \stage_2_data_r_reg_n_0_[54]\,
      Q(8) => \stage_2_data_r_reg_n_0_[55]\,
      Q(7) => \stage_2_data_r_reg_n_0_[56]\,
      Q(6) => \stage_2_data_r_reg_n_0_[57]\,
      Q(5) => \stage_2_data_r_reg_n_0_[58]\,
      Q(4) => \stage_2_data_r_reg_n_0_[59]\,
      Q(3) => \stage_2_data_r_reg_n_0_[60]\,
      Q(2) => \stage_2_data_r_reg_n_0_[61]\,
      Q(1) => \stage_2_data_r_reg_n_0_[62]\,
      Q(0) => \stage_2_data_r_reg_n_0_[63]\,
      user_clk => user_clk
    );
stage_3_output_switch_control_i: entity work.aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL
     port map (
      D(2) => output_select_c(13),
      D(1) => output_select_c(14),
      D(0) => output_select_c(18),
      OUTPUT_SELECT_Buffer(3) => OUTPUT_SELECT_Buffer(13),
      OUTPUT_SELECT_Buffer(2) => OUTPUT_SELECT_Buffer(14),
      OUTPUT_SELECT_Buffer(1) => OUTPUT_SELECT_Buffer(18),
      OUTPUT_SELECT_Buffer(0) => OUTPUT_SELECT_Buffer(19),
      Q(0) => stage_3_storage_count_r(2),
      SR(0) => take_storage_c,
      user_clk => user_clk
    );
stage_3_storage_ce_control_i: entity work.aurora_rx_4l_64b_STORAGE_CE_CONTROL
     port map (
      D(3) => ce_command_c(0),
      D(2) => stage_3_storage_count_control_i_n_1,
      D(1) => ce_command_c(2),
      D(0) => stage_3_storage_count_control_i_n_3,
      Q(3) => stage_3_storage_ce_control_i_n_0,
      Q(2) => stage_3_storage_ce_control_i_n_1,
      Q(1) => p_0_in0,
      Q(0) => stage_3_storage_ce_control_i_n_3,
      RESET => RESET,
      user_clk => user_clk
    );
stage_3_storage_count_control_i: entity work.aurora_rx_4l_64b_STORAGE_COUNT_CONTROL
     port map (
      D(3) => ce_command_c(0),
      D(2) => stage_3_storage_count_control_i_n_1,
      D(1) => ce_command_c(2),
      D(0) => stage_3_storage_count_control_i_n_3,
      FRAME_ERR_RESULT_Buffer0 => FRAME_ERR_RESULT_Buffer0,
      Q(1) => stage_3_storage_count_r(1),
      Q(0) => stage_3_storage_count_r(2),
      SR(0) => sideband_output_i_n_1,
      end_storage_r0 => end_storage_r0,
      end_storage_r_reg => stage_3_storage_count_control_i_n_6,
      stage_2_end_after_start_r => stage_2_end_after_start_r,
      stage_2_end_before_start_r => stage_2_end_before_start_r,
      stage_2_frame_err_r => stage_2_frame_err_r,
      stage_2_start_with_data_r => stage_2_start_with_data_r,
      stage_2_start_with_data_r_reg(0) => rx_rem_c(2),
      stage_3_end_storage_r => stage_3_end_storage_r,
      \storage_count_r_reg[0]_0\(2) => output_select_c(13),
      \storage_count_r_reg[0]_0\(1) => output_select_c(14),
      \storage_count_r_reg[0]_0\(0) => output_select_c(18),
      \storage_count_r_reg[0]_1\(2) => \L__0\(1),
      \storage_count_r_reg[0]_1\(1) => \L__0\(2),
      \storage_count_r_reg[0]_1\(0) => \L__0\(3),
      \storage_count_r_reg[1]_0\(3) => stage_3_storage_count_control_i_n_10,
      \storage_count_r_reg[1]_0\(2) => stage_3_storage_count_control_i_n_11,
      \storage_count_r_reg[1]_0\(1) => stage_3_storage_count_control_i_n_12,
      \storage_count_r_reg[1]_0\(0) => stage_3_storage_count_control_i_n_13,
      \storage_count_r_reg[1]_1\(1) => storage_count_c(1),
      \storage_count_r_reg[1]_1\(0) => storage_count_c(2),
      \storage_count_r_reg[2]_0\ => stage_3_storage_count_control_i_n_14,
      user_clk => user_clk
    );
stage_3_storage_switch_control_i: entity work.aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL
     port map (
      D(4) => stage_3_storage_count_control_i_n_10,
      D(3) => stage_3_storage_count_r(1),
      D(2) => stage_3_storage_count_control_i_n_11,
      D(1) => stage_3_storage_count_control_i_n_12,
      D(0) => stage_3_storage_count_control_i_n_13,
      Q(4) => STORAGE_SELECT_Buffer(3),
      Q(3) => STORAGE_SELECT_Buffer(8),
      Q(2) => STORAGE_SELECT_Buffer(13),
      Q(1) => STORAGE_SELECT_Buffer(18),
      Q(0) => STORAGE_SELECT_Buffer(19),
      SR(0) => take_storage_c,
      user_clk => user_clk
    );
stage_4_storage_mux_i: entity work.aurora_rx_4l_64b_STORAGE_MUX
     port map (
      D(63) => \STORAGE_DATA_Buffer[0]_i_1_n_0\,
      D(62) => \STORAGE_DATA_Buffer[1]_i_1_n_0\,
      D(61) => \STORAGE_DATA_Buffer[2]_i_1_n_0\,
      D(60) => \STORAGE_DATA_Buffer[3]_i_1_n_0\,
      D(59) => \STORAGE_DATA_Buffer[4]_i_1_n_0\,
      D(58) => \STORAGE_DATA_Buffer[5]_i_1_n_0\,
      D(57) => \STORAGE_DATA_Buffer[6]_i_1_n_0\,
      D(56) => \STORAGE_DATA_Buffer[7]_i_1_n_0\,
      D(55) => \STORAGE_DATA_Buffer[8]_i_1_n_0\,
      D(54) => \STORAGE_DATA_Buffer[9]_i_1_n_0\,
      D(53) => \STORAGE_DATA_Buffer[10]_i_1_n_0\,
      D(52) => \STORAGE_DATA_Buffer[11]_i_1_n_0\,
      D(51) => \STORAGE_DATA_Buffer[12]_i_1_n_0\,
      D(50) => \STORAGE_DATA_Buffer[13]_i_1_n_0\,
      D(49) => \STORAGE_DATA_Buffer[14]_i_1_n_0\,
      D(48) => \STORAGE_DATA_Buffer[15]_i_1_n_0\,
      D(47) => \STORAGE_DATA_Buffer[16]_i_1_n_0\,
      D(46) => \STORAGE_DATA_Buffer[17]_i_1_n_0\,
      D(45) => \STORAGE_DATA_Buffer[18]_i_1_n_0\,
      D(44) => \STORAGE_DATA_Buffer[19]_i_1_n_0\,
      D(43) => \STORAGE_DATA_Buffer[20]_i_1_n_0\,
      D(42) => \STORAGE_DATA_Buffer[21]_i_1_n_0\,
      D(41) => \STORAGE_DATA_Buffer[22]_i_1_n_0\,
      D(40) => \STORAGE_DATA_Buffer[23]_i_1_n_0\,
      D(39) => \STORAGE_DATA_Buffer[24]_i_1_n_0\,
      D(38) => \STORAGE_DATA_Buffer[25]_i_1_n_0\,
      D(37) => \STORAGE_DATA_Buffer[26]_i_1_n_0\,
      D(36) => \STORAGE_DATA_Buffer[27]_i_1_n_0\,
      D(35) => \STORAGE_DATA_Buffer[28]_i_1_n_0\,
      D(34) => \STORAGE_DATA_Buffer[29]_i_1_n_0\,
      D(33) => \STORAGE_DATA_Buffer[30]_i_1_n_0\,
      D(32) => \STORAGE_DATA_Buffer[31]_i_1_n_0\,
      D(31) => \STORAGE_DATA_Buffer[32]_i_1_n_0\,
      D(30) => \STORAGE_DATA_Buffer[33]_i_1_n_0\,
      D(29) => \STORAGE_DATA_Buffer[34]_i_1_n_0\,
      D(28) => \STORAGE_DATA_Buffer[35]_i_1_n_0\,
      D(27) => \STORAGE_DATA_Buffer[36]_i_1_n_0\,
      D(26) => \STORAGE_DATA_Buffer[37]_i_1_n_0\,
      D(25) => \STORAGE_DATA_Buffer[38]_i_1_n_0\,
      D(24) => \STORAGE_DATA_Buffer[39]_i_1_n_0\,
      D(23) => \STORAGE_DATA_Buffer[40]_i_1_n_0\,
      D(22) => \STORAGE_DATA_Buffer[41]_i_1_n_0\,
      D(21) => \STORAGE_DATA_Buffer[42]_i_1_n_0\,
      D(20) => \STORAGE_DATA_Buffer[43]_i_1_n_0\,
      D(19) => \STORAGE_DATA_Buffer[44]_i_1_n_0\,
      D(18) => \STORAGE_DATA_Buffer[45]_i_1_n_0\,
      D(17) => \STORAGE_DATA_Buffer[46]_i_1_n_0\,
      D(16) => \STORAGE_DATA_Buffer[47]_i_1_n_0\,
      D(15) => \STORAGE_DATA_Buffer[48]_i_1_n_0\,
      D(14) => \STORAGE_DATA_Buffer[49]_i_1_n_0\,
      D(13) => \STORAGE_DATA_Buffer[50]_i_1_n_0\,
      D(12) => \STORAGE_DATA_Buffer[51]_i_1_n_0\,
      D(11) => \STORAGE_DATA_Buffer[52]_i_1_n_0\,
      D(10) => \STORAGE_DATA_Buffer[53]_i_1_n_0\,
      D(9) => \STORAGE_DATA_Buffer[54]_i_1_n_0\,
      D(8) => \STORAGE_DATA_Buffer[55]_i_1_n_0\,
      D(7) => \STORAGE_DATA_Buffer[56]_i_1_n_0\,
      D(6) => \STORAGE_DATA_Buffer[57]_i_1_n_0\,
      D(5) => \STORAGE_DATA_Buffer[58]_i_1_n_0\,
      D(4) => \STORAGE_DATA_Buffer[59]_i_1_n_0\,
      D(3) => \STORAGE_DATA_Buffer[60]_i_1_n_0\,
      D(2) => \STORAGE_DATA_Buffer[61]_i_1_n_0\,
      D(1) => \STORAGE_DATA_Buffer[62]_i_1_n_0\,
      D(0) => \STORAGE_DATA_Buffer[63]_i_1_n_0\,
      E(3) => stage_3_storage_ce_control_i_n_0,
      E(2) => stage_3_storage_ce_control_i_n_1,
      E(1) => p_0_in0,
      E(0) => stage_3_storage_ce_control_i_n_3,
      Q(63) => STORAGE_DATA(0),
      Q(62) => STORAGE_DATA(1),
      Q(61) => STORAGE_DATA(2),
      Q(60) => STORAGE_DATA(3),
      Q(59) => STORAGE_DATA(4),
      Q(58) => STORAGE_DATA(5),
      Q(57) => STORAGE_DATA(6),
      Q(56) => STORAGE_DATA(7),
      Q(55) => STORAGE_DATA(8),
      Q(54) => STORAGE_DATA(9),
      Q(53) => STORAGE_DATA(10),
      Q(52) => STORAGE_DATA(11),
      Q(51) => STORAGE_DATA(12),
      Q(50) => STORAGE_DATA(13),
      Q(49) => STORAGE_DATA(14),
      Q(48) => STORAGE_DATA(15),
      Q(47) => STORAGE_DATA(16),
      Q(46) => STORAGE_DATA(17),
      Q(45) => STORAGE_DATA(18),
      Q(44) => STORAGE_DATA(19),
      Q(43) => STORAGE_DATA(20),
      Q(42) => STORAGE_DATA(21),
      Q(41) => STORAGE_DATA(22),
      Q(40) => STORAGE_DATA(23),
      Q(39) => STORAGE_DATA(24),
      Q(38) => STORAGE_DATA(25),
      Q(37) => STORAGE_DATA(26),
      Q(36) => STORAGE_DATA(27),
      Q(35) => STORAGE_DATA(28),
      Q(34) => STORAGE_DATA(29),
      Q(33) => STORAGE_DATA(30),
      Q(32) => STORAGE_DATA(31),
      Q(31) => STORAGE_DATA(32),
      Q(30) => STORAGE_DATA(33),
      Q(29) => STORAGE_DATA(34),
      Q(28) => STORAGE_DATA(35),
      Q(27) => STORAGE_DATA(36),
      Q(26) => STORAGE_DATA(37),
      Q(25) => STORAGE_DATA(38),
      Q(24) => STORAGE_DATA(39),
      Q(23) => STORAGE_DATA(40),
      Q(22) => STORAGE_DATA(41),
      Q(21) => STORAGE_DATA(42),
      Q(20) => STORAGE_DATA(43),
      Q(19) => STORAGE_DATA(44),
      Q(18) => STORAGE_DATA(45),
      Q(17) => STORAGE_DATA(46),
      Q(16) => STORAGE_DATA(47),
      Q(15) => STORAGE_DATA(48),
      Q(14) => STORAGE_DATA(49),
      Q(13) => STORAGE_DATA(50),
      Q(12) => STORAGE_DATA(51),
      Q(11) => STORAGE_DATA(52),
      Q(10) => STORAGE_DATA(53),
      Q(9) => STORAGE_DATA(54),
      Q(8) => STORAGE_DATA(55),
      Q(7) => STORAGE_DATA(56),
      Q(6) => STORAGE_DATA(57),
      Q(5) => STORAGE_DATA(58),
      Q(4) => STORAGE_DATA(59),
      Q(3) => STORAGE_DATA(60),
      Q(2) => STORAGE_DATA(61),
      Q(1) => STORAGE_DATA(62),
      Q(0) => STORAGE_DATA(63),
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LL_UFC_DATAPATH is
  port (
    \stage_1_data_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
    UFC_RX_EOF_N : out STD_LOGIC;
    M_AXI_UFC_RX_TLAST : out STD_LOGIC;
    M_AXI_UFC_RX_TVALID : out STD_LOGIC;
    \UFC_RX_REM_Buffer_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \stage_1_data_r_reg[7]_0\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \stage_1_data_r_reg[23]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[55]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[39]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[6]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[22]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[54]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[38]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[5]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[21]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[53]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[37]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[4]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[20]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[52]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[36]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[3]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[19]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[51]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[35]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[2]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[18]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[50]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[34]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[1]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[17]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[49]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[33]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[0]_1\ : in STD_LOGIC;
    \stage_1_data_r_reg[16]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[48]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[32]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[15]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[31]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[63]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[47]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[14]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[30]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[62]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[46]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[13]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[29]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[61]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[45]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[12]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[28]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[60]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[44]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[11]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[27]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[59]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[43]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[10]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[26]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[58]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[42]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[9]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[25]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[57]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[41]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[8]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[24]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[56]_0\ : in STD_LOGIC;
    \stage_1_data_r_reg[40]_0\ : in STD_LOGIC;
    RESET : in STD_LOGIC;
    ufc_start_i : in STD_LOGIC;
    \BARREL_SHIFTER_CONTROL_Buffer_reg[1]\ : in STD_LOGIC;
    \BARREL_SHIFTER_CONTROL_Buffer_reg[2]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
end aurora_rx_4l_64b_RX_LL_UFC_DATAPATH;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LL_UFC_DATAPATH is
  signal MUXED_DATA_Buffer : STD_LOGIC_VECTOR ( 0 to 63 );
  signal SHIFTED_DATA_Buffer : STD_LOGIC_VECTOR ( 0 to 15 );
  signal UFC_EOF_N_Buffer : STD_LOGIC;
  signal UFC_OUTPUT_SELECT_Buffer : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^ufc_rx_eof_n\ : STD_LOGIC;
  signal UFC_SRC_RDY_N_Buffer : STD_LOGIC;
  signal UFC_STORAGE_SELECT_Buffer : STD_LOGIC_VECTOR ( 0 to 11 );
  signal barrel_shifted_count_r : STD_LOGIC_VECTOR ( 0 to 2 );
  signal p_8_out : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal rx_ufc_src_rdy : STD_LOGIC;
  signal \^stage_1_data_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal stage_1_ufc_start_r : STD_LOGIC;
  signal storage_count_2x_c : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal ufc_barrel_shifter_control_i_n_0 : STD_LOGIC;
  signal ufc_barrel_shifter_control_i_n_1 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_0 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_100 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_101 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_102 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_103 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_104 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_105 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_106 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_107 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_108 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_109 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_110 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_111 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_17 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_18 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_19 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_20 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_21 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_22 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_23 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_24 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_25 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_26 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_27 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_28 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_29 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_30 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_31 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_32 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_33 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_34 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_35 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_36 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_37 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_38 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_39 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_40 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_41 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_42 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_43 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_44 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_45 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_46 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_47 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_48 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_49 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_50 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_51 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_52 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_53 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_54 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_55 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_56 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_57 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_58 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_59 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_60 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_61 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_62 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_63 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_64 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_65 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_66 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_67 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_68 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_69 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_70 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_71 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_72 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_73 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_74 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_75 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_76 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_77 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_78 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_79 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_96 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_97 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_98 : STD_LOGIC;
  signal ufc_barrel_shifter_i_n_99 : STD_LOGIC;
  signal ufc_output_select_c0_in : STD_LOGIC_VECTOR ( 9 to 9 );
  signal ufc_output_switch_control_i_n_0 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_10 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_11 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_12 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_13 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_14 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_15 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_16 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_17 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_18 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_19 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_20 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_6 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_7 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_8 : STD_LOGIC;
  signal ufc_output_switch_control_i_n_9 : STD_LOGIC;
  signal ufc_sideband_output_i_n_2 : STD_LOGIC;
  signal ufc_sideband_output_i_n_3 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_0 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_1 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_15 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_16 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_17 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_4 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_6 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_7 : STD_LOGIC;
  signal ufc_storage_count_control_i_n_8 : STD_LOGIC;
  signal ufc_storage_select_c : STD_LOGIC_VECTOR ( 3 to 11 );
begin
  UFC_RX_EOF_N <= \^ufc_rx_eof_n\;
  \stage_1_data_r_reg[0]_0\(63 downto 0) <= \^stage_1_data_r_reg[0]_0\(63 downto 0);
M_AXI_UFC_RX_TLAST_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ufc_rx_eof_n\,
      O => M_AXI_UFC_RX_TLAST
    );
M_AXI_UFC_RX_TVALID_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_ufc_src_rdy,
      O => M_AXI_UFC_RX_TVALID
    );
UFC_RX_EOF_N_Buffer_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_EOF_N_Buffer,
      Q => \^ufc_rx_eof_n\,
      R => '0'
    );
\UFC_RX_REM_Buffer_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ufc_sideband_output_i_n_2,
      Q => \UFC_RX_REM_Buffer_reg[0]_0\(1),
      R => '0'
    );
\UFC_RX_REM_Buffer_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ufc_sideband_output_i_n_3,
      Q => \UFC_RX_REM_Buffer_reg[0]_0\(0),
      R => '0'
    );
UFC_RX_SRC_RDY_N_Buffer_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => UFC_SRC_RDY_N_Buffer,
      Q => rx_ufc_src_rdy,
      S => RESET
    );
\stage_1_data_r_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[0]_1\,
      Q => \^stage_1_data_r_reg[0]_0\(63),
      R => '0'
    );
\stage_1_data_r_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[10]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(53),
      R => '0'
    );
\stage_1_data_r_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[11]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(52),
      R => '0'
    );
\stage_1_data_r_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[12]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(51),
      R => '0'
    );
\stage_1_data_r_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[13]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(50),
      R => '0'
    );
\stage_1_data_r_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[14]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(49),
      R => '0'
    );
\stage_1_data_r_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[15]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(48),
      R => '0'
    );
\stage_1_data_r_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[16]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(47),
      R => '0'
    );
\stage_1_data_r_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[17]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(46),
      R => '0'
    );
\stage_1_data_r_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[18]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(45),
      R => '0'
    );
\stage_1_data_r_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[19]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(44),
      R => '0'
    );
\stage_1_data_r_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[1]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(62),
      R => '0'
    );
\stage_1_data_r_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[20]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(43),
      R => '0'
    );
\stage_1_data_r_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[21]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(42),
      R => '0'
    );
\stage_1_data_r_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[22]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(41),
      R => '0'
    );
\stage_1_data_r_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[23]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(40),
      R => '0'
    );
\stage_1_data_r_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[24]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(39),
      R => '0'
    );
\stage_1_data_r_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[25]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(38),
      R => '0'
    );
\stage_1_data_r_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[26]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(37),
      R => '0'
    );
\stage_1_data_r_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[27]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(36),
      R => '0'
    );
\stage_1_data_r_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[28]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(35),
      R => '0'
    );
\stage_1_data_r_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[29]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(34),
      R => '0'
    );
\stage_1_data_r_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[2]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(61),
      R => '0'
    );
\stage_1_data_r_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[30]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(33),
      R => '0'
    );
\stage_1_data_r_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[31]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(32),
      R => '0'
    );
\stage_1_data_r_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[32]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(31),
      R => '0'
    );
\stage_1_data_r_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[33]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(30),
      R => '0'
    );
\stage_1_data_r_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[34]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(29),
      R => '0'
    );
\stage_1_data_r_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[35]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(28),
      R => '0'
    );
\stage_1_data_r_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[36]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(27),
      R => '0'
    );
\stage_1_data_r_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[37]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(26),
      R => '0'
    );
\stage_1_data_r_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[38]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(25),
      R => '0'
    );
\stage_1_data_r_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[39]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(24),
      R => '0'
    );
\stage_1_data_r_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[3]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(60),
      R => '0'
    );
\stage_1_data_r_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[40]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(23),
      R => '0'
    );
\stage_1_data_r_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[41]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(22),
      R => '0'
    );
\stage_1_data_r_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[42]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(21),
      R => '0'
    );
\stage_1_data_r_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[43]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(20),
      R => '0'
    );
\stage_1_data_r_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[44]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(19),
      R => '0'
    );
\stage_1_data_r_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[45]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(18),
      R => '0'
    );
\stage_1_data_r_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[46]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(17),
      R => '0'
    );
\stage_1_data_r_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[47]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(16),
      R => '0'
    );
\stage_1_data_r_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[48]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(15),
      R => '0'
    );
\stage_1_data_r_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[49]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(14),
      R => '0'
    );
\stage_1_data_r_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[4]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(59),
      R => '0'
    );
\stage_1_data_r_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[50]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(13),
      R => '0'
    );
\stage_1_data_r_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[51]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(12),
      R => '0'
    );
\stage_1_data_r_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[52]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(11),
      R => '0'
    );
\stage_1_data_r_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[53]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(10),
      R => '0'
    );
\stage_1_data_r_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[54]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(9),
      R => '0'
    );
\stage_1_data_r_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[55]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(8),
      R => '0'
    );
\stage_1_data_r_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[56]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(7),
      R => '0'
    );
\stage_1_data_r_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[57]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(6),
      R => '0'
    );
\stage_1_data_r_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[58]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(5),
      R => '0'
    );
\stage_1_data_r_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[59]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(4),
      R => '0'
    );
\stage_1_data_r_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[5]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(58),
      R => '0'
    );
\stage_1_data_r_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[60]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(3),
      R => '0'
    );
\stage_1_data_r_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[61]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(2),
      R => '0'
    );
\stage_1_data_r_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[62]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(1),
      R => '0'
    );
\stage_1_data_r_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[63]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(0),
      R => '0'
    );
\stage_1_data_r_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[6]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(57),
      R => '0'
    );
\stage_1_data_r_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[7]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(56),
      R => '0'
    );
\stage_1_data_r_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[8]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(55),
      R => '0'
    );
\stage_1_data_r_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \stage_1_data_r_reg[9]_0\,
      Q => \^stage_1_data_r_reg[0]_0\(54),
      R => '0'
    );
stage_1_ufc_start_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ufc_start_i,
      Q => stage_1_ufc_start_r,
      R => RESET
    );
ufc_barrel_shifter_control_i: entity work.aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL
     port map (
      \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0\ => ufc_barrel_shifter_control_i_n_0,
      \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1\ => \BARREL_SHIFTER_CONTROL_Buffer_reg[1]\,
      \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0\ => ufc_barrel_shifter_control_i_n_1,
      \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1\ => \BARREL_SHIFTER_CONTROL_Buffer_reg[2]\,
      user_clk => user_clk
    );
ufc_barrel_shifter_i: entity work.aurora_rx_4l_64b_UFC_BARREL_SHIFTER
     port map (
      D(15 downto 0) => p_8_out(31 downto 16),
      MUXED_DATA_Buffer(31) => MUXED_DATA_Buffer(32),
      MUXED_DATA_Buffer(30) => MUXED_DATA_Buffer(33),
      MUXED_DATA_Buffer(29) => MUXED_DATA_Buffer(34),
      MUXED_DATA_Buffer(28) => MUXED_DATA_Buffer(35),
      MUXED_DATA_Buffer(27) => MUXED_DATA_Buffer(36),
      MUXED_DATA_Buffer(26) => MUXED_DATA_Buffer(37),
      MUXED_DATA_Buffer(25) => MUXED_DATA_Buffer(38),
      MUXED_DATA_Buffer(24) => MUXED_DATA_Buffer(39),
      MUXED_DATA_Buffer(23) => MUXED_DATA_Buffer(40),
      MUXED_DATA_Buffer(22) => MUXED_DATA_Buffer(41),
      MUXED_DATA_Buffer(21) => MUXED_DATA_Buffer(42),
      MUXED_DATA_Buffer(20) => MUXED_DATA_Buffer(43),
      MUXED_DATA_Buffer(19) => MUXED_DATA_Buffer(44),
      MUXED_DATA_Buffer(18) => MUXED_DATA_Buffer(45),
      MUXED_DATA_Buffer(17) => MUXED_DATA_Buffer(46),
      MUXED_DATA_Buffer(16) => MUXED_DATA_Buffer(47),
      MUXED_DATA_Buffer(15) => MUXED_DATA_Buffer(48),
      MUXED_DATA_Buffer(14) => MUXED_DATA_Buffer(49),
      MUXED_DATA_Buffer(13) => MUXED_DATA_Buffer(50),
      MUXED_DATA_Buffer(12) => MUXED_DATA_Buffer(51),
      MUXED_DATA_Buffer(11) => MUXED_DATA_Buffer(52),
      MUXED_DATA_Buffer(10) => MUXED_DATA_Buffer(53),
      MUXED_DATA_Buffer(9) => MUXED_DATA_Buffer(54),
      MUXED_DATA_Buffer(8) => MUXED_DATA_Buffer(55),
      MUXED_DATA_Buffer(7) => MUXED_DATA_Buffer(56),
      MUXED_DATA_Buffer(6) => MUXED_DATA_Buffer(57),
      MUXED_DATA_Buffer(5) => MUXED_DATA_Buffer(58),
      MUXED_DATA_Buffer(4) => MUXED_DATA_Buffer(59),
      MUXED_DATA_Buffer(3) => MUXED_DATA_Buffer(60),
      MUXED_DATA_Buffer(2) => MUXED_DATA_Buffer(61),
      MUXED_DATA_Buffer(1) => MUXED_DATA_Buffer(62),
      MUXED_DATA_Buffer(0) => MUXED_DATA_Buffer(63),
      Q(15) => SHIFTED_DATA_Buffer(0),
      Q(14) => SHIFTED_DATA_Buffer(1),
      Q(13) => SHIFTED_DATA_Buffer(2),
      Q(12) => SHIFTED_DATA_Buffer(3),
      Q(11) => SHIFTED_DATA_Buffer(4),
      Q(10) => SHIFTED_DATA_Buffer(5),
      Q(9) => SHIFTED_DATA_Buffer(6),
      Q(8) => SHIFTED_DATA_Buffer(7),
      Q(7) => SHIFTED_DATA_Buffer(8),
      Q(6) => SHIFTED_DATA_Buffer(9),
      Q(5) => SHIFTED_DATA_Buffer(10),
      Q(4) => SHIFTED_DATA_Buffer(11),
      Q(3) => SHIFTED_DATA_Buffer(12),
      Q(2) => SHIFTED_DATA_Buffer(13),
      Q(1) => SHIFTED_DATA_Buffer(14),
      Q(0) => SHIFTED_DATA_Buffer(15),
      \SHIFTED_DATA_Buffer_reg[0]_0\ => \^stage_1_data_r_reg[0]_0\(31),
      \SHIFTED_DATA_Buffer_reg[0]_1\(31 downto 0) => \^stage_1_data_r_reg[0]_0\(63 downto 32),
      \SHIFTED_DATA_Buffer_reg[10]_0\ => \^stage_1_data_r_reg[0]_0\(21),
      \SHIFTED_DATA_Buffer_reg[11]_0\ => \^stage_1_data_r_reg[0]_0\(20),
      \SHIFTED_DATA_Buffer_reg[12]_0\ => \^stage_1_data_r_reg[0]_0\(19),
      \SHIFTED_DATA_Buffer_reg[13]_0\ => \^stage_1_data_r_reg[0]_0\(18),
      \SHIFTED_DATA_Buffer_reg[14]_0\ => \^stage_1_data_r_reg[0]_0\(17),
      \SHIFTED_DATA_Buffer_reg[15]_0\ => \^stage_1_data_r_reg[0]_0\(16),
      \SHIFTED_DATA_Buffer_reg[1]_0\ => \^stage_1_data_r_reg[0]_0\(30),
      \SHIFTED_DATA_Buffer_reg[2]_0\ => \^stage_1_data_r_reg[0]_0\(29),
      \SHIFTED_DATA_Buffer_reg[32]_0\ => ufc_barrel_shifter_i_n_96,
      \SHIFTED_DATA_Buffer_reg[32]_1\ => ufc_barrel_shifter_control_i_n_0,
      \SHIFTED_DATA_Buffer_reg[33]_0\ => ufc_barrel_shifter_i_n_97,
      \SHIFTED_DATA_Buffer_reg[34]_0\ => ufc_barrel_shifter_i_n_98,
      \SHIFTED_DATA_Buffer_reg[35]_0\ => ufc_barrel_shifter_i_n_99,
      \SHIFTED_DATA_Buffer_reg[36]_0\ => ufc_barrel_shifter_i_n_100,
      \SHIFTED_DATA_Buffer_reg[37]_0\ => ufc_barrel_shifter_i_n_101,
      \SHIFTED_DATA_Buffer_reg[38]_0\ => ufc_barrel_shifter_i_n_102,
      \SHIFTED_DATA_Buffer_reg[39]_0\ => ufc_barrel_shifter_i_n_103,
      \SHIFTED_DATA_Buffer_reg[3]_0\ => \^stage_1_data_r_reg[0]_0\(28),
      \SHIFTED_DATA_Buffer_reg[40]_0\ => ufc_barrel_shifter_i_n_104,
      \SHIFTED_DATA_Buffer_reg[41]_0\ => ufc_barrel_shifter_i_n_105,
      \SHIFTED_DATA_Buffer_reg[42]_0\ => ufc_barrel_shifter_i_n_106,
      \SHIFTED_DATA_Buffer_reg[43]_0\ => ufc_barrel_shifter_i_n_107,
      \SHIFTED_DATA_Buffer_reg[44]_0\ => ufc_barrel_shifter_i_n_108,
      \SHIFTED_DATA_Buffer_reg[45]_0\ => ufc_barrel_shifter_i_n_109,
      \SHIFTED_DATA_Buffer_reg[46]_0\ => ufc_barrel_shifter_i_n_110,
      \SHIFTED_DATA_Buffer_reg[47]_0\ => ufc_barrel_shifter_i_n_111,
      \SHIFTED_DATA_Buffer_reg[47]_1\ => ufc_barrel_shifter_control_i_n_1,
      \SHIFTED_DATA_Buffer_reg[48]_0\ => ufc_barrel_shifter_i_n_0,
      \SHIFTED_DATA_Buffer_reg[48]_1\ => ufc_barrel_shifter_i_n_17,
      \SHIFTED_DATA_Buffer_reg[48]_2\ => ufc_barrel_shifter_i_n_48,
      \SHIFTED_DATA_Buffer_reg[48]_3\ => ufc_barrel_shifter_i_n_49,
      \SHIFTED_DATA_Buffer_reg[48]_4\ => \^stage_1_data_r_reg[0]_0\(15),
      \SHIFTED_DATA_Buffer_reg[49]_0\ => ufc_barrel_shifter_i_n_18,
      \SHIFTED_DATA_Buffer_reg[49]_1\ => ufc_barrel_shifter_i_n_19,
      \SHIFTED_DATA_Buffer_reg[49]_2\ => ufc_barrel_shifter_i_n_50,
      \SHIFTED_DATA_Buffer_reg[49]_3\ => ufc_barrel_shifter_i_n_51,
      \SHIFTED_DATA_Buffer_reg[49]_4\ => \^stage_1_data_r_reg[0]_0\(14),
      \SHIFTED_DATA_Buffer_reg[4]_0\ => \^stage_1_data_r_reg[0]_0\(27),
      \SHIFTED_DATA_Buffer_reg[50]_0\ => ufc_barrel_shifter_i_n_20,
      \SHIFTED_DATA_Buffer_reg[50]_1\ => ufc_barrel_shifter_i_n_21,
      \SHIFTED_DATA_Buffer_reg[50]_2\ => ufc_barrel_shifter_i_n_52,
      \SHIFTED_DATA_Buffer_reg[50]_3\ => ufc_barrel_shifter_i_n_53,
      \SHIFTED_DATA_Buffer_reg[50]_4\ => \^stage_1_data_r_reg[0]_0\(13),
      \SHIFTED_DATA_Buffer_reg[51]_0\ => ufc_barrel_shifter_i_n_22,
      \SHIFTED_DATA_Buffer_reg[51]_1\ => ufc_barrel_shifter_i_n_23,
      \SHIFTED_DATA_Buffer_reg[51]_2\ => ufc_barrel_shifter_i_n_54,
      \SHIFTED_DATA_Buffer_reg[51]_3\ => ufc_barrel_shifter_i_n_55,
      \SHIFTED_DATA_Buffer_reg[51]_4\ => \^stage_1_data_r_reg[0]_0\(12),
      \SHIFTED_DATA_Buffer_reg[52]_0\ => ufc_barrel_shifter_i_n_24,
      \SHIFTED_DATA_Buffer_reg[52]_1\ => ufc_barrel_shifter_i_n_25,
      \SHIFTED_DATA_Buffer_reg[52]_2\ => ufc_barrel_shifter_i_n_56,
      \SHIFTED_DATA_Buffer_reg[52]_3\ => ufc_barrel_shifter_i_n_57,
      \SHIFTED_DATA_Buffer_reg[52]_4\ => \^stage_1_data_r_reg[0]_0\(11),
      \SHIFTED_DATA_Buffer_reg[53]_0\ => ufc_barrel_shifter_i_n_26,
      \SHIFTED_DATA_Buffer_reg[53]_1\ => ufc_barrel_shifter_i_n_27,
      \SHIFTED_DATA_Buffer_reg[53]_2\ => ufc_barrel_shifter_i_n_58,
      \SHIFTED_DATA_Buffer_reg[53]_3\ => ufc_barrel_shifter_i_n_59,
      \SHIFTED_DATA_Buffer_reg[53]_4\ => \^stage_1_data_r_reg[0]_0\(10),
      \SHIFTED_DATA_Buffer_reg[54]_0\ => ufc_barrel_shifter_i_n_28,
      \SHIFTED_DATA_Buffer_reg[54]_1\ => ufc_barrel_shifter_i_n_29,
      \SHIFTED_DATA_Buffer_reg[54]_2\ => ufc_barrel_shifter_i_n_60,
      \SHIFTED_DATA_Buffer_reg[54]_3\ => ufc_barrel_shifter_i_n_61,
      \SHIFTED_DATA_Buffer_reg[54]_4\ => \^stage_1_data_r_reg[0]_0\(9),
      \SHIFTED_DATA_Buffer_reg[55]_0\ => ufc_barrel_shifter_i_n_30,
      \SHIFTED_DATA_Buffer_reg[55]_1\ => ufc_barrel_shifter_i_n_31,
      \SHIFTED_DATA_Buffer_reg[55]_2\ => ufc_barrel_shifter_i_n_62,
      \SHIFTED_DATA_Buffer_reg[55]_3\ => ufc_barrel_shifter_i_n_63,
      \SHIFTED_DATA_Buffer_reg[55]_4\ => \^stage_1_data_r_reg[0]_0\(8),
      \SHIFTED_DATA_Buffer_reg[56]_0\ => ufc_barrel_shifter_i_n_32,
      \SHIFTED_DATA_Buffer_reg[56]_1\ => ufc_barrel_shifter_i_n_33,
      \SHIFTED_DATA_Buffer_reg[56]_2\ => ufc_barrel_shifter_i_n_64,
      \SHIFTED_DATA_Buffer_reg[56]_3\ => ufc_barrel_shifter_i_n_65,
      \SHIFTED_DATA_Buffer_reg[56]_4\ => \^stage_1_data_r_reg[0]_0\(7),
      \SHIFTED_DATA_Buffer_reg[57]_0\ => ufc_barrel_shifter_i_n_34,
      \SHIFTED_DATA_Buffer_reg[57]_1\ => ufc_barrel_shifter_i_n_35,
      \SHIFTED_DATA_Buffer_reg[57]_2\ => ufc_barrel_shifter_i_n_66,
      \SHIFTED_DATA_Buffer_reg[57]_3\ => ufc_barrel_shifter_i_n_67,
      \SHIFTED_DATA_Buffer_reg[57]_4\ => \^stage_1_data_r_reg[0]_0\(6),
      \SHIFTED_DATA_Buffer_reg[58]_0\ => ufc_barrel_shifter_i_n_36,
      \SHIFTED_DATA_Buffer_reg[58]_1\ => ufc_barrel_shifter_i_n_37,
      \SHIFTED_DATA_Buffer_reg[58]_2\ => ufc_barrel_shifter_i_n_68,
      \SHIFTED_DATA_Buffer_reg[58]_3\ => ufc_barrel_shifter_i_n_69,
      \SHIFTED_DATA_Buffer_reg[58]_4\ => \^stage_1_data_r_reg[0]_0\(5),
      \SHIFTED_DATA_Buffer_reg[59]_0\ => ufc_barrel_shifter_i_n_38,
      \SHIFTED_DATA_Buffer_reg[59]_1\ => ufc_barrel_shifter_i_n_39,
      \SHIFTED_DATA_Buffer_reg[59]_2\ => ufc_barrel_shifter_i_n_70,
      \SHIFTED_DATA_Buffer_reg[59]_3\ => ufc_barrel_shifter_i_n_71,
      \SHIFTED_DATA_Buffer_reg[59]_4\ => \^stage_1_data_r_reg[0]_0\(4),
      \SHIFTED_DATA_Buffer_reg[5]_0\ => \^stage_1_data_r_reg[0]_0\(26),
      \SHIFTED_DATA_Buffer_reg[60]_0\ => ufc_barrel_shifter_i_n_40,
      \SHIFTED_DATA_Buffer_reg[60]_1\ => ufc_barrel_shifter_i_n_41,
      \SHIFTED_DATA_Buffer_reg[60]_2\ => ufc_barrel_shifter_i_n_72,
      \SHIFTED_DATA_Buffer_reg[60]_3\ => ufc_barrel_shifter_i_n_73,
      \SHIFTED_DATA_Buffer_reg[60]_4\ => \^stage_1_data_r_reg[0]_0\(3),
      \SHIFTED_DATA_Buffer_reg[61]_0\ => ufc_barrel_shifter_i_n_42,
      \SHIFTED_DATA_Buffer_reg[61]_1\ => ufc_barrel_shifter_i_n_43,
      \SHIFTED_DATA_Buffer_reg[61]_2\ => ufc_barrel_shifter_i_n_74,
      \SHIFTED_DATA_Buffer_reg[61]_3\ => ufc_barrel_shifter_i_n_75,
      \SHIFTED_DATA_Buffer_reg[61]_4\ => \^stage_1_data_r_reg[0]_0\(2),
      \SHIFTED_DATA_Buffer_reg[62]_0\ => ufc_barrel_shifter_i_n_44,
      \SHIFTED_DATA_Buffer_reg[62]_1\ => ufc_barrel_shifter_i_n_45,
      \SHIFTED_DATA_Buffer_reg[62]_2\ => ufc_barrel_shifter_i_n_76,
      \SHIFTED_DATA_Buffer_reg[62]_3\ => ufc_barrel_shifter_i_n_77,
      \SHIFTED_DATA_Buffer_reg[62]_4\ => \^stage_1_data_r_reg[0]_0\(1),
      \SHIFTED_DATA_Buffer_reg[63]_0\ => ufc_barrel_shifter_i_n_46,
      \SHIFTED_DATA_Buffer_reg[63]_1\ => ufc_barrel_shifter_i_n_47,
      \SHIFTED_DATA_Buffer_reg[63]_2\ => ufc_barrel_shifter_i_n_78,
      \SHIFTED_DATA_Buffer_reg[63]_3\ => ufc_barrel_shifter_i_n_79,
      \SHIFTED_DATA_Buffer_reg[63]_4\ => \^stage_1_data_r_reg[0]_0\(0),
      \SHIFTED_DATA_Buffer_reg[6]_0\ => \^stage_1_data_r_reg[0]_0\(25),
      \SHIFTED_DATA_Buffer_reg[7]_0\ => \^stage_1_data_r_reg[0]_0\(24),
      \SHIFTED_DATA_Buffer_reg[8]_0\ => \^stage_1_data_r_reg[0]_0\(23),
      \SHIFTED_DATA_Buffer_reg[9]_0\ => \^stage_1_data_r_reg[0]_0\(22),
      UFC_OUTPUT_SELECT_Buffer(3 downto 2) => UFC_OUTPUT_SELECT_Buffer(4 downto 3),
      UFC_OUTPUT_SELECT_Buffer(1 downto 0) => UFC_OUTPUT_SELECT_Buffer(1 downto 0),
      UFC_STORAGE_SELECT_Buffer(5) => UFC_STORAGE_SELECT_Buffer(1),
      UFC_STORAGE_SELECT_Buffer(4) => UFC_STORAGE_SELECT_Buffer(4),
      UFC_STORAGE_SELECT_Buffer(3) => UFC_STORAGE_SELECT_Buffer(7),
      UFC_STORAGE_SELECT_Buffer(2) => UFC_STORAGE_SELECT_Buffer(8),
      UFC_STORAGE_SELECT_Buffer(1) => UFC_STORAGE_SELECT_Buffer(10),
      UFC_STORAGE_SELECT_Buffer(0) => UFC_STORAGE_SELECT_Buffer(11),
      user_clk => user_clk
    );
ufc_output_mux_i: entity work.aurora_rx_4l_64b_UFC_OUTPUT_MUX
     port map (
      D(31) => MUXED_DATA_Buffer(0),
      D(30) => MUXED_DATA_Buffer(1),
      D(29) => MUXED_DATA_Buffer(2),
      D(28) => MUXED_DATA_Buffer(3),
      D(27) => MUXED_DATA_Buffer(4),
      D(26) => MUXED_DATA_Buffer(5),
      D(25) => MUXED_DATA_Buffer(6),
      D(24) => MUXED_DATA_Buffer(7),
      D(23) => MUXED_DATA_Buffer(8),
      D(22) => MUXED_DATA_Buffer(9),
      D(21) => MUXED_DATA_Buffer(10),
      D(20) => MUXED_DATA_Buffer(11),
      D(19) => MUXED_DATA_Buffer(12),
      D(18) => MUXED_DATA_Buffer(13),
      D(17) => MUXED_DATA_Buffer(14),
      D(16) => MUXED_DATA_Buffer(15),
      D(15 downto 0) => p_8_out(31 downto 16),
      \MUXED_DATA_Buffer_reg[16]_0\ => ufc_output_switch_control_i_n_0,
      \MUXED_DATA_Buffer_reg[17]_0\ => ufc_output_switch_control_i_n_6,
      \MUXED_DATA_Buffer_reg[18]_0\ => ufc_output_switch_control_i_n_7,
      \MUXED_DATA_Buffer_reg[19]_0\ => ufc_output_switch_control_i_n_8,
      \MUXED_DATA_Buffer_reg[20]_0\ => ufc_output_switch_control_i_n_9,
      \MUXED_DATA_Buffer_reg[21]_0\ => ufc_output_switch_control_i_n_10,
      \MUXED_DATA_Buffer_reg[22]_0\ => ufc_output_switch_control_i_n_11,
      \MUXED_DATA_Buffer_reg[23]_0\ => ufc_output_switch_control_i_n_12,
      \MUXED_DATA_Buffer_reg[24]_0\ => ufc_output_switch_control_i_n_13,
      \MUXED_DATA_Buffer_reg[25]_0\ => ufc_output_switch_control_i_n_14,
      \MUXED_DATA_Buffer_reg[26]_0\ => ufc_output_switch_control_i_n_15,
      \MUXED_DATA_Buffer_reg[27]_0\ => ufc_output_switch_control_i_n_16,
      \MUXED_DATA_Buffer_reg[28]_0\ => ufc_output_switch_control_i_n_17,
      \MUXED_DATA_Buffer_reg[29]_0\ => ufc_output_switch_control_i_n_18,
      \MUXED_DATA_Buffer_reg[30]_0\ => ufc_output_switch_control_i_n_19,
      \MUXED_DATA_Buffer_reg[31]_0\ => ufc_output_switch_control_i_n_20,
      \MUXED_DATA_Buffer_reg[48]_0\ => ufc_barrel_shifter_i_n_96,
      \MUXED_DATA_Buffer_reg[49]_0\ => ufc_barrel_shifter_i_n_97,
      \MUXED_DATA_Buffer_reg[50]_0\ => ufc_barrel_shifter_i_n_98,
      \MUXED_DATA_Buffer_reg[51]_0\ => ufc_barrel_shifter_i_n_99,
      \MUXED_DATA_Buffer_reg[52]_0\ => ufc_barrel_shifter_i_n_100,
      \MUXED_DATA_Buffer_reg[53]_0\ => ufc_barrel_shifter_i_n_101,
      \MUXED_DATA_Buffer_reg[54]_0\ => ufc_barrel_shifter_i_n_102,
      \MUXED_DATA_Buffer_reg[55]_0\ => ufc_barrel_shifter_i_n_103,
      \MUXED_DATA_Buffer_reg[56]_0\ => ufc_barrel_shifter_i_n_104,
      \MUXED_DATA_Buffer_reg[57]_0\ => ufc_barrel_shifter_i_n_105,
      \MUXED_DATA_Buffer_reg[58]_0\ => ufc_barrel_shifter_i_n_106,
      \MUXED_DATA_Buffer_reg[59]_0\ => ufc_barrel_shifter_i_n_107,
      \MUXED_DATA_Buffer_reg[60]_0\ => ufc_barrel_shifter_i_n_108,
      \MUXED_DATA_Buffer_reg[61]_0\ => ufc_barrel_shifter_i_n_109,
      \MUXED_DATA_Buffer_reg[62]_0\ => ufc_barrel_shifter_i_n_110,
      \MUXED_DATA_Buffer_reg[63]_0\ => ufc_barrel_shifter_i_n_111,
      M_AXI_UFC_RX_TDATA(63 downto 0) => M_AXI_UFC_RX_TDATA(63 downto 0),
      UFC_OUTPUT_SELECT_Buffer(0) => UFC_OUTPUT_SELECT_Buffer(2),
      user_clk => user_clk
    );
ufc_output_switch_control_i: entity work.aurora_rx_4l_64b_UFC_OUTPUT_SWITCH_CONTROL
     port map (
      MUXED_DATA_Buffer(15) => MUXED_DATA_Buffer(16),
      MUXED_DATA_Buffer(14) => MUXED_DATA_Buffer(17),
      MUXED_DATA_Buffer(13) => MUXED_DATA_Buffer(18),
      MUXED_DATA_Buffer(12) => MUXED_DATA_Buffer(19),
      MUXED_DATA_Buffer(11) => MUXED_DATA_Buffer(20),
      MUXED_DATA_Buffer(10) => MUXED_DATA_Buffer(21),
      MUXED_DATA_Buffer(9) => MUXED_DATA_Buffer(22),
      MUXED_DATA_Buffer(8) => MUXED_DATA_Buffer(23),
      MUXED_DATA_Buffer(7) => MUXED_DATA_Buffer(24),
      MUXED_DATA_Buffer(6) => MUXED_DATA_Buffer(25),
      MUXED_DATA_Buffer(5) => MUXED_DATA_Buffer(26),
      MUXED_DATA_Buffer(4) => MUXED_DATA_Buffer(27),
      MUXED_DATA_Buffer(3) => MUXED_DATA_Buffer(28),
      MUXED_DATA_Buffer(2) => MUXED_DATA_Buffer(29),
      MUXED_DATA_Buffer(1) => MUXED_DATA_Buffer(30),
      MUXED_DATA_Buffer(0) => MUXED_DATA_Buffer(31),
      \MUXED_DATA_Buffer_reg[16]\ => ufc_output_switch_control_i_n_0,
      \MUXED_DATA_Buffer_reg[17]\ => ufc_output_switch_control_i_n_6,
      \MUXED_DATA_Buffer_reg[18]\ => ufc_output_switch_control_i_n_7,
      \MUXED_DATA_Buffer_reg[19]\ => ufc_output_switch_control_i_n_8,
      \MUXED_DATA_Buffer_reg[20]\ => ufc_output_switch_control_i_n_9,
      \MUXED_DATA_Buffer_reg[21]\ => ufc_output_switch_control_i_n_10,
      \MUXED_DATA_Buffer_reg[22]\ => ufc_output_switch_control_i_n_11,
      \MUXED_DATA_Buffer_reg[23]\ => ufc_output_switch_control_i_n_12,
      \MUXED_DATA_Buffer_reg[24]\ => ufc_output_switch_control_i_n_13,
      \MUXED_DATA_Buffer_reg[25]\ => ufc_output_switch_control_i_n_14,
      \MUXED_DATA_Buffer_reg[26]\ => ufc_output_switch_control_i_n_15,
      \MUXED_DATA_Buffer_reg[27]\ => ufc_output_switch_control_i_n_16,
      \MUXED_DATA_Buffer_reg[28]\ => ufc_output_switch_control_i_n_17,
      \MUXED_DATA_Buffer_reg[29]\ => ufc_output_switch_control_i_n_18,
      \MUXED_DATA_Buffer_reg[30]\ => ufc_output_switch_control_i_n_19,
      \MUXED_DATA_Buffer_reg[31]\ => ufc_output_switch_control_i_n_20,
      Q(15) => SHIFTED_DATA_Buffer(0),
      Q(14) => SHIFTED_DATA_Buffer(1),
      Q(13) => SHIFTED_DATA_Buffer(2),
      Q(12) => SHIFTED_DATA_Buffer(3),
      Q(11) => SHIFTED_DATA_Buffer(4),
      Q(10) => SHIFTED_DATA_Buffer(5),
      Q(9) => SHIFTED_DATA_Buffer(6),
      Q(8) => SHIFTED_DATA_Buffer(7),
      Q(7) => SHIFTED_DATA_Buffer(8),
      Q(6) => SHIFTED_DATA_Buffer(9),
      Q(5) => SHIFTED_DATA_Buffer(10),
      Q(4) => SHIFTED_DATA_Buffer(11),
      Q(3) => SHIFTED_DATA_Buffer(12),
      Q(2) => SHIFTED_DATA_Buffer(13),
      Q(1) => SHIFTED_DATA_Buffer(14),
      Q(0) => SHIFTED_DATA_Buffer(15),
      \UFC_OUTPUT_SELECT_Buffer_reg[7]_0\(4 downto 0) => UFC_OUTPUT_SELECT_Buffer(4 downto 0),
      \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(2) => ufc_storage_count_control_i_n_1,
      \UFC_OUTPUT_SELECT_Buffer_reg[7]_1\(1 downto 0) => storage_count_2x_c(2 downto 1),
      \UFC_OUTPUT_SELECT_Buffer_reg[9]_0\ => ufc_storage_count_control_i_n_4,
      user_clk => user_clk
    );
ufc_sideband_output_i: entity work.aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT
     port map (
      D(1) => ufc_storage_count_control_i_n_6,
      D(0) => ufc_storage_count_control_i_n_7,
      Q(1) => ufc_sideband_output_i_n_2,
      Q(0) => ufc_sideband_output_i_n_3,
      RESET => RESET,
      UFC_EOF_N_Buffer => UFC_EOF_N_Buffer,
      UFC_EOF_N_Buffer_reg_0 => ufc_storage_count_control_i_n_15,
      UFC_SRC_RDY_N_Buffer => UFC_SRC_RDY_N_Buffer,
      UFC_SRC_RDY_N_Buffer_reg_0 => ufc_storage_count_control_i_n_4,
      user_clk => user_clk
    );
ufc_storage_count_control_i: entity work.aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL
     port map (
      D(1) => ufc_storage_count_control_i_n_6,
      D(0) => ufc_storage_count_control_i_n_7,
      Q(2) => ufc_storage_count_control_i_n_1,
      Q(1 downto 0) => storage_count_2x_c(2 downto 1),
      RESET => RESET,
      stage_1_ufc_start_r => stage_1_ufc_start_r,
      \storage_count_r_reg[0]_0\ => ufc_storage_count_control_i_n_4,
      \storage_count_r_reg[0]_1\ => ufc_storage_count_control_i_n_8,
      \storage_count_r_reg[0]_2\(5) => ufc_storage_select_c(3),
      \storage_count_r_reg[0]_2\(4) => ufc_storage_select_c(4),
      \storage_count_r_reg[0]_2\(3) => ufc_storage_select_c(7),
      \storage_count_r_reg[0]_2\(2) => ufc_storage_select_c(8),
      \storage_count_r_reg[0]_2\(1) => ufc_storage_select_c(10),
      \storage_count_r_reg[0]_2\(0) => ufc_storage_select_c(11),
      \storage_count_r_reg[0]_3\ => ufc_storage_count_control_i_n_15,
      \storage_count_r_reg[0]_4\ => ufc_storage_count_control_i_n_16,
      \storage_count_r_reg[0]_5\ => ufc_storage_count_control_i_n_17,
      \storage_count_r_reg[0]_6\(2) => barrel_shifted_count_r(0),
      \storage_count_r_reg[0]_6\(1) => barrel_shifted_count_r(1),
      \storage_count_r_reg[0]_6\(0) => barrel_shifted_count_r(2),
      \storage_count_r_reg[1]_0\ => ufc_storage_count_control_i_n_0,
      ufc_output_select_c0_in(0) => ufc_output_select_c0_in(9),
      user_clk => user_clk
    );
ufc_storage_mux_i: entity work.aurora_rx_4l_64b_UFC_STORAGE_MUX
     port map (
      MUXED_DATA_Buffer(0 to 63) => MUXED_DATA_Buffer(0 to 63),
      \MUXED_DATA_Buffer_reg[0]_0\ => ufc_barrel_shifter_i_n_17,
      \MUXED_DATA_Buffer_reg[10]_0\ => ufc_barrel_shifter_i_n_37,
      \MUXED_DATA_Buffer_reg[11]_0\ => ufc_barrel_shifter_i_n_39,
      \MUXED_DATA_Buffer_reg[12]_0\ => ufc_barrel_shifter_i_n_41,
      \MUXED_DATA_Buffer_reg[13]_0\ => ufc_barrel_shifter_i_n_43,
      \MUXED_DATA_Buffer_reg[14]_0\ => ufc_barrel_shifter_i_n_45,
      \MUXED_DATA_Buffer_reg[15]_0\ => ufc_barrel_shifter_i_n_47,
      \MUXED_DATA_Buffer_reg[16]_0\ => ufc_barrel_shifter_i_n_49,
      \MUXED_DATA_Buffer_reg[17]_0\ => ufc_barrel_shifter_i_n_51,
      \MUXED_DATA_Buffer_reg[18]_0\ => ufc_barrel_shifter_i_n_53,
      \MUXED_DATA_Buffer_reg[19]_0\ => ufc_barrel_shifter_i_n_55,
      \MUXED_DATA_Buffer_reg[1]_0\ => ufc_barrel_shifter_i_n_19,
      \MUXED_DATA_Buffer_reg[20]_0\ => ufc_barrel_shifter_i_n_57,
      \MUXED_DATA_Buffer_reg[21]_0\ => ufc_barrel_shifter_i_n_59,
      \MUXED_DATA_Buffer_reg[22]_0\ => ufc_barrel_shifter_i_n_61,
      \MUXED_DATA_Buffer_reg[23]_0\ => ufc_barrel_shifter_i_n_63,
      \MUXED_DATA_Buffer_reg[24]_0\ => ufc_barrel_shifter_i_n_65,
      \MUXED_DATA_Buffer_reg[25]_0\ => ufc_barrel_shifter_i_n_67,
      \MUXED_DATA_Buffer_reg[26]_0\ => ufc_barrel_shifter_i_n_69,
      \MUXED_DATA_Buffer_reg[27]_0\ => ufc_barrel_shifter_i_n_71,
      \MUXED_DATA_Buffer_reg[28]_0\ => ufc_barrel_shifter_i_n_73,
      \MUXED_DATA_Buffer_reg[29]_0\ => ufc_barrel_shifter_i_n_75,
      \MUXED_DATA_Buffer_reg[2]_0\ => ufc_barrel_shifter_i_n_21,
      \MUXED_DATA_Buffer_reg[30]_0\ => ufc_barrel_shifter_i_n_77,
      \MUXED_DATA_Buffer_reg[31]_0\ => ufc_barrel_shifter_i_n_79,
      \MUXED_DATA_Buffer_reg[32]_0\ => ufc_barrel_shifter_i_n_0,
      \MUXED_DATA_Buffer_reg[33]_0\ => ufc_barrel_shifter_i_n_18,
      \MUXED_DATA_Buffer_reg[34]_0\ => ufc_barrel_shifter_i_n_20,
      \MUXED_DATA_Buffer_reg[35]_0\ => ufc_barrel_shifter_i_n_22,
      \MUXED_DATA_Buffer_reg[36]_0\ => ufc_barrel_shifter_i_n_24,
      \MUXED_DATA_Buffer_reg[37]_0\ => ufc_barrel_shifter_i_n_26,
      \MUXED_DATA_Buffer_reg[38]_0\ => ufc_barrel_shifter_i_n_28,
      \MUXED_DATA_Buffer_reg[39]_0\ => ufc_barrel_shifter_i_n_30,
      \MUXED_DATA_Buffer_reg[3]_0\ => ufc_barrel_shifter_i_n_23,
      \MUXED_DATA_Buffer_reg[40]_0\ => ufc_barrel_shifter_i_n_32,
      \MUXED_DATA_Buffer_reg[41]_0\ => ufc_barrel_shifter_i_n_34,
      \MUXED_DATA_Buffer_reg[42]_0\ => ufc_barrel_shifter_i_n_36,
      \MUXED_DATA_Buffer_reg[43]_0\ => ufc_barrel_shifter_i_n_38,
      \MUXED_DATA_Buffer_reg[44]_0\ => ufc_barrel_shifter_i_n_40,
      \MUXED_DATA_Buffer_reg[45]_0\ => ufc_barrel_shifter_i_n_42,
      \MUXED_DATA_Buffer_reg[46]_0\ => ufc_barrel_shifter_i_n_44,
      \MUXED_DATA_Buffer_reg[47]_0\ => ufc_barrel_shifter_i_n_46,
      \MUXED_DATA_Buffer_reg[48]_0\ => ufc_barrel_shifter_i_n_48,
      \MUXED_DATA_Buffer_reg[49]_0\ => ufc_barrel_shifter_i_n_50,
      \MUXED_DATA_Buffer_reg[4]_0\ => ufc_barrel_shifter_i_n_25,
      \MUXED_DATA_Buffer_reg[50]_0\ => ufc_barrel_shifter_i_n_52,
      \MUXED_DATA_Buffer_reg[51]_0\ => ufc_barrel_shifter_i_n_54,
      \MUXED_DATA_Buffer_reg[52]_0\ => ufc_barrel_shifter_i_n_56,
      \MUXED_DATA_Buffer_reg[53]_0\ => ufc_barrel_shifter_i_n_58,
      \MUXED_DATA_Buffer_reg[54]_0\ => ufc_barrel_shifter_i_n_60,
      \MUXED_DATA_Buffer_reg[55]_0\ => ufc_barrel_shifter_i_n_62,
      \MUXED_DATA_Buffer_reg[56]_0\ => ufc_barrel_shifter_i_n_64,
      \MUXED_DATA_Buffer_reg[57]_0\ => ufc_barrel_shifter_i_n_66,
      \MUXED_DATA_Buffer_reg[58]_0\ => ufc_barrel_shifter_i_n_68,
      \MUXED_DATA_Buffer_reg[59]_0\ => ufc_barrel_shifter_i_n_70,
      \MUXED_DATA_Buffer_reg[5]_0\ => ufc_barrel_shifter_i_n_27,
      \MUXED_DATA_Buffer_reg[60]_0\ => ufc_barrel_shifter_i_n_72,
      \MUXED_DATA_Buffer_reg[61]_0\ => ufc_barrel_shifter_i_n_74,
      \MUXED_DATA_Buffer_reg[62]_0\ => ufc_barrel_shifter_i_n_76,
      \MUXED_DATA_Buffer_reg[63]_0\ => ufc_barrel_shifter_i_n_78,
      \MUXED_DATA_Buffer_reg[6]_0\ => ufc_barrel_shifter_i_n_29,
      \MUXED_DATA_Buffer_reg[7]_0\ => ufc_barrel_shifter_i_n_31,
      \MUXED_DATA_Buffer_reg[8]_0\ => ufc_barrel_shifter_i_n_33,
      \MUXED_DATA_Buffer_reg[9]_0\ => ufc_barrel_shifter_i_n_35,
      UFC_STORAGE_SELECT_Buffer(3) => UFC_STORAGE_SELECT_Buffer(0),
      UFC_STORAGE_SELECT_Buffer(2) => UFC_STORAGE_SELECT_Buffer(3),
      UFC_STORAGE_SELECT_Buffer(1) => UFC_STORAGE_SELECT_Buffer(6),
      UFC_STORAGE_SELECT_Buffer(0) => UFC_STORAGE_SELECT_Buffer(9),
      user_clk => user_clk
    );
ufc_storage_switch_control_i: entity work.aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL
     port map (
      D(5) => ufc_storage_select_c(3),
      D(4) => ufc_storage_select_c(4),
      D(3) => ufc_storage_select_c(7),
      D(2) => ufc_storage_select_c(8),
      D(1) => ufc_storage_select_c(10),
      D(0) => ufc_storage_select_c(11),
      UFC_STORAGE_SELECT_Buffer(9) => UFC_STORAGE_SELECT_Buffer(0),
      UFC_STORAGE_SELECT_Buffer(8) => UFC_STORAGE_SELECT_Buffer(1),
      UFC_STORAGE_SELECT_Buffer(7) => UFC_STORAGE_SELECT_Buffer(3),
      UFC_STORAGE_SELECT_Buffer(6) => UFC_STORAGE_SELECT_Buffer(4),
      UFC_STORAGE_SELECT_Buffer(5) => UFC_STORAGE_SELECT_Buffer(6),
      UFC_STORAGE_SELECT_Buffer(4) => UFC_STORAGE_SELECT_Buffer(7),
      UFC_STORAGE_SELECT_Buffer(3) => UFC_STORAGE_SELECT_Buffer(8),
      UFC_STORAGE_SELECT_Buffer(2) => UFC_STORAGE_SELECT_Buffer(9),
      UFC_STORAGE_SELECT_Buffer(1) => UFC_STORAGE_SELECT_Buffer(10),
      UFC_STORAGE_SELECT_Buffer(0) => UFC_STORAGE_SELECT_Buffer(11),
      \UFC_STORAGE_SELECT_Buffer_reg[1]_0\ => ufc_storage_count_control_i_n_0,
      \UFC_STORAGE_SELECT_Buffer_reg[6]_0\ => ufc_storage_count_control_i_n_16,
      \UFC_STORAGE_SELECT_Buffer_reg[9]_0\ => ufc_storage_count_control_i_n_17,
      \UFC_STORAGE_SELECT_Buffer_reg[9]_1\ => ufc_storage_count_control_i_n_8,
      ufc_output_select_c0_in(0) => ufc_output_select_c0_in(9),
      user_clk => user_clk
    );
ufc_valid_data_counter: entity work.aurora_rx_4l_64b_VALID_DATA_COUNTER
     port map (
      \COUNT_Buffer_reg[0]_0\(2) => barrel_shifted_count_r(0),
      \COUNT_Buffer_reg[0]_0\(1) => barrel_shifted_count_r(1),
      \COUNT_Buffer_reg[0]_0\(0) => barrel_shifted_count_r(2),
      Q(3 downto 0) => Q(3 downto 0),
      RESET => RESET,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_multi_gt is
  port (
    gt0_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i : out STD_LOGIC;
    CHBONDDONE_OUT : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_0 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE1 : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxpmaresetdone_out : out STD_LOGIC;
    gt1_rxprbserr_out : out STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_2 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE2 : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxpmaresetdone_out : out STD_LOGIC;
    gt2_rxprbserr_out : out STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_4 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE3 : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxpmaresetdone_out : out STD_LOGIC;
    gt3_rxprbserr_out : out STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gthe2_i_6 : out STD_LOGIC;
    gthe2_i_7 : out STD_LOGIC;
    gthe2_i_8 : out STD_LOGIC;
    gthe2_i_9 : out STD_LOGIC;
    gthe2_i_10 : out STD_LOGIC;
    gthe2_i_11 : out STD_LOGIC;
    gthe2_i_12 : out STD_LOGIC;
    gthe2_i_13 : out STD_LOGIC;
    gthe2_i_14 : out STD_LOGIC;
    gthe2_i_15 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg : out STD_LOGIC;
    hard_err_flop_r0 : out STD_LOGIC;
    gthe2_i_16 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_17 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_18 : out STD_LOGIC;
    gthe2_i_19 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg_0 : out STD_LOGIC;
    hard_err_flop_r0_0 : out STD_LOGIC;
    gthe2_i_20 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_21 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_22 : out STD_LOGIC;
    gthe2_i_23 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg_1 : out STD_LOGIC;
    hard_err_flop_r0_1 : out STD_LOGIC;
    gthe2_i_24 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_25 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_26 : out STD_LOGIC;
    gthe2_i_27 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg_2 : out STD_LOGIC;
    hard_err_flop_r0_2 : out STD_LOGIC;
    gthe2_i_28 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_29 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC_VECTOR ( 0 to 3 );
    RXP : in STD_LOGIC_VECTOR ( 0 to 3 );
    gt_refclk1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    fsm_gt_rx_reset_t : in STD_LOGIC;
    gt_qpllclk_quad2_in : in STD_LOGIC;
    gt_qpllrefclk_quad2_in : in STD_LOGIC;
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_0 : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_0 : in STD_LOGIC;
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt_rxuserrdy_i : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_rxbufreset_in : in STD_LOGIC;
    gt1_rxcdrhold_in : in STD_LOGIC;
    gt1_rxcdrovrden_in : in STD_LOGIC;
    en_chan_sync_i : in STD_LOGIC;
    gt1_rxdfelpmreset_in : in STD_LOGIC;
    gt1_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_1 : in STD_LOGIC;
    gt1_rxpcsreset_in : in STD_LOGIC;
    gt1_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_1 : in STD_LOGIC;
    gt1_rxprbscntreset_in : in STD_LOGIC;
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt_qpllclk_quad3_in : in STD_LOGIC;
    gt_qpllrefclk_quad3_in : in STD_LOGIC;
    gt2_rxbufreset_in : in STD_LOGIC;
    gt2_rxcdrhold_in : in STD_LOGIC;
    gt2_rxcdrovrden_in : in STD_LOGIC;
    gt2_rxdfelpmreset_in : in STD_LOGIC;
    gt2_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_2 : in STD_LOGIC;
    gt2_rxpcsreset_in : in STD_LOGIC;
    gt2_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_2 : in STD_LOGIC;
    gt2_rxprbscntreset_in : in STD_LOGIC;
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_rxbufreset_in : in STD_LOGIC;
    gt3_rxcdrhold_in : in STD_LOGIC;
    gt3_rxcdrovrden_in : in STD_LOGIC;
    gt3_rxdfelpmreset_in : in STD_LOGIC;
    gt3_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_3 : in STD_LOGIC;
    gt3_rxpcsreset_in : in STD_LOGIC;
    gt3_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_3 : in STD_LOGIC;
    gt3_rxprbscntreset_in : in STD_LOGIC;
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    flag2_reg : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_0\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_1\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_2\ : in STD_LOGIC;
    gtp_rx_reset_i_0 : in STD_LOGIC;
    comma_over_two_cycles_r : in STD_LOGIC;
    first_v_received_r : in STD_LOGIC;
    bucket_full_r : in STD_LOGIC;
    gtp_rx_reset_i_1 : in STD_LOGIC;
    comma_over_two_cycles_r_3 : in STD_LOGIC;
    first_v_received_r_4 : in STD_LOGIC;
    bucket_full_r_5 : in STD_LOGIC;
    gtp_rx_reset_i_2 : in STD_LOGIC;
    comma_over_two_cycles_r_6 : in STD_LOGIC;
    first_v_received_r_7 : in STD_LOGIC;
    bucket_full_r_8 : in STD_LOGIC;
    gtp_rx_reset_i_3 : in STD_LOGIC;
    comma_over_two_cycles_r_9 : in STD_LOGIC;
    first_v_received_r_10 : in STD_LOGIC;
    bucket_full_r_11 : in STD_LOGIC;
    cpll_reset_i : in STD_LOGIC
  );
end aurora_rx_4l_64b_multi_gt;

architecture STRUCTURE of aurora_rx_4l_64b_multi_gt is
  signal chbondo_LANE1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal chbondo_LANE2 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^gt0_cplllock_out\ : STD_LOGIC;
  signal \^gt1_cplllock_out\ : STD_LOGIC;
  signal \^gt3_cplllock_out\ : STD_LOGIC;
begin
  gt0_cplllock_out <= \^gt0_cplllock_out\;
  gt1_cplllock_out <= \^gt1_cplllock_out\;
  gt3_cplllock_out <= \^gt3_cplllock_out\;
gt0_aurora_rx_4l_64b_i: entity work.aurora_rx_4l_64b_gt
     port map (
      CHBONDDONE_OUT => CHBONDDONE_OUT,
      D(1 downto 0) => D(1 downto 0),
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPWE_IN => DRPWE_IN,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE1(4 downto 0),
      RXN(0) => RXN(0),
      RXP(0) => RXP(0),
      SR(0) => SR(0),
      bucket_full_r => bucket_full_r,
      comma_over_two_cycles_r => comma_over_two_cycles_r,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      ena_comma_align_i_0 => ena_comma_align_i_0,
      first_v_received_r => first_v_received_r,
      first_v_received_r_reg => first_v_received_r_reg,
      flag2_reg_0 => flag2_reg,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt0_cplllock_out => \^gt0_cplllock_out\,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_rx_disp_err_out(1 downto 0) => gt0_rx_disp_err_out(1 downto 0),
      gt0_rx_not_in_table_out(1 downto 0) => gt0_rx_not_in_table_out(1 downto 0),
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2 downto 0) => gt0_rxbufstatus_out(2 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt_qpllclk_quad2_in => gt_qpllclk_quad2_in,
      gt_qpllrefclk_quad2_in => gt_qpllrefclk_quad2_in,
      gt_refclk1 => gt_refclk1,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gthe2_i_0 => gthe2_i,
      gthe2_i_1 => gthe2_i_6,
      gthe2_i_2 => gthe2_i_7,
      gthe2_i_3 => gthe2_i_14,
      gthe2_i_4(1 downto 0) => gthe2_i_15(1 downto 0),
      gthe2_i_5(7 downto 0) => gthe2_i_16(7 downto 0),
      gthe2_i_6(7 downto 0) => gthe2_i_17(7 downto 0),
      gtp_rx_reset_i_0 => gtp_rx_reset_i_0,
      hard_err_flop_r0 => hard_err_flop_r0,
      init_clk_in => init_clk_in,
      rx_polarity_i_0 => rx_polarity_i_0,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[1]\ => \word_aligned_control_bits_r_reg[1]\
    );
gt1_aurora_rx_4l_64b_i: entity work.aurora_rx_4l_64b_gt_33
     port map (
      CHBONDDONE_OUT_LANE1 => CHBONDDONE_OUT_LANE1,
      DRPADDR_IN_LANE1(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPEN_IN_LANE1 => DRPEN_IN_LANE1,
      DRPRDY_OUT_LANE1 => DRPRDY_OUT_LANE1,
      DRPWE_IN_LANE1 => DRPWE_IN_LANE1,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE1(4 downto 0),
      RXN(0) => RXN(1),
      RXP(0) => RXP(1),
      SR(0) => SR(0),
      bucket_full_r_5 => bucket_full_r_5,
      comma_over_two_cycles_r_3 => comma_over_two_cycles_r_3,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      en_chan_sync_i => en_chan_sync_i,
      ena_comma_align_i_1 => ena_comma_align_i_1,
      first_v_received_r_4 => first_v_received_r_4,
      first_v_received_r_reg => first_v_received_r_reg_0,
      flag2_reg_0 => flag2_reg,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt1_cplllock_out => \^gt1_cplllock_out\,
      gt1_dmonitorout_out(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
      gt1_eyescanreset_in => gt1_eyescanreset_in,
      gt1_eyescantrigger_in => gt1_eyescantrigger_in,
      gt1_rx_disp_err_out(1 downto 0) => gt1_rx_disp_err_out(1 downto 0),
      gt1_rx_not_in_table_out(1 downto 0) => gt1_rx_not_in_table_out(1 downto 0),
      gt1_rxbufreset_in => gt1_rxbufreset_in,
      gt1_rxbufstatus_out(2 downto 0) => gt1_rxbufstatus_out(2 downto 0),
      gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
      gt1_rxcdrhold_in => gt1_rxcdrhold_in,
      gt1_rxcdrovrden_in => gt1_rxcdrovrden_in,
      gt1_rxcommadet_out => gt1_rxcommadet_out,
      gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
      gt1_rxlpmen_in => gt1_rxlpmen_in,
      gt1_rxmonitorout_out(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      gt1_rxmonitorsel_in(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      gt1_rxpcsreset_in => gt1_rxpcsreset_in,
      gt1_rxpmareset_in => gt1_rxpmareset_in,
      gt1_rxpmaresetdone_out => gt1_rxpmaresetdone_out,
      gt1_rxprbscntreset_in => gt1_rxprbscntreset_in,
      gt1_rxprbserr_out => gt1_rxprbserr_out,
      gt1_rxprbssel_in(2 downto 0) => gt1_rxprbssel_in(2 downto 0),
      gt1_rxresetdone_out => gt1_rxresetdone_out,
      gt_qpllclk_quad2_in => gt_qpllclk_quad2_in,
      gt_qpllrefclk_quad2_in => gt_qpllrefclk_quad2_in,
      gt_refclk1 => gt_refclk1,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gthe2_i_0 => gthe2_i_0,
      gthe2_i_1(1 downto 0) => gthe2_i_1(1 downto 0),
      gthe2_i_2 => gthe2_i_8,
      gthe2_i_3 => gthe2_i_9,
      gthe2_i_4 => gthe2_i_18,
      gthe2_i_5(1 downto 0) => gthe2_i_19(1 downto 0),
      gthe2_i_6(7 downto 0) => gthe2_i_20(7 downto 0),
      gthe2_i_7(7 downto 0) => gthe2_i_21(7 downto 0),
      gtp_rx_reset_i_1 => gtp_rx_reset_i_1,
      hard_err_flop_r0_0 => hard_err_flop_r0_0,
      init_clk_in => init_clk_in,
      rx_polarity_i_1 => rx_polarity_i_1,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[1]\ => \word_aligned_control_bits_r_reg[1]_0\
    );
gt2_aurora_rx_4l_64b_i: entity work.aurora_rx_4l_64b_gt_34
     port map (
      CHBONDDONE_OUT_LANE2 => CHBONDDONE_OUT_LANE2,
      DRPADDR_IN_LANE2(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPEN_IN_LANE2 => DRPEN_IN_LANE2,
      DRPRDY_OUT_LANE2 => DRPRDY_OUT_LANE2,
      DRPWE_IN_LANE2 => DRPWE_IN_LANE2,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE2(4 downto 0),
      RXN(0) => RXN(2),
      RXP(0) => RXP(2),
      SR(0) => SR(0),
      TX_LOCK => TX_LOCK,
      TX_OUT_CLK => TX_OUT_CLK,
      bucket_full_r_8 => bucket_full_r_8,
      comma_over_two_cycles_r_6 => comma_over_two_cycles_r_6,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      ena_comma_align_i_2 => ena_comma_align_i_2,
      first_v_received_r_7 => first_v_received_r_7,
      first_v_received_r_reg => first_v_received_r_reg_1,
      flag2_reg_0 => flag2_reg,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt0_cplllock_out => \^gt0_cplllock_out\,
      gt1_cplllock_out => \^gt1_cplllock_out\,
      gt2_cplllock_out => gt2_cplllock_out,
      gt2_dmonitorout_out(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      gt2_eyescandataerror_out => gt2_eyescandataerror_out,
      gt2_eyescanreset_in => gt2_eyescanreset_in,
      gt2_eyescantrigger_in => gt2_eyescantrigger_in,
      gt2_rx_disp_err_out(1 downto 0) => gt2_rx_disp_err_out(1 downto 0),
      gt2_rx_not_in_table_out(1 downto 0) => gt2_rx_not_in_table_out(1 downto 0),
      gt2_rxbufreset_in => gt2_rxbufreset_in,
      gt2_rxbufstatus_out(2 downto 0) => gt2_rxbufstatus_out(2 downto 0),
      gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
      gt2_rxcdrhold_in => gt2_rxcdrhold_in,
      gt2_rxcdrovrden_in => gt2_rxcdrovrden_in,
      gt2_rxcommadet_out => gt2_rxcommadet_out,
      gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
      gt2_rxlpmen_in => gt2_rxlpmen_in,
      gt2_rxmonitorout_out(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      gt2_rxmonitorsel_in(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      gt2_rxpcsreset_in => gt2_rxpcsreset_in,
      gt2_rxpmareset_in => gt2_rxpmareset_in,
      gt2_rxpmaresetdone_out => gt2_rxpmaresetdone_out,
      gt2_rxprbscntreset_in => gt2_rxprbscntreset_in,
      gt2_rxprbserr_out => gt2_rxprbserr_out,
      gt2_rxprbssel_in(2 downto 0) => gt2_rxprbssel_in(2 downto 0),
      gt2_rxresetdone_out => gt2_rxresetdone_out,
      gt3_cplllock_out => \^gt3_cplllock_out\,
      gt_qpllclk_quad3_in => gt_qpllclk_quad3_in,
      gt_qpllrefclk_quad3_in => gt_qpllrefclk_quad3_in,
      gt_refclk1 => gt_refclk1,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gthe2_i_0 => gthe2_i_2,
      gthe2_i_1(1 downto 0) => gthe2_i_3(1 downto 0),
      gthe2_i_2 => gthe2_i_10,
      gthe2_i_3 => gthe2_i_11,
      gthe2_i_4 => gthe2_i_22,
      gthe2_i_5(1 downto 0) => gthe2_i_23(1 downto 0),
      gthe2_i_6(7 downto 0) => gthe2_i_24(7 downto 0),
      gthe2_i_7(7 downto 0) => gthe2_i_25(7 downto 0),
      gthe2_i_8(4 downto 0) => chbondo_LANE1(4 downto 0),
      gtp_rx_reset_i_2 => gtp_rx_reset_i_2,
      hard_err_flop_r0_1 => hard_err_flop_r0_1,
      init_clk_in => init_clk_in,
      rx_polarity_i_2 => rx_polarity_i_2,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[1]\ => \word_aligned_control_bits_r_reg[1]_1\
    );
gt3_aurora_rx_4l_64b_i: entity work.aurora_rx_4l_64b_gt_35
     port map (
      CHBONDDONE_OUT_LANE3 => CHBONDDONE_OUT_LANE3,
      DRPADDR_IN_LANE3(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN_IN_LANE3 => DRPEN_IN_LANE3,
      DRPRDY_OUT_LANE3 => DRPRDY_OUT_LANE3,
      DRPWE_IN_LANE3 => DRPWE_IN_LANE3,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXCHBONDO(4 downto 0) => chbondo_LANE2(4 downto 0),
      RXN(0) => RXN(3),
      RXP(0) => RXP(3),
      SR(0) => SR(0),
      bucket_full_r_11 => bucket_full_r_11,
      comma_over_two_cycles_r_9 => comma_over_two_cycles_r_9,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      ena_comma_align_i_3 => ena_comma_align_i_3,
      first_v_received_r_10 => first_v_received_r_10,
      first_v_received_r_reg => first_v_received_r_reg_2,
      flag2_reg_0 => flag2_reg,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt3_cplllock_out => \^gt3_cplllock_out\,
      gt3_dmonitorout_out(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      gt3_eyescandataerror_out => gt3_eyescandataerror_out,
      gt3_eyescanreset_in => gt3_eyescanreset_in,
      gt3_eyescantrigger_in => gt3_eyescantrigger_in,
      gt3_rx_disp_err_out(1 downto 0) => gt3_rx_disp_err_out(1 downto 0),
      gt3_rx_not_in_table_out(1 downto 0) => gt3_rx_not_in_table_out(1 downto 0),
      gt3_rxbufreset_in => gt3_rxbufreset_in,
      gt3_rxbufstatus_out(2 downto 0) => gt3_rxbufstatus_out(2 downto 0),
      gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
      gt3_rxcdrhold_in => gt3_rxcdrhold_in,
      gt3_rxcdrovrden_in => gt3_rxcdrovrden_in,
      gt3_rxcommadet_out => gt3_rxcommadet_out,
      gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
      gt3_rxlpmen_in => gt3_rxlpmen_in,
      gt3_rxmonitorout_out(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      gt3_rxmonitorsel_in(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      gt3_rxpcsreset_in => gt3_rxpcsreset_in,
      gt3_rxpmareset_in => gt3_rxpmareset_in,
      gt3_rxpmaresetdone_out => gt3_rxpmaresetdone_out,
      gt3_rxprbscntreset_in => gt3_rxprbscntreset_in,
      gt3_rxprbserr_out => gt3_rxprbserr_out,
      gt3_rxprbssel_in(2 downto 0) => gt3_rxprbssel_in(2 downto 0),
      gt3_rxresetdone_out => gt3_rxresetdone_out,
      gt_qpllclk_quad3_in => gt_qpllclk_quad3_in,
      gt_qpllrefclk_quad3_in => gt_qpllrefclk_quad3_in,
      gt_refclk1 => gt_refclk1,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gthe2_i_0 => gthe2_i_4,
      gthe2_i_1(1 downto 0) => gthe2_i_5(1 downto 0),
      gthe2_i_2 => gthe2_i_12,
      gthe2_i_3 => gthe2_i_13,
      gthe2_i_4 => gthe2_i_26,
      gthe2_i_5(1 downto 0) => gthe2_i_27(1 downto 0),
      gthe2_i_6(7 downto 0) => gthe2_i_28(7 downto 0),
      gthe2_i_7(7 downto 0) => gthe2_i_29(7 downto 0),
      gtp_rx_reset_i_3 => gtp_rx_reset_i_3,
      hard_err_flop_r0_2 => hard_err_flop_r0_2,
      init_clk_in => init_clk_in,
      rx_polarity_i_3 => rx_polarity_i_3,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[1]\ => \word_aligned_control_bits_r_reg[1]_2\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_rx_startup_fsm is
  port (
    fsm_gt_rx_reset_t : out STD_LOGIC;
    gt_rxuserrdy_i : out STD_LOGIC;
    cpll_reset_i : out STD_LOGIC;
    CPLL_RESET_reg_0 : out STD_LOGIC;
    in0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    rxfsm_rxresetdone_r : in STD_LOGIC;
    AR : in STD_LOGIC_VECTOR ( 0 to 0 );
    reset_time_out_reg_0 : in STD_LOGIC
  );
end aurora_rx_4l_64b_rx_startup_fsm;

architecture STRUCTURE of aurora_rx_4l_64b_rx_startup_fsm is
  signal CPLL_RESET_i_1_n_0 : STD_LOGIC;
  signal \FSM_sequential_rx_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_12_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_13_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_sequential_rx_state[3]_i_9_n_0\ : STD_LOGIC;
  signal RXUSERRDY_i_1_n_0 : STD_LOGIC;
  signal check_tlock_max_i_1_n_0 : STD_LOGIC;
  signal check_tlock_max_reg_n_0 : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal \^cpll_reset_i\ : STD_LOGIC;
  signal \^fsm_gt_rx_reset_t\ : STD_LOGIC;
  signal \^gt_rxuserrdy_i\ : STD_LOGIC;
  signal gtrxreset_i_i_1_n_0 : STD_LOGIC;
  signal init_wait_count : STD_LOGIC;
  signal \init_wait_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \init_wait_count[6]_i_3_n_0\ : STD_LOGIC;
  signal \init_wait_count[6]_i_4_n_0\ : STD_LOGIC;
  signal init_wait_count_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal init_wait_done_i_1_n_0 : STD_LOGIC;
  signal init_wait_done_i_2_n_0 : STD_LOGIC;
  signal init_wait_done_reg_n_0 : STD_LOGIC;
  signal \mmcm_lock_count[2]_i_1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[3]_i_1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[4]_i_1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[5]_i_1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[6]_i_1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[7]_i_1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[8]_i_1_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[9]_i_2_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[9]_i_3_n_0\ : STD_LOGIC;
  signal \mmcm_lock_count[9]_i_4_n_0\ : STD_LOGIC;
  signal mmcm_lock_count_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal mmcm_lock_i : STD_LOGIC;
  signal mmcm_lock_reclocked : STD_LOGIC;
  signal mmcm_lock_reclocked_i_1_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 1 );
  signal p_0_in_0 : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pll_reset_asserted_i_1_n_0 : STD_LOGIC;
  signal pll_reset_asserted_reg_n_0 : STD_LOGIC;
  signal reset_time_out_reg_n_0 : STD_LOGIC;
  signal run_phase_alignment_int : STD_LOGIC;
  signal run_phase_alignment_int_i_1_n_0 : STD_LOGIC;
  signal run_phase_alignment_int_s2 : STD_LOGIC;
  signal run_phase_alignment_int_s3 : STD_LOGIC;
  signal rx_fsm_reset_done_int : STD_LOGIC;
  signal rx_fsm_reset_done_int_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_1_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_3_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_4_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_i_5_n_0 : STD_LOGIC;
  signal rx_fsm_reset_done_int_s3 : STD_LOGIC;
  signal rx_state : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rx_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxpmaresetdone_i : STD_LOGIC;
  signal rxpmaresetdone_rx_s : STD_LOGIC;
  signal rxresetdone_s2 : STD_LOGIC;
  signal rxresetdone_s3 : STD_LOGIC;
  signal scndry_out : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal sync_CPLLLOCK_cdc_sync_n_0 : STD_LOGIC;
  signal sync_CPLLLOCK_cdc_sync_n_1 : STD_LOGIC;
  signal sync_mmcm_lock_reclocked_cdc_sync_n_1 : STD_LOGIC;
  signal sync_rx_fsm_reset_done_int_cdc_sync_n_0 : STD_LOGIC;
  signal time_out_100us_i_1_n_0 : STD_LOGIC;
  signal time_out_100us_i_2_n_0 : STD_LOGIC;
  signal time_out_100us_i_3_n_0 : STD_LOGIC;
  signal time_out_100us_reg_n_0 : STD_LOGIC;
  signal time_out_1us_i_1_n_0 : STD_LOGIC;
  signal time_out_1us_i_2_n_0 : STD_LOGIC;
  signal time_out_1us_i_3_n_0 : STD_LOGIC;
  signal time_out_1us_i_4_n_0 : STD_LOGIC;
  signal time_out_1us_reg_n_0 : STD_LOGIC;
  signal time_out_2ms_i_1_n_0 : STD_LOGIC;
  signal time_out_2ms_i_2_n_0 : STD_LOGIC;
  signal time_out_2ms_i_3_n_0 : STD_LOGIC;
  signal time_out_2ms_i_4_n_0 : STD_LOGIC;
  signal time_out_2ms_i_5_n_0 : STD_LOGIC;
  signal time_out_2ms_reg_n_0 : STD_LOGIC;
  signal time_out_counter : STD_LOGIC;
  signal \time_out_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_4_n_0\ : STD_LOGIC;
  signal \time_out_counter[0]_i_5_n_0\ : STD_LOGIC;
  signal time_out_counter_reg : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \time_out_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \time_out_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal time_out_wait_bypass : STD_LOGIC;
  signal time_out_wait_bypass_i_1_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_2_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_3_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_i_4_n_0 : STD_LOGIC;
  signal time_out_wait_bypass_s2 : STD_LOGIC;
  signal time_out_wait_bypass_s3 : STD_LOGIC;
  signal time_tlock_max : STD_LOGIC;
  signal time_tlock_max1 : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_1\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_2\ : STD_LOGIC;
  signal \time_tlock_max1_carry__0_n_3\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \time_tlock_max1_carry__1_n_3\ : STD_LOGIC;
  signal time_tlock_max1_carry_i_1_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_2_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_3_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_4_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_i_5_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_0 : STD_LOGIC;
  signal time_tlock_max1_carry_n_1 : STD_LOGIC;
  signal time_tlock_max1_carry_n_2 : STD_LOGIC;
  signal time_tlock_max1_carry_n_3 : STD_LOGIC;
  signal time_tlock_max_i_1_n_0 : STD_LOGIC;
  signal \wait_bypass_count[0]_i_2_n_0\ : STD_LOGIC;
  signal \wait_bypass_count[0]_i_4_n_0\ : STD_LOGIC;
  signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \wait_bypass_count_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \wait_bypass_count_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \wait_time_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[4]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[5]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_1_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_3_n_0\ : STD_LOGIC;
  signal \wait_time_cnt[6]_i_4_n_0\ : STD_LOGIC;
  signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_time_tlock_max1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[0]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[0]_i_3\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[2]_i_2\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_10\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_11\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_13\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_8\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_9\ : label is "soft_lutpair12";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[0]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[1]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[2]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[3]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101";
  attribute SOFT_HLUTNM of gtrxreset_i_i_1 : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \init_wait_count[1]_i_1\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \init_wait_count[2]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \init_wait_count[3]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \init_wait_count[4]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \init_wait_count[6]_i_3\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \init_wait_count[6]_i_4\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \mmcm_lock_count[8]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \mmcm_lock_count[9]_i_3\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of mmcm_lock_reclocked_i_2 : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of run_phase_alignment_int_i_1 : label is "soft_lutpair9";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of run_phase_alignment_int_s3_reg : label is "no";
  attribute SOFT_HLUTNM of rx_fsm_reset_done_int_i_5 : label is "soft_lutpair9";
  attribute equivalent_register_removal of rx_fsm_reset_done_int_s3_reg : label is "no";
  attribute equivalent_register_removal of rxresetdone_s3_reg : label is "no";
  attribute SOFT_HLUTNM of time_out_2ms_i_4 : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \time_out_counter[0]_i_3\ : label is "soft_lutpair13";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_out_counter_reg[8]_i_1\ : label is 11;
  attribute equivalent_register_removal of time_out_wait_bypass_s3_reg : label is "no";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of time_tlock_max1_carry : label is 11;
  attribute COMPARATOR_THRESHOLD of \time_tlock_max1_carry__0\ : label is 11;
  attribute COMPARATOR_THRESHOLD of \time_tlock_max1_carry__1\ : label is 11;
  attribute SOFT_HLUTNM of time_tlock_max_i_1 : label is "soft_lutpair15";
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[0]_i_3\ : label is 11;
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \wait_bypass_count_reg[8]_i_1\ : label is 11;
  attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1\ : label is "soft_lutpair10";
begin
  cpll_reset_i <= \^cpll_reset_i\;
  fsm_gt_rx_reset_t <= \^fsm_gt_rx_reset_t\;
  gt_rxuserrdy_i <= \^gt_rxuserrdy_i\;
CPLL_RESET_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFF00000100"
    )
        port map (
      I0 => pll_reset_asserted_reg_n_0,
      I1 => rx_state(3),
      I2 => rx_state(2),
      I3 => rx_state(0),
      I4 => rx_state(1),
      I5 => \^cpll_reset_i\,
      O => CPLL_RESET_i_1_n_0
    );
CPLL_RESET_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => CPLL_RESET_i_1_n_0,
      Q => \^cpll_reset_i\,
      R => AR(0)
    );
\FSM_sequential_rx_state[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFEFEF"
    )
        port map (
      I0 => \FSM_sequential_rx_state[0]_i_2_n_0\,
      I1 => \FSM_sequential_rx_state[0]_i_3_n_0\,
      I2 => rx_state(0),
      I3 => rx_state(1),
      I4 => rx_state(3),
      O => \rx_state__0\(0)
    );
\FSM_sequential_rx_state[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222AAAA00300000"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => reset_time_out_reg_n_0,
      I2 => time_tlock_max,
      I3 => rx_state(3),
      I4 => rx_state(2),
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[0]_i_2_n_0\
    );
\FSM_sequential_rx_state[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rx_state(3),
      I1 => reset_time_out_reg_n_0,
      I2 => \^gt_rxuserrdy_i\,
      I3 => time_out_100us_reg_n_0,
      O => \FSM_sequential_rx_state[0]_i_3_n_0\
    );
\FSM_sequential_rx_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF24200400"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => rx_state(2),
      I4 => \FSM_sequential_rx_state[1]_i_2_n_0\,
      I5 => \FSM_sequential_rx_state[1]_i_3_n_0\,
      O => \rx_state__0\(1)
    );
\FSM_sequential_rx_state[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^gt_rxuserrdy_i\,
      I1 => time_out_100us_reg_n_0,
      O => \FSM_sequential_rx_state[1]_i_2_n_0\
    );
\FSM_sequential_rx_state[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AABF000F0000"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_tlock_max,
      I2 => rx_state(2),
      I3 => rx_state(3),
      I4 => rx_state(1),
      I5 => rx_state(0),
      O => \FSM_sequential_rx_state[1]_i_3_n_0\
    );
\FSM_sequential_rx_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"010C0C0C01000C0C"
    )
        port map (
      I0 => time_out_2ms_reg_n_0,
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(1),
      I4 => rx_state(0),
      I5 => \FSM_sequential_rx_state[2]_i_2_n_0\,
      O => \rx_state__0\(2)
    );
\FSM_sequential_rx_state[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_tlock_max,
      O => \FSM_sequential_rx_state[2]_i_2_n_0\
    );
\FSM_sequential_rx_state[3]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_time_out_reg_n_0,
      I1 => time_out_2ms_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_10_n_0\
    );
\FSM_sequential_rx_state[3]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(3),
      O => \FSM_sequential_rx_state[3]_i_11_n_0\
    );
\FSM_sequential_rx_state[3]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000008F888888"
    )
        port map (
      I0 => rx_state(3),
      I1 => \^gt_rxuserrdy_i\,
      I2 => rx_state(0),
      I3 => rx_state(2),
      I4 => reset_time_out_reg_0,
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_12_n_0\
    );
\FSM_sequential_rx_state[3]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(0),
      O => \FSM_sequential_rx_state[3]_i_13_n_0\
    );
\FSM_sequential_rx_state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFAAAAEAEFAAAA"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_8_n_0\,
      I1 => \FSM_sequential_rx_state[3]_i_9_n_0\,
      I2 => rx_state(0),
      I3 => time_out_wait_bypass_s3,
      I4 => rx_state(3),
      I5 => rx_state(1),
      O => \rx_state__0\(3)
    );
\FSM_sequential_rx_state[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000F440000"
    )
        port map (
      I0 => \FSM_sequential_rx_state[2]_i_2_n_0\,
      I1 => rx_state(2),
      I2 => \FSM_sequential_rx_state[3]_i_10_n_0\,
      I3 => rx_state(1),
      I4 => rx_state(0),
      I5 => rx_state(3),
      O => \FSM_sequential_rx_state[3]_i_3_n_0\
    );
\FSM_sequential_rx_state[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAEAFFAAAAEA"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_12_n_0\,
      I1 => mmcm_lock_reclocked,
      I2 => rx_state(2),
      I3 => rx_state(3),
      I4 => \FSM_sequential_rx_state[3]_i_13_n_0\,
      I5 => \^gt_rxuserrdy_i\,
      O => \FSM_sequential_rx_state[3]_i_5_n_0\
    );
\FSM_sequential_rx_state[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAAA"
    )
        port map (
      I0 => \FSM_sequential_rx_state[0]_i_3_n_0\,
      I1 => \wait_time_cnt[6]_i_4_n_0\,
      I2 => wait_time_cnt_reg(6),
      I3 => rx_state(3),
      I4 => rx_state(0),
      I5 => rx_state(1),
      O => \FSM_sequential_rx_state[3]_i_6_n_0\
    );
\FSM_sequential_rx_state[3]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80800080"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(2),
      I3 => time_out_2ms_reg_n_0,
      I4 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_8_n_0\
    );
\FSM_sequential_rx_state[3]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => time_out_100us_reg_n_0,
      I1 => \^gt_rxuserrdy_i\,
      I2 => reset_time_out_reg_n_0,
      O => \FSM_sequential_rx_state[3]_i_9_n_0\
    );
\FSM_sequential_rx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(0),
      Q => rx_state(0),
      R => AR(0)
    );
\FSM_sequential_rx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(1),
      Q => rx_state(1),
      R => AR(0)
    );
\FSM_sequential_rx_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(2),
      Q => rx_state(2),
      R => AR(0)
    );
\FSM_sequential_rx_state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => sync_CPLLLOCK_cdc_sync_n_0,
      D => \rx_state__0\(3),
      Q => rx_state(3),
      R => AR(0)
    );
RXUSERRDY_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB4000"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(0),
      I2 => rx_state(2),
      I3 => rx_state(1),
      I4 => \^gt_rxuserrdy_i\,
      O => RXUSERRDY_i_1_n_0
    );
RXUSERRDY_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => RXUSERRDY_i_1_n_0,
      Q => \^gt_rxuserrdy_i\,
      R => AR(0)
    );
check_tlock_max_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFB0008"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(0),
      I2 => rx_state(1),
      I3 => rx_state(3),
      I4 => check_tlock_max_reg_n_0,
      O => check_tlock_max_i_1_n_0
    );
check_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => check_tlock_max_i_1_n_0,
      Q => check_tlock_max_reg_n_0,
      R => AR(0)
    );
\flag2_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cpll_reset_i\,
      O => CPLL_RESET_reg_0
    );
gtrxreset_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_22\
     port map (
      fsm_gt_rx_reset_t => \^fsm_gt_rx_reset_t\,
      init_clk_in => init_clk_in,
      \out\ => scndry_out,
      user_clk => user_clk
    );
gtrxreset_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEF0100"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(1),
      I2 => rx_state(2),
      I3 => rx_state(0),
      I4 => \^fsm_gt_rx_reset_t\,
      O => gtrxreset_i_i_1_n_0
    );
gtrxreset_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_i_i_1_n_0,
      Q => \^fsm_gt_rx_reset_t\,
      R => AR(0)
    );
\init_wait_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(0),
      O => \init_wait_count[0]_i_1_n_0\
    );
\init_wait_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_count_reg(1),
      O => p_0_in(1)
    );
\init_wait_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => p_0_in(2)
    );
\init_wait_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => init_wait_count_reg(2),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(3),
      O => p_0_in(3)
    );
\init_wait_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => init_wait_count_reg(3),
      I1 => init_wait_count_reg(1),
      I2 => init_wait_count_reg(0),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(4),
      O => p_0_in(4)
    );
\init_wait_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(4),
      I5 => init_wait_count_reg(5),
      O => p_0_in(5)
    );
\init_wait_count[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFFFF"
    )
        port map (
      I0 => \init_wait_count[6]_i_3_n_0\,
      I1 => init_wait_count_reg(3),
      I2 => init_wait_count_reg(4),
      I3 => init_wait_count_reg(5),
      I4 => init_wait_count_reg(6),
      I5 => init_wait_count_reg(0),
      O => init_wait_count
    );
\init_wait_count[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \init_wait_count[6]_i_4_n_0\,
      I1 => init_wait_count_reg(5),
      I2 => init_wait_count_reg(4),
      I3 => init_wait_count_reg(3),
      I4 => init_wait_count_reg(6),
      O => p_0_in(6)
    );
\init_wait_count[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(2),
      O => \init_wait_count[6]_i_3_n_0\
    );
\init_wait_count[6]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => init_wait_count_reg(1),
      I1 => init_wait_count_reg(0),
      I2 => init_wait_count_reg(2),
      O => \init_wait_count[6]_i_4_n_0\
    );
\init_wait_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => \init_wait_count[0]_i_1_n_0\,
      Q => init_wait_count_reg(0)
    );
\init_wait_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(1),
      Q => init_wait_count_reg(1)
    );
\init_wait_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(2),
      Q => init_wait_count_reg(2)
    );
\init_wait_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(3),
      Q => init_wait_count_reg(3)
    );
\init_wait_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(4),
      Q => init_wait_count_reg(4)
    );
\init_wait_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(5),
      Q => init_wait_count_reg(5)
    );
\init_wait_count_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => init_wait_count,
      CLR => AR(0),
      D => p_0_in(6),
      Q => init_wait_count_reg(6)
    );
init_wait_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => init_wait_count_reg(0),
      I1 => init_wait_done_i_2_n_0,
      I2 => init_wait_done_reg_n_0,
      O => init_wait_done_i_1_n_0
    );
init_wait_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => init_wait_count_reg(4),
      I1 => init_wait_count_reg(3),
      I2 => init_wait_count_reg(1),
      I3 => init_wait_count_reg(2),
      I4 => init_wait_count_reg(5),
      I5 => init_wait_count_reg(6),
      O => init_wait_done_i_2_n_0
    );
init_wait_done_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      CLR => AR(0),
      D => init_wait_done_i_1_n_0,
      Q => init_wait_done_reg_n_0
    );
\mmcm_lock_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      O => \p_0_in__0\(0)
    );
\mmcm_lock_count[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => mmcm_lock_count_reg(0),
      I1 => mmcm_lock_count_reg(1),
      O => \p_0_in__0\(1)
    );
\mmcm_lock_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => mmcm_lock_count_reg(1),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(2),
      O => \mmcm_lock_count[2]_i_1_n_0\
    );
\mmcm_lock_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => mmcm_lock_count_reg(2),
      I1 => mmcm_lock_count_reg(0),
      I2 => mmcm_lock_count_reg(1),
      I3 => mmcm_lock_count_reg(3),
      O => \mmcm_lock_count[3]_i_1_n_0\
    );
\mmcm_lock_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => mmcm_lock_count_reg(3),
      I1 => mmcm_lock_count_reg(1),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(2),
      I4 => mmcm_lock_count_reg(4),
      O => \mmcm_lock_count[4]_i_1_n_0\
    );
\mmcm_lock_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[5]_i_1_n_0\
    );
\mmcm_lock_count[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \mmcm_lock_count[9]_i_4_n_0\,
      I1 => mmcm_lock_count_reg(6),
      O => \mmcm_lock_count[6]_i_1_n_0\
    );
\mmcm_lock_count[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => mmcm_lock_count_reg(6),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(7),
      O => \mmcm_lock_count[7]_i_1_n_0\
    );
\mmcm_lock_count[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => mmcm_lock_count_reg(7),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(6),
      I3 => mmcm_lock_count_reg(8),
      O => \mmcm_lock_count[8]_i_1_n_0\
    );
\mmcm_lock_count[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(7),
      I1 => \mmcm_lock_count[9]_i_4_n_0\,
      I2 => mmcm_lock_count_reg(6),
      I3 => mmcm_lock_count_reg(8),
      I4 => mmcm_lock_count_reg(9),
      O => \mmcm_lock_count[9]_i_2_n_0\
    );
\mmcm_lock_count[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FF0800"
    )
        port map (
      I0 => mmcm_lock_count_reg(8),
      I1 => mmcm_lock_count_reg(6),
      I2 => \mmcm_lock_count[9]_i_4_n_0\,
      I3 => mmcm_lock_count_reg(7),
      I4 => mmcm_lock_count_reg(9),
      O => \mmcm_lock_count[9]_i_3_n_0\
    );
\mmcm_lock_count[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => mmcm_lock_count_reg(4),
      I1 => mmcm_lock_count_reg(2),
      I2 => mmcm_lock_count_reg(0),
      I3 => mmcm_lock_count_reg(1),
      I4 => mmcm_lock_count_reg(3),
      I5 => mmcm_lock_count_reg(5),
      O => \mmcm_lock_count[9]_i_4_n_0\
    );
\mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(0),
      Q => mmcm_lock_count_reg(0),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \p_0_in__0\(1),
      Q => mmcm_lock_count_reg(1),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[2]_i_1_n_0\,
      Q => mmcm_lock_count_reg(2),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[3]_i_1_n_0\,
      Q => mmcm_lock_count_reg(3),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[4]_i_1_n_0\,
      Q => mmcm_lock_count_reg(4),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[5]_i_1_n_0\,
      Q => mmcm_lock_count_reg(5),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[6]_i_1_n_0\,
      Q => mmcm_lock_count_reg(6),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[7]_i_1_n_0\,
      Q => mmcm_lock_count_reg(7),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[8]_i_1_n_0\,
      Q => mmcm_lock_count_reg(8),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
\mmcm_lock_count_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => \mmcm_lock_count[9]_i_2_n_0\,
      D => \mmcm_lock_count[9]_i_3_n_0\,
      Q => mmcm_lock_count_reg(9),
      R => sync_mmcm_lock_reclocked_cdc_sync_n_1
    );
mmcm_lock_reclocked_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => mmcm_lock_reclocked,
      I1 => p_0_in_0,
      I2 => mmcm_lock_i,
      O => mmcm_lock_reclocked_i_1_n_0
    );
mmcm_lock_reclocked_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => mmcm_lock_count_reg(9),
      I1 => mmcm_lock_count_reg(8),
      I2 => mmcm_lock_count_reg(6),
      I3 => \mmcm_lock_count[9]_i_4_n_0\,
      I4 => mmcm_lock_count_reg(7),
      O => p_0_in_0
    );
mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => mmcm_lock_reclocked_i_1_n_0,
      Q => mmcm_lock_reclocked,
      R => '0'
    );
pll_reset_asserted_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDFF0100"
    )
        port map (
      I0 => rx_state(1),
      I1 => rx_state(2),
      I2 => rx_state(3),
      I3 => rx_state(0),
      I4 => pll_reset_asserted_reg_n_0,
      O => pll_reset_asserted_i_1_n_0
    );
pll_reset_asserted_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => pll_reset_asserted_i_1_n_0,
      Q => pll_reset_asserted_reg_n_0,
      R => AR(0)
    );
reset_time_out_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => sync_CPLLLOCK_cdc_sync_n_1,
      Q => reset_time_out_reg_n_0,
      S => AR(0)
    );
run_phase_alignment_int_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF0010"
    )
        port map (
      I0 => rx_state(2),
      I1 => rx_state(1),
      I2 => rx_state(3),
      I3 => rx_state(0),
      I4 => run_phase_alignment_int,
      O => run_phase_alignment_int_i_1_n_0
    );
run_phase_alignment_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => run_phase_alignment_int_i_1_n_0,
      Q => run_phase_alignment_int,
      R => AR(0)
    );
run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => run_phase_alignment_int_s2,
      Q => run_phase_alignment_int_s3,
      R => '0'
    );
rx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABA8"
    )
        port map (
      I0 => rx_fsm_reset_done_int_0,
      I1 => rx_fsm_reset_done_int_i_3_n_0,
      I2 => rx_fsm_reset_done_int_i_4_n_0,
      I3 => rx_fsm_reset_done_int,
      O => rx_fsm_reset_done_int_i_1_n_0
    );
rx_fsm_reset_done_int_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => rx_state(0),
      I1 => time_out_1us_reg_n_0,
      I2 => rx_state(2),
      I3 => reset_time_out_reg_n_0,
      I4 => \^gt_rxuserrdy_i\,
      O => rx_fsm_reset_done_int_0
    );
rx_fsm_reset_done_int_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400040004040400"
    )
        port map (
      I0 => \FSM_sequential_rx_state[3]_i_13_n_0\,
      I1 => rx_state(3),
      I2 => rx_state(2),
      I3 => \^gt_rxuserrdy_i\,
      I4 => time_out_100us_reg_n_0,
      I5 => reset_time_out_reg_n_0,
      O => rx_fsm_reset_done_int_i_3_n_0
    );
rx_fsm_reset_done_int_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000808080008"
    )
        port map (
      I0 => rx_fsm_reset_done_int_i_5_n_0,
      I1 => rx_state(1),
      I2 => rx_state(0),
      I3 => \^gt_rxuserrdy_i\,
      I4 => time_out_1us_reg_n_0,
      I5 => reset_time_out_reg_n_0,
      O => rx_fsm_reset_done_int_i_4_n_0
    );
rx_fsm_reset_done_int_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rx_state(3),
      I1 => rx_state(2),
      O => rx_fsm_reset_done_int_i_5_n_0
    );
rx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_fsm_reset_done_int_i_1_n_0,
      Q => rx_fsm_reset_done_int,
      R => AR(0)
    );
rx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => sync_rx_fsm_reset_done_int_cdc_sync_n_0,
      Q => rx_fsm_reset_done_int_s3,
      R => '0'
    );
rxpmaresetdone_i_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      CLR => scndry_out,
      D => rxpmaresetdone_rx_s,
      Q => rxpmaresetdone_i
    );
rxresetdone_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rxresetdone_s2,
      Q => rxresetdone_s3,
      R => '0'
    );
sync_CPLLLOCK_cdc_sync: entity work.aurora_rx_4l_64b_cdc_sync_23
     port map (
      E(0) => sync_CPLLLOCK_cdc_sync_n_0,
      \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[3]_i_3_n_0\,
      \FSM_sequential_rx_state_reg[0]_0\ => \FSM_sequential_rx_state[3]_i_6_n_0\,
      \FSM_sequential_rx_state_reg[0]_1\ => time_out_2ms_reg_n_0,
      \FSM_sequential_rx_state_reg[0]_2\ => \FSM_sequential_rx_state[3]_i_11_n_0\,
      \FSM_sequential_rx_state_reg[0]_3\ => pll_reset_asserted_reg_n_0,
      \FSM_sequential_rx_state_reg[0]_4\ => init_wait_done_reg_n_0,
      \FSM_sequential_rx_state_reg[1]\ => sync_CPLLLOCK_cdc_sync_n_1,
      Q(3 downto 0) => rx_state(3 downto 0),
      in0 => in0,
      init_clk_in => init_clk_in,
      reset_time_out_reg => reset_time_out_reg_0,
      reset_time_out_reg_0 => \FSM_sequential_rx_state[3]_i_5_n_0\,
      reset_time_out_reg_1 => reset_time_out_reg_n_0,
      rxresetdone_s3 => rxresetdone_s3
    );
sync_QPLLLOCK_cdc_sync: entity work.aurora_rx_4l_64b_cdc_sync_24
     port map (
      init_clk_in => init_clk_in
    );
sync_RXRESETDONE_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_25\
     port map (
      init_clk_in => init_clk_in,
      \out\ => rxresetdone_s2,
      rxfsm_rxresetdone_r => rxfsm_rxresetdone_r,
      user_clk => user_clk
    );
sync_mmcm_lock_reclocked_cdc_sync: entity work.aurora_rx_4l_64b_cdc_sync_26
     port map (
      SR(0) => sync_mmcm_lock_reclocked_cdc_sync_n_1,
      init_clk_in => init_clk_in,
      \out\ => mmcm_lock_i
    );
sync_pmaresetdone_fallingedge_detect_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_27\
     port map (
      init_clk_in => init_clk_in,
      user_clk => user_clk
    );
sync_run_phase_alignment_int_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_28\
     port map (
      init_clk_in => init_clk_in,
      \out\ => run_phase_alignment_int_s2,
      run_phase_alignment_int => run_phase_alignment_int,
      user_clk => user_clk
    );
sync_rx_fsm_reset_done_int_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_29\
     port map (
      init_clk_in => init_clk_in,
      \out\ => sync_rx_fsm_reset_done_int_cdc_sync_n_0,
      rx_fsm_reset_done_int => rx_fsm_reset_done_int,
      user_clk => user_clk
    );
sync_rxpmaresetdone_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_30\
     port map (
      init_clk_in => init_clk_in,
      rxpmaresetdone_i => rxpmaresetdone_i,
      user_clk => user_clk
    );
sync_rxpmaresetdone_rx_s_cdc_sync: entity work.aurora_rx_4l_64b_cdc_sync_31
     port map (
      \out\ => rxpmaresetdone_rx_s,
      user_clk => user_clk
    );
sync_time_out_wait_bypass_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_32\
     port map (
      init_clk_in => init_clk_in,
      \out\ => time_out_wait_bypass_s2,
      time_out_wait_bypass => time_out_wait_bypass,
      user_clk => user_clk
    );
time_out_100us_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00020000"
    )
        port map (
      I0 => time_out_100us_i_2_n_0,
      I1 => time_out_counter_reg(4),
      I2 => time_out_counter_reg(5),
      I3 => time_out_2ms_i_3_n_0,
      I4 => time_out_100us_i_3_n_0,
      I5 => time_out_100us_reg_n_0,
      O => time_out_100us_i_1_n_0
    );
time_out_100us_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => time_out_1us_i_4_n_0,
      I1 => time_out_counter_reg(6),
      I2 => time_out_counter_reg(7),
      I3 => time_out_counter_reg(2),
      I4 => time_out_counter_reg(1),
      O => time_out_100us_i_2_n_0
    );
time_out_100us_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(11),
      I2 => time_out_counter_reg(8),
      I3 => time_out_counter_reg(10),
      I4 => time_out_counter_reg(18),
      I5 => time_out_counter_reg(13),
      O => time_out_100us_i_3_n_0
    );
time_out_100us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_100us_i_1_n_0,
      Q => time_out_100us_reg_n_0,
      R => reset_time_out_reg_n_0
    );
time_out_1us_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000200"
    )
        port map (
      I0 => time_out_1us_i_2_n_0,
      I1 => time_out_1us_i_3_n_0,
      I2 => time_out_counter_reg(0),
      I3 => time_out_1us_i_4_n_0,
      I4 => time_out_2ms_i_5_n_0,
      I5 => time_out_1us_reg_n_0,
      O => time_out_1us_i_1_n_0
    );
time_out_1us_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000002000"
    )
        port map (
      I0 => time_out_counter_reg(7),
      I1 => time_out_counter_reg(9),
      I2 => time_out_counter_reg(2),
      I3 => time_out_counter_reg(3),
      I4 => time_out_counter_reg(18),
      I5 => time_out_counter_reg(11),
      O => time_out_1us_i_2_n_0
    );
time_out_1us_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(5),
      O => time_out_1us_i_3_n_0
    );
time_out_1us_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => time_out_counter_reg(17),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(15),
      I3 => time_out_counter_reg(14),
      O => time_out_1us_i_4_n_0
    );
time_out_1us_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_1us_i_1_n_0,
      Q => time_out_1us_reg_n_0,
      R => reset_time_out_reg_n_0
    );
time_out_2ms_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0020"
    )
        port map (
      I0 => time_out_2ms_i_2_n_0,
      I1 => time_out_2ms_i_3_n_0,
      I2 => time_out_2ms_i_4_n_0,
      I3 => time_out_2ms_i_5_n_0,
      I4 => time_out_2ms_reg_n_0,
      O => time_out_2ms_i_1_n_0
    );
time_out_2ms_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(16),
      I2 => time_out_counter_reg(11),
      I3 => time_out_counter_reg(14),
      I4 => time_out_counter_reg(18),
      I5 => time_out_counter_reg(17),
      O => time_out_2ms_i_2_n_0
    );
time_out_2ms_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => time_out_counter_reg(9),
      I1 => time_out_counter_reg(3),
      I2 => time_out_counter_reg(0),
      O => time_out_2ms_i_3_n_0
    );
time_out_2ms_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => time_out_counter_reg(2),
      I1 => time_out_counter_reg(4),
      I2 => time_out_counter_reg(7),
      I3 => time_out_counter_reg(5),
      O => time_out_2ms_i_4_n_0
    );
time_out_2ms_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(13),
      I2 => time_out_counter_reg(8),
      I3 => time_out_counter_reg(10),
      I4 => time_out_counter_reg(1),
      I5 => time_out_counter_reg(6),
      O => time_out_2ms_i_5_n_0
    );
time_out_2ms_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_2ms_i_1_n_0,
      Q => time_out_2ms_reg_n_0,
      R => reset_time_out_reg_n_0
    );
\time_out_counter[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => time_out_2ms_i_5_n_0,
      I1 => time_out_counter_reg(4),
      I2 => \time_out_counter[0]_i_3_n_0\,
      I3 => time_out_counter_reg(2),
      I4 => time_out_2ms_i_3_n_0,
      I5 => \time_out_counter[0]_i_4_n_0\,
      O => time_out_counter
    );
\time_out_counter[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(7),
      O => \time_out_counter[0]_i_3_n_0\
    );
\time_out_counter[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF7FFFFFFFFF"
    )
        port map (
      I0 => time_out_counter_reg(17),
      I1 => time_out_counter_reg(18),
      I2 => time_out_counter_reg(15),
      I3 => time_out_counter_reg(16),
      I4 => time_out_counter_reg(14),
      I5 => time_out_counter_reg(11),
      O => \time_out_counter[0]_i_4_n_0\
    );
\time_out_counter[0]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(0),
      O => \time_out_counter[0]_i_5_n_0\
    );
\time_out_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_7\,
      Q => time_out_counter_reg(0),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_out_counter_reg[0]_i_2_n_0\,
      CO(2) => \time_out_counter_reg[0]_i_2_n_1\,
      CO(1) => \time_out_counter_reg[0]_i_2_n_2\,
      CO(0) => \time_out_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_out_counter_reg[0]_i_2_n_4\,
      O(2) => \time_out_counter_reg[0]_i_2_n_5\,
      O(1) => \time_out_counter_reg[0]_i_2_n_6\,
      O(0) => \time_out_counter_reg[0]_i_2_n_7\,
      S(3 downto 1) => time_out_counter_reg(3 downto 1),
      S(0) => \time_out_counter[0]_i_5_n_0\
    );
\time_out_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_5\,
      Q => time_out_counter_reg(10),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_4\,
      Q => time_out_counter_reg(11),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_7\,
      Q => time_out_counter_reg(12),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[8]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[12]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[12]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[12]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[12]_i_1_n_4\,
      O(2) => \time_out_counter_reg[12]_i_1_n_5\,
      O(1) => \time_out_counter_reg[12]_i_1_n_6\,
      O(0) => \time_out_counter_reg[12]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(15 downto 12)
    );
\time_out_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_6\,
      Q => time_out_counter_reg(13),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_5\,
      Q => time_out_counter_reg(14),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[12]_i_1_n_4\,
      Q => time_out_counter_reg(15),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1_n_7\,
      Q => time_out_counter_reg(16),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \time_out_counter_reg[16]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\(3),
      O(2) => \time_out_counter_reg[16]_i_1_n_5\,
      O(1) => \time_out_counter_reg[16]_i_1_n_6\,
      O(0) => \time_out_counter_reg[16]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => time_out_counter_reg(18 downto 16)
    );
\time_out_counter_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1_n_6\,
      Q => time_out_counter_reg(17),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[16]_i_1_n_5\,
      Q => time_out_counter_reg(18),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_6\,
      Q => time_out_counter_reg(1),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_5\,
      Q => time_out_counter_reg(2),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[0]_i_2_n_4\,
      Q => time_out_counter_reg(3),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_7\,
      Q => time_out_counter_reg(4),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[0]_i_2_n_0\,
      CO(3) => \time_out_counter_reg[4]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[4]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[4]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[4]_i_1_n_4\,
      O(2) => \time_out_counter_reg[4]_i_1_n_5\,
      O(1) => \time_out_counter_reg[4]_i_1_n_6\,
      O(0) => \time_out_counter_reg[4]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(7 downto 4)
    );
\time_out_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_6\,
      Q => time_out_counter_reg(5),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_5\,
      Q => time_out_counter_reg(6),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[4]_i_1_n_4\,
      Q => time_out_counter_reg(7),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_7\,
      Q => time_out_counter_reg(8),
      R => reset_time_out_reg_n_0
    );
\time_out_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_out_counter_reg[4]_i_1_n_0\,
      CO(3) => \time_out_counter_reg[8]_i_1_n_0\,
      CO(2) => \time_out_counter_reg[8]_i_1_n_1\,
      CO(1) => \time_out_counter_reg[8]_i_1_n_2\,
      CO(0) => \time_out_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_out_counter_reg[8]_i_1_n_4\,
      O(2) => \time_out_counter_reg[8]_i_1_n_5\,
      O(1) => \time_out_counter_reg[8]_i_1_n_6\,
      O(0) => \time_out_counter_reg[8]_i_1_n_7\,
      S(3 downto 0) => time_out_counter_reg(11 downto 8)
    );
\time_out_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => time_out_counter,
      D => \time_out_counter_reg[8]_i_1_n_6\,
      Q => time_out_counter_reg(9),
      R => reset_time_out_reg_n_0
    );
time_out_wait_bypass_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AB00"
    )
        port map (
      I0 => time_out_wait_bypass,
      I1 => rx_fsm_reset_done_int_s3,
      I2 => time_out_wait_bypass_i_2_n_0,
      I3 => run_phase_alignment_int_s3,
      O => time_out_wait_bypass_i_1_n_0
    );
time_out_wait_bypass_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => time_out_wait_bypass_i_3_n_0,
      I1 => wait_bypass_count_reg(1),
      I2 => wait_bypass_count_reg(11),
      I3 => wait_bypass_count_reg(0),
      I4 => time_out_wait_bypass_i_4_n_0,
      O => time_out_wait_bypass_i_2_n_0
    );
time_out_wait_bypass_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => wait_bypass_count_reg(9),
      I1 => wait_bypass_count_reg(4),
      I2 => wait_bypass_count_reg(12),
      I3 => wait_bypass_count_reg(2),
      O => time_out_wait_bypass_i_3_n_0
    );
time_out_wait_bypass_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400000000"
    )
        port map (
      I0 => wait_bypass_count_reg(5),
      I1 => wait_bypass_count_reg(7),
      I2 => wait_bypass_count_reg(3),
      I3 => wait_bypass_count_reg(6),
      I4 => wait_bypass_count_reg(10),
      I5 => wait_bypass_count_reg(8),
      O => time_out_wait_bypass_i_4_n_0
    );
time_out_wait_bypass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => time_out_wait_bypass_i_1_n_0,
      Q => time_out_wait_bypass,
      R => '0'
    );
time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_out_wait_bypass_s2,
      Q => time_out_wait_bypass_s3,
      R => '0'
    );
time_tlock_max1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => time_tlock_max1_carry_n_0,
      CO(2) => time_tlock_max1_carry_n_1,
      CO(1) => time_tlock_max1_carry_n_2,
      CO(0) => time_tlock_max1_carry_n_3,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => time_tlock_max1_carry_i_1_n_0,
      DI(1) => '0',
      DI(0) => time_out_counter_reg(1),
      O(3 downto 0) => NLW_time_tlock_max1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => time_tlock_max1_carry_i_2_n_0,
      S(2) => time_tlock_max1_carry_i_3_n_0,
      S(1) => time_tlock_max1_carry_i_4_n_0,
      S(0) => time_tlock_max1_carry_i_5_n_0
    );
\time_tlock_max1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => time_tlock_max1_carry_n_0,
      CO(3) => \time_tlock_max1_carry__0_n_0\,
      CO(2) => \time_tlock_max1_carry__0_n_1\,
      CO(1) => \time_tlock_max1_carry__0_n_2\,
      CO(0) => \time_tlock_max1_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \time_tlock_max1_carry__0_i_1_n_0\,
      DI(2) => '0',
      DI(1) => time_out_counter_reg(11),
      DI(0) => '0',
      O(3 downto 0) => \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \time_tlock_max1_carry__0_i_2_n_0\,
      S(2) => \time_tlock_max1_carry__0_i_3_n_0\,
      S(1) => \time_tlock_max1_carry__0_i_4_n_0\,
      S(0) => \time_tlock_max1_carry__0_i_5_n_0\
    );
\time_tlock_max1_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(14),
      I1 => time_out_counter_reg(15),
      O => \time_tlock_max1_carry__0_i_1_n_0\
    );
\time_tlock_max1_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(15),
      I1 => time_out_counter_reg(14),
      O => \time_tlock_max1_carry__0_i_2_n_0\
    );
\time_tlock_max1_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(12),
      I1 => time_out_counter_reg(13),
      O => \time_tlock_max1_carry__0_i_3_n_0\
    );
\time_tlock_max1_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(10),
      I1 => time_out_counter_reg(11),
      O => \time_tlock_max1_carry__0_i_4_n_0\
    );
\time_tlock_max1_carry__0_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(8),
      I1 => time_out_counter_reg(9),
      O => \time_tlock_max1_carry__0_i_5_n_0\
    );
\time_tlock_max1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_tlock_max1_carry__0_n_0\,
      CO(3 downto 2) => \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => time_tlock_max1,
      CO(0) => \time_tlock_max1_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => time_out_counter_reg(18),
      DI(0) => \time_tlock_max1_carry__1_i_1_n_0\,
      O(3 downto 0) => \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \time_tlock_max1_carry__1_i_2_n_0\,
      S(0) => \time_tlock_max1_carry__1_i_3_n_0\
    );
\time_tlock_max1_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(16),
      I1 => time_out_counter_reg(17),
      O => \time_tlock_max1_carry__1_i_1_n_0\
    );
\time_tlock_max1_carry__1_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(18),
      O => \time_tlock_max1_carry__1_i_2_n_0\
    );
\time_tlock_max1_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(17),
      I1 => time_out_counter_reg(16),
      O => \time_tlock_max1_carry__1_i_3_n_0\
    );
time_tlock_max1_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_out_counter_reg(4),
      I1 => time_out_counter_reg(5),
      O => time_tlock_max1_carry_i_1_n_0
    );
time_tlock_max1_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(6),
      I1 => time_out_counter_reg(7),
      O => time_tlock_max1_carry_i_2_n_0
    );
time_tlock_max1_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_out_counter_reg(5),
      I1 => time_out_counter_reg(4),
      O => time_tlock_max1_carry_i_3_n_0
    );
time_tlock_max1_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_out_counter_reg(2),
      I1 => time_out_counter_reg(3),
      O => time_tlock_max1_carry_i_4_n_0
    );
time_tlock_max1_carry_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_counter_reg(0),
      I1 => time_out_counter_reg(1),
      O => time_tlock_max1_carry_i_5_n_0
    );
time_tlock_max_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => time_tlock_max1,
      I1 => check_tlock_max_reg_n_0,
      I2 => time_tlock_max,
      O => time_tlock_max_i_1_n_0
    );
time_tlock_max_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => time_tlock_max_i_1_n_0,
      Q => time_tlock_max,
      R => reset_time_out_reg_n_0
    );
\wait_bypass_count[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => run_phase_alignment_int_s3,
      O => clear
    );
\wait_bypass_count[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => time_out_wait_bypass_i_2_n_0,
      I1 => rx_fsm_reset_done_int_s3,
      O => \wait_bypass_count[0]_i_2_n_0\
    );
\wait_bypass_count[0]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_bypass_count_reg(0),
      O => \wait_bypass_count[0]_i_4_n_0\
    );
\wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_7\,
      Q => wait_bypass_count_reg(0),
      R => clear
    );
\wait_bypass_count_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(2) => \wait_bypass_count_reg[0]_i_3_n_1\,
      CO(1) => \wait_bypass_count_reg[0]_i_3_n_2\,
      CO(0) => \wait_bypass_count_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \wait_bypass_count_reg[0]_i_3_n_4\,
      O(2) => \wait_bypass_count_reg[0]_i_3_n_5\,
      O(1) => \wait_bypass_count_reg[0]_i_3_n_6\,
      O(0) => \wait_bypass_count_reg[0]_i_3_n_7\,
      S(3 downto 1) => wait_bypass_count_reg(3 downto 1),
      S(0) => \wait_bypass_count[0]_i_4_n_0\
    );
\wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_5\,
      Q => wait_bypass_count_reg(10),
      R => clear
    );
\wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_4\,
      Q => wait_bypass_count_reg(11),
      R => clear
    );
\wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[12]_i_1_n_7\,
      Q => wait_bypass_count_reg(12),
      R => clear
    );
\wait_bypass_count_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
      O(0) => \wait_bypass_count_reg[12]_i_1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => wait_bypass_count_reg(12)
    );
\wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_6\,
      Q => wait_bypass_count_reg(1),
      R => clear
    );
\wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_5\,
      Q => wait_bypass_count_reg(2),
      R => clear
    );
\wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[0]_i_3_n_4\,
      Q => wait_bypass_count_reg(3),
      R => clear
    );
\wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_7\,
      Q => wait_bypass_count_reg(4),
      R => clear
    );
\wait_bypass_count_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[0]_i_3_n_0\,
      CO(3) => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[4]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[4]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[4]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[4]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[4]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[4]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(7 downto 4)
    );
\wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_6\,
      Q => wait_bypass_count_reg(5),
      R => clear
    );
\wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_5\,
      Q => wait_bypass_count_reg(6),
      R => clear
    );
\wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[4]_i_1_n_4\,
      Q => wait_bypass_count_reg(7),
      R => clear
    );
\wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_7\,
      Q => wait_bypass_count_reg(8),
      R => clear
    );
\wait_bypass_count_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \wait_bypass_count_reg[4]_i_1_n_0\,
      CO(3) => \wait_bypass_count_reg[8]_i_1_n_0\,
      CO(2) => \wait_bypass_count_reg[8]_i_1_n_1\,
      CO(1) => \wait_bypass_count_reg[8]_i_1_n_2\,
      CO(0) => \wait_bypass_count_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \wait_bypass_count_reg[8]_i_1_n_4\,
      O(2) => \wait_bypass_count_reg[8]_i_1_n_5\,
      O(1) => \wait_bypass_count_reg[8]_i_1_n_6\,
      O(0) => \wait_bypass_count_reg[8]_i_1_n_7\,
      S(3 downto 0) => wait_bypass_count_reg(11 downto 8)
    );
\wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => \wait_bypass_count[0]_i_2_n_0\,
      D => \wait_bypass_count_reg[8]_i_1_n_6\,
      Q => wait_bypass_count_reg(9),
      R => clear
    );
\wait_time_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      O => wait_time_cnt0(0)
    );
\wait_time_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => wait_time_cnt_reg(0),
      I1 => wait_time_cnt_reg(1),
      O => \wait_time_cnt[1]_i_1_n_0\
    );
\wait_time_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => wait_time_cnt_reg(1),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(2),
      O => \wait_time_cnt[2]_i_1_n_0\
    );
\wait_time_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => wait_time_cnt_reg(2),
      I1 => wait_time_cnt_reg(0),
      I2 => wait_time_cnt_reg(1),
      I3 => wait_time_cnt_reg(3),
      O => \wait_time_cnt[3]_i_1_n_0\
    );
\wait_time_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => wait_time_cnt_reg(3),
      I1 => wait_time_cnt_reg(1),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(2),
      I4 => wait_time_cnt_reg(4),
      O => \wait_time_cnt[4]_i_1_n_0\
    );
\wait_time_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[5]_i_1_n_0\
    );
\wait_time_cnt[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => rx_state(0),
      I1 => rx_state(1),
      I2 => rx_state(3),
      O => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => sel
    );
\wait_time_cnt[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \wait_time_cnt[6]_i_4_n_0\,
      I1 => wait_time_cnt_reg(6),
      O => \wait_time_cnt[6]_i_3_n_0\
    );
\wait_time_cnt[6]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => wait_time_cnt_reg(4),
      I1 => wait_time_cnt_reg(2),
      I2 => wait_time_cnt_reg(0),
      I3 => wait_time_cnt_reg(1),
      I4 => wait_time_cnt_reg(3),
      I5 => wait_time_cnt_reg(5),
      O => \wait_time_cnt[6]_i_4_n_0\
    );
\wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => wait_time_cnt0(0),
      Q => wait_time_cnt_reg(0),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => \wait_time_cnt[1]_i_1_n_0\,
      Q => wait_time_cnt_reg(1),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => \wait_time_cnt[2]_i_1_n_0\,
      Q => wait_time_cnt_reg(2),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => \wait_time_cnt[3]_i_1_n_0\,
      Q => wait_time_cnt_reg(3),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => sel,
      D => \wait_time_cnt[4]_i_1_n_0\,
      Q => wait_time_cnt_reg(4),
      R => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => \wait_time_cnt[5]_i_1_n_0\,
      Q => wait_time_cnt_reg(5),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
\wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => init_clk_in,
      CE => sel,
      D => \wait_time_cnt[6]_i_3_n_0\,
      Q => wait_time_cnt_reg(6),
      S => \wait_time_cnt[6]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_GT_WRAPPER is
  port (
    gt0_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i : out STD_LOGIC;
    CHBONDDONE_OUT : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_0 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE1 : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxpmaresetdone_out : out STD_LOGIC;
    gt1_rxprbserr_out : out STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_2 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE2 : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxpmaresetdone_out : out STD_LOGIC;
    gt2_rxprbserr_out : out STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_cplllock_out : out STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gthe2_i_4 : out STD_LOGIC;
    CHBONDDONE_OUT_LANE3 : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxpmaresetdone_out : out STD_LOGIC;
    gt3_rxprbserr_out : out STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gthe2_i_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    RX_RESETDONE_OUT : out STD_LOGIC;
    link_reset_r : out STD_LOGIC;
    gthe2_i_6 : out STD_LOGIC;
    gthe2_i_7 : out STD_LOGIC;
    gthe2_i_8 : out STD_LOGIC;
    gthe2_i_9 : out STD_LOGIC;
    gthe2_i_10 : out STD_LOGIC;
    gthe2_i_11 : out STD_LOGIC;
    gthe2_i_12 : out STD_LOGIC;
    gthe2_i_13 : out STD_LOGIC;
    gthe2_i_14 : out STD_LOGIC;
    gthe2_i_15 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg : out STD_LOGIC;
    hard_err_flop_r0 : out STD_LOGIC;
    gthe2_i_16 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_17 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_18 : out STD_LOGIC;
    gthe2_i_19 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg_0 : out STD_LOGIC;
    hard_err_flop_r0_0 : out STD_LOGIC;
    gthe2_i_20 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_21 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_22 : out STD_LOGIC;
    gthe2_i_23 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg_1 : out STD_LOGIC;
    hard_err_flop_r0_1 : out STD_LOGIC;
    gthe2_i_24 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_25 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_26 : out STD_LOGIC;
    gthe2_i_27 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    first_v_received_r_reg_2 : out STD_LOGIC;
    hard_err_flop_r0_2 : out STD_LOGIC;
    gthe2_i_28 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gthe2_i_29 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rxfsm_rxresetdone_r3_reg_0 : out STD_LOGIC;
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPEN_IN : in STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    RXN : in STD_LOGIC_VECTOR ( 0 to 3 );
    RXP : in STD_LOGIC_VECTOR ( 0 to 3 );
    gt_refclk1 : in STD_LOGIC;
    gt_qpllclk_quad2_in : in STD_LOGIC;
    gt_qpllrefclk_quad2_in : in STD_LOGIC;
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_0 : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_0 : in STD_LOGIC;
    gt0_rxprbscntreset_in : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    POWER_DOWN : in STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_rxbufreset_in : in STD_LOGIC;
    gt1_rxcdrhold_in : in STD_LOGIC;
    gt1_rxcdrovrden_in : in STD_LOGIC;
    en_chan_sync_i : in STD_LOGIC;
    gt1_rxdfelpmreset_in : in STD_LOGIC;
    gt1_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_1 : in STD_LOGIC;
    gt1_rxpcsreset_in : in STD_LOGIC;
    gt1_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_1 : in STD_LOGIC;
    gt1_rxprbscntreset_in : in STD_LOGIC;
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt_qpllclk_quad3_in : in STD_LOGIC;
    gt_qpllrefclk_quad3_in : in STD_LOGIC;
    gt2_rxbufreset_in : in STD_LOGIC;
    gt2_rxcdrhold_in : in STD_LOGIC;
    gt2_rxcdrovrden_in : in STD_LOGIC;
    gt2_rxdfelpmreset_in : in STD_LOGIC;
    gt2_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_2 : in STD_LOGIC;
    gt2_rxpcsreset_in : in STD_LOGIC;
    gt2_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_2 : in STD_LOGIC;
    gt2_rxprbscntreset_in : in STD_LOGIC;
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_rxbufreset_in : in STD_LOGIC;
    gt3_rxcdrhold_in : in STD_LOGIC;
    gt3_rxcdrovrden_in : in STD_LOGIC;
    gt3_rxdfelpmreset_in : in STD_LOGIC;
    gt3_rxlpmen_in : in STD_LOGIC;
    ena_comma_align_i_3 : in STD_LOGIC;
    gt3_rxpcsreset_in : in STD_LOGIC;
    gt3_rxpmareset_in : in STD_LOGIC;
    rx_polarity_i_3 : in STD_LOGIC;
    gt3_rxprbscntreset_in : in STD_LOGIC;
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    gtrxreset_i : in STD_LOGIC;
    LINK_RESET_OUT : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_0\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_1\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]_2\ : in STD_LOGIC;
    gtp_rx_reset_i_0 : in STD_LOGIC;
    comma_over_two_cycles_r : in STD_LOGIC;
    first_v_received_r : in STD_LOGIC;
    bucket_full_r : in STD_LOGIC;
    gtp_rx_reset_i_1 : in STD_LOGIC;
    comma_over_two_cycles_r_3 : in STD_LOGIC;
    first_v_received_r_4 : in STD_LOGIC;
    bucket_full_r_5 : in STD_LOGIC;
    gtp_rx_reset_i_2 : in STD_LOGIC;
    comma_over_two_cycles_r_6 : in STD_LOGIC;
    first_v_received_r_7 : in STD_LOGIC;
    bucket_full_r_8 : in STD_LOGIC;
    gtp_rx_reset_i_3 : in STD_LOGIC;
    comma_over_two_cycles_r_9 : in STD_LOGIC;
    first_v_received_r_10 : in STD_LOGIC;
    bucket_full_r_11 : in STD_LOGIC;
    \out\ : in STD_LOGIC
  );
end aurora_rx_4l_64b_GT_WRAPPER;

architecture STRUCTURE of aurora_rx_4l_64b_GT_WRAPPER is
  signal CPLLLOCK : STD_LOGIC;
  signal \^rx_resetdone_out\ : STD_LOGIC;
  signal cpll_reset_i : STD_LOGIC;
  signal fsm_gt_rx_reset_t : STD_LOGIC;
  signal \^gt0_cplllock_out\ : STD_LOGIC;
  signal \^gt0_rxresetdone_out\ : STD_LOGIC;
  signal gt0_rxresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt0_rxresetdone_r3 : STD_LOGIC;
  signal \^gt1_cplllock_out\ : STD_LOGIC;
  signal \^gt1_rxresetdone_out\ : STD_LOGIC;
  signal gt1_rxresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt1_rxresetdone_r3 : STD_LOGIC;
  signal \^gt2_cplllock_out\ : STD_LOGIC;
  signal \^gt2_rxresetdone_out\ : STD_LOGIC;
  signal gt2_rxresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt2_rxresetdone_r3 : STD_LOGIC;
  signal \^gt3_cplllock_out\ : STD_LOGIC;
  signal \^gt3_rxresetdone_out\ : STD_LOGIC;
  signal gt3_rxresetdone_r2_reg_srl2_n_0 : STD_LOGIC;
  signal gt3_rxresetdone_r3 : STD_LOGIC;
  signal gt_rx_reset_i : STD_LOGIC;
  signal gt_rxresetfsm_i_n_3 : STD_LOGIC;
  signal gt_rxuserrdy_i : STD_LOGIC;
  signal gtrxreset_pulse : STD_LOGIC;
  signal gtrxreset_pulse0 : STD_LOGIC;
  signal gtrxreset_r1 : STD_LOGIC;
  signal gtrxreset_r2 : STD_LOGIC;
  signal gtrxreset_r3 : STD_LOGIC;
  signal gtrxreset_sync : STD_LOGIC;
  signal \^link_reset_r\ : STD_LOGIC;
  signal link_reset_r2 : STD_LOGIC;
  signal rx_cdrlock_counter : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \rx_cdrlock_counter[0]_i_2_n_0\ : STD_LOGIC;
  signal \rx_cdrlock_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal \rx_cdrlock_counter[10]_i_2_n_0\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[0]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[10]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[1]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[2]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[3]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[4]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[5]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[6]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[7]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[8]\ : STD_LOGIC;
  signal \rx_cdrlock_counter_reg_n_0_[9]\ : STD_LOGIC;
  signal rx_cdrlocked_i_1_n_0 : STD_LOGIC;
  signal rx_cdrlocked_reg_n_0 : STD_LOGIC;
  signal \rxfsm_rxresetdone_i__0\ : STD_LOGIC;
  signal rxfsm_rxresetdone_r : STD_LOGIC;
  signal rxfsm_rxresetdone_r2 : STD_LOGIC;
  signal rxfsm_soft_reset_r : STD_LOGIC;
  signal rxfsm_soft_reset_r_i_1_n_0 : STD_LOGIC;
  attribute srl_name : string;
  attribute srl_name of gt0_rxresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt0_rxresetdone_r2_reg_srl2 ";
  attribute srl_name of gt1_rxresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt1_rxresetdone_r2_reg_srl2 ";
  attribute srl_name of gt2_rxresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt2_rxresetdone_r2_reg_srl2 ";
  attribute srl_name of gt3_rxresetdone_r2_reg_srl2 : label is "U0/\gt_wrapper_i/gt3_rxresetdone_r2_reg_srl2 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of gt_rx_reset_i_reg : label is "no";
  attribute equivalent_register_removal of gtrxreset_r1_reg : label is "no";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[0]_i_2\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[2]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[3]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[4]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[6]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[7]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[8]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \rx_cdrlock_counter[9]_i_1\ : label is "soft_lutpair20";
  attribute equivalent_register_removal of rxfsm_rxresetdone_r2_reg : label is "no";
begin
  RX_RESETDONE_OUT <= \^rx_resetdone_out\;
  gt0_cplllock_out <= \^gt0_cplllock_out\;
  gt0_rxresetdone_out <= \^gt0_rxresetdone_out\;
  gt1_cplllock_out <= \^gt1_cplllock_out\;
  gt1_rxresetdone_out <= \^gt1_rxresetdone_out\;
  gt2_cplllock_out <= \^gt2_cplllock_out\;
  gt2_rxresetdone_out <= \^gt2_rxresetdone_out\;
  gt3_cplllock_out <= \^gt3_cplllock_out\;
  gt3_rxresetdone_out <= \^gt3_rxresetdone_out\;
  link_reset_r <= \^link_reset_r\;
aurora_rx_4l_64b_multi_gt_i: entity work.aurora_rx_4l_64b_multi_gt
     port map (
      CHBONDDONE_OUT => CHBONDDONE_OUT,
      CHBONDDONE_OUT_LANE1 => CHBONDDONE_OUT_LANE1,
      CHBONDDONE_OUT_LANE2 => CHBONDDONE_OUT_LANE2,
      CHBONDDONE_OUT_LANE3 => CHBONDDONE_OUT_LANE3,
      D(1 downto 0) => D(1 downto 0),
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPADDR_IN_LANE1(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPADDR_IN_LANE2(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPADDR_IN_LANE3(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPEN_IN_LANE1 => DRPEN_IN_LANE1,
      DRPEN_IN_LANE2 => DRPEN_IN_LANE2,
      DRPEN_IN_LANE3 => DRPEN_IN_LANE3,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPRDY_OUT_LANE1 => DRPRDY_OUT_LANE1,
      DRPRDY_OUT_LANE2 => DRPRDY_OUT_LANE2,
      DRPRDY_OUT_LANE3 => DRPRDY_OUT_LANE3,
      DRPWE_IN => DRPWE_IN,
      DRPWE_IN_LANE1 => DRPWE_IN_LANE1,
      DRPWE_IN_LANE2 => DRPWE_IN_LANE2,
      DRPWE_IN_LANE3 => DRPWE_IN_LANE3,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXN(0 to 3) => RXN(0 to 3),
      RXP(0 to 3) => RXP(0 to 3),
      SR(0) => gt_rx_reset_i,
      TX_LOCK => TX_LOCK,
      TX_OUT_CLK => TX_OUT_CLK,
      bucket_full_r => bucket_full_r,
      bucket_full_r_11 => bucket_full_r_11,
      bucket_full_r_5 => bucket_full_r_5,
      bucket_full_r_8 => bucket_full_r_8,
      comma_over_two_cycles_r => comma_over_two_cycles_r,
      comma_over_two_cycles_r_3 => comma_over_two_cycles_r_3,
      comma_over_two_cycles_r_6 => comma_over_two_cycles_r_6,
      comma_over_two_cycles_r_9 => comma_over_two_cycles_r_9,
      cpll_reset_i => cpll_reset_i,
      drpclk_in => drpclk_in,
      en_chan_sync_i => en_chan_sync_i,
      ena_comma_align_i_0 => ena_comma_align_i_0,
      ena_comma_align_i_1 => ena_comma_align_i_1,
      ena_comma_align_i_2 => ena_comma_align_i_2,
      ena_comma_align_i_3 => ena_comma_align_i_3,
      first_v_received_r => first_v_received_r,
      first_v_received_r_10 => first_v_received_r_10,
      first_v_received_r_4 => first_v_received_r_4,
      first_v_received_r_7 => first_v_received_r_7,
      first_v_received_r_reg => first_v_received_r_reg,
      first_v_received_r_reg_0 => first_v_received_r_reg_0,
      first_v_received_r_reg_1 => first_v_received_r_reg_1,
      first_v_received_r_reg_2 => first_v_received_r_reg_2,
      flag2_reg => gt_rxresetfsm_i_n_3,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt0_cplllock_out => \^gt0_cplllock_out\,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_rx_disp_err_out(1 downto 0) => gt0_rx_disp_err_out(1 downto 0),
      gt0_rx_not_in_table_out(1 downto 0) => gt0_rx_not_in_table_out(1 downto 0),
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2 downto 0) => gt0_rxbufstatus_out(2 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => \^gt0_rxresetdone_out\,
      gt1_cplllock_out => \^gt1_cplllock_out\,
      gt1_dmonitorout_out(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
      gt1_eyescanreset_in => gt1_eyescanreset_in,
      gt1_eyescantrigger_in => gt1_eyescantrigger_in,
      gt1_rx_disp_err_out(1 downto 0) => gt1_rx_disp_err_out(1 downto 0),
      gt1_rx_not_in_table_out(1 downto 0) => gt1_rx_not_in_table_out(1 downto 0),
      gt1_rxbufreset_in => gt1_rxbufreset_in,
      gt1_rxbufstatus_out(2 downto 0) => gt1_rxbufstatus_out(2 downto 0),
      gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
      gt1_rxcdrhold_in => gt1_rxcdrhold_in,
      gt1_rxcdrovrden_in => gt1_rxcdrovrden_in,
      gt1_rxcommadet_out => gt1_rxcommadet_out,
      gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
      gt1_rxlpmen_in => gt1_rxlpmen_in,
      gt1_rxmonitorout_out(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      gt1_rxmonitorsel_in(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      gt1_rxpcsreset_in => gt1_rxpcsreset_in,
      gt1_rxpmareset_in => gt1_rxpmareset_in,
      gt1_rxpmaresetdone_out => gt1_rxpmaresetdone_out,
      gt1_rxprbscntreset_in => gt1_rxprbscntreset_in,
      gt1_rxprbserr_out => gt1_rxprbserr_out,
      gt1_rxprbssel_in(2 downto 0) => gt1_rxprbssel_in(2 downto 0),
      gt1_rxresetdone_out => \^gt1_rxresetdone_out\,
      gt2_cplllock_out => \^gt2_cplllock_out\,
      gt2_dmonitorout_out(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      gt2_eyescandataerror_out => gt2_eyescandataerror_out,
      gt2_eyescanreset_in => gt2_eyescanreset_in,
      gt2_eyescantrigger_in => gt2_eyescantrigger_in,
      gt2_rx_disp_err_out(1 downto 0) => gt2_rx_disp_err_out(1 downto 0),
      gt2_rx_not_in_table_out(1 downto 0) => gt2_rx_not_in_table_out(1 downto 0),
      gt2_rxbufreset_in => gt2_rxbufreset_in,
      gt2_rxbufstatus_out(2 downto 0) => gt2_rxbufstatus_out(2 downto 0),
      gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
      gt2_rxcdrhold_in => gt2_rxcdrhold_in,
      gt2_rxcdrovrden_in => gt2_rxcdrovrden_in,
      gt2_rxcommadet_out => gt2_rxcommadet_out,
      gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
      gt2_rxlpmen_in => gt2_rxlpmen_in,
      gt2_rxmonitorout_out(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      gt2_rxmonitorsel_in(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      gt2_rxpcsreset_in => gt2_rxpcsreset_in,
      gt2_rxpmareset_in => gt2_rxpmareset_in,
      gt2_rxpmaresetdone_out => gt2_rxpmaresetdone_out,
      gt2_rxprbscntreset_in => gt2_rxprbscntreset_in,
      gt2_rxprbserr_out => gt2_rxprbserr_out,
      gt2_rxprbssel_in(2 downto 0) => gt2_rxprbssel_in(2 downto 0),
      gt2_rxresetdone_out => \^gt2_rxresetdone_out\,
      gt3_cplllock_out => \^gt3_cplllock_out\,
      gt3_dmonitorout_out(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      gt3_eyescandataerror_out => gt3_eyescandataerror_out,
      gt3_eyescanreset_in => gt3_eyescanreset_in,
      gt3_eyescantrigger_in => gt3_eyescantrigger_in,
      gt3_rx_disp_err_out(1 downto 0) => gt3_rx_disp_err_out(1 downto 0),
      gt3_rx_not_in_table_out(1 downto 0) => gt3_rx_not_in_table_out(1 downto 0),
      gt3_rxbufreset_in => gt3_rxbufreset_in,
      gt3_rxbufstatus_out(2 downto 0) => gt3_rxbufstatus_out(2 downto 0),
      gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
      gt3_rxcdrhold_in => gt3_rxcdrhold_in,
      gt3_rxcdrovrden_in => gt3_rxcdrovrden_in,
      gt3_rxcommadet_out => gt3_rxcommadet_out,
      gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
      gt3_rxlpmen_in => gt3_rxlpmen_in,
      gt3_rxmonitorout_out(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      gt3_rxmonitorsel_in(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      gt3_rxpcsreset_in => gt3_rxpcsreset_in,
      gt3_rxpmareset_in => gt3_rxpmareset_in,
      gt3_rxpmaresetdone_out => gt3_rxpmaresetdone_out,
      gt3_rxprbscntreset_in => gt3_rxprbscntreset_in,
      gt3_rxprbserr_out => gt3_rxprbserr_out,
      gt3_rxprbssel_in(2 downto 0) => gt3_rxprbssel_in(2 downto 0),
      gt3_rxresetdone_out => \^gt3_rxresetdone_out\,
      gt_qpllclk_quad2_in => gt_qpllclk_quad2_in,
      gt_qpllclk_quad3_in => gt_qpllclk_quad3_in,
      gt_qpllrefclk_quad2_in => gt_qpllrefclk_quad2_in,
      gt_qpllrefclk_quad3_in => gt_qpllrefclk_quad3_in,
      gt_refclk1 => gt_refclk1,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      gthe2_i => gthe2_i,
      gthe2_i_0 => gthe2_i_0,
      gthe2_i_1(1 downto 0) => gthe2_i_1(1 downto 0),
      gthe2_i_10 => gthe2_i_10,
      gthe2_i_11 => gthe2_i_11,
      gthe2_i_12 => gthe2_i_12,
      gthe2_i_13 => gthe2_i_13,
      gthe2_i_14 => gthe2_i_14,
      gthe2_i_15(1 downto 0) => gthe2_i_15(1 downto 0),
      gthe2_i_16(7 downto 0) => gthe2_i_16(7 downto 0),
      gthe2_i_17(7 downto 0) => gthe2_i_17(7 downto 0),
      gthe2_i_18 => gthe2_i_18,
      gthe2_i_19(1 downto 0) => gthe2_i_19(1 downto 0),
      gthe2_i_2 => gthe2_i_2,
      gthe2_i_20(7 downto 0) => gthe2_i_20(7 downto 0),
      gthe2_i_21(7 downto 0) => gthe2_i_21(7 downto 0),
      gthe2_i_22 => gthe2_i_22,
      gthe2_i_23(1 downto 0) => gthe2_i_23(1 downto 0),
      gthe2_i_24(7 downto 0) => gthe2_i_24(7 downto 0),
      gthe2_i_25(7 downto 0) => gthe2_i_25(7 downto 0),
      gthe2_i_26 => gthe2_i_26,
      gthe2_i_27(1 downto 0) => gthe2_i_27(1 downto 0),
      gthe2_i_28(7 downto 0) => gthe2_i_28(7 downto 0),
      gthe2_i_29(7 downto 0) => gthe2_i_29(7 downto 0),
      gthe2_i_3(1 downto 0) => gthe2_i_3(1 downto 0),
      gthe2_i_4 => gthe2_i_4,
      gthe2_i_5(1 downto 0) => gthe2_i_5(1 downto 0),
      gthe2_i_6 => gthe2_i_6,
      gthe2_i_7 => gthe2_i_7,
      gthe2_i_8 => gthe2_i_8,
      gthe2_i_9 => gthe2_i_9,
      gtp_rx_reset_i_0 => gtp_rx_reset_i_0,
      gtp_rx_reset_i_1 => gtp_rx_reset_i_1,
      gtp_rx_reset_i_2 => gtp_rx_reset_i_2,
      gtp_rx_reset_i_3 => gtp_rx_reset_i_3,
      hard_err_flop_r0 => hard_err_flop_r0,
      hard_err_flop_r0_0 => hard_err_flop_r0_0,
      hard_err_flop_r0_1 => hard_err_flop_r0_1,
      hard_err_flop_r0_2 => hard_err_flop_r0_2,
      init_clk_in => init_clk_in,
      rx_polarity_i_0 => rx_polarity_i_0,
      rx_polarity_i_1 => rx_polarity_i_1,
      rx_polarity_i_2 => rx_polarity_i_2,
      rx_polarity_i_3 => rx_polarity_i_3,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[1]\ => \word_aligned_control_bits_r_reg[1]\,
      \word_aligned_control_bits_r_reg[1]_0\ => \word_aligned_control_bits_r_reg[1]_0\,
      \word_aligned_control_bits_r_reg[1]_1\ => \word_aligned_control_bits_r_reg[1]_1\,
      \word_aligned_control_bits_r_reg[1]_2\ => \word_aligned_control_bits_r_reg[1]_2\
    );
gt0_rxresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt0_rxresetdone_out\,
      Q => gt0_rxresetdone_r2_reg_srl2_n_0
    );
gt0_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt0_rxresetdone_r2_reg_srl2_n_0,
      Q => gt0_rxresetdone_r3,
      R => '0'
    );
gt1_rxresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt1_rxresetdone_out\,
      Q => gt1_rxresetdone_r2_reg_srl2_n_0
    );
gt1_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt1_rxresetdone_r2_reg_srl2_n_0,
      Q => gt1_rxresetdone_r3,
      R => '0'
    );
gt2_rxresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt2_rxresetdone_out\,
      Q => gt2_rxresetdone_r2_reg_srl2_n_0
    );
gt2_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt2_rxresetdone_r2_reg_srl2_n_0,
      Q => gt2_rxresetdone_r3,
      R => '0'
    );
gt3_rxresetdone_r2_reg_srl2: unisim.vcomponents.SRL16E
     port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => user_clk,
      D => \^gt3_rxresetdone_out\,
      Q => gt3_rxresetdone_r2_reg_srl2_n_0
    );
gt3_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => gt3_rxresetdone_r2_reg_srl2_n_0,
      Q => gt3_rxresetdone_r3,
      R => '0'
    );
gt_pll_lock_i: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^gt3_cplllock_out\,
      I1 => \^gt0_cplllock_out\,
      I2 => \^gt1_cplllock_out\,
      I3 => \^gt2_cplllock_out\,
      O => CPLLLOCK
    );
gt_rx_reset_i_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => fsm_gt_rx_reset_t,
      Q => gt_rx_reset_i,
      R => '0'
    );
gt_rxresetdone_r_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rx_resetdone_out\,
      O => rxfsm_rxresetdone_r3_reg_0
    );
gt_rxresetfsm_i: entity work.aurora_rx_4l_64b_rx_startup_fsm
     port map (
      AR(0) => rxfsm_soft_reset_r,
      CPLL_RESET_reg_0 => gt_rxresetfsm_i_n_3,
      cpll_reset_i => cpll_reset_i,
      fsm_gt_rx_reset_t => fsm_gt_rx_reset_t,
      gt_rxuserrdy_i => gt_rxuserrdy_i,
      in0 => CPLLLOCK,
      init_clk_in => init_clk_in,
      reset_time_out_reg_0 => rx_cdrlocked_reg_n_0,
      rxfsm_rxresetdone_r => rxfsm_rxresetdone_r,
      user_clk => user_clk
    );
gtrxreset_cdc_sync: entity work.\aurora_rx_4l_64b_cdc_sync__parameterized2_21\
     port map (
      gtrxreset_i => gtrxreset_i,
      init_clk_in => init_clk_in,
      \out\ => gtrxreset_sync,
      user_clk => user_clk
    );
gtrxreset_pulse_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => gtrxreset_r2,
      I1 => gtrxreset_r3,
      O => gtrxreset_pulse0
    );
gtrxreset_pulse_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_pulse0,
      Q => gtrxreset_pulse,
      R => '0'
    );
gtrxreset_r1_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_sync,
      Q => gtrxreset_r1,
      R => '0'
    );
gtrxreset_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_r1,
      Q => gtrxreset_r2,
      R => '0'
    );
gtrxreset_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => gtrxreset_r2,
      Q => gtrxreset_r3,
      R => '0'
    );
link_reset_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => \^link_reset_r\,
      Q => link_reset_r2,
      R => '0'
    );
link_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => LINK_RESET_OUT,
      Q => \^link_reset_r\,
      R => '0'
    );
\rx_cdrlock_counter[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFBF"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[6]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[5]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[1]\,
      I3 => \rx_cdrlock_counter[0]_i_2_n_0\,
      I4 => \rx_cdrlock_counter[0]_i_3_n_0\,
      I5 => \rx_cdrlock_counter_reg_n_0_[0]\,
      O => rx_cdrlock_counter(0)
    );
\rx_cdrlock_counter[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[10]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[0]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[2]\,
      I3 => \rx_cdrlock_counter_reg_n_0_[4]\,
      O => \rx_cdrlock_counter[0]_i_2_n_0\
    );
\rx_cdrlock_counter[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[7]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[9]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[8]\,
      I3 => \rx_cdrlock_counter_reg_n_0_[3]\,
      O => \rx_cdrlock_counter[0]_i_3_n_0\
    );
\rx_cdrlock_counter[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[10]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[8]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[6]\,
      I3 => \rx_cdrlock_counter[10]_i_2_n_0\,
      I4 => \rx_cdrlock_counter_reg_n_0_[7]\,
      I5 => \rx_cdrlock_counter_reg_n_0_[9]\,
      O => rx_cdrlock_counter(10)
    );
\rx_cdrlock_counter[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[5]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[4]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[2]\,
      I3 => \rx_cdrlock_counter_reg_n_0_[0]\,
      I4 => \rx_cdrlock_counter_reg_n_0_[1]\,
      I5 => \rx_cdrlock_counter_reg_n_0_[3]\,
      O => \rx_cdrlock_counter[10]_i_2_n_0\
    );
\rx_cdrlock_counter[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[0]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[1]\,
      O => rx_cdrlock_counter(1)
    );
\rx_cdrlock_counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[2]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[0]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[1]\,
      O => rx_cdrlock_counter(2)
    );
\rx_cdrlock_counter[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[3]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[1]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[0]\,
      I3 => \rx_cdrlock_counter_reg_n_0_[2]\,
      O => rx_cdrlock_counter(3)
    );
\rx_cdrlock_counter[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[4]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[2]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[0]\,
      I3 => \rx_cdrlock_counter_reg_n_0_[1]\,
      I4 => \rx_cdrlock_counter_reg_n_0_[3]\,
      O => rx_cdrlock_counter(4)
    );
\rx_cdrlock_counter[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[3]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[1]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[0]\,
      I3 => \rx_cdrlock_counter_reg_n_0_[2]\,
      I4 => \rx_cdrlock_counter_reg_n_0_[4]\,
      I5 => \rx_cdrlock_counter_reg_n_0_[5]\,
      O => rx_cdrlock_counter(5)
    );
\rx_cdrlock_counter[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[6]\,
      I1 => \rx_cdrlock_counter[10]_i_2_n_0\,
      O => rx_cdrlock_counter(6)
    );
\rx_cdrlock_counter[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[7]\,
      I1 => \rx_cdrlock_counter[10]_i_2_n_0\,
      I2 => \rx_cdrlock_counter_reg_n_0_[6]\,
      O => rx_cdrlock_counter(7)
    );
\rx_cdrlock_counter[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[8]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[6]\,
      I2 => \rx_cdrlock_counter[10]_i_2_n_0\,
      I3 => \rx_cdrlock_counter_reg_n_0_[7]\,
      O => rx_cdrlock_counter(8)
    );
\rx_cdrlock_counter[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[9]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[7]\,
      I2 => \rx_cdrlock_counter[10]_i_2_n_0\,
      I3 => \rx_cdrlock_counter_reg_n_0_[6]\,
      I4 => \rx_cdrlock_counter_reg_n_0_[8]\,
      O => rx_cdrlock_counter(9)
    );
\rx_cdrlock_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(0),
      Q => \rx_cdrlock_counter_reg_n_0_[0]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(10),
      Q => \rx_cdrlock_counter_reg_n_0_[10]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(1),
      Q => \rx_cdrlock_counter_reg_n_0_[1]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(2),
      Q => \rx_cdrlock_counter_reg_n_0_[2]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(3),
      Q => \rx_cdrlock_counter_reg_n_0_[3]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(4),
      Q => \rx_cdrlock_counter_reg_n_0_[4]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(5),
      Q => \rx_cdrlock_counter_reg_n_0_[5]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(6),
      Q => \rx_cdrlock_counter_reg_n_0_[6]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(7),
      Q => \rx_cdrlock_counter_reg_n_0_[7]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(8),
      Q => \rx_cdrlock_counter_reg_n_0_[8]\,
      R => gt_rx_reset_i
    );
\rx_cdrlock_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlock_counter(9),
      Q => \rx_cdrlock_counter_reg_n_0_[9]\,
      R => gt_rx_reset_i
    );
rx_cdrlocked_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000040"
    )
        port map (
      I0 => \rx_cdrlock_counter_reg_n_0_[6]\,
      I1 => \rx_cdrlock_counter_reg_n_0_[5]\,
      I2 => \rx_cdrlock_counter_reg_n_0_[1]\,
      I3 => \rx_cdrlock_counter[0]_i_2_n_0\,
      I4 => \rx_cdrlock_counter[0]_i_3_n_0\,
      I5 => rx_cdrlocked_reg_n_0,
      O => rx_cdrlocked_i_1_n_0
    );
rx_cdrlocked_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => rx_cdrlocked_i_1_n_0,
      Q => rx_cdrlocked_reg_n_0,
      R => gt_rx_reset_i
    );
rxfsm_rxresetdone_i: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => gt3_rxresetdone_r3,
      I1 => gt0_rxresetdone_r3,
      I2 => gt1_rxresetdone_r3,
      I3 => gt2_rxresetdone_r3,
      O => \rxfsm_rxresetdone_i__0\
    );
rxfsm_rxresetdone_r2_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rxfsm_rxresetdone_r,
      Q => rxfsm_rxresetdone_r2,
      R => '0'
    );
rxfsm_rxresetdone_r3_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rxfsm_rxresetdone_r2,
      Q => \^rx_resetdone_out\,
      R => '0'
    );
rxfsm_rxresetdone_r_reg: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rxfsm_rxresetdone_i__0\,
      Q => rxfsm_rxresetdone_r,
      R => '0'
    );
rxfsm_soft_reset_r_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \out\,
      I1 => gtrxreset_pulse,
      I2 => link_reset_r2,
      O => rxfsm_soft_reset_r_i_1_n_0
    );
rxfsm_soft_reset_r_reg: unisim.vcomponents.FDRE
     port map (
      C => init_clk_in,
      CE => '1',
      D => rxfsm_soft_reset_r_i_1_n_0,
      Q => rxfsm_soft_reset_r,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5 is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ena_comma_align_i_0 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    gtp_rx_reset_i_0 : out STD_LOGIC;
    GOT_V : out STD_LOGIC;
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    link_reset_lane0_i : out STD_LOGIC;
    RX_PE_DATA : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RX_SCP_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF : out STD_LOGIC;
    rx_polarity_i_0 : out STD_LOGIC;
    left_aligned_r_reg : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]\ : out STD_LOGIC;
    RX_SUF_Buffer_reg : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]_0\ : out STD_LOGIC;
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    good_as_r0 : out STD_LOGIC;
    GOT_A : out STD_LOGIC_VECTOR ( 0 to 1 );
    \word_aligned_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]\ : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    start_rx_i : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[2]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[3]\ : in STD_LOGIC;
    begin_r_reg : in STD_LOGIC;
    reset_count_r_reg : in STD_LOGIC;
    \counter2_r_reg[15]\ : in STD_LOGIC;
    good_as_r_reg : in STD_LOGIC;
    good_as_r_reg_0 : in STD_LOGIC;
    good_as_r_reg_1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    good_as_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    good_as_r_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_CHAR_IS_COMMA_R_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg_0 : in STD_LOGIC;
    \soft_err_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \word_aligned_data_r_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
end aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5;

architecture STRUCTURE of aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5 is
  signal RX_CC_Buffer : STD_LOGIC;
  signal RX_NEG_Buffer : STD_LOGIC;
  signal begin_r0 : STD_LOGIC;
  signal enable_err_detect_i : STD_LOGIC;
  signal \^left_aligned_r_reg\ : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_6 : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_7 : STD_LOGIC;
  signal rx_sp_i : STD_LOGIC;
begin
  left_aligned_r_reg <= \^left_aligned_r_reg\;
aurora_rx_4l_64b_hotplug_i: entity work.aurora_rx_4l_64b_HOTPLUG_16
     port map (
      D(0) => RX_CC_Buffer,
      HPCNT_RESET => HPCNT_RESET,
      SR(0) => SR(0),
      init_clk_in => init_clk_in,
      link_reset_lane0_i => link_reset_lane0_i,
      user_clk => user_clk
    );
rx_err_detect_simplex_gtp_i: entity work.aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17
     port map (
      D(0) => D(0),
      SR(0) => SR(0),
      begin_r0 => begin_r0,
      bucket_full_r => bucket_full_r,
      enable_err_detect_i => enable_err_detect_i,
      hard_err_flop_r0 => hard_err_flop_r0,
      hard_err_flop_r_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \soft_err_r_reg[0]_0\(1 downto 0) => \soft_err_r_reg[0]\(1 downto 0),
      user_clk => user_clk,
      user_clk_0 => user_clk_0
    );
rx_lane_init_sm_simplex_i: entity work.aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18
     port map (
      ENABLE_ERR_DETECT_Buffer_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \RX_CHAR_IS_COMMA_R_reg[1]_0\(1 downto 0) => \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0),
      RX_LANE_UP(0) => RX_LANE_UP(0),
      RX_NEG_Buffer => RX_NEG_Buffer,
      SR(0) => SR(0),
      align_r_reg_0 => ena_comma_align_i_0,
      begin_r0 => begin_r0,
      begin_r_reg_0 => begin_r_reg,
      comma_over_two_cycles_r => comma_over_two_cycles_r,
      \counter2_r_reg[15]_0\ => \counter2_r_reg[15]\,
      enable_err_detect_i => enable_err_detect_i,
      gthe2_i => rx_lane_init_sm_simplex_i_n_6,
      left_aligned_r_reg => left_aligned_r_reg_0,
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      reset_count_r_reg_0 => reset_count_r_reg,
      rst_r_reg_0 => gtp_rx_reset_i_0,
      rx_polarity_i_0 => rx_polarity_i_0,
      rx_sp_i => rx_sp_i,
      user_clk => user_clk
    );
sym_dec_i: entity work.aurora_rx_4l_64b_SYM_DEC_19
     port map (
      D(0) => RX_CC_Buffer,
      GOT_A(0 to 1) => GOT_A(0 to 1),
      GOT_V => GOT_V,
      Q(0) => Q(0),
      RX_ECP_Buffer0 => RX_ECP_Buffer0,
      RX_NEG_Buffer => RX_NEG_Buffer,
      RX_PE_DATA(0) => RX_PE_DATA(0),
      \RX_PE_DATA_Buffer_reg[10]_0\ => \RX_PE_DATA_Buffer_reg[10]\,
      \RX_PE_DATA_Buffer_reg[8]_0\ => RX_PE_DATA(2),
      \RX_PE_DATA_Buffer_reg[8]_1\ => \RX_PE_DATA_Buffer_reg[8]\,
      \RX_PE_DATA_Buffer_reg[8]_2\ => \RX_PE_DATA_Buffer_reg[8]_0\,
      \RX_PE_DATA_Buffer_reg[9]_0\ => RX_PE_DATA(1),
      RX_PE_DATA_V_Buffer_reg_0(0) => RX_PE_DATA_V_Buffer_reg(0),
      RX_SCP_Buffer_reg_0(0) => RX_SCP_Buffer_reg(0),
      RX_SUF_Buffer_reg_0 => RX_SUF,
      RX_SUF_Buffer_reg_1 => RX_SUF_Buffer_reg,
      RX_SUF_Buffer_reg_2 => RX_SUF_Buffer_reg_0,
      SR(0) => SR(0),
      first_v_received_r => first_v_received_r,
      good_as_r0 => good_as_r0,
      good_as_r_reg => good_as_r_reg,
      good_as_r_reg_0 => good_as_r_reg_0,
      good_as_r_reg_1 => good_as_r_reg_1,
      good_as_r_reg_2(0) => good_as_r_reg_2(0),
      good_as_r_reg_3(0) => good_as_r_reg_3(0),
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      left_aligned_r_reg_1 => rx_lane_init_sm_simplex_i_n_6,
      rx_sp_i => rx_sp_i,
      \stage_1_count_value_r_reg[1]\ => \stage_1_count_value_r_reg[1]\,
      \stage_1_count_value_r_reg[2]\ => \stage_1_count_value_r_reg[2]\,
      \stage_1_lane_mask_r_reg[2]\ => \stage_1_lane_mask_r_reg[2]\,
      \stage_1_lane_mask_r_reg[3]\ => \stage_1_lane_mask_r_reg[3]\,
      start_rx_i => start_rx_i,
      std_bool26_out => std_bool26_out,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[0]_0\ => \word_aligned_control_bits_r_reg[0]\,
      \word_aligned_control_bits_r_reg[1]_0\ => \word_aligned_control_bits_r_reg[1]\,
      \word_aligned_data_r_reg[0]_0\(7 downto 0) => \word_aligned_data_r_reg[0]\(7 downto 0),
      \word_aligned_data_r_reg[0]_1\(7 downto 0) => \word_aligned_data_r_reg[0]_0\(7 downto 0),
      \word_aligned_data_r_reg[11]_0\(4 downto 0) => \word_aligned_data_r_reg[11]\(4 downto 0),
      \word_aligned_data_r_reg[8]_0\(7 downto 0) => \word_aligned_data_r_reg[8]\(7 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2 is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ena_comma_align_i_1 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    gtp_rx_reset_i_1 : out STD_LOGIC;
    GOT_V_Buffer_reg : out STD_LOGIC;
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    link_reset_lane1_i : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]\ : out STD_LOGIC;
    RX_SCP_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg : out STD_LOGIC;
    rx_polarity_i_1 : out STD_LOGIC;
    left_aligned_r_reg : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_0\ : out STD_LOGIC;
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_1\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]_2\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    \GOT_A_Buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \GOT_A_Buffer_reg[0]\ : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]\ : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    RX_SUF : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    begin_r_reg : in STD_LOGIC;
    reset_count_r_reg : in STD_LOGIC;
    \counter2_r_reg[15]\ : in STD_LOGIC;
    \RX_CHAR_IS_COMMA_R_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg_0 : in STD_LOGIC;
    \soft_err_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \word_aligned_data_r_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2 : entity is "aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5";
end aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2;

architecture STRUCTURE of aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2 is
  signal RX_CC_Buffer : STD_LOGIC;
  signal RX_NEG_Buffer : STD_LOGIC;
  signal begin_r0 : STD_LOGIC;
  signal enable_err_detect_i : STD_LOGIC;
  signal \^left_aligned_r_reg\ : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_6 : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_7 : STD_LOGIC;
  signal rx_sp_i : STD_LOGIC;
begin
  left_aligned_r_reg <= \^left_aligned_r_reg\;
aurora_rx_4l_64b_hotplug_i: entity work.aurora_rx_4l_64b_HOTPLUG_11
     port map (
      D(0) => RX_CC_Buffer,
      HPCNT_RESET => HPCNT_RESET,
      SR(0) => SR(0),
      init_clk_in => init_clk_in,
      link_reset_lane1_i => link_reset_lane1_i,
      user_clk => user_clk
    );
rx_err_detect_simplex_gtp_i: entity work.aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12
     port map (
      D(0) => D(0),
      SR(0) => SR(0),
      begin_r0 => begin_r0,
      bucket_full_r => bucket_full_r,
      enable_err_detect_i => enable_err_detect_i,
      hard_err_flop_r0 => hard_err_flop_r0,
      hard_err_flop_r_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \soft_err_r_reg[0]_0\(1 downto 0) => \soft_err_r_reg[0]\(1 downto 0),
      user_clk => user_clk,
      user_clk_0 => user_clk_0
    );
rx_lane_init_sm_simplex_i: entity work.aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13
     port map (
      ENABLE_ERR_DETECT_Buffer_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \RX_CHAR_IS_COMMA_R_reg[1]_0\(1 downto 0) => \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0),
      RX_LANE_UP(0) => RX_LANE_UP(0),
      RX_NEG_Buffer => RX_NEG_Buffer,
      SR(0) => SR(0),
      align_r_reg_0 => ena_comma_align_i_1,
      begin_r0 => begin_r0,
      begin_r_reg_0 => begin_r_reg,
      comma_over_two_cycles_r => comma_over_two_cycles_r,
      \counter2_r_reg[15]_0\ => \counter2_r_reg[15]\,
      enable_err_detect_i => enable_err_detect_i,
      gthe2_i => rx_lane_init_sm_simplex_i_n_6,
      left_aligned_r_reg => left_aligned_r_reg_0,
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      reset_count_r_reg_0 => reset_count_r_reg,
      rst_r_reg_0 => gtp_rx_reset_i_1,
      rx_polarity_i_1 => rx_polarity_i_1,
      rx_sp_i => rx_sp_i,
      user_clk => user_clk
    );
sym_dec_i: entity work.aurora_rx_4l_64b_SYM_DEC_14
     port map (
      D(0) => RX_CC_Buffer,
      \GOT_A_Buffer_reg[0]_0\ => \GOT_A_Buffer_reg[0]\,
      \GOT_A_Buffer_reg[1]_0\(0) => \GOT_A_Buffer_reg[1]\(0),
      GOT_V_Buffer_reg_0 => GOT_V_Buffer_reg,
      Q(4 downto 0) => Q(4 downto 0),
      RX_ECP_Buffer0 => RX_ECP_Buffer0,
      RX_NEG_Buffer => RX_NEG_Buffer,
      \RX_PE_DATA_Buffer_reg[10]_0\ => \RX_PE_DATA_Buffer_reg[10]\,
      \RX_PE_DATA_Buffer_reg[10]_1\ => \RX_PE_DATA_Buffer_reg[10]_0\,
      \RX_PE_DATA_Buffer_reg[10]_2\ => \RX_PE_DATA_Buffer_reg[10]_1\,
      \RX_PE_DATA_Buffer_reg[10]_3\ => \RX_PE_DATA_Buffer_reg[10]_2\,
      \RX_PE_DATA_Buffer_reg[8]_0\ => \RX_PE_DATA_Buffer_reg[8]\,
      \RX_PE_DATA_Buffer_reg[9]_0\ => \RX_PE_DATA_Buffer_reg[9]\,
      RX_PE_DATA_V_Buffer_reg_0(0) => RX_PE_DATA_V_Buffer_reg(0),
      RX_SCP_Buffer_reg_0(0) => RX_SCP_Buffer_reg(0),
      RX_SUF => RX_SUF,
      RX_SUF_Buffer_reg_0 => RX_SUF_Buffer_reg,
      RX_SUF_Buffer_reg_1 => RX_SUF_Buffer_reg_0,
      SR(0) => SR(0),
      first_v_received_r => first_v_received_r,
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      left_aligned_r_reg_1 => rx_lane_init_sm_simplex_i_n_6,
      rx_sp_i => rx_sp_i,
      \stage_1_count_value_r_reg[1]\ => \stage_1_count_value_r_reg[1]\,
      \stage_1_count_value_r_reg[2]\ => \stage_1_count_value_r_reg[2]\,
      std_bool26_out => std_bool26_out,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[0]_0\ => \word_aligned_control_bits_r_reg[0]\,
      \word_aligned_control_bits_r_reg[1]_0\ => \word_aligned_control_bits_r_reg[1]\,
      \word_aligned_data_r_reg[0]_0\(7 downto 0) => \word_aligned_data_r_reg[0]\(7 downto 0),
      \word_aligned_data_r_reg[0]_1\(7 downto 0) => \word_aligned_data_r_reg[0]_0\(7 downto 0),
      \word_aligned_data_r_reg[8]_0\(7 downto 0) => \word_aligned_data_r_reg[8]\(7 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3 is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ena_comma_align_i_2 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    gtp_rx_reset_i_2 : out STD_LOGIC;
    GOT_V_Buffer_reg : out STD_LOGIC;
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    link_reset_lane2_i : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]\ : out STD_LOGIC;
    RX_SCP_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg : out STD_LOGIC;
    rx_polarity_i_2 : out STD_LOGIC;
    left_aligned_r_reg : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    neqOp : out STD_LOGIC;
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    \GOT_A_Buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \GOT_A_Buffer_reg[0]\ : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]\ : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    load_ufc_control_code_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \stage_1_count_value_r_reg[3]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]_1\ : in STD_LOGIC;
    begin_r_reg : in STD_LOGIC;
    reset_count_r_reg : in STD_LOGIC;
    \counter2_r_reg[15]\ : in STD_LOGIC;
    \RX_CHAR_IS_COMMA_R_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg_0 : in STD_LOGIC;
    \soft_err_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \word_aligned_data_r_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3 : entity is "aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5";
end aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3;

architecture STRUCTURE of aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3 is
  signal RX_CC_Buffer : STD_LOGIC;
  signal RX_NEG_Buffer : STD_LOGIC;
  signal begin_r0 : STD_LOGIC;
  signal enable_err_detect_i : STD_LOGIC;
  signal \^left_aligned_r_reg\ : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_6 : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_7 : STD_LOGIC;
  signal rx_sp_i : STD_LOGIC;
begin
  left_aligned_r_reg <= \^left_aligned_r_reg\;
aurora_rx_4l_64b_hotplug_i: entity work.aurora_rx_4l_64b_HOTPLUG_6
     port map (
      D(0) => RX_CC_Buffer,
      HPCNT_RESET => HPCNT_RESET,
      SR(0) => SR(0),
      init_clk_in => init_clk_in,
      link_reset_lane2_i => link_reset_lane2_i,
      user_clk => user_clk
    );
rx_err_detect_simplex_gtp_i: entity work.aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7
     port map (
      D(0) => D(0),
      SR(0) => SR(0),
      begin_r0 => begin_r0,
      bucket_full_r => bucket_full_r,
      enable_err_detect_i => enable_err_detect_i,
      hard_err_flop_r0 => hard_err_flop_r0,
      hard_err_flop_r_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \soft_err_r_reg[0]_0\(1 downto 0) => \soft_err_r_reg[0]\(1 downto 0),
      user_clk => user_clk,
      user_clk_0 => user_clk_0
    );
rx_lane_init_sm_simplex_i: entity work.aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8
     port map (
      ENABLE_ERR_DETECT_Buffer_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \RX_CHAR_IS_COMMA_R_reg[1]_0\(1 downto 0) => \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0),
      RX_LANE_UP(0) => RX_LANE_UP(0),
      RX_NEG_Buffer => RX_NEG_Buffer,
      SR(0) => SR(0),
      align_r_reg_0 => ena_comma_align_i_2,
      begin_r0 => begin_r0,
      begin_r_reg_0 => begin_r_reg,
      comma_over_two_cycles_r => comma_over_two_cycles_r,
      \counter2_r_reg[15]_0\ => \counter2_r_reg[15]\,
      enable_err_detect_i => enable_err_detect_i,
      gthe2_i => rx_lane_init_sm_simplex_i_n_6,
      left_aligned_r_reg => left_aligned_r_reg_0,
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      reset_count_r_reg_0 => reset_count_r_reg,
      rst_r_reg_0 => gtp_rx_reset_i_2,
      rx_polarity_i_2 => rx_polarity_i_2,
      rx_sp_i => rx_sp_i,
      user_clk => user_clk
    );
sym_dec_i: entity work.aurora_rx_4l_64b_SYM_DEC_9
     port map (
      D(0) => RX_CC_Buffer,
      \GOT_A_Buffer_reg[0]_0\ => \GOT_A_Buffer_reg[0]\,
      \GOT_A_Buffer_reg[1]_0\(0) => \GOT_A_Buffer_reg[1]\(0),
      GOT_V_Buffer_reg_0 => GOT_V_Buffer_reg,
      Q(4 downto 0) => Q(4 downto 0),
      RX_ECP_Buffer0 => RX_ECP_Buffer0,
      RX_NEG_Buffer => RX_NEG_Buffer,
      \RX_PE_DATA_Buffer_reg[10]_0\ => \RX_PE_DATA_Buffer_reg[10]\,
      \RX_PE_DATA_Buffer_reg[8]_0\ => \RX_PE_DATA_Buffer_reg[8]\,
      \RX_PE_DATA_Buffer_reg[9]_0\ => \RX_PE_DATA_Buffer_reg[9]\,
      RX_PE_DATA_V_Buffer_reg_0(0) => RX_PE_DATA_V_Buffer_reg(0),
      RX_SCP_Buffer_reg_0(0) => RX_SCP_Buffer_reg(0),
      RX_SUF_Buffer_reg_0 => RX_SUF_Buffer_reg,
      RX_SUF_Buffer_reg_1 => RX_SUF_Buffer_reg_0,
      SR(0) => SR(0),
      first_v_received_r => first_v_received_r,
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      left_aligned_r_reg_1 => rx_lane_init_sm_simplex_i_n_6,
      load_ufc_control_code_r_reg(2 downto 0) => load_ufc_control_code_r_reg(2 downto 0),
      neqOp => neqOp,
      rx_sp_i => rx_sp_i,
      \stage_1_count_value_r_reg[3]\ => \stage_1_count_value_r_reg[3]\,
      \stage_1_count_value_r_reg[3]_0\ => \stage_1_count_value_r_reg[3]_0\,
      \stage_1_count_value_r_reg[3]_1\ => \stage_1_count_value_r_reg[3]_1\,
      std_bool26_out => std_bool26_out,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[0]_0\ => \word_aligned_control_bits_r_reg[0]\,
      \word_aligned_control_bits_r_reg[1]_0\ => \word_aligned_control_bits_r_reg[1]\,
      \word_aligned_data_r_reg[0]_0\(7 downto 0) => \word_aligned_data_r_reg[0]\(7 downto 0),
      \word_aligned_data_r_reg[0]_1\(7 downto 0) => \word_aligned_data_r_reg[0]_0\(7 downto 0),
      \word_aligned_data_r_reg[8]_0\(7 downto 0) => \word_aligned_data_r_reg[8]\(7 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4 is
  port (
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 0 );
    ena_comma_align_i_3 : out STD_LOGIC;
    comma_over_two_cycles_r : out STD_LOGIC;
    gtp_rx_reset_i_3 : out STD_LOGIC;
    GOT_V_Buffer_reg : out STD_LOGIC;
    bucket_full_r : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[9]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[8]\ : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[10]\ : out STD_LOGIC;
    RX_SCP_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    RX_SUF_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    rx_polarity_i_3 : out STD_LOGIC;
    left_aligned_r_reg : out STD_LOGIC;
    RX_PE_DATA_V_Buffer_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk_0 : out STD_LOGIC;
    RX_SUF_Buffer_reg_0 : out STD_LOGIC;
    \RX_PE_DATA_Buffer_reg[9]_0\ : out STD_LOGIC;
    LINK_RESET_OUT : out STD_LOGIC;
    bad_as_r0 : out STD_LOGIC;
    \GOT_A_Buffer_reg[0]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_PE_DATA_Buffer_reg[9]_1\ : out STD_LOGIC;
    \word_aligned_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \word_aligned_data_r_reg[0]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    first_v_received_r : out STD_LOGIC;
    std_bool26_out : out STD_LOGIC;
    RX_ECP_Buffer0 : out STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_clk : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[1]\ : in STD_LOGIC;
    \word_aligned_control_bits_r_reg[0]\ : in STD_LOGIC;
    hard_err_flop_r0 : in STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    HPCNT_RESET : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]_0\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    RX_PE_DATA : in STD_LOGIC_VECTOR ( 0 to 0 );
    \stage_1_count_value_r_reg[2]_0\ : in STD_LOGIC;
    link_reset_lane0_i : in STD_LOGIC;
    link_reset_lane1_i : in STD_LOGIC;
    link_reset_lane2_i : in STD_LOGIC;
    begin_r_reg : in STD_LOGIC;
    reset_count_r_reg : in STD_LOGIC;
    \counter2_r_reg[15]\ : in STD_LOGIC;
    GOT_A : in STD_LOGIC_VECTOR ( 0 to 1 );
    bad_as_r_reg : in STD_LOGIC;
    bad_as_r_reg_0 : in STD_LOGIC;
    bad_as_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    bad_as_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \RX_CHAR_IS_COMMA_R_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    left_aligned_r_reg_0 : in STD_LOGIC;
    \soft_err_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \word_aligned_data_r_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \word_aligned_data_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4 : entity is "aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5";
end aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4;

architecture STRUCTURE of aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4 is
  signal RX_CC_Buffer : STD_LOGIC;
  signal RX_NEG_Buffer : STD_LOGIC;
  signal begin_r0 : STD_LOGIC;
  signal enable_err_detect_i : STD_LOGIC;
  signal \^left_aligned_r_reg\ : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_6 : STD_LOGIC;
  signal rx_lane_init_sm_simplex_i_n_7 : STD_LOGIC;
  signal rx_sp_i : STD_LOGIC;
begin
  left_aligned_r_reg <= \^left_aligned_r_reg\;
aurora_rx_4l_64b_hotplug_i: entity work.aurora_rx_4l_64b_HOTPLUG
     port map (
      D(0) => RX_CC_Buffer,
      HPCNT_RESET => HPCNT_RESET,
      LINK_RESET_OUT => LINK_RESET_OUT,
      SR(0) => SR(0),
      init_clk_in => init_clk_in,
      link_reset_lane0_i => link_reset_lane0_i,
      link_reset_lane1_i => link_reset_lane1_i,
      link_reset_lane2_i => link_reset_lane2_i,
      user_clk => user_clk
    );
rx_err_detect_simplex_gtp_i: entity work.aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5
     port map (
      D(0) => D(0),
      SR(0) => SR(0),
      begin_r0 => begin_r0,
      bucket_full_r => bucket_full_r,
      enable_err_detect_i => enable_err_detect_i,
      hard_err_flop_r0 => hard_err_flop_r0,
      hard_err_flop_r_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \soft_err_r_reg[0]_0\(1 downto 0) => \soft_err_r_reg[0]\(1 downto 0),
      user_clk => user_clk,
      user_clk_0 => user_clk_0
    );
rx_lane_init_sm_simplex_i: entity work.aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX
     port map (
      ENABLE_ERR_DETECT_Buffer_reg_0 => rx_lane_init_sm_simplex_i_n_7,
      \RX_CHAR_IS_COMMA_R_reg[1]_0\(1 downto 0) => \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0),
      RX_LANE_UP(0) => RX_LANE_UP(0),
      RX_NEG_Buffer => RX_NEG_Buffer,
      SR(0) => SR(0),
      align_r_reg_0 => ena_comma_align_i_3,
      begin_r0 => begin_r0,
      begin_r_reg_0 => begin_r_reg,
      comma_over_two_cycles_r => comma_over_two_cycles_r,
      \counter2_r_reg[15]_0\ => \counter2_r_reg[15]\,
      enable_err_detect_i => enable_err_detect_i,
      gthe2_i => rx_lane_init_sm_simplex_i_n_6,
      left_aligned_r_reg => left_aligned_r_reg_0,
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      reset_count_r_reg_0 => reset_count_r_reg,
      rst_r_reg_0 => gtp_rx_reset_i_3,
      rx_polarity_i_3 => rx_polarity_i_3,
      rx_sp_i => rx_sp_i,
      user_clk => user_clk
    );
sym_dec_i: entity work.aurora_rx_4l_64b_SYM_DEC
     port map (
      D(0) => RX_CC_Buffer,
      GOT_A(0 to 1) => GOT_A(0 to 1),
      \GOT_A_Buffer_reg[0]_0\ => \GOT_A_Buffer_reg[0]\,
      GOT_V_Buffer_reg_0 => GOT_V_Buffer_reg,
      Q(0) => Q(0),
      RX_ECP_Buffer0 => RX_ECP_Buffer0,
      RX_NEG_Buffer => RX_NEG_Buffer,
      RX_PE_DATA(0) => RX_PE_DATA(0),
      \RX_PE_DATA_Buffer_reg[10]_0\ => \RX_PE_DATA_Buffer_reg[10]\,
      \RX_PE_DATA_Buffer_reg[8]_0\ => \RX_PE_DATA_Buffer_reg[8]\,
      \RX_PE_DATA_Buffer_reg[9]_0\ => \RX_PE_DATA_Buffer_reg[9]\,
      \RX_PE_DATA_Buffer_reg[9]_1\ => \RX_PE_DATA_Buffer_reg[9]_0\,
      \RX_PE_DATA_Buffer_reg[9]_2\ => \RX_PE_DATA_Buffer_reg[9]_1\,
      RX_PE_DATA_V_Buffer_reg_0(0) => RX_PE_DATA_V_Buffer_reg(0),
      RX_SCP_Buffer_reg_0(0) => RX_SCP_Buffer_reg(0),
      RX_SUF_Buffer_reg_0 => RX_SUF_Buffer_reg(0),
      RX_SUF_Buffer_reg_1 => RX_SUF_Buffer_reg_0,
      SR(0) => SR(0),
      bad_as_r0 => bad_as_r0,
      bad_as_r_reg => bad_as_r_reg,
      bad_as_r_reg_0 => bad_as_r_reg_0,
      bad_as_r_reg_1(0) => bad_as_r_reg_1(0),
      bad_as_r_reg_2(0) => bad_as_r_reg_2(0),
      first_v_received_r => first_v_received_r,
      left_aligned_r_reg_0 => \^left_aligned_r_reg\,
      left_aligned_r_reg_1 => rx_lane_init_sm_simplex_i_n_6,
      rx_sp_i => rx_sp_i,
      \stage_1_count_value_r_reg[1]\ => \stage_1_count_value_r_reg[1]\,
      \stage_1_count_value_r_reg[1]_0\ => \stage_1_count_value_r_reg[1]_0\,
      \stage_1_count_value_r_reg[2]\ => \stage_1_count_value_r_reg[2]\,
      \stage_1_count_value_r_reg[2]_0\ => \stage_1_count_value_r_reg[2]_0\,
      std_bool26_out => std_bool26_out,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[0]_0\ => \word_aligned_control_bits_r_reg[0]\,
      \word_aligned_control_bits_r_reg[1]_0\ => \word_aligned_control_bits_r_reg[1]\,
      \word_aligned_data_r_reg[0]_0\(7 downto 0) => \word_aligned_data_r_reg[0]\(7 downto 0),
      \word_aligned_data_r_reg[0]_1\(7 downto 0) => \word_aligned_data_r_reg[0]_0\(7 downto 0),
      \word_aligned_data_r_reg[11]_0\(4 downto 0) => \word_aligned_data_r_reg[11]\(4 downto 0),
      \word_aligned_data_r_reg[8]_0\(7 downto 0) => \word_aligned_data_r_reg[8]\(7 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_RX_LL is
  port (
    RX_EOF_N : out STD_LOGIC;
    FRAME_ERR : out STD_LOGIC;
    M_AXI_RX_TLAST : out STD_LOGIC;
    M_AXI_RX_TVALID : out STD_LOGIC;
    M_AXI_UFC_RX_TLAST : out STD_LOGIC;
    UFC_RX_EOF_N : out STD_LOGIC;
    M_AXI_UFC_RX_TVALID : out STD_LOGIC;
    \RX_REM_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \UFC_RX_REM_Buffer_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    RESET : in STD_LOGIC;
    neqOp : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[3]\ : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[1]\ : in STD_LOGIC;
    \stage_1_lane_mask_r_reg[2]\ : in STD_LOGIC;
    std_bool26_out : in STD_LOGIC;
    std_bool26_out_0 : in STD_LOGIC;
    std_bool26_out_1 : in STD_LOGIC;
    std_bool26_out_2 : in STD_LOGIC;
    RX_ECP_Buffer0 : in STD_LOGIC;
    RX_ECP_Buffer0_3 : in STD_LOGIC;
    RX_ECP_Buffer0_4 : in STD_LOGIC;
    RX_ECP_Buffer0_5 : in STD_LOGIC;
    \stage_1_data_r_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[16]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[48]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[32]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \stage_1_data_r_reg[11]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \stage_1_data_r_reg[59]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \stage_1_data_r_reg[43]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    RX_PE_DATA : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \stage_1_data_r_reg[26]\ : in STD_LOGIC;
    \stage_1_data_r_reg[58]\ : in STD_LOGIC;
    \stage_1_data_r_reg[42]\ : in STD_LOGIC;
    \stage_1_data_r_reg[25]\ : in STD_LOGIC;
    \stage_1_data_r_reg[57]\ : in STD_LOGIC;
    \stage_1_data_r_reg[41]\ : in STD_LOGIC;
    \stage_1_data_r_reg[24]\ : in STD_LOGIC;
    \stage_1_data_r_reg[56]\ : in STD_LOGIC;
    \stage_1_data_r_reg[40]\ : in STD_LOGIC;
    start_rx_i : in STD_LOGIC;
    \stage_1_count_value_r_reg[0]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[1]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[2]\ : in STD_LOGIC;
    \stage_1_count_value_r_reg[3]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rx_scp_r_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rx_suf_r_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rx_suf_r_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end aurora_rx_4l_64b_RX_LL;

architecture STRUCTURE of aurora_rx_4l_64b_RX_LL is
  signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_2_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pdu_data_v_i : STD_LOGIC_VECTOR ( 0 to 3 );
  signal pdu_ecp_i : STD_LOGIC_VECTOR ( 0 to 3 );
  signal pdu_pad_i : STD_LOGIC_VECTOR ( 0 to 3 );
  signal pdu_scp_i : STD_LOGIC_VECTOR ( 0 to 3 );
  signal rx_ll_ufc_datapath_i_n_0 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_1 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_10 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_11 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_12 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_13 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_14 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_15 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_2 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_3 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_4 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_48 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_49 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_5 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_50 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_51 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_52 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_53 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_54 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_55 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_56 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_57 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_58 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_59 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_6 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_60 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_61 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_62 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_63 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_7 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_8 : STD_LOGIC;
  signal rx_ll_ufc_datapath_i_n_9 : STD_LOGIC;
  signal \stage_1_rx_ll_deframer_i/S1_in\ : STD_LOGIC;
  signal \stage_1_rx_ll_deframer_i/S3_in\ : STD_LOGIC;
  signal \stage_1_rx_ll_deframer_i/S5_in\ : STD_LOGIC;
  signal ufc_data_v_i : STD_LOGIC_VECTOR ( 0 to 3 );
  signal ufc_filter_i_n_10 : STD_LOGIC;
  signal ufc_filter_i_n_11 : STD_LOGIC;
  signal ufc_filter_i_n_12 : STD_LOGIC;
  signal ufc_filter_i_n_13 : STD_LOGIC;
  signal ufc_filter_i_n_14 : STD_LOGIC;
  signal ufc_filter_i_n_15 : STD_LOGIC;
  signal ufc_filter_i_n_16 : STD_LOGIC;
  signal ufc_filter_i_n_17 : STD_LOGIC;
  signal ufc_filter_i_n_18 : STD_LOGIC;
  signal ufc_filter_i_n_19 : STD_LOGIC;
  signal ufc_filter_i_n_20 : STD_LOGIC;
  signal ufc_filter_i_n_21 : STD_LOGIC;
  signal ufc_filter_i_n_22 : STD_LOGIC;
  signal ufc_filter_i_n_23 : STD_LOGIC;
  signal ufc_filter_i_n_24 : STD_LOGIC;
  signal ufc_filter_i_n_25 : STD_LOGIC;
  signal ufc_filter_i_n_26 : STD_LOGIC;
  signal ufc_filter_i_n_27 : STD_LOGIC;
  signal ufc_filter_i_n_28 : STD_LOGIC;
  signal ufc_filter_i_n_29 : STD_LOGIC;
  signal ufc_filter_i_n_30 : STD_LOGIC;
  signal ufc_filter_i_n_31 : STD_LOGIC;
  signal ufc_filter_i_n_32 : STD_LOGIC;
  signal ufc_filter_i_n_33 : STD_LOGIC;
  signal ufc_filter_i_n_34 : STD_LOGIC;
  signal ufc_filter_i_n_35 : STD_LOGIC;
  signal ufc_filter_i_n_36 : STD_LOGIC;
  signal ufc_filter_i_n_37 : STD_LOGIC;
  signal ufc_filter_i_n_38 : STD_LOGIC;
  signal ufc_filter_i_n_39 : STD_LOGIC;
  signal ufc_filter_i_n_40 : STD_LOGIC;
  signal ufc_filter_i_n_41 : STD_LOGIC;
  signal ufc_filter_i_n_42 : STD_LOGIC;
  signal ufc_filter_i_n_43 : STD_LOGIC;
  signal ufc_filter_i_n_44 : STD_LOGIC;
  signal ufc_filter_i_n_45 : STD_LOGIC;
  signal ufc_filter_i_n_46 : STD_LOGIC;
  signal ufc_filter_i_n_47 : STD_LOGIC;
  signal ufc_filter_i_n_48 : STD_LOGIC;
  signal ufc_filter_i_n_49 : STD_LOGIC;
  signal ufc_filter_i_n_50 : STD_LOGIC;
  signal ufc_filter_i_n_51 : STD_LOGIC;
  signal ufc_filter_i_n_52 : STD_LOGIC;
  signal ufc_filter_i_n_53 : STD_LOGIC;
  signal ufc_filter_i_n_54 : STD_LOGIC;
  signal ufc_filter_i_n_55 : STD_LOGIC;
  signal ufc_filter_i_n_56 : STD_LOGIC;
  signal ufc_filter_i_n_57 : STD_LOGIC;
  signal ufc_filter_i_n_58 : STD_LOGIC;
  signal ufc_filter_i_n_59 : STD_LOGIC;
  signal ufc_filter_i_n_60 : STD_LOGIC;
  signal ufc_filter_i_n_61 : STD_LOGIC;
  signal ufc_filter_i_n_62 : STD_LOGIC;
  signal ufc_filter_i_n_63 : STD_LOGIC;
  signal ufc_filter_i_n_64 : STD_LOGIC;
  signal ufc_filter_i_n_65 : STD_LOGIC;
  signal ufc_filter_i_n_66 : STD_LOGIC;
  signal ufc_filter_i_n_67 : STD_LOGIC;
  signal ufc_filter_i_n_68 : STD_LOGIC;
  signal ufc_filter_i_n_69 : STD_LOGIC;
  signal ufc_filter_i_n_70 : STD_LOGIC;
  signal ufc_filter_i_n_71 : STD_LOGIC;
  signal ufc_filter_i_n_72 : STD_LOGIC;
  signal ufc_filter_i_n_73 : STD_LOGIC;
  signal ufc_filter_i_n_78 : STD_LOGIC;
  signal ufc_filter_i_n_79 : STD_LOGIC;
  signal ufc_filter_i_n_80 : STD_LOGIC;
  signal ufc_filter_i_n_81 : STD_LOGIC;
  signal ufc_filter_i_n_82 : STD_LOGIC;
  signal ufc_filter_i_n_9 : STD_LOGIC;
  signal ufc_filter_i_n_91 : STD_LOGIC;
  signal ufc_start_i : STD_LOGIC;
begin
rx_ll_pdu_datapath_i: entity work.aurora_rx_4l_64b_RX_LL_PDU_DATAPATH
     port map (
      D(3) => pdu_ecp_i(0),
      D(2) => pdu_ecp_i(1),
      D(1) => pdu_ecp_i(2),
      D(0) => pdu_ecp_i(3),
      \DEFRAMED_DATA_V_Buffer_reg[0]\(3) => pdu_data_v_i(0),
      \DEFRAMED_DATA_V_Buffer_reg[0]\(2) => pdu_data_v_i(1),
      \DEFRAMED_DATA_V_Buffer_reg[0]\(1) => pdu_data_v_i(2),
      \DEFRAMED_DATA_V_Buffer_reg[0]\(0) => pdu_data_v_i(3),
      FRAME_ERR => FRAME_ERR,
      M_AXI_RX_TDATA(63 downto 0) => M_AXI_RX_TDATA(63 downto 0),
      M_AXI_RX_TLAST => M_AXI_RX_TLAST,
      M_AXI_RX_TVALID => M_AXI_RX_TVALID,
      Q(3) => pdu_scp_i(0),
      Q(2) => pdu_scp_i(1),
      Q(1) => pdu_scp_i(2),
      Q(0) => pdu_scp_i(3),
      RESET => RESET,
      RX_EOF_N => RX_EOF_N,
      \RX_REM_Buffer_reg[0]_0\(2 downto 0) => \RX_REM_Buffer_reg[0]\(2 downto 0),
      S1_in => \stage_1_rx_ll_deframer_i/S1_in\,
      S3_in => \stage_1_rx_ll_deframer_i/S3_in\,
      S5_in => \stage_1_rx_ll_deframer_i/S5_in\,
      data_after_start_muxcy_3 => ufc_filter_i_n_91,
      in_frame_muxcy_0 => ufc_filter_i_n_80,
      in_frame_muxcy_1 => ufc_filter_i_n_79,
      in_frame_muxcy_2 => ufc_filter_i_n_78,
      in_frame_muxcy_3 => ufc_filter_i_n_73,
      pdu_pad_i(0 to 3) => pdu_pad_i(0 to 3),
      \stage_2_data_r_reg[0]_0\(63) => rx_ll_ufc_datapath_i_n_0,
      \stage_2_data_r_reg[0]_0\(62) => rx_ll_ufc_datapath_i_n_1,
      \stage_2_data_r_reg[0]_0\(61) => rx_ll_ufc_datapath_i_n_2,
      \stage_2_data_r_reg[0]_0\(60) => rx_ll_ufc_datapath_i_n_3,
      \stage_2_data_r_reg[0]_0\(59) => rx_ll_ufc_datapath_i_n_4,
      \stage_2_data_r_reg[0]_0\(58) => rx_ll_ufc_datapath_i_n_5,
      \stage_2_data_r_reg[0]_0\(57) => rx_ll_ufc_datapath_i_n_6,
      \stage_2_data_r_reg[0]_0\(56) => rx_ll_ufc_datapath_i_n_7,
      \stage_2_data_r_reg[0]_0\(55) => rx_ll_ufc_datapath_i_n_8,
      \stage_2_data_r_reg[0]_0\(54) => rx_ll_ufc_datapath_i_n_9,
      \stage_2_data_r_reg[0]_0\(53) => rx_ll_ufc_datapath_i_n_10,
      \stage_2_data_r_reg[0]_0\(52) => rx_ll_ufc_datapath_i_n_11,
      \stage_2_data_r_reg[0]_0\(51) => rx_ll_ufc_datapath_i_n_12,
      \stage_2_data_r_reg[0]_0\(50) => rx_ll_ufc_datapath_i_n_13,
      \stage_2_data_r_reg[0]_0\(49) => rx_ll_ufc_datapath_i_n_14,
      \stage_2_data_r_reg[0]_0\(48) => rx_ll_ufc_datapath_i_n_15,
      \stage_2_data_r_reg[0]_0\(47 downto 32) => p_2_in(15 downto 0),
      \stage_2_data_r_reg[0]_0\(31 downto 16) => p_1_in(15 downto 0),
      \stage_2_data_r_reg[0]_0\(15) => rx_ll_ufc_datapath_i_n_48,
      \stage_2_data_r_reg[0]_0\(14) => rx_ll_ufc_datapath_i_n_49,
      \stage_2_data_r_reg[0]_0\(13) => rx_ll_ufc_datapath_i_n_50,
      \stage_2_data_r_reg[0]_0\(12) => rx_ll_ufc_datapath_i_n_51,
      \stage_2_data_r_reg[0]_0\(11) => rx_ll_ufc_datapath_i_n_52,
      \stage_2_data_r_reg[0]_0\(10) => rx_ll_ufc_datapath_i_n_53,
      \stage_2_data_r_reg[0]_0\(9) => rx_ll_ufc_datapath_i_n_54,
      \stage_2_data_r_reg[0]_0\(8) => rx_ll_ufc_datapath_i_n_55,
      \stage_2_data_r_reg[0]_0\(7) => rx_ll_ufc_datapath_i_n_56,
      \stage_2_data_r_reg[0]_0\(6) => rx_ll_ufc_datapath_i_n_57,
      \stage_2_data_r_reg[0]_0\(5) => rx_ll_ufc_datapath_i_n_58,
      \stage_2_data_r_reg[0]_0\(4) => rx_ll_ufc_datapath_i_n_59,
      \stage_2_data_r_reg[0]_0\(3) => rx_ll_ufc_datapath_i_n_60,
      \stage_2_data_r_reg[0]_0\(2) => rx_ll_ufc_datapath_i_n_61,
      \stage_2_data_r_reg[0]_0\(1) => rx_ll_ufc_datapath_i_n_62,
      \stage_2_data_r_reg[0]_0\(0) => rx_ll_ufc_datapath_i_n_63,
      start_rx_i => start_rx_i,
      user_clk => user_clk
    );
rx_ll_ufc_datapath_i: entity work.aurora_rx_4l_64b_RX_LL_UFC_DATAPATH
     port map (
      \BARREL_SHIFTER_CONTROL_Buffer_reg[1]\ => ufc_filter_i_n_81,
      \BARREL_SHIFTER_CONTROL_Buffer_reg[2]\ => ufc_filter_i_n_82,
      M_AXI_UFC_RX_TDATA(63 downto 0) => M_AXI_UFC_RX_TDATA(63 downto 0),
      M_AXI_UFC_RX_TLAST => M_AXI_UFC_RX_TLAST,
      M_AXI_UFC_RX_TVALID => M_AXI_UFC_RX_TVALID,
      Q(3) => ufc_data_v_i(0),
      Q(2) => ufc_data_v_i(1),
      Q(1) => ufc_data_v_i(2),
      Q(0) => ufc_data_v_i(3),
      RESET => RESET,
      UFC_RX_EOF_N => UFC_RX_EOF_N,
      \UFC_RX_REM_Buffer_reg[0]_0\(1 downto 0) => \UFC_RX_REM_Buffer_reg[0]\(1 downto 0),
      \stage_1_data_r_reg[0]_0\(63) => rx_ll_ufc_datapath_i_n_0,
      \stage_1_data_r_reg[0]_0\(62) => rx_ll_ufc_datapath_i_n_1,
      \stage_1_data_r_reg[0]_0\(61) => rx_ll_ufc_datapath_i_n_2,
      \stage_1_data_r_reg[0]_0\(60) => rx_ll_ufc_datapath_i_n_3,
      \stage_1_data_r_reg[0]_0\(59) => rx_ll_ufc_datapath_i_n_4,
      \stage_1_data_r_reg[0]_0\(58) => rx_ll_ufc_datapath_i_n_5,
      \stage_1_data_r_reg[0]_0\(57) => rx_ll_ufc_datapath_i_n_6,
      \stage_1_data_r_reg[0]_0\(56) => rx_ll_ufc_datapath_i_n_7,
      \stage_1_data_r_reg[0]_0\(55) => rx_ll_ufc_datapath_i_n_8,
      \stage_1_data_r_reg[0]_0\(54) => rx_ll_ufc_datapath_i_n_9,
      \stage_1_data_r_reg[0]_0\(53) => rx_ll_ufc_datapath_i_n_10,
      \stage_1_data_r_reg[0]_0\(52) => rx_ll_ufc_datapath_i_n_11,
      \stage_1_data_r_reg[0]_0\(51) => rx_ll_ufc_datapath_i_n_12,
      \stage_1_data_r_reg[0]_0\(50) => rx_ll_ufc_datapath_i_n_13,
      \stage_1_data_r_reg[0]_0\(49) => rx_ll_ufc_datapath_i_n_14,
      \stage_1_data_r_reg[0]_0\(48) => rx_ll_ufc_datapath_i_n_15,
      \stage_1_data_r_reg[0]_0\(47 downto 32) => p_2_in(15 downto 0),
      \stage_1_data_r_reg[0]_0\(31 downto 16) => p_1_in(15 downto 0),
      \stage_1_data_r_reg[0]_0\(15) => rx_ll_ufc_datapath_i_n_48,
      \stage_1_data_r_reg[0]_0\(14) => rx_ll_ufc_datapath_i_n_49,
      \stage_1_data_r_reg[0]_0\(13) => rx_ll_ufc_datapath_i_n_50,
      \stage_1_data_r_reg[0]_0\(12) => rx_ll_ufc_datapath_i_n_51,
      \stage_1_data_r_reg[0]_0\(11) => rx_ll_ufc_datapath_i_n_52,
      \stage_1_data_r_reg[0]_0\(10) => rx_ll_ufc_datapath_i_n_53,
      \stage_1_data_r_reg[0]_0\(9) => rx_ll_ufc_datapath_i_n_54,
      \stage_1_data_r_reg[0]_0\(8) => rx_ll_ufc_datapath_i_n_55,
      \stage_1_data_r_reg[0]_0\(7) => rx_ll_ufc_datapath_i_n_56,
      \stage_1_data_r_reg[0]_0\(6) => rx_ll_ufc_datapath_i_n_57,
      \stage_1_data_r_reg[0]_0\(5) => rx_ll_ufc_datapath_i_n_58,
      \stage_1_data_r_reg[0]_0\(4) => rx_ll_ufc_datapath_i_n_59,
      \stage_1_data_r_reg[0]_0\(3) => rx_ll_ufc_datapath_i_n_60,
      \stage_1_data_r_reg[0]_0\(2) => rx_ll_ufc_datapath_i_n_61,
      \stage_1_data_r_reg[0]_0\(1) => rx_ll_ufc_datapath_i_n_62,
      \stage_1_data_r_reg[0]_0\(0) => rx_ll_ufc_datapath_i_n_63,
      \stage_1_data_r_reg[0]_1\ => ufc_filter_i_n_37,
      \stage_1_data_r_reg[10]_0\ => ufc_filter_i_n_61,
      \stage_1_data_r_reg[11]_0\ => ufc_filter_i_n_57,
      \stage_1_data_r_reg[12]_0\ => ufc_filter_i_n_53,
      \stage_1_data_r_reg[13]_0\ => ufc_filter_i_n_49,
      \stage_1_data_r_reg[14]_0\ => ufc_filter_i_n_45,
      \stage_1_data_r_reg[15]_0\ => ufc_filter_i_n_41,
      \stage_1_data_r_reg[16]_0\ => ufc_filter_i_n_38,
      \stage_1_data_r_reg[17]_0\ => ufc_filter_i_n_34,
      \stage_1_data_r_reg[18]_0\ => ufc_filter_i_n_30,
      \stage_1_data_r_reg[19]_0\ => ufc_filter_i_n_26,
      \stage_1_data_r_reg[1]_0\ => ufc_filter_i_n_33,
      \stage_1_data_r_reg[20]_0\ => ufc_filter_i_n_22,
      \stage_1_data_r_reg[21]_0\ => ufc_filter_i_n_18,
      \stage_1_data_r_reg[22]_0\ => ufc_filter_i_n_14,
      \stage_1_data_r_reg[23]_0\ => ufc_filter_i_n_10,
      \stage_1_data_r_reg[24]_0\ => ufc_filter_i_n_70,
      \stage_1_data_r_reg[25]_0\ => ufc_filter_i_n_66,
      \stage_1_data_r_reg[26]_0\ => ufc_filter_i_n_62,
      \stage_1_data_r_reg[27]_0\ => ufc_filter_i_n_58,
      \stage_1_data_r_reg[28]_0\ => ufc_filter_i_n_54,
      \stage_1_data_r_reg[29]_0\ => ufc_filter_i_n_50,
      \stage_1_data_r_reg[2]_0\ => ufc_filter_i_n_29,
      \stage_1_data_r_reg[30]_0\ => ufc_filter_i_n_46,
      \stage_1_data_r_reg[31]_0\ => ufc_filter_i_n_42,
      \stage_1_data_r_reg[32]_0\ => ufc_filter_i_n_40,
      \stage_1_data_r_reg[33]_0\ => ufc_filter_i_n_36,
      \stage_1_data_r_reg[34]_0\ => ufc_filter_i_n_32,
      \stage_1_data_r_reg[35]_0\ => ufc_filter_i_n_28,
      \stage_1_data_r_reg[36]_0\ => ufc_filter_i_n_24,
      \stage_1_data_r_reg[37]_0\ => ufc_filter_i_n_20,
      \stage_1_data_r_reg[38]_0\ => ufc_filter_i_n_16,
      \stage_1_data_r_reg[39]_0\ => ufc_filter_i_n_12,
      \stage_1_data_r_reg[3]_0\ => ufc_filter_i_n_25,
      \stage_1_data_r_reg[40]_0\ => ufc_filter_i_n_72,
      \stage_1_data_r_reg[41]_0\ => ufc_filter_i_n_68,
      \stage_1_data_r_reg[42]_0\ => ufc_filter_i_n_64,
      \stage_1_data_r_reg[43]_0\ => ufc_filter_i_n_60,
      \stage_1_data_r_reg[44]_0\ => ufc_filter_i_n_56,
      \stage_1_data_r_reg[45]_0\ => ufc_filter_i_n_52,
      \stage_1_data_r_reg[46]_0\ => ufc_filter_i_n_48,
      \stage_1_data_r_reg[47]_0\ => ufc_filter_i_n_44,
      \stage_1_data_r_reg[48]_0\ => ufc_filter_i_n_39,
      \stage_1_data_r_reg[49]_0\ => ufc_filter_i_n_35,
      \stage_1_data_r_reg[4]_0\ => ufc_filter_i_n_21,
      \stage_1_data_r_reg[50]_0\ => ufc_filter_i_n_31,
      \stage_1_data_r_reg[51]_0\ => ufc_filter_i_n_27,
      \stage_1_data_r_reg[52]_0\ => ufc_filter_i_n_23,
      \stage_1_data_r_reg[53]_0\ => ufc_filter_i_n_19,
      \stage_1_data_r_reg[54]_0\ => ufc_filter_i_n_15,
      \stage_1_data_r_reg[55]_0\ => ufc_filter_i_n_11,
      \stage_1_data_r_reg[56]_0\ => ufc_filter_i_n_71,
      \stage_1_data_r_reg[57]_0\ => ufc_filter_i_n_67,
      \stage_1_data_r_reg[58]_0\ => ufc_filter_i_n_63,
      \stage_1_data_r_reg[59]_0\ => ufc_filter_i_n_59,
      \stage_1_data_r_reg[5]_0\ => ufc_filter_i_n_17,
      \stage_1_data_r_reg[60]_0\ => ufc_filter_i_n_55,
      \stage_1_data_r_reg[61]_0\ => ufc_filter_i_n_51,
      \stage_1_data_r_reg[62]_0\ => ufc_filter_i_n_47,
      \stage_1_data_r_reg[63]_0\ => ufc_filter_i_n_43,
      \stage_1_data_r_reg[6]_0\ => ufc_filter_i_n_13,
      \stage_1_data_r_reg[7]_0\ => ufc_filter_i_n_9,
      \stage_1_data_r_reg[8]_0\ => ufc_filter_i_n_69,
      \stage_1_data_r_reg[9]_0\ => ufc_filter_i_n_65,
      ufc_start_i => ufc_start_i,
      user_clk => user_clk
    );
ufc_filter_i: entity work.aurora_rx_4l_64b_UFC_FILTER
     port map (
      D(3) => pdu_ecp_i(0),
      D(2) => pdu_ecp_i(1),
      D(1) => pdu_ecp_i(2),
      D(0) => pdu_ecp_i(3),
      \PDU_DATA_V_Buffer_reg[0]_0\(3) => pdu_data_v_i(0),
      \PDU_DATA_V_Buffer_reg[0]_0\(2) => pdu_data_v_i(1),
      \PDU_DATA_V_Buffer_reg[0]_0\(1) => pdu_data_v_i(2),
      \PDU_DATA_V_Buffer_reg[0]_0\(0) => pdu_data_v_i(3),
      \PDU_ECP_Buffer_reg[0]_0\ => ufc_filter_i_n_80,
      \PDU_ECP_Buffer_reg[1]_0\ => ufc_filter_i_n_79,
      \PDU_ECP_Buffer_reg[2]_0\ => ufc_filter_i_n_78,
      \PDU_ECP_Buffer_reg[3]_0\ => ufc_filter_i_n_73,
      \PDU_SCP_Buffer_reg[0]_0\(3) => pdu_scp_i(0),
      \PDU_SCP_Buffer_reg[0]_0\(2) => pdu_scp_i(1),
      \PDU_SCP_Buffer_reg[0]_0\(1) => pdu_scp_i(2),
      \PDU_SCP_Buffer_reg[0]_0\(0) => pdu_scp_i(3),
      \PDU_SCP_Buffer_reg[3]_0\ => ufc_filter_i_n_91,
      Q(4 downto 0) => Q(4 downto 0),
      RESET => RESET,
      RX_ECP_Buffer0 => RX_ECP_Buffer0,
      RX_ECP_Buffer0_3 => RX_ECP_Buffer0_3,
      RX_ECP_Buffer0_4 => RX_ECP_Buffer0_4,
      RX_ECP_Buffer0_5 => RX_ECP_Buffer0_5,
      RX_PE_DATA(2 downto 0) => RX_PE_DATA(2 downto 0),
      \RX_PE_DATA_Buffer_reg[10]\ => ufc_filter_i_n_61,
      \RX_PE_DATA_Buffer_reg[10]_0\ => ufc_filter_i_n_62,
      \RX_PE_DATA_Buffer_reg[10]_1\ => ufc_filter_i_n_63,
      \RX_PE_DATA_Buffer_reg[10]_2\ => ufc_filter_i_n_64,
      \RX_PE_DATA_Buffer_reg[8]\ => ufc_filter_i_n_69,
      \RX_PE_DATA_Buffer_reg[8]_0\ => ufc_filter_i_n_70,
      \RX_PE_DATA_Buffer_reg[8]_1\ => ufc_filter_i_n_71,
      \RX_PE_DATA_Buffer_reg[8]_2\ => ufc_filter_i_n_72,
      \RX_PE_DATA_Buffer_reg[9]\ => ufc_filter_i_n_65,
      \RX_PE_DATA_Buffer_reg[9]_0\ => ufc_filter_i_n_66,
      \RX_PE_DATA_Buffer_reg[9]_1\ => ufc_filter_i_n_67,
      \RX_PE_DATA_Buffer_reg[9]_2\ => ufc_filter_i_n_68,
      S1_in => \stage_1_rx_ll_deframer_i/S1_in\,
      S3_in => \stage_1_rx_ll_deframer_i/S3_in\,
      S5_in => \stage_1_rx_ll_deframer_i/S5_in\,
      \UFC_DATA_V_Buffer_reg[0]_0\(3) => ufc_data_v_i(0),
      \UFC_DATA_V_Buffer_reg[0]_0\(2) => ufc_data_v_i(1),
      \UFC_DATA_V_Buffer_reg[0]_0\(1) => ufc_data_v_i(2),
      \UFC_DATA_V_Buffer_reg[0]_0\(0) => ufc_data_v_i(3),
      \UFC_MESSAGE_START_Buffer_reg[1]_0\ => ufc_filter_i_n_81,
      \UFC_MESSAGE_START_Buffer_reg[1]_1\ => ufc_filter_i_n_82,
      neqOp => neqOp,
      pdu_pad_i(0 to 3) => pdu_pad_i(0 to 3),
      \rx_data_v_r_reg[0]_0\(3 downto 0) => D(3 downto 0),
      \rx_scp_r_reg[0]_0\(3 downto 0) => \rx_scp_r_reg[0]\(3 downto 0),
      \rx_suf_r_reg[0]_0\(3 downto 2) => \rx_suf_r_reg[0]\(2 downto 1),
      \rx_suf_r_reg[0]_0\(1) => \rx_suf_r_reg[2]\(0),
      \rx_suf_r_reg[0]_0\(0) => \rx_suf_r_reg[0]\(0),
      \stage_1_count_value_r_reg[0]_0\ => \stage_1_count_value_r_reg[0]\,
      \stage_1_count_value_r_reg[1]_0\ => \stage_1_count_value_r_reg[1]\,
      \stage_1_count_value_r_reg[2]_0\ => \stage_1_count_value_r_reg[2]\,
      \stage_1_count_value_r_reg[3]_0\ => \stage_1_count_value_r_reg[3]\,
      \stage_1_data_r_reg[0]\(7 downto 0) => \stage_1_data_r_reg[0]\(7 downto 0),
      \stage_1_data_r_reg[11]\(4 downto 0) => \stage_1_data_r_reg[11]\(4 downto 0),
      \stage_1_data_r_reg[16]\(7 downto 0) => \stage_1_data_r_reg[16]\(7 downto 0),
      \stage_1_data_r_reg[24]\ => \stage_1_data_r_reg[24]\,
      \stage_1_data_r_reg[25]\ => \stage_1_data_r_reg[25]\,
      \stage_1_data_r_reg[26]\ => \stage_1_data_r_reg[26]\,
      \stage_1_data_r_reg[32]\(7 downto 0) => \stage_1_data_r_reg[32]\(7 downto 0),
      \stage_1_data_r_reg[40]\ => \stage_1_data_r_reg[40]\,
      \stage_1_data_r_reg[41]\ => \stage_1_data_r_reg[41]\,
      \stage_1_data_r_reg[42]\ => \stage_1_data_r_reg[42]\,
      \stage_1_data_r_reg[43]\(4 downto 0) => \stage_1_data_r_reg[43]\(4 downto 0),
      \stage_1_data_r_reg[48]\(7 downto 0) => \stage_1_data_r_reg[48]\(7 downto 0),
      \stage_1_data_r_reg[56]\ => \stage_1_data_r_reg[56]\,
      \stage_1_data_r_reg[57]\ => \stage_1_data_r_reg[57]\,
      \stage_1_data_r_reg[58]\ => \stage_1_data_r_reg[58]\,
      \stage_1_data_r_reg[59]\(4 downto 0) => \stage_1_data_r_reg[59]\(4 downto 0),
      \stage_1_lane_mask_r_reg[1]_0\ => \stage_1_lane_mask_r_reg[1]\,
      \stage_1_lane_mask_r_reg[2]_0\ => \stage_1_lane_mask_r_reg[2]\,
      \stage_1_lane_mask_r_reg[3]_0\ => \stage_1_lane_mask_r_reg[3]\,
      std_bool26_out => std_bool26_out,
      std_bool26_out_0 => std_bool26_out_0,
      std_bool26_out_1 => std_bool26_out_1,
      std_bool26_out_2 => std_bool26_out_2,
      ufc_start_i => ufc_start_i,
      user_clk => user_clk,
      \word_aligned_data_r_reg[0]\ => ufc_filter_i_n_37,
      \word_aligned_data_r_reg[0]_0\ => ufc_filter_i_n_38,
      \word_aligned_data_r_reg[0]_1\ => ufc_filter_i_n_39,
      \word_aligned_data_r_reg[0]_2\ => ufc_filter_i_n_40,
      \word_aligned_data_r_reg[11]\ => ufc_filter_i_n_57,
      \word_aligned_data_r_reg[11]_0\ => ufc_filter_i_n_58,
      \word_aligned_data_r_reg[11]_1\ => ufc_filter_i_n_59,
      \word_aligned_data_r_reg[11]_2\ => ufc_filter_i_n_60,
      \word_aligned_data_r_reg[12]\ => ufc_filter_i_n_53,
      \word_aligned_data_r_reg[12]_0\ => ufc_filter_i_n_54,
      \word_aligned_data_r_reg[12]_1\ => ufc_filter_i_n_55,
      \word_aligned_data_r_reg[12]_2\ => ufc_filter_i_n_56,
      \word_aligned_data_r_reg[13]\ => ufc_filter_i_n_49,
      \word_aligned_data_r_reg[13]_0\ => ufc_filter_i_n_50,
      \word_aligned_data_r_reg[13]_1\ => ufc_filter_i_n_51,
      \word_aligned_data_r_reg[13]_2\ => ufc_filter_i_n_52,
      \word_aligned_data_r_reg[14]\ => ufc_filter_i_n_45,
      \word_aligned_data_r_reg[14]_0\ => ufc_filter_i_n_46,
      \word_aligned_data_r_reg[14]_1\ => ufc_filter_i_n_47,
      \word_aligned_data_r_reg[14]_2\ => ufc_filter_i_n_48,
      \word_aligned_data_r_reg[15]\ => ufc_filter_i_n_41,
      \word_aligned_data_r_reg[15]_0\ => ufc_filter_i_n_42,
      \word_aligned_data_r_reg[15]_1\ => ufc_filter_i_n_43,
      \word_aligned_data_r_reg[15]_2\ => ufc_filter_i_n_44,
      \word_aligned_data_r_reg[1]\ => ufc_filter_i_n_33,
      \word_aligned_data_r_reg[1]_0\ => ufc_filter_i_n_34,
      \word_aligned_data_r_reg[1]_1\ => ufc_filter_i_n_35,
      \word_aligned_data_r_reg[1]_2\ => ufc_filter_i_n_36,
      \word_aligned_data_r_reg[2]\ => ufc_filter_i_n_29,
      \word_aligned_data_r_reg[2]_0\ => ufc_filter_i_n_30,
      \word_aligned_data_r_reg[2]_1\ => ufc_filter_i_n_31,
      \word_aligned_data_r_reg[2]_2\ => ufc_filter_i_n_32,
      \word_aligned_data_r_reg[3]\ => ufc_filter_i_n_25,
      \word_aligned_data_r_reg[3]_0\ => ufc_filter_i_n_26,
      \word_aligned_data_r_reg[3]_1\ => ufc_filter_i_n_27,
      \word_aligned_data_r_reg[3]_2\ => ufc_filter_i_n_28,
      \word_aligned_data_r_reg[4]\ => ufc_filter_i_n_21,
      \word_aligned_data_r_reg[4]_0\ => ufc_filter_i_n_22,
      \word_aligned_data_r_reg[4]_1\ => ufc_filter_i_n_23,
      \word_aligned_data_r_reg[4]_2\ => ufc_filter_i_n_24,
      \word_aligned_data_r_reg[5]\ => ufc_filter_i_n_17,
      \word_aligned_data_r_reg[5]_0\ => ufc_filter_i_n_18,
      \word_aligned_data_r_reg[5]_1\ => ufc_filter_i_n_19,
      \word_aligned_data_r_reg[5]_2\ => ufc_filter_i_n_20,
      \word_aligned_data_r_reg[6]\ => ufc_filter_i_n_13,
      \word_aligned_data_r_reg[6]_0\ => ufc_filter_i_n_14,
      \word_aligned_data_r_reg[6]_1\ => ufc_filter_i_n_15,
      \word_aligned_data_r_reg[6]_2\ => ufc_filter_i_n_16,
      \word_aligned_data_r_reg[7]\ => ufc_filter_i_n_9,
      \word_aligned_data_r_reg[7]_0\ => ufc_filter_i_n_10,
      \word_aligned_data_r_reg[7]_1\ => ufc_filter_i_n_11,
      \word_aligned_data_r_reg[7]_2\ => ufc_filter_i_n_12
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b_core is
  port (
    M_AXI_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M_AXI_RX_TKEEP : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_RX_TVALID : out STD_LOGIC;
    M_AXI_RX_TLAST : out STD_LOGIC;
    M_AXI_UFC_RX_TDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M_AXI_UFC_RX_TKEEP : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_UFC_RX_TVALID : out STD_LOGIC;
    M_AXI_UFC_RX_TLAST : out STD_LOGIC;
    RXP : in STD_LOGIC_VECTOR ( 0 to 3 );
    RXN : in STD_LOGIC_VECTOR ( 0 to 3 );
    gt_refclk1 : in STD_LOGIC;
    RX_HARD_ERR : out STD_LOGIC;
    SOFT_ERR : out STD_LOGIC;
    FRAME_ERR : out STD_LOGIC;
    RX_CHANNEL_UP : out STD_LOGIC;
    RX_LANE_UP : out STD_LOGIC_VECTOR ( 0 to 3 );
    user_clk : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    RX_SYSTEM_RESET : in STD_LOGIC;
    RX_RESETDONE_OUT : out STD_LOGIC;
    LINK_RESET_OUT : out STD_LOGIC;
    POWER_DOWN : in STD_LOGIC;
    GT_RESET : in STD_LOGIC;
    TX_LOCK : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    PLL_NOT_LOCKED : in STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    DRPADDR_IN : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN : in STD_LOGIC;
    DRPRDY_OUT : out STD_LOGIC;
    DRPWE_IN : in STD_LOGIC;
    DRPADDR_IN_LANE1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN_LANE1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT_LANE1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN_LANE1 : in STD_LOGIC;
    DRPRDY_OUT_LANE1 : out STD_LOGIC;
    DRPWE_IN_LANE1 : in STD_LOGIC;
    DRPADDR_IN_LANE2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN_LANE2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT_LANE2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN_LANE2 : in STD_LOGIC;
    DRPRDY_OUT_LANE2 : out STD_LOGIC;
    DRPWE_IN_LANE2 : in STD_LOGIC;
    DRPADDR_IN_LANE3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI_IN_LANE3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPDO_OUT_LANE3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRPEN_IN_LANE3 : in STD_LOGIC;
    DRPRDY_OUT_LANE3 : out STD_LOGIC;
    DRPWE_IN_LANE3 : in STD_LOGIC;
    TX_OUT_CLK : out STD_LOGIC;
    gt0_qplllock_in : in STD_LOGIC;
    gt0_qpllrefclklost_in : in STD_LOGIC;
    gt0_qpllreset_out : out STD_LOGIC;
    gt1_qplllock_in : in STD_LOGIC;
    gt1_qpllrefclklost_in : in STD_LOGIC;
    gt1_qpllreset_out : out STD_LOGIC;
    gt_qpllclk_quad2_in : in STD_LOGIC;
    gt_qpllrefclk_quad2_in : in STD_LOGIC;
    gt_qpllclk_quad3_in : in STD_LOGIC;
    gt_qpllrefclk_quad3_in : in STD_LOGIC;
    gt0_cplllock_out : out STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_realign_out : out STD_LOGIC;
    gt0_rx_buf_err_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_cplllock_out : out STD_LOGIC;
    gt1_rxlpmen_in : in STD_LOGIC;
    gt1_rxcdrovrden_in : in STD_LOGIC;
    gt1_rxdfelpmreset_in : in STD_LOGIC;
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxcdrhold_in : in STD_LOGIC;
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxprbserr_out : out STD_LOGIC;
    gt1_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_rxprbscntreset_in : in STD_LOGIC;
    gt1_rxpcsreset_in : in STD_LOGIC;
    gt1_rxpmareset_in : in STD_LOGIC;
    gt1_rxpmaresetdone_out : out STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt1_rxbufreset_in : in STD_LOGIC;
    gt1_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_realign_out : out STD_LOGIC;
    gt1_rx_buf_err_out : out STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_cplllock_out : out STD_LOGIC;
    gt2_rxlpmen_in : in STD_LOGIC;
    gt2_rxcdrovrden_in : in STD_LOGIC;
    gt2_rxdfelpmreset_in : in STD_LOGIC;
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxcdrhold_in : in STD_LOGIC;
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxprbserr_out : out STD_LOGIC;
    gt2_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_rxprbscntreset_in : in STD_LOGIC;
    gt2_rxpcsreset_in : in STD_LOGIC;
    gt2_rxpmareset_in : in STD_LOGIC;
    gt2_rxpmaresetdone_out : out STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt2_rxbufreset_in : in STD_LOGIC;
    gt2_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_realign_out : out STD_LOGIC;
    gt2_rx_buf_err_out : out STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    gt2_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_cplllock_out : out STD_LOGIC;
    gt3_rxlpmen_in : in STD_LOGIC;
    gt3_rxcdrovrden_in : in STD_LOGIC;
    gt3_rxdfelpmreset_in : in STD_LOGIC;
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxcdrhold_in : in STD_LOGIC;
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxprbserr_out : out STD_LOGIC;
    gt3_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_rxprbscntreset_in : in STD_LOGIC;
    gt3_rxpcsreset_in : in STD_LOGIC;
    gt3_rxpmareset_in : in STD_LOGIC;
    gt3_rxpmaresetdone_out : out STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt3_rxbufreset_in : in STD_LOGIC;
    gt3_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_realign_out : out STD_LOGIC;
    gt3_rx_buf_err_out : out STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    sys_reset_out : out STD_LOGIC;
    LOOPBACK : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of aurora_rx_4l_64b_core : entity is 0;
  attribute SIM_GTRESET_SPEEDUP : string;
  attribute SIM_GTRESET_SPEEDUP of aurora_rx_4l_64b_core : entity is "FALSE";
end aurora_rx_4l_64b_core;

architecture STRUCTURE of aurora_rx_4l_64b_core is
  signal \<const0>\ : STD_LOGIC;
  signal CHBONDDONE_OUT : STD_LOGIC;
  signal CHBONDDONE_OUT_LANE1 : STD_LOGIC;
  signal CHBONDDONE_OUT_LANE2 : STD_LOGIC;
  signal CHBONDDONE_OUT_LANE3 : STD_LOGIC;
  signal GOT_A : STD_LOGIC_VECTOR ( 0 to 1 );
  signal GOT_V : STD_LOGIC;
  signal HARD_ERR : STD_LOGIC;
  signal HPCNT_RESET : STD_LOGIC;
  signal \^link_reset_out\ : STD_LOGIC;
  signal \^m_axi_rx_tkeep\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \^m_axi_ufc_rx_tkeep\ : STD_LOGIC_VECTOR ( 7 downto 3 );
  signal RESET : STD_LOGIC;
  signal RESET_24 : STD_LOGIC;
  signal \^rx_channel_up\ : STD_LOGIC;
  signal \^rx_lane_up\ : STD_LOGIC_VECTOR ( 0 to 3 );
  signal RX_PE_DATA : STD_LOGIC_VECTOR ( 8 to 10 );
  signal RX_PE_DATA_V : STD_LOGIC;
  signal RX_SCP : STD_LOGIC;
  signal RX_SUF : STD_LOGIC;
  signal \^tx_lock\ : STD_LOGIC;
  signal ch_bond_done_dly_i : STD_LOGIC_VECTOR ( 0 to 3 );
  signal ch_bond_done_r2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ch_bond_load_pulse_i : STD_LOGIC;
  signal \ch_bond_load_pulse_i[0]_i_1_n_0\ : STD_LOGIC;
  signal \ch_bond_load_pulse_i[1]_i_1_n_0\ : STD_LOGIC;
  signal \ch_bond_load_pulse_i[2]_i_1_n_0\ : STD_LOGIC;
  signal \ch_bond_load_pulse_i[3]_i_1_n_0\ : STD_LOGIC;
  signal \ch_bond_load_pulse_i_reg_n_0_[0]\ : STD_LOGIC;
  signal \ch_bond_load_pulse_i_reg_n_0_[1]\ : STD_LOGIC;
  signal \ch_bond_load_pulse_i_reg_n_0_[2]\ : STD_LOGIC;
  signal \ch_bond_load_pulse_i_reg_n_0_[3]\ : STD_LOGIC;
  signal en_chan_sync_i : STD_LOGIC;
  signal ena_comma_align_i_0 : STD_LOGIC;
  signal ena_comma_align_i_1 : STD_LOGIC;
  signal ena_comma_align_i_2 : STD_LOGIC;
  signal ena_comma_align_i_3 : STD_LOGIC;
  signal \^gt0_rx_buf_err_out\ : STD_LOGIC;
  signal \^gt0_rx_realign_out\ : STD_LOGIC;
  signal \^gt0_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt1_rx_buf_err_out\ : STD_LOGIC;
  signal \^gt1_rx_realign_out\ : STD_LOGIC;
  signal \^gt1_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt2_rx_buf_err_out\ : STD_LOGIC;
  signal \^gt2_rx_realign_out\ : STD_LOGIC;
  signal \^gt2_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gt3_rx_buf_err_out\ : STD_LOGIC;
  signal \^gt3_rx_realign_out\ : STD_LOGIC;
  signal \^gt3_rxbufstatus_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gt_reset_sync_init_clk : STD_LOGIC;
  signal gt_wrapper_i_n_231 : STD_LOGIC;
  signal gt_wrapper_i_n_232 : STD_LOGIC;
  signal gt_wrapper_i_n_233 : STD_LOGIC;
  signal gt_wrapper_i_n_234 : STD_LOGIC;
  signal gt_wrapper_i_n_235 : STD_LOGIC;
  signal gt_wrapper_i_n_236 : STD_LOGIC;
  signal gt_wrapper_i_n_237 : STD_LOGIC;
  signal gt_wrapper_i_n_238 : STD_LOGIC;
  signal gt_wrapper_i_n_239 : STD_LOGIC;
  signal gt_wrapper_i_n_242 : STD_LOGIC;
  signal gt_wrapper_i_n_244 : STD_LOGIC;
  signal gt_wrapper_i_n_245 : STD_LOGIC;
  signal gt_wrapper_i_n_246 : STD_LOGIC;
  signal gt_wrapper_i_n_247 : STD_LOGIC;
  signal gt_wrapper_i_n_248 : STD_LOGIC;
  signal gt_wrapper_i_n_249 : STD_LOGIC;
  signal gt_wrapper_i_n_250 : STD_LOGIC;
  signal gt_wrapper_i_n_251 : STD_LOGIC;
  signal gt_wrapper_i_n_252 : STD_LOGIC;
  signal gt_wrapper_i_n_253 : STD_LOGIC;
  signal gt_wrapper_i_n_254 : STD_LOGIC;
  signal gt_wrapper_i_n_255 : STD_LOGIC;
  signal gt_wrapper_i_n_256 : STD_LOGIC;
  signal gt_wrapper_i_n_257 : STD_LOGIC;
  signal gt_wrapper_i_n_258 : STD_LOGIC;
  signal gt_wrapper_i_n_259 : STD_LOGIC;
  signal gt_wrapper_i_n_260 : STD_LOGIC;
  signal gt_wrapper_i_n_263 : STD_LOGIC;
  signal gt_wrapper_i_n_265 : STD_LOGIC;
  signal gt_wrapper_i_n_266 : STD_LOGIC;
  signal gt_wrapper_i_n_267 : STD_LOGIC;
  signal gt_wrapper_i_n_268 : STD_LOGIC;
  signal gt_wrapper_i_n_269 : STD_LOGIC;
  signal gt_wrapper_i_n_270 : STD_LOGIC;
  signal gt_wrapper_i_n_271 : STD_LOGIC;
  signal gt_wrapper_i_n_272 : STD_LOGIC;
  signal gt_wrapper_i_n_273 : STD_LOGIC;
  signal gt_wrapper_i_n_274 : STD_LOGIC;
  signal gt_wrapper_i_n_275 : STD_LOGIC;
  signal gt_wrapper_i_n_276 : STD_LOGIC;
  signal gt_wrapper_i_n_277 : STD_LOGIC;
  signal gt_wrapper_i_n_278 : STD_LOGIC;
  signal gt_wrapper_i_n_279 : STD_LOGIC;
  signal gt_wrapper_i_n_280 : STD_LOGIC;
  signal gt_wrapper_i_n_281 : STD_LOGIC;
  signal gt_wrapper_i_n_284 : STD_LOGIC;
  signal gt_wrapper_i_n_286 : STD_LOGIC;
  signal gt_wrapper_i_n_287 : STD_LOGIC;
  signal gt_wrapper_i_n_288 : STD_LOGIC;
  signal gt_wrapper_i_n_289 : STD_LOGIC;
  signal gt_wrapper_i_n_290 : STD_LOGIC;
  signal gt_wrapper_i_n_291 : STD_LOGIC;
  signal gt_wrapper_i_n_292 : STD_LOGIC;
  signal gt_wrapper_i_n_293 : STD_LOGIC;
  signal gt_wrapper_i_n_294 : STD_LOGIC;
  signal gt_wrapper_i_n_295 : STD_LOGIC;
  signal gt_wrapper_i_n_296 : STD_LOGIC;
  signal gt_wrapper_i_n_297 : STD_LOGIC;
  signal gt_wrapper_i_n_298 : STD_LOGIC;
  signal gt_wrapper_i_n_299 : STD_LOGIC;
  signal gt_wrapper_i_n_300 : STD_LOGIC;
  signal gt_wrapper_i_n_301 : STD_LOGIC;
  signal gt_wrapper_i_n_302 : STD_LOGIC;
  signal gt_wrapper_i_n_305 : STD_LOGIC;
  signal gt_wrapper_i_n_307 : STD_LOGIC;
  signal gt_wrapper_i_n_308 : STD_LOGIC;
  signal gt_wrapper_i_n_309 : STD_LOGIC;
  signal gt_wrapper_i_n_310 : STD_LOGIC;
  signal gt_wrapper_i_n_311 : STD_LOGIC;
  signal gt_wrapper_i_n_312 : STD_LOGIC;
  signal gt_wrapper_i_n_313 : STD_LOGIC;
  signal gt_wrapper_i_n_314 : STD_LOGIC;
  signal gt_wrapper_i_n_315 : STD_LOGIC;
  signal gt_wrapper_i_n_316 : STD_LOGIC;
  signal gt_wrapper_i_n_317 : STD_LOGIC;
  signal gt_wrapper_i_n_318 : STD_LOGIC;
  signal gt_wrapper_i_n_319 : STD_LOGIC;
  signal gt_wrapper_i_n_320 : STD_LOGIC;
  signal gt_wrapper_i_n_321 : STD_LOGIC;
  signal gt_wrapper_i_n_322 : STD_LOGIC;
  signal gt_wrapper_i_n_323 : STD_LOGIC;
  signal gtp_rx_reset_i_0 : STD_LOGIC;
  signal gtp_rx_reset_i_1 : STD_LOGIC;
  signal gtp_rx_reset_i_2 : STD_LOGIC;
  signal gtp_rx_reset_i_3 : STD_LOGIC;
  signal gtrxreset_i : STD_LOGIC;
  signal link_reset_lane0_i : STD_LOGIC;
  signal link_reset_lane1_i : STD_LOGIC;
  signal link_reset_lane2_i : STD_LOGIC;
  signal link_reset_r : STD_LOGIC;
  signal reset_sync_init_clk : STD_LOGIC;
  signal reset_sync_user_clk : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_14 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_16 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_17 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_18 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_19 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_20 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_21 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_26 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_27 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_28 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_29 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_30 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_31 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_32 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_33 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_34 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_35 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_36 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_0_i_n_37 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_10 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_11 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_12 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_14 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_15 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_16 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_17 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_18 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_19 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_20 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_22 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_23 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_24 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_25 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_26 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_27 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_28 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_29 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_30 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_31 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_32 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_33 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_35 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_36 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_4 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_6 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_8 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_1_i_n_9 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_10 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_11 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_12 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_14 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_15 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_16 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_18 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_20 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_21 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_22 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_23 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_24 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_25 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_26 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_27 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_28 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_29 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_30 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_31 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_33 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_34 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_4 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_6 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_8 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_2_i_n_9 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_10 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_11 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_13 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_14 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_15 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_16 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_17 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_20 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_21 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_22 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_24 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_25 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_26 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_27 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_28 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_29 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_30 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_31 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_32 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_33 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_34 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_35 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_4 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_6 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_7 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_8 : STD_LOGIC;
  signal rx_aurora_lane_simplex_v5_3_i_n_9 : STD_LOGIC;
  signal \rx_channel_init_sm_simplex_i/bad_as_r0\ : STD_LOGIC;
  signal \rx_channel_init_sm_simplex_i/good_as_r0\ : STD_LOGIC;
  signal \rx_channel_init_sm_simplex_i/p_0_in10_in\ : STD_LOGIC;
  signal \rx_channel_init_sm_simplex_i/p_1_in11_in\ : STD_LOGIC;
  signal rx_char_is_comma_i_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_char_is_comma_i_2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_char_is_comma_i_4 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_char_is_comma_i_6 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_eof : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/bucket_full_r\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/bucket_full_r_10\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/bucket_full_r_16\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/bucket_full_r_22\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/hard_err_flop_r0\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_0\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_2\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_4\ : STD_LOGIC;
  signal \rx_err_detect_simplex_gtp_i/p_2_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rx_err_detect_simplex_gtp_i/p_2_out_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rx_err_detect_simplex_gtp_i/p_2_out_3\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rx_err_detect_simplex_gtp_i/p_2_out_5\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rx_global_logic_simplex_i_n_1 : STD_LOGIC;
  signal rx_global_logic_simplex_i_n_10 : STD_LOGIC;
  signal rx_global_logic_simplex_i_n_13 : STD_LOGIC;
  signal rx_global_logic_simplex_i_n_14 : STD_LOGIC;
  signal rx_global_logic_simplex_i_n_2 : STD_LOGIC;
  signal rx_global_logic_simplex_i_n_3 : STD_LOGIC;
  signal \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r\ : STD_LOGIC;
  signal \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_11\ : STD_LOGIC;
  signal \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_17\ : STD_LOGIC;
  signal \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_23\ : STD_LOGIC;
  signal rx_polarity_i_0 : STD_LOGIC;
  signal rx_polarity_i_1 : STD_LOGIC;
  signal rx_polarity_i_2 : STD_LOGIC;
  signal rx_polarity_i_3 : STD_LOGIC;
  signal rx_rem : STD_LOGIC_VECTOR ( 0 to 2 );
  signal rx_ufc_eof : STD_LOGIC;
  signal rx_ufc_rem : STD_LOGIC_VECTOR ( 0 to 1 );
  signal start_rx_i : STD_LOGIC;
  signal \sym_dec_i/RX_ECP_Buffer0\ : STD_LOGIC;
  signal \sym_dec_i/RX_ECP_Buffer0_12\ : STD_LOGIC;
  signal \sym_dec_i/RX_ECP_Buffer0_18\ : STD_LOGIC;
  signal \sym_dec_i/RX_ECP_Buffer0_6\ : STD_LOGIC;
  signal \sym_dec_i/first_v_received_r\ : STD_LOGIC;
  signal \sym_dec_i/first_v_received_r_14\ : STD_LOGIC;
  signal \sym_dec_i/first_v_received_r_20\ : STD_LOGIC;
  signal \sym_dec_i/first_v_received_r_8\ : STD_LOGIC;
  signal \sym_dec_i/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \sym_dec_i/p_0_in_15\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \sym_dec_i/p_0_in_21\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \sym_dec_i/p_0_in_9\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \sym_dec_i/std_bool26_out\ : STD_LOGIC;
  signal \sym_dec_i/std_bool26_out_13\ : STD_LOGIC;
  signal \sym_dec_i/std_bool26_out_19\ : STD_LOGIC;
  signal \sym_dec_i/std_bool26_out_7\ : STD_LOGIC;
  signal \^sys_reset_out\ : STD_LOGIC;
  signal \ufc_filter_i/neqOp\ : STD_LOGIC;
begin
  LINK_RESET_OUT <= \^link_reset_out\;
  M_AXI_RX_TKEEP(7 downto 1) <= \^m_axi_rx_tkeep\(7 downto 1);
  M_AXI_RX_TKEEP(0) <= \<const0>\;
  M_AXI_UFC_RX_TKEEP(7) <= \^m_axi_ufc_rx_tkeep\(7);
  M_AXI_UFC_RX_TKEEP(6) <= \^m_axi_ufc_rx_tkeep\(7);
  M_AXI_UFC_RX_TKEEP(5) <= \^m_axi_ufc_rx_tkeep\(5);
  M_AXI_UFC_RX_TKEEP(4) <= \^m_axi_ufc_rx_tkeep\(5);
  M_AXI_UFC_RX_TKEEP(3) <= \^m_axi_ufc_rx_tkeep\(3);
  M_AXI_UFC_RX_TKEEP(2) <= \^m_axi_ufc_rx_tkeep\(3);
  M_AXI_UFC_RX_TKEEP(1) <= \<const0>\;
  M_AXI_UFC_RX_TKEEP(0) <= \<const0>\;
  RX_CHANNEL_UP <= \^rx_channel_up\;
  RX_LANE_UP(0 to 3) <= \^rx_lane_up\(0 to 3);
  TX_LOCK <= \^tx_lock\;
  gt0_qpllreset_out <= \<const0>\;
  gt0_rx_buf_err_out <= \^gt0_rx_buf_err_out\;
  gt0_rx_realign_out <= \^gt0_rx_realign_out\;
  gt0_rxbufstatus_out(2) <= \^gt0_rx_buf_err_out\;
  gt0_rxbufstatus_out(1 downto 0) <= \^gt0_rxbufstatus_out\(1 downto 0);
  gt1_qpllreset_out <= \<const0>\;
  gt1_rx_buf_err_out <= \^gt1_rx_buf_err_out\;
  gt1_rx_realign_out <= \^gt1_rx_realign_out\;
  gt1_rxbufstatus_out(2) <= \^gt1_rx_buf_err_out\;
  gt1_rxbufstatus_out(1 downto 0) <= \^gt1_rxbufstatus_out\(1 downto 0);
  gt2_rx_buf_err_out <= \^gt2_rx_buf_err_out\;
  gt2_rx_realign_out <= \^gt2_rx_realign_out\;
  gt2_rxbufstatus_out(2) <= \^gt2_rx_buf_err_out\;
  gt2_rxbufstatus_out(1 downto 0) <= \^gt2_rxbufstatus_out\(1 downto 0);
  gt3_rx_buf_err_out <= \^gt3_rx_buf_err_out\;
  gt3_rx_realign_out <= \^gt3_rx_realign_out\;
  gt3_rxbufstatus_out(2) <= \^gt3_rx_buf_err_out\;
  gt3_rxbufstatus_out(1 downto 0) <= \^gt3_rxbufstatus_out\(1 downto 0);
  sys_reset_out <= \^sys_reset_out\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\ch_bond_done_dly_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ch_bond_done_r2(3),
      Q => ch_bond_done_dly_i(0),
      R => ch_bond_load_pulse_i
    );
\ch_bond_done_dly_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ch_bond_done_r2(2),
      Q => ch_bond_done_dly_i(1),
      R => ch_bond_load_pulse_i
    );
\ch_bond_done_dly_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ch_bond_done_r2(1),
      Q => ch_bond_done_dly_i(2),
      R => ch_bond_load_pulse_i
    );
\ch_bond_done_dly_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => ch_bond_done_r2(0),
      Q => ch_bond_done_dly_i(3),
      R => ch_bond_load_pulse_i
    );
\ch_bond_done_r2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_global_logic_simplex_i_n_13,
      Q => ch_bond_done_r2(0),
      R => '0'
    );
\ch_bond_done_r2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_channel_init_sm_simplex_i/p_1_in11_in\,
      Q => ch_bond_done_r2(1),
      R => '0'
    );
\ch_bond_done_r2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \rx_channel_init_sm_simplex_i/p_0_in10_in\,
      Q => ch_bond_done_r2(2),
      R => '0'
    );
\ch_bond_done_r2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => rx_global_logic_simplex_i_n_10,
      Q => ch_bond_done_r2(3),
      R => '0'
    );
\ch_bond_load_pulse_i[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ch_bond_done_r2(3),
      I1 => ch_bond_done_dly_i(0),
      O => \ch_bond_load_pulse_i[0]_i_1_n_0\
    );
\ch_bond_load_pulse_i[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ch_bond_done_r2(2),
      I1 => ch_bond_done_dly_i(1),
      O => \ch_bond_load_pulse_i[1]_i_1_n_0\
    );
\ch_bond_load_pulse_i[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ch_bond_done_r2(1),
      I1 => ch_bond_done_dly_i(2),
      O => \ch_bond_load_pulse_i[2]_i_1_n_0\
    );
\ch_bond_load_pulse_i[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ch_bond_done_r2(0),
      I1 => ch_bond_done_dly_i(3),
      O => \ch_bond_load_pulse_i[3]_i_1_n_0\
    );
\ch_bond_load_pulse_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ch_bond_load_pulse_i[0]_i_1_n_0\,
      Q => \ch_bond_load_pulse_i_reg_n_0_[0]\,
      R => ch_bond_load_pulse_i
    );
\ch_bond_load_pulse_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ch_bond_load_pulse_i[1]_i_1_n_0\,
      Q => \ch_bond_load_pulse_i_reg_n_0_[1]\,
      R => ch_bond_load_pulse_i
    );
\ch_bond_load_pulse_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ch_bond_load_pulse_i[2]_i_1_n_0\,
      Q => \ch_bond_load_pulse_i_reg_n_0_[2]\,
      R => ch_bond_load_pulse_i
    );
\ch_bond_load_pulse_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => '1',
      D => \ch_bond_load_pulse_i[3]_i_1_n_0\,
      Q => \ch_bond_load_pulse_i_reg_n_0_[3]\,
      R => ch_bond_load_pulse_i
    );
core_reset_logic_i: entity work.aurora_rx_4l_64b_RESET_LOGIC
     port map (
      SR(0) => ch_bond_load_pulse_i,
      SYSTEM_RESET_reg_0 => \^sys_reset_out\,
      TX_LOCK => \^tx_lock\,
      en_chan_sync_i => en_chan_sync_i,
      gt_rxresetdone_r2_reg_0 => gt_wrapper_i_n_323,
      init_clk_in => init_clk_in,
      link_reset_r => link_reset_r,
      \out\ => reset_sync_user_clk,
      user_clk => user_clk
    );
gt_reset_cdc_sync: entity work.aurora_rx_4l_64b_cdc_sync
     port map (
      GT_RESET => GT_RESET,
      HPCNT_RESET => HPCNT_RESET,
      \hotplug_count_synth.count_for_reset_r_reg[0]\ => reset_sync_init_clk,
      init_clk_in => init_clk_in,
      \out\ => gt_reset_sync_init_clk
    );
gt_wrapper_i: entity work.aurora_rx_4l_64b_GT_WRAPPER
     port map (
      CHBONDDONE_OUT => CHBONDDONE_OUT,
      CHBONDDONE_OUT_LANE1 => CHBONDDONE_OUT_LANE1,
      CHBONDDONE_OUT_LANE2 => CHBONDDONE_OUT_LANE2,
      CHBONDDONE_OUT_LANE3 => CHBONDDONE_OUT_LANE3,
      D(1 downto 0) => rx_char_is_comma_i_0(1 downto 0),
      DRPADDR_IN(8 downto 0) => DRPADDR_IN(8 downto 0),
      DRPADDR_IN_LANE1(8 downto 0) => DRPADDR_IN_LANE1(8 downto 0),
      DRPADDR_IN_LANE2(8 downto 0) => DRPADDR_IN_LANE2(8 downto 0),
      DRPADDR_IN_LANE3(8 downto 0) => DRPADDR_IN_LANE3(8 downto 0),
      DRPDI_IN(15 downto 0) => DRPDI_IN(15 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => DRPDI_IN_LANE1(15 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => DRPDI_IN_LANE2(15 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => DRPDI_IN_LANE3(15 downto 0),
      DRPDO_OUT(15 downto 0) => DRPDO_OUT(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => DRPDO_OUT_LANE1(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => DRPDO_OUT_LANE2(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => DRPDO_OUT_LANE3(15 downto 0),
      DRPEN_IN => DRPEN_IN,
      DRPEN_IN_LANE1 => DRPEN_IN_LANE1,
      DRPEN_IN_LANE2 => DRPEN_IN_LANE2,
      DRPEN_IN_LANE3 => DRPEN_IN_LANE3,
      DRPRDY_OUT => DRPRDY_OUT,
      DRPRDY_OUT_LANE1 => DRPRDY_OUT_LANE1,
      DRPRDY_OUT_LANE2 => DRPRDY_OUT_LANE2,
      DRPRDY_OUT_LANE3 => DRPRDY_OUT_LANE3,
      DRPWE_IN => DRPWE_IN,
      DRPWE_IN_LANE1 => DRPWE_IN_LANE1,
      DRPWE_IN_LANE2 => DRPWE_IN_LANE2,
      DRPWE_IN_LANE3 => DRPWE_IN_LANE3,
      LINK_RESET_OUT => \^link_reset_out\,
      LOOPBACK(2 downto 0) => LOOPBACK(2 downto 0),
      POWER_DOWN => POWER_DOWN,
      RXN(0 to 3) => RXN(0 to 3),
      RXP(0 to 3) => RXP(0 to 3),
      RX_RESETDONE_OUT => RX_RESETDONE_OUT,
      TX_LOCK => \^tx_lock\,
      TX_OUT_CLK => TX_OUT_CLK,
      bucket_full_r => \rx_err_detect_simplex_gtp_i/bucket_full_r\,
      bucket_full_r_11 => \rx_err_detect_simplex_gtp_i/bucket_full_r_22\,
      bucket_full_r_5 => \rx_err_detect_simplex_gtp_i/bucket_full_r_10\,
      bucket_full_r_8 => \rx_err_detect_simplex_gtp_i/bucket_full_r_16\,
      comma_over_two_cycles_r => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r\,
      comma_over_two_cycles_r_3 => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_11\,
      comma_over_two_cycles_r_6 => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_17\,
      comma_over_two_cycles_r_9 => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_23\,
      drpclk_in => drpclk_in,
      en_chan_sync_i => en_chan_sync_i,
      ena_comma_align_i_0 => ena_comma_align_i_0,
      ena_comma_align_i_1 => ena_comma_align_i_1,
      ena_comma_align_i_2 => ena_comma_align_i_2,
      ena_comma_align_i_3 => ena_comma_align_i_3,
      first_v_received_r => \sym_dec_i/first_v_received_r\,
      first_v_received_r_10 => \sym_dec_i/first_v_received_r_20\,
      first_v_received_r_4 => \sym_dec_i/first_v_received_r_8\,
      first_v_received_r_7 => \sym_dec_i/first_v_received_r_14\,
      first_v_received_r_reg => gt_wrapper_i_n_242,
      first_v_received_r_reg_0 => gt_wrapper_i_n_263,
      first_v_received_r_reg_1 => gt_wrapper_i_n_284,
      first_v_received_r_reg_2 => gt_wrapper_i_n_305,
      gt0_cplllock_out => gt0_cplllock_out,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_rx_disp_err_out(1 downto 0) => gt0_rx_disp_err_out(1 downto 0),
      gt0_rx_not_in_table_out(1 downto 0) => gt0_rx_not_in_table_out(1 downto 0),
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2) => \^gt0_rx_buf_err_out\,
      gt0_rxbufstatus_out(1 downto 0) => \^gt0_rxbufstatus_out\(1 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt1_cplllock_out => gt1_cplllock_out,
      gt1_dmonitorout_out(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
      gt1_eyescanreset_in => gt1_eyescanreset_in,
      gt1_eyescantrigger_in => gt1_eyescantrigger_in,
      gt1_rx_disp_err_out(1 downto 0) => gt1_rx_disp_err_out(1 downto 0),
      gt1_rx_not_in_table_out(1 downto 0) => gt1_rx_not_in_table_out(1 downto 0),
      gt1_rxbufreset_in => gt1_rxbufreset_in,
      gt1_rxbufstatus_out(2) => \^gt1_rx_buf_err_out\,
      gt1_rxbufstatus_out(1 downto 0) => \^gt1_rxbufstatus_out\(1 downto 0),
      gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
      gt1_rxcdrhold_in => gt1_rxcdrhold_in,
      gt1_rxcdrovrden_in => gt1_rxcdrovrden_in,
      gt1_rxcommadet_out => gt1_rxcommadet_out,
      gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
      gt1_rxlpmen_in => gt1_rxlpmen_in,
      gt1_rxmonitorout_out(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      gt1_rxmonitorsel_in(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      gt1_rxpcsreset_in => gt1_rxpcsreset_in,
      gt1_rxpmareset_in => gt1_rxpmareset_in,
      gt1_rxpmaresetdone_out => gt1_rxpmaresetdone_out,
      gt1_rxprbscntreset_in => gt1_rxprbscntreset_in,
      gt1_rxprbserr_out => gt1_rxprbserr_out,
      gt1_rxprbssel_in(2 downto 0) => gt1_rxprbssel_in(2 downto 0),
      gt1_rxresetdone_out => gt1_rxresetdone_out,
      gt2_cplllock_out => gt2_cplllock_out,
      gt2_dmonitorout_out(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      gt2_eyescandataerror_out => gt2_eyescandataerror_out,
      gt2_eyescanreset_in => gt2_eyescanreset_in,
      gt2_eyescantrigger_in => gt2_eyescantrigger_in,
      gt2_rx_disp_err_out(1 downto 0) => gt2_rx_disp_err_out(1 downto 0),
      gt2_rx_not_in_table_out(1 downto 0) => gt2_rx_not_in_table_out(1 downto 0),
      gt2_rxbufreset_in => gt2_rxbufreset_in,
      gt2_rxbufstatus_out(2) => \^gt2_rx_buf_err_out\,
      gt2_rxbufstatus_out(1 downto 0) => \^gt2_rxbufstatus_out\(1 downto 0),
      gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
      gt2_rxcdrhold_in => gt2_rxcdrhold_in,
      gt2_rxcdrovrden_in => gt2_rxcdrovrden_in,
      gt2_rxcommadet_out => gt2_rxcommadet_out,
      gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
      gt2_rxlpmen_in => gt2_rxlpmen_in,
      gt2_rxmonitorout_out(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      gt2_rxmonitorsel_in(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      gt2_rxpcsreset_in => gt2_rxpcsreset_in,
      gt2_rxpmareset_in => gt2_rxpmareset_in,
      gt2_rxpmaresetdone_out => gt2_rxpmaresetdone_out,
      gt2_rxprbscntreset_in => gt2_rxprbscntreset_in,
      gt2_rxprbserr_out => gt2_rxprbserr_out,
      gt2_rxprbssel_in(2 downto 0) => gt2_rxprbssel_in(2 downto 0),
      gt2_rxresetdone_out => gt2_rxresetdone_out,
      gt3_cplllock_out => gt3_cplllock_out,
      gt3_dmonitorout_out(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      gt3_eyescandataerror_out => gt3_eyescandataerror_out,
      gt3_eyescanreset_in => gt3_eyescanreset_in,
      gt3_eyescantrigger_in => gt3_eyescantrigger_in,
      gt3_rx_disp_err_out(1 downto 0) => gt3_rx_disp_err_out(1 downto 0),
      gt3_rx_not_in_table_out(1 downto 0) => gt3_rx_not_in_table_out(1 downto 0),
      gt3_rxbufreset_in => gt3_rxbufreset_in,
      gt3_rxbufstatus_out(2) => \^gt3_rx_buf_err_out\,
      gt3_rxbufstatus_out(1 downto 0) => \^gt3_rxbufstatus_out\(1 downto 0),
      gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
      gt3_rxcdrhold_in => gt3_rxcdrhold_in,
      gt3_rxcdrovrden_in => gt3_rxcdrovrden_in,
      gt3_rxcommadet_out => gt3_rxcommadet_out,
      gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
      gt3_rxlpmen_in => gt3_rxlpmen_in,
      gt3_rxmonitorout_out(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      gt3_rxmonitorsel_in(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      gt3_rxpcsreset_in => gt3_rxpcsreset_in,
      gt3_rxpmareset_in => gt3_rxpmareset_in,
      gt3_rxpmaresetdone_out => gt3_rxpmaresetdone_out,
      gt3_rxprbscntreset_in => gt3_rxprbscntreset_in,
      gt3_rxprbserr_out => gt3_rxprbserr_out,
      gt3_rxprbssel_in(2 downto 0) => gt3_rxprbssel_in(2 downto 0),
      gt3_rxresetdone_out => gt3_rxresetdone_out,
      gt_qpllclk_quad2_in => gt_qpllclk_quad2_in,
      gt_qpllclk_quad3_in => gt_qpllclk_quad3_in,
      gt_qpllrefclk_quad2_in => gt_qpllrefclk_quad2_in,
      gt_qpllrefclk_quad3_in => gt_qpllrefclk_quad3_in,
      gt_refclk1 => gt_refclk1,
      gthe2_i => \^gt0_rx_realign_out\,
      gthe2_i_0 => \^gt1_rx_realign_out\,
      gthe2_i_1(1 downto 0) => rx_char_is_comma_i_2(1 downto 0),
      gthe2_i_10 => gt_wrapper_i_n_235,
      gthe2_i_11 => gt_wrapper_i_n_236,
      gthe2_i_12 => gt_wrapper_i_n_237,
      gthe2_i_13 => gt_wrapper_i_n_238,
      gthe2_i_14 => gt_wrapper_i_n_239,
      gthe2_i_15(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out_5\(1 downto 0),
      gthe2_i_16(7) => gt_wrapper_i_n_244,
      gthe2_i_16(6) => gt_wrapper_i_n_245,
      gthe2_i_16(5) => gt_wrapper_i_n_246,
      gthe2_i_16(4) => gt_wrapper_i_n_247,
      gthe2_i_16(3) => gt_wrapper_i_n_248,
      gthe2_i_16(2) => gt_wrapper_i_n_249,
      gthe2_i_16(1) => gt_wrapper_i_n_250,
      gthe2_i_16(0) => gt_wrapper_i_n_251,
      gthe2_i_17(7) => gt_wrapper_i_n_252,
      gthe2_i_17(6) => gt_wrapper_i_n_253,
      gthe2_i_17(5) => gt_wrapper_i_n_254,
      gthe2_i_17(4) => gt_wrapper_i_n_255,
      gthe2_i_17(3) => gt_wrapper_i_n_256,
      gthe2_i_17(2) => gt_wrapper_i_n_257,
      gthe2_i_17(1) => gt_wrapper_i_n_258,
      gthe2_i_17(0) => gt_wrapper_i_n_259,
      gthe2_i_18 => gt_wrapper_i_n_260,
      gthe2_i_19(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out_3\(1 downto 0),
      gthe2_i_2 => \^gt2_rx_realign_out\,
      gthe2_i_20(7) => gt_wrapper_i_n_265,
      gthe2_i_20(6) => gt_wrapper_i_n_266,
      gthe2_i_20(5) => gt_wrapper_i_n_267,
      gthe2_i_20(4) => gt_wrapper_i_n_268,
      gthe2_i_20(3) => gt_wrapper_i_n_269,
      gthe2_i_20(2) => gt_wrapper_i_n_270,
      gthe2_i_20(1) => gt_wrapper_i_n_271,
      gthe2_i_20(0) => gt_wrapper_i_n_272,
      gthe2_i_21(7) => gt_wrapper_i_n_273,
      gthe2_i_21(6) => gt_wrapper_i_n_274,
      gthe2_i_21(5) => gt_wrapper_i_n_275,
      gthe2_i_21(4) => gt_wrapper_i_n_276,
      gthe2_i_21(3) => gt_wrapper_i_n_277,
      gthe2_i_21(2) => gt_wrapper_i_n_278,
      gthe2_i_21(1) => gt_wrapper_i_n_279,
      gthe2_i_21(0) => gt_wrapper_i_n_280,
      gthe2_i_22 => gt_wrapper_i_n_281,
      gthe2_i_23(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out_1\(1 downto 0),
      gthe2_i_24(7) => gt_wrapper_i_n_286,
      gthe2_i_24(6) => gt_wrapper_i_n_287,
      gthe2_i_24(5) => gt_wrapper_i_n_288,
      gthe2_i_24(4) => gt_wrapper_i_n_289,
      gthe2_i_24(3) => gt_wrapper_i_n_290,
      gthe2_i_24(2) => gt_wrapper_i_n_291,
      gthe2_i_24(1) => gt_wrapper_i_n_292,
      gthe2_i_24(0) => gt_wrapper_i_n_293,
      gthe2_i_25(7) => gt_wrapper_i_n_294,
      gthe2_i_25(6) => gt_wrapper_i_n_295,
      gthe2_i_25(5) => gt_wrapper_i_n_296,
      gthe2_i_25(4) => gt_wrapper_i_n_297,
      gthe2_i_25(3) => gt_wrapper_i_n_298,
      gthe2_i_25(2) => gt_wrapper_i_n_299,
      gthe2_i_25(1) => gt_wrapper_i_n_300,
      gthe2_i_25(0) => gt_wrapper_i_n_301,
      gthe2_i_26 => gt_wrapper_i_n_302,
      gthe2_i_27(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out\(1 downto 0),
      gthe2_i_28(7) => gt_wrapper_i_n_307,
      gthe2_i_28(6) => gt_wrapper_i_n_308,
      gthe2_i_28(5) => gt_wrapper_i_n_309,
      gthe2_i_28(4) => gt_wrapper_i_n_310,
      gthe2_i_28(3) => gt_wrapper_i_n_311,
      gthe2_i_28(2) => gt_wrapper_i_n_312,
      gthe2_i_28(1) => gt_wrapper_i_n_313,
      gthe2_i_28(0) => gt_wrapper_i_n_314,
      gthe2_i_29(7) => gt_wrapper_i_n_315,
      gthe2_i_29(6) => gt_wrapper_i_n_316,
      gthe2_i_29(5) => gt_wrapper_i_n_317,
      gthe2_i_29(4) => gt_wrapper_i_n_318,
      gthe2_i_29(3) => gt_wrapper_i_n_319,
      gthe2_i_29(2) => gt_wrapper_i_n_320,
      gthe2_i_29(1) => gt_wrapper_i_n_321,
      gthe2_i_29(0) => gt_wrapper_i_n_322,
      gthe2_i_3(1 downto 0) => rx_char_is_comma_i_4(1 downto 0),
      gthe2_i_4 => \^gt3_rx_realign_out\,
      gthe2_i_5(1 downto 0) => rx_char_is_comma_i_6(1 downto 0),
      gthe2_i_6 => gt_wrapper_i_n_231,
      gthe2_i_7 => gt_wrapper_i_n_232,
      gthe2_i_8 => gt_wrapper_i_n_233,
      gthe2_i_9 => gt_wrapper_i_n_234,
      gtp_rx_reset_i_0 => gtp_rx_reset_i_0,
      gtp_rx_reset_i_1 => gtp_rx_reset_i_1,
      gtp_rx_reset_i_2 => gtp_rx_reset_i_2,
      gtp_rx_reset_i_3 => gtp_rx_reset_i_3,
      gtrxreset_i => gtrxreset_i,
      hard_err_flop_r0 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_4\,
      hard_err_flop_r0_0 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_2\,
      hard_err_flop_r0_1 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_0\,
      hard_err_flop_r0_2 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0\,
      init_clk_in => init_clk_in,
      link_reset_r => link_reset_r,
      \out\ => gt_reset_sync_init_clk,
      rx_polarity_i_0 => rx_polarity_i_0,
      rx_polarity_i_1 => rx_polarity_i_1,
      rx_polarity_i_2 => rx_polarity_i_2,
      rx_polarity_i_3 => rx_polarity_i_3,
      rxfsm_rxresetdone_r3_reg_0 => gt_wrapper_i_n_323,
      sync_clk => sync_clk,
      user_clk => user_clk,
      \word_aligned_control_bits_r_reg[1]\ => rx_aurora_lane_simplex_v5_0_i_n_14,
      \word_aligned_control_bits_r_reg[1]_0\ => rx_aurora_lane_simplex_v5_1_i_n_14,
      \word_aligned_control_bits_r_reg[1]_1\ => rx_aurora_lane_simplex_v5_2_i_n_14,
      \word_aligned_control_bits_r_reg[1]_2\ => rx_aurora_lane_simplex_v5_3_i_n_13
    );
hpcnt_reset_cdc_sync: entity work.aurora_rx_4l_64b_cdc_sync_0
     port map (
      RX_SYSTEM_RESET => RX_SYSTEM_RESET,
      init_clk_in => init_clk_in,
      \out\ => reset_sync_init_clk
    );
ll_to_axi_pdu_i: entity work.aurora_rx_4l_64b_LL_TO_AXI
     port map (
      M_AXI_RX_TKEEP(6 downto 0) => \^m_axi_rx_tkeep\(7 downto 1),
      RX_EOF_N => rx_eof,
      RX_REM(0 to 2) => rx_rem(0 to 2)
    );
ll_to_axi_ufc_i: entity work.\aurora_rx_4l_64b_LL_TO_AXI__parameterized1\
     port map (
      M_AXI_UFC_RX_TKEEP(2) => \^m_axi_ufc_rx_tkeep\(7),
      M_AXI_UFC_RX_TKEEP(1) => \^m_axi_ufc_rx_tkeep\(5),
      M_AXI_UFC_RX_TKEEP(0) => \^m_axi_ufc_rx_tkeep\(3),
      UFC_RX_EOF_N => rx_ufc_eof,
      UFC_RX_REM(1) => rx_ufc_rem(0),
      UFC_RX_REM(0) => rx_ufc_rem(1)
    );
reset_sync_user_clk_cdc_sync: entity work.aurora_rx_4l_64b_cdc_sync_1
     port map (
      RX_SYSTEM_RESET => RX_SYSTEM_RESET,
      \out\ => reset_sync_user_clk,
      user_clk => user_clk
    );
rx_aurora_lane_simplex_v5_0_i: entity work.aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5
     port map (
      D(0) => HARD_ERR,
      GOT_A(0 to 1) => GOT_A(0 to 1),
      GOT_V => GOT_V,
      HPCNT_RESET => HPCNT_RESET,
      Q(0) => rx_aurora_lane_simplex_v5_1_i_n_35,
      \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0) => rx_char_is_comma_i_0(1 downto 0),
      RX_ECP_Buffer0 => \sym_dec_i/RX_ECP_Buffer0\,
      RX_LANE_UP(0) => \^rx_lane_up\(0),
      RX_PE_DATA(2) => RX_PE_DATA(8),
      RX_PE_DATA(1) => RX_PE_DATA(9),
      RX_PE_DATA(0) => RX_PE_DATA(10),
      \RX_PE_DATA_Buffer_reg[10]\ => rx_aurora_lane_simplex_v5_0_i_n_17,
      \RX_PE_DATA_Buffer_reg[8]\ => rx_aurora_lane_simplex_v5_0_i_n_19,
      \RX_PE_DATA_Buffer_reg[8]_0\ => rx_aurora_lane_simplex_v5_0_i_n_20,
      RX_PE_DATA_V_Buffer_reg(0) => RX_PE_DATA_V,
      RX_SCP_Buffer_reg(0) => RX_SCP,
      RX_SUF => RX_SUF,
      RX_SUF_Buffer_reg => rx_aurora_lane_simplex_v5_0_i_n_18,
      RX_SUF_Buffer_reg_0 => rx_aurora_lane_simplex_v5_0_i_n_21,
      SR(0) => RESET,
      begin_r_reg => \^gt0_rx_realign_out\,
      bucket_full_r => \rx_err_detect_simplex_gtp_i/bucket_full_r\,
      comma_over_two_cycles_r => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r\,
      \counter2_r_reg[15]\ => \^rx_channel_up\,
      ena_comma_align_i_0 => ena_comma_align_i_0,
      first_v_received_r => \sym_dec_i/first_v_received_r\,
      good_as_r0 => \rx_channel_init_sm_simplex_i/good_as_r0\,
      good_as_r_reg => rx_aurora_lane_simplex_v5_3_i_n_20,
      good_as_r_reg_0 => rx_aurora_lane_simplex_v5_2_i_n_34,
      good_as_r_reg_1 => rx_aurora_lane_simplex_v5_1_i_n_36,
      good_as_r_reg_2(0) => rx_aurora_lane_simplex_v5_2_i_n_33,
      good_as_r_reg_3(0) => rx_aurora_lane_simplex_v5_3_i_n_21,
      gtp_rx_reset_i_0 => gtp_rx_reset_i_0,
      hard_err_flop_r0 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_4\,
      init_clk_in => init_clk_in,
      left_aligned_r_reg => rx_aurora_lane_simplex_v5_0_i_n_14,
      left_aligned_r_reg_0 => gt_wrapper_i_n_242,
      link_reset_lane0_i => link_reset_lane0_i,
      reset_count_r_reg => gt_wrapper_i_n_239,
      rx_polarity_i_0 => rx_polarity_i_0,
      \soft_err_r_reg[0]\(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out_5\(1 downto 0),
      \stage_1_count_value_r_reg[1]\ => rx_aurora_lane_simplex_v5_2_i_n_8,
      \stage_1_count_value_r_reg[2]\ => rx_aurora_lane_simplex_v5_2_i_n_12,
      \stage_1_lane_mask_r_reg[2]\ => rx_aurora_lane_simplex_v5_1_i_n_12,
      \stage_1_lane_mask_r_reg[3]\ => rx_aurora_lane_simplex_v5_1_i_n_17,
      start_rx_i => start_rx_i,
      std_bool26_out => \sym_dec_i/std_bool26_out\,
      user_clk => user_clk,
      user_clk_0 => rx_aurora_lane_simplex_v5_0_i_n_16,
      \word_aligned_control_bits_r_reg[0]\ => gt_wrapper_i_n_232,
      \word_aligned_control_bits_r_reg[1]\ => gt_wrapper_i_n_231,
      \word_aligned_data_r_reg[0]\(7) => rx_aurora_lane_simplex_v5_0_i_n_30,
      \word_aligned_data_r_reg[0]\(6) => rx_aurora_lane_simplex_v5_0_i_n_31,
      \word_aligned_data_r_reg[0]\(5) => rx_aurora_lane_simplex_v5_0_i_n_32,
      \word_aligned_data_r_reg[0]\(4) => rx_aurora_lane_simplex_v5_0_i_n_33,
      \word_aligned_data_r_reg[0]\(3) => rx_aurora_lane_simplex_v5_0_i_n_34,
      \word_aligned_data_r_reg[0]\(2) => rx_aurora_lane_simplex_v5_0_i_n_35,
      \word_aligned_data_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_0_i_n_36,
      \word_aligned_data_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_0_i_n_37,
      \word_aligned_data_r_reg[0]_0\(7) => gt_wrapper_i_n_252,
      \word_aligned_data_r_reg[0]_0\(6) => gt_wrapper_i_n_253,
      \word_aligned_data_r_reg[0]_0\(5) => gt_wrapper_i_n_254,
      \word_aligned_data_r_reg[0]_0\(4) => gt_wrapper_i_n_255,
      \word_aligned_data_r_reg[0]_0\(3) => gt_wrapper_i_n_256,
      \word_aligned_data_r_reg[0]_0\(2) => gt_wrapper_i_n_257,
      \word_aligned_data_r_reg[0]_0\(1) => gt_wrapper_i_n_258,
      \word_aligned_data_r_reg[0]_0\(0) => gt_wrapper_i_n_259,
      \word_aligned_data_r_reg[11]\(4) => \sym_dec_i/p_0_in\(0),
      \word_aligned_data_r_reg[11]\(3) => rx_aurora_lane_simplex_v5_0_i_n_26,
      \word_aligned_data_r_reg[11]\(2) => rx_aurora_lane_simplex_v5_0_i_n_27,
      \word_aligned_data_r_reg[11]\(1) => rx_aurora_lane_simplex_v5_0_i_n_28,
      \word_aligned_data_r_reg[11]\(0) => rx_aurora_lane_simplex_v5_0_i_n_29,
      \word_aligned_data_r_reg[8]\(7) => gt_wrapper_i_n_244,
      \word_aligned_data_r_reg[8]\(6) => gt_wrapper_i_n_245,
      \word_aligned_data_r_reg[8]\(5) => gt_wrapper_i_n_246,
      \word_aligned_data_r_reg[8]\(4) => gt_wrapper_i_n_247,
      \word_aligned_data_r_reg[8]\(3) => gt_wrapper_i_n_248,
      \word_aligned_data_r_reg[8]\(2) => gt_wrapper_i_n_249,
      \word_aligned_data_r_reg[8]\(1) => gt_wrapper_i_n_250,
      \word_aligned_data_r_reg[8]\(0) => gt_wrapper_i_n_251
    );
rx_aurora_lane_simplex_v5_1_i: entity work.aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2
     port map (
      D(0) => rx_aurora_lane_simplex_v5_1_i_n_6,
      \GOT_A_Buffer_reg[0]\ => rx_aurora_lane_simplex_v5_1_i_n_36,
      \GOT_A_Buffer_reg[1]\(0) => rx_aurora_lane_simplex_v5_1_i_n_35,
      GOT_V_Buffer_reg => rx_aurora_lane_simplex_v5_1_i_n_4,
      HPCNT_RESET => HPCNT_RESET,
      Q(4) => \sym_dec_i/p_0_in_9\(0),
      Q(3) => rx_aurora_lane_simplex_v5_1_i_n_22,
      Q(2) => rx_aurora_lane_simplex_v5_1_i_n_23,
      Q(1) => rx_aurora_lane_simplex_v5_1_i_n_24,
      Q(0) => rx_aurora_lane_simplex_v5_1_i_n_25,
      \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0) => rx_char_is_comma_i_2(1 downto 0),
      RX_ECP_Buffer0 => \sym_dec_i/RX_ECP_Buffer0_6\,
      RX_LANE_UP(0) => \^rx_lane_up\(1),
      \RX_PE_DATA_Buffer_reg[10]\ => rx_aurora_lane_simplex_v5_1_i_n_10,
      \RX_PE_DATA_Buffer_reg[10]_0\ => rx_aurora_lane_simplex_v5_1_i_n_17,
      \RX_PE_DATA_Buffer_reg[10]_1\ => rx_aurora_lane_simplex_v5_1_i_n_19,
      \RX_PE_DATA_Buffer_reg[10]_2\ => rx_aurora_lane_simplex_v5_1_i_n_20,
      \RX_PE_DATA_Buffer_reg[8]\ => rx_aurora_lane_simplex_v5_1_i_n_9,
      \RX_PE_DATA_Buffer_reg[9]\ => rx_aurora_lane_simplex_v5_1_i_n_8,
      RX_PE_DATA_V_Buffer_reg(0) => rx_aurora_lane_simplex_v5_1_i_n_15,
      RX_SCP_Buffer_reg(0) => rx_aurora_lane_simplex_v5_1_i_n_11,
      RX_SUF => RX_SUF,
      RX_SUF_Buffer_reg => rx_aurora_lane_simplex_v5_1_i_n_12,
      RX_SUF_Buffer_reg_0 => rx_aurora_lane_simplex_v5_1_i_n_18,
      SR(0) => rx_global_logic_simplex_i_n_1,
      begin_r_reg => \^gt1_rx_realign_out\,
      bucket_full_r => \rx_err_detect_simplex_gtp_i/bucket_full_r_10\,
      comma_over_two_cycles_r => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_11\,
      \counter2_r_reg[15]\ => \^rx_channel_up\,
      ena_comma_align_i_1 => ena_comma_align_i_1,
      first_v_received_r => \sym_dec_i/first_v_received_r_8\,
      gtp_rx_reset_i_1 => gtp_rx_reset_i_1,
      hard_err_flop_r0 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_2\,
      init_clk_in => init_clk_in,
      left_aligned_r_reg => rx_aurora_lane_simplex_v5_1_i_n_14,
      left_aligned_r_reg_0 => gt_wrapper_i_n_263,
      link_reset_lane1_i => link_reset_lane1_i,
      reset_count_r_reg => gt_wrapper_i_n_260,
      rx_polarity_i_1 => rx_polarity_i_1,
      \soft_err_r_reg[0]\(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out_3\(1 downto 0),
      \stage_1_count_value_r_reg[1]\ => rx_aurora_lane_simplex_v5_2_i_n_12,
      \stage_1_count_value_r_reg[2]\ => rx_aurora_lane_simplex_v5_2_i_n_10,
      std_bool26_out => \sym_dec_i/std_bool26_out_7\,
      user_clk => user_clk,
      user_clk_0 => rx_aurora_lane_simplex_v5_1_i_n_16,
      \word_aligned_control_bits_r_reg[0]\ => gt_wrapper_i_n_234,
      \word_aligned_control_bits_r_reg[1]\ => gt_wrapper_i_n_233,
      \word_aligned_data_r_reg[0]\(7) => rx_aurora_lane_simplex_v5_1_i_n_26,
      \word_aligned_data_r_reg[0]\(6) => rx_aurora_lane_simplex_v5_1_i_n_27,
      \word_aligned_data_r_reg[0]\(5) => rx_aurora_lane_simplex_v5_1_i_n_28,
      \word_aligned_data_r_reg[0]\(4) => rx_aurora_lane_simplex_v5_1_i_n_29,
      \word_aligned_data_r_reg[0]\(3) => rx_aurora_lane_simplex_v5_1_i_n_30,
      \word_aligned_data_r_reg[0]\(2) => rx_aurora_lane_simplex_v5_1_i_n_31,
      \word_aligned_data_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_1_i_n_32,
      \word_aligned_data_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_1_i_n_33,
      \word_aligned_data_r_reg[0]_0\(7) => gt_wrapper_i_n_273,
      \word_aligned_data_r_reg[0]_0\(6) => gt_wrapper_i_n_274,
      \word_aligned_data_r_reg[0]_0\(5) => gt_wrapper_i_n_275,
      \word_aligned_data_r_reg[0]_0\(4) => gt_wrapper_i_n_276,
      \word_aligned_data_r_reg[0]_0\(3) => gt_wrapper_i_n_277,
      \word_aligned_data_r_reg[0]_0\(2) => gt_wrapper_i_n_278,
      \word_aligned_data_r_reg[0]_0\(1) => gt_wrapper_i_n_279,
      \word_aligned_data_r_reg[0]_0\(0) => gt_wrapper_i_n_280,
      \word_aligned_data_r_reg[8]\(7) => gt_wrapper_i_n_265,
      \word_aligned_data_r_reg[8]\(6) => gt_wrapper_i_n_266,
      \word_aligned_data_r_reg[8]\(5) => gt_wrapper_i_n_267,
      \word_aligned_data_r_reg[8]\(4) => gt_wrapper_i_n_268,
      \word_aligned_data_r_reg[8]\(3) => gt_wrapper_i_n_269,
      \word_aligned_data_r_reg[8]\(2) => gt_wrapper_i_n_270,
      \word_aligned_data_r_reg[8]\(1) => gt_wrapper_i_n_271,
      \word_aligned_data_r_reg[8]\(0) => gt_wrapper_i_n_272
    );
rx_aurora_lane_simplex_v5_2_i: entity work.aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3
     port map (
      D(0) => rx_aurora_lane_simplex_v5_2_i_n_6,
      \GOT_A_Buffer_reg[0]\ => rx_aurora_lane_simplex_v5_2_i_n_34,
      \GOT_A_Buffer_reg[1]\(0) => rx_aurora_lane_simplex_v5_2_i_n_33,
      GOT_V_Buffer_reg => rx_aurora_lane_simplex_v5_2_i_n_4,
      HPCNT_RESET => HPCNT_RESET,
      Q(4) => \sym_dec_i/p_0_in_15\(0),
      Q(3) => rx_aurora_lane_simplex_v5_2_i_n_20,
      Q(2) => rx_aurora_lane_simplex_v5_2_i_n_21,
      Q(1) => rx_aurora_lane_simplex_v5_2_i_n_22,
      Q(0) => rx_aurora_lane_simplex_v5_2_i_n_23,
      \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0) => rx_char_is_comma_i_4(1 downto 0),
      RX_ECP_Buffer0 => \sym_dec_i/RX_ECP_Buffer0_12\,
      RX_LANE_UP(0) => \^rx_lane_up\(2),
      \RX_PE_DATA_Buffer_reg[10]\ => rx_aurora_lane_simplex_v5_2_i_n_9,
      \RX_PE_DATA_Buffer_reg[8]\ => rx_aurora_lane_simplex_v5_2_i_n_8,
      \RX_PE_DATA_Buffer_reg[9]\ => rx_aurora_lane_simplex_v5_2_i_n_10,
      RX_PE_DATA_V_Buffer_reg(0) => rx_aurora_lane_simplex_v5_2_i_n_15,
      RX_SCP_Buffer_reg(0) => rx_aurora_lane_simplex_v5_2_i_n_11,
      RX_SUF_Buffer_reg => rx_aurora_lane_simplex_v5_2_i_n_12,
      RX_SUF_Buffer_reg_0 => rx_aurora_lane_simplex_v5_2_i_n_18,
      SR(0) => rx_global_logic_simplex_i_n_2,
      begin_r_reg => \^gt2_rx_realign_out\,
      bucket_full_r => \rx_err_detect_simplex_gtp_i/bucket_full_r_16\,
      comma_over_two_cycles_r => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_17\,
      \counter2_r_reg[15]\ => \^rx_channel_up\,
      ena_comma_align_i_2 => ena_comma_align_i_2,
      first_v_received_r => \sym_dec_i/first_v_received_r_14\,
      gtp_rx_reset_i_2 => gtp_rx_reset_i_2,
      hard_err_flop_r0 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_0\,
      init_clk_in => init_clk_in,
      left_aligned_r_reg => rx_aurora_lane_simplex_v5_2_i_n_14,
      left_aligned_r_reg_0 => gt_wrapper_i_n_284,
      link_reset_lane2_i => link_reset_lane2_i,
      load_ufc_control_code_r_reg(2) => RX_SUF,
      load_ufc_control_code_r_reg(1) => rx_aurora_lane_simplex_v5_1_i_n_12,
      load_ufc_control_code_r_reg(0) => rx_aurora_lane_simplex_v5_3_i_n_11,
      neqOp => \ufc_filter_i/neqOp\,
      reset_count_r_reg => gt_wrapper_i_n_281,
      rx_polarity_i_2 => rx_polarity_i_2,
      \soft_err_r_reg[0]\(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out_1\(1 downto 0),
      \stage_1_count_value_r_reg[3]\ => rx_aurora_lane_simplex_v5_0_i_n_20,
      \stage_1_count_value_r_reg[3]_0\ => rx_aurora_lane_simplex_v5_1_i_n_20,
      \stage_1_count_value_r_reg[3]_1\ => rx_aurora_lane_simplex_v5_3_i_n_9,
      std_bool26_out => \sym_dec_i/std_bool26_out_13\,
      user_clk => user_clk,
      user_clk_0 => rx_aurora_lane_simplex_v5_2_i_n_16,
      \word_aligned_control_bits_r_reg[0]\ => gt_wrapper_i_n_236,
      \word_aligned_control_bits_r_reg[1]\ => gt_wrapper_i_n_235,
      \word_aligned_data_r_reg[0]\(7) => rx_aurora_lane_simplex_v5_2_i_n_24,
      \word_aligned_data_r_reg[0]\(6) => rx_aurora_lane_simplex_v5_2_i_n_25,
      \word_aligned_data_r_reg[0]\(5) => rx_aurora_lane_simplex_v5_2_i_n_26,
      \word_aligned_data_r_reg[0]\(4) => rx_aurora_lane_simplex_v5_2_i_n_27,
      \word_aligned_data_r_reg[0]\(3) => rx_aurora_lane_simplex_v5_2_i_n_28,
      \word_aligned_data_r_reg[0]\(2) => rx_aurora_lane_simplex_v5_2_i_n_29,
      \word_aligned_data_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_2_i_n_30,
      \word_aligned_data_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_2_i_n_31,
      \word_aligned_data_r_reg[0]_0\(7) => gt_wrapper_i_n_294,
      \word_aligned_data_r_reg[0]_0\(6) => gt_wrapper_i_n_295,
      \word_aligned_data_r_reg[0]_0\(5) => gt_wrapper_i_n_296,
      \word_aligned_data_r_reg[0]_0\(4) => gt_wrapper_i_n_297,
      \word_aligned_data_r_reg[0]_0\(3) => gt_wrapper_i_n_298,
      \word_aligned_data_r_reg[0]_0\(2) => gt_wrapper_i_n_299,
      \word_aligned_data_r_reg[0]_0\(1) => gt_wrapper_i_n_300,
      \word_aligned_data_r_reg[0]_0\(0) => gt_wrapper_i_n_301,
      \word_aligned_data_r_reg[8]\(7) => gt_wrapper_i_n_286,
      \word_aligned_data_r_reg[8]\(6) => gt_wrapper_i_n_287,
      \word_aligned_data_r_reg[8]\(5) => gt_wrapper_i_n_288,
      \word_aligned_data_r_reg[8]\(4) => gt_wrapper_i_n_289,
      \word_aligned_data_r_reg[8]\(3) => gt_wrapper_i_n_290,
      \word_aligned_data_r_reg[8]\(2) => gt_wrapper_i_n_291,
      \word_aligned_data_r_reg[8]\(1) => gt_wrapper_i_n_292,
      \word_aligned_data_r_reg[8]\(0) => gt_wrapper_i_n_293
    );
rx_aurora_lane_simplex_v5_3_i: entity work.aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4
     port map (
      D(0) => rx_aurora_lane_simplex_v5_3_i_n_6,
      GOT_A(0 to 1) => GOT_A(0 to 1),
      \GOT_A_Buffer_reg[0]\ => rx_aurora_lane_simplex_v5_3_i_n_20,
      GOT_V_Buffer_reg => rx_aurora_lane_simplex_v5_3_i_n_4,
      HPCNT_RESET => HPCNT_RESET,
      LINK_RESET_OUT => \^link_reset_out\,
      Q(0) => rx_aurora_lane_simplex_v5_3_i_n_21,
      \RX_CHAR_IS_COMMA_R_reg[1]\(1 downto 0) => rx_char_is_comma_i_6(1 downto 0),
      RX_ECP_Buffer0 => \sym_dec_i/RX_ECP_Buffer0_18\,
      RX_LANE_UP(0) => \^rx_lane_up\(3),
      RX_PE_DATA(0) => RX_PE_DATA(9),
      \RX_PE_DATA_Buffer_reg[10]\ => rx_aurora_lane_simplex_v5_3_i_n_9,
      \RX_PE_DATA_Buffer_reg[8]\ => rx_aurora_lane_simplex_v5_3_i_n_8,
      \RX_PE_DATA_Buffer_reg[9]\ => rx_aurora_lane_simplex_v5_3_i_n_7,
      \RX_PE_DATA_Buffer_reg[9]_0\ => rx_aurora_lane_simplex_v5_3_i_n_17,
      \RX_PE_DATA_Buffer_reg[9]_1\ => rx_aurora_lane_simplex_v5_3_i_n_22,
      RX_PE_DATA_V_Buffer_reg(0) => rx_aurora_lane_simplex_v5_3_i_n_14,
      RX_SCP_Buffer_reg(0) => rx_aurora_lane_simplex_v5_3_i_n_10,
      RX_SUF_Buffer_reg(0) => rx_aurora_lane_simplex_v5_3_i_n_11,
      RX_SUF_Buffer_reg_0 => rx_aurora_lane_simplex_v5_3_i_n_16,
      SR(0) => rx_global_logic_simplex_i_n_3,
      bad_as_r0 => \rx_channel_init_sm_simplex_i/bad_as_r0\,
      bad_as_r_reg => rx_aurora_lane_simplex_v5_1_i_n_36,
      bad_as_r_reg_0 => rx_aurora_lane_simplex_v5_2_i_n_34,
      bad_as_r_reg_1(0) => rx_aurora_lane_simplex_v5_2_i_n_33,
      bad_as_r_reg_2(0) => rx_aurora_lane_simplex_v5_1_i_n_35,
      begin_r_reg => \^gt3_rx_realign_out\,
      bucket_full_r => \rx_err_detect_simplex_gtp_i/bucket_full_r_22\,
      comma_over_two_cycles_r => \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_23\,
      \counter2_r_reg[15]\ => \^rx_channel_up\,
      ena_comma_align_i_3 => ena_comma_align_i_3,
      first_v_received_r => \sym_dec_i/first_v_received_r_20\,
      gtp_rx_reset_i_3 => gtp_rx_reset_i_3,
      hard_err_flop_r0 => \rx_err_detect_simplex_gtp_i/hard_err_flop_r0\,
      init_clk_in => init_clk_in,
      left_aligned_r_reg => rx_aurora_lane_simplex_v5_3_i_n_13,
      left_aligned_r_reg_0 => gt_wrapper_i_n_305,
      link_reset_lane0_i => link_reset_lane0_i,
      link_reset_lane1_i => link_reset_lane1_i,
      link_reset_lane2_i => link_reset_lane2_i,
      reset_count_r_reg => gt_wrapper_i_n_302,
      rx_polarity_i_3 => rx_polarity_i_3,
      \soft_err_r_reg[0]\(1 downto 0) => \rx_err_detect_simplex_gtp_i/p_2_out\(1 downto 0),
      \stage_1_count_value_r_reg[1]\ => rx_aurora_lane_simplex_v5_0_i_n_18,
      \stage_1_count_value_r_reg[1]_0\ => rx_aurora_lane_simplex_v5_1_i_n_19,
      \stage_1_count_value_r_reg[2]\ => rx_aurora_lane_simplex_v5_1_i_n_18,
      \stage_1_count_value_r_reg[2]_0\ => rx_aurora_lane_simplex_v5_0_i_n_21,
      std_bool26_out => \sym_dec_i/std_bool26_out_19\,
      user_clk => user_clk,
      user_clk_0 => rx_aurora_lane_simplex_v5_3_i_n_15,
      \word_aligned_control_bits_r_reg[0]\ => gt_wrapper_i_n_238,
      \word_aligned_control_bits_r_reg[1]\ => gt_wrapper_i_n_237,
      \word_aligned_data_r_reg[0]\(7) => rx_aurora_lane_simplex_v5_3_i_n_28,
      \word_aligned_data_r_reg[0]\(6) => rx_aurora_lane_simplex_v5_3_i_n_29,
      \word_aligned_data_r_reg[0]\(5) => rx_aurora_lane_simplex_v5_3_i_n_30,
      \word_aligned_data_r_reg[0]\(4) => rx_aurora_lane_simplex_v5_3_i_n_31,
      \word_aligned_data_r_reg[0]\(3) => rx_aurora_lane_simplex_v5_3_i_n_32,
      \word_aligned_data_r_reg[0]\(2) => rx_aurora_lane_simplex_v5_3_i_n_33,
      \word_aligned_data_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_3_i_n_34,
      \word_aligned_data_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_3_i_n_35,
      \word_aligned_data_r_reg[0]_0\(7) => gt_wrapper_i_n_315,
      \word_aligned_data_r_reg[0]_0\(6) => gt_wrapper_i_n_316,
      \word_aligned_data_r_reg[0]_0\(5) => gt_wrapper_i_n_317,
      \word_aligned_data_r_reg[0]_0\(4) => gt_wrapper_i_n_318,
      \word_aligned_data_r_reg[0]_0\(3) => gt_wrapper_i_n_319,
      \word_aligned_data_r_reg[0]_0\(2) => gt_wrapper_i_n_320,
      \word_aligned_data_r_reg[0]_0\(1) => gt_wrapper_i_n_321,
      \word_aligned_data_r_reg[0]_0\(0) => gt_wrapper_i_n_322,
      \word_aligned_data_r_reg[11]\(4) => \sym_dec_i/p_0_in_21\(0),
      \word_aligned_data_r_reg[11]\(3) => rx_aurora_lane_simplex_v5_3_i_n_24,
      \word_aligned_data_r_reg[11]\(2) => rx_aurora_lane_simplex_v5_3_i_n_25,
      \word_aligned_data_r_reg[11]\(1) => rx_aurora_lane_simplex_v5_3_i_n_26,
      \word_aligned_data_r_reg[11]\(0) => rx_aurora_lane_simplex_v5_3_i_n_27,
      \word_aligned_data_r_reg[8]\(7) => gt_wrapper_i_n_307,
      \word_aligned_data_r_reg[8]\(6) => gt_wrapper_i_n_308,
      \word_aligned_data_r_reg[8]\(5) => gt_wrapper_i_n_309,
      \word_aligned_data_r_reg[8]\(4) => gt_wrapper_i_n_310,
      \word_aligned_data_r_reg[8]\(3) => gt_wrapper_i_n_311,
      \word_aligned_data_r_reg[8]\(2) => gt_wrapper_i_n_312,
      \word_aligned_data_r_reg[8]\(1) => gt_wrapper_i_n_313,
      \word_aligned_data_r_reg[8]\(0) => gt_wrapper_i_n_314
    );
rx_global_logic_simplex_i: entity work.aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX
     port map (
      CHANNEL_UP_Buffer_reg => \^rx_channel_up\,
      CHBONDDONE_OUT => CHBONDDONE_OUT,
      CHBONDDONE_OUT_LANE1 => CHBONDDONE_OUT_LANE1,
      CHBONDDONE_OUT_LANE2 => CHBONDDONE_OUT_LANE2,
      CHBONDDONE_OUT_LANE3 => CHBONDDONE_OUT_LANE3,
      D(3) => rx_global_logic_simplex_i_n_10,
      D(2) => \rx_channel_init_sm_simplex_i/p_0_in10_in\,
      D(1) => \rx_channel_init_sm_simplex_i/p_1_in11_in\,
      D(0) => rx_global_logic_simplex_i_n_13,
      GOT_V => GOT_V,
      POWER_DOWN => POWER_DOWN,
      Q(3) => \ch_bond_load_pulse_i_reg_n_0_[0]\,
      Q(2) => \ch_bond_load_pulse_i_reg_n_0_[1]\,
      Q(1) => \ch_bond_load_pulse_i_reg_n_0_[2]\,
      Q(0) => \ch_bond_load_pulse_i_reg_n_0_[3]\,
      RESET => RESET_24,
      RX_HARD_ERR => RX_HARD_ERR,
      RX_LANE_UP(0 to 3) => \^rx_lane_up\(0 to 3),
      RX_SUF => RX_SUF,
      SOFT_ERR => SOFT_ERR,
      SR(0) => RESET,
      START_RX_Buffer_reg => rx_global_logic_simplex_i_n_14,
      START_RX_Buffer_reg_0 => \^sys_reset_out\,
      all_lanes_v_r_reg => rx_aurora_lane_simplex_v5_1_i_n_4,
      all_lanes_v_r_reg_0 => rx_aurora_lane_simplex_v5_2_i_n_4,
      all_lanes_v_r_reg_1 => rx_aurora_lane_simplex_v5_3_i_n_4,
      bad_as_r0 => \rx_channel_init_sm_simplex_i/bad_as_r0\,
      en_chan_sync_i => en_chan_sync_i,
      good_as_r0 => \rx_channel_init_sm_simplex_i/good_as_r0\,
      gtrxreset_i => gtrxreset_i,
      \hard_err_r_reg[0]\(3) => HARD_ERR,
      \hard_err_r_reg[0]\(2) => rx_aurora_lane_simplex_v5_1_i_n_6,
      \hard_err_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_2_i_n_6,
      \hard_err_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_3_i_n_6,
      reset_lanes_flop_1_i(0) => rx_global_logic_simplex_i_n_1,
      reset_lanes_flop_2_i(0) => rx_global_logic_simplex_i_n_2,
      reset_lanes_flop_3_i(0) => rx_global_logic_simplex_i_n_3,
      \soft_err_r_reg[0]\ => rx_aurora_lane_simplex_v5_0_i_n_16,
      \soft_err_r_reg[1]\ => rx_aurora_lane_simplex_v5_1_i_n_16,
      \soft_err_r_reg[2]\ => rx_aurora_lane_simplex_v5_2_i_n_16,
      \soft_err_r_reg[3]\ => rx_aurora_lane_simplex_v5_3_i_n_15,
      start_rx_i => start_rx_i,
      user_clk => user_clk
    );
rx_ll_i: entity work.aurora_rx_4l_64b_RX_LL
     port map (
      D(3) => RX_PE_DATA_V,
      D(2) => rx_aurora_lane_simplex_v5_1_i_n_15,
      D(1) => rx_aurora_lane_simplex_v5_2_i_n_15,
      D(0) => rx_aurora_lane_simplex_v5_3_i_n_14,
      FRAME_ERR => FRAME_ERR,
      M_AXI_RX_TDATA(63 downto 0) => M_AXI_RX_TDATA(63 downto 0),
      M_AXI_RX_TLAST => M_AXI_RX_TLAST,
      M_AXI_RX_TVALID => M_AXI_RX_TVALID,
      M_AXI_UFC_RX_TDATA(63 downto 0) => M_AXI_UFC_RX_TDATA(63 downto 0),
      M_AXI_UFC_RX_TLAST => M_AXI_UFC_RX_TLAST,
      M_AXI_UFC_RX_TVALID => M_AXI_UFC_RX_TVALID,
      Q(4) => \sym_dec_i/p_0_in_9\(0),
      Q(3) => rx_aurora_lane_simplex_v5_1_i_n_22,
      Q(2) => rx_aurora_lane_simplex_v5_1_i_n_23,
      Q(1) => rx_aurora_lane_simplex_v5_1_i_n_24,
      Q(0) => rx_aurora_lane_simplex_v5_1_i_n_25,
      RESET => RESET_24,
      RX_ECP_Buffer0 => \sym_dec_i/RX_ECP_Buffer0\,
      RX_ECP_Buffer0_3 => \sym_dec_i/RX_ECP_Buffer0_6\,
      RX_ECP_Buffer0_4 => \sym_dec_i/RX_ECP_Buffer0_12\,
      RX_ECP_Buffer0_5 => \sym_dec_i/RX_ECP_Buffer0_18\,
      RX_EOF_N => rx_eof,
      RX_PE_DATA(2) => RX_PE_DATA(8),
      RX_PE_DATA(1) => RX_PE_DATA(9),
      RX_PE_DATA(0) => RX_PE_DATA(10),
      \RX_REM_Buffer_reg[0]\(2) => rx_rem(0),
      \RX_REM_Buffer_reg[0]\(1) => rx_rem(1),
      \RX_REM_Buffer_reg[0]\(0) => rx_rem(2),
      UFC_RX_EOF_N => rx_ufc_eof,
      \UFC_RX_REM_Buffer_reg[0]\(1) => rx_ufc_rem(0),
      \UFC_RX_REM_Buffer_reg[0]\(0) => rx_ufc_rem(1),
      neqOp => \ufc_filter_i/neqOp\,
      \rx_scp_r_reg[0]\(3) => RX_SCP,
      \rx_scp_r_reg[0]\(2) => rx_aurora_lane_simplex_v5_1_i_n_11,
      \rx_scp_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_2_i_n_11,
      \rx_scp_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_3_i_n_10,
      \rx_suf_r_reg[0]\(2) => RX_SUF,
      \rx_suf_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_1_i_n_12,
      \rx_suf_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_3_i_n_11,
      \rx_suf_r_reg[2]\(0) => rx_aurora_lane_simplex_v5_2_i_n_12,
      \stage_1_count_value_r_reg[0]\ => rx_aurora_lane_simplex_v5_3_i_n_22,
      \stage_1_count_value_r_reg[1]\ => rx_aurora_lane_simplex_v5_3_i_n_16,
      \stage_1_count_value_r_reg[2]\ => rx_aurora_lane_simplex_v5_3_i_n_17,
      \stage_1_count_value_r_reg[3]\ => rx_aurora_lane_simplex_v5_2_i_n_18,
      \stage_1_data_r_reg[0]\(7) => rx_aurora_lane_simplex_v5_0_i_n_30,
      \stage_1_data_r_reg[0]\(6) => rx_aurora_lane_simplex_v5_0_i_n_31,
      \stage_1_data_r_reg[0]\(5) => rx_aurora_lane_simplex_v5_0_i_n_32,
      \stage_1_data_r_reg[0]\(4) => rx_aurora_lane_simplex_v5_0_i_n_33,
      \stage_1_data_r_reg[0]\(3) => rx_aurora_lane_simplex_v5_0_i_n_34,
      \stage_1_data_r_reg[0]\(2) => rx_aurora_lane_simplex_v5_0_i_n_35,
      \stage_1_data_r_reg[0]\(1) => rx_aurora_lane_simplex_v5_0_i_n_36,
      \stage_1_data_r_reg[0]\(0) => rx_aurora_lane_simplex_v5_0_i_n_37,
      \stage_1_data_r_reg[11]\(4) => \sym_dec_i/p_0_in\(0),
      \stage_1_data_r_reg[11]\(3) => rx_aurora_lane_simplex_v5_0_i_n_26,
      \stage_1_data_r_reg[11]\(2) => rx_aurora_lane_simplex_v5_0_i_n_27,
      \stage_1_data_r_reg[11]\(1) => rx_aurora_lane_simplex_v5_0_i_n_28,
      \stage_1_data_r_reg[11]\(0) => rx_aurora_lane_simplex_v5_0_i_n_29,
      \stage_1_data_r_reg[16]\(7) => rx_aurora_lane_simplex_v5_1_i_n_26,
      \stage_1_data_r_reg[16]\(6) => rx_aurora_lane_simplex_v5_1_i_n_27,
      \stage_1_data_r_reg[16]\(5) => rx_aurora_lane_simplex_v5_1_i_n_28,
      \stage_1_data_r_reg[16]\(4) => rx_aurora_lane_simplex_v5_1_i_n_29,
      \stage_1_data_r_reg[16]\(3) => rx_aurora_lane_simplex_v5_1_i_n_30,
      \stage_1_data_r_reg[16]\(2) => rx_aurora_lane_simplex_v5_1_i_n_31,
      \stage_1_data_r_reg[16]\(1) => rx_aurora_lane_simplex_v5_1_i_n_32,
      \stage_1_data_r_reg[16]\(0) => rx_aurora_lane_simplex_v5_1_i_n_33,
      \stage_1_data_r_reg[24]\ => rx_aurora_lane_simplex_v5_1_i_n_9,
      \stage_1_data_r_reg[25]\ => rx_aurora_lane_simplex_v5_1_i_n_8,
      \stage_1_data_r_reg[26]\ => rx_aurora_lane_simplex_v5_1_i_n_10,
      \stage_1_data_r_reg[32]\(7) => rx_aurora_lane_simplex_v5_2_i_n_24,
      \stage_1_data_r_reg[32]\(6) => rx_aurora_lane_simplex_v5_2_i_n_25,
      \stage_1_data_r_reg[32]\(5) => rx_aurora_lane_simplex_v5_2_i_n_26,
      \stage_1_data_r_reg[32]\(4) => rx_aurora_lane_simplex_v5_2_i_n_27,
      \stage_1_data_r_reg[32]\(3) => rx_aurora_lane_simplex_v5_2_i_n_28,
      \stage_1_data_r_reg[32]\(2) => rx_aurora_lane_simplex_v5_2_i_n_29,
      \stage_1_data_r_reg[32]\(1) => rx_aurora_lane_simplex_v5_2_i_n_30,
      \stage_1_data_r_reg[32]\(0) => rx_aurora_lane_simplex_v5_2_i_n_31,
      \stage_1_data_r_reg[40]\ => rx_aurora_lane_simplex_v5_2_i_n_8,
      \stage_1_data_r_reg[41]\ => rx_aurora_lane_simplex_v5_2_i_n_10,
      \stage_1_data_r_reg[42]\ => rx_aurora_lane_simplex_v5_2_i_n_9,
      \stage_1_data_r_reg[43]\(4) => \sym_dec_i/p_0_in_15\(0),
      \stage_1_data_r_reg[43]\(3) => rx_aurora_lane_simplex_v5_2_i_n_20,
      \stage_1_data_r_reg[43]\(2) => rx_aurora_lane_simplex_v5_2_i_n_21,
      \stage_1_data_r_reg[43]\(1) => rx_aurora_lane_simplex_v5_2_i_n_22,
      \stage_1_data_r_reg[43]\(0) => rx_aurora_lane_simplex_v5_2_i_n_23,
      \stage_1_data_r_reg[48]\(7) => rx_aurora_lane_simplex_v5_3_i_n_28,
      \stage_1_data_r_reg[48]\(6) => rx_aurora_lane_simplex_v5_3_i_n_29,
      \stage_1_data_r_reg[48]\(5) => rx_aurora_lane_simplex_v5_3_i_n_30,
      \stage_1_data_r_reg[48]\(4) => rx_aurora_lane_simplex_v5_3_i_n_31,
      \stage_1_data_r_reg[48]\(3) => rx_aurora_lane_simplex_v5_3_i_n_32,
      \stage_1_data_r_reg[48]\(2) => rx_aurora_lane_simplex_v5_3_i_n_33,
      \stage_1_data_r_reg[48]\(1) => rx_aurora_lane_simplex_v5_3_i_n_34,
      \stage_1_data_r_reg[48]\(0) => rx_aurora_lane_simplex_v5_3_i_n_35,
      \stage_1_data_r_reg[56]\ => rx_aurora_lane_simplex_v5_3_i_n_8,
      \stage_1_data_r_reg[57]\ => rx_aurora_lane_simplex_v5_3_i_n_7,
      \stage_1_data_r_reg[58]\ => rx_aurora_lane_simplex_v5_3_i_n_9,
      \stage_1_data_r_reg[59]\(4) => \sym_dec_i/p_0_in_21\(0),
      \stage_1_data_r_reg[59]\(3) => rx_aurora_lane_simplex_v5_3_i_n_24,
      \stage_1_data_r_reg[59]\(2) => rx_aurora_lane_simplex_v5_3_i_n_25,
      \stage_1_data_r_reg[59]\(1) => rx_aurora_lane_simplex_v5_3_i_n_26,
      \stage_1_data_r_reg[59]\(0) => rx_aurora_lane_simplex_v5_3_i_n_27,
      \stage_1_lane_mask_r_reg[1]\ => rx_global_logic_simplex_i_n_14,
      \stage_1_lane_mask_r_reg[2]\ => rx_aurora_lane_simplex_v5_0_i_n_17,
      \stage_1_lane_mask_r_reg[3]\ => rx_aurora_lane_simplex_v5_0_i_n_19,
      start_rx_i => start_rx_i,
      std_bool26_out => \sym_dec_i/std_bool26_out\,
      std_bool26_out_0 => \sym_dec_i/std_bool26_out_7\,
      std_bool26_out_1 => \sym_dec_i/std_bool26_out_13\,
      std_bool26_out_2 => \sym_dec_i/std_bool26_out_19\,
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity aurora_rx_4l_64b is
  port (
    m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_rx_tvalid : out STD_LOGIC;
    m_axi_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_rx_tlast : out STD_LOGIC;
    m_axi_ufc_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_ufc_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_ufc_rx_tvalid : out STD_LOGIC;
    m_axi_ufc_rx_tlast : out STD_LOGIC;
    rxp : in STD_LOGIC_VECTOR ( 0 to 3 );
    rxn : in STD_LOGIC_VECTOR ( 0 to 3 );
    gt_refclk1 : in STD_LOGIC;
    frame_err : out STD_LOGIC;
    rx_hard_err : out STD_LOGIC;
    soft_err : out STD_LOGIC;
    rx_lane_up : out STD_LOGIC_VECTOR ( 0 to 3 );
    rx_channel_up : out STD_LOGIC;
    user_clk : in STD_LOGIC;
    sync_clk : in STD_LOGIC;
    rx_system_reset : in STD_LOGIC;
    power_down : in STD_LOGIC;
    loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_reset : in STD_LOGIC;
    tx_lock : out STD_LOGIC;
    sys_reset_out : out STD_LOGIC;
    init_clk_in : in STD_LOGIC;
    rx_resetdone_out : out STD_LOGIC;
    link_reset_out : out STD_LOGIC;
    drpclk_in : in STD_LOGIC;
    drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in : in STD_LOGIC;
    drprdy_out : out STD_LOGIC;
    drpwe_in : in STD_LOGIC;
    drpaddr_in_lane1 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in_lane1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out_lane1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in_lane1 : in STD_LOGIC;
    drprdy_out_lane1 : out STD_LOGIC;
    drpwe_in_lane1 : in STD_LOGIC;
    drpaddr_in_lane2 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in_lane2 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out_lane2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in_lane2 : in STD_LOGIC;
    drprdy_out_lane2 : out STD_LOGIC;
    drpwe_in_lane2 : in STD_LOGIC;
    drpaddr_in_lane3 : in STD_LOGIC_VECTOR ( 8 downto 0 );
    drpdi_in_lane3 : in STD_LOGIC_VECTOR ( 15 downto 0 );
    drpdo_out_lane3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    drpen_in_lane3 : in STD_LOGIC;
    drprdy_out_lane3 : out STD_LOGIC;
    drpwe_in_lane3 : in STD_LOGIC;
    gt0_cplllock_out : out STD_LOGIC;
    gt0_rxlpmen_in : in STD_LOGIC;
    gt0_rxcdrovrden_in : in STD_LOGIC;
    gt0_rxdfelpmreset_in : in STD_LOGIC;
    gt0_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt0_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rxcdrhold_in : in STD_LOGIC;
    gt0_eyescanreset_in : in STD_LOGIC;
    gt0_eyescandataerror_out : out STD_LOGIC;
    gt0_eyescantrigger_in : in STD_LOGIC;
    gt0_rxbyteisaligned_out : out STD_LOGIC;
    gt0_rxcommadet_out : out STD_LOGIC;
    gt0_rxprbserr_out : out STD_LOGIC;
    gt0_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_rxprbscntreset_in : in STD_LOGIC;
    gt0_rxpcsreset_in : in STD_LOGIC;
    gt0_rxpmareset_in : in STD_LOGIC;
    gt0_rxpmaresetdone_out : out STD_LOGIC;
    gt0_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt0_rxbufreset_in : in STD_LOGIC;
    gt0_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt0_rx_realign_out : out STD_LOGIC;
    gt0_rx_buf_err_out : out STD_LOGIC;
    gt0_rxresetdone_out : out STD_LOGIC;
    gt0_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_cplllock_out : out STD_LOGIC;
    gt1_rxlpmen_in : in STD_LOGIC;
    gt1_rxcdrovrden_in : in STD_LOGIC;
    gt1_rxdfelpmreset_in : in STD_LOGIC;
    gt1_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt1_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rxcdrhold_in : in STD_LOGIC;
    gt1_eyescanreset_in : in STD_LOGIC;
    gt1_eyescandataerror_out : out STD_LOGIC;
    gt1_eyescantrigger_in : in STD_LOGIC;
    gt1_rxbyteisaligned_out : out STD_LOGIC;
    gt1_rxcommadet_out : out STD_LOGIC;
    gt1_rxprbserr_out : out STD_LOGIC;
    gt1_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt1_rxprbscntreset_in : in STD_LOGIC;
    gt1_rxpcsreset_in : in STD_LOGIC;
    gt1_rxpmareset_in : in STD_LOGIC;
    gt1_rxpmaresetdone_out : out STD_LOGIC;
    gt1_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt1_rxbufreset_in : in STD_LOGIC;
    gt1_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt1_rx_realign_out : out STD_LOGIC;
    gt1_rx_buf_err_out : out STD_LOGIC;
    gt1_rxresetdone_out : out STD_LOGIC;
    gt1_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_cplllock_out : out STD_LOGIC;
    gt2_rxlpmen_in : in STD_LOGIC;
    gt2_rxcdrovrden_in : in STD_LOGIC;
    gt2_rxdfelpmreset_in : in STD_LOGIC;
    gt2_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt2_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rxcdrhold_in : in STD_LOGIC;
    gt2_eyescanreset_in : in STD_LOGIC;
    gt2_eyescandataerror_out : out STD_LOGIC;
    gt2_eyescantrigger_in : in STD_LOGIC;
    gt2_rxbyteisaligned_out : out STD_LOGIC;
    gt2_rxcommadet_out : out STD_LOGIC;
    gt2_rxprbserr_out : out STD_LOGIC;
    gt2_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt2_rxprbscntreset_in : in STD_LOGIC;
    gt2_rxpcsreset_in : in STD_LOGIC;
    gt2_rxpmareset_in : in STD_LOGIC;
    gt2_rxpmaresetdone_out : out STD_LOGIC;
    gt2_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt2_rxbufreset_in : in STD_LOGIC;
    gt2_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt2_rx_realign_out : out STD_LOGIC;
    gt2_rx_buf_err_out : out STD_LOGIC;
    gt2_rxresetdone_out : out STD_LOGIC;
    gt2_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_cplllock_out : out STD_LOGIC;
    gt3_rxlpmen_in : in STD_LOGIC;
    gt3_rxcdrovrden_in : in STD_LOGIC;
    gt3_rxdfelpmreset_in : in STD_LOGIC;
    gt3_rxmonitorout_out : out STD_LOGIC_VECTOR ( 6 downto 0 );
    gt3_rxmonitorsel_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rxcdrhold_in : in STD_LOGIC;
    gt3_eyescanreset_in : in STD_LOGIC;
    gt3_eyescandataerror_out : out STD_LOGIC;
    gt3_eyescantrigger_in : in STD_LOGIC;
    gt3_rxbyteisaligned_out : out STD_LOGIC;
    gt3_rxcommadet_out : out STD_LOGIC;
    gt3_rxprbserr_out : out STD_LOGIC;
    gt3_rxprbssel_in : in STD_LOGIC_VECTOR ( 2 downto 0 );
    gt3_rxprbscntreset_in : in STD_LOGIC;
    gt3_rxpcsreset_in : in STD_LOGIC;
    gt3_rxpmareset_in : in STD_LOGIC;
    gt3_rxpmaresetdone_out : out STD_LOGIC;
    gt3_dmonitorout_out : out STD_LOGIC_VECTOR ( 14 downto 0 );
    gt3_rxbufreset_in : in STD_LOGIC;
    gt3_rx_disp_err_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_not_in_table_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt3_rx_realign_out : out STD_LOGIC;
    gt3_rx_buf_err_out : out STD_LOGIC;
    gt3_rxresetdone_out : out STD_LOGIC;
    gt3_rxbufstatus_out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt0_qplllock_in : in STD_LOGIC;
    gt0_qpllrefclklost_in : in STD_LOGIC;
    gt0_qpllreset_out : out STD_LOGIC;
    gt1_qplllock_in : in STD_LOGIC;
    gt1_qpllrefclklost_in : in STD_LOGIC;
    gt1_qpllreset_out : out STD_LOGIC;
    gt_qpllclk_quad2_in : in STD_LOGIC;
    gt_qpllrefclk_quad2_in : in STD_LOGIC;
    gt_qpllclk_quad3_in : in STD_LOGIC;
    gt_qpllrefclk_quad3_in : in STD_LOGIC;
    tx_out_clk : out STD_LOGIC;
    pll_not_locked : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of aurora_rx_4l_64b : entity is true;
end aurora_rx_4l_64b;

architecture STRUCTURE of aurora_rx_4l_64b is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^m_axi_rx_tkeep\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \^m_axi_ufc_rx_tkeep\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal NLW_U0_gt0_qpllreset_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_gt1_qpllreset_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_RX_TKEEP_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_UFC_RX_TKEEP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute EXAMPLE_SIMULATION : integer;
  attribute EXAMPLE_SIMULATION of U0 : label is 0;
  attribute SIM_GTRESET_SPEEDUP : string;
  attribute SIM_GTRESET_SPEEDUP of U0 : label is "FALSE";
begin
  gt0_qpllreset_out <= \<const0>\;
  gt1_qpllreset_out <= \<const0>\;
  m_axi_rx_tkeep(7 downto 1) <= \^m_axi_rx_tkeep\(7 downto 1);
  m_axi_rx_tkeep(0) <= \<const1>\;
  m_axi_ufc_rx_tkeep(7 downto 2) <= \^m_axi_ufc_rx_tkeep\(7 downto 2);
  m_axi_ufc_rx_tkeep(1) <= \<const1>\;
  m_axi_ufc_rx_tkeep(0) <= \<const1>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.aurora_rx_4l_64b_core
     port map (
      DRPADDR_IN(8 downto 0) => drpaddr_in(8 downto 0),
      DRPADDR_IN_LANE1(8 downto 0) => drpaddr_in_lane1(8 downto 0),
      DRPADDR_IN_LANE2(8 downto 0) => drpaddr_in_lane2(8 downto 0),
      DRPADDR_IN_LANE3(8 downto 0) => drpaddr_in_lane3(8 downto 0),
      DRPDI_IN(15 downto 0) => drpdi_in(15 downto 0),
      DRPDI_IN_LANE1(15 downto 0) => drpdi_in_lane1(15 downto 0),
      DRPDI_IN_LANE2(15 downto 0) => drpdi_in_lane2(15 downto 0),
      DRPDI_IN_LANE3(15 downto 0) => drpdi_in_lane3(15 downto 0),
      DRPDO_OUT(15 downto 0) => drpdo_out(15 downto 0),
      DRPDO_OUT_LANE1(15 downto 0) => drpdo_out_lane1(15 downto 0),
      DRPDO_OUT_LANE2(15 downto 0) => drpdo_out_lane2(15 downto 0),
      DRPDO_OUT_LANE3(15 downto 0) => drpdo_out_lane3(15 downto 0),
      DRPEN_IN => drpen_in,
      DRPEN_IN_LANE1 => drpen_in_lane1,
      DRPEN_IN_LANE2 => drpen_in_lane2,
      DRPEN_IN_LANE3 => drpen_in_lane3,
      DRPRDY_OUT => drprdy_out,
      DRPRDY_OUT_LANE1 => drprdy_out_lane1,
      DRPRDY_OUT_LANE2 => drprdy_out_lane2,
      DRPRDY_OUT_LANE3 => drprdy_out_lane3,
      DRPWE_IN => drpwe_in,
      DRPWE_IN_LANE1 => drpwe_in_lane1,
      DRPWE_IN_LANE2 => drpwe_in_lane2,
      DRPWE_IN_LANE3 => drpwe_in_lane3,
      FRAME_ERR => frame_err,
      GT_RESET => gt_reset,
      LINK_RESET_OUT => link_reset_out,
      LOOPBACK(2 downto 0) => loopback(2 downto 0),
      M_AXI_RX_TDATA(63 downto 0) => m_axi_rx_tdata(63 downto 0),
      M_AXI_RX_TKEEP(7 downto 1) => \^m_axi_rx_tkeep\(7 downto 1),
      M_AXI_RX_TKEEP(0) => NLW_U0_M_AXI_RX_TKEEP_UNCONNECTED(0),
      M_AXI_RX_TLAST => m_axi_rx_tlast,
      M_AXI_RX_TVALID => m_axi_rx_tvalid,
      M_AXI_UFC_RX_TDATA(63 downto 0) => m_axi_ufc_rx_tdata(63 downto 0),
      M_AXI_UFC_RX_TKEEP(7 downto 2) => \^m_axi_ufc_rx_tkeep\(7 downto 2),
      M_AXI_UFC_RX_TKEEP(1 downto 0) => NLW_U0_M_AXI_UFC_RX_TKEEP_UNCONNECTED(1 downto 0),
      M_AXI_UFC_RX_TLAST => m_axi_ufc_rx_tlast,
      M_AXI_UFC_RX_TVALID => m_axi_ufc_rx_tvalid,
      PLL_NOT_LOCKED => '0',
      POWER_DOWN => power_down,
      RXN(0 to 3) => rxn(0 to 3),
      RXP(0 to 3) => rxp(0 to 3),
      RX_CHANNEL_UP => rx_channel_up,
      RX_HARD_ERR => rx_hard_err,
      RX_LANE_UP(0 to 3) => rx_lane_up(0 to 3),
      RX_RESETDONE_OUT => rx_resetdone_out,
      RX_SYSTEM_RESET => rx_system_reset,
      SOFT_ERR => soft_err,
      TX_LOCK => tx_lock,
      TX_OUT_CLK => tx_out_clk,
      drpclk_in => drpclk_in,
      gt0_cplllock_out => gt0_cplllock_out,
      gt0_dmonitorout_out(14 downto 0) => gt0_dmonitorout_out(14 downto 0),
      gt0_eyescandataerror_out => gt0_eyescandataerror_out,
      gt0_eyescanreset_in => gt0_eyescanreset_in,
      gt0_eyescantrigger_in => gt0_eyescantrigger_in,
      gt0_qplllock_in => '0',
      gt0_qpllrefclklost_in => '0',
      gt0_qpllreset_out => NLW_U0_gt0_qpllreset_out_UNCONNECTED,
      gt0_rx_buf_err_out => gt0_rx_buf_err_out,
      gt0_rx_disp_err_out(1 downto 0) => gt0_rx_disp_err_out(1 downto 0),
      gt0_rx_not_in_table_out(1 downto 0) => gt0_rx_not_in_table_out(1 downto 0),
      gt0_rx_realign_out => gt0_rx_realign_out,
      gt0_rxbufreset_in => gt0_rxbufreset_in,
      gt0_rxbufstatus_out(2 downto 0) => gt0_rxbufstatus_out(2 downto 0),
      gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
      gt0_rxcdrhold_in => gt0_rxcdrhold_in,
      gt0_rxcdrovrden_in => gt0_rxcdrovrden_in,
      gt0_rxcommadet_out => gt0_rxcommadet_out,
      gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
      gt0_rxlpmen_in => gt0_rxlpmen_in,
      gt0_rxmonitorout_out(6 downto 0) => gt0_rxmonitorout_out(6 downto 0),
      gt0_rxmonitorsel_in(1 downto 0) => gt0_rxmonitorsel_in(1 downto 0),
      gt0_rxpcsreset_in => gt0_rxpcsreset_in,
      gt0_rxpmareset_in => gt0_rxpmareset_in,
      gt0_rxpmaresetdone_out => gt0_rxpmaresetdone_out,
      gt0_rxprbscntreset_in => gt0_rxprbscntreset_in,
      gt0_rxprbserr_out => gt0_rxprbserr_out,
      gt0_rxprbssel_in(2 downto 0) => gt0_rxprbssel_in(2 downto 0),
      gt0_rxresetdone_out => gt0_rxresetdone_out,
      gt1_cplllock_out => gt1_cplllock_out,
      gt1_dmonitorout_out(14 downto 0) => gt1_dmonitorout_out(14 downto 0),
      gt1_eyescandataerror_out => gt1_eyescandataerror_out,
      gt1_eyescanreset_in => gt1_eyescanreset_in,
      gt1_eyescantrigger_in => gt1_eyescantrigger_in,
      gt1_qplllock_in => '0',
      gt1_qpllrefclklost_in => '0',
      gt1_qpllreset_out => NLW_U0_gt1_qpllreset_out_UNCONNECTED,
      gt1_rx_buf_err_out => gt1_rx_buf_err_out,
      gt1_rx_disp_err_out(1 downto 0) => gt1_rx_disp_err_out(1 downto 0),
      gt1_rx_not_in_table_out(1 downto 0) => gt1_rx_not_in_table_out(1 downto 0),
      gt1_rx_realign_out => gt1_rx_realign_out,
      gt1_rxbufreset_in => gt1_rxbufreset_in,
      gt1_rxbufstatus_out(2 downto 0) => gt1_rxbufstatus_out(2 downto 0),
      gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
      gt1_rxcdrhold_in => gt1_rxcdrhold_in,
      gt1_rxcdrovrden_in => gt1_rxcdrovrden_in,
      gt1_rxcommadet_out => gt1_rxcommadet_out,
      gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
      gt1_rxlpmen_in => gt1_rxlpmen_in,
      gt1_rxmonitorout_out(6 downto 0) => gt1_rxmonitorout_out(6 downto 0),
      gt1_rxmonitorsel_in(1 downto 0) => gt1_rxmonitorsel_in(1 downto 0),
      gt1_rxpcsreset_in => gt1_rxpcsreset_in,
      gt1_rxpmareset_in => gt1_rxpmareset_in,
      gt1_rxpmaresetdone_out => gt1_rxpmaresetdone_out,
      gt1_rxprbscntreset_in => gt1_rxprbscntreset_in,
      gt1_rxprbserr_out => gt1_rxprbserr_out,
      gt1_rxprbssel_in(2 downto 0) => gt1_rxprbssel_in(2 downto 0),
      gt1_rxresetdone_out => gt1_rxresetdone_out,
      gt2_cplllock_out => gt2_cplllock_out,
      gt2_dmonitorout_out(14 downto 0) => gt2_dmonitorout_out(14 downto 0),
      gt2_eyescandataerror_out => gt2_eyescandataerror_out,
      gt2_eyescanreset_in => gt2_eyescanreset_in,
      gt2_eyescantrigger_in => gt2_eyescantrigger_in,
      gt2_rx_buf_err_out => gt2_rx_buf_err_out,
      gt2_rx_disp_err_out(1 downto 0) => gt2_rx_disp_err_out(1 downto 0),
      gt2_rx_not_in_table_out(1 downto 0) => gt2_rx_not_in_table_out(1 downto 0),
      gt2_rx_realign_out => gt2_rx_realign_out,
      gt2_rxbufreset_in => gt2_rxbufreset_in,
      gt2_rxbufstatus_out(2 downto 0) => gt2_rxbufstatus_out(2 downto 0),
      gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
      gt2_rxcdrhold_in => gt2_rxcdrhold_in,
      gt2_rxcdrovrden_in => gt2_rxcdrovrden_in,
      gt2_rxcommadet_out => gt2_rxcommadet_out,
      gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
      gt2_rxlpmen_in => gt2_rxlpmen_in,
      gt2_rxmonitorout_out(6 downto 0) => gt2_rxmonitorout_out(6 downto 0),
      gt2_rxmonitorsel_in(1 downto 0) => gt2_rxmonitorsel_in(1 downto 0),
      gt2_rxpcsreset_in => gt2_rxpcsreset_in,
      gt2_rxpmareset_in => gt2_rxpmareset_in,
      gt2_rxpmaresetdone_out => gt2_rxpmaresetdone_out,
      gt2_rxprbscntreset_in => gt2_rxprbscntreset_in,
      gt2_rxprbserr_out => gt2_rxprbserr_out,
      gt2_rxprbssel_in(2 downto 0) => gt2_rxprbssel_in(2 downto 0),
      gt2_rxresetdone_out => gt2_rxresetdone_out,
      gt3_cplllock_out => gt3_cplllock_out,
      gt3_dmonitorout_out(14 downto 0) => gt3_dmonitorout_out(14 downto 0),
      gt3_eyescandataerror_out => gt3_eyescandataerror_out,
      gt3_eyescanreset_in => gt3_eyescanreset_in,
      gt3_eyescantrigger_in => gt3_eyescantrigger_in,
      gt3_rx_buf_err_out => gt3_rx_buf_err_out,
      gt3_rx_disp_err_out(1 downto 0) => gt3_rx_disp_err_out(1 downto 0),
      gt3_rx_not_in_table_out(1 downto 0) => gt3_rx_not_in_table_out(1 downto 0),
      gt3_rx_realign_out => gt3_rx_realign_out,
      gt3_rxbufreset_in => gt3_rxbufreset_in,
      gt3_rxbufstatus_out(2 downto 0) => gt3_rxbufstatus_out(2 downto 0),
      gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
      gt3_rxcdrhold_in => gt3_rxcdrhold_in,
      gt3_rxcdrovrden_in => gt3_rxcdrovrden_in,
      gt3_rxcommadet_out => gt3_rxcommadet_out,
      gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
      gt3_rxlpmen_in => gt3_rxlpmen_in,
      gt3_rxmonitorout_out(6 downto 0) => gt3_rxmonitorout_out(6 downto 0),
      gt3_rxmonitorsel_in(1 downto 0) => gt3_rxmonitorsel_in(1 downto 0),
      gt3_rxpcsreset_in => gt3_rxpcsreset_in,
      gt3_rxpmareset_in => gt3_rxpmareset_in,
      gt3_rxpmaresetdone_out => gt3_rxpmaresetdone_out,
      gt3_rxprbscntreset_in => gt3_rxprbscntreset_in,
      gt3_rxprbserr_out => gt3_rxprbserr_out,
      gt3_rxprbssel_in(2 downto 0) => gt3_rxprbssel_in(2 downto 0),
      gt3_rxresetdone_out => gt3_rxresetdone_out,
      gt_qpllclk_quad2_in => gt_qpllclk_quad2_in,
      gt_qpllclk_quad3_in => gt_qpllclk_quad3_in,
      gt_qpllrefclk_quad2_in => gt_qpllrefclk_quad2_in,
      gt_qpllrefclk_quad3_in => gt_qpllrefclk_quad3_in,
      gt_refclk1 => gt_refclk1,
      init_clk_in => init_clk_in,
      sync_clk => sync_clk,
      sys_reset_out => sys_reset_out,
      user_clk => user_clk
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
end STRUCTURE;
