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--
--  UFC_BARREL_SHIFTER_CONTROL
--
--
--
--  Description: this module controls the UFC barrel shifter
--
--               This module supports 4 2-byte lane designs
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL is

    port (

            UFC_MESSAGE_START      : in std_logic_vector(0 to 3);
            USER_CLK               : in std_logic;
            BARREL_SHIFTER_CONTROL : out std_logic_vector(0 to 2)

         );

end aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL;

architecture RTL of aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL is

-- Parameter Declarations --

    constant DLY : time := 1 ns;

-- External Register Declarations

    signal BARREL_SHIFTER_CONTROL_Buffer : std_logic_vector(0 to 2);

-- Internal Register Declarations --

    signal  barrel_shifter_control_i : std_logic_vector(0 to 2);

begin

    BARREL_SHIFTER_CONTROL <= BARREL_SHIFTER_CONTROL_Buffer;

-- Main Body of Code --

    -- Control for barrel shifting --

    -- Generate a barrel shift control number, which indicates how far to the left all the
    -- lane data should be shifted.

    process (UFC_MESSAGE_START)

    begin

        if (UFC_MESSAGE_START(0) = '1') then

            barrel_shifter_control_i <= conv_std_logic_vector(1,3);

        elsif (UFC_MESSAGE_START(1) = '1') then

            barrel_shifter_control_i <= conv_std_logic_vector(2,3);

        elsif (UFC_MESSAGE_START(2) = '1') then

            barrel_shifter_control_i <= conv_std_logic_vector(3,3);

        else

            barrel_shifter_control_i <= (others => '0');

        end if;

    end process;


    -- Register the barrel shifter control number

    process(USER_CLK)

    begin

        if (USER_CLK 'event and USER_CLK = '1') then

            BARREL_SHIFTER_CONTROL_Buffer <= barrel_shifter_control_i after DLY;

        end if;

    end process;

end RTL;
