-----------------------------------------------------------------------
-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
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-- (including loss of data, profits, goodwill, or any type of
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------------------------------------------------------------------------------------
--  aurora_rx_4l_64b
--
--
--  Description: This is the top level module for a 4 2-byte lane
--               Simplex Aurora reference design module.
--
--               This module is a Simplex RX module. All GTs are only used for
--               receiving.
--               This module supports the following features:
--
--               * User Flow Control
--               * Supports GT
------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on

entity aurora_rx_4l_64b_core is
   generic(
          SIM_GTRESET_SPEEDUP : string  :=   "FALSE";
          EXAMPLE_SIMULATION  : integer :=  0      
          );
    port  (

    -- RX Stream Interface
M_AXI_RX_TDATA         : out std_logic_vector(63 downto 0);
M_AXI_RX_TKEEP         : out std_logic_vector(7 downto 0);
            M_AXI_RX_TVALID        : out std_logic;
            M_AXI_RX_TLAST         : out std_logic;

    -- User Flow Control RX Inteface

M_AXI_UFC_RX_TDATA     : out std_logic_vector(63 downto 0);
M_AXI_UFC_RX_TKEEP     : out std_logic_vector(7 downto 0);
            M_AXI_UFC_RX_TVALID    : out std_logic;
            M_AXI_UFC_RX_TLAST     : out std_logic;

    -- GT Serial I/O

RXP              : in std_logic_vector(0 to 3);
RXN              : in std_logic_vector(0 to 3);

    -- GT Reference Clock Interface

            gt_refclk1    : in std_logic;
    -- Error Detection Interface

            RX_HARD_ERR    : out std_logic;
            SOFT_ERR       : out std_logic;
            FRAME_ERR      : out std_logic;

    -- Status

            RX_CHANNEL_UP    : out std_logic;
RX_LANE_UP       : out std_logic_vector(0 to 3);



    -- System Interface

            user_clk         : in  std_logic;
            sync_clk         : in  std_logic;
            RX_SYSTEM_RESET  : in  std_logic;
            RX_RESETDONE_OUT : out std_logic;
            LINK_RESET_OUT      : out std_logic;  
            POWER_DOWN       : in  std_logic;
            GT_RESET         : in  std_logic;
            TX_LOCK          : out std_logic;
            init_clk_in   : in  std_logic;
            PLL_NOT_LOCKED      : in  std_logic;
drpclk_in                                      : in   std_logic;
DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
DRPDI_IN                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
DRPEN_IN                                : in   std_logic;
DRPRDY_OUT                              : out  std_logic;
DRPWE_IN                                : in   std_logic;
DRPADDR_IN_LANE1                              : in   std_logic_vector(8 downto 0);
DRPDI_IN_LANE1                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE1                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE1                                : in   std_logic;
DRPRDY_OUT_LANE1                              : out  std_logic;
DRPWE_IN_LANE1                                : in   std_logic;
DRPADDR_IN_LANE2                              : in   std_logic_vector(8 downto 0);
DRPDI_IN_LANE2                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE2                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE2                                : in   std_logic;
DRPRDY_OUT_LANE2                              : out  std_logic;
DRPWE_IN_LANE2                                : in   std_logic;
DRPADDR_IN_LANE3                              : in   std_logic_vector(8 downto 0);
DRPDI_IN_LANE3                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE3                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE3                                : in   std_logic;
DRPRDY_OUT_LANE3                              : out  std_logic;
DRPWE_IN_LANE3                                : in   std_logic;
 
            TX_OUT_CLK       : out std_logic;
--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
    ------------------------- Common Block - QPLL Ports ------------------------
      gt1_qplllock_in       :  in  std_logic;
      gt1_qpllrefclklost_in :  in  std_logic;
      gt1_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad2_in    : in  std_logic;
   gt_qpllrefclk_quad2_in : in  std_logic;
   gt_qpllclk_quad3_in    : in  std_logic;
   gt_qpllrefclk_quad3_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}

    gt0_cplllock_out                            : out  std_logic;

    gt0_rxlpmen_in                              : in   std_logic;
    gt0_rxcdrovrden_in                          : in   std_logic;
    gt0_rxdfelpmreset_in                        : in   std_logic;
    gt0_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt0_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt0_rxcdrhold_in                            : in   std_logic;
    gt0_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt0_eyescandataerror_out                    : out  std_logic;
    gt0_eyescantrigger_in                       : in   std_logic;
    gt0_rxbyteisaligned_out                     : out  std_logic;
    gt0_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt0_rxprbserr_out                           : out  std_logic;
    gt0_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt0_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt0_rxpcsreset_in                           : in   std_logic;
    gt0_rxpmareset_in                           : in   std_logic;
    gt0_rxpmaresetdone_out                      : out    std_logic;
    gt0_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt0_rxbufreset_in                           : in   std_logic;
    gt0_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt0_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt0_rx_realign_out                          : out  std_logic;
    gt0_rx_buf_err_out                          : out  std_logic;
    gt0_rxresetdone_out                         : out  std_logic;
    gt0_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt1_cplllock_out                            : out  std_logic;

    gt1_rxlpmen_in                              : in   std_logic;
    gt1_rxcdrovrden_in                          : in   std_logic;
    gt1_rxdfelpmreset_in                        : in   std_logic;
    gt1_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt1_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt1_rxcdrhold_in                            : in   std_logic;
    gt1_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt1_eyescandataerror_out                    : out  std_logic;
    gt1_eyescantrigger_in                       : in   std_logic;
    gt1_rxbyteisaligned_out                     : out  std_logic;
    gt1_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt1_rxprbserr_out                           : out  std_logic;
    gt1_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt1_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt1_rxpcsreset_in                           : in   std_logic;
    gt1_rxpmareset_in                           : in   std_logic;
    gt1_rxpmaresetdone_out                      : out    std_logic;
    gt1_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt1_rxbufreset_in                           : in   std_logic;
    gt1_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt1_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt1_rx_realign_out                          : out  std_logic;
    gt1_rx_buf_err_out                          : out  std_logic;
    gt1_rxresetdone_out                         : out  std_logic;
    gt1_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt2_cplllock_out                            : out  std_logic;

    gt2_rxlpmen_in                              : in   std_logic;
    gt2_rxcdrovrden_in                          : in   std_logic;
    gt2_rxdfelpmreset_in                        : in   std_logic;
    gt2_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt2_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt2_rxcdrhold_in                            : in   std_logic;
    gt2_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt2_eyescandataerror_out                    : out  std_logic;
    gt2_eyescantrigger_in                       : in   std_logic;
    gt2_rxbyteisaligned_out                     : out  std_logic;
    gt2_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt2_rxprbserr_out                           : out  std_logic;
    gt2_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt2_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt2_rxpcsreset_in                           : in   std_logic;
    gt2_rxpmareset_in                           : in   std_logic;
    gt2_rxpmaresetdone_out                      : out    std_logic;
    gt2_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt2_rxbufreset_in                           : in   std_logic;
    gt2_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt2_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt2_rx_realign_out                          : out  std_logic;
    gt2_rx_buf_err_out                          : out  std_logic;
    gt2_rxresetdone_out                         : out  std_logic;
    gt2_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt3_cplllock_out                            : out  std_logic;

    gt3_rxlpmen_in                              : in   std_logic;
    gt3_rxcdrovrden_in                          : in   std_logic;
    gt3_rxdfelpmreset_in                        : in   std_logic;
    gt3_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt3_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt3_rxcdrhold_in                            : in   std_logic;
    gt3_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt3_eyescandataerror_out                    : out  std_logic;
    gt3_eyescantrigger_in                       : in   std_logic;
    gt3_rxbyteisaligned_out                     : out  std_logic;
    gt3_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt3_rxprbserr_out                           : out  std_logic;
    gt3_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt3_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt3_rxpcsreset_in                           : in   std_logic;
    gt3_rxpmareset_in                           : in   std_logic;
    gt3_rxpmaresetdone_out                      : out    std_logic;
    gt3_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt3_rxbufreset_in                           : in   std_logic;
    gt3_rx_disp_err_out                         : out  std_logic_vector(1 downto 0);
    gt3_rx_not_in_table_out                     : out  std_logic_vector(1 downto 0);
    gt3_rx_realign_out                          : out  std_logic;
    gt3_rx_buf_err_out                          : out  std_logic;
    gt3_rxresetdone_out                         : out  std_logic;
    gt3_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);

            sys_reset_out   : out std_logic; 
            LOOPBACK         : in  std_logic_vector(2 downto 0)
         );

end aurora_rx_4l_64b_core;

architecture MAPPED of aurora_rx_4l_64b_core is
  attribute core_generation_info           : string;
attribute core_generation_info of MAPPED : architecture is "aurora_rx_4l_64b,aurora_8b10b_v11_1_14,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=right,c_gt_clock_1=GTHQ2,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=4,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=1,c_gt_loc_8=2,c_gt_loc_9=3,c_lane_width=2,c_line_rate=64130,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160325,c_simplex=true,c_simplex_mode=RX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=RX-only_Simplex}";

    -- Parameter Declarations --
    constant DLY : time := 1 ns;
           -- Simplex timer parameters
    constant C_SIMPLEX_TIMER       : integer  := 18;     -- Simplex Timer 
    constant C_ALIGNED_TIMER       : integer  := 158990;  -- Timer to assert TX_ALIGNED signal 
    constant C_BONDED_TIMER        : integer  := C_ALIGNED_TIMER + 4096;  -- Timer to assert TX_BONDED signal 
    constant C_VERIFY_TIMER        : integer  := C_BONDED_TIMER + 512;  -- Timer to assert TX_VERIFY signal 
    constant WATCHDOG_TIMEOUT      : integer := 14;

--*********************************Component Declarations****************************

    component aurora_rx_4l_64b_RESET_LOGIC
    port (
           RESET                  : in std_logic;
           USER_CLK               : in std_logic;
           INIT_CLK_IN            : in std_logic;
           TX_LOCK_IN             : in std_logic;
           PLL_NOT_LOCKED         : in std_logic;
           LINK_RESET_IN          : in std_logic;
           RX_RESETDONE_IN        : in std_logic;
           SYSTEM_RESET           : out std_logic
         );
     end component;

   -- AXI Shim modules
   component aurora_rx_4l_64b_LL_TO_AXI is
   generic
   (
    DATA_WIDTH  : integer :=   16;      -- DATA bus width
    USE_UFC_REM : integer :=   0;       -- UFC REM bus width identifier
    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
    REM_WIDTH   : integer :=   1        -- REM bus width
   );  

   port
   (

    ----------------------  AXI4-S Interface -------------------------------
    AXI4_S_OP_TDATA                 : out   std_logic_vector (DATA_WIDTH-1 downto 0);
    AXI4_S_OP_TKEEP                 : out   std_logic_vector (STRB_WIDTH-1 downto 0);
    AXI4_S_OP_TVALID                : out   std_logic;
    AXI4_S_OP_TLAST                 : out   std_logic;
    AXI4_S_IP_TREADY                : in    std_logic;

    ----------------------  LocalLink Interface ----------------------------
    LL_IP_DATA                      : in    std_logic_vector (0 to DATA_WIDTH-1);
    LL_IP_REM                       : in    std_logic_vector (0 to REM_WIDTH-1);
    LL_IP_SRC_RDY_N                 : in    std_logic;
    LL_IP_SOF_N                     : in    std_logic;
    LL_IP_EOF_N                     : in    std_logic;
    LL_OP_DST_RDY_N                 : out   std_logic

   );
   end component;

   component aurora_rx_4l_64b_AXI_TO_LL is
   generic
   (
    DATA_WIDTH  : integer :=   16;      -- DATA bus width
    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
    REM_WIDTH   : integer :=   1;       -- REM bus width
    USE_4_NFC   : integer :=   0;       --  0 => PDU, 1 => NFC, 2 => UFC
    USE_UFC_REM : integer :=   0        -- UFC REM bus width identifier
   );  

   port
   (

     ----------------------  AXI4-S Interface -------------------------------
     AXI4_S_IP_TX_TDATA              : in    std_logic_vector (DATA_WIDTH-1 downto 0);
     AXI4_S_IP_TX_TKEEP              : in    std_logic_vector (STRB_WIDTH-1 downto 0);
     AXI4_S_IP_TX_TVALID             : in    std_logic;
     AXI4_S_IP_TX_TLAST              : in    std_logic;
     AXI4_S_OP_TX_TREADY             : out   std_logic;

     ----------------------  LocalLink Interface ----------------------------
     LL_OP_DATA                      : out   std_logic_vector (0 to DATA_WIDTH-1);
     LL_OP_REM                       : out   std_logic_vector (0 to REM_WIDTH -1);
     LL_OP_SRC_RDY_N                 : out   std_logic;
     LL_OP_SOF_N                     : out   std_logic;
     LL_OP_EOF_N                     : out   std_logic;
     LL_IP_DST_RDY_N                 : in    std_logic;

     ----------------------  System Interface ----------------------------
     USER_CLK                        : in    std_logic;
     RESET                           : in    std_logic;
     CHANNEL_UP                      : in    std_logic

   );
   end component;
   

  component  aurora_rx_4l_64b_cdc_sync is
    generic (
        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
                                    -- 0 is pulse synch
                                    -- 1 is level synch
                                    -- 2 is ack based level sync
        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
                                    -- 0 is reset not needed 
                                    -- 1 is reset needed 
        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
                                    -- 0 is bus input
                                    -- 1 is single bit input
        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
        C_VECTOR_WIDTH              : integer range 0 to 32 := 32               ;
        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
            -- Vector Data witdth
    );

    port (
        prmry_aclk                  : in  std_logic                             ;               --
        prmry_resetn                : in  std_logic                             ;               --
        prmry_in                    : in  std_logic                             ;               --
        prmry_vect_in               : in  std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
        prmry_ack                   : out std_logic                             ;
                                                                                                --
        scndry_aclk                 : in  std_logic                             ;               --
        scndry_resetn               : in  std_logic                             ;               --
                                                                                                --
        -- Primary to Secondary Clock Crossing                                                  --
        scndry_out                  : out std_logic                             ;               --
                                                                                                --
        scndry_vect_out             : out std_logic_vector                                      --
                                        (C_VECTOR_WIDTH - 1 downto 0)                           --

    );
  end component;

    component FD

    -- synthesis translate_off
        generic (INIT : bit := '0');
    -- synthesis translate_on
        port (
                Q : out std_ulogic;
                C : in  std_ulogic;
                D : in  std_ulogic
             );
    end component;



    component aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5
    generic (
        EXAMPLE_SIMULATION  : integer :=  0      
   
        );
        port (

        -- GT Interface

                RX_DATA           : in std_logic_vector(15 downto 0);  -- 2-byte data bus from the GT.
                RX_NOT_IN_TABLE   : in std_logic_vector(1 downto 0);   -- Invalid 10-bit code was recieved.
                RX_DISP_ERR       : in std_logic_vector(1 downto 0);   -- Disparity error detected on RX interface.
                RX_CHAR_IS_K      : in std_logic_vector(1 downto 0);   -- Indicates which bytes of RX_DATA are control.
                RX_CHAR_IS_COMMA  : in std_logic_vector(1 downto 0);   -- Comma received on given byte.
                RX_STATUS         : in std_logic_vector(5 downto 0);                      -- GT Status and Event bus.
                RX_BUF_ERR        : in std_logic;                      -- Provides one bit of GT Status and Event bus.
                RX_REALIGN        : in std_logic;                      -- SERDES was realigned because of a new comma.
                RX_POLARITY       : out std_logic;                     -- Controls interpreted polarity of serial data inputs.
                V5_RX_RESET       : out std_logic;                     -- Reset RX side of GT logic.
                LINK_RESET_OUT    : out std_logic;                     -- Link reset for hotplug scenerio.
                HPCNT_RESET       : in  std_logic;                     -- Hotplug count reset input.
                INIT_CLK          : in  std_logic;         
                ENA_COMMA_ALIGN   : out std_logic;                     -- Request comma alignment.

        -- RX_LL Interface

                RX_PAD            : out std_logic;                     -- Indicates lane received PAD.
                RX_PE_DATA        : out std_logic_vector(0 to 15);     -- RX data from lane to RX_LL.
                RX_PE_DATA_V      : out std_logic;                     -- RX_PE_DATA is data, not control symbol.
                RX_SCP            : out std_logic;                     -- Indicates lane received SCP.
                RX_ECP            : out std_logic;                     -- Indicates lane received ECP.
                RX_SUF            : out std_logic;                     -- Indicates lane received SUF.
                RX_FC_NB          : out std_logic_vector(0 to 3);      -- Size code for SNF or SUF.
        -- Global Logic Interface

                CHANNEL_UP        : in  std_logic;                     -- Channel is verified and ready
                LANE_UP           : out std_logic;                     -- Lane is ready for bonding and verification.
                SOFT_ERR        : out std_logic;                     -- Soft error detected.
                HARD_ERR        : out std_logic;                     -- Hard error detected.
                CHANNEL_BOND_LOAD : out std_logic;                     -- Channel Bonding done code received.
                GOT_A             : out std_logic_vector(0 to 1);      -- Indicates lane recieved 'A character' bytes.
                GOT_V             : out std_logic;                     -- Verification symbols received.

        -- System Interface

                USER_CLK          : in std_logic;                      -- System clock for all non-GT Aurora Logic.
                RESET             : in std_logic                       -- Reset the lane.
             );
    end component;

    component aurora_rx_4l_64b_GT_WRAPPER
       generic(
          SIM_GTRESET_SPEEDUP : string :=   "FALSE";     -- Set to "true" to speed up sim reset
          EXAMPLE_SIMULATION  : integer :=  0      
              );
        port  (
RXFSM_DATA_VALID                        : in    std_logic; 
--____________________________COMMON PORTS ,_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in       :  in  std_logic;
      gt0_qpllrefclklost_in :  in  std_logic;
      gt0_qpllreset_out     :  out std_logic;
    ------------------------- Common Block - QPLL Ports ------------------------
      gt1_qplllock_in       :  in  std_logic;
      gt1_qpllrefclklost_in :  in  std_logic;
      gt1_qpllreset_out     :  out std_logic;
   gt_qpllclk_quad2_in    : in  std_logic;
   gt_qpllrefclk_quad2_in : in  std_logic;
   gt_qpllclk_quad3_in    : in  std_logic;
   gt_qpllrefclk_quad3_in : in  std_logic;
--____________________________COMMON PORTS _______________________________}

    gt0_txresetdone_out         : out    std_logic;
    gt0_rxresetdone_out         : out    std_logic;
    gt0_rxpmaresetdone_out      : out    std_logic;
    gt0_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt0_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt1_txresetdone_out         : out    std_logic;
    gt1_rxresetdone_out         : out    std_logic;
    gt1_rxpmaresetdone_out      : out    std_logic;
    gt1_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt1_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt2_txresetdone_out         : out    std_logic;
    gt2_rxresetdone_out         : out    std_logic;
    gt2_rxpmaresetdone_out      : out    std_logic;
    gt2_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt2_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);
    gt3_txresetdone_out         : out    std_logic;
    gt3_rxresetdone_out         : out    std_logic;
    gt3_rxpmaresetdone_out      : out    std_logic;
    gt3_txbufstatus_out                         : out  std_logic_vector(1 downto 0);
    gt3_rxbufstatus_out                         : out  std_logic_vector(2 downto 0);


    gt0_rxlpmen_in                              : in   std_logic;
    gt0_rxcdrovrden_in                          : in   std_logic;
    gt0_rxdfelpmreset_in                        : in   std_logic;
    gt0_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt0_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt0_rxcdrhold_in                            : in   std_logic;
    gt0_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt0_eyescandataerror_out                    : out  std_logic;
    gt0_eyescantrigger_in                       : in   std_logic;
    gt0_rxbyteisaligned_out                     : out  std_logic;
    gt0_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt0_rxprbserr_out                           : out  std_logic;
    gt0_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt0_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt0_rxpcsreset_in                           : in   std_logic;
    gt0_rxpmareset_in                           : in   std_logic;
    gt0_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt0_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt0_txprbsforceerr_in                       : in   std_logic;
    gt0_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt0_txpcsreset_in                           : in   std_logic;
    gt0_txinhibit_in                            : in   std_logic;
    gt0_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt0_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt0_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt0_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt0_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt0_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt0_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt0_txpolarity_in                           : in   std_logic;

    gt1_rxlpmen_in                              : in   std_logic;
    gt1_rxcdrovrden_in                          : in   std_logic;
    gt1_rxdfelpmreset_in                        : in   std_logic;
    gt1_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt1_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt1_rxcdrhold_in                            : in   std_logic;
    gt1_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt1_eyescandataerror_out                    : out  std_logic;
    gt1_eyescantrigger_in                       : in   std_logic;
    gt1_rxbyteisaligned_out                     : out  std_logic;
    gt1_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt1_rxprbserr_out                           : out  std_logic;
    gt1_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt1_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt1_rxpcsreset_in                           : in   std_logic;
    gt1_rxpmareset_in                           : in   std_logic;
    gt1_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt1_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt1_txprbsforceerr_in                       : in   std_logic;
    gt1_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt1_txpcsreset_in                           : in   std_logic;
    gt1_txinhibit_in                            : in   std_logic;
    gt1_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt1_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt1_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt1_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt1_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt1_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt1_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt1_txpolarity_in                           : in   std_logic;

    gt2_rxlpmen_in                              : in   std_logic;
    gt2_rxcdrovrden_in                          : in   std_logic;
    gt2_rxdfelpmreset_in                        : in   std_logic;
    gt2_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt2_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt2_rxcdrhold_in                            : in   std_logic;
    gt2_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt2_eyescandataerror_out                    : out  std_logic;
    gt2_eyescantrigger_in                       : in   std_logic;
    gt2_rxbyteisaligned_out                     : out  std_logic;
    gt2_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt2_rxprbserr_out                           : out  std_logic;
    gt2_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt2_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt2_rxpcsreset_in                           : in   std_logic;
    gt2_rxpmareset_in                           : in   std_logic;
    gt2_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt2_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt2_txprbsforceerr_in                       : in   std_logic;
    gt2_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt2_txpcsreset_in                           : in   std_logic;
    gt2_txinhibit_in                            : in   std_logic;
    gt2_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt2_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt2_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt2_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt2_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt2_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt2_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt2_txpolarity_in                           : in   std_logic;

    gt3_rxlpmen_in                              : in   std_logic;
    gt3_rxcdrovrden_in                          : in   std_logic;
    gt3_rxdfelpmreset_in                        : in   std_logic;
    gt3_rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
    gt3_rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
    gt3_rxcdrhold_in                            : in   std_logic;
    gt3_eyescanreset_in                         : in   std_logic;
    -------------------------- RX Margin Analysis Ports ------------------------
    gt3_eyescandataerror_out                    : out  std_logic;
    gt3_eyescantrigger_in                       : in   std_logic;
    gt3_rxbyteisaligned_out                     : out  std_logic;
    gt3_rxcommadet_out                          : out  std_logic;
        ------------------- Receive Ports - Pattern Checker Ports ------------------
    gt3_rxprbserr_out                           : out  std_logic;
    gt3_rxprbssel_in                            : in   std_logic_vector(2 downto 0);
        ------------------- Receive Ports - Pattern Checker ports ------------------
    gt3_rxprbscntreset_in                       : in   std_logic;
        ------------------- Receive Ports - RX Data Path interface -----------------
    gt3_rxpcsreset_in                           : in   std_logic;
    gt3_rxpmareset_in                           : in   std_logic;
    gt3_dmonitorout_out                         : out  std_logic_vector(14 downto 0);
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    gt3_rxbufreset_in                           : in   std_logic;
        ------------------ Transmit Ports - Pattern Generator Ports ----------------
    gt3_txprbsforceerr_in                       : in   std_logic;
    gt3_txprbssel_in                            : in   std_logic_vector(2 downto 0); 
        ------------------- Transmit Ports - TX Data Path interface -----------------
    gt3_txpcsreset_in                           : in   std_logic;
    gt3_txinhibit_in                            : in   std_logic;
    gt3_txpmareset_in                           : in   std_logic;
    ------------------------ TX Configurable Driver Ports ----------------------
    gt3_txpostcursor_in                         : in   std_logic_vector(4 downto 0);
    gt3_txprecursor_in                          : in   std_logic_vector(4 downto 0);
    ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
    gt3_txchardispmode_in                       : in   std_logic_vector(1 downto 0);
    gt3_txchardispval_in                        : in   std_logic_vector(1 downto 0);
    gt3_txdiffctrl_in                           : in   std_logic_vector(3 downto 0);
    gt3_txmaincursor_in                         : in   std_logic_vector(6 downto 0);
    ----------------- Transmit Ports - TX Polarity Control Ports ---------------
    gt3_txpolarity_in                           : in   std_logic;

                -- DRP I/F
DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN                               : in   std_logic;
DRPDI_IN                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
DRPEN_IN                                : in   std_logic;
DRPRDY_OUT                              : out  std_logic;
DRPWE_IN                                : in   std_logic;
DRPADDR_IN_LANE1                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE1                               : in   std_logic;
DRPDI_IN_LANE1                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE1                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE1                                : in   std_logic;
DRPRDY_OUT_LANE1                              : out  std_logic;
DRPWE_IN_LANE1                                : in   std_logic;
DRPADDR_IN_LANE2                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE2                               : in   std_logic;
DRPDI_IN_LANE2                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE2                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE2                                : in   std_logic;
DRPRDY_OUT_LANE2                              : out  std_logic;
DRPWE_IN_LANE2                                : in   std_logic;
DRPADDR_IN_LANE3                              : in   std_logic_vector(8 downto 0);
DRPCLK_IN_LANE3                               : in   std_logic;
DRPDI_IN_LANE3                                : in   std_logic_vector(15 downto 0);
DRPDO_OUT_LANE3                               : out  std_logic_vector(15 downto 0);
DRPEN_IN_LANE3                                : in   std_logic;
DRPRDY_OUT_LANE3                              : out  std_logic;
DRPWE_IN_LANE3                                : in   std_logic;

                INIT_CLK_IN        : in    std_logic;
        	PLL_NOT_LOCKED           : in    std_logic;
        	TX_RESETDONE_OUT         : out   std_logic;
        	RX_RESETDONE_OUT         : out   std_logic;

ENCHANSYNC_IN           : in    std_logic;
ENCHANSYNC_IN_LANE1           : in    std_logic;
ENCHANSYNC_IN_LANE2           : in    std_logic;
ENCHANSYNC_IN_LANE3           : in    std_logic;
ENMCOMMAALIGN_IN        : in    std_logic;
ENMCOMMAALIGN_IN_LANE1        : in    std_logic;
ENMCOMMAALIGN_IN_LANE2        : in    std_logic;
ENMCOMMAALIGN_IN_LANE3        : in    std_logic;
ENPCOMMAALIGN_IN        : in    std_logic;
ENPCOMMAALIGN_IN_LANE1        : in    std_logic;
ENPCOMMAALIGN_IN_LANE2        : in    std_logic;
ENPCOMMAALIGN_IN_LANE3        : in    std_logic;

                REFCLK                  : in    std_logic;
                LOOPBACK_IN             : in    std_logic_vector (2 downto 0);
RXPOLARITY_IN           : in    std_logic;
RXPOLARITY_IN_LANE1           : in    std_logic;
RXPOLARITY_IN_LANE2           : in    std_logic;
RXPOLARITY_IN_LANE3           : in    std_logic;
RXRESET_IN              : in    std_logic;
RXRESET_IN_LANE1              : in    std_logic;
RXRESET_IN_LANE2              : in    std_logic;
RXRESET_IN_LANE3              : in    std_logic;
                RXUSRCLK_IN             : in    std_logic;
                RXUSRCLK2_IN            : in    std_logic;
RX1N_IN                 : in    std_logic;
RX1N_IN_LANE1                 : in    std_logic;
RX1N_IN_LANE2                 : in    std_logic;
RX1N_IN_LANE3                 : in    std_logic;
RX1P_IN                 : in    std_logic;
RX1P_IN_LANE1                 : in    std_logic;
RX1P_IN_LANE2                 : in    std_logic;
RX1P_IN_LANE3                 : in    std_logic;
TXCHARISK_IN            : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE1            : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE2            : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_LANE3            : in    std_logic_vector (1 downto 0);
TXDATA_IN               : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE1               : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE2               : in    std_logic_vector (15 downto 0);
TXDATA_IN_LANE3               : in    std_logic_vector (15 downto 0);
                GTRESET_IN                                     : in    std_logic;
TXRESET_IN              : in    std_logic;
TXRESET_IN_LANE1              : in    std_logic;
TXRESET_IN_LANE2              : in    std_logic;
TXRESET_IN_LANE3              : in    std_logic;
                TXUSRCLK_IN             : in    std_logic;
                TXUSRCLK2_IN            : in    std_logic;
RXBUFERR_OUT            : out   std_logic;
RXBUFERR_OUT_LANE1            : out   std_logic;
RXBUFERR_OUT_LANE2            : out   std_logic;
RXBUFERR_OUT_LANE3            : out   std_logic;
RXCHARISCOMMA_OUT       : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE1       : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE2       : out   std_logic_vector (1 downto 0);
RXCHARISCOMMA_OUT_LANE3       : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT           : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE1           : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE2           : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_LANE3           : out   std_logic_vector (1 downto 0);
RXDATA_OUT              : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE1              : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE2              : out   std_logic_vector (15 downto 0);
RXDATA_OUT_LANE3              : out   std_logic_vector (15 downto 0);
RXDISPERR_OUT           : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE1           : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE2           : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_LANE3           : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT        : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE1        : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE2        : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_LANE3        : out   std_logic_vector (1 downto 0);
RXREALIGN_OUT           : out   std_logic;
RXREALIGN_OUT_LANE1           : out   std_logic;
RXREALIGN_OUT_LANE2           : out   std_logic;
RXREALIGN_OUT_LANE3           : out   std_logic;
CHBONDDONE_OUT          : out   std_logic;
CHBONDDONE_OUT_LANE1          : out   std_logic;
CHBONDDONE_OUT_LANE2          : out   std_logic;
CHBONDDONE_OUT_LANE3          : out   std_logic;
TXBUFERR_OUT            : out   std_logic;
TXBUFERR_OUT_LANE1            : out   std_logic;
TXBUFERR_OUT_LANE2            : out   std_logic;
TXBUFERR_OUT_LANE3            : out   std_logic;
               GTRXRESET_IN            :  in std_logic;

                LINK_RESET_IN          : in std_logic;                     -- Link reset for hotplug scenerio.
PLLLKDET_OUT            : out   std_logic;
PLLLKDET_OUT_LANE1            : out   std_logic;
PLLLKDET_OUT_LANE2            : out   std_logic;
PLLLKDET_OUT_LANE3            : out   std_logic;
TXOUTCLK1_OUT           : out   std_logic;
TXOUTCLK1_OUT_LANE1           : out   std_logic;
TXOUTCLK1_OUT_LANE2           : out   std_logic;
TXOUTCLK1_OUT_LANE3           : out   std_logic;
TX1N_OUT                : out   std_logic;
TX1N_OUT_LANE1                : out   std_logic;
TX1N_OUT_LANE2                : out   std_logic;
TX1N_OUT_LANE3                : out   std_logic;
TX1P_OUT                : out   std_logic;
TX1P_OUT_LANE1                : out   std_logic;
TX1P_OUT_LANE2                : out   std_logic;
TX1P_OUT_LANE3                : out   std_logic;

                POWERDOWN_IN            : in    std_logic

             );
    end component;

    component BUFG
        port (
                O : out STD_ULOGIC;
                I : in STD_ULOGIC
             );
    end component;


    component aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX
generic (
           WATCHDOG_TIMEOUT   : integer := 14
        );
port (
        -- GT Interface

        CH_BOND_DONE       : in std_logic_vector(0 to 3);
        EN_CHAN_SYNC       : out std_logic;

        -- Aurora Lane Interface

        LANE_UP            : in std_logic_vector(0 to 3);
        SOFT_ERR           : in std_logic_vector(0 to 3);
        HARD_ERR           : in std_logic_vector(0 to 3);
        CHANNEL_BOND_LOAD  : in std_logic_vector(0 to 3);
        GOT_A              : in std_logic_vector(0 to 7);
        GOT_V              : in std_logic_vector(0 to 3);
        RESET_LANES        : out std_logic_vector(0 to 3);
        GTRXRESET_OUT         : out std_logic;

        -- Sideband Signal
        RX_ALIGNED         : out std_logic;
        RX_BONDED          : out std_logic;
        RX_VERIFY          : out std_logic;

        -- System Interface

        USER_CLK           : in std_logic;
        RESET              : in std_logic;
        POWER_DOWN         : in std_logic;
        CHANNEL_UP         : out std_logic;
        START_RX           : out std_logic;
        CHANNEL_SOFT_ERR : out std_logic;
        CHANNEL_HARD_ERR : out std_logic
        );
    end component;



    component aurora_rx_4l_64b_RX_LL
        port (
        -- LocalLink PDU Interface

RX_D             : out std_logic_vector(0 to 63);
RX_REM           : out std_logic_vector(0 to 2);
                RX_SRC_RDY_N     : out std_logic;
                RX_SOF_N         : out std_logic;
                RX_EOF_N         : out std_logic;

        -- UFC Interface

UFC_RX_DATA      : out std_logic_vector(0 to 63);
UFC_RX_REM       : out std_logic_vector(0 to 2);
                UFC_RX_SRC_RDY_N : out std_logic;
                UFC_RX_SOF_N     : out std_logic;
                UFC_RX_EOF_N     : out std_logic;
        -- Global Logic Interface

                START_RX         : in std_logic;

        -- Aurora Lane Interface

RX_PAD           : in std_logic_vector(0 to 3);
RX_PE_DATA       : in std_logic_vector(0 to 63);
RX_PE_DATA_V     : in std_logic_vector(0 to 3);
RX_SCP           : in std_logic_vector(0 to 3);
RX_ECP           : in std_logic_vector(0 to 3);
RX_SUF           : in std_logic_vector(0 to 3);
RX_FC_NB         : in std_logic_vector(0 to 15);

        -- Error Interface

                FRAME_ERR      : out std_logic;

        -- System Interface

                USER_CLK         : in std_logic
             );
    end component;


--*********************************Signal Declarations**********************************
signal TX1N_OUT_unused                 : std_logic_vector(0 to 3);
signal TX1P_OUT_unused                 : std_logic_vector(0 to 3);
signal RX1N_IN_unused                  : std_logic_vector(0 to 3);
signal RX1P_IN_unused                  : std_logic_vector(0 to 3);
signal rx_char_is_comma_i_unused        : std_logic_vector(7 downto 0);    
signal rx_char_is_k_i_unused            : std_logic_vector(7 downto 0);    
signal rx_data_i_unused                : std_logic_vector(63 downto 0);    
signal rx_disp_err_i_unused            : std_logic_vector(7 downto 0);    
signal rx_not_in_table_i_unused        : std_logic_vector(7 downto 0);    
signal rx_realign_i_unused             : std_logic_vector(3 downto 0);    
signal ch_bond_done_i_unused           : std_logic_vector(3 downto 0);


signal ch_bond_done_i                   :   std_logic_vector(3 downto 0);
signal ch_bond_done_r1                  :   std_logic_vector(3 downto 0);
signal ch_bond_done_r2                  :   std_logic_vector(3 downto 0);
signal ch_bond_load_not_used_i          :   std_logic_vector(0 to 3);
    signal en_chan_sync_i                   :   std_logic;
signal ena_comma_align_i                :   std_logic_vector(3 downto 0);
signal got_a_i                          :   std_logic_vector(0 to 7);
signal got_v_i                          :   std_logic_vector(0 to 3);
signal gtp_rx_reset_i                   :   std_logic_vector(3 downto 0);
signal gtp_tx_reset_i                   :   std_logic_vector(3 downto 0);
signal open_rx_rec1_clk_i               :   std_logic_vector(3 downto 0);
signal open_rx_rec2_clk_i               :   std_logic_vector(3 downto 0);
signal tx_out_clk_i                     :   std_logic_vector(0 to 3);
signal raw_tx_out_clk_i             :   std_logic_vector(0 to 3);
signal rx_buf_err_i                     :   std_logic_vector(3 downto 0);
   
    signal rx_channel_up_i                  :   std_logic;
signal rx_char_is_comma_i               :   std_logic_vector(7 downto 0);
signal rx_char_is_k_i                   :   std_logic_vector(7 downto 0);
signal rx_clk_cor_cnt_i                 :   std_logic_vector(11 downto 0);
signal rx_data_i                        :   std_logic_vector(63 downto 0);
signal rx_disp_err_i                    :   std_logic_vector(7 downto 0);
signal rx_ecp_i                         :   std_logic_vector(0 to 3);
signal rx_fc_nb_i                       :   std_logic_vector(0 to 15);
signal rx_hard_err_i                  :   std_logic_vector(0 to 3);
signal rx_lane_up_i                     :   std_logic_vector(0 to 3);
signal rx_not_in_table_i                :   std_logic_vector(7 downto 0);
signal rx_pad_i                         :   std_logic_vector(0 to 3);
signal rx_pe_data_i                     :   std_logic_vector(0 to 63);
signal rx_pe_data_v_i                   :   std_logic_vector(0 to 3);
signal rx_polarity_i                    :   std_logic_vector(3 downto 0);
signal rx_realign_i                     :   std_logic_vector(3 downto 0);
signal rx_reset_lanes_i                 :   std_logic_vector(0 to 3);
signal rx_scp_i                         :   std_logic_vector(0 to 3);
signal rx_suf_i                         :   std_logic_vector(0 to 3);
signal rxmclk_out_not_used_i            :   std_logic_vector(0 to 3);
signal rxpcshclkout_not_used_i          :   std_logic_vector(0 to 3);
signal soft_err_i                     :   std_logic_vector(0 to 3);
    signal start_rx_i                       :   std_logic;
    signal tied_to_ground_i                 :   std_logic;
    signal tied_to_ground_vec_i             :   std_logic_vector(47 downto 0);
    signal tied_to_vcc_i                    :   std_logic;
signal tx_buf_err_i                     :   std_logic_vector(3 downto 0);
signal tx_char_is_k_i                   :   std_logic_vector(7 downto 0);
signal tx_data_i                        :   std_logic_vector(63 downto 0);
signal tx_lock_i                        :   std_logic_vector(0 to 3);
signal ch_bond_load_pulse_i             : std_logic_vector(0 to 3);
signal ch_bond_done_dly_i               : std_logic_vector(0 to 3);


signal tied_to_gnd_vec_i        : std_logic_vector(0 to 63);
signal axi_rx_snf               : std_logic_vector(0 to 3);
signal rx_nfc_data              : std_logic_vector(0 to 15);
    -- RX AXI PDU I/F signals
signal rx_data                  : std_logic_vector(0 to 63);
signal rx_rem                   : std_logic_vector(0 to 2);
signal rx_src_rdy               : std_logic;
signal rx_sof                   : std_logic;
signal rx_eof                   : std_logic;
    -- RX AXI UFC I/F signals
signal rx_ufc_data               : std_logic_vector(0 to 63);
signal rx_ufc_rem                : std_logic_vector(0 to 2);
signal rx_ufc_src_rdy            : std_logic;
signal rx_ufc_sof                : std_logic;
signal rx_ufc_eof                : std_logic;
    signal link_reset_lane0_i       : std_logic;
    signal link_reset_lane1_i       : std_logic;
    signal link_reset_lane2_i       : std_logic;
    signal link_reset_lane3_i       : std_logic;
signal link_reset_i             : std_logic;


signal   gtrxreset_i              : std_logic;
signal   system_reset_i           : std_logic;
signal   tx_lock_comb_i           : std_logic;
signal   rx_resetdone_i           : std_logic;
signal   hpcnt_reset_i            : std_logic;
signal   reset_sync_init_clk      : std_logic;
signal   reset_sync_user_clk      : std_logic;
signal   gt_reset_sync_init_clk   : std_logic;

signal  rxfsm_data_valid_r       : std_logic;
signal DO_CC_I            : std_logic;
signal WARN_CC            : std_logic;
begin
--*********************************Main Body of Code**********************************

    -- Tie off constant signals

    tied_to_ground_vec_i        <=  (others => '0');
    tied_to_ground_i            <=  '0';
    tied_to_vcc_i               <=  '1';

    link_reset_i    <=   link_reset_lane0_i or link_reset_lane1_i or link_reset_lane2_i or link_reset_lane3_i ;

    process(user_clk)
    begin
      if(user_clk'event and user_clk='1') then
        rxfsm_data_valid_r   <= AND_REDUCE(rx_lane_up_i) after DLY;
      end if;
    end process;

    LINK_RESET_OUT  <=  link_reset_i;   


    -- Connect global external signals to their internal counterparts

    tx_lock              <=  tx_lock_comb_i;
    sys_reset_out        <=  system_reset_i;


    --GT0
    gt0_rx_disp_err_out        <=  rx_disp_err_i(1 downto 0);
    gt0_rx_not_in_table_out    <=  rx_not_in_table_i(1 downto 0);
    gt0_rx_realign_out         <=  rx_realign_i (0);
    gt0_rx_buf_err_out         <=  rx_buf_err_i (0);
    gt0_cplllock_out           <=  tx_lock_i(0); 

    --GT1
    gt1_rx_disp_err_out        <=  rx_disp_err_i(3 downto 2);
    gt1_rx_not_in_table_out    <=  rx_not_in_table_i(3 downto 2);
    gt1_rx_realign_out         <=  rx_realign_i (1);
    gt1_rx_buf_err_out         <=  rx_buf_err_i (1);
    gt1_cplllock_out           <=  tx_lock_i(1); 

    --GT2
    gt2_rx_disp_err_out        <=  rx_disp_err_i(5 downto 4);
    gt2_rx_not_in_table_out    <=  rx_not_in_table_i(5 downto 4);
    gt2_rx_realign_out         <=  rx_realign_i (2);
    gt2_rx_buf_err_out         <=  rx_buf_err_i (2);
    gt2_cplllock_out           <=  tx_lock_i(2); 

    --GT3
    gt3_rx_disp_err_out        <=  rx_disp_err_i(7 downto 6);
    gt3_rx_not_in_table_out    <=  rx_not_in_table_i(7 downto 6);
    gt3_rx_realign_out         <=  rx_realign_i (3);
    gt3_rx_buf_err_out         <=  rx_buf_err_i (3);
    gt3_cplllock_out           <=  tx_lock_i(3); 



    RX_CHANNEL_UP      <= rx_channel_up_i;
    rx_resetdone_out     <=  rx_resetdone_i;

    --Connect the TXOUTCLK of lane 0 to TX_OUT_CLK
TX_OUT_CLK  <= tx_out_clk_i(2);
   
    -- Connect TX_LOCK to the tx_lock_i from lane 0
    tx_lock_comb_i    <=   AND_REDUCE(tx_lock_i);

 reset_sync_user_clk_cdc_sync : aurora_rx_4l_64b_cdc_sync
   generic map
     (
       c_cdc_type        => 1,   
       c_flop_input      => 0,  
       c_reset_state     => 0,  
       c_single_bit      => 1,  
       c_vector_width    => 2,  
       c_mtbf_stages     => 3 
     )
  port map
     (
       prmry_aclk        => '0'                ,
       prmry_resetn      => '1'                ,
       prmry_in          => RX_SYSTEM_RESET    ,
       prmry_vect_in     => "00"               ,
       scndry_aclk       => user_clk           ,
       scndry_resetn     => '1'                ,
       prmry_ack         => open               ,
       scndry_out        => reset_sync_user_clk,
       scndry_vect_out   => open           
     );

 gt_reset_cdc_sync : aurora_rx_4l_64b_cdc_sync
   generic map
     (
       c_cdc_type        => 1,   
       c_flop_input      => 0,  
       c_reset_state     => 0,  
       c_single_bit      => 1,  
       c_vector_width    => 2,  
       c_mtbf_stages     => 3 
     )
  port map
     (
       prmry_aclk        => '0'                   ,
       prmry_resetn      => '1'                   ,
       prmry_in          => GT_RESET              ,
       prmry_vect_in     => "00"                  ,
       scndry_aclk       => init_clk_in           ,
       scndry_resetn     => '1'                   ,
       prmry_ack         => open                  ,
       scndry_out        => gt_reset_sync_init_clk,
       scndry_vect_out   => open           
     );

    -- RESET_LOGIC instance
    core_reset_logic_i  :  aurora_rx_4l_64b_RESET_LOGIC 
    port map
    (
        RESET                    =>   reset_sync_user_clk,
        USER_CLK                 =>   user_clk,
        INIT_CLK_IN              =>   init_clk_in,
        TX_LOCK_IN               =>   tx_lock_comb_i,
        PLL_NOT_LOCKED           =>   pll_not_locked,
	     RX_RESETDONE_IN          =>   rx_resetdone_i,
        LINK_RESET_IN            =>   link_reset_i,
        SYSTEM_RESET             =>   system_reset_i
    );

 hpcnt_reset_cdc_sync : aurora_rx_4l_64b_cdc_sync
   generic map
     (
       c_cdc_type        => 1,   
       c_flop_input      => 0,  
       c_reset_state     => 0,  
       c_single_bit      => 1,  
       c_vector_width    => 2,  
       c_mtbf_stages     => 3 
     )
  port map
     (
       prmry_aclk        => user_clk           ,
       prmry_resetn      => '1'                ,
       prmry_in          => RX_SYSTEM_RESET    ,
       prmry_vect_in     => "00"               ,
       scndry_aclk       => init_clk_in        ,
       scndry_resetn     => '1'                ,
       prmry_ack         => open               ,
       scndry_out        => reset_sync_init_clk,
       scndry_vect_out   => open           
     );

hpcnt_reset_i <= gt_reset_sync_init_clk or reset_sync_init_clk;

    -- Instantiate RX Lane 0 --

RX_LANE_UP (0) <= rx_lane_up_i (0);

    rx_aurora_lane_simplex_v5_0_i : aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5
    generic map
    (
       EXAMPLE_SIMULATION   => EXAMPLE_SIMULATION
    )        
        port map (

        -- GT Interface

                    RX_DATA           => rx_data_i(15 downto 0),
                    RX_NOT_IN_TABLE   => rx_not_in_table_i(1 downto 0),
                    RX_DISP_ERR       => rx_disp_err_i(1 downto 0),
                    RX_CHAR_IS_K      => rx_char_is_k_i(1 downto 0),
                    RX_CHAR_IS_COMMA  => rx_char_is_comma_i(1 downto 0),
                    RX_STATUS         => tied_to_ground_vec_i(5 downto 0),
                    RX_REALIGN        => rx_realign_i (0),
                    RX_BUF_ERR        => rx_buf_err_i (0),
                    RX_POLARITY       => rx_polarity_i (0),
                    V5_RX_RESET       => gtp_rx_reset_i (0),
                    INIT_CLK          => init_clk_in,
                    LINK_RESET_OUT    => link_reset_lane0_i,
                    HPCNT_RESET       => hpcnt_reset_i,

        -- Comma Detect Phase Align Interface

ENA_COMMA_ALIGN   => ena_comma_align_i (0),

        -- RX_LL Interface

RX_PAD            => rx_pad_i (0),
                    RX_PE_DATA        => rx_pe_data_i(0 to 15),
RX_PE_DATA_V      => rx_pe_data_v_i (0),
RX_SCP            => rx_scp_i (0),
RX_ECP            => rx_ecp_i (0),
RX_SUF            => rx_suf_i (0),
                    RX_FC_NB          => rx_fc_nb_i(0 to 3),

        -- Global Logic Interface

                    CHANNEL_UP        => rx_channel_up_i,
LANE_UP           => rx_lane_up_i (0),
SOFT_ERR        => soft_err_i (0),
HARD_ERR        => rx_hard_err_i (0),
CHANNEL_BOND_LOAD => ch_bond_load_not_used_i (0),
                    GOT_A             => got_a_i(0 to 1),
GOT_V             => got_v_i (0),

        -- System Interface

                    USER_CLK          => user_clk,
RESET             => rx_reset_lanes_i (0)
                 );

    -- Tie off TX signals to the GT

    tx_char_is_k_i(1 downto 0) <= "00";
    tx_data_i(15 downto 0)   <= (others => '0');
gtp_tx_reset_i (0)     <=   '0';



    -- Instantiate RX Lane 1 --

RX_LANE_UP (1) <= rx_lane_up_i (1);

    rx_aurora_lane_simplex_v5_1_i : aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5
    generic map
    (
       EXAMPLE_SIMULATION   => EXAMPLE_SIMULATION
    )        
        port map (

        -- GT Interface

                    RX_DATA           => rx_data_i(31 downto 16),
                    RX_NOT_IN_TABLE   => rx_not_in_table_i(3 downto 2),
                    RX_DISP_ERR       => rx_disp_err_i(3 downto 2),
                    RX_CHAR_IS_K      => rx_char_is_k_i(3 downto 2),
                    RX_CHAR_IS_COMMA  => rx_char_is_comma_i(3 downto 2),
                    RX_STATUS         => tied_to_ground_vec_i(5 downto 0),
                    RX_REALIGN        => rx_realign_i (1),
                    RX_BUF_ERR        => rx_buf_err_i (1),
                    RX_POLARITY       => rx_polarity_i (1),
                    V5_RX_RESET       => gtp_rx_reset_i (1),
                    INIT_CLK          => init_clk_in,
                    LINK_RESET_OUT    => link_reset_lane1_i,
                    HPCNT_RESET       => hpcnt_reset_i,

        -- Comma Detect Phase Align Interface

ENA_COMMA_ALIGN   => ena_comma_align_i (1),

        -- RX_LL Interface

RX_PAD            => rx_pad_i (1),
                    RX_PE_DATA        => rx_pe_data_i(16 to 31),
RX_PE_DATA_V      => rx_pe_data_v_i (1),
RX_SCP            => rx_scp_i (1),
RX_ECP            => rx_ecp_i (1),
RX_SUF            => rx_suf_i (1),
                    RX_FC_NB          => rx_fc_nb_i(4 to 7),

        -- Global Logic Interface

                    CHANNEL_UP        => rx_channel_up_i,
LANE_UP           => rx_lane_up_i (1),
SOFT_ERR        => soft_err_i (1),
HARD_ERR        => rx_hard_err_i (1),
CHANNEL_BOND_LOAD => ch_bond_load_not_used_i (1),
                    GOT_A             => got_a_i(2 to 3),
GOT_V             => got_v_i (1),

        -- System Interface

                    USER_CLK          => user_clk,
RESET             => rx_reset_lanes_i (1)
                 );

    -- Tie off TX signals to the GT

    tx_char_is_k_i(3 downto 2) <= "00";
    tx_data_i(31 downto 16)   <= (others => '0');
gtp_tx_reset_i (1)     <=   '0';



    -- Instantiate RX Lane 2 --

RX_LANE_UP (2) <= rx_lane_up_i (2);

    rx_aurora_lane_simplex_v5_2_i : aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5
    generic map
    (
       EXAMPLE_SIMULATION   => EXAMPLE_SIMULATION
    )        
        port map (

        -- GT Interface

                    RX_DATA           => rx_data_i(47 downto 32),
                    RX_NOT_IN_TABLE   => rx_not_in_table_i(5 downto 4),
                    RX_DISP_ERR       => rx_disp_err_i(5 downto 4),
                    RX_CHAR_IS_K      => rx_char_is_k_i(5 downto 4),
                    RX_CHAR_IS_COMMA  => rx_char_is_comma_i(5 downto 4),
                    RX_STATUS         => tied_to_ground_vec_i(5 downto 0),
                    RX_REALIGN        => rx_realign_i (2),
                    RX_BUF_ERR        => rx_buf_err_i (2),
                    RX_POLARITY       => rx_polarity_i (2),
                    V5_RX_RESET       => gtp_rx_reset_i (2),
                    INIT_CLK          => init_clk_in,
                    LINK_RESET_OUT    => link_reset_lane2_i,
                    HPCNT_RESET       => hpcnt_reset_i,

        -- Comma Detect Phase Align Interface

ENA_COMMA_ALIGN   => ena_comma_align_i (2),

        -- RX_LL Interface

RX_PAD            => rx_pad_i (2),
                    RX_PE_DATA        => rx_pe_data_i(32 to 47),
RX_PE_DATA_V      => rx_pe_data_v_i (2),
RX_SCP            => rx_scp_i (2),
RX_ECP            => rx_ecp_i (2),
RX_SUF            => rx_suf_i (2),
                    RX_FC_NB          => rx_fc_nb_i(8 to 11),

        -- Global Logic Interface

                    CHANNEL_UP        => rx_channel_up_i,
LANE_UP           => rx_lane_up_i (2),
SOFT_ERR        => soft_err_i (2),
HARD_ERR        => rx_hard_err_i (2),
CHANNEL_BOND_LOAD => ch_bond_load_not_used_i (2),
                    GOT_A             => got_a_i(4 to 5),
GOT_V             => got_v_i (2),

        -- System Interface

                    USER_CLK          => user_clk,
RESET             => rx_reset_lanes_i (2)
                 );

    -- Tie off TX signals to the GT

    tx_char_is_k_i(5 downto 4) <= "00";
    tx_data_i(47 downto 32)   <= (others => '0');
gtp_tx_reset_i (2)     <=   '0';



    -- Instantiate RX Lane 3 --

RX_LANE_UP (3) <= rx_lane_up_i (3);

    rx_aurora_lane_simplex_v5_3_i : aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5
    generic map
    (
       EXAMPLE_SIMULATION   => EXAMPLE_SIMULATION
    )        
        port map (

        -- GT Interface

                    RX_DATA           => rx_data_i(63 downto 48),
                    RX_NOT_IN_TABLE   => rx_not_in_table_i(7 downto 6),
                    RX_DISP_ERR       => rx_disp_err_i(7 downto 6),
                    RX_CHAR_IS_K      => rx_char_is_k_i(7 downto 6),
                    RX_CHAR_IS_COMMA  => rx_char_is_comma_i(7 downto 6),
                    RX_STATUS         => tied_to_ground_vec_i(5 downto 0),
                    RX_REALIGN        => rx_realign_i (3),
                    RX_BUF_ERR        => rx_buf_err_i (3),
                    RX_POLARITY       => rx_polarity_i (3),
                    V5_RX_RESET       => gtp_rx_reset_i (3),
                    INIT_CLK          => init_clk_in,
                    LINK_RESET_OUT    => link_reset_lane3_i,
                    HPCNT_RESET       => hpcnt_reset_i,

        -- Comma Detect Phase Align Interface

ENA_COMMA_ALIGN   => ena_comma_align_i (3),

        -- RX_LL Interface

RX_PAD            => rx_pad_i (3),
                    RX_PE_DATA        => rx_pe_data_i(48 to 63),
RX_PE_DATA_V      => rx_pe_data_v_i (3),
RX_SCP            => rx_scp_i (3),
RX_ECP            => rx_ecp_i (3),
RX_SUF            => rx_suf_i (3),
                    RX_FC_NB          => rx_fc_nb_i(12 to 15),

        -- Global Logic Interface

                    CHANNEL_UP        => rx_channel_up_i,
LANE_UP           => rx_lane_up_i (3),
SOFT_ERR        => soft_err_i (3),
HARD_ERR        => rx_hard_err_i (3),
CHANNEL_BOND_LOAD => ch_bond_load_not_used_i (3),
                    GOT_A             => got_a_i(6 to 7),
GOT_V             => got_v_i (3),

        -- System Interface

                    USER_CLK          => user_clk,
RESET             => rx_reset_lanes_i (3)
                 );

    -- Tie off TX signals to the GT

    tx_char_is_k_i(7 downto 6) <= "00";
    tx_data_i(63 downto 48)   <= (others => '0');
gtp_tx_reset_i (3)     <=   '0';


    gt_wrapper_i : aurora_rx_4l_64b_GT_WRAPPER
        generic map(
                     SIM_GTRESET_SPEEDUP  => SIM_GTRESET_SPEEDUP,
                     EXAMPLE_SIMULATION          => EXAMPLE_SIMULATION
                   )
        port map   (
--____________________________COMMON PORTS INST_______________________________{
    ------------------------- Common Block - QPLL Ports ------------------------
      gt0_qplllock_in        =>  gt0_qplllock_in,
      gt0_qpllrefclklost_in  =>  gt0_qpllrefclklost_in,
      gt0_qpllreset_out      =>  gt0_qpllreset_out,
    ------------------------- Common Block - QPLL Ports ------------------------
      gt1_qplllock_in        =>  gt1_qplllock_in,
      gt1_qpllrefclklost_in  =>  gt1_qpllrefclklost_in,
      gt1_qpllreset_out      =>  gt1_qpllreset_out,
        gt_qpllclk_quad2_in     => gt_qpllclk_quad2_in    ,
        gt_qpllrefclk_quad2_in  => gt_qpllrefclk_quad2_in ,
        gt_qpllclk_quad3_in     => gt_qpllclk_quad3_in    ,
        gt_qpllrefclk_quad3_in  => gt_qpllrefclk_quad3_in ,
--____________________________COMMON PORTS INST_______________________________}

       ------------------------ TX Configurable Driver Ports ----------------------
        gt0_txpostcursor_in        => "00000",
        gt0_txprecursor_in         => "00000",
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
        gt0_txchardispmode_in      => "00",
        gt0_txchardispval_in       => "00",
        gt0_txdiffctrl_in          => "1000",
        gt0_txmaincursor_in        => "0000000",
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
        gt0_txpolarity_in          => '0',

        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt0_txprbsforceerr_in      => tied_to_ground_i,
        gt0_txprbssel_in           => "000",
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt0_txpcsreset_in          => tied_to_ground_i,
        gt0_txinhibit_in           => tied_to_ground_i,
        gt0_txpmareset_in          => tied_to_ground_i,
        gt0_txresetdone_out        => open,
        gt0_txbufstatus_out             => open,
        gt0_rxbufstatus_out             => gt0_rxbufstatus_out,

        gt0_rxresetdone_out        => gt0_rxresetdone_out,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt0_eyescanreset_in                => gt0_eyescanreset_in,
         gt0_eyescandataerror_out           => gt0_eyescandataerror_out,
         gt0_eyescantrigger_in              => gt0_eyescantrigger_in,

         gt0_rxlpmen_in                     => gt0_rxlpmen_in,
         gt0_rxcdrovrden_in                 => gt0_rxcdrovrden_in,
         gt0_rxdfelpmreset_in               => gt0_rxdfelpmreset_in,
         gt0_rxmonitorout_out               => gt0_rxmonitorout_out,
         gt0_rxmonitorsel_in                => gt0_rxmonitorsel_in,
         gt0_rxcdrhold_in                   => gt0_rxcdrhold_in,

         gt0_rxbyteisaligned_out            => gt0_rxbyteisaligned_out,
         gt0_rxcommadet_out                 => gt0_rxcommadet_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt0_rxprbserr_out               => gt0_rxprbserr_out,
        gt0_rxprbssel_in                => gt0_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt0_rxprbscntreset_in           => gt0_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt0_rxpcsreset_in               => gt0_rxpcsreset_in,
        gt0_rxpmareset_in               => gt0_rxpmareset_in,
        gt0_dmonitorout_out             => gt0_dmonitorout_out,
        gt0_rxpmaresetdone_out          => gt0_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt0_rxbufreset_in               => gt0_rxbufreset_in,

       ------------------------ TX Configurable Driver Ports ----------------------
        gt1_txpostcursor_in        => "00000",
        gt1_txprecursor_in         => "00000",
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
        gt1_txchardispmode_in      => "00",
        gt1_txchardispval_in       => "00",
        gt1_txdiffctrl_in          => "1000",
        gt1_txmaincursor_in        => "0000000",
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
        gt1_txpolarity_in          => '0',

        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt1_txprbsforceerr_in      => tied_to_ground_i,
        gt1_txprbssel_in           => "000",
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt1_txpcsreset_in          => tied_to_ground_i,
        gt1_txinhibit_in           => tied_to_ground_i,
        gt1_txpmareset_in          => tied_to_ground_i,
        gt1_txresetdone_out        => open,
        gt1_txbufstatus_out             => open,
        gt1_rxbufstatus_out             => gt1_rxbufstatus_out,

        gt1_rxresetdone_out        => gt1_rxresetdone_out,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt1_eyescanreset_in                => gt1_eyescanreset_in,
         gt1_eyescandataerror_out           => gt1_eyescandataerror_out,
         gt1_eyescantrigger_in              => gt1_eyescantrigger_in,

         gt1_rxlpmen_in                     => gt1_rxlpmen_in,
         gt1_rxcdrovrden_in                 => gt1_rxcdrovrden_in,
         gt1_rxdfelpmreset_in               => gt1_rxdfelpmreset_in,
         gt1_rxmonitorout_out               => gt1_rxmonitorout_out,
         gt1_rxmonitorsel_in                => gt1_rxmonitorsel_in,
         gt1_rxcdrhold_in                   => gt1_rxcdrhold_in,

         gt1_rxbyteisaligned_out            => gt1_rxbyteisaligned_out,
         gt1_rxcommadet_out                 => gt1_rxcommadet_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt1_rxprbserr_out               => gt1_rxprbserr_out,
        gt1_rxprbssel_in                => gt1_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt1_rxprbscntreset_in           => gt1_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt1_rxpcsreset_in               => gt1_rxpcsreset_in,
        gt1_rxpmareset_in               => gt1_rxpmareset_in,
        gt1_dmonitorout_out             => gt1_dmonitorout_out,
        gt1_rxpmaresetdone_out          => gt1_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt1_rxbufreset_in               => gt1_rxbufreset_in,

       ------------------------ TX Configurable Driver Ports ----------------------
        gt2_txpostcursor_in        => "00000",
        gt2_txprecursor_in         => "00000",
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
        gt2_txchardispmode_in      => "00",
        gt2_txchardispval_in       => "00",
        gt2_txdiffctrl_in          => "1000",
        gt2_txmaincursor_in        => "0000000",
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
        gt2_txpolarity_in          => '0',

        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt2_txprbsforceerr_in      => tied_to_ground_i,
        gt2_txprbssel_in           => "000",
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt2_txpcsreset_in          => tied_to_ground_i,
        gt2_txinhibit_in           => tied_to_ground_i,
        gt2_txpmareset_in          => tied_to_ground_i,
        gt2_txresetdone_out        => open,
        gt2_txbufstatus_out             => open,
        gt2_rxbufstatus_out             => gt2_rxbufstatus_out,

        gt2_rxresetdone_out        => gt2_rxresetdone_out,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt2_eyescanreset_in                => gt2_eyescanreset_in,
         gt2_eyescandataerror_out           => gt2_eyescandataerror_out,
         gt2_eyescantrigger_in              => gt2_eyescantrigger_in,

         gt2_rxlpmen_in                     => gt2_rxlpmen_in,
         gt2_rxcdrovrden_in                 => gt2_rxcdrovrden_in,
         gt2_rxdfelpmreset_in               => gt2_rxdfelpmreset_in,
         gt2_rxmonitorout_out               => gt2_rxmonitorout_out,
         gt2_rxmonitorsel_in                => gt2_rxmonitorsel_in,
         gt2_rxcdrhold_in                   => gt2_rxcdrhold_in,

         gt2_rxbyteisaligned_out            => gt2_rxbyteisaligned_out,
         gt2_rxcommadet_out                 => gt2_rxcommadet_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt2_rxprbserr_out               => gt2_rxprbserr_out,
        gt2_rxprbssel_in                => gt2_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt2_rxprbscntreset_in           => gt2_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt2_rxpcsreset_in               => gt2_rxpcsreset_in,
        gt2_rxpmareset_in               => gt2_rxpmareset_in,
        gt2_dmonitorout_out             => gt2_dmonitorout_out,
        gt2_rxpmaresetdone_out          => gt2_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt2_rxbufreset_in               => gt2_rxbufreset_in,

       ------------------------ TX Configurable Driver Ports ----------------------
        gt3_txpostcursor_in        => "00000",
        gt3_txprecursor_in         => "00000",
        ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
        gt3_txchardispmode_in      => "00",
        gt3_txchardispval_in       => "00",
        gt3_txdiffctrl_in          => "1000",
        gt3_txmaincursor_in        => "0000000",
        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
        gt3_txpolarity_in          => '0',

        ------------------ Transmit Ports - Pattern Generator Ports ----------------
        gt3_txprbsforceerr_in      => tied_to_ground_i,
        gt3_txprbssel_in           => "000",
        ------------------- Transmit Ports - TX Data Path interface -----------------
        gt3_txpcsreset_in          => tied_to_ground_i,
        gt3_txinhibit_in           => tied_to_ground_i,
        gt3_txpmareset_in          => tied_to_ground_i,
        gt3_txresetdone_out        => open,
        gt3_txbufstatus_out             => open,
        gt3_rxbufstatus_out             => gt3_rxbufstatus_out,

        gt3_rxresetdone_out        => gt3_rxresetdone_out,
        -------------------------- RX Margin Analysis Ports ------------------------
         gt3_eyescanreset_in                => gt3_eyescanreset_in,
         gt3_eyescandataerror_out           => gt3_eyescandataerror_out,
         gt3_eyescantrigger_in              => gt3_eyescantrigger_in,

         gt3_rxlpmen_in                     => gt3_rxlpmen_in,
         gt3_rxcdrovrden_in                 => gt3_rxcdrovrden_in,
         gt3_rxdfelpmreset_in               => gt3_rxdfelpmreset_in,
         gt3_rxmonitorout_out               => gt3_rxmonitorout_out,
         gt3_rxmonitorsel_in                => gt3_rxmonitorsel_in,
         gt3_rxcdrhold_in                   => gt3_rxcdrhold_in,

         gt3_rxbyteisaligned_out            => gt3_rxbyteisaligned_out,
         gt3_rxcommadet_out                 => gt3_rxcommadet_out,
        ------------------- Receive Ports - Pattern Checker Ports ------------------
        gt3_rxprbserr_out               => gt3_rxprbserr_out,
        gt3_rxprbssel_in                => gt3_rxprbssel_in,
        ------------------- Receive Ports - Pattern Checker ports ------------------
        gt3_rxprbscntreset_in           => gt3_rxprbscntreset_in,
        ------------------- Receive Ports - RX Data Path interface -----------------
        gt3_rxpcsreset_in               => gt3_rxpcsreset_in,
        gt3_rxpmareset_in               => gt3_rxpmareset_in,
        gt3_dmonitorout_out             => gt3_dmonitorout_out,
        gt3_rxpmaresetdone_out          => gt3_rxpmaresetdone_out,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        gt3_rxbufreset_in               => gt3_rxbufreset_in,



        -- DRP I/F
DRPCLK_IN                      => drpclk_in,
DRPADDR_IN                     => DRPADDR_IN,
DRPDI_IN                       => DRPDI_IN,
DRPDO_OUT                      => DRPDO_OUT,
DRPEN_IN                       => DRPEN_IN,
DRPRDY_OUT                     => DRPRDY_OUT,
DRPWE_IN                       => DRPWE_IN,
DRPCLK_IN_LANE1                      => drpclk_in,
DRPADDR_IN_LANE1                     => DRPADDR_IN_LANE1,
DRPDI_IN_LANE1                       => DRPDI_IN_LANE1,
DRPDO_OUT_LANE1                      => DRPDO_OUT_LANE1,
DRPEN_IN_LANE1                       => DRPEN_IN_LANE1,
DRPRDY_OUT_LANE1                     => DRPRDY_OUT_LANE1,
DRPWE_IN_LANE1                       => DRPWE_IN_LANE1,
DRPCLK_IN_LANE2                      => drpclk_in,
DRPADDR_IN_LANE2                     => DRPADDR_IN_LANE2,
DRPDI_IN_LANE2                       => DRPDI_IN_LANE2,
DRPDO_OUT_LANE2                      => DRPDO_OUT_LANE2,
DRPEN_IN_LANE2                       => DRPEN_IN_LANE2,
DRPRDY_OUT_LANE2                     => DRPRDY_OUT_LANE2,
DRPWE_IN_LANE2                       => DRPWE_IN_LANE2,
DRPCLK_IN_LANE3                      => drpclk_in,
DRPADDR_IN_LANE3                     => DRPADDR_IN_LANE3,
DRPDI_IN_LANE3                       => DRPDI_IN_LANE3,
DRPDO_OUT_LANE3                      => DRPDO_OUT_LANE3,
DRPEN_IN_LANE3                       => DRPEN_IN_LANE3,
DRPRDY_OUT_LANE3                     => DRPRDY_OUT_LANE3,
DRPWE_IN_LANE3                       => DRPWE_IN_LANE3,

        INIT_CLK_IN                => init_clk_in,   
	PLL_NOT_LOCKED                   => PLL_NOT_LOCKED,
RXFSM_DATA_VALID                              => rxfsm_data_valid_r,
	TX_RESETDONE_OUT                 => OPEN,
	RX_RESETDONE_OUT                 => rx_resetdone_i,   
        -- Aurora Lane Interface
RXPOLARITY_IN           => rx_polarity_i (0),
RXPOLARITY_IN_LANE1           => rx_polarity_i (1),
RXPOLARITY_IN_LANE2           => rx_polarity_i (2),
RXPOLARITY_IN_LANE3           => rx_polarity_i (3),
RXRESET_IN              => gtp_rx_reset_i (0),
RXRESET_IN_LANE1              => gtp_rx_reset_i (1),
RXRESET_IN_LANE2              => gtp_rx_reset_i (2),
RXRESET_IN_LANE3              => gtp_rx_reset_i (3),
TXCHARISK_IN            => tx_char_is_k_i(1 downto 0),
TXCHARISK_IN_LANE1            => tx_char_is_k_i(3 downto 2),
TXCHARISK_IN_LANE2            => tx_char_is_k_i(5 downto 4),
TXCHARISK_IN_LANE3            => tx_char_is_k_i(7 downto 6),
TXDATA_IN               => tx_data_i(15 downto 0),
TXDATA_IN_LANE1               => tx_data_i(31 downto 16),
TXDATA_IN_LANE2               => tx_data_i(47 downto 32),
TXDATA_IN_LANE3               => tx_data_i(63 downto 48),
TXRESET_IN              => gtp_tx_reset_i (0),
TXRESET_IN_LANE1              => gtp_tx_reset_i (1),
TXRESET_IN_LANE2              => gtp_tx_reset_i (2),
TXRESET_IN_LANE3              => gtp_tx_reset_i (3),
RXDATA_OUT              => rx_data_i(15 downto 0),
RXDATA_OUT_LANE1              => rx_data_i(31 downto 16),
RXDATA_OUT_LANE2              => rx_data_i(47 downto 32),
RXDATA_OUT_LANE3              => rx_data_i(63 downto 48),
RXNOTINTABLE_OUT        => rx_not_in_table_i(1 downto 0),
RXNOTINTABLE_OUT_LANE1        => rx_not_in_table_i(3 downto 2),
RXNOTINTABLE_OUT_LANE2        => rx_not_in_table_i(5 downto 4),
RXNOTINTABLE_OUT_LANE3        => rx_not_in_table_i(7 downto 6),
RXDISPERR_OUT           => rx_disp_err_i(1 downto 0),
RXDISPERR_OUT_LANE1           => rx_disp_err_i(3 downto 2),
RXDISPERR_OUT_LANE2           => rx_disp_err_i(5 downto 4),
RXDISPERR_OUT_LANE3           => rx_disp_err_i(7 downto 6),
RXCHARISK_OUT           => rx_char_is_k_i(1 downto 0),
RXCHARISK_OUT_LANE1           => rx_char_is_k_i(3 downto 2),
RXCHARISK_OUT_LANE2           => rx_char_is_k_i(5 downto 4),
RXCHARISK_OUT_LANE3           => rx_char_is_k_i(7 downto 6),
RXCHARISCOMMA_OUT       => rx_char_is_comma_i(1 downto 0),
RXCHARISCOMMA_OUT_LANE1       => rx_char_is_comma_i(3 downto 2),
RXCHARISCOMMA_OUT_LANE2       => rx_char_is_comma_i(5 downto 4),
RXCHARISCOMMA_OUT_LANE3       => rx_char_is_comma_i(7 downto 6),
TXBUFERR_OUT            => tx_buf_err_i (0),
TXBUFERR_OUT_LANE1            => tx_buf_err_i (1),
TXBUFERR_OUT_LANE2            => tx_buf_err_i (2),
TXBUFERR_OUT_LANE3            => tx_buf_err_i (3),
RXBUFERR_OUT            => rx_buf_err_i (0),
RXBUFERR_OUT_LANE1            => rx_buf_err_i (1),
RXBUFERR_OUT_LANE2            => rx_buf_err_i (2),
RXBUFERR_OUT_LANE3            => rx_buf_err_i (3),
RXREALIGN_OUT           => rx_realign_i (0),
RXREALIGN_OUT_LANE1           => rx_realign_i (1),
RXREALIGN_OUT_LANE2           => rx_realign_i (2),
RXREALIGN_OUT_LANE3           => rx_realign_i (3),
        -- Reset due to channel initialization watchdog timer expiry  
                    GTRXRESET_IN                =>  gtrxreset_i,

        -- reset for hot plug
                    LINK_RESET_IN      => link_reset_i,
        --  Phase Align Interface

ENMCOMMAALIGN_IN        => ena_comma_align_i (0),
ENMCOMMAALIGN_IN_LANE1        => ena_comma_align_i (1),
ENMCOMMAALIGN_IN_LANE2        => ena_comma_align_i (2),
ENMCOMMAALIGN_IN_LANE3        => ena_comma_align_i (3),
ENPCOMMAALIGN_IN        => ena_comma_align_i (0),
ENPCOMMAALIGN_IN_LANE1        => ena_comma_align_i (1),
ENPCOMMAALIGN_IN_LANE2        => ena_comma_align_i (2),
ENPCOMMAALIGN_IN_LANE3        => ena_comma_align_i (3),
        -- Global Logic Interface

ENCHANSYNC_IN           => tied_to_vcc_i,
ENCHANSYNC_IN_LANE1           => en_chan_sync_i,
ENCHANSYNC_IN_LANE2           => tied_to_vcc_i,
ENCHANSYNC_IN_LANE3           => tied_to_vcc_i,
CHBONDDONE_OUT          => ch_bond_done_i (0),
CHBONDDONE_OUT_LANE1          => ch_bond_done_i (1),
CHBONDDONE_OUT_LANE2          => ch_bond_done_i (2),
CHBONDDONE_OUT_LANE3          => ch_bond_done_i (3),

        -- Serial IO
RX1N_IN       => RXN (0),
RX1N_IN_LANE1       => RXN (1),
RX1N_IN_LANE2       => RXN (2),
RX1N_IN_LANE3       => RXN (3),
RX1P_IN       => RXP (0),
RX1P_IN_LANE1       => RXP (1),
RX1P_IN_LANE2       => RXP (2),
RX1P_IN_LANE3       => RXP (3),
TX1N_OUT      => open,
TX1N_OUT_LANE1      => open,
TX1N_OUT_LANE2      => open,
TX1N_OUT_LANE3      => open,
TX1P_OUT      => open,
TX1P_OUT_LANE1      => open,
TX1P_OUT_LANE2      => open,
TX1P_OUT_LANE3      => open,

        -- Reference Clocks and User Clock

                    RXUSRCLK_IN             => sync_clk,
                    RXUSRCLK2_IN            => user_clk,
                    TXUSRCLK_IN             => sync_clk,
                    TXUSRCLK2_IN            => user_clk,
                    REFCLK                  =>  gt_refclk1,

TXOUTCLK1_OUT           => tx_out_clk_i (0),
TXOUTCLK1_OUT_LANE1           => tx_out_clk_i (1),
TXOUTCLK1_OUT_LANE2           => tx_out_clk_i (2),
TXOUTCLK1_OUT_LANE3           => tx_out_clk_i (3),
PLLLKDET_OUT            => tx_lock_i (0),       
PLLLKDET_OUT_LANE1            => tx_lock_i (1),       
PLLLKDET_OUT_LANE2            => tx_lock_i (2),       
PLLLKDET_OUT_LANE3            => tx_lock_i (3),       

        -- System Interface

                    GTRESET_IN                                     => gt_reset_sync_init_clk,
                    LOOPBACK_IN                                         => LOOPBACK,

                    POWERDOWN_IN                                       => POWER_DOWN
                 );


-- FF stages added for timing closure
process (user_clk)
begin
  if (user_clk 'event and user_clk = '1') then
    ch_bond_done_r1 <= ch_bond_done_i;
  end if;
end process;

process (user_clk)
begin
  if (user_clk 'event and user_clk = '1') then
    ch_bond_done_r2 <= ch_bond_done_r1;
  end if;
end process;

process(user_clk)
begin
  if(user_clk='1' and user_clk'event)then
    if(system_reset_i='1')then
      ch_bond_done_dly_i  <=  (others => '0');
    elsif(en_chan_sync_i='1')then
      ch_bond_done_dly_i  <=  ch_bond_done_r2;
    else
      ch_bond_done_dly_i  <=  (others => '0');
    end if;
  end if;
end process;

process(user_clk)
begin
  if(user_clk='1' and user_clk'event)then
    if(system_reset_i='1')then
      ch_bond_load_pulse_i  <=  (others => '0');
    elsif(en_chan_sync_i='1')then
      ch_bond_load_pulse_i  <=  ch_bond_done_r2 and not ch_bond_done_dly_i;
    else
      ch_bond_load_pulse_i  <=  (others => '0');
    end if;
  end if;
end process;

    -- Instantiate RX Global Logic --

    rx_global_logic_simplex_i : aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX
    generic map
        (
          WATCHDOG_TIMEOUT  => WATCHDOG_TIMEOUT 
        )
    port map (

        -- GT Interface

        CH_BOND_DONE        =>  ch_bond_done_i,
        EN_CHAN_SYNC        =>  en_chan_sync_i,

        -- Aurora Lane Interface

        LANE_UP             =>  rx_lane_up_i,
        SOFT_ERR            =>  soft_err_i,
        HARD_ERR            =>  rx_hard_err_i,
        CHANNEL_BOND_LOAD   =>  ch_bond_load_pulse_i,
        GOT_A               =>  got_a_i,
        GOT_V               =>  got_v_i,
        RESET_LANES         =>  rx_reset_lanes_i,
        GTRXRESET_OUT       => gtrxreset_i,

        -- Sideband Signals
        RX_ALIGNED          =>  OPEN,
        RX_BONDED           =>  OPEN,
        RX_VERIFY           =>  OPEN,

        -- System Interface

        USER_CLK            =>  user_clk,
        RESET               =>  system_reset_i,
        POWER_DOWN          =>  POWER_DOWN,
        CHANNEL_UP          =>  rx_channel_up_i,
        START_RX            =>  start_rx_i,
        CHANNEL_SOFT_ERR    =>  SOFT_ERR,
        CHANNEL_HARD_ERR    =>  RX_HARD_ERR
             );





    --_____________________________ RX AXI SHIM _______________________________
    ll_to_axi_pdu_i : aurora_rx_4l_64b_LL_TO_AXI
    generic map
    (
       DATA_WIDTH           => 64,
       STRB_WIDTH           => 8,
       REM_WIDTH            => 3
    )

    port map
    (
      LL_IP_DATA            => rx_data,
      LL_IP_SOF_N           => rx_sof,
      LL_IP_EOF_N           => rx_eof,
      LL_IP_REM             => rx_rem,
      LL_IP_SRC_RDY_N       => rx_src_rdy,
      LL_OP_DST_RDY_N       => OPEN,

      AXI4_S_OP_TVALID      => M_AXI_RX_TVALID,
      AXI4_S_OP_TDATA       => M_AXI_RX_TDATA,
      AXI4_S_OP_TKEEP       => M_AXI_RX_TKEEP,
      AXI4_S_OP_TLAST       => M_AXI_RX_TLAST,
      AXI4_S_IP_TREADY      => tied_to_ground_i

    );

    ll_to_axi_ufc_i : aurora_rx_4l_64b_LL_TO_AXI
    generic map
    (
       DATA_WIDTH           => 64,
       USE_UFC_REM          => 1,            
       STRB_WIDTH           => 8,
       REM_WIDTH            => 3
    )

    port map
    (
      LL_IP_DATA            => rx_ufc_data,
      LL_IP_SOF_N           => rx_ufc_sof,
      LL_IP_EOF_N           => rx_ufc_eof,
      LL_IP_REM             => rx_ufc_rem,
      LL_IP_SRC_RDY_N       => rx_ufc_src_rdy,
      LL_OP_DST_RDY_N       => OPEN,

      AXI4_S_OP_TVALID      => M_AXI_UFC_RX_TVALID,
      AXI4_S_OP_TDATA       => M_AXI_UFC_RX_TDATA,
      AXI4_S_OP_TKEEP       => M_AXI_UFC_RX_TKEEP,
      AXI4_S_OP_TLAST       => M_AXI_UFC_RX_TLAST,
      AXI4_S_IP_TREADY      => tied_to_ground_i

    );



    -- Instantiate RX_LL --

    rx_ll_i : aurora_rx_4l_64b_RX_LL

        port map (

        -- AXI PDU Interface
                    RX_D                    => rx_data,
                    RX_REM                  => rx_rem,
                    RX_SRC_RDY_N            => rx_src_rdy,
                    RX_SOF_N                => rx_sof,
                    RX_EOF_N                => rx_eof,

            -- UFC Interface

                    UFC_RX_DATA      => rx_ufc_data,
                    UFC_RX_REM       => rx_ufc_rem,
                    UFC_RX_SRC_RDY_N => rx_ufc_src_rdy,
                    UFC_RX_SOF_N     => rx_ufc_sof,
                    UFC_RX_EOF_N     => rx_ufc_eof,
            -- Global Logic Interface

                    START_RX         => start_rx_i,

            -- Aurora Lane Interface

                    RX_PAD           => rx_pad_i,
                    RX_PE_DATA       => rx_pe_data_i,
                    RX_PE_DATA_V     => rx_pe_data_v_i,
                    RX_SCP           => rx_scp_i,
                    RX_ECP           => rx_ecp_i,
                    RX_SUF           => rx_suf_i,
                    RX_FC_NB         => rx_fc_nb_i,

            -- Error Interface

                    FRAME_ERR      => FRAME_ERR,

            -- System Interface

                    USER_CLK         => user_clk

                 );

end MAPPED;
