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--

--
--  RX_GLOBAL_LOGIC_SIMPLEX
--
--
--
--  Description: The GLOBAL_LOGIC module handles channel bonding, channel
--               verification, channel error manangement and idle generation.
--
--               This module supports 4 2-byte lane designs
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX is

generic (
           WATCHDOG_TIMEOUT   : integer := 14
        );


port (

    -- GTP Interface

       CH_BOND_DONE       : in std_logic_vector(0 to 3);
       EN_CHAN_SYNC       : out std_logic;

    -- Aurora Lane Interface

       LANE_UP            : in std_logic_vector(0 to 3);
       SOFT_ERR           : in std_logic_vector(0 to 3);
       HARD_ERR           : in std_logic_vector(0 to 3);
       CHANNEL_BOND_LOAD  : in std_logic_vector(0 to 3);
       GOT_A              : in std_logic_vector(0 to 7);
       GOT_V              : in std_logic_vector(0 to 3);
       RESET_LANES        : out std_logic_vector(0 to 3);
       GTRXRESET_OUT         : out std_logic;

    -- Sideband Signal
       RX_ALIGNED         : out std_logic;
       RX_BONDED          : out std_logic;
       RX_VERIFY          : out std_logic;

    -- System Interface

       USER_CLK           : in std_logic;
       RESET              : in std_logic;
       POWER_DOWN         : in std_logic;
       CHANNEL_UP         : out std_logic;
       START_RX           : out std_logic;
       CHANNEL_SOFT_ERR   : out std_logic;
       CHANNEL_HARD_ERR   : out std_logic

    );

end aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX;

architecture MAPPED of aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX is

-- External Register Declarations --

    signal EN_CHAN_SYNC_Buffer       : std_logic;
    signal RESET_LANES_Buffer        : std_logic_vector(0 to 3);
    signal CHANNEL_UP_Buffer         : std_logic;
    signal START_RX_Buffer           : std_logic;
    signal CHANNEL_SOFT_ERR_Buffer   : std_logic;
    signal CHANNEL_HARD_ERR_Buffer   : std_logic;
    signal RX_BONDED_Buffer          : std_logic;
    signal RX_ALIGNED_Buffer         : std_logic;
   
-- Wire Declarations --

    signal reset_channel_i : std_logic;

-- Component Declarations --

    component aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX
    generic (
                 WATCHDOG_TIMEOUT   : integer := 14
            );

       port (

        -- GTP Interface

        CH_BOND_DONE      : in std_logic_vector(0 to 3);
        EN_CHAN_SYNC      : out std_logic;

        -- Aurora Lane Interface

        CHANNEL_BOND_LOAD : in std_logic_vector(0 to 3);
        GOT_A             : in std_logic_vector(0 to 7);
        GOT_V             : in std_logic_vector(0 to 3);
        RESET_LANES       : out std_logic_vector(0 to 3);

        -- System Interface

        USER_CLK          : in std_logic;
        RESET             : in std_logic;
        CHANNEL_UP        : out std_logic;
        START_RX          : out std_logic;

        -- Sideband Signals

        RX_BONDED         : out std_logic;

        -- Channel Init State Machine Interface

        GTRXRESET_OUT         : out std_logic;
        RESET_CHANNEL     : in std_logic

            );

    end component;



    component aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX

      port (

        -- Aurora Lane Interface

        SOFT_ERR           : in std_logic_vector(0 to 3);
        HARD_ERR           : in std_logic_vector(0 to 3);
        LANE_UP            : in std_logic_vector(0 to 3);

        -- System Interface

        USER_CLK           : in std_logic;
        POWER_DOWN         : in std_logic;

        CHANNEL_SOFT_ERR   : out std_logic;
        CHANNEL_HARD_ERR   : out std_logic;

        -- Sideband Signal

        RX_ALIGNED         : out std_logic;

        -- Channel Init SM Interface

        RESET_CHANNEL      : out std_logic

             );

    end component;

begin

    EN_CHAN_SYNC       <= EN_CHAN_SYNC_Buffer;
    RESET_LANES        <= RESET_LANES_Buffer;
    CHANNEL_UP         <= CHANNEL_UP_Buffer;
    START_RX           <= START_RX_Buffer;
    CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer;
    CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;
    RX_ALIGNED         <= RX_ALIGNED_Buffer;
    RX_BONDED          <= RX_BONDED_Buffer;
    RX_VERIFY          <= CHANNEL_UP_Buffer;
   
-- Main Body of Code --

    -- State Machine for channel bonding and verification.

    rx_channel_init_sm_simplex_i : aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX
    generic map
        (
          WATCHDOG_TIMEOUT  => WATCHDOG_TIMEOUT 
        )

    port map (

        -- GTP Interface

        CH_BOND_DONE      => CH_BOND_DONE,
        EN_CHAN_SYNC      => EN_CHAN_SYNC_Buffer,

        -- Aurora Lane Interface

        CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
        GOT_A             => GOT_A,
        GOT_V             => GOT_V,
        RESET_LANES       => RESET_LANES_Buffer,

        -- System Interface

        USER_CLK          => USER_CLK,
        RESET             => RESET,
        START_RX          => START_RX_Buffer,
        CHANNEL_UP        => CHANNEL_UP_Buffer,

        -- Sideband Signals
       
       RX_BONDED          => RX_BONDED_Buffer,

        -- Channel Error Management Module Interface
       GTRXRESET_OUT      => GTRXRESET_OUT,
       RESET_CHANNEL      => reset_channel_i

              );



    -- Channel Error Management module.

    rx_channel_err_detect_simplex_i : aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX

    port map (

        -- Aurora Lane Interface

        SOFT_ERR         => SOFT_ERR,
        HARD_ERR         => HARD_ERR,
        LANE_UP          => LANE_UP,

        -- System Interface

        USER_CLK         => USER_CLK,
        POWER_DOWN       => POWER_DOWN,
        CHANNEL_SOFT_ERR => CHANNEL_SOFT_ERR_Buffer,
        CHANNEL_HARD_ERR => CHANNEL_HARD_ERR_Buffer,

        -- Sideband Signal
       
        RX_ALIGNED       => RX_ALIGNED_Buffer,


        -- Channel Init State Machine Interface

        RESET_CHANNEL    => reset_channel_i

             );

end MAPPED;
