// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
// Date        : Mon May 13 11:36:00 2024
// Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode funcsim
//               /home/gitlab-runner/builds/z7w3GeU4/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_sim_netlist.v
// Design      : aurora_rx_4l_64b
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* NotValidForBitStream *)
module aurora_rx_4l_64b
   (m_axi_rx_tdata,
    m_axi_rx_tvalid,
    m_axi_rx_tkeep,
    m_axi_rx_tlast,
    m_axi_ufc_rx_tdata,
    m_axi_ufc_rx_tkeep,
    m_axi_ufc_rx_tvalid,
    m_axi_ufc_rx_tlast,
    rxp,
    rxn,
    gt_refclk1,
    frame_err,
    rx_hard_err,
    soft_err,
    rx_lane_up,
    rx_channel_up,
    user_clk,
    sync_clk,
    rx_system_reset,
    power_down,
    loopback,
    gt_reset,
    tx_lock,
    sys_reset_out,
    init_clk_in,
    rx_resetdone_out,
    link_reset_out,
    drpclk_in,
    drpaddr_in,
    drpdi_in,
    drpdo_out,
    drpen_in,
    drprdy_out,
    drpwe_in,
    drpaddr_in_lane1,
    drpdi_in_lane1,
    drpdo_out_lane1,
    drpen_in_lane1,
    drprdy_out_lane1,
    drpwe_in_lane1,
    drpaddr_in_lane2,
    drpdi_in_lane2,
    drpdo_out_lane2,
    drpen_in_lane2,
    drprdy_out_lane2,
    drpwe_in_lane2,
    drpaddr_in_lane3,
    drpdi_in_lane3,
    drpdo_out_lane3,
    drpen_in_lane3,
    drprdy_out_lane3,
    drpwe_in_lane3,
    gt0_cplllock_out,
    gt0_rxlpmen_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxmonitorout_out,
    gt0_rxmonitorsel_in,
    gt0_rxcdrhold_in,
    gt0_eyescanreset_in,
    gt0_eyescandataerror_out,
    gt0_eyescantrigger_in,
    gt0_rxbyteisaligned_out,
    gt0_rxcommadet_out,
    gt0_rxprbserr_out,
    gt0_rxprbssel_in,
    gt0_rxprbscntreset_in,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    gt0_rxpmaresetdone_out,
    gt0_dmonitorout_out,
    gt0_rxbufreset_in,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    gt0_rx_realign_out,
    gt0_rx_buf_err_out,
    gt0_rxresetdone_out,
    gt0_rxbufstatus_out,
    gt1_cplllock_out,
    gt1_rxlpmen_in,
    gt1_rxcdrovrden_in,
    gt1_rxdfelpmreset_in,
    gt1_rxmonitorout_out,
    gt1_rxmonitorsel_in,
    gt1_rxcdrhold_in,
    gt1_eyescanreset_in,
    gt1_eyescandataerror_out,
    gt1_eyescantrigger_in,
    gt1_rxbyteisaligned_out,
    gt1_rxcommadet_out,
    gt1_rxprbserr_out,
    gt1_rxprbssel_in,
    gt1_rxprbscntreset_in,
    gt1_rxpcsreset_in,
    gt1_rxpmareset_in,
    gt1_rxpmaresetdone_out,
    gt1_dmonitorout_out,
    gt1_rxbufreset_in,
    gt1_rx_disp_err_out,
    gt1_rx_not_in_table_out,
    gt1_rx_realign_out,
    gt1_rx_buf_err_out,
    gt1_rxresetdone_out,
    gt1_rxbufstatus_out,
    gt2_cplllock_out,
    gt2_rxlpmen_in,
    gt2_rxcdrovrden_in,
    gt2_rxdfelpmreset_in,
    gt2_rxmonitorout_out,
    gt2_rxmonitorsel_in,
    gt2_rxcdrhold_in,
    gt2_eyescanreset_in,
    gt2_eyescandataerror_out,
    gt2_eyescantrigger_in,
    gt2_rxbyteisaligned_out,
    gt2_rxcommadet_out,
    gt2_rxprbserr_out,
    gt2_rxprbssel_in,
    gt2_rxprbscntreset_in,
    gt2_rxpcsreset_in,
    gt2_rxpmareset_in,
    gt2_rxpmaresetdone_out,
    gt2_dmonitorout_out,
    gt2_rxbufreset_in,
    gt2_rx_disp_err_out,
    gt2_rx_not_in_table_out,
    gt2_rx_realign_out,
    gt2_rx_buf_err_out,
    gt2_rxresetdone_out,
    gt2_rxbufstatus_out,
    gt3_cplllock_out,
    gt3_rxlpmen_in,
    gt3_rxcdrovrden_in,
    gt3_rxdfelpmreset_in,
    gt3_rxmonitorout_out,
    gt3_rxmonitorsel_in,
    gt3_rxcdrhold_in,
    gt3_eyescanreset_in,
    gt3_eyescandataerror_out,
    gt3_eyescantrigger_in,
    gt3_rxbyteisaligned_out,
    gt3_rxcommadet_out,
    gt3_rxprbserr_out,
    gt3_rxprbssel_in,
    gt3_rxprbscntreset_in,
    gt3_rxpcsreset_in,
    gt3_rxpmareset_in,
    gt3_rxpmaresetdone_out,
    gt3_dmonitorout_out,
    gt3_rxbufreset_in,
    gt3_rx_disp_err_out,
    gt3_rx_not_in_table_out,
    gt3_rx_realign_out,
    gt3_rx_buf_err_out,
    gt3_rxresetdone_out,
    gt3_rxbufstatus_out,
    gt0_qplllock_in,
    gt0_qpllrefclklost_in,
    gt0_qpllreset_out,
    gt1_qplllock_in,
    gt1_qpllrefclklost_in,
    gt1_qpllreset_out,
    gt_qpllclk_quad2_in,
    gt_qpllrefclk_quad2_in,
    gt_qpllclk_quad3_in,
    gt_qpllrefclk_quad3_in,
    tx_out_clk,
    pll_not_locked);
  output [63:0]m_axi_rx_tdata;
  output m_axi_rx_tvalid;
  output [7:0]m_axi_rx_tkeep;
  output m_axi_rx_tlast;
  output [63:0]m_axi_ufc_rx_tdata;
  output [7:0]m_axi_ufc_rx_tkeep;
  output m_axi_ufc_rx_tvalid;
  output m_axi_ufc_rx_tlast;
  input [0:3]rxp;
  input [0:3]rxn;
  input gt_refclk1;
  output frame_err;
  output rx_hard_err;
  output soft_err;
  output [0:3]rx_lane_up;
  output rx_channel_up;
  input user_clk;
  input sync_clk;
  input rx_system_reset;
  input power_down;
  input [2:0]loopback;
  input gt_reset;
  output tx_lock;
  output sys_reset_out;
  input init_clk_in;
  output rx_resetdone_out;
  output link_reset_out;
  input drpclk_in;
  input [8:0]drpaddr_in;
  input [15:0]drpdi_in;
  output [15:0]drpdo_out;
  input drpen_in;
  output drprdy_out;
  input drpwe_in;
  input [8:0]drpaddr_in_lane1;
  input [15:0]drpdi_in_lane1;
  output [15:0]drpdo_out_lane1;
  input drpen_in_lane1;
  output drprdy_out_lane1;
  input drpwe_in_lane1;
  input [8:0]drpaddr_in_lane2;
  input [15:0]drpdi_in_lane2;
  output [15:0]drpdo_out_lane2;
  input drpen_in_lane2;
  output drprdy_out_lane2;
  input drpwe_in_lane2;
  input [8:0]drpaddr_in_lane3;
  input [15:0]drpdi_in_lane3;
  output [15:0]drpdo_out_lane3;
  input drpen_in_lane3;
  output drprdy_out_lane3;
  input drpwe_in_lane3;
  output gt0_cplllock_out;
  input gt0_rxlpmen_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  output [6:0]gt0_rxmonitorout_out;
  input [1:0]gt0_rxmonitorsel_in;
  input gt0_rxcdrhold_in;
  input gt0_eyescanreset_in;
  output gt0_eyescandataerror_out;
  input gt0_eyescantrigger_in;
  output gt0_rxbyteisaligned_out;
  output gt0_rxcommadet_out;
  output gt0_rxprbserr_out;
  input [2:0]gt0_rxprbssel_in;
  input gt0_rxprbscntreset_in;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  output gt0_rxpmaresetdone_out;
  output [14:0]gt0_dmonitorout_out;
  input gt0_rxbufreset_in;
  output [1:0]gt0_rx_disp_err_out;
  output [1:0]gt0_rx_not_in_table_out;
  output gt0_rx_realign_out;
  output gt0_rx_buf_err_out;
  output gt0_rxresetdone_out;
  output [2:0]gt0_rxbufstatus_out;
  output gt1_cplllock_out;
  input gt1_rxlpmen_in;
  input gt1_rxcdrovrden_in;
  input gt1_rxdfelpmreset_in;
  output [6:0]gt1_rxmonitorout_out;
  input [1:0]gt1_rxmonitorsel_in;
  input gt1_rxcdrhold_in;
  input gt1_eyescanreset_in;
  output gt1_eyescandataerror_out;
  input gt1_eyescantrigger_in;
  output gt1_rxbyteisaligned_out;
  output gt1_rxcommadet_out;
  output gt1_rxprbserr_out;
  input [2:0]gt1_rxprbssel_in;
  input gt1_rxprbscntreset_in;
  input gt1_rxpcsreset_in;
  input gt1_rxpmareset_in;
  output gt1_rxpmaresetdone_out;
  output [14:0]gt1_dmonitorout_out;
  input gt1_rxbufreset_in;
  output [1:0]gt1_rx_disp_err_out;
  output [1:0]gt1_rx_not_in_table_out;
  output gt1_rx_realign_out;
  output gt1_rx_buf_err_out;
  output gt1_rxresetdone_out;
  output [2:0]gt1_rxbufstatus_out;
  output gt2_cplllock_out;
  input gt2_rxlpmen_in;
  input gt2_rxcdrovrden_in;
  input gt2_rxdfelpmreset_in;
  output [6:0]gt2_rxmonitorout_out;
  input [1:0]gt2_rxmonitorsel_in;
  input gt2_rxcdrhold_in;
  input gt2_eyescanreset_in;
  output gt2_eyescandataerror_out;
  input gt2_eyescantrigger_in;
  output gt2_rxbyteisaligned_out;
  output gt2_rxcommadet_out;
  output gt2_rxprbserr_out;
  input [2:0]gt2_rxprbssel_in;
  input gt2_rxprbscntreset_in;
  input gt2_rxpcsreset_in;
  input gt2_rxpmareset_in;
  output gt2_rxpmaresetdone_out;
  output [14:0]gt2_dmonitorout_out;
  input gt2_rxbufreset_in;
  output [1:0]gt2_rx_disp_err_out;
  output [1:0]gt2_rx_not_in_table_out;
  output gt2_rx_realign_out;
  output gt2_rx_buf_err_out;
  output gt2_rxresetdone_out;
  output [2:0]gt2_rxbufstatus_out;
  output gt3_cplllock_out;
  input gt3_rxlpmen_in;
  input gt3_rxcdrovrden_in;
  input gt3_rxdfelpmreset_in;
  output [6:0]gt3_rxmonitorout_out;
  input [1:0]gt3_rxmonitorsel_in;
  input gt3_rxcdrhold_in;
  input gt3_eyescanreset_in;
  output gt3_eyescandataerror_out;
  input gt3_eyescantrigger_in;
  output gt3_rxbyteisaligned_out;
  output gt3_rxcommadet_out;
  output gt3_rxprbserr_out;
  input [2:0]gt3_rxprbssel_in;
  input gt3_rxprbscntreset_in;
  input gt3_rxpcsreset_in;
  input gt3_rxpmareset_in;
  output gt3_rxpmaresetdone_out;
  output [14:0]gt3_dmonitorout_out;
  input gt3_rxbufreset_in;
  output [1:0]gt3_rx_disp_err_out;
  output [1:0]gt3_rx_not_in_table_out;
  output gt3_rx_realign_out;
  output gt3_rx_buf_err_out;
  output gt3_rxresetdone_out;
  output [2:0]gt3_rxbufstatus_out;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt1_qplllock_in;
  input gt1_qpllrefclklost_in;
  output gt1_qpllreset_out;
  input gt_qpllclk_quad2_in;
  input gt_qpllrefclk_quad2_in;
  input gt_qpllclk_quad3_in;
  input gt_qpllrefclk_quad3_in;
  output tx_out_clk;
  input pll_not_locked;

  wire \<const0> ;
  wire \<const1> ;
  wire [8:0]drpaddr_in;
  wire [8:0]drpaddr_in_lane1;
  wire [8:0]drpaddr_in_lane2;
  wire [8:0]drpaddr_in_lane3;
  wire drpclk_in;
  wire [15:0]drpdi_in;
  wire [15:0]drpdi_in_lane1;
  wire [15:0]drpdi_in_lane2;
  wire [15:0]drpdi_in_lane3;
  wire [15:0]drpdo_out;
  wire [15:0]drpdo_out_lane1;
  wire [15:0]drpdo_out_lane2;
  wire [15:0]drpdo_out_lane3;
  wire drpen_in;
  wire drpen_in_lane1;
  wire drpen_in_lane2;
  wire drpen_in_lane3;
  wire drprdy_out;
  wire drprdy_out_lane1;
  wire drprdy_out_lane2;
  wire drprdy_out_lane3;
  wire drpwe_in;
  wire drpwe_in_lane1;
  wire drpwe_in_lane2;
  wire drpwe_in_lane3;
  wire frame_err;
  wire gt0_cplllock_out;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire gt0_rx_buf_err_out;
  wire [1:0]gt0_rx_disp_err_out;
  wire [1:0]gt0_rx_not_in_table_out;
  wire gt0_rx_realign_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt1_cplllock_out;
  wire [14:0]gt1_dmonitorout_out;
  wire gt1_eyescandataerror_out;
  wire gt1_eyescanreset_in;
  wire gt1_eyescantrigger_in;
  wire gt1_rx_buf_err_out;
  wire [1:0]gt1_rx_disp_err_out;
  wire [1:0]gt1_rx_not_in_table_out;
  wire gt1_rx_realign_out;
  wire gt1_rxbufreset_in;
  wire [2:0]gt1_rxbufstatus_out;
  wire gt1_rxbyteisaligned_out;
  wire gt1_rxcdrhold_in;
  wire gt1_rxcdrovrden_in;
  wire gt1_rxcommadet_out;
  wire gt1_rxdfelpmreset_in;
  wire gt1_rxlpmen_in;
  wire [6:0]gt1_rxmonitorout_out;
  wire [1:0]gt1_rxmonitorsel_in;
  wire gt1_rxpcsreset_in;
  wire gt1_rxpmareset_in;
  wire gt1_rxpmaresetdone_out;
  wire gt1_rxprbscntreset_in;
  wire gt1_rxprbserr_out;
  wire [2:0]gt1_rxprbssel_in;
  wire gt1_rxresetdone_out;
  wire gt2_cplllock_out;
  wire [14:0]gt2_dmonitorout_out;
  wire gt2_eyescandataerror_out;
  wire gt2_eyescanreset_in;
  wire gt2_eyescantrigger_in;
  wire gt2_rx_buf_err_out;
  wire [1:0]gt2_rx_disp_err_out;
  wire [1:0]gt2_rx_not_in_table_out;
  wire gt2_rx_realign_out;
  wire gt2_rxbufreset_in;
  wire [2:0]gt2_rxbufstatus_out;
  wire gt2_rxbyteisaligned_out;
  wire gt2_rxcdrhold_in;
  wire gt2_rxcdrovrden_in;
  wire gt2_rxcommadet_out;
  wire gt2_rxdfelpmreset_in;
  wire gt2_rxlpmen_in;
  wire [6:0]gt2_rxmonitorout_out;
  wire [1:0]gt2_rxmonitorsel_in;
  wire gt2_rxpcsreset_in;
  wire gt2_rxpmareset_in;
  wire gt2_rxpmaresetdone_out;
  wire gt2_rxprbscntreset_in;
  wire gt2_rxprbserr_out;
  wire [2:0]gt2_rxprbssel_in;
  wire gt2_rxresetdone_out;
  wire gt3_cplllock_out;
  wire [14:0]gt3_dmonitorout_out;
  wire gt3_eyescandataerror_out;
  wire gt3_eyescanreset_in;
  wire gt3_eyescantrigger_in;
  wire gt3_rx_buf_err_out;
  wire [1:0]gt3_rx_disp_err_out;
  wire [1:0]gt3_rx_not_in_table_out;
  wire gt3_rx_realign_out;
  wire gt3_rxbufreset_in;
  wire [2:0]gt3_rxbufstatus_out;
  wire gt3_rxbyteisaligned_out;
  wire gt3_rxcdrhold_in;
  wire gt3_rxcdrovrden_in;
  wire gt3_rxcommadet_out;
  wire gt3_rxdfelpmreset_in;
  wire gt3_rxlpmen_in;
  wire [6:0]gt3_rxmonitorout_out;
  wire [1:0]gt3_rxmonitorsel_in;
  wire gt3_rxpcsreset_in;
  wire gt3_rxpmareset_in;
  wire gt3_rxpmaresetdone_out;
  wire gt3_rxprbscntreset_in;
  wire gt3_rxprbserr_out;
  wire [2:0]gt3_rxprbssel_in;
  wire gt3_rxresetdone_out;
  wire gt_qpllclk_quad2_in;
  wire gt_qpllclk_quad3_in;
  wire gt_qpllrefclk_quad2_in;
  wire gt_qpllrefclk_quad3_in;
  wire gt_refclk1;
  wire gt_reset;
  wire init_clk_in;
  wire link_reset_out;
  wire [2:0]loopback;
  wire [63:0]m_axi_rx_tdata;
  wire [7:1]\^m_axi_rx_tkeep ;
  wire m_axi_rx_tlast;
  wire m_axi_rx_tvalid;
  wire [63:0]m_axi_ufc_rx_tdata;
  wire [7:2]\^m_axi_ufc_rx_tkeep ;
  wire m_axi_ufc_rx_tlast;
  wire m_axi_ufc_rx_tvalid;
  wire power_down;
  wire rx_channel_up;
  wire rx_hard_err;
  wire [0:3]rx_lane_up;
  wire rx_resetdone_out;
  wire rx_system_reset;
  wire [0:3]rxn;
  wire [0:3]rxp;
  wire soft_err;
  wire sync_clk;
  wire sys_reset_out;
  wire tx_lock;
  wire tx_out_clk;
  wire user_clk;
  wire NLW_U0_gt0_qpllreset_out_UNCONNECTED;
  wire NLW_U0_gt1_qpllreset_out_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_RX_TKEEP_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_UFC_RX_TKEEP_UNCONNECTED;

  assign gt0_qpllreset_out = \<const0> ;
  assign gt1_qpllreset_out = \<const0> ;
  assign m_axi_rx_tkeep[7:1] = \^m_axi_rx_tkeep [7:1];
  assign m_axi_rx_tkeep[0] = \<const1> ;
  assign m_axi_ufc_rx_tkeep[7:2] = \^m_axi_ufc_rx_tkeep [7:2];
  assign m_axi_ufc_rx_tkeep[1] = \<const1> ;
  assign m_axi_ufc_rx_tkeep[0] = \<const1> ;
  GND GND
       (.G(\<const0> ));
  (* EXAMPLE_SIMULATION = "0" *) 
  (* SIM_GTRESET_SPEEDUP = "FALSE" *) 
  aurora_rx_4l_64b_core U0
       (.DRPADDR_IN(drpaddr_in),
        .DRPADDR_IN_LANE1(drpaddr_in_lane1),
        .DRPADDR_IN_LANE2(drpaddr_in_lane2),
        .DRPADDR_IN_LANE3(drpaddr_in_lane3),
        .DRPDI_IN(drpdi_in),
        .DRPDI_IN_LANE1(drpdi_in_lane1),
        .DRPDI_IN_LANE2(drpdi_in_lane2),
        .DRPDI_IN_LANE3(drpdi_in_lane3),
        .DRPDO_OUT(drpdo_out),
        .DRPDO_OUT_LANE1(drpdo_out_lane1),
        .DRPDO_OUT_LANE2(drpdo_out_lane2),
        .DRPDO_OUT_LANE3(drpdo_out_lane3),
        .DRPEN_IN(drpen_in),
        .DRPEN_IN_LANE1(drpen_in_lane1),
        .DRPEN_IN_LANE2(drpen_in_lane2),
        .DRPEN_IN_LANE3(drpen_in_lane3),
        .DRPRDY_OUT(drprdy_out),
        .DRPRDY_OUT_LANE1(drprdy_out_lane1),
        .DRPRDY_OUT_LANE2(drprdy_out_lane2),
        .DRPRDY_OUT_LANE3(drprdy_out_lane3),
        .DRPWE_IN(drpwe_in),
        .DRPWE_IN_LANE1(drpwe_in_lane1),
        .DRPWE_IN_LANE2(drpwe_in_lane2),
        .DRPWE_IN_LANE3(drpwe_in_lane3),
        .FRAME_ERR(frame_err),
        .GT_RESET(gt_reset),
        .LINK_RESET_OUT(link_reset_out),
        .LOOPBACK(loopback),
        .M_AXI_RX_TDATA(m_axi_rx_tdata),
        .M_AXI_RX_TKEEP({\^m_axi_rx_tkeep ,NLW_U0_M_AXI_RX_TKEEP_UNCONNECTED[0]}),
        .M_AXI_RX_TLAST(m_axi_rx_tlast),
        .M_AXI_RX_TVALID(m_axi_rx_tvalid),
        .M_AXI_UFC_RX_TDATA(m_axi_ufc_rx_tdata),
        .M_AXI_UFC_RX_TKEEP({\^m_axi_ufc_rx_tkeep ,NLW_U0_M_AXI_UFC_RX_TKEEP_UNCONNECTED[1:0]}),
        .M_AXI_UFC_RX_TLAST(m_axi_ufc_rx_tlast),
        .M_AXI_UFC_RX_TVALID(m_axi_ufc_rx_tvalid),
        .PLL_NOT_LOCKED(1'b0),
        .POWER_DOWN(power_down),
        .RXN(rxn),
        .RXP(rxp),
        .RX_CHANNEL_UP(rx_channel_up),
        .RX_HARD_ERR(rx_hard_err),
        .RX_LANE_UP(rx_lane_up),
        .RX_RESETDONE_OUT(rx_resetdone_out),
        .RX_SYSTEM_RESET(rx_system_reset),
        .SOFT_ERR(soft_err),
        .TX_LOCK(tx_lock),
        .TX_OUT_CLK(tx_out_clk),
        .drpclk_in(drpclk_in),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_qplllock_in(1'b0),
        .gt0_qpllrefclklost_in(1'b0),
        .gt0_qpllreset_out(NLW_U0_gt0_qpllreset_out_UNCONNECTED),
        .gt0_rx_buf_err_out(gt0_rx_buf_err_out),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rx_realign_out(gt0_rx_realign_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out(gt0_rxbufstatus_out),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_dmonitorout_out(gt1_dmonitorout_out),
        .gt1_eyescandataerror_out(gt1_eyescandataerror_out),
        .gt1_eyescanreset_in(gt1_eyescanreset_in),
        .gt1_eyescantrigger_in(gt1_eyescantrigger_in),
        .gt1_qplllock_in(1'b0),
        .gt1_qpllrefclklost_in(1'b0),
        .gt1_qpllreset_out(NLW_U0_gt1_qpllreset_out_UNCONNECTED),
        .gt1_rx_buf_err_out(gt1_rx_buf_err_out),
        .gt1_rx_disp_err_out(gt1_rx_disp_err_out),
        .gt1_rx_not_in_table_out(gt1_rx_not_in_table_out),
        .gt1_rx_realign_out(gt1_rx_realign_out),
        .gt1_rxbufreset_in(gt1_rxbufreset_in),
        .gt1_rxbufstatus_out(gt1_rxbufstatus_out),
        .gt1_rxbyteisaligned_out(gt1_rxbyteisaligned_out),
        .gt1_rxcdrhold_in(gt1_rxcdrhold_in),
        .gt1_rxcdrovrden_in(gt1_rxcdrovrden_in),
        .gt1_rxcommadet_out(gt1_rxcommadet_out),
        .gt1_rxdfelpmreset_in(gt1_rxdfelpmreset_in),
        .gt1_rxlpmen_in(gt1_rxlpmen_in),
        .gt1_rxmonitorout_out(gt1_rxmonitorout_out),
        .gt1_rxmonitorsel_in(gt1_rxmonitorsel_in),
        .gt1_rxpcsreset_in(gt1_rxpcsreset_in),
        .gt1_rxpmareset_in(gt1_rxpmareset_in),
        .gt1_rxpmaresetdone_out(gt1_rxpmaresetdone_out),
        .gt1_rxprbscntreset_in(gt1_rxprbscntreset_in),
        .gt1_rxprbserr_out(gt1_rxprbserr_out),
        .gt1_rxprbssel_in(gt1_rxprbssel_in),
        .gt1_rxresetdone_out(gt1_rxresetdone_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_dmonitorout_out(gt2_dmonitorout_out),
        .gt2_eyescandataerror_out(gt2_eyescandataerror_out),
        .gt2_eyescanreset_in(gt2_eyescanreset_in),
        .gt2_eyescantrigger_in(gt2_eyescantrigger_in),
        .gt2_rx_buf_err_out(gt2_rx_buf_err_out),
        .gt2_rx_disp_err_out(gt2_rx_disp_err_out),
        .gt2_rx_not_in_table_out(gt2_rx_not_in_table_out),
        .gt2_rx_realign_out(gt2_rx_realign_out),
        .gt2_rxbufreset_in(gt2_rxbufreset_in),
        .gt2_rxbufstatus_out(gt2_rxbufstatus_out),
        .gt2_rxbyteisaligned_out(gt2_rxbyteisaligned_out),
        .gt2_rxcdrhold_in(gt2_rxcdrhold_in),
        .gt2_rxcdrovrden_in(gt2_rxcdrovrden_in),
        .gt2_rxcommadet_out(gt2_rxcommadet_out),
        .gt2_rxdfelpmreset_in(gt2_rxdfelpmreset_in),
        .gt2_rxlpmen_in(gt2_rxlpmen_in),
        .gt2_rxmonitorout_out(gt2_rxmonitorout_out),
        .gt2_rxmonitorsel_in(gt2_rxmonitorsel_in),
        .gt2_rxpcsreset_in(gt2_rxpcsreset_in),
        .gt2_rxpmareset_in(gt2_rxpmareset_in),
        .gt2_rxpmaresetdone_out(gt2_rxpmaresetdone_out),
        .gt2_rxprbscntreset_in(gt2_rxprbscntreset_in),
        .gt2_rxprbserr_out(gt2_rxprbserr_out),
        .gt2_rxprbssel_in(gt2_rxprbssel_in),
        .gt2_rxresetdone_out(gt2_rxresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_dmonitorout_out(gt3_dmonitorout_out),
        .gt3_eyescandataerror_out(gt3_eyescandataerror_out),
        .gt3_eyescanreset_in(gt3_eyescanreset_in),
        .gt3_eyescantrigger_in(gt3_eyescantrigger_in),
        .gt3_rx_buf_err_out(gt3_rx_buf_err_out),
        .gt3_rx_disp_err_out(gt3_rx_disp_err_out),
        .gt3_rx_not_in_table_out(gt3_rx_not_in_table_out),
        .gt3_rx_realign_out(gt3_rx_realign_out),
        .gt3_rxbufreset_in(gt3_rxbufreset_in),
        .gt3_rxbufstatus_out(gt3_rxbufstatus_out),
        .gt3_rxbyteisaligned_out(gt3_rxbyteisaligned_out),
        .gt3_rxcdrhold_in(gt3_rxcdrhold_in),
        .gt3_rxcdrovrden_in(gt3_rxcdrovrden_in),
        .gt3_rxcommadet_out(gt3_rxcommadet_out),
        .gt3_rxdfelpmreset_in(gt3_rxdfelpmreset_in),
        .gt3_rxlpmen_in(gt3_rxlpmen_in),
        .gt3_rxmonitorout_out(gt3_rxmonitorout_out),
        .gt3_rxmonitorsel_in(gt3_rxmonitorsel_in),
        .gt3_rxpcsreset_in(gt3_rxpcsreset_in),
        .gt3_rxpmareset_in(gt3_rxpmareset_in),
        .gt3_rxpmaresetdone_out(gt3_rxpmaresetdone_out),
        .gt3_rxprbscntreset_in(gt3_rxprbscntreset_in),
        .gt3_rxprbserr_out(gt3_rxprbserr_out),
        .gt3_rxprbssel_in(gt3_rxprbssel_in),
        .gt3_rxresetdone_out(gt3_rxresetdone_out),
        .gt_qpllclk_quad2_in(gt_qpllclk_quad2_in),
        .gt_qpllclk_quad3_in(gt_qpllclk_quad3_in),
        .gt_qpllrefclk_quad2_in(gt_qpllrefclk_quad2_in),
        .gt_qpllrefclk_quad3_in(gt_qpllrefclk_quad3_in),
        .gt_refclk1(gt_refclk1),
        .init_clk_in(init_clk_in),
        .sync_clk(sync_clk),
        .sys_reset_out(sys_reset_out),
        .user_clk(user_clk));
  VCC VCC
       (.P(\<const1> ));
endmodule

module aurora_rx_4l_64b_GT_WRAPPER
   (gt0_cplllock_out,
    DRPRDY_OUT,
    gt0_eyescandataerror_out,
    gt0_rxbyteisaligned_out,
    gthe2_i,
    CHBONDDONE_OUT,
    gt0_rxcommadet_out,
    gt0_rxpmaresetdone_out,
    gt0_rxprbserr_out,
    gt0_rxresetdone_out,
    gt0_dmonitorout_out,
    DRPDO_OUT,
    gt0_rxbufstatus_out,
    gt0_rxmonitorout_out,
    D,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    gt1_cplllock_out,
    DRPRDY_OUT_LANE1,
    gt1_eyescandataerror_out,
    gt1_rxbyteisaligned_out,
    gthe2_i_0,
    CHBONDDONE_OUT_LANE1,
    gt1_rxcommadet_out,
    gt1_rxpmaresetdone_out,
    gt1_rxprbserr_out,
    gt1_rxresetdone_out,
    gt1_dmonitorout_out,
    DRPDO_OUT_LANE1,
    gt1_rxbufstatus_out,
    gt1_rxmonitorout_out,
    gthe2_i_1,
    gt1_rx_disp_err_out,
    gt1_rx_not_in_table_out,
    gt2_cplllock_out,
    DRPRDY_OUT_LANE2,
    gt2_eyescandataerror_out,
    gt2_rxbyteisaligned_out,
    gthe2_i_2,
    CHBONDDONE_OUT_LANE2,
    gt2_rxcommadet_out,
    gt2_rxpmaresetdone_out,
    gt2_rxprbserr_out,
    gt2_rxresetdone_out,
    TX_OUT_CLK,
    gt2_dmonitorout_out,
    DRPDO_OUT_LANE2,
    gt2_rxbufstatus_out,
    gt2_rxmonitorout_out,
    gthe2_i_3,
    gt2_rx_disp_err_out,
    gt2_rx_not_in_table_out,
    gt3_cplllock_out,
    DRPRDY_OUT_LANE3,
    gt3_eyescandataerror_out,
    gt3_rxbyteisaligned_out,
    gthe2_i_4,
    CHBONDDONE_OUT_LANE3,
    gt3_rxcommadet_out,
    gt3_rxpmaresetdone_out,
    gt3_rxprbserr_out,
    gt3_rxresetdone_out,
    gt3_dmonitorout_out,
    DRPDO_OUT_LANE3,
    gt3_rxbufstatus_out,
    gt3_rxmonitorout_out,
    gthe2_i_5,
    gt3_rx_disp_err_out,
    gt3_rx_not_in_table_out,
    RX_RESETDONE_OUT,
    link_reset_r,
    gthe2_i_6,
    gthe2_i_7,
    gthe2_i_8,
    gthe2_i_9,
    gthe2_i_10,
    gthe2_i_11,
    gthe2_i_12,
    gthe2_i_13,
    gthe2_i_14,
    gthe2_i_15,
    first_v_received_r_reg,
    hard_err_flop_r0,
    gthe2_i_16,
    gthe2_i_17,
    gthe2_i_18,
    gthe2_i_19,
    first_v_received_r_reg_0,
    hard_err_flop_r0_0,
    gthe2_i_20,
    gthe2_i_21,
    gthe2_i_22,
    gthe2_i_23,
    first_v_received_r_reg_1,
    hard_err_flop_r0_1,
    gthe2_i_24,
    gthe2_i_25,
    gthe2_i_26,
    gthe2_i_27,
    first_v_received_r_reg_2,
    hard_err_flop_r0_2,
    gthe2_i_28,
    gthe2_i_29,
    rxfsm_rxresetdone_r3_reg_0,
    TX_LOCK,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt0_eyescanreset_in,
    gt0_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    gt_qpllclk_quad2_in,
    gt_qpllrefclk_quad2_in,
    gt0_rxbufreset_in,
    gt0_rxcdrhold_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxlpmen_in,
    ena_comma_align_i_0,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    rx_polarity_i_0,
    gt0_rxprbscntreset_in,
    sync_clk,
    user_clk,
    DRPDI_IN,
    gt0_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt0_rxprbssel_in,
    DRPADDR_IN,
    DRPEN_IN_LANE1,
    DRPWE_IN_LANE1,
    gt1_eyescanreset_in,
    gt1_eyescantrigger_in,
    gt1_rxbufreset_in,
    gt1_rxcdrhold_in,
    gt1_rxcdrovrden_in,
    en_chan_sync_i,
    gt1_rxdfelpmreset_in,
    gt1_rxlpmen_in,
    ena_comma_align_i_1,
    gt1_rxpcsreset_in,
    gt1_rxpmareset_in,
    rx_polarity_i_1,
    gt1_rxprbscntreset_in,
    DRPDI_IN_LANE1,
    gt1_rxmonitorsel_in,
    gt1_rxprbssel_in,
    DRPADDR_IN_LANE1,
    DRPEN_IN_LANE2,
    DRPWE_IN_LANE2,
    gt2_eyescanreset_in,
    gt2_eyescantrigger_in,
    gt_qpllclk_quad3_in,
    gt_qpllrefclk_quad3_in,
    gt2_rxbufreset_in,
    gt2_rxcdrhold_in,
    gt2_rxcdrovrden_in,
    gt2_rxdfelpmreset_in,
    gt2_rxlpmen_in,
    ena_comma_align_i_2,
    gt2_rxpcsreset_in,
    gt2_rxpmareset_in,
    rx_polarity_i_2,
    gt2_rxprbscntreset_in,
    DRPDI_IN_LANE2,
    gt2_rxmonitorsel_in,
    gt2_rxprbssel_in,
    DRPADDR_IN_LANE2,
    DRPEN_IN_LANE3,
    DRPWE_IN_LANE3,
    gt3_eyescanreset_in,
    gt3_eyescantrigger_in,
    gt3_rxbufreset_in,
    gt3_rxcdrhold_in,
    gt3_rxcdrovrden_in,
    gt3_rxdfelpmreset_in,
    gt3_rxlpmen_in,
    ena_comma_align_i_3,
    gt3_rxpcsreset_in,
    gt3_rxpmareset_in,
    rx_polarity_i_3,
    gt3_rxprbscntreset_in,
    DRPDI_IN_LANE3,
    gt3_rxmonitorsel_in,
    gt3_rxprbssel_in,
    DRPADDR_IN_LANE3,
    gtrxreset_i,
    LINK_RESET_OUT,
    \word_aligned_control_bits_r_reg[1] ,
    \word_aligned_control_bits_r_reg[1]_0 ,
    \word_aligned_control_bits_r_reg[1]_1 ,
    \word_aligned_control_bits_r_reg[1]_2 ,
    gtp_rx_reset_i_0,
    comma_over_two_cycles_r,
    first_v_received_r,
    bucket_full_r,
    gtp_rx_reset_i_1,
    comma_over_two_cycles_r_3,
    first_v_received_r_4,
    bucket_full_r_5,
    gtp_rx_reset_i_2,
    comma_over_two_cycles_r_6,
    first_v_received_r_7,
    bucket_full_r_8,
    gtp_rx_reset_i_3,
    comma_over_two_cycles_r_9,
    first_v_received_r_10,
    bucket_full_r_11,
    out);
  output gt0_cplllock_out;
  output DRPRDY_OUT;
  output gt0_eyescandataerror_out;
  output gt0_rxbyteisaligned_out;
  output gthe2_i;
  output CHBONDDONE_OUT;
  output gt0_rxcommadet_out;
  output gt0_rxpmaresetdone_out;
  output gt0_rxprbserr_out;
  output gt0_rxresetdone_out;
  output [14:0]gt0_dmonitorout_out;
  output [15:0]DRPDO_OUT;
  output [2:0]gt0_rxbufstatus_out;
  output [6:0]gt0_rxmonitorout_out;
  output [1:0]D;
  output [1:0]gt0_rx_disp_err_out;
  output [1:0]gt0_rx_not_in_table_out;
  output gt1_cplllock_out;
  output DRPRDY_OUT_LANE1;
  output gt1_eyescandataerror_out;
  output gt1_rxbyteisaligned_out;
  output gthe2_i_0;
  output CHBONDDONE_OUT_LANE1;
  output gt1_rxcommadet_out;
  output gt1_rxpmaresetdone_out;
  output gt1_rxprbserr_out;
  output gt1_rxresetdone_out;
  output [14:0]gt1_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE1;
  output [2:0]gt1_rxbufstatus_out;
  output [6:0]gt1_rxmonitorout_out;
  output [1:0]gthe2_i_1;
  output [1:0]gt1_rx_disp_err_out;
  output [1:0]gt1_rx_not_in_table_out;
  output gt2_cplllock_out;
  output DRPRDY_OUT_LANE2;
  output gt2_eyescandataerror_out;
  output gt2_rxbyteisaligned_out;
  output gthe2_i_2;
  output CHBONDDONE_OUT_LANE2;
  output gt2_rxcommadet_out;
  output gt2_rxpmaresetdone_out;
  output gt2_rxprbserr_out;
  output gt2_rxresetdone_out;
  output TX_OUT_CLK;
  output [14:0]gt2_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE2;
  output [2:0]gt2_rxbufstatus_out;
  output [6:0]gt2_rxmonitorout_out;
  output [1:0]gthe2_i_3;
  output [1:0]gt2_rx_disp_err_out;
  output [1:0]gt2_rx_not_in_table_out;
  output gt3_cplllock_out;
  output DRPRDY_OUT_LANE3;
  output gt3_eyescandataerror_out;
  output gt3_rxbyteisaligned_out;
  output gthe2_i_4;
  output CHBONDDONE_OUT_LANE3;
  output gt3_rxcommadet_out;
  output gt3_rxpmaresetdone_out;
  output gt3_rxprbserr_out;
  output gt3_rxresetdone_out;
  output [14:0]gt3_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE3;
  output [2:0]gt3_rxbufstatus_out;
  output [6:0]gt3_rxmonitorout_out;
  output [1:0]gthe2_i_5;
  output [1:0]gt3_rx_disp_err_out;
  output [1:0]gt3_rx_not_in_table_out;
  output RX_RESETDONE_OUT;
  output link_reset_r;
  output gthe2_i_6;
  output gthe2_i_7;
  output gthe2_i_8;
  output gthe2_i_9;
  output gthe2_i_10;
  output gthe2_i_11;
  output gthe2_i_12;
  output gthe2_i_13;
  output gthe2_i_14;
  output [1:0]gthe2_i_15;
  output first_v_received_r_reg;
  output hard_err_flop_r0;
  output [7:0]gthe2_i_16;
  output [7:0]gthe2_i_17;
  output gthe2_i_18;
  output [1:0]gthe2_i_19;
  output first_v_received_r_reg_0;
  output hard_err_flop_r0_0;
  output [7:0]gthe2_i_20;
  output [7:0]gthe2_i_21;
  output gthe2_i_22;
  output [1:0]gthe2_i_23;
  output first_v_received_r_reg_1;
  output hard_err_flop_r0_1;
  output [7:0]gthe2_i_24;
  output [7:0]gthe2_i_25;
  output gthe2_i_26;
  output [1:0]gthe2_i_27;
  output first_v_received_r_reg_2;
  output hard_err_flop_r0_2;
  output [7:0]gthe2_i_28;
  output [7:0]gthe2_i_29;
  output rxfsm_rxresetdone_r3_reg_0;
  output TX_LOCK;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt0_eyescanreset_in;
  input gt0_eyescantrigger_in;
  input [0:3]RXN;
  input [0:3]RXP;
  input gt_refclk1;
  input gt_qpllclk_quad2_in;
  input gt_qpllrefclk_quad2_in;
  input gt0_rxbufreset_in;
  input gt0_rxcdrhold_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  input gt0_rxlpmen_in;
  input ena_comma_align_i_0;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  input rx_polarity_i_0;
  input gt0_rxprbscntreset_in;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN;
  input [1:0]gt0_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_rxprbssel_in;
  input [8:0]DRPADDR_IN;
  input DRPEN_IN_LANE1;
  input DRPWE_IN_LANE1;
  input gt1_eyescanreset_in;
  input gt1_eyescantrigger_in;
  input gt1_rxbufreset_in;
  input gt1_rxcdrhold_in;
  input gt1_rxcdrovrden_in;
  input en_chan_sync_i;
  input gt1_rxdfelpmreset_in;
  input gt1_rxlpmen_in;
  input ena_comma_align_i_1;
  input gt1_rxpcsreset_in;
  input gt1_rxpmareset_in;
  input rx_polarity_i_1;
  input gt1_rxprbscntreset_in;
  input [15:0]DRPDI_IN_LANE1;
  input [1:0]gt1_rxmonitorsel_in;
  input [2:0]gt1_rxprbssel_in;
  input [8:0]DRPADDR_IN_LANE1;
  input DRPEN_IN_LANE2;
  input DRPWE_IN_LANE2;
  input gt2_eyescanreset_in;
  input gt2_eyescantrigger_in;
  input gt_qpllclk_quad3_in;
  input gt_qpllrefclk_quad3_in;
  input gt2_rxbufreset_in;
  input gt2_rxcdrhold_in;
  input gt2_rxcdrovrden_in;
  input gt2_rxdfelpmreset_in;
  input gt2_rxlpmen_in;
  input ena_comma_align_i_2;
  input gt2_rxpcsreset_in;
  input gt2_rxpmareset_in;
  input rx_polarity_i_2;
  input gt2_rxprbscntreset_in;
  input [15:0]DRPDI_IN_LANE2;
  input [1:0]gt2_rxmonitorsel_in;
  input [2:0]gt2_rxprbssel_in;
  input [8:0]DRPADDR_IN_LANE2;
  input DRPEN_IN_LANE3;
  input DRPWE_IN_LANE3;
  input gt3_eyescanreset_in;
  input gt3_eyescantrigger_in;
  input gt3_rxbufreset_in;
  input gt3_rxcdrhold_in;
  input gt3_rxcdrovrden_in;
  input gt3_rxdfelpmreset_in;
  input gt3_rxlpmen_in;
  input ena_comma_align_i_3;
  input gt3_rxpcsreset_in;
  input gt3_rxpmareset_in;
  input rx_polarity_i_3;
  input gt3_rxprbscntreset_in;
  input [15:0]DRPDI_IN_LANE3;
  input [1:0]gt3_rxmonitorsel_in;
  input [2:0]gt3_rxprbssel_in;
  input [8:0]DRPADDR_IN_LANE3;
  input gtrxreset_i;
  input LINK_RESET_OUT;
  input \word_aligned_control_bits_r_reg[1] ;
  input \word_aligned_control_bits_r_reg[1]_0 ;
  input \word_aligned_control_bits_r_reg[1]_1 ;
  input \word_aligned_control_bits_r_reg[1]_2 ;
  input gtp_rx_reset_i_0;
  input comma_over_two_cycles_r;
  input first_v_received_r;
  input bucket_full_r;
  input gtp_rx_reset_i_1;
  input comma_over_two_cycles_r_3;
  input first_v_received_r_4;
  input bucket_full_r_5;
  input gtp_rx_reset_i_2;
  input comma_over_two_cycles_r_6;
  input first_v_received_r_7;
  input bucket_full_r_8;
  input gtp_rx_reset_i_3;
  input comma_over_two_cycles_r_9;
  input first_v_received_r_10;
  input bucket_full_r_11;
  input out;

  wire CHBONDDONE_OUT;
  wire CHBONDDONE_OUT_LANE1;
  wire CHBONDDONE_OUT_LANE2;
  wire CHBONDDONE_OUT_LANE3;
  wire CPLLLOCK;
  wire [1:0]D;
  wire [8:0]DRPADDR_IN;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT;
  wire [15:0]DRPDO_OUT_LANE1;
  wire [15:0]DRPDO_OUT_LANE2;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN;
  wire DRPEN_IN_LANE1;
  wire DRPEN_IN_LANE2;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT;
  wire DRPRDY_OUT_LANE1;
  wire DRPRDY_OUT_LANE2;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN;
  wire DRPWE_IN_LANE1;
  wire DRPWE_IN_LANE2;
  wire DRPWE_IN_LANE3;
  wire LINK_RESET_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [0:3]RXN;
  wire [0:3]RXP;
  wire RX_RESETDONE_OUT;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire bucket_full_r;
  wire bucket_full_r_11;
  wire bucket_full_r_5;
  wire bucket_full_r_8;
  wire comma_over_two_cycles_r;
  wire comma_over_two_cycles_r_3;
  wire comma_over_two_cycles_r_6;
  wire comma_over_two_cycles_r_9;
  wire cpll_reset_i;
  wire drpclk_in;
  wire en_chan_sync_i;
  wire ena_comma_align_i_0;
  wire ena_comma_align_i_1;
  wire ena_comma_align_i_2;
  wire ena_comma_align_i_3;
  wire first_v_received_r;
  wire first_v_received_r_10;
  wire first_v_received_r_4;
  wire first_v_received_r_7;
  wire first_v_received_r_reg;
  wire first_v_received_r_reg_0;
  wire first_v_received_r_reg_1;
  wire first_v_received_r_reg_2;
  wire fsm_gt_rx_reset_t;
  wire gt0_cplllock_out;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire [1:0]gt0_rx_disp_err_out;
  wire [1:0]gt0_rx_not_in_table_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt0_rxresetdone_r2_reg_srl2_n_0;
  wire gt0_rxresetdone_r3;
  wire gt1_cplllock_out;
  wire [14:0]gt1_dmonitorout_out;
  wire gt1_eyescandataerror_out;
  wire gt1_eyescanreset_in;
  wire gt1_eyescantrigger_in;
  wire [1:0]gt1_rx_disp_err_out;
  wire [1:0]gt1_rx_not_in_table_out;
  wire gt1_rxbufreset_in;
  wire [2:0]gt1_rxbufstatus_out;
  wire gt1_rxbyteisaligned_out;
  wire gt1_rxcdrhold_in;
  wire gt1_rxcdrovrden_in;
  wire gt1_rxcommadet_out;
  wire gt1_rxdfelpmreset_in;
  wire gt1_rxlpmen_in;
  wire [6:0]gt1_rxmonitorout_out;
  wire [1:0]gt1_rxmonitorsel_in;
  wire gt1_rxpcsreset_in;
  wire gt1_rxpmareset_in;
  wire gt1_rxpmaresetdone_out;
  wire gt1_rxprbscntreset_in;
  wire gt1_rxprbserr_out;
  wire [2:0]gt1_rxprbssel_in;
  wire gt1_rxresetdone_out;
  wire gt1_rxresetdone_r2_reg_srl2_n_0;
  wire gt1_rxresetdone_r3;
  wire gt2_cplllock_out;
  wire [14:0]gt2_dmonitorout_out;
  wire gt2_eyescandataerror_out;
  wire gt2_eyescanreset_in;
  wire gt2_eyescantrigger_in;
  wire [1:0]gt2_rx_disp_err_out;
  wire [1:0]gt2_rx_not_in_table_out;
  wire gt2_rxbufreset_in;
  wire [2:0]gt2_rxbufstatus_out;
  wire gt2_rxbyteisaligned_out;
  wire gt2_rxcdrhold_in;
  wire gt2_rxcdrovrden_in;
  wire gt2_rxcommadet_out;
  wire gt2_rxdfelpmreset_in;
  wire gt2_rxlpmen_in;
  wire [6:0]gt2_rxmonitorout_out;
  wire [1:0]gt2_rxmonitorsel_in;
  wire gt2_rxpcsreset_in;
  wire gt2_rxpmareset_in;
  wire gt2_rxpmaresetdone_out;
  wire gt2_rxprbscntreset_in;
  wire gt2_rxprbserr_out;
  wire [2:0]gt2_rxprbssel_in;
  wire gt2_rxresetdone_out;
  wire gt2_rxresetdone_r2_reg_srl2_n_0;
  wire gt2_rxresetdone_r3;
  wire gt3_cplllock_out;
  wire [14:0]gt3_dmonitorout_out;
  wire gt3_eyescandataerror_out;
  wire gt3_eyescanreset_in;
  wire gt3_eyescantrigger_in;
  wire [1:0]gt3_rx_disp_err_out;
  wire [1:0]gt3_rx_not_in_table_out;
  wire gt3_rxbufreset_in;
  wire [2:0]gt3_rxbufstatus_out;
  wire gt3_rxbyteisaligned_out;
  wire gt3_rxcdrhold_in;
  wire gt3_rxcdrovrden_in;
  wire gt3_rxcommadet_out;
  wire gt3_rxdfelpmreset_in;
  wire gt3_rxlpmen_in;
  wire [6:0]gt3_rxmonitorout_out;
  wire [1:0]gt3_rxmonitorsel_in;
  wire gt3_rxpcsreset_in;
  wire gt3_rxpmareset_in;
  wire gt3_rxpmaresetdone_out;
  wire gt3_rxprbscntreset_in;
  wire gt3_rxprbserr_out;
  wire [2:0]gt3_rxprbssel_in;
  wire gt3_rxresetdone_out;
  wire gt3_rxresetdone_r2_reg_srl2_n_0;
  wire gt3_rxresetdone_r3;
  wire gt_qpllclk_quad2_in;
  wire gt_qpllclk_quad3_in;
  wire gt_qpllrefclk_quad2_in;
  wire gt_qpllrefclk_quad3_in;
  wire gt_refclk1;
  wire gt_rx_reset_i;
  wire gt_rxresetfsm_i_n_3;
  wire gt_rxuserrdy_i;
  wire gthe2_i;
  wire gthe2_i_0;
  wire [1:0]gthe2_i_1;
  wire gthe2_i_10;
  wire gthe2_i_11;
  wire gthe2_i_12;
  wire gthe2_i_13;
  wire gthe2_i_14;
  wire [1:0]gthe2_i_15;
  wire [7:0]gthe2_i_16;
  wire [7:0]gthe2_i_17;
  wire gthe2_i_18;
  wire [1:0]gthe2_i_19;
  wire gthe2_i_2;
  wire [7:0]gthe2_i_20;
  wire [7:0]gthe2_i_21;
  wire gthe2_i_22;
  wire [1:0]gthe2_i_23;
  wire [7:0]gthe2_i_24;
  wire [7:0]gthe2_i_25;
  wire gthe2_i_26;
  wire [1:0]gthe2_i_27;
  wire [7:0]gthe2_i_28;
  wire [7:0]gthe2_i_29;
  wire [1:0]gthe2_i_3;
  wire gthe2_i_4;
  wire [1:0]gthe2_i_5;
  wire gthe2_i_6;
  wire gthe2_i_7;
  wire gthe2_i_8;
  wire gthe2_i_9;
  wire gtp_rx_reset_i_0;
  wire gtp_rx_reset_i_1;
  wire gtp_rx_reset_i_2;
  wire gtp_rx_reset_i_3;
  wire gtrxreset_i;
  wire gtrxreset_pulse;
  wire gtrxreset_pulse0;
  wire gtrxreset_r1;
  wire gtrxreset_r2;
  wire gtrxreset_r3;
  wire gtrxreset_sync;
  wire hard_err_flop_r0;
  wire hard_err_flop_r0_0;
  wire hard_err_flop_r0_1;
  wire hard_err_flop_r0_2;
  wire init_clk_in;
  wire link_reset_r;
  wire link_reset_r2;
  wire out;
  wire [10:0]rx_cdrlock_counter;
  wire \rx_cdrlock_counter[0]_i_2_n_0 ;
  wire \rx_cdrlock_counter[0]_i_3_n_0 ;
  wire \rx_cdrlock_counter[10]_i_2_n_0 ;
  wire \rx_cdrlock_counter_reg_n_0_[0] ;
  wire \rx_cdrlock_counter_reg_n_0_[10] ;
  wire \rx_cdrlock_counter_reg_n_0_[1] ;
  wire \rx_cdrlock_counter_reg_n_0_[2] ;
  wire \rx_cdrlock_counter_reg_n_0_[3] ;
  wire \rx_cdrlock_counter_reg_n_0_[4] ;
  wire \rx_cdrlock_counter_reg_n_0_[5] ;
  wire \rx_cdrlock_counter_reg_n_0_[6] ;
  wire \rx_cdrlock_counter_reg_n_0_[7] ;
  wire \rx_cdrlock_counter_reg_n_0_[8] ;
  wire \rx_cdrlock_counter_reg_n_0_[9] ;
  wire rx_cdrlocked_i_1_n_0;
  wire rx_cdrlocked_reg_n_0;
  wire rx_polarity_i_0;
  wire rx_polarity_i_1;
  wire rx_polarity_i_2;
  wire rx_polarity_i_3;
  wire rxfsm_rxresetdone_i__0;
  wire rxfsm_rxresetdone_r;
  wire rxfsm_rxresetdone_r2;
  wire rxfsm_rxresetdone_r3_reg_0;
  wire rxfsm_soft_reset_r;
  wire rxfsm_soft_reset_r_i_1_n_0;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire \word_aligned_control_bits_r_reg[1]_0 ;
  wire \word_aligned_control_bits_r_reg[1]_1 ;
  wire \word_aligned_control_bits_r_reg[1]_2 ;

  aurora_rx_4l_64b_multi_gt aurora_rx_4l_64b_multi_gt_i
       (.CHBONDDONE_OUT(CHBONDDONE_OUT),
        .CHBONDDONE_OUT_LANE1(CHBONDDONE_OUT_LANE1),
        .CHBONDDONE_OUT_LANE2(CHBONDDONE_OUT_LANE2),
        .CHBONDDONE_OUT_LANE3(CHBONDDONE_OUT_LANE3),
        .D(D),
        .DRPADDR_IN(DRPADDR_IN),
        .DRPADDR_IN_LANE1(DRPADDR_IN_LANE1),
        .DRPADDR_IN_LANE2(DRPADDR_IN_LANE2),
        .DRPADDR_IN_LANE3(DRPADDR_IN_LANE3),
        .DRPDI_IN(DRPDI_IN),
        .DRPDI_IN_LANE1(DRPDI_IN_LANE1),
        .DRPDI_IN_LANE2(DRPDI_IN_LANE2),
        .DRPDI_IN_LANE3(DRPDI_IN_LANE3),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPDO_OUT_LANE1(DRPDO_OUT_LANE1),
        .DRPDO_OUT_LANE2(DRPDO_OUT_LANE2),
        .DRPDO_OUT_LANE3(DRPDO_OUT_LANE3),
        .DRPEN_IN(DRPEN_IN),
        .DRPEN_IN_LANE1(DRPEN_IN_LANE1),
        .DRPEN_IN_LANE2(DRPEN_IN_LANE2),
        .DRPEN_IN_LANE3(DRPEN_IN_LANE3),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPRDY_OUT_LANE1(DRPRDY_OUT_LANE1),
        .DRPRDY_OUT_LANE2(DRPRDY_OUT_LANE2),
        .DRPRDY_OUT_LANE3(DRPRDY_OUT_LANE3),
        .DRPWE_IN(DRPWE_IN),
        .DRPWE_IN_LANE1(DRPWE_IN_LANE1),
        .DRPWE_IN_LANE2(DRPWE_IN_LANE2),
        .DRPWE_IN_LANE3(DRPWE_IN_LANE3),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXN(RXN),
        .RXP(RXP),
        .SR(gt_rx_reset_i),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .bucket_full_r(bucket_full_r),
        .bucket_full_r_11(bucket_full_r_11),
        .bucket_full_r_5(bucket_full_r_5),
        .bucket_full_r_8(bucket_full_r_8),
        .comma_over_two_cycles_r(comma_over_two_cycles_r),
        .comma_over_two_cycles_r_3(comma_over_two_cycles_r_3),
        .comma_over_two_cycles_r_6(comma_over_two_cycles_r_6),
        .comma_over_two_cycles_r_9(comma_over_two_cycles_r_9),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .en_chan_sync_i(en_chan_sync_i),
        .ena_comma_align_i_0(ena_comma_align_i_0),
        .ena_comma_align_i_1(ena_comma_align_i_1),
        .ena_comma_align_i_2(ena_comma_align_i_2),
        .ena_comma_align_i_3(ena_comma_align_i_3),
        .first_v_received_r(first_v_received_r),
        .first_v_received_r_10(first_v_received_r_10),
        .first_v_received_r_4(first_v_received_r_4),
        .first_v_received_r_7(first_v_received_r_7),
        .first_v_received_r_reg(first_v_received_r_reg),
        .first_v_received_r_reg_0(first_v_received_r_reg_0),
        .first_v_received_r_reg_1(first_v_received_r_reg_1),
        .first_v_received_r_reg_2(first_v_received_r_reg_2),
        .flag2_reg(gt_rxresetfsm_i_n_3),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out(gt0_rxbufstatus_out),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_dmonitorout_out(gt1_dmonitorout_out),
        .gt1_eyescandataerror_out(gt1_eyescandataerror_out),
        .gt1_eyescanreset_in(gt1_eyescanreset_in),
        .gt1_eyescantrigger_in(gt1_eyescantrigger_in),
        .gt1_rx_disp_err_out(gt1_rx_disp_err_out),
        .gt1_rx_not_in_table_out(gt1_rx_not_in_table_out),
        .gt1_rxbufreset_in(gt1_rxbufreset_in),
        .gt1_rxbufstatus_out(gt1_rxbufstatus_out),
        .gt1_rxbyteisaligned_out(gt1_rxbyteisaligned_out),
        .gt1_rxcdrhold_in(gt1_rxcdrhold_in),
        .gt1_rxcdrovrden_in(gt1_rxcdrovrden_in),
        .gt1_rxcommadet_out(gt1_rxcommadet_out),
        .gt1_rxdfelpmreset_in(gt1_rxdfelpmreset_in),
        .gt1_rxlpmen_in(gt1_rxlpmen_in),
        .gt1_rxmonitorout_out(gt1_rxmonitorout_out),
        .gt1_rxmonitorsel_in(gt1_rxmonitorsel_in),
        .gt1_rxpcsreset_in(gt1_rxpcsreset_in),
        .gt1_rxpmareset_in(gt1_rxpmareset_in),
        .gt1_rxpmaresetdone_out(gt1_rxpmaresetdone_out),
        .gt1_rxprbscntreset_in(gt1_rxprbscntreset_in),
        .gt1_rxprbserr_out(gt1_rxprbserr_out),
        .gt1_rxprbssel_in(gt1_rxprbssel_in),
        .gt1_rxresetdone_out(gt1_rxresetdone_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_dmonitorout_out(gt2_dmonitorout_out),
        .gt2_eyescandataerror_out(gt2_eyescandataerror_out),
        .gt2_eyescanreset_in(gt2_eyescanreset_in),
        .gt2_eyescantrigger_in(gt2_eyescantrigger_in),
        .gt2_rx_disp_err_out(gt2_rx_disp_err_out),
        .gt2_rx_not_in_table_out(gt2_rx_not_in_table_out),
        .gt2_rxbufreset_in(gt2_rxbufreset_in),
        .gt2_rxbufstatus_out(gt2_rxbufstatus_out),
        .gt2_rxbyteisaligned_out(gt2_rxbyteisaligned_out),
        .gt2_rxcdrhold_in(gt2_rxcdrhold_in),
        .gt2_rxcdrovrden_in(gt2_rxcdrovrden_in),
        .gt2_rxcommadet_out(gt2_rxcommadet_out),
        .gt2_rxdfelpmreset_in(gt2_rxdfelpmreset_in),
        .gt2_rxlpmen_in(gt2_rxlpmen_in),
        .gt2_rxmonitorout_out(gt2_rxmonitorout_out),
        .gt2_rxmonitorsel_in(gt2_rxmonitorsel_in),
        .gt2_rxpcsreset_in(gt2_rxpcsreset_in),
        .gt2_rxpmareset_in(gt2_rxpmareset_in),
        .gt2_rxpmaresetdone_out(gt2_rxpmaresetdone_out),
        .gt2_rxprbscntreset_in(gt2_rxprbscntreset_in),
        .gt2_rxprbserr_out(gt2_rxprbserr_out),
        .gt2_rxprbssel_in(gt2_rxprbssel_in),
        .gt2_rxresetdone_out(gt2_rxresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_dmonitorout_out(gt3_dmonitorout_out),
        .gt3_eyescandataerror_out(gt3_eyescandataerror_out),
        .gt3_eyescanreset_in(gt3_eyescanreset_in),
        .gt3_eyescantrigger_in(gt3_eyescantrigger_in),
        .gt3_rx_disp_err_out(gt3_rx_disp_err_out),
        .gt3_rx_not_in_table_out(gt3_rx_not_in_table_out),
        .gt3_rxbufreset_in(gt3_rxbufreset_in),
        .gt3_rxbufstatus_out(gt3_rxbufstatus_out),
        .gt3_rxbyteisaligned_out(gt3_rxbyteisaligned_out),
        .gt3_rxcdrhold_in(gt3_rxcdrhold_in),
        .gt3_rxcdrovrden_in(gt3_rxcdrovrden_in),
        .gt3_rxcommadet_out(gt3_rxcommadet_out),
        .gt3_rxdfelpmreset_in(gt3_rxdfelpmreset_in),
        .gt3_rxlpmen_in(gt3_rxlpmen_in),
        .gt3_rxmonitorout_out(gt3_rxmonitorout_out),
        .gt3_rxmonitorsel_in(gt3_rxmonitorsel_in),
        .gt3_rxpcsreset_in(gt3_rxpcsreset_in),
        .gt3_rxpmareset_in(gt3_rxpmareset_in),
        .gt3_rxpmaresetdone_out(gt3_rxpmaresetdone_out),
        .gt3_rxprbscntreset_in(gt3_rxprbscntreset_in),
        .gt3_rxprbserr_out(gt3_rxprbserr_out),
        .gt3_rxprbssel_in(gt3_rxprbssel_in),
        .gt3_rxresetdone_out(gt3_rxresetdone_out),
        .gt_qpllclk_quad2_in(gt_qpllclk_quad2_in),
        .gt_qpllclk_quad3_in(gt_qpllclk_quad3_in),
        .gt_qpllrefclk_quad2_in(gt_qpllrefclk_quad2_in),
        .gt_qpllrefclk_quad3_in(gt_qpllrefclk_quad3_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gthe2_i(gthe2_i),
        .gthe2_i_0(gthe2_i_0),
        .gthe2_i_1(gthe2_i_1),
        .gthe2_i_10(gthe2_i_10),
        .gthe2_i_11(gthe2_i_11),
        .gthe2_i_12(gthe2_i_12),
        .gthe2_i_13(gthe2_i_13),
        .gthe2_i_14(gthe2_i_14),
        .gthe2_i_15(gthe2_i_15),
        .gthe2_i_16(gthe2_i_16),
        .gthe2_i_17(gthe2_i_17),
        .gthe2_i_18(gthe2_i_18),
        .gthe2_i_19(gthe2_i_19),
        .gthe2_i_2(gthe2_i_2),
        .gthe2_i_20(gthe2_i_20),
        .gthe2_i_21(gthe2_i_21),
        .gthe2_i_22(gthe2_i_22),
        .gthe2_i_23(gthe2_i_23),
        .gthe2_i_24(gthe2_i_24),
        .gthe2_i_25(gthe2_i_25),
        .gthe2_i_26(gthe2_i_26),
        .gthe2_i_27(gthe2_i_27),
        .gthe2_i_28(gthe2_i_28),
        .gthe2_i_29(gthe2_i_29),
        .gthe2_i_3(gthe2_i_3),
        .gthe2_i_4(gthe2_i_4),
        .gthe2_i_5(gthe2_i_5),
        .gthe2_i_6(gthe2_i_6),
        .gthe2_i_7(gthe2_i_7),
        .gthe2_i_8(gthe2_i_8),
        .gthe2_i_9(gthe2_i_9),
        .gtp_rx_reset_i_0(gtp_rx_reset_i_0),
        .gtp_rx_reset_i_1(gtp_rx_reset_i_1),
        .gtp_rx_reset_i_2(gtp_rx_reset_i_2),
        .gtp_rx_reset_i_3(gtp_rx_reset_i_3),
        .hard_err_flop_r0(hard_err_flop_r0),
        .hard_err_flop_r0_0(hard_err_flop_r0_0),
        .hard_err_flop_r0_1(hard_err_flop_r0_1),
        .hard_err_flop_r0_2(hard_err_flop_r0_2),
        .init_clk_in(init_clk_in),
        .rx_polarity_i_0(rx_polarity_i_0),
        .rx_polarity_i_1(rx_polarity_i_1),
        .rx_polarity_i_2(rx_polarity_i_2),
        .rx_polarity_i_3(rx_polarity_i_3),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[1] (\word_aligned_control_bits_r_reg[1] ),
        .\word_aligned_control_bits_r_reg[1]_0 (\word_aligned_control_bits_r_reg[1]_0 ),
        .\word_aligned_control_bits_r_reg[1]_1 (\word_aligned_control_bits_r_reg[1]_1 ),
        .\word_aligned_control_bits_r_reg[1]_2 (\word_aligned_control_bits_r_reg[1]_2 ));
  (* srl_name = "U0/\gt_wrapper_i/gt0_rxresetdone_r2_reg_srl2 " *) 
  SRL16E gt0_rxresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt0_rxresetdone_out),
        .Q(gt0_rxresetdone_r2_reg_srl2_n_0));
  FDRE gt0_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt0_rxresetdone_r2_reg_srl2_n_0),
        .Q(gt0_rxresetdone_r3),
        .R(1'b0));
  (* srl_name = "U0/\gt_wrapper_i/gt1_rxresetdone_r2_reg_srl2 " *) 
  SRL16E gt1_rxresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt1_rxresetdone_out),
        .Q(gt1_rxresetdone_r2_reg_srl2_n_0));
  FDRE gt1_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt1_rxresetdone_r2_reg_srl2_n_0),
        .Q(gt1_rxresetdone_r3),
        .R(1'b0));
  (* srl_name = "U0/\gt_wrapper_i/gt2_rxresetdone_r2_reg_srl2 " *) 
  SRL16E gt2_rxresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt2_rxresetdone_out),
        .Q(gt2_rxresetdone_r2_reg_srl2_n_0));
  FDRE gt2_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt2_rxresetdone_r2_reg_srl2_n_0),
        .Q(gt2_rxresetdone_r3),
        .R(1'b0));
  (* srl_name = "U0/\gt_wrapper_i/gt3_rxresetdone_r2_reg_srl2 " *) 
  SRL16E gt3_rxresetdone_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(gt3_rxresetdone_out),
        .Q(gt3_rxresetdone_r2_reg_srl2_n_0));
  FDRE gt3_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt3_rxresetdone_r2_reg_srl2_n_0),
        .Q(gt3_rxresetdone_r3),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    gt_pll_lock_i
       (.I0(gt3_cplllock_out),
        .I1(gt0_cplllock_out),
        .I2(gt1_cplllock_out),
        .I3(gt2_cplllock_out),
        .O(CPLLLOCK));
  (* equivalent_register_removal = "no" *) 
  FDRE gt_rx_reset_i_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(fsm_gt_rx_reset_t),
        .Q(gt_rx_reset_i),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    gt_rxresetdone_r_i_1
       (.I0(RX_RESETDONE_OUT),
        .O(rxfsm_rxresetdone_r3_reg_0));
  aurora_rx_4l_64b_rx_startup_fsm gt_rxresetfsm_i
       (.AR(rxfsm_soft_reset_r),
        .CPLL_RESET_reg_0(gt_rxresetfsm_i_n_3),
        .cpll_reset_i(cpll_reset_i),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .in0(CPLLLOCK),
        .init_clk_in(init_clk_in),
        .reset_time_out_reg_0(rx_cdrlocked_reg_n_0),
        .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync__parameterized2_21 gtrxreset_cdc_sync
       (.gtrxreset_i(gtrxreset_i),
        .init_clk_in(init_clk_in),
        .out(gtrxreset_sync),
        .user_clk(user_clk));
  LUT2 #(
    .INIT(4'h2)) 
    gtrxreset_pulse_i_1
       (.I0(gtrxreset_r2),
        .I1(gtrxreset_r3),
        .O(gtrxreset_pulse0));
  FDRE gtrxreset_pulse_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_pulse0),
        .Q(gtrxreset_pulse),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE gtrxreset_r1_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_sync),
        .Q(gtrxreset_r1),
        .R(1'b0));
  FDRE gtrxreset_r2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_r1),
        .Q(gtrxreset_r2),
        .R(1'b0));
  FDRE gtrxreset_r3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_r2),
        .Q(gtrxreset_r3),
        .R(1'b0));
  FDRE link_reset_r2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(link_reset_r2),
        .R(1'b0));
  FDRE link_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(LINK_RESET_OUT),
        .Q(link_reset_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFFFFBF)) 
    \rx_cdrlock_counter[0]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[6] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[5] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[1] ),
        .I3(\rx_cdrlock_counter[0]_i_2_n_0 ),
        .I4(\rx_cdrlock_counter[0]_i_3_n_0 ),
        .I5(\rx_cdrlock_counter_reg_n_0_[0] ),
        .O(rx_cdrlock_counter[0]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    \rx_cdrlock_counter[0]_i_2 
       (.I0(\rx_cdrlock_counter_reg_n_0_[10] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[0] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[2] ),
        .I3(\rx_cdrlock_counter_reg_n_0_[4] ),
        .O(\rx_cdrlock_counter[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \rx_cdrlock_counter[0]_i_3 
       (.I0(\rx_cdrlock_counter_reg_n_0_[7] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[9] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[8] ),
        .I3(\rx_cdrlock_counter_reg_n_0_[3] ),
        .O(\rx_cdrlock_counter[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rx_cdrlock_counter[10]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[10] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[8] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[6] ),
        .I3(\rx_cdrlock_counter[10]_i_2_n_0 ),
        .I4(\rx_cdrlock_counter_reg_n_0_[7] ),
        .I5(\rx_cdrlock_counter_reg_n_0_[9] ),
        .O(rx_cdrlock_counter[10]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_cdrlock_counter[10]_i_2 
       (.I0(\rx_cdrlock_counter_reg_n_0_[5] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[4] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[2] ),
        .I3(\rx_cdrlock_counter_reg_n_0_[0] ),
        .I4(\rx_cdrlock_counter_reg_n_0_[1] ),
        .I5(\rx_cdrlock_counter_reg_n_0_[3] ),
        .O(\rx_cdrlock_counter[10]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rx_cdrlock_counter[1]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[0] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[1] ),
        .O(rx_cdrlock_counter[1]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \rx_cdrlock_counter[2]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[2] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[0] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[1] ),
        .O(rx_cdrlock_counter[2]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rx_cdrlock_counter[3]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[3] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[1] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[0] ),
        .I3(\rx_cdrlock_counter_reg_n_0_[2] ),
        .O(rx_cdrlock_counter[3]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rx_cdrlock_counter[4]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[4] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[2] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[0] ),
        .I3(\rx_cdrlock_counter_reg_n_0_[1] ),
        .I4(\rx_cdrlock_counter_reg_n_0_[3] ),
        .O(rx_cdrlock_counter[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \rx_cdrlock_counter[5]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[3] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[1] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[0] ),
        .I3(\rx_cdrlock_counter_reg_n_0_[2] ),
        .I4(\rx_cdrlock_counter_reg_n_0_[4] ),
        .I5(\rx_cdrlock_counter_reg_n_0_[5] ),
        .O(rx_cdrlock_counter[5]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rx_cdrlock_counter[6]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[6] ),
        .I1(\rx_cdrlock_counter[10]_i_2_n_0 ),
        .O(rx_cdrlock_counter[6]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \rx_cdrlock_counter[7]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[7] ),
        .I1(\rx_cdrlock_counter[10]_i_2_n_0 ),
        .I2(\rx_cdrlock_counter_reg_n_0_[6] ),
        .O(rx_cdrlock_counter[7]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rx_cdrlock_counter[8]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[8] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[6] ),
        .I2(\rx_cdrlock_counter[10]_i_2_n_0 ),
        .I3(\rx_cdrlock_counter_reg_n_0_[7] ),
        .O(rx_cdrlock_counter[8]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rx_cdrlock_counter[9]_i_1 
       (.I0(\rx_cdrlock_counter_reg_n_0_[9] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[7] ),
        .I2(\rx_cdrlock_counter[10]_i_2_n_0 ),
        .I3(\rx_cdrlock_counter_reg_n_0_[6] ),
        .I4(\rx_cdrlock_counter_reg_n_0_[8] ),
        .O(rx_cdrlock_counter[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[0] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[0]),
        .Q(\rx_cdrlock_counter_reg_n_0_[0] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[10] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[10]),
        .Q(\rx_cdrlock_counter_reg_n_0_[10] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[1] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[1]),
        .Q(\rx_cdrlock_counter_reg_n_0_[1] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[2] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[2]),
        .Q(\rx_cdrlock_counter_reg_n_0_[2] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[3] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[3]),
        .Q(\rx_cdrlock_counter_reg_n_0_[3] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[4] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[4]),
        .Q(\rx_cdrlock_counter_reg_n_0_[4] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[5] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[5]),
        .Q(\rx_cdrlock_counter_reg_n_0_[5] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[6] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[6]),
        .Q(\rx_cdrlock_counter_reg_n_0_[6] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[7] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[7]),
        .Q(\rx_cdrlock_counter_reg_n_0_[7] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[8] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[8]),
        .Q(\rx_cdrlock_counter_reg_n_0_[8] ),
        .R(gt_rx_reset_i));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cdrlock_counter_reg[9] 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlock_counter[9]),
        .Q(\rx_cdrlock_counter_reg_n_0_[9] ),
        .R(gt_rx_reset_i));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000040)) 
    rx_cdrlocked_i_1
       (.I0(\rx_cdrlock_counter_reg_n_0_[6] ),
        .I1(\rx_cdrlock_counter_reg_n_0_[5] ),
        .I2(\rx_cdrlock_counter_reg_n_0_[1] ),
        .I3(\rx_cdrlock_counter[0]_i_2_n_0 ),
        .I4(\rx_cdrlock_counter[0]_i_3_n_0 ),
        .I5(rx_cdrlocked_reg_n_0),
        .O(rx_cdrlocked_i_1_n_0));
  FDRE rx_cdrlocked_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_cdrlocked_i_1_n_0),
        .Q(rx_cdrlocked_reg_n_0),
        .R(gt_rx_reset_i));
  LUT4 #(
    .INIT(16'h8000)) 
    rxfsm_rxresetdone_i
       (.I0(gt3_rxresetdone_r3),
        .I1(gt0_rxresetdone_r3),
        .I2(gt1_rxresetdone_r3),
        .I3(gt2_rxresetdone_r3),
        .O(rxfsm_rxresetdone_i__0));
  (* equivalent_register_removal = "no" *) 
  FDRE rxfsm_rxresetdone_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rxfsm_rxresetdone_r),
        .Q(rxfsm_rxresetdone_r2),
        .R(1'b0));
  FDRE rxfsm_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rxfsm_rxresetdone_r2),
        .Q(RX_RESETDONE_OUT),
        .R(1'b0));
  FDRE rxfsm_rxresetdone_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rxfsm_rxresetdone_i__0),
        .Q(rxfsm_rxresetdone_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    rxfsm_soft_reset_r_i_1
       (.I0(out),
        .I1(gtrxreset_pulse),
        .I2(link_reset_r2),
        .O(rxfsm_soft_reset_r_i_1_n_0));
  FDRE rxfsm_soft_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rxfsm_soft_reset_r_i_1_n_0),
        .Q(rxfsm_soft_reset_r),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_HOTPLUG
   (LINK_RESET_OUT,
    user_clk,
    init_clk_in,
    HPCNT_RESET,
    link_reset_lane0_i,
    link_reset_lane1_i,
    link_reset_lane2_i,
    SR,
    D);
  output LINK_RESET_OUT;
  input user_clk;
  input init_clk_in;
  input HPCNT_RESET;
  input link_reset_lane0_i;
  input link_reset_lane1_i;
  input link_reset_lane2_i;
  input [0:0]SR;
  input [0:0]D;

  wire [0:0]D;
  wire HPCNT_RESET;
  wire LINK_RESET_OUT;
  wire [0:0]SR;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire init_clk_in;
  wire link_reset_0;
  wire link_reset_lane0_i;
  wire link_reset_lane1_i;
  wire link_reset_lane2_i;
  wire link_reset_lane3_i;
  wire link_reset_r;
  wire link_reset_r_i_2__2_n_0;
  wire link_reset_r_i_3__2_n_0;
  wire link_reset_r_i_4__2_n_0;
  wire link_reset_r_i_5__2_n_0;
  wire link_reset_r_i_6__2_n_0;
  wire rx_cc_cdc_sync_n_0;
  wire rx_cc_cdc_sync_n_1;
  wire rx_cc_cdc_sync_n_10;
  wire rx_cc_cdc_sync_n_11;
  wire rx_cc_cdc_sync_n_12;
  wire rx_cc_cdc_sync_n_13;
  wire rx_cc_cdc_sync_n_14;
  wire rx_cc_cdc_sync_n_15;
  wire rx_cc_cdc_sync_n_16;
  wire rx_cc_cdc_sync_n_17;
  wire rx_cc_cdc_sync_n_18;
  wire rx_cc_cdc_sync_n_19;
  wire rx_cc_cdc_sync_n_2;
  wire rx_cc_cdc_sync_n_20;
  wire rx_cc_cdc_sync_n_21;
  wire rx_cc_cdc_sync_n_22;
  wire rx_cc_cdc_sync_n_23;
  wire rx_cc_cdc_sync_n_24;
  wire rx_cc_cdc_sync_n_25;
  wire rx_cc_cdc_sync_n_3;
  wire rx_cc_cdc_sync_n_4;
  wire rx_cc_cdc_sync_n_5;
  wire rx_cc_cdc_sync_n_6;
  wire rx_cc_cdc_sync_n_7;
  wire rx_cc_cdc_sync_n_8;
  wire rx_cc_cdc_sync_n_9;
  wire [7:0]rx_cc_extend_r;
  wire rx_cc_extend_r2;
  wire rx_cc_extend_r2_i_1_n_0;
  wire rx_cc_extend_r2_i_2_n_0;
  wire user_clk;

  LUT4 #(
    .INIT(16'hFFFE)) 
    LINK_RESET_OUT_INST_0
       (.I0(link_reset_lane3_i),
        .I1(link_reset_lane0_i),
        .I2(link_reset_lane1_i),
        .I3(link_reset_lane2_i),
        .O(LINK_RESET_OUT));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[0] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_3),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [0]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[10] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_9),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [10]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[11] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_8),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [11]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[12] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_15),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [12]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[13] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_14),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [13]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[14] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_13),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [14]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[15] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_12),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [15]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[16] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_19),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [16]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[17] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_18),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [17]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[18] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_17),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [18]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[19] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_16),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [19]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[1] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_2),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [1]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[20] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_23),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [20]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[21] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_22),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [21]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[22] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_21),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [22]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[23] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_20),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [23]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[24] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_25),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [24]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[25] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_24),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [25]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[2] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_1),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [2]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[3] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_0),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [3]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[4] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_7),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [4]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[5] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_6),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [5]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[6] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_5),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [6]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[7] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_4),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [7]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[8] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_11),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [8]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[9] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_10),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [9]));
  FDRE #(
    .INIT(1'b0)) 
    \hotplug_enable.LINK_RESET_OUT_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(link_reset_lane3_i),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    link_reset_r_i_1__2
       (.I0(link_reset_r_i_2__2_n_0),
        .I1(link_reset_r_i_3__2_n_0),
        .I2(link_reset_r_i_4__2_n_0),
        .I3(link_reset_r_i_5__2_n_0),
        .I4(link_reset_r_i_6__2_n_0),
        .O(link_reset_0));
  LUT3 #(
    .INIT(8'h80)) 
    link_reset_r_i_2__2
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .O(link_reset_r_i_2__2_n_0));
  LUT5 #(
    .INIT(32'h78F8F8F8)) 
    link_reset_r_i_3__2
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .O(link_reset_r_i_3__2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_4__2
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .O(link_reset_r_i_4__2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_5__2
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .O(link_reset_r_i_5__2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_6__2
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .O(link_reset_r_i_6__2_n_0));
  FDRE link_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_0),
        .Q(link_reset_r),
        .R(1'b0));
  aurora_rx_4l_64b_cdc_sync__parameterized2 rx_cc_cdc_sync
       (.O({rx_cc_cdc_sync_n_0,rx_cc_cdc_sync_n_1,rx_cc_cdc_sync_n_2,rx_cc_cdc_sync_n_3}),
        .\hotplug_count_synth.count_for_reset_r_reg (\hotplug_count_synth.count_for_reset_r_reg ),
        .\hotplug_count_synth.count_for_reset_r_reg[11] ({rx_cc_cdc_sync_n_8,rx_cc_cdc_sync_n_9,rx_cc_cdc_sync_n_10,rx_cc_cdc_sync_n_11}),
        .\hotplug_count_synth.count_for_reset_r_reg[15] ({rx_cc_cdc_sync_n_12,rx_cc_cdc_sync_n_13,rx_cc_cdc_sync_n_14,rx_cc_cdc_sync_n_15}),
        .\hotplug_count_synth.count_for_reset_r_reg[19] ({rx_cc_cdc_sync_n_16,rx_cc_cdc_sync_n_17,rx_cc_cdc_sync_n_18,rx_cc_cdc_sync_n_19}),
        .\hotplug_count_synth.count_for_reset_r_reg[23] ({rx_cc_cdc_sync_n_20,rx_cc_cdc_sync_n_21,rx_cc_cdc_sync_n_22,rx_cc_cdc_sync_n_23}),
        .\hotplug_count_synth.count_for_reset_r_reg[25] ({rx_cc_cdc_sync_n_24,rx_cc_cdc_sync_n_25}),
        .\hotplug_count_synth.count_for_reset_r_reg[7] ({rx_cc_cdc_sync_n_4,rx_cc_cdc_sync_n_5,rx_cc_cdc_sync_n_6,rx_cc_cdc_sync_n_7}),
        .init_clk_in(init_clk_in),
        .rx_cc_extend_r2(rx_cc_extend_r2),
        .user_clk(user_clk));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    rx_cc_extend_r2_i_1
       (.I0(rx_cc_extend_r[2]),
        .I1(rx_cc_extend_r[3]),
        .I2(rx_cc_extend_r[0]),
        .I3(rx_cc_extend_r[1]),
        .I4(rx_cc_extend_r2_i_2_n_0),
        .O(rx_cc_extend_r2_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    rx_cc_extend_r2_i_2
       (.I0(rx_cc_extend_r[5]),
        .I1(rx_cc_extend_r[4]),
        .I2(rx_cc_extend_r[7]),
        .I3(rx_cc_extend_r[6]),
        .O(rx_cc_extend_r2_i_2_n_0));
  FDRE rx_cc_extend_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2_i_1_n_0),
        .Q(rx_cc_extend_r2),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[1]),
        .Q(rx_cc_extend_r[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[2]),
        .Q(rx_cc_extend_r[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[3]),
        .Q(rx_cc_extend_r[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[4]),
        .Q(rx_cc_extend_r[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[5]),
        .Q(rx_cc_extend_r[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[6]),
        .Q(rx_cc_extend_r[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[7]),
        .Q(rx_cc_extend_r[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(rx_cc_extend_r[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_HOTPLUG" *) 
module aurora_rx_4l_64b_HOTPLUG_11
   (link_reset_lane1_i,
    user_clk,
    init_clk_in,
    HPCNT_RESET,
    SR,
    D);
  output link_reset_lane1_i;
  input user_clk;
  input init_clk_in;
  input HPCNT_RESET;
  input [0:0]SR;
  input [0:0]D;

  wire [0:0]D;
  wire HPCNT_RESET;
  wire [0:0]SR;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire init_clk_in;
  wire link_reset_0;
  wire link_reset_lane1_i;
  wire link_reset_r;
  wire link_reset_r_i_2__0_n_0;
  wire link_reset_r_i_3__0_n_0;
  wire link_reset_r_i_4__0_n_0;
  wire link_reset_r_i_5__0_n_0;
  wire link_reset_r_i_6__0_n_0;
  wire rx_cc_cdc_sync_n_0;
  wire rx_cc_cdc_sync_n_1;
  wire rx_cc_cdc_sync_n_10;
  wire rx_cc_cdc_sync_n_11;
  wire rx_cc_cdc_sync_n_12;
  wire rx_cc_cdc_sync_n_13;
  wire rx_cc_cdc_sync_n_14;
  wire rx_cc_cdc_sync_n_15;
  wire rx_cc_cdc_sync_n_16;
  wire rx_cc_cdc_sync_n_17;
  wire rx_cc_cdc_sync_n_18;
  wire rx_cc_cdc_sync_n_19;
  wire rx_cc_cdc_sync_n_2;
  wire rx_cc_cdc_sync_n_20;
  wire rx_cc_cdc_sync_n_21;
  wire rx_cc_cdc_sync_n_22;
  wire rx_cc_cdc_sync_n_23;
  wire rx_cc_cdc_sync_n_24;
  wire rx_cc_cdc_sync_n_25;
  wire rx_cc_cdc_sync_n_3;
  wire rx_cc_cdc_sync_n_4;
  wire rx_cc_cdc_sync_n_5;
  wire rx_cc_cdc_sync_n_6;
  wire rx_cc_cdc_sync_n_7;
  wire rx_cc_cdc_sync_n_8;
  wire rx_cc_cdc_sync_n_9;
  wire [7:0]rx_cc_extend_r;
  wire rx_cc_extend_r2;
  wire rx_cc_extend_r2_i_1_n_0;
  wire rx_cc_extend_r2_i_2_n_0;
  wire user_clk;

  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[0] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_3),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [0]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[10] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_9),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [10]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[11] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_8),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [11]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[12] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_15),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [12]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[13] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_14),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [13]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[14] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_13),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [14]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[15] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_12),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [15]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[16] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_19),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [16]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[17] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_18),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [17]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[18] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_17),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [18]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[19] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_16),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [19]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[1] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_2),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [1]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[20] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_23),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [20]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[21] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_22),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [21]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[22] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_21),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [22]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[23] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_20),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [23]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[24] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_25),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [24]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[25] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_24),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [25]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[2] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_1),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [2]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[3] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_0),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [3]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[4] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_7),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [4]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[5] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_6),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [5]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[6] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_5),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [6]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[7] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_4),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [7]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[8] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_11),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [8]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[9] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_10),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [9]));
  FDRE #(
    .INIT(1'b0)) 
    \hotplug_enable.LINK_RESET_OUT_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(link_reset_lane1_i),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    link_reset_r_i_1__0
       (.I0(link_reset_r_i_2__0_n_0),
        .I1(link_reset_r_i_3__0_n_0),
        .I2(link_reset_r_i_4__0_n_0),
        .I3(link_reset_r_i_5__0_n_0),
        .I4(link_reset_r_i_6__0_n_0),
        .O(link_reset_0));
  LUT3 #(
    .INIT(8'h80)) 
    link_reset_r_i_2__0
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .O(link_reset_r_i_2__0_n_0));
  LUT5 #(
    .INIT(32'h78F8F8F8)) 
    link_reset_r_i_3__0
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .O(link_reset_r_i_3__0_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_4__0
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .O(link_reset_r_i_4__0_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_5__0
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .O(link_reset_r_i_5__0_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_6__0
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .O(link_reset_r_i_6__0_n_0));
  FDRE link_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_0),
        .Q(link_reset_r),
        .R(1'b0));
  aurora_rx_4l_64b_cdc_sync__parameterized2_15 rx_cc_cdc_sync
       (.O({rx_cc_cdc_sync_n_0,rx_cc_cdc_sync_n_1,rx_cc_cdc_sync_n_2,rx_cc_cdc_sync_n_3}),
        .\hotplug_count_synth.count_for_reset_r_reg (\hotplug_count_synth.count_for_reset_r_reg ),
        .\hotplug_count_synth.count_for_reset_r_reg[11] ({rx_cc_cdc_sync_n_8,rx_cc_cdc_sync_n_9,rx_cc_cdc_sync_n_10,rx_cc_cdc_sync_n_11}),
        .\hotplug_count_synth.count_for_reset_r_reg[15] ({rx_cc_cdc_sync_n_12,rx_cc_cdc_sync_n_13,rx_cc_cdc_sync_n_14,rx_cc_cdc_sync_n_15}),
        .\hotplug_count_synth.count_for_reset_r_reg[19] ({rx_cc_cdc_sync_n_16,rx_cc_cdc_sync_n_17,rx_cc_cdc_sync_n_18,rx_cc_cdc_sync_n_19}),
        .\hotplug_count_synth.count_for_reset_r_reg[23] ({rx_cc_cdc_sync_n_20,rx_cc_cdc_sync_n_21,rx_cc_cdc_sync_n_22,rx_cc_cdc_sync_n_23}),
        .\hotplug_count_synth.count_for_reset_r_reg[25] ({rx_cc_cdc_sync_n_24,rx_cc_cdc_sync_n_25}),
        .\hotplug_count_synth.count_for_reset_r_reg[7] ({rx_cc_cdc_sync_n_4,rx_cc_cdc_sync_n_5,rx_cc_cdc_sync_n_6,rx_cc_cdc_sync_n_7}),
        .init_clk_in(init_clk_in),
        .rx_cc_extend_r2(rx_cc_extend_r2),
        .user_clk(user_clk));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    rx_cc_extend_r2_i_1
       (.I0(rx_cc_extend_r[2]),
        .I1(rx_cc_extend_r[3]),
        .I2(rx_cc_extend_r[0]),
        .I3(rx_cc_extend_r[1]),
        .I4(rx_cc_extend_r2_i_2_n_0),
        .O(rx_cc_extend_r2_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    rx_cc_extend_r2_i_2
       (.I0(rx_cc_extend_r[5]),
        .I1(rx_cc_extend_r[4]),
        .I2(rx_cc_extend_r[7]),
        .I3(rx_cc_extend_r[6]),
        .O(rx_cc_extend_r2_i_2_n_0));
  FDRE rx_cc_extend_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2_i_1_n_0),
        .Q(rx_cc_extend_r2),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[1]),
        .Q(rx_cc_extend_r[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[2]),
        .Q(rx_cc_extend_r[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[3]),
        .Q(rx_cc_extend_r[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[4]),
        .Q(rx_cc_extend_r[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[5]),
        .Q(rx_cc_extend_r[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[6]),
        .Q(rx_cc_extend_r[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[7]),
        .Q(rx_cc_extend_r[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(rx_cc_extend_r[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_HOTPLUG" *) 
module aurora_rx_4l_64b_HOTPLUG_16
   (link_reset_lane0_i,
    user_clk,
    init_clk_in,
    HPCNT_RESET,
    SR,
    D);
  output link_reset_lane0_i;
  input user_clk;
  input init_clk_in;
  input HPCNT_RESET;
  input [0:0]SR;
  input [0:0]D;

  wire [0:0]D;
  wire HPCNT_RESET;
  wire [0:0]SR;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire init_clk_in;
  wire link_reset_0;
  wire link_reset_lane0_i;
  wire link_reset_r;
  wire link_reset_r_i_2_n_0;
  wire link_reset_r_i_3_n_0;
  wire link_reset_r_i_4_n_0;
  wire link_reset_r_i_5_n_0;
  wire link_reset_r_i_6_n_0;
  wire rx_cc_cdc_sync_n_0;
  wire rx_cc_cdc_sync_n_1;
  wire rx_cc_cdc_sync_n_10;
  wire rx_cc_cdc_sync_n_11;
  wire rx_cc_cdc_sync_n_12;
  wire rx_cc_cdc_sync_n_13;
  wire rx_cc_cdc_sync_n_14;
  wire rx_cc_cdc_sync_n_15;
  wire rx_cc_cdc_sync_n_16;
  wire rx_cc_cdc_sync_n_17;
  wire rx_cc_cdc_sync_n_18;
  wire rx_cc_cdc_sync_n_19;
  wire rx_cc_cdc_sync_n_2;
  wire rx_cc_cdc_sync_n_20;
  wire rx_cc_cdc_sync_n_21;
  wire rx_cc_cdc_sync_n_22;
  wire rx_cc_cdc_sync_n_23;
  wire rx_cc_cdc_sync_n_24;
  wire rx_cc_cdc_sync_n_25;
  wire rx_cc_cdc_sync_n_3;
  wire rx_cc_cdc_sync_n_4;
  wire rx_cc_cdc_sync_n_5;
  wire rx_cc_cdc_sync_n_6;
  wire rx_cc_cdc_sync_n_7;
  wire rx_cc_cdc_sync_n_8;
  wire rx_cc_cdc_sync_n_9;
  wire [7:0]rx_cc_extend_r;
  wire rx_cc_extend_r2;
  wire rx_cc_extend_r2_i_1_n_0;
  wire rx_cc_extend_r2_i_2_n_0;
  wire user_clk;

  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[0] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_3),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [0]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[10] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_9),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [10]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[11] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_8),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [11]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[12] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_15),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [12]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[13] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_14),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [13]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[14] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_13),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [14]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[15] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_12),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [15]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[16] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_19),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [16]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[17] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_18),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [17]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[18] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_17),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [18]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[19] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_16),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [19]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[1] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_2),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [1]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[20] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_23),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [20]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[21] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_22),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [21]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[22] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_21),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [22]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[23] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_20),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [23]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[24] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_25),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [24]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[25] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_24),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [25]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[2] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_1),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [2]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[3] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_0),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [3]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[4] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_7),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [4]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[5] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_6),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [5]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[6] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_5),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [6]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[7] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_4),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [7]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[8] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_11),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [8]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[9] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_10),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [9]));
  FDRE #(
    .INIT(1'b0)) 
    \hotplug_enable.LINK_RESET_OUT_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(link_reset_lane0_i),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    link_reset_r_i_1
       (.I0(link_reset_r_i_2_n_0),
        .I1(link_reset_r_i_3_n_0),
        .I2(link_reset_r_i_4_n_0),
        .I3(link_reset_r_i_5_n_0),
        .I4(link_reset_r_i_6_n_0),
        .O(link_reset_0));
  LUT3 #(
    .INIT(8'h80)) 
    link_reset_r_i_2
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .O(link_reset_r_i_2_n_0));
  LUT5 #(
    .INIT(32'h78F8F8F8)) 
    link_reset_r_i_3
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .O(link_reset_r_i_3_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_4
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .O(link_reset_r_i_4_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_5
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .O(link_reset_r_i_5_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_6
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .O(link_reset_r_i_6_n_0));
  FDRE link_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_0),
        .Q(link_reset_r),
        .R(1'b0));
  aurora_rx_4l_64b_cdc_sync__parameterized2_20 rx_cc_cdc_sync
       (.O({rx_cc_cdc_sync_n_0,rx_cc_cdc_sync_n_1,rx_cc_cdc_sync_n_2,rx_cc_cdc_sync_n_3}),
        .\hotplug_count_synth.count_for_reset_r_reg (\hotplug_count_synth.count_for_reset_r_reg ),
        .\hotplug_count_synth.count_for_reset_r_reg[11] ({rx_cc_cdc_sync_n_8,rx_cc_cdc_sync_n_9,rx_cc_cdc_sync_n_10,rx_cc_cdc_sync_n_11}),
        .\hotplug_count_synth.count_for_reset_r_reg[15] ({rx_cc_cdc_sync_n_12,rx_cc_cdc_sync_n_13,rx_cc_cdc_sync_n_14,rx_cc_cdc_sync_n_15}),
        .\hotplug_count_synth.count_for_reset_r_reg[19] ({rx_cc_cdc_sync_n_16,rx_cc_cdc_sync_n_17,rx_cc_cdc_sync_n_18,rx_cc_cdc_sync_n_19}),
        .\hotplug_count_synth.count_for_reset_r_reg[23] ({rx_cc_cdc_sync_n_20,rx_cc_cdc_sync_n_21,rx_cc_cdc_sync_n_22,rx_cc_cdc_sync_n_23}),
        .\hotplug_count_synth.count_for_reset_r_reg[25] ({rx_cc_cdc_sync_n_24,rx_cc_cdc_sync_n_25}),
        .\hotplug_count_synth.count_for_reset_r_reg[7] ({rx_cc_cdc_sync_n_4,rx_cc_cdc_sync_n_5,rx_cc_cdc_sync_n_6,rx_cc_cdc_sync_n_7}),
        .init_clk_in(init_clk_in),
        .rx_cc_extend_r2(rx_cc_extend_r2),
        .user_clk(user_clk));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    rx_cc_extend_r2_i_1
       (.I0(rx_cc_extend_r[2]),
        .I1(rx_cc_extend_r[3]),
        .I2(rx_cc_extend_r[0]),
        .I3(rx_cc_extend_r[1]),
        .I4(rx_cc_extend_r2_i_2_n_0),
        .O(rx_cc_extend_r2_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    rx_cc_extend_r2_i_2
       (.I0(rx_cc_extend_r[5]),
        .I1(rx_cc_extend_r[4]),
        .I2(rx_cc_extend_r[7]),
        .I3(rx_cc_extend_r[6]),
        .O(rx_cc_extend_r2_i_2_n_0));
  FDRE rx_cc_extend_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2_i_1_n_0),
        .Q(rx_cc_extend_r2),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[1]),
        .Q(rx_cc_extend_r[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[2]),
        .Q(rx_cc_extend_r[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[3]),
        .Q(rx_cc_extend_r[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[4]),
        .Q(rx_cc_extend_r[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[5]),
        .Q(rx_cc_extend_r[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[6]),
        .Q(rx_cc_extend_r[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[7]),
        .Q(rx_cc_extend_r[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(rx_cc_extend_r[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_HOTPLUG" *) 
module aurora_rx_4l_64b_HOTPLUG_6
   (link_reset_lane2_i,
    user_clk,
    init_clk_in,
    HPCNT_RESET,
    SR,
    D);
  output link_reset_lane2_i;
  input user_clk;
  input init_clk_in;
  input HPCNT_RESET;
  input [0:0]SR;
  input [0:0]D;

  wire [0:0]D;
  wire HPCNT_RESET;
  wire [0:0]SR;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire init_clk_in;
  wire link_reset_0;
  wire link_reset_lane2_i;
  wire link_reset_r;
  wire link_reset_r_i_2__1_n_0;
  wire link_reset_r_i_3__1_n_0;
  wire link_reset_r_i_4__1_n_0;
  wire link_reset_r_i_5__1_n_0;
  wire link_reset_r_i_6__1_n_0;
  wire rx_cc_cdc_sync_n_0;
  wire rx_cc_cdc_sync_n_1;
  wire rx_cc_cdc_sync_n_10;
  wire rx_cc_cdc_sync_n_11;
  wire rx_cc_cdc_sync_n_12;
  wire rx_cc_cdc_sync_n_13;
  wire rx_cc_cdc_sync_n_14;
  wire rx_cc_cdc_sync_n_15;
  wire rx_cc_cdc_sync_n_16;
  wire rx_cc_cdc_sync_n_17;
  wire rx_cc_cdc_sync_n_18;
  wire rx_cc_cdc_sync_n_19;
  wire rx_cc_cdc_sync_n_2;
  wire rx_cc_cdc_sync_n_20;
  wire rx_cc_cdc_sync_n_21;
  wire rx_cc_cdc_sync_n_22;
  wire rx_cc_cdc_sync_n_23;
  wire rx_cc_cdc_sync_n_24;
  wire rx_cc_cdc_sync_n_25;
  wire rx_cc_cdc_sync_n_3;
  wire rx_cc_cdc_sync_n_4;
  wire rx_cc_cdc_sync_n_5;
  wire rx_cc_cdc_sync_n_6;
  wire rx_cc_cdc_sync_n_7;
  wire rx_cc_cdc_sync_n_8;
  wire rx_cc_cdc_sync_n_9;
  wire [7:0]rx_cc_extend_r;
  wire rx_cc_extend_r2;
  wire rx_cc_extend_r2_i_1_n_0;
  wire rx_cc_extend_r2_i_2_n_0;
  wire user_clk;

  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[0] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_3),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [0]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[10] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_9),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [10]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[11] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_8),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [11]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[12] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_15),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [12]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[13] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_14),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [13]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[14] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_13),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [14]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[15] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_12),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [15]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[16] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_19),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [16]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[17] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_18),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [17]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[18] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_17),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [18]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[19] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_16),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [19]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[1] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_2),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [1]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[20] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_23),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [20]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[21] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_22),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [21]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[22] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_21),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [22]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[23] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_20),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [23]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[24] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_25),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [24]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[25] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_24),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [25]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[2] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_1),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [2]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[3] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_0),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [3]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[4] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_7),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [4]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[5] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_6),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [5]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[6] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_5),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [6]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[7] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_4),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [7]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[8] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_11),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [8]));
  FDCE #(
    .INIT(1'b0)) 
    \hotplug_count_synth.count_for_reset_r_reg[9] 
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(HPCNT_RESET),
        .D(rx_cc_cdc_sync_n_10),
        .Q(\hotplug_count_synth.count_for_reset_r_reg [9]));
  FDRE #(
    .INIT(1'b0)) 
    \hotplug_enable.LINK_RESET_OUT_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(link_reset_lane2_i),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    link_reset_r_i_1__1
       (.I0(link_reset_r_i_2__1_n_0),
        .I1(link_reset_r_i_3__1_n_0),
        .I2(link_reset_r_i_4__1_n_0),
        .I3(link_reset_r_i_5__1_n_0),
        .I4(link_reset_r_i_6__1_n_0),
        .O(link_reset_0));
  LUT3 #(
    .INIT(8'h80)) 
    link_reset_r_i_2__1
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .O(link_reset_r_i_2__1_n_0));
  LUT5 #(
    .INIT(32'h78F8F8F8)) 
    link_reset_r_i_3__1
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .O(link_reset_r_i_3__1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_4__1
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .O(link_reset_r_i_4__1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_5__1
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .O(link_reset_r_i_5__1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    link_reset_r_i_6__1
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I2(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I3(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I4(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I5(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .O(link_reset_r_i_6__1_n_0));
  FDRE link_reset_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_0),
        .Q(link_reset_r),
        .R(1'b0));
  aurora_rx_4l_64b_cdc_sync__parameterized2_10 rx_cc_cdc_sync
       (.O({rx_cc_cdc_sync_n_0,rx_cc_cdc_sync_n_1,rx_cc_cdc_sync_n_2,rx_cc_cdc_sync_n_3}),
        .\hotplug_count_synth.count_for_reset_r_reg (\hotplug_count_synth.count_for_reset_r_reg ),
        .\hotplug_count_synth.count_for_reset_r_reg[11] ({rx_cc_cdc_sync_n_8,rx_cc_cdc_sync_n_9,rx_cc_cdc_sync_n_10,rx_cc_cdc_sync_n_11}),
        .\hotplug_count_synth.count_for_reset_r_reg[15] ({rx_cc_cdc_sync_n_12,rx_cc_cdc_sync_n_13,rx_cc_cdc_sync_n_14,rx_cc_cdc_sync_n_15}),
        .\hotplug_count_synth.count_for_reset_r_reg[19] ({rx_cc_cdc_sync_n_16,rx_cc_cdc_sync_n_17,rx_cc_cdc_sync_n_18,rx_cc_cdc_sync_n_19}),
        .\hotplug_count_synth.count_for_reset_r_reg[23] ({rx_cc_cdc_sync_n_20,rx_cc_cdc_sync_n_21,rx_cc_cdc_sync_n_22,rx_cc_cdc_sync_n_23}),
        .\hotplug_count_synth.count_for_reset_r_reg[25] ({rx_cc_cdc_sync_n_24,rx_cc_cdc_sync_n_25}),
        .\hotplug_count_synth.count_for_reset_r_reg[7] ({rx_cc_cdc_sync_n_4,rx_cc_cdc_sync_n_5,rx_cc_cdc_sync_n_6,rx_cc_cdc_sync_n_7}),
        .init_clk_in(init_clk_in),
        .rx_cc_extend_r2(rx_cc_extend_r2),
        .user_clk(user_clk));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    rx_cc_extend_r2_i_1
       (.I0(rx_cc_extend_r[2]),
        .I1(rx_cc_extend_r[3]),
        .I2(rx_cc_extend_r[0]),
        .I3(rx_cc_extend_r[1]),
        .I4(rx_cc_extend_r2_i_2_n_0),
        .O(rx_cc_extend_r2_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    rx_cc_extend_r2_i_2
       (.I0(rx_cc_extend_r[5]),
        .I1(rx_cc_extend_r[4]),
        .I2(rx_cc_extend_r[7]),
        .I3(rx_cc_extend_r[6]),
        .O(rx_cc_extend_r2_i_2_n_0));
  FDRE rx_cc_extend_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2_i_1_n_0),
        .Q(rx_cc_extend_r2),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[1]),
        .Q(rx_cc_extend_r[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[2]),
        .Q(rx_cc_extend_r[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[3]),
        .Q(rx_cc_extend_r[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[4]),
        .Q(rx_cc_extend_r[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[5]),
        .Q(rx_cc_extend_r[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[6]),
        .Q(rx_cc_extend_r[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r[7]),
        .Q(rx_cc_extend_r[6]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rx_cc_extend_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(rx_cc_extend_r[7]),
        .R(SR));
endmodule

module aurora_rx_4l_64b_LEFT_ALIGN_CONTROL
   (Q,
    D,
    user_clk);
  output [4:0]Q;
  input [4:0]D;
  input user_clk;

  wire [4:0]D;
  wire [4:0]Q;
  wire user_clk;

  FDRE \MUX_SELECT_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \MUX_SELECT_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \MUX_SELECT_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \MUX_SELECT_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \MUX_SELECT_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_LEFT_ALIGN_MUX
   (\MUXED_DATA_Buffer_reg[0]_0 ,
    Q,
    \MUXED_DATA_Buffer_reg[0]_1 ,
    user_clk);
  output [63:0]\MUXED_DATA_Buffer_reg[0]_0 ;
  input [63:0]Q;
  input [4:0]\MUXED_DATA_Buffer_reg[0]_1 ;
  input user_clk;

  wire [63:0]\MUXED_DATA_Buffer_reg[0]_0 ;
  wire [4:0]\MUXED_DATA_Buffer_reg[0]_1 ;
  wire [63:0]Q;
  wire [0:47]muxed_data_c;
  wire user_clk;

  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[0]_i_1 
       (.I0(Q[47]),
        .I1(Q[63]),
        .I2(Q[15]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[31]),
        .O(muxed_data_c[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[10]_i_1 
       (.I0(Q[37]),
        .I1(Q[53]),
        .I2(Q[5]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[21]),
        .O(muxed_data_c[10]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[11]_i_1 
       (.I0(Q[36]),
        .I1(Q[52]),
        .I2(Q[4]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[20]),
        .O(muxed_data_c[11]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[12]_i_1 
       (.I0(Q[35]),
        .I1(Q[51]),
        .I2(Q[3]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[19]),
        .O(muxed_data_c[12]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[13]_i_1 
       (.I0(Q[34]),
        .I1(Q[50]),
        .I2(Q[2]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[18]),
        .O(muxed_data_c[13]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[14]_i_1 
       (.I0(Q[33]),
        .I1(Q[49]),
        .I2(Q[1]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[17]),
        .O(muxed_data_c[14]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[15]_i_1 
       (.I0(Q[32]),
        .I1(Q[48]),
        .I2(Q[0]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[16]),
        .O(muxed_data_c[15]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[16]_i_1 
       (.I0(Q[31]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[15]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[47]),
        .O(muxed_data_c[16]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[17]_i_1 
       (.I0(Q[30]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[14]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[46]),
        .O(muxed_data_c[17]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[18]_i_1 
       (.I0(Q[29]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[13]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[45]),
        .O(muxed_data_c[18]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[19]_i_1 
       (.I0(Q[28]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[12]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[44]),
        .O(muxed_data_c[19]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[1]_i_1 
       (.I0(Q[46]),
        .I1(Q[62]),
        .I2(Q[14]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[30]),
        .O(muxed_data_c[1]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[20]_i_1 
       (.I0(Q[27]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[11]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[43]),
        .O(muxed_data_c[20]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[21]_i_1 
       (.I0(Q[26]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[10]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[42]),
        .O(muxed_data_c[21]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[22]_i_1 
       (.I0(Q[25]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[9]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[41]),
        .O(muxed_data_c[22]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[23]_i_1 
       (.I0(Q[24]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[8]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[40]),
        .O(muxed_data_c[23]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[24]_i_1 
       (.I0(Q[23]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[7]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[39]),
        .O(muxed_data_c[24]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[25]_i_1 
       (.I0(Q[22]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[6]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[38]),
        .O(muxed_data_c[25]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[26]_i_1 
       (.I0(Q[21]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[5]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[37]),
        .O(muxed_data_c[26]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[27]_i_1 
       (.I0(Q[20]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[4]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[36]),
        .O(muxed_data_c[27]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[28]_i_1 
       (.I0(Q[19]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[3]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[35]),
        .O(muxed_data_c[28]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[29]_i_1 
       (.I0(Q[18]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[2]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[34]),
        .O(muxed_data_c[29]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[2]_i_1 
       (.I0(Q[45]),
        .I1(Q[61]),
        .I2(Q[13]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[29]),
        .O(muxed_data_c[2]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[30]_i_1 
       (.I0(Q[17]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[1]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[33]),
        .O(muxed_data_c[30]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[31]_i_1 
       (.I0(Q[16]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [1]),
        .I2(Q[0]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [2]),
        .I4(Q[32]),
        .O(muxed_data_c[31]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[32]_i_1 
       (.I0(Q[15]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[31]),
        .O(muxed_data_c[32]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[33]_i_1 
       (.I0(Q[14]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[30]),
        .O(muxed_data_c[33]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[34]_i_1 
       (.I0(Q[13]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[29]),
        .O(muxed_data_c[34]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[35]_i_1 
       (.I0(Q[12]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[28]),
        .O(muxed_data_c[35]));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[36]_i_1 
       (.I0(Q[11]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[27]),
        .O(muxed_data_c[36]));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[37]_i_1 
       (.I0(Q[10]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[26]),
        .O(muxed_data_c[37]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[38]_i_1 
       (.I0(Q[9]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[25]),
        .O(muxed_data_c[38]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[39]_i_1 
       (.I0(Q[8]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[24]),
        .O(muxed_data_c[39]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[3]_i_1 
       (.I0(Q[44]),
        .I1(Q[60]),
        .I2(Q[12]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[28]),
        .O(muxed_data_c[3]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[40]_i_1 
       (.I0(Q[7]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[23]),
        .O(muxed_data_c[40]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[41]_i_1 
       (.I0(Q[6]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[22]),
        .O(muxed_data_c[41]));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[42]_i_1 
       (.I0(Q[5]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[21]),
        .O(muxed_data_c[42]));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[43]_i_1 
       (.I0(Q[4]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[20]),
        .O(muxed_data_c[43]));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[44]_i_1 
       (.I0(Q[3]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[19]),
        .O(muxed_data_c[44]));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[45]_i_1 
       (.I0(Q[2]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[18]),
        .O(muxed_data_c[45]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[46]_i_1 
       (.I0(Q[1]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[17]),
        .O(muxed_data_c[46]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \MUXED_DATA_Buffer[47]_i_1 
       (.I0(Q[0]),
        .I1(\MUXED_DATA_Buffer_reg[0]_1 [0]),
        .I2(Q[16]),
        .O(muxed_data_c[47]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[4]_i_1 
       (.I0(Q[43]),
        .I1(Q[59]),
        .I2(Q[11]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[27]),
        .O(muxed_data_c[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[5]_i_1 
       (.I0(Q[42]),
        .I1(Q[58]),
        .I2(Q[10]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[26]),
        .O(muxed_data_c[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[6]_i_1 
       (.I0(Q[41]),
        .I1(Q[57]),
        .I2(Q[9]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[25]),
        .O(muxed_data_c[6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[7]_i_1 
       (.I0(Q[40]),
        .I1(Q[56]),
        .I2(Q[8]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[24]),
        .O(muxed_data_c[7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[8]_i_1 
       (.I0(Q[39]),
        .I1(Q[55]),
        .I2(Q[7]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[23]),
        .O(muxed_data_c[8]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \MUXED_DATA_Buffer[9]_i_1 
       (.I0(Q[38]),
        .I1(Q[54]),
        .I2(Q[6]),
        .I3(\MUXED_DATA_Buffer_reg[0]_1 [4]),
        .I4(\MUXED_DATA_Buffer_reg[0]_1 [3]),
        .I5(Q[22]),
        .O(muxed_data_c[9]));
  FDRE \MUXED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[0]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [63]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[10]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [53]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[11]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [52]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[12]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [51]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[13]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [50]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[14]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [49]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[15]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [48]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[16]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [47]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[17]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [46]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[18]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [45]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[19]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [44]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[1]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [62]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[20]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [43]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[21]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [42]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[22]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [41]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[23]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [40]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[24]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [39]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[25]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [38]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[26]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [37]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[27]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [36]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[28]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [35]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[29]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [34]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[2]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [61]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[30]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [33]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[31]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [32]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[32]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [31]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[33]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [30]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[34]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [29]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[35]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [28]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[36]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [27]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[37]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [26]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[38]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [25]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[39]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [24]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[3]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [60]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[40]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [23]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[41]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [22]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[42]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [21]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[43]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [20]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[44]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [19]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[45]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [18]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[46]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [17]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[47]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [16]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[15]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [15]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[14]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [14]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[4]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [59]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[13]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [13]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[12]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [12]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[11]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [11]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[10]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [10]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[9]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [9]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[8]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [8]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[7]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[6]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[5]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[4]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[5]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [58]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[3]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[2]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[1]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[0]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[6]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [57]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[7]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [56]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[8]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [55]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(muxed_data_c[9]),
        .Q(\MUXED_DATA_Buffer_reg[0]_0 [54]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_LL_TO_AXI
   (M_AXI_RX_TKEEP,
    RX_EOF_N,
    RX_REM);
  output [6:0]M_AXI_RX_TKEEP;
  input RX_EOF_N;
  input [0:2]RX_REM;

  wire [6:0]M_AXI_RX_TKEEP;
  wire RX_EOF_N;
  wire [0:2]RX_REM;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \M_AXI_RX_TKEEP[1]_INST_0 
       (.I0(RX_EOF_N),
        .I1(RX_REM[0]),
        .I2(RX_REM[1]),
        .I3(RX_REM[2]),
        .O(M_AXI_RX_TKEEP[0]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \M_AXI_RX_TKEEP[2]_INST_0 
       (.I0(RX_EOF_N),
        .I1(RX_REM[0]),
        .I2(RX_REM[1]),
        .O(M_AXI_RX_TKEEP[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'hFFEA)) 
    \M_AXI_RX_TKEEP[3]_INST_0 
       (.I0(RX_EOF_N),
        .I1(RX_REM[2]),
        .I2(RX_REM[1]),
        .I3(RX_REM[0]),
        .O(M_AXI_RX_TKEEP[2]));
  LUT2 #(
    .INIT(4'hE)) 
    \M_AXI_RX_TKEEP[4]_INST_0 
       (.I0(RX_EOF_N),
        .I1(RX_REM[0]),
        .O(M_AXI_RX_TKEEP[3]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hEEEA)) 
    \M_AXI_RX_TKEEP[5]_INST_0 
       (.I0(RX_EOF_N),
        .I1(RX_REM[0]),
        .I2(RX_REM[1]),
        .I3(RX_REM[2]),
        .O(M_AXI_RX_TKEEP[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \M_AXI_RX_TKEEP[6]_INST_0 
       (.I0(RX_EOF_N),
        .I1(RX_REM[1]),
        .I2(RX_REM[0]),
        .O(M_AXI_RX_TKEEP[5]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    \M_AXI_RX_TKEEP[7]_INST_0 
       (.I0(RX_EOF_N),
        .I1(RX_REM[2]),
        .I2(RX_REM[0]),
        .I3(RX_REM[1]),
        .O(M_AXI_RX_TKEEP[6]));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_LL_TO_AXI" *) 
module aurora_rx_4l_64b_LL_TO_AXI__parameterized1
   (M_AXI_UFC_RX_TKEEP,
    UFC_RX_EOF_N,
    UFC_RX_REM);
  output [2:0]M_AXI_UFC_RX_TKEEP;
  input UFC_RX_EOF_N;
  input [1:0]UFC_RX_REM;

  wire [2:0]M_AXI_UFC_RX_TKEEP;
  wire UFC_RX_EOF_N;
  wire [1:0]UFC_RX_REM;

  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \M_AXI_UFC_RX_TKEEP[2]_INST_0 
       (.I0(UFC_RX_EOF_N),
        .I1(UFC_RX_REM[0]),
        .I2(UFC_RX_REM[1]),
        .O(M_AXI_UFC_RX_TKEEP[0]));
  LUT2 #(
    .INIT(4'hE)) 
    \M_AXI_UFC_RX_TKEEP[4]_INST_0 
       (.I0(UFC_RX_EOF_N),
        .I1(UFC_RX_REM[1]),
        .O(M_AXI_UFC_RX_TKEEP[1]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \M_AXI_UFC_RX_TKEEP[6]_INST_0 
       (.I0(UFC_RX_EOF_N),
        .I1(UFC_RX_REM[1]),
        .I2(UFC_RX_REM[0]),
        .O(M_AXI_UFC_RX_TKEEP[2]));
endmodule

module aurora_rx_4l_64b_OUTPUT_MUX
   (M_AXI_RX_TDATA,
    Q,
    user_clk,
    \OUTPUT_DATA_Buffer_reg[48]_0 ,
    OUTPUT_SELECT_Buffer);
  output [63:0]M_AXI_RX_TDATA;
  input [63:0]Q;
  input user_clk;
  input [47:0]\OUTPUT_DATA_Buffer_reg[48]_0 ;
  input [3:0]OUTPUT_SELECT_Buffer;

  wire [63:0]M_AXI_RX_TDATA;
  wire [47:0]\OUTPUT_DATA_Buffer_reg[48]_0 ;
  wire [3:0]OUTPUT_SELECT_Buffer;
  wire [63:0]Q;
  wire [16:63]output_data_c;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[16]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [47]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[47]),
        .O(output_data_c[16]));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[17]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [46]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[46]),
        .O(output_data_c[17]));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[18]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [45]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[45]),
        .O(output_data_c[18]));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[19]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [44]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[44]),
        .O(output_data_c[19]));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[20]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [43]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[43]),
        .O(output_data_c[20]));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[21]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [42]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[42]),
        .O(output_data_c[21]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[22]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [41]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[41]),
        .O(output_data_c[22]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[23]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [40]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[40]),
        .O(output_data_c[23]));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[24]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [39]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[39]),
        .O(output_data_c[24]));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[25]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [38]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[38]),
        .O(output_data_c[25]));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[26]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [37]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[37]),
        .O(output_data_c[26]));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[27]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [36]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[36]),
        .O(output_data_c[27]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[28]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [35]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[35]),
        .O(output_data_c[28]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[29]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [34]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[34]),
        .O(output_data_c[29]));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[30]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [33]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[33]),
        .O(output_data_c[30]));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \OUTPUT_DATA_Buffer[31]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [32]),
        .I1(OUTPUT_SELECT_Buffer[3]),
        .I2(Q[32]),
        .O(output_data_c[31]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[32]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [47]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [31]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[31]),
        .O(output_data_c[32]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[33]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [46]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [30]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[30]),
        .O(output_data_c[33]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[34]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [45]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [29]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[29]),
        .O(output_data_c[34]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[35]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [44]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [28]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[28]),
        .O(output_data_c[35]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[36]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [43]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [27]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[27]),
        .O(output_data_c[36]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[37]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [42]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [26]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[26]),
        .O(output_data_c[37]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[38]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [41]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [25]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[25]),
        .O(output_data_c[38]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[39]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [40]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [24]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[24]),
        .O(output_data_c[39]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[40]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [39]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [23]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[23]),
        .O(output_data_c[40]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[41]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [38]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [22]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[22]),
        .O(output_data_c[41]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[42]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [37]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [21]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[21]),
        .O(output_data_c[42]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[43]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [36]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [20]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[20]),
        .O(output_data_c[43]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[44]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [35]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [19]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[19]),
        .O(output_data_c[44]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[45]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [34]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [18]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[18]),
        .O(output_data_c[45]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[46]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [33]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [17]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[17]),
        .O(output_data_c[46]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \OUTPUT_DATA_Buffer[47]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [32]),
        .I1(OUTPUT_SELECT_Buffer[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [16]),
        .I3(OUTPUT_SELECT_Buffer[3]),
        .I4(Q[16]),
        .O(output_data_c[47]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[48]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [47]),
        .I1(Q[15]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [15]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [31]),
        .O(output_data_c[48]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[49]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [46]),
        .I1(Q[14]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [14]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [30]),
        .O(output_data_c[49]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[50]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [45]),
        .I1(Q[13]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [13]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [29]),
        .O(output_data_c[50]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[51]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [44]),
        .I1(Q[12]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [12]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [28]),
        .O(output_data_c[51]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[52]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [43]),
        .I1(Q[11]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [11]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [27]),
        .O(output_data_c[52]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[53]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [42]),
        .I1(Q[10]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [10]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [26]),
        .O(output_data_c[53]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[54]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [41]),
        .I1(Q[9]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [9]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [25]),
        .O(output_data_c[54]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[55]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [40]),
        .I1(Q[8]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [8]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [24]),
        .O(output_data_c[55]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[56]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [39]),
        .I1(Q[7]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [7]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [23]),
        .O(output_data_c[56]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[57]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [38]),
        .I1(Q[6]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [6]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [22]),
        .O(output_data_c[57]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[58]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [37]),
        .I1(Q[5]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [5]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [21]),
        .O(output_data_c[58]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[59]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [36]),
        .I1(Q[4]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [4]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [20]),
        .O(output_data_c[59]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[60]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [35]),
        .I1(Q[3]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [3]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [19]),
        .O(output_data_c[60]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[61]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [34]),
        .I1(Q[2]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [2]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [18]),
        .O(output_data_c[61]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[62]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [33]),
        .I1(Q[1]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [1]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [17]),
        .O(output_data_c[62]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \OUTPUT_DATA_Buffer[63]_i_1 
       (.I0(\OUTPUT_DATA_Buffer_reg[48]_0 [32]),
        .I1(Q[0]),
        .I2(\OUTPUT_DATA_Buffer_reg[48]_0 [0]),
        .I3(OUTPUT_SELECT_Buffer[1]),
        .I4(OUTPUT_SELECT_Buffer[0]),
        .I5(\OUTPUT_DATA_Buffer_reg[48]_0 [16]),
        .O(output_data_c[63]));
  FDRE \OUTPUT_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[63]),
        .Q(M_AXI_RX_TDATA[7]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[53]),
        .Q(M_AXI_RX_TDATA[13]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[52]),
        .Q(M_AXI_RX_TDATA[12]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[51]),
        .Q(M_AXI_RX_TDATA[11]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[50]),
        .Q(M_AXI_RX_TDATA[10]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[49]),
        .Q(M_AXI_RX_TDATA[9]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[48]),
        .Q(M_AXI_RX_TDATA[8]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[16]),
        .Q(M_AXI_RX_TDATA[23]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[17]),
        .Q(M_AXI_RX_TDATA[22]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[18]),
        .Q(M_AXI_RX_TDATA[21]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[19]),
        .Q(M_AXI_RX_TDATA[20]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[62]),
        .Q(M_AXI_RX_TDATA[6]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[20]),
        .Q(M_AXI_RX_TDATA[19]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[21]),
        .Q(M_AXI_RX_TDATA[18]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[22]),
        .Q(M_AXI_RX_TDATA[17]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[23]),
        .Q(M_AXI_RX_TDATA[16]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[24]),
        .Q(M_AXI_RX_TDATA[31]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[25]),
        .Q(M_AXI_RX_TDATA[30]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[26]),
        .Q(M_AXI_RX_TDATA[29]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[27]),
        .Q(M_AXI_RX_TDATA[28]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[28]),
        .Q(M_AXI_RX_TDATA[27]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[29]),
        .Q(M_AXI_RX_TDATA[26]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[61]),
        .Q(M_AXI_RX_TDATA[5]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[30]),
        .Q(M_AXI_RX_TDATA[25]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[31]),
        .Q(M_AXI_RX_TDATA[24]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[32]),
        .Q(M_AXI_RX_TDATA[39]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[33]),
        .Q(M_AXI_RX_TDATA[38]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[34]),
        .Q(M_AXI_RX_TDATA[37]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[35]),
        .Q(M_AXI_RX_TDATA[36]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[36]),
        .Q(M_AXI_RX_TDATA[35]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[37]),
        .Q(M_AXI_RX_TDATA[34]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[38]),
        .Q(M_AXI_RX_TDATA[33]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[39]),
        .Q(M_AXI_RX_TDATA[32]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[60]),
        .Q(M_AXI_RX_TDATA[4]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[40]),
        .Q(M_AXI_RX_TDATA[47]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[41]),
        .Q(M_AXI_RX_TDATA[46]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[42]),
        .Q(M_AXI_RX_TDATA[45]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[43]),
        .Q(M_AXI_RX_TDATA[44]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[44]),
        .Q(M_AXI_RX_TDATA[43]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[45]),
        .Q(M_AXI_RX_TDATA[42]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[46]),
        .Q(M_AXI_RX_TDATA[41]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[47]),
        .Q(M_AXI_RX_TDATA[40]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[48]),
        .Q(M_AXI_RX_TDATA[55]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[49]),
        .Q(M_AXI_RX_TDATA[54]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[59]),
        .Q(M_AXI_RX_TDATA[3]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[50]),
        .Q(M_AXI_RX_TDATA[53]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[51]),
        .Q(M_AXI_RX_TDATA[52]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[52]),
        .Q(M_AXI_RX_TDATA[51]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[53]),
        .Q(M_AXI_RX_TDATA[50]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[54]),
        .Q(M_AXI_RX_TDATA[49]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[55]),
        .Q(M_AXI_RX_TDATA[48]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[56]),
        .Q(M_AXI_RX_TDATA[63]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[57]),
        .Q(M_AXI_RX_TDATA[62]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[58]),
        .Q(M_AXI_RX_TDATA[61]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[59]),
        .Q(M_AXI_RX_TDATA[60]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[58]),
        .Q(M_AXI_RX_TDATA[2]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[60]),
        .Q(M_AXI_RX_TDATA[59]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[61]),
        .Q(M_AXI_RX_TDATA[58]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[62]),
        .Q(M_AXI_RX_TDATA[57]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(output_data_c[63]),
        .Q(M_AXI_RX_TDATA[56]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[57]),
        .Q(M_AXI_RX_TDATA[1]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[56]),
        .Q(M_AXI_RX_TDATA[0]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[55]),
        .Q(M_AXI_RX_TDATA[15]),
        .R(1'b0));
  FDRE \OUTPUT_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[54]),
        .Q(M_AXI_RX_TDATA[14]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL
   (OUTPUT_SELECT_Buffer,
    SR,
    Q,
    user_clk,
    D);
  output [3:0]OUTPUT_SELECT_Buffer;
  input [0:0]SR;
  input [0:0]Q;
  input user_clk;
  input [2:0]D;

  wire [2:0]D;
  wire [3:0]OUTPUT_SELECT_Buffer;
  wire [0:0]Q;
  wire [0:0]SR;
  wire user_clk;

  FDRE \OUTPUT_SELECT_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(OUTPUT_SELECT_Buffer[3]),
        .R(SR));
  FDRE \OUTPUT_SELECT_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(OUTPUT_SELECT_Buffer[2]),
        .R(SR));
  FDRE \OUTPUT_SELECT_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(OUTPUT_SELECT_Buffer[1]),
        .R(SR));
  FDRE \OUTPUT_SELECT_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q),
        .Q(OUTPUT_SELECT_Buffer[0]),
        .R(SR));
endmodule

module aurora_rx_4l_64b_RESET_LOGIC
   (SYSTEM_RESET_reg_0,
    SR,
    out,
    link_reset_r,
    init_clk_in,
    user_clk,
    TX_LOCK,
    gt_rxresetdone_r2_reg_0,
    en_chan_sync_i);
  output SYSTEM_RESET_reg_0;
  output [0:0]SR;
  input out;
  input link_reset_r;
  input init_clk_in;
  input user_clk;
  input TX_LOCK;
  input gt_rxresetdone_r2_reg_0;
  input en_chan_sync_i;

  wire [0:0]SR;
  wire SYSTEM_RESET0_n_0;
  wire SYSTEM_RESET_reg_0;
  wire TX_LOCK;
  wire en_chan_sync_i;
  wire gt_rxresetdone_r;
  wire gt_rxresetdone_r2;
  wire gt_rxresetdone_r2_reg_0;
  wire gt_rxresetdone_r3;
  wire init_clk_in;
  wire link_reset_r;
  wire out;
  wire scndry_out;
  wire tx_lock_comb_r;
  wire tx_lock_sync;
  wire user_clk;

  LUT4 #(
    .INIT(16'hFFDF)) 
    SYSTEM_RESET0
       (.I0(tx_lock_sync),
        .I1(out),
        .I2(gt_rxresetdone_r3),
        .I3(scndry_out),
        .O(SYSTEM_RESET0_n_0));
  FDRE SYSTEM_RESET_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(SYSTEM_RESET0_n_0),
        .Q(SYSTEM_RESET_reg_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    \ch_bond_done_dly_i[0]_i_1 
       (.I0(SYSTEM_RESET_reg_0),
        .I1(en_chan_sync_i),
        .O(SR));
  FDCE gt_rxresetdone_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(gt_rxresetdone_r2_reg_0),
        .D(gt_rxresetdone_r),
        .Q(gt_rxresetdone_r2));
  FDRE gt_rxresetdone_r3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(gt_rxresetdone_r2),
        .Q(gt_rxresetdone_r3),
        .R(1'b0));
  FDCE gt_rxresetdone_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(gt_rxresetdone_r2_reg_0),
        .D(1'b1),
        .Q(gt_rxresetdone_r));
  aurora_rx_4l_64b_cdc_sync__parameterized2_36 link_reset_cdc_sync
       (.init_clk_in(init_clk_in),
        .link_reset_r(link_reset_r),
        .out(scndry_out),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync__parameterized2_37 tx_lock_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(tx_lock_sync),
        .tx_lock_comb_r(tx_lock_comb_r),
        .user_clk(user_clk));
  FDRE tx_lock_comb_r_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(TX_LOCK),
        .Q(tx_lock_comb_r),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5
   (RX_LANE_UP,
    ena_comma_align_i_0,
    comma_over_two_cycles_r,
    gtp_rx_reset_i_0,
    GOT_V,
    bucket_full_r,
    D,
    link_reset_lane0_i,
    RX_PE_DATA,
    RX_SCP_Buffer_reg,
    RX_SUF,
    rx_polarity_i_0,
    left_aligned_r_reg,
    RX_PE_DATA_V_Buffer_reg,
    user_clk_0,
    \RX_PE_DATA_Buffer_reg[10] ,
    RX_SUF_Buffer_reg,
    \RX_PE_DATA_Buffer_reg[8] ,
    \RX_PE_DATA_Buffer_reg[8]_0 ,
    RX_SUF_Buffer_reg_0,
    good_as_r0,
    GOT_A,
    \word_aligned_data_r_reg[11] ,
    \word_aligned_data_r_reg[0] ,
    first_v_received_r,
    std_bool26_out,
    RX_ECP_Buffer0,
    SR,
    user_clk,
    \word_aligned_control_bits_r_reg[1] ,
    \word_aligned_control_bits_r_reg[0] ,
    hard_err_flop_r0,
    init_clk_in,
    HPCNT_RESET,
    start_rx_i,
    \stage_1_lane_mask_r_reg[2] ,
    \stage_1_count_value_r_reg[1] ,
    \stage_1_count_value_r_reg[2] ,
    \stage_1_lane_mask_r_reg[3] ,
    begin_r_reg,
    reset_count_r_reg,
    \counter2_r_reg[15] ,
    good_as_r_reg,
    good_as_r_reg_0,
    good_as_r_reg_1,
    Q,
    good_as_r_reg_2,
    good_as_r_reg_3,
    \RX_CHAR_IS_COMMA_R_reg[1] ,
    left_aligned_r_reg_0,
    \soft_err_r_reg[0] ,
    \word_aligned_data_r_reg[8] ,
    \word_aligned_data_r_reg[0]_0 );
  output [0:0]RX_LANE_UP;
  output ena_comma_align_i_0;
  output comma_over_two_cycles_r;
  output gtp_rx_reset_i_0;
  output GOT_V;
  output bucket_full_r;
  output [0:0]D;
  output link_reset_lane0_i;
  output [2:0]RX_PE_DATA;
  output [0:0]RX_SCP_Buffer_reg;
  output RX_SUF;
  output rx_polarity_i_0;
  output left_aligned_r_reg;
  output [0:0]RX_PE_DATA_V_Buffer_reg;
  output user_clk_0;
  output \RX_PE_DATA_Buffer_reg[10] ;
  output RX_SUF_Buffer_reg;
  output \RX_PE_DATA_Buffer_reg[8] ;
  output \RX_PE_DATA_Buffer_reg[8]_0 ;
  output RX_SUF_Buffer_reg_0;
  output good_as_r0;
  output [0:1]GOT_A;
  output [4:0]\word_aligned_data_r_reg[11] ;
  output [7:0]\word_aligned_data_r_reg[0] ;
  output first_v_received_r;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input [0:0]SR;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1] ;
  input \word_aligned_control_bits_r_reg[0] ;
  input hard_err_flop_r0;
  input init_clk_in;
  input HPCNT_RESET;
  input start_rx_i;
  input \stage_1_lane_mask_r_reg[2] ;
  input \stage_1_count_value_r_reg[1] ;
  input \stage_1_count_value_r_reg[2] ;
  input \stage_1_lane_mask_r_reg[3] ;
  input begin_r_reg;
  input reset_count_r_reg;
  input \counter2_r_reg[15] ;
  input good_as_r_reg;
  input good_as_r_reg_0;
  input good_as_r_reg_1;
  input [0:0]Q;
  input [0:0]good_as_r_reg_2;
  input [0:0]good_as_r_reg_3;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  input left_aligned_r_reg_0;
  input [1:0]\soft_err_r_reg[0] ;
  input [7:0]\word_aligned_data_r_reg[8] ;
  input [7:0]\word_aligned_data_r_reg[0]_0 ;

  wire [0:0]D;
  wire [0:1]GOT_A;
  wire GOT_V;
  wire HPCNT_RESET;
  wire [0:0]Q;
  wire RX_CC_Buffer;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  wire RX_ECP_Buffer0;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [2:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[10] ;
  wire \RX_PE_DATA_Buffer_reg[8] ;
  wire \RX_PE_DATA_Buffer_reg[8]_0 ;
  wire [0:0]RX_PE_DATA_V_Buffer_reg;
  wire [0:0]RX_SCP_Buffer_reg;
  wire RX_SUF;
  wire RX_SUF_Buffer_reg;
  wire RX_SUF_Buffer_reg_0;
  wire [0:0]SR;
  wire begin_r0;
  wire begin_r_reg;
  wire bucket_full_r;
  wire comma_over_two_cycles_r;
  wire \counter2_r_reg[15] ;
  wire ena_comma_align_i_0;
  wire enable_err_detect_i;
  wire first_v_received_r;
  wire good_as_r0;
  wire good_as_r_reg;
  wire good_as_r_reg_0;
  wire good_as_r_reg_1;
  wire [0:0]good_as_r_reg_2;
  wire [0:0]good_as_r_reg_3;
  wire gtp_rx_reset_i_0;
  wire hard_err_flop_r0;
  wire init_clk_in;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire link_reset_lane0_i;
  wire reset_count_r_reg;
  wire rx_lane_init_sm_simplex_i_n_6;
  wire rx_lane_init_sm_simplex_i_n_7;
  wire rx_polarity_i_0;
  wire rx_sp_i;
  wire [1:0]\soft_err_r_reg[0] ;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[2] ;
  wire \stage_1_lane_mask_r_reg[2] ;
  wire \stage_1_lane_mask_r_reg[3] ;
  wire start_rx_i;
  wire std_bool26_out;
  wire user_clk;
  wire user_clk_0;
  wire \word_aligned_control_bits_r_reg[0] ;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire [7:0]\word_aligned_data_r_reg[0] ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [4:0]\word_aligned_data_r_reg[11] ;
  wire [7:0]\word_aligned_data_r_reg[8] ;

  aurora_rx_4l_64b_HOTPLUG_16 aurora_rx_4l_64b_hotplug_i
       (.D(RX_CC_Buffer),
        .HPCNT_RESET(HPCNT_RESET),
        .SR(SR),
        .init_clk_in(init_clk_in),
        .link_reset_lane0_i(link_reset_lane0_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17 rx_err_detect_simplex_gtp_i
       (.D(D),
        .SR(SR),
        .begin_r0(begin_r0),
        .bucket_full_r(bucket_full_r),
        .enable_err_detect_i(enable_err_detect_i),
        .hard_err_flop_r0(hard_err_flop_r0),
        .hard_err_flop_r_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
        .user_clk(user_clk),
        .user_clk_0(user_clk_0));
  aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18 rx_lane_init_sm_simplex_i
       (.ENABLE_ERR_DETECT_Buffer_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\RX_CHAR_IS_COMMA_R_reg[1]_0 (\RX_CHAR_IS_COMMA_R_reg[1] ),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .SR(SR),
        .align_r_reg_0(ena_comma_align_i_0),
        .begin_r0(begin_r0),
        .begin_r_reg_0(begin_r_reg),
        .comma_over_two_cycles_r(comma_over_two_cycles_r),
        .\counter2_r_reg[15]_0 (\counter2_r_reg[15] ),
        .enable_err_detect_i(enable_err_detect_i),
        .gthe2_i(rx_lane_init_sm_simplex_i_n_6),
        .left_aligned_r_reg(left_aligned_r_reg_0),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .reset_count_r_reg_0(reset_count_r_reg),
        .rst_r_reg_0(gtp_rx_reset_i_0),
        .rx_polarity_i_0(rx_polarity_i_0),
        .rx_sp_i(rx_sp_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_SYM_DEC_19 sym_dec_i
       (.D(RX_CC_Buffer),
        .GOT_A(GOT_A),
        .GOT_V(GOT_V),
        .Q(Q),
        .RX_ECP_Buffer0(RX_ECP_Buffer0),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .RX_PE_DATA(RX_PE_DATA[0]),
        .\RX_PE_DATA_Buffer_reg[10]_0 (\RX_PE_DATA_Buffer_reg[10] ),
        .\RX_PE_DATA_Buffer_reg[8]_0 (RX_PE_DATA[2]),
        .\RX_PE_DATA_Buffer_reg[8]_1 (\RX_PE_DATA_Buffer_reg[8] ),
        .\RX_PE_DATA_Buffer_reg[8]_2 (\RX_PE_DATA_Buffer_reg[8]_0 ),
        .\RX_PE_DATA_Buffer_reg[9]_0 (RX_PE_DATA[1]),
        .RX_PE_DATA_V_Buffer_reg_0(RX_PE_DATA_V_Buffer_reg),
        .RX_SCP_Buffer_reg_0(RX_SCP_Buffer_reg),
        .RX_SUF_Buffer_reg_0(RX_SUF),
        .RX_SUF_Buffer_reg_1(RX_SUF_Buffer_reg),
        .RX_SUF_Buffer_reg_2(RX_SUF_Buffer_reg_0),
        .SR(SR),
        .first_v_received_r(first_v_received_r),
        .good_as_r0(good_as_r0),
        .good_as_r_reg(good_as_r_reg),
        .good_as_r_reg_0(good_as_r_reg_0),
        .good_as_r_reg_1(good_as_r_reg_1),
        .good_as_r_reg_2(good_as_r_reg_2),
        .good_as_r_reg_3(good_as_r_reg_3),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .left_aligned_r_reg_1(rx_lane_init_sm_simplex_i_n_6),
        .rx_sp_i(rx_sp_i),
        .\stage_1_count_value_r_reg[1] (\stage_1_count_value_r_reg[1] ),
        .\stage_1_count_value_r_reg[2] (\stage_1_count_value_r_reg[2] ),
        .\stage_1_lane_mask_r_reg[2] (\stage_1_lane_mask_r_reg[2] ),
        .\stage_1_lane_mask_r_reg[3] (\stage_1_lane_mask_r_reg[3] ),
        .start_rx_i(start_rx_i),
        .std_bool26_out(std_bool26_out),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[0]_0 (\word_aligned_control_bits_r_reg[0] ),
        .\word_aligned_control_bits_r_reg[1]_0 (\word_aligned_control_bits_r_reg[1] ),
        .\word_aligned_data_r_reg[0]_0 (\word_aligned_data_r_reg[0] ),
        .\word_aligned_data_r_reg[0]_1 (\word_aligned_data_r_reg[0]_0 ),
        .\word_aligned_data_r_reg[11]_0 (\word_aligned_data_r_reg[11] ),
        .\word_aligned_data_r_reg[8]_0 (\word_aligned_data_r_reg[8] ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5" *) 
module aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2
   (RX_LANE_UP,
    ena_comma_align_i_1,
    comma_over_two_cycles_r,
    gtp_rx_reset_i_1,
    GOT_V_Buffer_reg,
    bucket_full_r,
    D,
    link_reset_lane1_i,
    \RX_PE_DATA_Buffer_reg[9] ,
    \RX_PE_DATA_Buffer_reg[8] ,
    \RX_PE_DATA_Buffer_reg[10] ,
    RX_SCP_Buffer_reg,
    RX_SUF_Buffer_reg,
    rx_polarity_i_1,
    left_aligned_r_reg,
    RX_PE_DATA_V_Buffer_reg,
    user_clk_0,
    \RX_PE_DATA_Buffer_reg[10]_0 ,
    RX_SUF_Buffer_reg_0,
    \RX_PE_DATA_Buffer_reg[10]_1 ,
    \RX_PE_DATA_Buffer_reg[10]_2 ,
    Q,
    \word_aligned_data_r_reg[0] ,
    first_v_received_r,
    \GOT_A_Buffer_reg[1] ,
    \GOT_A_Buffer_reg[0] ,
    std_bool26_out,
    RX_ECP_Buffer0,
    SR,
    user_clk,
    \word_aligned_control_bits_r_reg[1] ,
    \word_aligned_control_bits_r_reg[0] ,
    hard_err_flop_r0,
    init_clk_in,
    HPCNT_RESET,
    \stage_1_count_value_r_reg[1] ,
    RX_SUF,
    \stage_1_count_value_r_reg[2] ,
    begin_r_reg,
    reset_count_r_reg,
    \counter2_r_reg[15] ,
    \RX_CHAR_IS_COMMA_R_reg[1] ,
    left_aligned_r_reg_0,
    \soft_err_r_reg[0] ,
    \word_aligned_data_r_reg[8] ,
    \word_aligned_data_r_reg[0]_0 );
  output [0:0]RX_LANE_UP;
  output ena_comma_align_i_1;
  output comma_over_two_cycles_r;
  output gtp_rx_reset_i_1;
  output GOT_V_Buffer_reg;
  output bucket_full_r;
  output [0:0]D;
  output link_reset_lane1_i;
  output \RX_PE_DATA_Buffer_reg[9] ;
  output \RX_PE_DATA_Buffer_reg[8] ;
  output \RX_PE_DATA_Buffer_reg[10] ;
  output [0:0]RX_SCP_Buffer_reg;
  output RX_SUF_Buffer_reg;
  output rx_polarity_i_1;
  output left_aligned_r_reg;
  output [0:0]RX_PE_DATA_V_Buffer_reg;
  output user_clk_0;
  output \RX_PE_DATA_Buffer_reg[10]_0 ;
  output RX_SUF_Buffer_reg_0;
  output \RX_PE_DATA_Buffer_reg[10]_1 ;
  output \RX_PE_DATA_Buffer_reg[10]_2 ;
  output [4:0]Q;
  output [7:0]\word_aligned_data_r_reg[0] ;
  output first_v_received_r;
  output [0:0]\GOT_A_Buffer_reg[1] ;
  output \GOT_A_Buffer_reg[0] ;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input [0:0]SR;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1] ;
  input \word_aligned_control_bits_r_reg[0] ;
  input hard_err_flop_r0;
  input init_clk_in;
  input HPCNT_RESET;
  input \stage_1_count_value_r_reg[1] ;
  input RX_SUF;
  input \stage_1_count_value_r_reg[2] ;
  input begin_r_reg;
  input reset_count_r_reg;
  input \counter2_r_reg[15] ;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  input left_aligned_r_reg_0;
  input [1:0]\soft_err_r_reg[0] ;
  input [7:0]\word_aligned_data_r_reg[8] ;
  input [7:0]\word_aligned_data_r_reg[0]_0 ;

  wire [0:0]D;
  wire \GOT_A_Buffer_reg[0] ;
  wire [0:0]\GOT_A_Buffer_reg[1] ;
  wire GOT_V_Buffer_reg;
  wire HPCNT_RESET;
  wire [4:0]Q;
  wire RX_CC_Buffer;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  wire RX_ECP_Buffer0;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire \RX_PE_DATA_Buffer_reg[10] ;
  wire \RX_PE_DATA_Buffer_reg[10]_0 ;
  wire \RX_PE_DATA_Buffer_reg[10]_1 ;
  wire \RX_PE_DATA_Buffer_reg[10]_2 ;
  wire \RX_PE_DATA_Buffer_reg[8] ;
  wire \RX_PE_DATA_Buffer_reg[9] ;
  wire [0:0]RX_PE_DATA_V_Buffer_reg;
  wire [0:0]RX_SCP_Buffer_reg;
  wire RX_SUF;
  wire RX_SUF_Buffer_reg;
  wire RX_SUF_Buffer_reg_0;
  wire [0:0]SR;
  wire begin_r0;
  wire begin_r_reg;
  wire bucket_full_r;
  wire comma_over_two_cycles_r;
  wire \counter2_r_reg[15] ;
  wire ena_comma_align_i_1;
  wire enable_err_detect_i;
  wire first_v_received_r;
  wire gtp_rx_reset_i_1;
  wire hard_err_flop_r0;
  wire init_clk_in;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire link_reset_lane1_i;
  wire reset_count_r_reg;
  wire rx_lane_init_sm_simplex_i_n_6;
  wire rx_lane_init_sm_simplex_i_n_7;
  wire rx_polarity_i_1;
  wire rx_sp_i;
  wire [1:0]\soft_err_r_reg[0] ;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[2] ;
  wire std_bool26_out;
  wire user_clk;
  wire user_clk_0;
  wire \word_aligned_control_bits_r_reg[0] ;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire [7:0]\word_aligned_data_r_reg[0] ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [7:0]\word_aligned_data_r_reg[8] ;

  aurora_rx_4l_64b_HOTPLUG_11 aurora_rx_4l_64b_hotplug_i
       (.D(RX_CC_Buffer),
        .HPCNT_RESET(HPCNT_RESET),
        .SR(SR),
        .init_clk_in(init_clk_in),
        .link_reset_lane1_i(link_reset_lane1_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12 rx_err_detect_simplex_gtp_i
       (.D(D),
        .SR(SR),
        .begin_r0(begin_r0),
        .bucket_full_r(bucket_full_r),
        .enable_err_detect_i(enable_err_detect_i),
        .hard_err_flop_r0(hard_err_flop_r0),
        .hard_err_flop_r_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
        .user_clk(user_clk),
        .user_clk_0(user_clk_0));
  aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13 rx_lane_init_sm_simplex_i
       (.ENABLE_ERR_DETECT_Buffer_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\RX_CHAR_IS_COMMA_R_reg[1]_0 (\RX_CHAR_IS_COMMA_R_reg[1] ),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .SR(SR),
        .align_r_reg_0(ena_comma_align_i_1),
        .begin_r0(begin_r0),
        .begin_r_reg_0(begin_r_reg),
        .comma_over_two_cycles_r(comma_over_two_cycles_r),
        .\counter2_r_reg[15]_0 (\counter2_r_reg[15] ),
        .enable_err_detect_i(enable_err_detect_i),
        .gthe2_i(rx_lane_init_sm_simplex_i_n_6),
        .left_aligned_r_reg(left_aligned_r_reg_0),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .reset_count_r_reg_0(reset_count_r_reg),
        .rst_r_reg_0(gtp_rx_reset_i_1),
        .rx_polarity_i_1(rx_polarity_i_1),
        .rx_sp_i(rx_sp_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_SYM_DEC_14 sym_dec_i
       (.D(RX_CC_Buffer),
        .\GOT_A_Buffer_reg[0]_0 (\GOT_A_Buffer_reg[0] ),
        .\GOT_A_Buffer_reg[1]_0 (\GOT_A_Buffer_reg[1] ),
        .GOT_V_Buffer_reg_0(GOT_V_Buffer_reg),
        .Q(Q),
        .RX_ECP_Buffer0(RX_ECP_Buffer0),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .\RX_PE_DATA_Buffer_reg[10]_0 (\RX_PE_DATA_Buffer_reg[10] ),
        .\RX_PE_DATA_Buffer_reg[10]_1 (\RX_PE_DATA_Buffer_reg[10]_0 ),
        .\RX_PE_DATA_Buffer_reg[10]_2 (\RX_PE_DATA_Buffer_reg[10]_1 ),
        .\RX_PE_DATA_Buffer_reg[10]_3 (\RX_PE_DATA_Buffer_reg[10]_2 ),
        .\RX_PE_DATA_Buffer_reg[8]_0 (\RX_PE_DATA_Buffer_reg[8] ),
        .\RX_PE_DATA_Buffer_reg[9]_0 (\RX_PE_DATA_Buffer_reg[9] ),
        .RX_PE_DATA_V_Buffer_reg_0(RX_PE_DATA_V_Buffer_reg),
        .RX_SCP_Buffer_reg_0(RX_SCP_Buffer_reg),
        .RX_SUF(RX_SUF),
        .RX_SUF_Buffer_reg_0(RX_SUF_Buffer_reg),
        .RX_SUF_Buffer_reg_1(RX_SUF_Buffer_reg_0),
        .SR(SR),
        .first_v_received_r(first_v_received_r),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .left_aligned_r_reg_1(rx_lane_init_sm_simplex_i_n_6),
        .rx_sp_i(rx_sp_i),
        .\stage_1_count_value_r_reg[1] (\stage_1_count_value_r_reg[1] ),
        .\stage_1_count_value_r_reg[2] (\stage_1_count_value_r_reg[2] ),
        .std_bool26_out(std_bool26_out),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[0]_0 (\word_aligned_control_bits_r_reg[0] ),
        .\word_aligned_control_bits_r_reg[1]_0 (\word_aligned_control_bits_r_reg[1] ),
        .\word_aligned_data_r_reg[0]_0 (\word_aligned_data_r_reg[0] ),
        .\word_aligned_data_r_reg[0]_1 (\word_aligned_data_r_reg[0]_0 ),
        .\word_aligned_data_r_reg[8]_0 (\word_aligned_data_r_reg[8] ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5" *) 
module aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3
   (RX_LANE_UP,
    ena_comma_align_i_2,
    comma_over_two_cycles_r,
    gtp_rx_reset_i_2,
    GOT_V_Buffer_reg,
    bucket_full_r,
    D,
    link_reset_lane2_i,
    \RX_PE_DATA_Buffer_reg[8] ,
    \RX_PE_DATA_Buffer_reg[10] ,
    \RX_PE_DATA_Buffer_reg[9] ,
    RX_SCP_Buffer_reg,
    RX_SUF_Buffer_reg,
    rx_polarity_i_2,
    left_aligned_r_reg,
    RX_PE_DATA_V_Buffer_reg,
    user_clk_0,
    neqOp,
    RX_SUF_Buffer_reg_0,
    Q,
    \word_aligned_data_r_reg[0] ,
    first_v_received_r,
    \GOT_A_Buffer_reg[1] ,
    \GOT_A_Buffer_reg[0] ,
    std_bool26_out,
    RX_ECP_Buffer0,
    SR,
    user_clk,
    \word_aligned_control_bits_r_reg[1] ,
    \word_aligned_control_bits_r_reg[0] ,
    hard_err_flop_r0,
    init_clk_in,
    HPCNT_RESET,
    load_ufc_control_code_r_reg,
    \stage_1_count_value_r_reg[3] ,
    \stage_1_count_value_r_reg[3]_0 ,
    \stage_1_count_value_r_reg[3]_1 ,
    begin_r_reg,
    reset_count_r_reg,
    \counter2_r_reg[15] ,
    \RX_CHAR_IS_COMMA_R_reg[1] ,
    left_aligned_r_reg_0,
    \soft_err_r_reg[0] ,
    \word_aligned_data_r_reg[8] ,
    \word_aligned_data_r_reg[0]_0 );
  output [0:0]RX_LANE_UP;
  output ena_comma_align_i_2;
  output comma_over_two_cycles_r;
  output gtp_rx_reset_i_2;
  output GOT_V_Buffer_reg;
  output bucket_full_r;
  output [0:0]D;
  output link_reset_lane2_i;
  output \RX_PE_DATA_Buffer_reg[8] ;
  output \RX_PE_DATA_Buffer_reg[10] ;
  output \RX_PE_DATA_Buffer_reg[9] ;
  output [0:0]RX_SCP_Buffer_reg;
  output RX_SUF_Buffer_reg;
  output rx_polarity_i_2;
  output left_aligned_r_reg;
  output [0:0]RX_PE_DATA_V_Buffer_reg;
  output user_clk_0;
  output neqOp;
  output RX_SUF_Buffer_reg_0;
  output [4:0]Q;
  output [7:0]\word_aligned_data_r_reg[0] ;
  output first_v_received_r;
  output [0:0]\GOT_A_Buffer_reg[1] ;
  output \GOT_A_Buffer_reg[0] ;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input [0:0]SR;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1] ;
  input \word_aligned_control_bits_r_reg[0] ;
  input hard_err_flop_r0;
  input init_clk_in;
  input HPCNT_RESET;
  input [2:0]load_ufc_control_code_r_reg;
  input \stage_1_count_value_r_reg[3] ;
  input \stage_1_count_value_r_reg[3]_0 ;
  input \stage_1_count_value_r_reg[3]_1 ;
  input begin_r_reg;
  input reset_count_r_reg;
  input \counter2_r_reg[15] ;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  input left_aligned_r_reg_0;
  input [1:0]\soft_err_r_reg[0] ;
  input [7:0]\word_aligned_data_r_reg[8] ;
  input [7:0]\word_aligned_data_r_reg[0]_0 ;

  wire [0:0]D;
  wire \GOT_A_Buffer_reg[0] ;
  wire [0:0]\GOT_A_Buffer_reg[1] ;
  wire GOT_V_Buffer_reg;
  wire HPCNT_RESET;
  wire [4:0]Q;
  wire RX_CC_Buffer;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  wire RX_ECP_Buffer0;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire \RX_PE_DATA_Buffer_reg[10] ;
  wire \RX_PE_DATA_Buffer_reg[8] ;
  wire \RX_PE_DATA_Buffer_reg[9] ;
  wire [0:0]RX_PE_DATA_V_Buffer_reg;
  wire [0:0]RX_SCP_Buffer_reg;
  wire RX_SUF_Buffer_reg;
  wire RX_SUF_Buffer_reg_0;
  wire [0:0]SR;
  wire begin_r0;
  wire begin_r_reg;
  wire bucket_full_r;
  wire comma_over_two_cycles_r;
  wire \counter2_r_reg[15] ;
  wire ena_comma_align_i_2;
  wire enable_err_detect_i;
  wire first_v_received_r;
  wire gtp_rx_reset_i_2;
  wire hard_err_flop_r0;
  wire init_clk_in;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire link_reset_lane2_i;
  wire [2:0]load_ufc_control_code_r_reg;
  wire neqOp;
  wire reset_count_r_reg;
  wire rx_lane_init_sm_simplex_i_n_6;
  wire rx_lane_init_sm_simplex_i_n_7;
  wire rx_polarity_i_2;
  wire rx_sp_i;
  wire [1:0]\soft_err_r_reg[0] ;
  wire \stage_1_count_value_r_reg[3] ;
  wire \stage_1_count_value_r_reg[3]_0 ;
  wire \stage_1_count_value_r_reg[3]_1 ;
  wire std_bool26_out;
  wire user_clk;
  wire user_clk_0;
  wire \word_aligned_control_bits_r_reg[0] ;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire [7:0]\word_aligned_data_r_reg[0] ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [7:0]\word_aligned_data_r_reg[8] ;

  aurora_rx_4l_64b_HOTPLUG_6 aurora_rx_4l_64b_hotplug_i
       (.D(RX_CC_Buffer),
        .HPCNT_RESET(HPCNT_RESET),
        .SR(SR),
        .init_clk_in(init_clk_in),
        .link_reset_lane2_i(link_reset_lane2_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7 rx_err_detect_simplex_gtp_i
       (.D(D),
        .SR(SR),
        .begin_r0(begin_r0),
        .bucket_full_r(bucket_full_r),
        .enable_err_detect_i(enable_err_detect_i),
        .hard_err_flop_r0(hard_err_flop_r0),
        .hard_err_flop_r_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
        .user_clk(user_clk),
        .user_clk_0(user_clk_0));
  aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8 rx_lane_init_sm_simplex_i
       (.ENABLE_ERR_DETECT_Buffer_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\RX_CHAR_IS_COMMA_R_reg[1]_0 (\RX_CHAR_IS_COMMA_R_reg[1] ),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .SR(SR),
        .align_r_reg_0(ena_comma_align_i_2),
        .begin_r0(begin_r0),
        .begin_r_reg_0(begin_r_reg),
        .comma_over_two_cycles_r(comma_over_two_cycles_r),
        .\counter2_r_reg[15]_0 (\counter2_r_reg[15] ),
        .enable_err_detect_i(enable_err_detect_i),
        .gthe2_i(rx_lane_init_sm_simplex_i_n_6),
        .left_aligned_r_reg(left_aligned_r_reg_0),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .reset_count_r_reg_0(reset_count_r_reg),
        .rst_r_reg_0(gtp_rx_reset_i_2),
        .rx_polarity_i_2(rx_polarity_i_2),
        .rx_sp_i(rx_sp_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_SYM_DEC_9 sym_dec_i
       (.D(RX_CC_Buffer),
        .\GOT_A_Buffer_reg[0]_0 (\GOT_A_Buffer_reg[0] ),
        .\GOT_A_Buffer_reg[1]_0 (\GOT_A_Buffer_reg[1] ),
        .GOT_V_Buffer_reg_0(GOT_V_Buffer_reg),
        .Q(Q),
        .RX_ECP_Buffer0(RX_ECP_Buffer0),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .\RX_PE_DATA_Buffer_reg[10]_0 (\RX_PE_DATA_Buffer_reg[10] ),
        .\RX_PE_DATA_Buffer_reg[8]_0 (\RX_PE_DATA_Buffer_reg[8] ),
        .\RX_PE_DATA_Buffer_reg[9]_0 (\RX_PE_DATA_Buffer_reg[9] ),
        .RX_PE_DATA_V_Buffer_reg_0(RX_PE_DATA_V_Buffer_reg),
        .RX_SCP_Buffer_reg_0(RX_SCP_Buffer_reg),
        .RX_SUF_Buffer_reg_0(RX_SUF_Buffer_reg),
        .RX_SUF_Buffer_reg_1(RX_SUF_Buffer_reg_0),
        .SR(SR),
        .first_v_received_r(first_v_received_r),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .left_aligned_r_reg_1(rx_lane_init_sm_simplex_i_n_6),
        .load_ufc_control_code_r_reg(load_ufc_control_code_r_reg),
        .neqOp(neqOp),
        .rx_sp_i(rx_sp_i),
        .\stage_1_count_value_r_reg[3] (\stage_1_count_value_r_reg[3] ),
        .\stage_1_count_value_r_reg[3]_0 (\stage_1_count_value_r_reg[3]_0 ),
        .\stage_1_count_value_r_reg[3]_1 (\stage_1_count_value_r_reg[3]_1 ),
        .std_bool26_out(std_bool26_out),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[0]_0 (\word_aligned_control_bits_r_reg[0] ),
        .\word_aligned_control_bits_r_reg[1]_0 (\word_aligned_control_bits_r_reg[1] ),
        .\word_aligned_data_r_reg[0]_0 (\word_aligned_data_r_reg[0] ),
        .\word_aligned_data_r_reg[0]_1 (\word_aligned_data_r_reg[0]_0 ),
        .\word_aligned_data_r_reg[8]_0 (\word_aligned_data_r_reg[8] ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5" *) 
module aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4
   (RX_LANE_UP,
    ena_comma_align_i_3,
    comma_over_two_cycles_r,
    gtp_rx_reset_i_3,
    GOT_V_Buffer_reg,
    bucket_full_r,
    D,
    \RX_PE_DATA_Buffer_reg[9] ,
    \RX_PE_DATA_Buffer_reg[8] ,
    \RX_PE_DATA_Buffer_reg[10] ,
    RX_SCP_Buffer_reg,
    RX_SUF_Buffer_reg,
    rx_polarity_i_3,
    left_aligned_r_reg,
    RX_PE_DATA_V_Buffer_reg,
    user_clk_0,
    RX_SUF_Buffer_reg_0,
    \RX_PE_DATA_Buffer_reg[9]_0 ,
    LINK_RESET_OUT,
    bad_as_r0,
    \GOT_A_Buffer_reg[0] ,
    Q,
    \RX_PE_DATA_Buffer_reg[9]_1 ,
    \word_aligned_data_r_reg[11] ,
    \word_aligned_data_r_reg[0] ,
    first_v_received_r,
    std_bool26_out,
    RX_ECP_Buffer0,
    SR,
    user_clk,
    \word_aligned_control_bits_r_reg[1] ,
    \word_aligned_control_bits_r_reg[0] ,
    hard_err_flop_r0,
    init_clk_in,
    HPCNT_RESET,
    \stage_1_count_value_r_reg[1] ,
    \stage_1_count_value_r_reg[1]_0 ,
    \stage_1_count_value_r_reg[2] ,
    RX_PE_DATA,
    \stage_1_count_value_r_reg[2]_0 ,
    link_reset_lane0_i,
    link_reset_lane1_i,
    link_reset_lane2_i,
    begin_r_reg,
    reset_count_r_reg,
    \counter2_r_reg[15] ,
    GOT_A,
    bad_as_r_reg,
    bad_as_r_reg_0,
    bad_as_r_reg_1,
    bad_as_r_reg_2,
    \RX_CHAR_IS_COMMA_R_reg[1] ,
    left_aligned_r_reg_0,
    \soft_err_r_reg[0] ,
    \word_aligned_data_r_reg[8] ,
    \word_aligned_data_r_reg[0]_0 );
  output [0:0]RX_LANE_UP;
  output ena_comma_align_i_3;
  output comma_over_two_cycles_r;
  output gtp_rx_reset_i_3;
  output GOT_V_Buffer_reg;
  output bucket_full_r;
  output [0:0]D;
  output \RX_PE_DATA_Buffer_reg[9] ;
  output \RX_PE_DATA_Buffer_reg[8] ;
  output \RX_PE_DATA_Buffer_reg[10] ;
  output [0:0]RX_SCP_Buffer_reg;
  output [0:0]RX_SUF_Buffer_reg;
  output rx_polarity_i_3;
  output left_aligned_r_reg;
  output [0:0]RX_PE_DATA_V_Buffer_reg;
  output user_clk_0;
  output RX_SUF_Buffer_reg_0;
  output \RX_PE_DATA_Buffer_reg[9]_0 ;
  output LINK_RESET_OUT;
  output bad_as_r0;
  output \GOT_A_Buffer_reg[0] ;
  output [0:0]Q;
  output \RX_PE_DATA_Buffer_reg[9]_1 ;
  output [4:0]\word_aligned_data_r_reg[11] ;
  output [7:0]\word_aligned_data_r_reg[0] ;
  output first_v_received_r;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input [0:0]SR;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1] ;
  input \word_aligned_control_bits_r_reg[0] ;
  input hard_err_flop_r0;
  input init_clk_in;
  input HPCNT_RESET;
  input \stage_1_count_value_r_reg[1] ;
  input \stage_1_count_value_r_reg[1]_0 ;
  input \stage_1_count_value_r_reg[2] ;
  input [0:0]RX_PE_DATA;
  input \stage_1_count_value_r_reg[2]_0 ;
  input link_reset_lane0_i;
  input link_reset_lane1_i;
  input link_reset_lane2_i;
  input begin_r_reg;
  input reset_count_r_reg;
  input \counter2_r_reg[15] ;
  input [0:1]GOT_A;
  input bad_as_r_reg;
  input bad_as_r_reg_0;
  input [0:0]bad_as_r_reg_1;
  input [0:0]bad_as_r_reg_2;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  input left_aligned_r_reg_0;
  input [1:0]\soft_err_r_reg[0] ;
  input [7:0]\word_aligned_data_r_reg[8] ;
  input [7:0]\word_aligned_data_r_reg[0]_0 ;

  wire [0:0]D;
  wire [0:1]GOT_A;
  wire \GOT_A_Buffer_reg[0] ;
  wire GOT_V_Buffer_reg;
  wire HPCNT_RESET;
  wire LINK_RESET_OUT;
  wire [0:0]Q;
  wire RX_CC_Buffer;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1] ;
  wire RX_ECP_Buffer0;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [0:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[10] ;
  wire \RX_PE_DATA_Buffer_reg[8] ;
  wire \RX_PE_DATA_Buffer_reg[9] ;
  wire \RX_PE_DATA_Buffer_reg[9]_0 ;
  wire \RX_PE_DATA_Buffer_reg[9]_1 ;
  wire [0:0]RX_PE_DATA_V_Buffer_reg;
  wire [0:0]RX_SCP_Buffer_reg;
  wire [0:0]RX_SUF_Buffer_reg;
  wire RX_SUF_Buffer_reg_0;
  wire [0:0]SR;
  wire bad_as_r0;
  wire bad_as_r_reg;
  wire bad_as_r_reg_0;
  wire [0:0]bad_as_r_reg_1;
  wire [0:0]bad_as_r_reg_2;
  wire begin_r0;
  wire begin_r_reg;
  wire bucket_full_r;
  wire comma_over_two_cycles_r;
  wire \counter2_r_reg[15] ;
  wire ena_comma_align_i_3;
  wire enable_err_detect_i;
  wire first_v_received_r;
  wire gtp_rx_reset_i_3;
  wire hard_err_flop_r0;
  wire init_clk_in;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire link_reset_lane0_i;
  wire link_reset_lane1_i;
  wire link_reset_lane2_i;
  wire reset_count_r_reg;
  wire rx_lane_init_sm_simplex_i_n_6;
  wire rx_lane_init_sm_simplex_i_n_7;
  wire rx_polarity_i_3;
  wire rx_sp_i;
  wire [1:0]\soft_err_r_reg[0] ;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[1]_0 ;
  wire \stage_1_count_value_r_reg[2] ;
  wire \stage_1_count_value_r_reg[2]_0 ;
  wire std_bool26_out;
  wire user_clk;
  wire user_clk_0;
  wire \word_aligned_control_bits_r_reg[0] ;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire [7:0]\word_aligned_data_r_reg[0] ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [4:0]\word_aligned_data_r_reg[11] ;
  wire [7:0]\word_aligned_data_r_reg[8] ;

  aurora_rx_4l_64b_HOTPLUG aurora_rx_4l_64b_hotplug_i
       (.D(RX_CC_Buffer),
        .HPCNT_RESET(HPCNT_RESET),
        .LINK_RESET_OUT(LINK_RESET_OUT),
        .SR(SR),
        .init_clk_in(init_clk_in),
        .link_reset_lane0_i(link_reset_lane0_i),
        .link_reset_lane1_i(link_reset_lane1_i),
        .link_reset_lane2_i(link_reset_lane2_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5 rx_err_detect_simplex_gtp_i
       (.D(D),
        .SR(SR),
        .begin_r0(begin_r0),
        .bucket_full_r(bucket_full_r),
        .enable_err_detect_i(enable_err_detect_i),
        .hard_err_flop_r0(hard_err_flop_r0),
        .hard_err_flop_r_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
        .user_clk(user_clk),
        .user_clk_0(user_clk_0));
  aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX rx_lane_init_sm_simplex_i
       (.ENABLE_ERR_DETECT_Buffer_reg_0(rx_lane_init_sm_simplex_i_n_7),
        .\RX_CHAR_IS_COMMA_R_reg[1]_0 (\RX_CHAR_IS_COMMA_R_reg[1] ),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .SR(SR),
        .align_r_reg_0(ena_comma_align_i_3),
        .begin_r0(begin_r0),
        .begin_r_reg_0(begin_r_reg),
        .comma_over_two_cycles_r(comma_over_two_cycles_r),
        .\counter2_r_reg[15]_0 (\counter2_r_reg[15] ),
        .enable_err_detect_i(enable_err_detect_i),
        .gthe2_i(rx_lane_init_sm_simplex_i_n_6),
        .left_aligned_r_reg(left_aligned_r_reg_0),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .reset_count_r_reg_0(reset_count_r_reg),
        .rst_r_reg_0(gtp_rx_reset_i_3),
        .rx_polarity_i_3(rx_polarity_i_3),
        .rx_sp_i(rx_sp_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_SYM_DEC sym_dec_i
       (.D(RX_CC_Buffer),
        .GOT_A(GOT_A),
        .\GOT_A_Buffer_reg[0]_0 (\GOT_A_Buffer_reg[0] ),
        .GOT_V_Buffer_reg_0(GOT_V_Buffer_reg),
        .Q(Q),
        .RX_ECP_Buffer0(RX_ECP_Buffer0),
        .RX_NEG_Buffer(RX_NEG_Buffer),
        .RX_PE_DATA(RX_PE_DATA),
        .\RX_PE_DATA_Buffer_reg[10]_0 (\RX_PE_DATA_Buffer_reg[10] ),
        .\RX_PE_DATA_Buffer_reg[8]_0 (\RX_PE_DATA_Buffer_reg[8] ),
        .\RX_PE_DATA_Buffer_reg[9]_0 (\RX_PE_DATA_Buffer_reg[9] ),
        .\RX_PE_DATA_Buffer_reg[9]_1 (\RX_PE_DATA_Buffer_reg[9]_0 ),
        .\RX_PE_DATA_Buffer_reg[9]_2 (\RX_PE_DATA_Buffer_reg[9]_1 ),
        .RX_PE_DATA_V_Buffer_reg_0(RX_PE_DATA_V_Buffer_reg),
        .RX_SCP_Buffer_reg_0(RX_SCP_Buffer_reg),
        .RX_SUF_Buffer_reg_0(RX_SUF_Buffer_reg),
        .RX_SUF_Buffer_reg_1(RX_SUF_Buffer_reg_0),
        .SR(SR),
        .bad_as_r0(bad_as_r0),
        .bad_as_r_reg(bad_as_r_reg),
        .bad_as_r_reg_0(bad_as_r_reg_0),
        .bad_as_r_reg_1(bad_as_r_reg_1),
        .bad_as_r_reg_2(bad_as_r_reg_2),
        .first_v_received_r(first_v_received_r),
        .left_aligned_r_reg_0(left_aligned_r_reg),
        .left_aligned_r_reg_1(rx_lane_init_sm_simplex_i_n_6),
        .rx_sp_i(rx_sp_i),
        .\stage_1_count_value_r_reg[1] (\stage_1_count_value_r_reg[1] ),
        .\stage_1_count_value_r_reg[1]_0 (\stage_1_count_value_r_reg[1]_0 ),
        .\stage_1_count_value_r_reg[2] (\stage_1_count_value_r_reg[2] ),
        .\stage_1_count_value_r_reg[2]_0 (\stage_1_count_value_r_reg[2]_0 ),
        .std_bool26_out(std_bool26_out),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[0]_0 (\word_aligned_control_bits_r_reg[0] ),
        .\word_aligned_control_bits_r_reg[1]_0 (\word_aligned_control_bits_r_reg[1] ),
        .\word_aligned_data_r_reg[0]_0 (\word_aligned_data_r_reg[0] ),
        .\word_aligned_data_r_reg[0]_1 (\word_aligned_data_r_reg[0]_0 ),
        .\word_aligned_data_r_reg[11]_0 (\word_aligned_data_r_reg[11] ),
        .\word_aligned_data_r_reg[8]_0 (\word_aligned_data_r_reg[8] ));
endmodule

module aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX
   (SOFT_ERR,
    RX_HARD_ERR,
    reset_channel_i,
    wait_for_lane_up_r0,
    user_clk,
    \soft_err_r_reg[0]_0 ,
    \soft_err_r_reg[1]_0 ,
    \soft_err_r_reg[2]_0 ,
    \soft_err_r_reg[3]_0 ,
    wait_for_lane_up_r_reg,
    POWER_DOWN,
    \hard_err_r_reg[0]_0 ,
    RX_LANE_UP);
  output SOFT_ERR;
  output RX_HARD_ERR;
  output reset_channel_i;
  output wait_for_lane_up_r0;
  input user_clk;
  input \soft_err_r_reg[0]_0 ;
  input \soft_err_r_reg[1]_0 ;
  input \soft_err_r_reg[2]_0 ;
  input \soft_err_r_reg[3]_0 ;
  input wait_for_lane_up_r_reg;
  input POWER_DOWN;
  input [3:0]\hard_err_r_reg[0]_0 ;
  input [0:3]RX_LANE_UP;

  wire POWER_DOWN;
  wire RESET_CHANNEL_Buffer0;
  wire RX_HARD_ERR;
  wire [0:3]RX_LANE_UP;
  wire SOFT_ERR;
  wire channel_hard_err_c__0;
  wire channel_soft_err_c__0;
  wire [3:0]\hard_err_r_reg[0]_0 ;
  wire \hard_err_r_reg_n_0_[0] ;
  wire \hard_err_r_reg_n_0_[3] ;
  wire \lane_up_r_reg_n_0_[0] ;
  wire \lane_up_r_reg_n_0_[2] ;
  wire \lane_up_r_reg_n_0_[3] ;
  wire p_0_in;
  wire p_0_in4_in;
  wire p_1_in2_in;
  wire p_1_in5_in;
  wire p_2_in;
  wire reset_channel_i;
  wire \soft_err_r_reg[0]_0 ;
  wire \soft_err_r_reg[1]_0 ;
  wire \soft_err_r_reg[2]_0 ;
  wire \soft_err_r_reg[3]_0 ;
  wire \soft_err_r_reg_n_0_[0] ;
  wire \soft_err_r_reg_n_0_[3] ;
  wire user_clk;
  wire wait_for_lane_up_r0;
  wire wait_for_lane_up_r_reg;

  FDRE #(
    .INIT(1'b1)) 
    CHANNEL_HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(channel_hard_err_c__0),
        .Q(RX_HARD_ERR),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    CHANNEL_SOFT_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(channel_soft_err_c__0),
        .Q(SOFT_ERR),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    RESET_CHANNEL_Buffer_i_1
       (.I0(\lane_up_r_reg_n_0_[2] ),
        .I1(p_2_in),
        .I2(\lane_up_r_reg_n_0_[0] ),
        .I3(\lane_up_r_reg_n_0_[3] ),
        .I4(POWER_DOWN),
        .O(RESET_CHANNEL_Buffer0));
  FDRE #(
    .INIT(1'b1)) 
    RESET_CHANNEL_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RESET_CHANNEL_Buffer0),
        .Q(reset_channel_i),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    channel_hard_err_c
       (.I0(\hard_err_r_reg_n_0_[3] ),
        .I1(\hard_err_r_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(p_1_in2_in),
        .O(channel_hard_err_c__0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    channel_soft_err_c
       (.I0(\soft_err_r_reg_n_0_[3] ),
        .I1(\soft_err_r_reg_n_0_[0] ),
        .I2(p_0_in4_in),
        .I3(p_1_in5_in),
        .O(channel_soft_err_c__0));
  FDRE \hard_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\hard_err_r_reg[0]_0 [3]),
        .Q(\hard_err_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \hard_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\hard_err_r_reg[0]_0 [2]),
        .Q(p_0_in),
        .R(1'b0));
  FDRE \hard_err_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\hard_err_r_reg[0]_0 [1]),
        .Q(p_1_in2_in),
        .R(1'b0));
  FDRE \hard_err_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\hard_err_r_reg[0]_0 [0]),
        .Q(\hard_err_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \lane_up_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_LANE_UP[0]),
        .Q(\lane_up_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \lane_up_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_LANE_UP[1]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \lane_up_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_LANE_UP[2]),
        .Q(\lane_up_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \lane_up_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_LANE_UP[3]),
        .Q(\lane_up_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \soft_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 ),
        .Q(\soft_err_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \soft_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[1]_0 ),
        .Q(p_0_in4_in),
        .R(1'b0));
  FDRE \soft_err_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[2]_0 ),
        .Q(p_1_in5_in),
        .R(1'b0));
  FDRE \soft_err_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[3]_0 ),
        .Q(\soft_err_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    wait_for_lane_up_r_i_1
       (.I0(reset_channel_i),
        .I1(wait_for_lane_up_r_reg),
        .O(wait_for_lane_up_r0));
endmodule

module aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX
   (SR,
    reset_lanes_flop_1_i_0,
    reset_lanes_flop_2_i_0,
    reset_lanes_flop_3_i_0,
    en_chan_sync_i,
    CHANNEL_UP_Buffer_reg_0,
    start_rx_i,
    gtrxreset_i,
    D,
    START_RX_Buffer_reg_0,
    RESET,
    user_clk,
    GOT_V,
    all_lanes_v_r_reg_0,
    all_lanes_v_r_reg_1,
    all_lanes_v_r_reg_2,
    bad_as_r0,
    wait_for_lane_up_r0,
    good_as_r0,
    START_RX_Buffer_reg_1,
    CHBONDDONE_OUT_LANE3,
    CHBONDDONE_OUT,
    CHBONDDONE_OUT_LANE2,
    CHBONDDONE_OUT_LANE1,
    RX_SUF,
    reset_channel_i,
    Q);
  output [0:0]SR;
  output [0:0]reset_lanes_flop_1_i_0;
  output [0:0]reset_lanes_flop_2_i_0;
  output [0:0]reset_lanes_flop_3_i_0;
  output en_chan_sync_i;
  output CHANNEL_UP_Buffer_reg_0;
  output start_rx_i;
  output gtrxreset_i;
  output [3:0]D;
  output START_RX_Buffer_reg_0;
  output RESET;
  input user_clk;
  input GOT_V;
  input all_lanes_v_r_reg_0;
  input all_lanes_v_r_reg_1;
  input all_lanes_v_r_reg_2;
  input bad_as_r0;
  input wait_for_lane_up_r0;
  input good_as_r0;
  input START_RX_Buffer_reg_1;
  input CHBONDDONE_OUT_LANE3;
  input CHBONDDONE_OUT;
  input CHBONDDONE_OUT_LANE2;
  input CHBONDDONE_OUT_LANE1;
  input RX_SUF;
  input reset_channel_i;
  input [3:0]Q;

  wire CHANNEL_UP_Buffer_reg_0;
  wire CHBONDDONE_OUT;
  wire CHBONDDONE_OUT_LANE1;
  wire CHBONDDONE_OUT_LANE2;
  wire CHBONDDONE_OUT_LANE3;
  wire [3:0]D;
  wire D_1;
  wire GOT_V;
  wire GTRXRESET_OUT_i_1_n_0;
  wire GTRXRESET_OUT_i_2_n_0;
  wire [3:0]Q;
  wire Q_0;
  wire RESET;
  wire RX_SUF;
  wire [0:0]SR;
  wire START_RX_Buffer0;
  wire START_RX_Buffer_reg_0;
  wire START_RX_Buffer_reg_1;
  wire \a_count_r[0]_i_1_n_0 ;
  wire \a_count_r[1]_i_1_n_0 ;
  wire \a_count_r[2]_i_1_n_0 ;
  wire \a_count_r_reg_n_0_[1] ;
  wire \a_count_r_reg_n_0_[2] ;
  wire all_ch_bond_done_r;
  wire all_ch_bond_done_r_i_1_n_0;
  wire all_channel_bond_load_c__0;
  wire all_channel_bond_load_r;
  wire all_lanes_v_c__0;
  wire all_lanes_v_r;
  wire all_lanes_v_r_reg_0;
  wire all_lanes_v_r_reg_1;
  wire all_lanes_v_r_reg_2;
  wire bad_as_r;
  wire bad_as_r0;
  wire bad_v_r;
  wire bad_v_r0;
  wire bond_passed_r;
  wire bonding_watchdog_r0;
  wire \bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ;
  wire \bonding_watchdog_r_reg[14]_srl15_i_3_n_0 ;
  wire \bonding_watchdog_r_reg[14]_srl15_i_4_n_0 ;
  wire \bonding_watchdog_r_reg[14]_srl15_n_0 ;
  wire \bonding_watchdog_r_reg_n_0_[15] ;
  wire \channel_bond_load_r_reg_n_0_[0] ;
  wire \channel_bond_load_r_reg_n_0_[3] ;
  wire channel_bond_r;
  wire check_bond_r;
  wire en_chan_sync_i;
  wire four_as_r;
  wire \free_count_r[13]_i_2_n_0 ;
  wire \free_count_r[13]_i_3_n_0 ;
  wire \free_count_r[13]_i_4_n_0 ;
  wire \free_count_r[13]_i_5_n_0 ;
  wire \free_count_r[1]_i_2_n_0 ;
  wire \free_count_r[1]_i_3_n_0 ;
  wire \free_count_r[5]_i_2_n_0 ;
  wire \free_count_r[5]_i_3_n_0 ;
  wire \free_count_r[5]_i_4_n_0 ;
  wire \free_count_r[5]_i_5_n_0 ;
  wire \free_count_r[9]_i_2_n_0 ;
  wire \free_count_r[9]_i_3_n_0 ;
  wire \free_count_r[9]_i_4_n_0 ;
  wire \free_count_r[9]_i_5_n_0 ;
  wire [0:13]free_count_r_reg;
  wire \free_count_r_reg[13]_i_1_n_0 ;
  wire \free_count_r_reg[13]_i_1_n_1 ;
  wire \free_count_r_reg[13]_i_1_n_2 ;
  wire \free_count_r_reg[13]_i_1_n_3 ;
  wire \free_count_r_reg[13]_i_1_n_4 ;
  wire \free_count_r_reg[13]_i_1_n_5 ;
  wire \free_count_r_reg[13]_i_1_n_6 ;
  wire \free_count_r_reg[13]_i_1_n_7 ;
  wire \free_count_r_reg[1]_i_1_n_3 ;
  wire \free_count_r_reg[1]_i_1_n_6 ;
  wire \free_count_r_reg[1]_i_1_n_7 ;
  wire \free_count_r_reg[5]_i_1_n_0 ;
  wire \free_count_r_reg[5]_i_1_n_1 ;
  wire \free_count_r_reg[5]_i_1_n_2 ;
  wire \free_count_r_reg[5]_i_1_n_3 ;
  wire \free_count_r_reg[5]_i_1_n_4 ;
  wire \free_count_r_reg[5]_i_1_n_5 ;
  wire \free_count_r_reg[5]_i_1_n_6 ;
  wire \free_count_r_reg[5]_i_1_n_7 ;
  wire \free_count_r_reg[9]_i_1_n_0 ;
  wire \free_count_r_reg[9]_i_1_n_1 ;
  wire \free_count_r_reg[9]_i_1_n_2 ;
  wire \free_count_r_reg[9]_i_1_n_3 ;
  wire \free_count_r_reg[9]_i_1_n_4 ;
  wire \free_count_r_reg[9]_i_1_n_5 ;
  wire \free_count_r_reg[9]_i_1_n_6 ;
  wire \free_count_r_reg[9]_i_1_n_7 ;
  wire good_as_r;
  wire good_as_r0;
  wire got_first_v_r;
  wire got_first_v_r_i_1_n_0;
  wire gtreset_flop_0_i_i_2_n_0;
  wire [7:0]gtrxreset_extend_r;
  wire gtrxreset_i;
  wire next_channel_bond_c;
  wire next_check_bond_c;
  wire next_ready_c;
  wire next_verify_c;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire [31:31]p_2_out;
  wire p_5_in6_in;
  wire ready_r;
  wire ready_r2;
  wire reset_channel_i;
  wire [0:0]reset_lanes_flop_1_i_0;
  wire [0:0]reset_lanes_flop_2_i_0;
  wire [0:0]reset_lanes_flop_3_i_0;
  wire \rxver_count_r_reg[1]_srl2_i_1_n_0 ;
  wire \rxver_count_r_reg[1]_srl2_n_0 ;
  wire \rxver_count_r_reg_n_0_[2] ;
  wire start_rx_i;
  wire user_clk;
  wire \v_count_r_reg[30]_srl31_n_0 ;
  wire \v_count_r_reg_n_0_[31] ;
  wire verify_r;
  wire \verify_watchdog_r_reg[14]_srl15_i_1_n_0 ;
  wire \verify_watchdog_r_reg[14]_srl15_n_0 ;
  wire \verify_watchdog_r_reg_n_0_[15] ;
  wire wait_for_lane_up_r;
  wire wait_for_lane_up_r0;
  wire [3:1]\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED ;
  wire \NLW_v_count_r_reg[30]_srl31_Q31_UNCONNECTED ;

  FDRE CHANNEL_UP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ready_r2),
        .Q(CHANNEL_UP_Buffer_reg_0),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    FRAME_ERR_Buffer_i_1
       (.I0(start_rx_i),
        .O(RESET));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    GTRXRESET_OUT_i_1
       (.I0(gtrxreset_extend_r[2]),
        .I1(gtrxreset_extend_r[3]),
        .I2(gtrxreset_extend_r[0]),
        .I3(gtrxreset_extend_r[1]),
        .I4(GTRXRESET_OUT_i_2_n_0),
        .O(GTRXRESET_OUT_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    GTRXRESET_OUT_i_2
       (.I0(gtrxreset_extend_r[5]),
        .I1(gtrxreset_extend_r[4]),
        .I2(gtrxreset_extend_r[7]),
        .I3(gtrxreset_extend_r[6]),
        .O(GTRXRESET_OUT_i_2_n_0));
  FDRE GTRXRESET_OUT_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(GTRXRESET_OUT_i_1_n_0),
        .Q(gtrxreset_i),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    START_RX_Buffer_i_1
       (.I0(wait_for_lane_up_r),
        .O(START_RX_Buffer0));
  FDRE START_RX_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(START_RX_Buffer0),
        .Q(start_rx_i),
        .R(START_RX_Buffer_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \a_count_r[0]_i_1 
       (.I0(four_as_r),
        .I1(good_as_r),
        .I2(\a_count_r_reg_n_0_[2] ),
        .I3(\a_count_r_reg_n_0_[1] ),
        .I4(check_bond_r),
        .O(\a_count_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \a_count_r[1]_i_1 
       (.I0(\a_count_r_reg_n_0_[1] ),
        .I1(good_as_r),
        .I2(\a_count_r_reg_n_0_[2] ),
        .I3(check_bond_r),
        .O(\a_count_r[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h60)) 
    \a_count_r[2]_i_1 
       (.I0(\a_count_r_reg_n_0_[2] ),
        .I1(good_as_r),
        .I2(check_bond_r),
        .O(\a_count_r[2]_i_1_n_0 ));
  FDRE \a_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\a_count_r[0]_i_1_n_0 ),
        .Q(four_as_r),
        .R(1'b0));
  FDRE \a_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\a_count_r[1]_i_1_n_0 ),
        .Q(\a_count_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \a_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\a_count_r[2]_i_1_n_0 ),
        .Q(\a_count_r_reg_n_0_[2] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    all_ch_bond_done_r_i_1
       (.I0(D[2]),
        .I1(channel_bond_r),
        .I2(D[1]),
        .I3(D[3]),
        .I4(D[0]),
        .O(all_ch_bond_done_r_i_1_n_0));
  FDRE all_ch_bond_done_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(all_ch_bond_done_r_i_1_n_0),
        .Q(all_ch_bond_done_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    all_channel_bond_load_c
       (.I0(\channel_bond_load_r_reg_n_0_[3] ),
        .I1(\channel_bond_load_r_reg_n_0_[0] ),
        .I2(p_1_in8_in),
        .I3(p_0_in7_in),
        .O(all_channel_bond_load_c__0));
  FDRE all_channel_bond_load_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(all_channel_bond_load_c__0),
        .Q(all_channel_bond_load_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    all_lanes_v_c
       (.I0(GOT_V),
        .I1(all_lanes_v_r_reg_0),
        .I2(all_lanes_v_r_reg_1),
        .I3(all_lanes_v_r_reg_2),
        .O(all_lanes_v_c__0));
  FDRE all_lanes_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(all_lanes_v_c__0),
        .Q(all_lanes_v_r),
        .R(1'b0));
  FDRE bad_as_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(bad_as_r0),
        .Q(bad_as_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h28)) 
    bad_v_r_i_1
       (.I0(got_first_v_r),
        .I1(all_lanes_v_r),
        .I2(\v_count_r_reg_n_0_[31] ),
        .O(bad_v_r0));
  FDRE bad_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(bad_v_r0),
        .Q(bad_v_r),
        .R(1'b0));
  FDRE bond_passed_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(all_ch_bond_done_r),
        .Q(bond_passed_r),
        .R(1'b0));
  (* srl_bus_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/bonding_watchdog_r_reg " *) 
  (* srl_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/bonding_watchdog_r_reg[14]_srl15 " *) 
  SRL16E \bonding_watchdog_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(bonding_watchdog_r0),
        .CLK(user_clk),
        .D(channel_bond_r),
        .Q(\bonding_watchdog_r_reg[14]_srl15_n_0 ));
  LUT4 #(
    .INIT(16'hFFAB)) 
    \bonding_watchdog_r_reg[14]_srl15_i_1 
       (.I0(\bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ),
        .I1(check_bond_r),
        .I2(channel_bond_r),
        .I3(all_channel_bond_load_r),
        .O(bonding_watchdog_r0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \bonding_watchdog_r_reg[14]_srl15_i_2 
       (.I0(\bonding_watchdog_r_reg[14]_srl15_i_3_n_0 ),
        .I1(\bonding_watchdog_r_reg[14]_srl15_i_4_n_0 ),
        .I2(free_count_r_reg[0]),
        .I3(free_count_r_reg[10]),
        .I4(free_count_r_reg[3]),
        .I5(free_count_r_reg[6]),
        .O(\bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \bonding_watchdog_r_reg[14]_srl15_i_3 
       (.I0(free_count_r_reg[11]),
        .I1(free_count_r_reg[13]),
        .I2(free_count_r_reg[9]),
        .I3(free_count_r_reg[1]),
        .I4(free_count_r_reg[8]),
        .I5(free_count_r_reg[7]),
        .O(\bonding_watchdog_r_reg[14]_srl15_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \bonding_watchdog_r_reg[14]_srl15_i_4 
       (.I0(free_count_r_reg[4]),
        .I1(free_count_r_reg[5]),
        .I2(free_count_r_reg[2]),
        .I3(free_count_r_reg[12]),
        .O(\bonding_watchdog_r_reg[14]_srl15_i_4_n_0 ));
  FDRE \bonding_watchdog_r_reg[15] 
       (.C(user_clk),
        .CE(bonding_watchdog_r0),
        .D(\bonding_watchdog_r_reg[14]_srl15_n_0 ),
        .Q(\bonding_watchdog_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \ch_bond_done_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(CHBONDDONE_OUT_LANE3),
        .Q(D[3]),
        .R(1'b0));
  FDRE \ch_bond_done_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(CHBONDDONE_OUT_LANE2),
        .Q(D[2]),
        .R(1'b0));
  FDRE \ch_bond_done_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(CHBONDDONE_OUT_LANE1),
        .Q(D[1]),
        .R(1'b0));
  FDRE \ch_bond_done_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(CHBONDDONE_OUT),
        .Q(D[0]),
        .R(1'b0));
  FDRE \channel_bond_load_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[3]),
        .Q(\channel_bond_load_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \channel_bond_load_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[2]),
        .Q(p_0_in7_in),
        .R(1'b0));
  FDRE \channel_bond_load_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[1]),
        .Q(p_1_in8_in),
        .R(1'b0));
  FDRE \channel_bond_load_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[0]),
        .Q(\channel_bond_load_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF444)) 
    channel_bond_r_i_1
       (.I0(bond_passed_r),
        .I1(channel_bond_r),
        .I2(bad_as_r),
        .I3(check_bond_r),
        .I4(wait_for_lane_up_r),
        .O(next_channel_bond_c));
  FDRE channel_bond_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_channel_bond_c),
        .Q(channel_bond_r),
        .R(wait_for_lane_up_r0));
  LUT5 #(
    .INIT(32'hFF040404)) 
    check_bond_r_i_1
       (.I0(bad_as_r),
        .I1(check_bond_r),
        .I2(four_as_r),
        .I3(bond_passed_r),
        .I4(channel_bond_r),
        .O(next_check_bond_c));
  FDRE check_bond_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_check_bond_c),
        .Q(check_bond_r),
        .R(wait_for_lane_up_r0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    en_chan_sync_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(channel_bond_r),
        .Q(en_chan_sync_i),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_2 
       (.I0(free_count_r_reg[10]),
        .O(\free_count_r[13]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_3 
       (.I0(free_count_r_reg[11]),
        .O(\free_count_r[13]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_4 
       (.I0(free_count_r_reg[12]),
        .O(\free_count_r[13]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[13]_i_5 
       (.I0(free_count_r_reg[13]),
        .O(\free_count_r[13]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[1]_i_2 
       (.I0(free_count_r_reg[0]),
        .O(\free_count_r[1]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[1]_i_3 
       (.I0(free_count_r_reg[1]),
        .O(\free_count_r[1]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_2 
       (.I0(free_count_r_reg[2]),
        .O(\free_count_r[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_3 
       (.I0(free_count_r_reg[3]),
        .O(\free_count_r[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_4 
       (.I0(free_count_r_reg[4]),
        .O(\free_count_r[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[5]_i_5 
       (.I0(free_count_r_reg[5]),
        .O(\free_count_r[5]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_2 
       (.I0(free_count_r_reg[6]),
        .O(\free_count_r[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_3 
       (.I0(free_count_r_reg[7]),
        .O(\free_count_r[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_4 
       (.I0(free_count_r_reg[8]),
        .O(\free_count_r[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \free_count_r[9]_i_5 
       (.I0(free_count_r_reg[9]),
        .O(\free_count_r[9]_i_5_n_0 ));
  FDSE \free_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[1]_i_1_n_6 ),
        .Q(free_count_r_reg[0]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_4 ),
        .Q(free_count_r_reg[10]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_5 ),
        .Q(free_count_r_reg[11]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_6 ),
        .Q(free_count_r_reg[12]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[13]_i_1_n_7 ),
        .Q(free_count_r_reg[13]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[13]_i_1 
       (.CI(1'b0),
        .CO({\free_count_r_reg[13]_i_1_n_0 ,\free_count_r_reg[13]_i_1_n_1 ,\free_count_r_reg[13]_i_1_n_2 ,\free_count_r_reg[13]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[13]_i_1_n_4 ,\free_count_r_reg[13]_i_1_n_5 ,\free_count_r_reg[13]_i_1_n_6 ,\free_count_r_reg[13]_i_1_n_7 }),
        .S({\free_count_r[13]_i_2_n_0 ,\free_count_r[13]_i_3_n_0 ,\free_count_r[13]_i_4_n_0 ,\free_count_r[13]_i_5_n_0 }));
  FDSE \free_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[1]_i_1_n_7 ),
        .Q(free_count_r_reg[1]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[1]_i_1 
       (.CI(\free_count_r_reg[5]_i_1_n_0 ),
        .CO({\NLW_free_count_r_reg[1]_i_1_CO_UNCONNECTED [3:1],\free_count_r_reg[1]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\NLW_free_count_r_reg[1]_i_1_O_UNCONNECTED [3:2],\free_count_r_reg[1]_i_1_n_6 ,\free_count_r_reg[1]_i_1_n_7 }),
        .S({1'b0,1'b0,\free_count_r[1]_i_2_n_0 ,\free_count_r[1]_i_3_n_0 }));
  FDSE \free_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_4 ),
        .Q(free_count_r_reg[2]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_5 ),
        .Q(free_count_r_reg[3]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_6 ),
        .Q(free_count_r_reg[4]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[5]_i_1_n_7 ),
        .Q(free_count_r_reg[5]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[5]_i_1 
       (.CI(\free_count_r_reg[9]_i_1_n_0 ),
        .CO({\free_count_r_reg[5]_i_1_n_0 ,\free_count_r_reg[5]_i_1_n_1 ,\free_count_r_reg[5]_i_1_n_2 ,\free_count_r_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[5]_i_1_n_4 ,\free_count_r_reg[5]_i_1_n_5 ,\free_count_r_reg[5]_i_1_n_6 ,\free_count_r_reg[5]_i_1_n_7 }),
        .S({\free_count_r[5]_i_2_n_0 ,\free_count_r[5]_i_3_n_0 ,\free_count_r[5]_i_4_n_0 ,\free_count_r[5]_i_5_n_0 }));
  FDSE \free_count_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_4 ),
        .Q(free_count_r_reg[6]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_5 ),
        .Q(free_count_r_reg[7]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_6 ),
        .Q(free_count_r_reg[8]),
        .S(wait_for_lane_up_r0));
  FDSE \free_count_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\free_count_r_reg[9]_i_1_n_7 ),
        .Q(free_count_r_reg[9]),
        .S(wait_for_lane_up_r0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \free_count_r_reg[9]_i_1 
       (.CI(\free_count_r_reg[13]_i_1_n_0 ),
        .CO({\free_count_r_reg[9]_i_1_n_0 ,\free_count_r_reg[9]_i_1_n_1 ,\free_count_r_reg[9]_i_1_n_2 ,\free_count_r_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\free_count_r_reg[9]_i_1_n_4 ,\free_count_r_reg[9]_i_1_n_5 ,\free_count_r_reg[9]_i_1_n_6 ,\free_count_r_reg[9]_i_1_n_7 }),
        .S({\free_count_r[9]_i_2_n_0 ,\free_count_r[9]_i_3_n_0 ,\free_count_r[9]_i_4_n_0 ,\free_count_r[9]_i_5_n_0 }));
  FDRE good_as_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(good_as_r0),
        .Q(good_as_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hA8)) 
    got_first_v_r_i_1
       (.I0(verify_r),
        .I1(got_first_v_r),
        .I2(all_lanes_v_r),
        .O(got_first_v_r_i_1_n_0));
  FDRE got_first_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(got_first_v_r_i_1_n_0),
        .Q(got_first_v_r),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    gtreset_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(p_5_in6_in),
        .Q(Q_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hF444F444F4F4F444)) 
    gtreset_flop_0_i_i_1
       (.I0(gtreset_flop_0_i_i_2_n_0),
        .I1(\bonding_watchdog_r_reg_n_0_[15] ),
        .I2(verify_r),
        .I3(\verify_watchdog_r_reg_n_0_[15] ),
        .I4(bad_v_r),
        .I5(\rxver_count_r_reg_n_0_[2] ),
        .O(p_5_in6_in));
  LUT2 #(
    .INIT(4'h1)) 
    gtreset_flop_0_i_i_2
       (.I0(check_bond_r),
        .I1(channel_bond_r),
        .O(gtreset_flop_0_i_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[1]),
        .Q(gtrxreset_extend_r[0]),
        .R(START_RX_Buffer_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[2]),
        .Q(gtrxreset_extend_r[1]),
        .R(START_RX_Buffer_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[3]),
        .Q(gtrxreset_extend_r[2]),
        .R(START_RX_Buffer_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[4]),
        .Q(gtrxreset_extend_r[3]),
        .R(START_RX_Buffer_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[5]),
        .Q(gtrxreset_extend_r[4]),
        .R(START_RX_Buffer_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[6]),
        .Q(gtrxreset_extend_r[5]),
        .R(START_RX_Buffer_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_extend_r[7]),
        .Q(gtrxreset_extend_r[6]),
        .R(START_RX_Buffer_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \gtrxreset_extend_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q_0),
        .Q(gtrxreset_extend_r[7]),
        .R(START_RX_Buffer_reg_1));
  FDRE ready_r2_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ready_r),
        .Q(ready_r2),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hEA)) 
    ready_r_i_1__3
       (.I0(ready_r),
        .I1(verify_r),
        .I2(\rxver_count_r_reg_n_0_[2] ),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(ready_r),
        .R(wait_for_lane_up_r0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_0_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_1),
        .Q(SR),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFAE)) 
    reset_lanes_flop_0_i_i_1
       (.I0(p_5_in6_in),
        .I1(reset_channel_i),
        .I2(wait_for_lane_up_r),
        .I3(START_RX_Buffer_reg_1),
        .O(D_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_1_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_1),
        .Q(reset_lanes_flop_1_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_2_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_1),
        .Q(reset_lanes_flop_2_i_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    reset_lanes_flop_3_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D_1),
        .Q(reset_lanes_flop_3_i_0),
        .R(1'b0));
  (* srl_bus_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg " *) 
  (* srl_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/rxver_count_r_reg[1]_srl2 " *) 
  SRL16E \rxver_count_r_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\rxver_count_r_reg[1]_srl2_i_1_n_0 ),
        .CLK(user_clk),
        .D(verify_r),
        .Q(\rxver_count_r_reg[1]_srl2_n_0 ));
  LUT3 #(
    .INIT(8'h8F)) 
    \rxver_count_r_reg[1]_srl2_i_1 
       (.I0(all_lanes_v_r),
        .I1(\v_count_r_reg_n_0_[31] ),
        .I2(verify_r),
        .O(\rxver_count_r_reg[1]_srl2_i_1_n_0 ));
  FDRE \rxver_count_r_reg[2] 
       (.C(user_clk),
        .CE(\rxver_count_r_reg[1]_srl2_i_1_n_0 ),
        .D(\rxver_count_r_reg[1]_srl2_n_0 ),
        .Q(\rxver_count_r_reg_n_0_[2] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    \stage_1_lane_mask_r[1]_i_1 
       (.I0(start_rx_i),
        .I1(RX_SUF),
        .O(START_RX_Buffer_reg_0));
  (* srl_bus_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg " *) 
  (* srl_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/v_count_r_reg[30]_srl31 " *) 
  SRLC32E \v_count_r_reg[30]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(user_clk),
        .D(p_2_out),
        .Q(\v_count_r_reg[30]_srl31_n_0 ),
        .Q31(\NLW_v_count_r_reg[30]_srl31_Q31_UNCONNECTED ));
  LUT4 #(
    .INIT(16'h8F88)) 
    \v_count_r_reg[30]_srl31_i_1 
       (.I0(\v_count_r_reg_n_0_[31] ),
        .I1(verify_r),
        .I2(got_first_v_r),
        .I3(all_lanes_v_r),
        .O(p_2_out));
  FDRE \v_count_r_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\v_count_r_reg[30]_srl31_n_0 ),
        .Q(\v_count_r_reg_n_0_[31] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h22F22222)) 
    verify_r_i_1
       (.I0(verify_r),
        .I1(\rxver_count_r_reg_n_0_[2] ),
        .I2(four_as_r),
        .I3(bad_as_r),
        .I4(check_bond_r),
        .O(next_verify_c));
  FDRE verify_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_verify_c),
        .Q(verify_r),
        .R(wait_for_lane_up_r0));
  (* srl_bus_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg " *) 
  (* srl_name = "U0/\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/verify_watchdog_r_reg[14]_srl15 " *) 
  SRL16E \verify_watchdog_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(\verify_watchdog_r_reg[14]_srl15_i_1_n_0 ),
        .CLK(user_clk),
        .D(verify_r),
        .Q(\verify_watchdog_r_reg[14]_srl15_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \verify_watchdog_r_reg[14]_srl15_i_1 
       (.I0(\bonding_watchdog_r_reg[14]_srl15_i_2_n_0 ),
        .I1(verify_r),
        .O(\verify_watchdog_r_reg[14]_srl15_i_1_n_0 ));
  FDRE \verify_watchdog_r_reg[15] 
       (.C(user_clk),
        .CE(\verify_watchdog_r_reg[14]_srl15_i_1_n_0 ),
        .D(\verify_watchdog_r_reg[14]_srl15_n_0 ),
        .Q(\verify_watchdog_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE wait_for_lane_up_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(wait_for_lane_up_r0),
        .Q(wait_for_lane_up_r),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5
   (bucket_full_r,
    D,
    user_clk_0,
    begin_r0,
    user_clk,
    hard_err_flop_r_reg_0,
    hard_err_flop_r0,
    SR,
    \soft_err_r_reg[0]_0 ,
    enable_err_detect_i);
  output bucket_full_r;
  output [0:0]D;
  output user_clk_0;
  output begin_r0;
  input user_clk;
  input hard_err_flop_r_reg_0;
  input hard_err_flop_r0;
  input [0:0]SR;
  input [1:0]\soft_err_r_reg[0]_0 ;
  input enable_err_detect_i;

  wire [0:0]D;
  wire [0:0]SR;
  wire begin_r0;
  wire bucket_full_r;
  wire bucket_full_r_i_1__2_n_0;
  wire [0:1]count_r;
  wire \count_r[0]_i_1__2_n_0 ;
  wire \count_r[1]_i_1__2_n_0 ;
  wire enable_err_detect_i;
  wire \good_count_r[0]_i_1__2_n_0 ;
  wire \good_count_r[1]_i_1__2_n_0 ;
  wire \good_count_r_reg_n_0_[1] ;
  wire hard_err_flop_r0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire p_0_in6_in;
  wire soft_err_flop_r0;
  wire [1:1]soft_err_r;
  wire [1:0]\soft_err_r_reg[0]_0 ;
  wire \soft_err_r_reg_n_0_[1] ;
  wire user_clk;
  wire user_clk_0;

  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_reset_i),
        .Q(D),
        .R(hard_err_flop_r_reg_0));
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_3_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 " *) 
  SRL16E SOFT_ERR_Buffer_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(soft_err_flop_r0),
        .Q(user_clk_0));
  LUT2 #(
    .INIT(4'hE)) 
    SOFT_ERR_Buffer_reg_srl2_i_1__2
       (.I0(soft_err_r),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .O(soft_err_flop_r0));
  LUT2 #(
    .INIT(4'hE)) 
    align_r_i_1__2
       (.I0(hard_err_reset_i),
        .I1(SR),
        .O(begin_r0));
  LUT2 #(
    .INIT(4'h8)) 
    bucket_full_r_i_1__2
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .O(bucket_full_r_i_1__2_n_0));
  FDRE bucket_full_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(bucket_full_r_i_1__2_n_0),
        .Q(bucket_full_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFEECE8CFFEEEE8C)) 
    \count_r[0]_i_1__2 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hEEDDAD4AEEDDDD4A)) 
    \count_r[1]_i_1__2 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[1]_i_1__2_n_0 ));
  FDRE \count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[0]_i_1__2_n_0 ),
        .Q(count_r[0]),
        .R(hard_err_flop_r_reg_0));
  FDRE \count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[1]_i_1__2_n_0 ),
        .Q(count_r[1]),
        .R(hard_err_flop_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \good_count_r[0]_i_1__2 
       (.I0(p_0_in6_in),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT4 #(
    .INIT(16'h32FF)) 
    \good_count_r[1]_i_1__2 
       (.I0(\good_count_r_reg_n_0_[1] ),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[1]_i_1__2_n_0 ));
  FDRE \good_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[0]_i_1__2_n_0 ),
        .Q(p_0_in6_in),
        .R(1'b0));
  FDRE \good_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[1]_i_1__2_n_0 ),
        .Q(\good_count_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r0),
        .Q(hard_err_reset_i),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [1]),
        .Q(soft_err_r),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [0]),
        .Q(\soft_err_r_reg_n_0_[1] ),
        .R(hard_err_flop_r_reg_0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5" *) 
module aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_12
   (bucket_full_r,
    D,
    user_clk_0,
    begin_r0,
    user_clk,
    hard_err_flop_r_reg_0,
    hard_err_flop_r0,
    SR,
    \soft_err_r_reg[0]_0 ,
    enable_err_detect_i);
  output bucket_full_r;
  output [0:0]D;
  output user_clk_0;
  output begin_r0;
  input user_clk;
  input hard_err_flop_r_reg_0;
  input hard_err_flop_r0;
  input [0:0]SR;
  input [1:0]\soft_err_r_reg[0]_0 ;
  input enable_err_detect_i;

  wire [0:0]D;
  wire [0:0]SR;
  wire begin_r0;
  wire bucket_full_r;
  wire bucket_full_r_i_1__0_n_0;
  wire [0:1]count_r;
  wire \count_r[0]_i_1__0_n_0 ;
  wire \count_r[1]_i_1__0_n_0 ;
  wire enable_err_detect_i;
  wire \good_count_r[0]_i_1__0_n_0 ;
  wire \good_count_r[1]_i_1__0_n_0 ;
  wire \good_count_r_reg_n_0_[1] ;
  wire hard_err_flop_r0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire p_0_in6_in;
  wire soft_err_flop_r0;
  wire [1:1]soft_err_r;
  wire [1:0]\soft_err_r_reg[0]_0 ;
  wire \soft_err_r_reg_n_0_[1] ;
  wire user_clk;
  wire user_clk_0;

  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_reset_i),
        .Q(D),
        .R(hard_err_flop_r_reg_0));
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_1_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 " *) 
  SRL16E SOFT_ERR_Buffer_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(soft_err_flop_r0),
        .Q(user_clk_0));
  LUT2 #(
    .INIT(4'hE)) 
    SOFT_ERR_Buffer_reg_srl2_i_1__0
       (.I0(soft_err_r),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .O(soft_err_flop_r0));
  LUT2 #(
    .INIT(4'hE)) 
    align_r_i_1__0
       (.I0(hard_err_reset_i),
        .I1(SR),
        .O(begin_r0));
  LUT2 #(
    .INIT(4'h8)) 
    bucket_full_r_i_1__0
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .O(bucket_full_r_i_1__0_n_0));
  FDRE bucket_full_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(bucket_full_r_i_1__0_n_0),
        .Q(bucket_full_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFEECE8CFFEEEE8C)) 
    \count_r[0]_i_1__0 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hEEDDAD4AEEDDDD4A)) 
    \count_r[1]_i_1__0 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[1]_i_1__0_n_0 ));
  FDRE \count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[0]_i_1__0_n_0 ),
        .Q(count_r[0]),
        .R(hard_err_flop_r_reg_0));
  FDRE \count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[1]_i_1__0_n_0 ),
        .Q(count_r[1]),
        .R(hard_err_flop_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \good_count_r[0]_i_1__0 
       (.I0(p_0_in6_in),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'h32FF)) 
    \good_count_r[1]_i_1__0 
       (.I0(\good_count_r_reg_n_0_[1] ),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[1]_i_1__0_n_0 ));
  FDRE \good_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[0]_i_1__0_n_0 ),
        .Q(p_0_in6_in),
        .R(1'b0));
  FDRE \good_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[1]_i_1__0_n_0 ),
        .Q(\good_count_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r0),
        .Q(hard_err_reset_i),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [1]),
        .Q(soft_err_r),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [0]),
        .Q(\soft_err_r_reg_n_0_[1] ),
        .R(hard_err_flop_r_reg_0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5" *) 
module aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_17
   (bucket_full_r,
    D,
    user_clk_0,
    begin_r0,
    user_clk,
    hard_err_flop_r_reg_0,
    hard_err_flop_r0,
    SR,
    \soft_err_r_reg[0]_0 ,
    enable_err_detect_i);
  output bucket_full_r;
  output [0:0]D;
  output user_clk_0;
  output begin_r0;
  input user_clk;
  input hard_err_flop_r_reg_0;
  input hard_err_flop_r0;
  input [0:0]SR;
  input [1:0]\soft_err_r_reg[0]_0 ;
  input enable_err_detect_i;

  wire [0:0]D;
  wire [0:0]SR;
  wire begin_r0;
  wire bucket_full_r;
  wire bucket_full_r_i_1_n_0;
  wire [0:1]count_r;
  wire \count_r[0]_i_1_n_0 ;
  wire \count_r[1]_i_1_n_0 ;
  wire enable_err_detect_i;
  wire \good_count_r[0]_i_1_n_0 ;
  wire \good_count_r[1]_i_1_n_0 ;
  wire \good_count_r_reg_n_0_[1] ;
  wire hard_err_flop_r0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire p_0_in6_in;
  wire soft_err_flop_r0;
  wire [1:1]soft_err_r;
  wire [1:0]\soft_err_r_reg[0]_0 ;
  wire \soft_err_r_reg_n_0_[1] ;
  wire user_clk;
  wire user_clk_0;

  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_reset_i),
        .Q(D),
        .R(hard_err_flop_r_reg_0));
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_0_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 " *) 
  SRL16E SOFT_ERR_Buffer_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(soft_err_flop_r0),
        .Q(user_clk_0));
  LUT2 #(
    .INIT(4'hE)) 
    SOFT_ERR_Buffer_reg_srl2_i_1
       (.I0(soft_err_r),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .O(soft_err_flop_r0));
  LUT2 #(
    .INIT(4'hE)) 
    align_r_i_1
       (.I0(hard_err_reset_i),
        .I1(SR),
        .O(begin_r0));
  LUT2 #(
    .INIT(4'h8)) 
    bucket_full_r_i_1
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .O(bucket_full_r_i_1_n_0));
  FDRE bucket_full_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(bucket_full_r_i_1_n_0),
        .Q(bucket_full_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFEECE8CFFEEEE8C)) 
    \count_r[0]_i_1 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEDDAD4AEEDDDD4A)) 
    \count_r[1]_i_1 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[1]_i_1_n_0 ));
  FDRE \count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[0]_i_1_n_0 ),
        .Q(count_r[0]),
        .R(hard_err_flop_r_reg_0));
  FDRE \count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[1]_i_1_n_0 ),
        .Q(count_r[1]),
        .R(hard_err_flop_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \good_count_r[0]_i_1 
       (.I0(p_0_in6_in),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h32FF)) 
    \good_count_r[1]_i_1 
       (.I0(\good_count_r_reg_n_0_[1] ),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[1]_i_1_n_0 ));
  FDRE \good_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[0]_i_1_n_0 ),
        .Q(p_0_in6_in),
        .R(1'b0));
  FDRE \good_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[1]_i_1_n_0 ),
        .Q(\good_count_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r0),
        .Q(hard_err_reset_i),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [1]),
        .Q(soft_err_r),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [0]),
        .Q(\soft_err_r_reg_n_0_[1] ),
        .R(hard_err_flop_r_reg_0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5" *) 
module aurora_rx_4l_64b_RX_ERR_DETECT_SIMPLEX_V5_7
   (bucket_full_r,
    D,
    user_clk_0,
    begin_r0,
    user_clk,
    hard_err_flop_r_reg_0,
    hard_err_flop_r0,
    SR,
    \soft_err_r_reg[0]_0 ,
    enable_err_detect_i);
  output bucket_full_r;
  output [0:0]D;
  output user_clk_0;
  output begin_r0;
  input user_clk;
  input hard_err_flop_r_reg_0;
  input hard_err_flop_r0;
  input [0:0]SR;
  input [1:0]\soft_err_r_reg[0]_0 ;
  input enable_err_detect_i;

  wire [0:0]D;
  wire [0:0]SR;
  wire begin_r0;
  wire bucket_full_r;
  wire bucket_full_r_i_1__1_n_0;
  wire [0:1]count_r;
  wire \count_r[0]_i_1__1_n_0 ;
  wire \count_r[1]_i_1__1_n_0 ;
  wire enable_err_detect_i;
  wire \good_count_r[0]_i_1__1_n_0 ;
  wire \good_count_r[1]_i_1__1_n_0 ;
  wire \good_count_r_reg_n_0_[1] ;
  wire hard_err_flop_r0;
  wire hard_err_flop_r_reg_0;
  wire hard_err_reset_i;
  wire p_0_in6_in;
  wire soft_err_flop_r0;
  wire [1:1]soft_err_r;
  wire [1:0]\soft_err_r_reg[0]_0 ;
  wire \soft_err_r_reg_n_0_[1] ;
  wire user_clk;
  wire user_clk_0;

  FDRE HARD_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_reset_i),
        .Q(D),
        .R(hard_err_flop_r_reg_0));
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_2_i/rx_err_detect_simplex_gtp_i/SOFT_ERR_Buffer_reg_srl2 " *) 
  SRL16E SOFT_ERR_Buffer_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(soft_err_flop_r0),
        .Q(user_clk_0));
  LUT2 #(
    .INIT(4'hE)) 
    SOFT_ERR_Buffer_reg_srl2_i_1__1
       (.I0(soft_err_r),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .O(soft_err_flop_r0));
  LUT2 #(
    .INIT(4'hE)) 
    align_r_i_1__1
       (.I0(hard_err_reset_i),
        .I1(SR),
        .O(begin_r0));
  LUT2 #(
    .INIT(4'h8)) 
    bucket_full_r_i_1__1
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .O(bucket_full_r_i_1__1_n_0));
  FDRE bucket_full_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(bucket_full_r_i_1__1_n_0),
        .Q(bucket_full_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFEECE8CFFEEEE8C)) 
    \count_r[0]_i_1__1 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hEEDDAD4AEEDDDD4A)) 
    \count_r[1]_i_1__1 
       (.I0(count_r[1]),
        .I1(count_r[0]),
        .I2(p_0_in6_in),
        .I3(\soft_err_r_reg_n_0_[1] ),
        .I4(soft_err_r),
        .I5(\good_count_r_reg_n_0_[1] ),
        .O(\count_r[1]_i_1__1_n_0 ));
  FDRE \count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[0]_i_1__1_n_0 ),
        .Q(count_r[0]),
        .R(hard_err_flop_r_reg_0));
  FDRE \count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\count_r[1]_i_1__1_n_0 ),
        .Q(count_r[1]),
        .R(hard_err_flop_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \good_count_r[0]_i_1__1 
       (.I0(p_0_in6_in),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'h32FF)) 
    \good_count_r[1]_i_1__1 
       (.I0(\good_count_r_reg_n_0_[1] ),
        .I1(\soft_err_r_reg_n_0_[1] ),
        .I2(soft_err_r),
        .I3(enable_err_detect_i),
        .O(\good_count_r[1]_i_1__1_n_0 ));
  FDRE \good_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[0]_i_1__1_n_0 ),
        .Q(p_0_in6_in),
        .R(1'b0));
  FDRE \good_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\good_count_r[1]_i_1__1_n_0 ),
        .Q(\good_count_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE hard_err_flop_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(hard_err_flop_r0),
        .Q(hard_err_reset_i),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [1]),
        .Q(soft_err_r),
        .R(hard_err_flop_r_reg_0));
  FDRE \soft_err_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\soft_err_r_reg[0]_0 [0]),
        .Q(\soft_err_r_reg_n_0_[1] ),
        .R(hard_err_flop_r_reg_0));
endmodule

module aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX
   (SR,
    reset_lanes_flop_1_i,
    reset_lanes_flop_2_i,
    reset_lanes_flop_3_i,
    en_chan_sync_i,
    CHANNEL_UP_Buffer_reg,
    start_rx_i,
    gtrxreset_i,
    SOFT_ERR,
    RX_HARD_ERR,
    D,
    START_RX_Buffer_reg,
    RESET,
    user_clk,
    GOT_V,
    all_lanes_v_r_reg,
    all_lanes_v_r_reg_0,
    all_lanes_v_r_reg_1,
    bad_as_r0,
    good_as_r0,
    START_RX_Buffer_reg_0,
    CHBONDDONE_OUT_LANE3,
    CHBONDDONE_OUT,
    CHBONDDONE_OUT_LANE2,
    CHBONDDONE_OUT_LANE1,
    \soft_err_r_reg[0] ,
    \soft_err_r_reg[1] ,
    \soft_err_r_reg[2] ,
    \soft_err_r_reg[3] ,
    RX_SUF,
    POWER_DOWN,
    Q,
    \hard_err_r_reg[0] ,
    RX_LANE_UP);
  output [0:0]SR;
  output [0:0]reset_lanes_flop_1_i;
  output [0:0]reset_lanes_flop_2_i;
  output [0:0]reset_lanes_flop_3_i;
  output en_chan_sync_i;
  output CHANNEL_UP_Buffer_reg;
  output start_rx_i;
  output gtrxreset_i;
  output SOFT_ERR;
  output RX_HARD_ERR;
  output [3:0]D;
  output START_RX_Buffer_reg;
  output RESET;
  input user_clk;
  input GOT_V;
  input all_lanes_v_r_reg;
  input all_lanes_v_r_reg_0;
  input all_lanes_v_r_reg_1;
  input bad_as_r0;
  input good_as_r0;
  input START_RX_Buffer_reg_0;
  input CHBONDDONE_OUT_LANE3;
  input CHBONDDONE_OUT;
  input CHBONDDONE_OUT_LANE2;
  input CHBONDDONE_OUT_LANE1;
  input \soft_err_r_reg[0] ;
  input \soft_err_r_reg[1] ;
  input \soft_err_r_reg[2] ;
  input \soft_err_r_reg[3] ;
  input RX_SUF;
  input POWER_DOWN;
  input [3:0]Q;
  input [3:0]\hard_err_r_reg[0] ;
  input [0:3]RX_LANE_UP;

  wire CHANNEL_UP_Buffer_reg;
  wire CHBONDDONE_OUT;
  wire CHBONDDONE_OUT_LANE1;
  wire CHBONDDONE_OUT_LANE2;
  wire CHBONDDONE_OUT_LANE3;
  wire [3:0]D;
  wire GOT_V;
  wire POWER_DOWN;
  wire [3:0]Q;
  wire RESET;
  wire RX_HARD_ERR;
  wire [0:3]RX_LANE_UP;
  wire RX_SUF;
  wire SOFT_ERR;
  wire [0:0]SR;
  wire START_RX_Buffer_reg;
  wire START_RX_Buffer_reg_0;
  wire all_lanes_v_r_reg;
  wire all_lanes_v_r_reg_0;
  wire all_lanes_v_r_reg_1;
  wire bad_as_r0;
  wire en_chan_sync_i;
  wire good_as_r0;
  wire gtrxreset_i;
  wire [3:0]\hard_err_r_reg[0] ;
  wire reset_channel_i;
  wire [0:0]reset_lanes_flop_1_i;
  wire [0:0]reset_lanes_flop_2_i;
  wire [0:0]reset_lanes_flop_3_i;
  wire \soft_err_r_reg[0] ;
  wire \soft_err_r_reg[1] ;
  wire \soft_err_r_reg[2] ;
  wire \soft_err_r_reg[3] ;
  wire start_rx_i;
  wire user_clk;
  wire wait_for_lane_up_r0;

  aurora_rx_4l_64b_RX_CHANNEL_ERR_DETECT_SIMPLEX rx_channel_err_detect_simplex_i
       (.POWER_DOWN(POWER_DOWN),
        .RX_HARD_ERR(RX_HARD_ERR),
        .RX_LANE_UP(RX_LANE_UP),
        .SOFT_ERR(SOFT_ERR),
        .\hard_err_r_reg[0]_0 (\hard_err_r_reg[0] ),
        .reset_channel_i(reset_channel_i),
        .\soft_err_r_reg[0]_0 (\soft_err_r_reg[0] ),
        .\soft_err_r_reg[1]_0 (\soft_err_r_reg[1] ),
        .\soft_err_r_reg[2]_0 (\soft_err_r_reg[2] ),
        .\soft_err_r_reg[3]_0 (\soft_err_r_reg[3] ),
        .user_clk(user_clk),
        .wait_for_lane_up_r0(wait_for_lane_up_r0),
        .wait_for_lane_up_r_reg(START_RX_Buffer_reg_0));
  aurora_rx_4l_64b_RX_CHANNEL_INIT_SM_SIMPLEX rx_channel_init_sm_simplex_i
       (.CHANNEL_UP_Buffer_reg_0(CHANNEL_UP_Buffer_reg),
        .CHBONDDONE_OUT(CHBONDDONE_OUT),
        .CHBONDDONE_OUT_LANE1(CHBONDDONE_OUT_LANE1),
        .CHBONDDONE_OUT_LANE2(CHBONDDONE_OUT_LANE2),
        .CHBONDDONE_OUT_LANE3(CHBONDDONE_OUT_LANE3),
        .D(D),
        .GOT_V(GOT_V),
        .Q(Q),
        .RESET(RESET),
        .RX_SUF(RX_SUF),
        .SR(SR),
        .START_RX_Buffer_reg_0(START_RX_Buffer_reg),
        .START_RX_Buffer_reg_1(START_RX_Buffer_reg_0),
        .all_lanes_v_r_reg_0(all_lanes_v_r_reg),
        .all_lanes_v_r_reg_1(all_lanes_v_r_reg_0),
        .all_lanes_v_r_reg_2(all_lanes_v_r_reg_1),
        .bad_as_r0(bad_as_r0),
        .en_chan_sync_i(en_chan_sync_i),
        .good_as_r0(good_as_r0),
        .gtrxreset_i(gtrxreset_i),
        .reset_channel_i(reset_channel_i),
        .reset_lanes_flop_1_i_0(reset_lanes_flop_1_i),
        .reset_lanes_flop_2_i_0(reset_lanes_flop_2_i),
        .reset_lanes_flop_3_i_0(reset_lanes_flop_3_i),
        .start_rx_i(start_rx_i),
        .user_clk(user_clk),
        .wait_for_lane_up_r0(wait_for_lane_up_r0));
endmodule

module aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX
   (RX_LANE_UP,
    align_r_reg_0,
    comma_over_two_cycles_r,
    rst_r_reg_0,
    enable_err_detect_i,
    rx_polarity_i_3,
    gthe2_i,
    ENABLE_ERR_DETECT_Buffer_reg_0,
    SR,
    user_clk,
    begin_r0,
    begin_r_reg_0,
    RX_NEG_Buffer,
    reset_count_r_reg_0,
    rx_sp_i,
    \counter2_r_reg[15]_0 ,
    \RX_CHAR_IS_COMMA_R_reg[1]_0 ,
    left_aligned_r_reg,
    left_aligned_r_reg_0);
  output [0:0]RX_LANE_UP;
  output align_r_reg_0;
  output comma_over_two_cycles_r;
  output rst_r_reg_0;
  output enable_err_detect_i;
  output rx_polarity_i_3;
  output gthe2_i;
  output ENABLE_ERR_DETECT_Buffer_reg_0;
  input [0:0]SR;
  input user_clk;
  input begin_r0;
  input begin_r_reg_0;
  input RX_NEG_Buffer;
  input reset_count_r_reg_0;
  input rx_sp_i;
  input \counter2_r_reg[15]_0 ;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  input left_aligned_r_reg;
  input left_aligned_r_reg_0;

  wire D;
  wire ENABLE_ERR_DETECT_Buffer_reg_0;
  wire [1:0]RX_CHAR_IS_COMMA_R;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [0:0]SR;
  wire align_r_reg_0;
  wire begin_r;
  wire begin_r0;
  wire begin_r_reg_0;
  wire comma_over_two_cycles_r;
  wire comma_over_two_cycles_r0;
  wire counter1_r0;
  wire \counter1_r[0]_i_4__2_n_0 ;
  wire \counter1_r[2]_i_1__2_n_0 ;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire \counter1_r_reg_n_0_[5] ;
  wire \counter1_r_reg_n_0_[6] ;
  wire \counter1_r_reg_n_0_[7] ;
  wire counter2_r0;
  wire \counter2_r_reg[14]_srl15_n_0 ;
  wire \counter2_r_reg[15]_0 ;
  wire \counter2_r_reg_n_0_[15] ;
  wire enable_err_detect_i;
  wire gthe2_i;
  wire inc_count_c;
  wire inc_count_c1;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire next_align_c;
  wire next_begin_c;
  wire next_polarity_c;
  wire next_ready_c;
  wire next_realign_c;
  wire next_rst_c;
  wire [7:0]p_0_in;
  wire polarity_r;
  wire prev_char_was_comma_r;
  wire realign_r;
  wire reset_count_r;
  wire reset_count_r0;
  wire reset_count_r_reg_0;
  wire rst_r_reg_0;
  wire rx_polarity_i_3;
  wire rx_polarity_r_i_1__2_n_0;
  wire rx_sp_i;
  wire std_bool;
  wire std_bool0_in;
  wire std_bool0_in3_in;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(enable_err_detect_i),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .Q(RX_CHAR_IS_COMMA_R[0]),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [1]),
        .Q(RX_CHAR_IS_COMMA_R[1]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_2__2
       (.I0(std_bool0_in),
        .I1(align_r_reg_0),
        .I2(std_bool0_in3_in),
        .I3(rst_r_reg_0),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r_reg_0),
        .R(begin_r0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    begin_r_i_1__2
       (.I0(realign_r),
        .I1(begin_r_reg_0),
        .I2(D),
        .I3(\counter2_r_reg_n_0_[15] ),
        .I4(polarity_r),
        .I5(RX_NEG_Buffer),
        .O(next_begin_c));
  FDSE begin_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_begin_c),
        .Q(begin_r),
        .S(begin_r0));
  LUT4 #(
    .INIT(16'h57FD)) 
    comma_over_two_cycles_r_i_1__2
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .I2(RX_CHAR_IS_COMMA_R[1]),
        .I3(prev_char_was_comma_r),
        .O(comma_over_two_cycles_r0));
  FDRE comma_over_two_cycles_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(comma_over_two_cycles_r0),
        .Q(comma_over_two_cycles_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \counter1_r[0]_i_1__2 
       (.I0(D),
        .I1(reset_count_r),
        .O(counter1_r0));
  LUT3 #(
    .INIT(8'hFD)) 
    \counter1_r[0]_i_2__2 
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[1]),
        .I2(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[0]_i_3__2 
       (.I0(std_bool0_in),
        .I1(std_bool),
        .I2(std_bool0_in3_in),
        .I3(\counter1_r[0]_i_4__2_n_0 ),
        .I4(\counter1_r_reg_n_0_[3] ),
        .I5(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \counter1_r[0]_i_4__2 
       (.I0(\counter1_r_reg_n_0_[5] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[7] ),
        .O(\counter1_r[0]_i_4__2_n_0 ));
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[1]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[1] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r[0]_i_4__2_n_0 ),
        .I3(std_bool0_in3_in),
        .I4(std_bool),
        .O(p_0_in[6]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[2]_i_1__2 
       (.I0(std_bool),
        .I1(std_bool0_in3_in),
        .I2(\counter1_r_reg_n_0_[7] ),
        .I3(\counter1_r_reg_n_0_[6] ),
        .I4(\counter1_r_reg_n_0_[5] ),
        .I5(\counter1_r_reg_n_0_[3] ),
        .O(\counter1_r[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[3]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[5] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[7] ),
        .I4(std_bool0_in3_in),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \counter1_r[4]_i_1__2 
       (.I0(std_bool0_in3_in),
        .I1(\counter1_r_reg_n_0_[7] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[5]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[6]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[7]_i_1__2 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[7]),
        .Q(std_bool0_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[6]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(\counter1_r[2]_i_1__2_n_0 ),
        .Q(std_bool),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[4]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[4] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[3]),
        .Q(std_bool0_in3_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[5] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[5] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[6] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[6] ),
        .R(counter1_r0));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[7] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[7] ),
        .S(counter1_r0));
  (* srl_bus_name = "U0/\rx_aurora_lane_simplex_v5_3_i/rx_lane_init_sm_simplex_i/counter2_r_reg " *) 
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_3_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 " *) 
  SRL16E \counter2_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(counter2_r0),
        .CLK(user_clk),
        .D(D),
        .Q(\counter2_r_reg[14]_srl15_n_0 ));
  LUT3 #(
    .INIT(8'hD5)) 
    \counter2_r_reg[14]_srl15_i_1__2 
       (.I0(D),
        .I1(rx_sp_i),
        .I2(\counter2_r_reg[15]_0 ),
        .O(counter2_r0));
  FDRE \counter2_r_reg[15] 
       (.C(user_clk),
        .CE(counter2_r0),
        .D(\counter2_r_reg[14]_srl15_n_0 ),
        .Q(\counter2_r_reg_n_0_[15] ),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(RX_LANE_UP),
        .R(SR));
  LUT5 #(
    .INIT(32'hFFAB00A8)) 
    left_aligned_r_i_1__2
       (.I0(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .I1(align_r_reg_0),
        .I2(D),
        .I3(left_aligned_r_reg),
        .I4(left_aligned_r_reg_0),
        .O(gthe2_i));
  LUT3 #(
    .INIT(8'h08)) 
    polarity_r_i_1__2
       (.I0(std_bool),
        .I1(realign_r),
        .I2(begin_r_reg_0),
        .O(next_polarity_c));
  FDRE polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_polarity_c),
        .Q(polarity_r),
        .R(begin_r0));
  LUT2 #(
    .INIT(4'hE)) 
    prev_char_was_comma_r_i_1__2
       (.I0(RX_CHAR_IS_COMMA_R[1]),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c1));
  FDRE prev_char_was_comma_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(inc_count_c1),
        .Q(prev_char_was_comma_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    ready_r_i_1__2
       (.I0(\counter2_r_reg_n_0_[15] ),
        .I1(D),
        .I2(RX_NEG_Buffer),
        .I3(polarity_r),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFF040404)) 
    realign_r_i_1__2
       (.I0(begin_r_reg_0),
        .I1(realign_r),
        .I2(std_bool),
        .I3(std_bool0_in),
        .I4(align_r_reg_0),
        .O(next_realign_c));
  FDRE realign_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_realign_c),
        .Q(realign_r),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFFFF04F5)) 
    reset_count_r_i_1__2
       (.I0(reset_count_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .I3(rst_r_reg_0),
        .I4(SR),
        .O(reset_count_r0));
  FDRE reset_count_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_count_r0),
        .Q(reset_count_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF2)) 
    rst_r_i_1__2
       (.I0(rst_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .O(next_rst_c));
  FDRE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(rst_r_reg_0),
        .R(begin_r0));
  LUT3 #(
    .INIT(8'h78)) 
    rx_polarity_r_i_1__2
       (.I0(RX_NEG_Buffer),
        .I1(polarity_r),
        .I2(rx_polarity_i_3),
        .O(rx_polarity_r_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rx_polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_polarity_r_i_1__2_n_0),
        .Q(rx_polarity_i_3),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \soft_err_r[0]_i_1__2 
       (.I0(enable_err_detect_i),
        .O(ENABLE_ERR_DETECT_Buffer_reg_0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX" *) 
module aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_13
   (RX_LANE_UP,
    align_r_reg_0,
    comma_over_two_cycles_r,
    rst_r_reg_0,
    enable_err_detect_i,
    rx_polarity_i_1,
    gthe2_i,
    ENABLE_ERR_DETECT_Buffer_reg_0,
    SR,
    user_clk,
    begin_r0,
    begin_r_reg_0,
    RX_NEG_Buffer,
    reset_count_r_reg_0,
    rx_sp_i,
    \counter2_r_reg[15]_0 ,
    \RX_CHAR_IS_COMMA_R_reg[1]_0 ,
    left_aligned_r_reg,
    left_aligned_r_reg_0);
  output [0:0]RX_LANE_UP;
  output align_r_reg_0;
  output comma_over_two_cycles_r;
  output rst_r_reg_0;
  output enable_err_detect_i;
  output rx_polarity_i_1;
  output gthe2_i;
  output ENABLE_ERR_DETECT_Buffer_reg_0;
  input [0:0]SR;
  input user_clk;
  input begin_r0;
  input begin_r_reg_0;
  input RX_NEG_Buffer;
  input reset_count_r_reg_0;
  input rx_sp_i;
  input \counter2_r_reg[15]_0 ;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  input left_aligned_r_reg;
  input left_aligned_r_reg_0;

  wire D;
  wire ENABLE_ERR_DETECT_Buffer_reg_0;
  wire [1:0]RX_CHAR_IS_COMMA_R;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [0:0]SR;
  wire align_r_reg_0;
  wire begin_r;
  wire begin_r0;
  wire begin_r_reg_0;
  wire comma_over_two_cycles_r;
  wire comma_over_two_cycles_r0;
  wire counter1_r0;
  wire \counter1_r[0]_i_4__0_n_0 ;
  wire \counter1_r[2]_i_1__0_n_0 ;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire \counter1_r_reg_n_0_[5] ;
  wire \counter1_r_reg_n_0_[6] ;
  wire \counter1_r_reg_n_0_[7] ;
  wire counter2_r0;
  wire \counter2_r_reg[14]_srl15_n_0 ;
  wire \counter2_r_reg[15]_0 ;
  wire \counter2_r_reg_n_0_[15] ;
  wire enable_err_detect_i;
  wire gthe2_i;
  wire inc_count_c;
  wire inc_count_c1;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire next_align_c;
  wire next_begin_c;
  wire next_polarity_c;
  wire next_ready_c;
  wire next_realign_c;
  wire next_rst_c;
  wire [7:0]p_0_in;
  wire polarity_r;
  wire prev_char_was_comma_r;
  wire realign_r;
  wire reset_count_r;
  wire reset_count_r0;
  wire reset_count_r_reg_0;
  wire rst_r_reg_0;
  wire rx_polarity_i_1;
  wire rx_polarity_r_i_1__0_n_0;
  wire rx_sp_i;
  wire std_bool;
  wire std_bool0_in;
  wire std_bool0_in3_in;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(enable_err_detect_i),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .Q(RX_CHAR_IS_COMMA_R[0]),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [1]),
        .Q(RX_CHAR_IS_COMMA_R[1]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_2__0
       (.I0(std_bool0_in),
        .I1(align_r_reg_0),
        .I2(std_bool0_in3_in),
        .I3(rst_r_reg_0),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r_reg_0),
        .R(begin_r0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    begin_r_i_1__0
       (.I0(realign_r),
        .I1(begin_r_reg_0),
        .I2(D),
        .I3(\counter2_r_reg_n_0_[15] ),
        .I4(polarity_r),
        .I5(RX_NEG_Buffer),
        .O(next_begin_c));
  FDSE begin_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_begin_c),
        .Q(begin_r),
        .S(begin_r0));
  LUT4 #(
    .INIT(16'h57FD)) 
    comma_over_two_cycles_r_i_1__0
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .I2(RX_CHAR_IS_COMMA_R[1]),
        .I3(prev_char_was_comma_r),
        .O(comma_over_two_cycles_r0));
  FDRE comma_over_two_cycles_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(comma_over_two_cycles_r0),
        .Q(comma_over_two_cycles_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \counter1_r[0]_i_1__0 
       (.I0(D),
        .I1(reset_count_r),
        .O(counter1_r0));
  LUT3 #(
    .INIT(8'hFD)) 
    \counter1_r[0]_i_2__0 
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[1]),
        .I2(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[0]_i_3__0 
       (.I0(std_bool0_in),
        .I1(std_bool),
        .I2(std_bool0_in3_in),
        .I3(\counter1_r[0]_i_4__0_n_0 ),
        .I4(\counter1_r_reg_n_0_[3] ),
        .I5(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \counter1_r[0]_i_4__0 
       (.I0(\counter1_r_reg_n_0_[5] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[7] ),
        .O(\counter1_r[0]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[1]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[1] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r[0]_i_4__0_n_0 ),
        .I3(std_bool0_in3_in),
        .I4(std_bool),
        .O(p_0_in[6]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[2]_i_1__0 
       (.I0(std_bool),
        .I1(std_bool0_in3_in),
        .I2(\counter1_r_reg_n_0_[7] ),
        .I3(\counter1_r_reg_n_0_[6] ),
        .I4(\counter1_r_reg_n_0_[5] ),
        .I5(\counter1_r_reg_n_0_[3] ),
        .O(\counter1_r[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[3]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[5] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[7] ),
        .I4(std_bool0_in3_in),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \counter1_r[4]_i_1__0 
       (.I0(std_bool0_in3_in),
        .I1(\counter1_r_reg_n_0_[7] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[5]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[6]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[7]_i_1__0 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[7]),
        .Q(std_bool0_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[6]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(\counter1_r[2]_i_1__0_n_0 ),
        .Q(std_bool),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[4]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[4] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[3]),
        .Q(std_bool0_in3_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[5] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[5] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[6] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[6] ),
        .R(counter1_r0));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[7] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[7] ),
        .S(counter1_r0));
  (* srl_bus_name = "U0/\rx_aurora_lane_simplex_v5_1_i/rx_lane_init_sm_simplex_i/counter2_r_reg " *) 
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_1_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 " *) 
  SRL16E \counter2_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(counter2_r0),
        .CLK(user_clk),
        .D(D),
        .Q(\counter2_r_reg[14]_srl15_n_0 ));
  LUT3 #(
    .INIT(8'hD5)) 
    \counter2_r_reg[14]_srl15_i_1__0 
       (.I0(D),
        .I1(rx_sp_i),
        .I2(\counter2_r_reg[15]_0 ),
        .O(counter2_r0));
  FDRE \counter2_r_reg[15] 
       (.C(user_clk),
        .CE(counter2_r0),
        .D(\counter2_r_reg[14]_srl15_n_0 ),
        .Q(\counter2_r_reg_n_0_[15] ),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(RX_LANE_UP),
        .R(SR));
  LUT5 #(
    .INIT(32'hFFAB00A8)) 
    left_aligned_r_i_1__0
       (.I0(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .I1(align_r_reg_0),
        .I2(D),
        .I3(left_aligned_r_reg),
        .I4(left_aligned_r_reg_0),
        .O(gthe2_i));
  LUT3 #(
    .INIT(8'h08)) 
    polarity_r_i_1__0
       (.I0(std_bool),
        .I1(realign_r),
        .I2(begin_r_reg_0),
        .O(next_polarity_c));
  FDRE polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_polarity_c),
        .Q(polarity_r),
        .R(begin_r0));
  LUT2 #(
    .INIT(4'hE)) 
    prev_char_was_comma_r_i_1__0
       (.I0(RX_CHAR_IS_COMMA_R[1]),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c1));
  FDRE prev_char_was_comma_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(inc_count_c1),
        .Q(prev_char_was_comma_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    ready_r_i_1__0
       (.I0(\counter2_r_reg_n_0_[15] ),
        .I1(D),
        .I2(RX_NEG_Buffer),
        .I3(polarity_r),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFF040404)) 
    realign_r_i_1__0
       (.I0(begin_r_reg_0),
        .I1(realign_r),
        .I2(std_bool),
        .I3(std_bool0_in),
        .I4(align_r_reg_0),
        .O(next_realign_c));
  FDRE realign_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_realign_c),
        .Q(realign_r),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFFFF04F5)) 
    reset_count_r_i_1__0
       (.I0(reset_count_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .I3(rst_r_reg_0),
        .I4(SR),
        .O(reset_count_r0));
  FDRE reset_count_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_count_r0),
        .Q(reset_count_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF2)) 
    rst_r_i_1__0
       (.I0(rst_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .O(next_rst_c));
  FDRE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(rst_r_reg_0),
        .R(begin_r0));
  LUT3 #(
    .INIT(8'h78)) 
    rx_polarity_r_i_1__0
       (.I0(RX_NEG_Buffer),
        .I1(polarity_r),
        .I2(rx_polarity_i_1),
        .O(rx_polarity_r_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rx_polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_polarity_r_i_1__0_n_0),
        .Q(rx_polarity_i_1),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \soft_err_r[0]_i_1__0 
       (.I0(enable_err_detect_i),
        .O(ENABLE_ERR_DETECT_Buffer_reg_0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX" *) 
module aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_18
   (RX_LANE_UP,
    align_r_reg_0,
    comma_over_two_cycles_r,
    rst_r_reg_0,
    enable_err_detect_i,
    rx_polarity_i_0,
    gthe2_i,
    ENABLE_ERR_DETECT_Buffer_reg_0,
    SR,
    user_clk,
    begin_r0,
    begin_r_reg_0,
    RX_NEG_Buffer,
    reset_count_r_reg_0,
    \counter2_r_reg[15]_0 ,
    rx_sp_i,
    \RX_CHAR_IS_COMMA_R_reg[1]_0 ,
    left_aligned_r_reg,
    left_aligned_r_reg_0);
  output [0:0]RX_LANE_UP;
  output align_r_reg_0;
  output comma_over_two_cycles_r;
  output rst_r_reg_0;
  output enable_err_detect_i;
  output rx_polarity_i_0;
  output gthe2_i;
  output ENABLE_ERR_DETECT_Buffer_reg_0;
  input [0:0]SR;
  input user_clk;
  input begin_r0;
  input begin_r_reg_0;
  input RX_NEG_Buffer;
  input reset_count_r_reg_0;
  input \counter2_r_reg[15]_0 ;
  input rx_sp_i;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  input left_aligned_r_reg;
  input left_aligned_r_reg_0;

  wire D;
  wire ENABLE_ERR_DETECT_Buffer_reg_0;
  wire [1:0]RX_CHAR_IS_COMMA_R;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [0:0]SR;
  wire align_r_reg_0;
  wire begin_r;
  wire begin_r0;
  wire begin_r_reg_0;
  wire comma_over_two_cycles_r;
  wire comma_over_two_cycles_r0;
  wire counter1_r0;
  wire \counter1_r[0]_i_4_n_0 ;
  wire \counter1_r[2]_i_1_n_0 ;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire \counter1_r_reg_n_0_[5] ;
  wire \counter1_r_reg_n_0_[6] ;
  wire \counter1_r_reg_n_0_[7] ;
  wire counter2_r0;
  wire \counter2_r_reg[14]_srl15_n_0 ;
  wire \counter2_r_reg[15]_0 ;
  wire \counter2_r_reg_n_0_[15] ;
  wire enable_err_detect_i;
  wire gthe2_i;
  wire inc_count_c;
  wire inc_count_c1;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire next_align_c;
  wire next_begin_c;
  wire next_polarity_c;
  wire next_ready_c;
  wire next_realign_c;
  wire next_rst_c;
  wire [7:0]p_0_in;
  wire polarity_r;
  wire prev_char_was_comma_r;
  wire realign_r;
  wire reset_count_r;
  wire reset_count_r0;
  wire reset_count_r_reg_0;
  wire rst_r_reg_0;
  wire rx_polarity_i_0;
  wire rx_polarity_r_i_1_n_0;
  wire rx_sp_i;
  wire std_bool;
  wire std_bool0_in;
  wire std_bool0_in3_in;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(enable_err_detect_i),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .Q(RX_CHAR_IS_COMMA_R[0]),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [1]),
        .Q(RX_CHAR_IS_COMMA_R[1]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_2
       (.I0(std_bool0_in),
        .I1(align_r_reg_0),
        .I2(std_bool0_in3_in),
        .I3(rst_r_reg_0),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r_reg_0),
        .R(begin_r0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    begin_r_i_1
       (.I0(realign_r),
        .I1(begin_r_reg_0),
        .I2(D),
        .I3(\counter2_r_reg_n_0_[15] ),
        .I4(polarity_r),
        .I5(RX_NEG_Buffer),
        .O(next_begin_c));
  FDSE begin_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_begin_c),
        .Q(begin_r),
        .S(begin_r0));
  LUT4 #(
    .INIT(16'h57FD)) 
    comma_over_two_cycles_r_i_1
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .I2(RX_CHAR_IS_COMMA_R[1]),
        .I3(prev_char_was_comma_r),
        .O(comma_over_two_cycles_r0));
  FDRE comma_over_two_cycles_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(comma_over_two_cycles_r0),
        .Q(comma_over_two_cycles_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \counter1_r[0]_i_1 
       (.I0(D),
        .I1(reset_count_r),
        .O(counter1_r0));
  LUT3 #(
    .INIT(8'hFD)) 
    \counter1_r[0]_i_2 
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[1]),
        .I2(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[0]_i_3 
       (.I0(std_bool0_in),
        .I1(std_bool),
        .I2(std_bool0_in3_in),
        .I3(\counter1_r[0]_i_4_n_0 ),
        .I4(\counter1_r_reg_n_0_[3] ),
        .I5(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \counter1_r[0]_i_4 
       (.I0(\counter1_r_reg_n_0_[5] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[7] ),
        .O(\counter1_r[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[1]_i_1 
       (.I0(\counter1_r_reg_n_0_[1] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r[0]_i_4_n_0 ),
        .I3(std_bool0_in3_in),
        .I4(std_bool),
        .O(p_0_in[6]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[2]_i_1 
       (.I0(std_bool),
        .I1(std_bool0_in3_in),
        .I2(\counter1_r_reg_n_0_[7] ),
        .I3(\counter1_r_reg_n_0_[6] ),
        .I4(\counter1_r_reg_n_0_[5] ),
        .I5(\counter1_r_reg_n_0_[3] ),
        .O(\counter1_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[3]_i_1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[5] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[7] ),
        .I4(std_bool0_in3_in),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \counter1_r[4]_i_1 
       (.I0(std_bool0_in3_in),
        .I1(\counter1_r_reg_n_0_[7] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[5]_i_1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[6]_i_1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[7]_i_1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[7]),
        .Q(std_bool0_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[6]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(\counter1_r[2]_i_1_n_0 ),
        .Q(std_bool),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[4]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[4] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[3]),
        .Q(std_bool0_in3_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[5] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[5] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[6] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[6] ),
        .R(counter1_r0));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[7] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[7] ),
        .S(counter1_r0));
  (* srl_bus_name = "U0/\rx_aurora_lane_simplex_v5_0_i/rx_lane_init_sm_simplex_i/counter2_r_reg " *) 
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_0_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 " *) 
  SRL16E \counter2_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(counter2_r0),
        .CLK(user_clk),
        .D(D),
        .Q(\counter2_r_reg[14]_srl15_n_0 ));
  LUT3 #(
    .INIT(8'hD5)) 
    \counter2_r_reg[14]_srl15_i_1 
       (.I0(D),
        .I1(\counter2_r_reg[15]_0 ),
        .I2(rx_sp_i),
        .O(counter2_r0));
  FDRE \counter2_r_reg[15] 
       (.C(user_clk),
        .CE(counter2_r0),
        .D(\counter2_r_reg[14]_srl15_n_0 ),
        .Q(\counter2_r_reg_n_0_[15] ),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(RX_LANE_UP),
        .R(SR));
  LUT5 #(
    .INIT(32'hFFAB00A8)) 
    left_aligned_r_i_1
       (.I0(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .I1(align_r_reg_0),
        .I2(D),
        .I3(left_aligned_r_reg),
        .I4(left_aligned_r_reg_0),
        .O(gthe2_i));
  LUT3 #(
    .INIT(8'h08)) 
    polarity_r_i_1
       (.I0(std_bool),
        .I1(realign_r),
        .I2(begin_r_reg_0),
        .O(next_polarity_c));
  FDRE polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_polarity_c),
        .Q(polarity_r),
        .R(begin_r0));
  LUT2 #(
    .INIT(4'hE)) 
    prev_char_was_comma_r_i_1
       (.I0(RX_CHAR_IS_COMMA_R[1]),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c1));
  FDRE prev_char_was_comma_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(inc_count_c1),
        .Q(prev_char_was_comma_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    ready_r_i_1
       (.I0(\counter2_r_reg_n_0_[15] ),
        .I1(D),
        .I2(RX_NEG_Buffer),
        .I3(polarity_r),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFF040404)) 
    realign_r_i_1
       (.I0(begin_r_reg_0),
        .I1(realign_r),
        .I2(std_bool),
        .I3(std_bool0_in),
        .I4(align_r_reg_0),
        .O(next_realign_c));
  FDRE realign_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_realign_c),
        .Q(realign_r),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFFFF04F5)) 
    reset_count_r_i_1
       (.I0(reset_count_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .I3(rst_r_reg_0),
        .I4(SR),
        .O(reset_count_r0));
  FDRE reset_count_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_count_r0),
        .Q(reset_count_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF2)) 
    rst_r_i_1
       (.I0(rst_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .O(next_rst_c));
  FDRE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(rst_r_reg_0),
        .R(begin_r0));
  LUT3 #(
    .INIT(8'h78)) 
    rx_polarity_r_i_1
       (.I0(RX_NEG_Buffer),
        .I1(polarity_r),
        .I2(rx_polarity_i_0),
        .O(rx_polarity_r_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rx_polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_polarity_r_i_1_n_0),
        .Q(rx_polarity_i_0),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \soft_err_r[0]_i_1 
       (.I0(enable_err_detect_i),
        .O(ENABLE_ERR_DETECT_Buffer_reg_0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX" *) 
module aurora_rx_4l_64b_RX_LANE_INIT_SM_SIMPLEX_8
   (RX_LANE_UP,
    align_r_reg_0,
    comma_over_two_cycles_r,
    rst_r_reg_0,
    enable_err_detect_i,
    rx_polarity_i_2,
    gthe2_i,
    ENABLE_ERR_DETECT_Buffer_reg_0,
    SR,
    user_clk,
    begin_r0,
    begin_r_reg_0,
    RX_NEG_Buffer,
    reset_count_r_reg_0,
    rx_sp_i,
    \counter2_r_reg[15]_0 ,
    \RX_CHAR_IS_COMMA_R_reg[1]_0 ,
    left_aligned_r_reg,
    left_aligned_r_reg_0);
  output [0:0]RX_LANE_UP;
  output align_r_reg_0;
  output comma_over_two_cycles_r;
  output rst_r_reg_0;
  output enable_err_detect_i;
  output rx_polarity_i_2;
  output gthe2_i;
  output ENABLE_ERR_DETECT_Buffer_reg_0;
  input [0:0]SR;
  input user_clk;
  input begin_r0;
  input begin_r_reg_0;
  input RX_NEG_Buffer;
  input reset_count_r_reg_0;
  input rx_sp_i;
  input \counter2_r_reg[15]_0 ;
  input [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  input left_aligned_r_reg;
  input left_aligned_r_reg_0;

  wire D;
  wire ENABLE_ERR_DETECT_Buffer_reg_0;
  wire [1:0]RX_CHAR_IS_COMMA_R;
  wire [1:0]\RX_CHAR_IS_COMMA_R_reg[1]_0 ;
  wire [0:0]RX_LANE_UP;
  wire RX_NEG_Buffer;
  wire [0:0]SR;
  wire align_r_reg_0;
  wire begin_r;
  wire begin_r0;
  wire begin_r_reg_0;
  wire comma_over_two_cycles_r;
  wire comma_over_two_cycles_r0;
  wire counter1_r0;
  wire \counter1_r[0]_i_4__1_n_0 ;
  wire \counter1_r[2]_i_1__1_n_0 ;
  wire \counter1_r_reg_n_0_[1] ;
  wire \counter1_r_reg_n_0_[3] ;
  wire \counter1_r_reg_n_0_[5] ;
  wire \counter1_r_reg_n_0_[6] ;
  wire \counter1_r_reg_n_0_[7] ;
  wire counter2_r0;
  wire \counter2_r_reg[14]_srl15_n_0 ;
  wire \counter2_r_reg[15]_0 ;
  wire \counter2_r_reg_n_0_[15] ;
  wire enable_err_detect_i;
  wire gthe2_i;
  wire inc_count_c;
  wire inc_count_c1;
  wire left_aligned_r_reg;
  wire left_aligned_r_reg_0;
  wire next_align_c;
  wire next_begin_c;
  wire next_polarity_c;
  wire next_ready_c;
  wire next_realign_c;
  wire next_rst_c;
  wire [7:0]p_0_in;
  wire polarity_r;
  wire prev_char_was_comma_r;
  wire realign_r;
  wire reset_count_r;
  wire reset_count_r0;
  wire reset_count_r_reg_0;
  wire rst_r_reg_0;
  wire rx_polarity_i_2;
  wire rx_polarity_r_i_1__1_n_0;
  wire rx_sp_i;
  wire std_bool;
  wire std_bool0_in;
  wire std_bool0_in3_in;
  wire user_clk;

  FDRE ENABLE_ERR_DETECT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(enable_err_detect_i),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .Q(RX_CHAR_IS_COMMA_R[0]),
        .R(1'b0));
  FDRE \RX_CHAR_IS_COMMA_R_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RX_CHAR_IS_COMMA_R_reg[1]_0 [1]),
        .Q(RX_CHAR_IS_COMMA_R[1]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hF444)) 
    align_r_i_2__1
       (.I0(std_bool0_in),
        .I1(align_r_reg_0),
        .I2(std_bool0_in3_in),
        .I3(rst_r_reg_0),
        .O(next_align_c));
  FDRE align_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_align_c),
        .Q(align_r_reg_0),
        .R(begin_r0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    begin_r_i_1__1
       (.I0(realign_r),
        .I1(begin_r_reg_0),
        .I2(D),
        .I3(\counter2_r_reg_n_0_[15] ),
        .I4(polarity_r),
        .I5(RX_NEG_Buffer),
        .O(next_begin_c));
  FDSE begin_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_begin_c),
        .Q(begin_r),
        .S(begin_r0));
  LUT4 #(
    .INIT(16'h57FD)) 
    comma_over_two_cycles_r_i_1__1
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .I2(RX_CHAR_IS_COMMA_R[1]),
        .I3(prev_char_was_comma_r),
        .O(comma_over_two_cycles_r0));
  FDRE comma_over_two_cycles_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(comma_over_two_cycles_r0),
        .Q(comma_over_two_cycles_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \counter1_r[0]_i_1__1 
       (.I0(D),
        .I1(reset_count_r),
        .O(counter1_r0));
  LUT3 #(
    .INIT(8'hFD)) 
    \counter1_r[0]_i_2__1 
       (.I0(align_r_reg_0),
        .I1(RX_CHAR_IS_COMMA_R[1]),
        .I2(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[0]_i_3__1 
       (.I0(std_bool0_in),
        .I1(std_bool),
        .I2(std_bool0_in3_in),
        .I3(\counter1_r[0]_i_4__1_n_0 ),
        .I4(\counter1_r_reg_n_0_[3] ),
        .I5(\counter1_r_reg_n_0_[1] ),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \counter1_r[0]_i_4__1 
       (.I0(\counter1_r_reg_n_0_[5] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[7] ),
        .O(\counter1_r[0]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[1]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[1] ),
        .I1(\counter1_r_reg_n_0_[3] ),
        .I2(\counter1_r[0]_i_4__1_n_0 ),
        .I3(std_bool0_in3_in),
        .I4(std_bool),
        .O(p_0_in[6]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \counter1_r[2]_i_1__1 
       (.I0(std_bool),
        .I1(std_bool0_in3_in),
        .I2(\counter1_r_reg_n_0_[7] ),
        .I3(\counter1_r_reg_n_0_[6] ),
        .I4(\counter1_r_reg_n_0_[5] ),
        .I5(\counter1_r_reg_n_0_[3] ),
        .O(\counter1_r[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \counter1_r[3]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[3] ),
        .I1(\counter1_r_reg_n_0_[5] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[7] ),
        .I4(std_bool0_in3_in),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \counter1_r[4]_i_1__1 
       (.I0(std_bool0_in3_in),
        .I1(\counter1_r_reg_n_0_[7] ),
        .I2(\counter1_r_reg_n_0_[6] ),
        .I3(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter1_r[5]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .I2(\counter1_r_reg_n_0_[5] ),
        .O(p_0_in[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \counter1_r[6]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .I1(\counter1_r_reg_n_0_[6] ),
        .O(p_0_in[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \counter1_r[7]_i_1__1 
       (.I0(\counter1_r_reg_n_0_[7] ),
        .O(p_0_in[0]));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[0] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[7]),
        .Q(std_bool0_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[1] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[6]),
        .Q(\counter1_r_reg_n_0_[1] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[2] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(\counter1_r[2]_i_1__1_n_0 ),
        .Q(std_bool),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[3] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[4]),
        .Q(\counter1_r_reg_n_0_[3] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[4] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[3]),
        .Q(std_bool0_in3_in),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[5] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[2]),
        .Q(\counter1_r_reg_n_0_[5] ),
        .R(counter1_r0));
  FDRE #(
    .INIT(1'b0)) 
    \counter1_r_reg[6] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[1]),
        .Q(\counter1_r_reg_n_0_[6] ),
        .R(counter1_r0));
  FDSE #(
    .INIT(1'b1)) 
    \counter1_r_reg[7] 
       (.C(user_clk),
        .CE(inc_count_c),
        .D(p_0_in[0]),
        .Q(\counter1_r_reg_n_0_[7] ),
        .S(counter1_r0));
  (* srl_bus_name = "U0/\rx_aurora_lane_simplex_v5_2_i/rx_lane_init_sm_simplex_i/counter2_r_reg " *) 
  (* srl_name = "U0/\rx_aurora_lane_simplex_v5_2_i/rx_lane_init_sm_simplex_i/counter2_r_reg[14]_srl15 " *) 
  SRL16E \counter2_r_reg[14]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(counter2_r0),
        .CLK(user_clk),
        .D(D),
        .Q(\counter2_r_reg[14]_srl15_n_0 ));
  LUT3 #(
    .INIT(8'hD5)) 
    \counter2_r_reg[14]_srl15_i_1__1 
       (.I0(D),
        .I1(rx_sp_i),
        .I2(\counter2_r_reg[15]_0 ),
        .O(counter2_r0));
  FDRE \counter2_r_reg[15] 
       (.C(user_clk),
        .CE(counter2_r0),
        .D(\counter2_r_reg[14]_srl15_n_0 ),
        .Q(\counter2_r_reg_n_0_[15] ),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    lane_up_flop_i
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(RX_LANE_UP),
        .R(SR));
  LUT5 #(
    .INIT(32'hFFAB00A8)) 
    left_aligned_r_i_1__1
       (.I0(\RX_CHAR_IS_COMMA_R_reg[1]_0 [0]),
        .I1(align_r_reg_0),
        .I2(D),
        .I3(left_aligned_r_reg),
        .I4(left_aligned_r_reg_0),
        .O(gthe2_i));
  LUT3 #(
    .INIT(8'h08)) 
    polarity_r_i_1__1
       (.I0(std_bool),
        .I1(realign_r),
        .I2(begin_r_reg_0),
        .O(next_polarity_c));
  FDRE polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_polarity_c),
        .Q(polarity_r),
        .R(begin_r0));
  LUT2 #(
    .INIT(4'hE)) 
    prev_char_was_comma_r_i_1__1
       (.I0(RX_CHAR_IS_COMMA_R[1]),
        .I1(RX_CHAR_IS_COMMA_R[0]),
        .O(inc_count_c1));
  FDRE prev_char_was_comma_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(inc_count_c1),
        .Q(prev_char_was_comma_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    ready_r_i_1__1
       (.I0(\counter2_r_reg_n_0_[15] ),
        .I1(D),
        .I2(RX_NEG_Buffer),
        .I3(polarity_r),
        .O(next_ready_c));
  FDRE ready_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_ready_c),
        .Q(D),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFF040404)) 
    realign_r_i_1__1
       (.I0(begin_r_reg_0),
        .I1(realign_r),
        .I2(std_bool),
        .I3(std_bool0_in),
        .I4(align_r_reg_0),
        .O(next_realign_c));
  FDRE realign_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_realign_c),
        .Q(realign_r),
        .R(begin_r0));
  LUT5 #(
    .INIT(32'hFFFF04F5)) 
    reset_count_r_i_1__1
       (.I0(reset_count_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .I3(rst_r_reg_0),
        .I4(SR),
        .O(reset_count_r0));
  FDRE reset_count_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(reset_count_r0),
        .Q(reset_count_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF2)) 
    rst_r_i_1__1
       (.I0(rst_r_reg_0),
        .I1(std_bool0_in3_in),
        .I2(begin_r),
        .O(next_rst_c));
  FDRE rst_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_rst_c),
        .Q(rst_r_reg_0),
        .R(begin_r0));
  LUT3 #(
    .INIT(8'h78)) 
    rx_polarity_r_i_1__1
       (.I0(RX_NEG_Buffer),
        .I1(polarity_r),
        .I2(rx_polarity_i_2),
        .O(rx_polarity_r_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rx_polarity_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_polarity_r_i_1__1_n_0),
        .Q(rx_polarity_i_2),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \soft_err_r[0]_i_1__1 
       (.I0(enable_err_detect_i),
        .O(ENABLE_ERR_DETECT_Buffer_reg_0));
endmodule

module aurora_rx_4l_64b_RX_LL
   (RX_EOF_N,
    FRAME_ERR,
    M_AXI_RX_TLAST,
    M_AXI_RX_TVALID,
    M_AXI_UFC_RX_TLAST,
    UFC_RX_EOF_N,
    M_AXI_UFC_RX_TVALID,
    \RX_REM_Buffer_reg[0] ,
    M_AXI_RX_TDATA,
    \UFC_RX_REM_Buffer_reg[0] ,
    M_AXI_UFC_RX_TDATA,
    RESET,
    neqOp,
    user_clk,
    \stage_1_lane_mask_r_reg[3] ,
    \stage_1_lane_mask_r_reg[1] ,
    \stage_1_lane_mask_r_reg[2] ,
    std_bool26_out,
    std_bool26_out_0,
    std_bool26_out_1,
    std_bool26_out_2,
    RX_ECP_Buffer0,
    RX_ECP_Buffer0_3,
    RX_ECP_Buffer0_4,
    RX_ECP_Buffer0_5,
    \stage_1_data_r_reg[0] ,
    \stage_1_data_r_reg[16] ,
    \stage_1_data_r_reg[48] ,
    \stage_1_data_r_reg[32] ,
    \stage_1_data_r_reg[11] ,
    Q,
    \stage_1_data_r_reg[59] ,
    \stage_1_data_r_reg[43] ,
    RX_PE_DATA,
    \stage_1_data_r_reg[26] ,
    \stage_1_data_r_reg[58] ,
    \stage_1_data_r_reg[42] ,
    \stage_1_data_r_reg[25] ,
    \stage_1_data_r_reg[57] ,
    \stage_1_data_r_reg[41] ,
    \stage_1_data_r_reg[24] ,
    \stage_1_data_r_reg[56] ,
    \stage_1_data_r_reg[40] ,
    start_rx_i,
    \stage_1_count_value_r_reg[0] ,
    \stage_1_count_value_r_reg[1] ,
    \stage_1_count_value_r_reg[2] ,
    \stage_1_count_value_r_reg[3] ,
    D,
    \rx_scp_r_reg[0] ,
    \rx_suf_r_reg[0] ,
    \rx_suf_r_reg[2] );
  output RX_EOF_N;
  output FRAME_ERR;
  output M_AXI_RX_TLAST;
  output M_AXI_RX_TVALID;
  output M_AXI_UFC_RX_TLAST;
  output UFC_RX_EOF_N;
  output M_AXI_UFC_RX_TVALID;
  output [2:0]\RX_REM_Buffer_reg[0] ;
  output [63:0]M_AXI_RX_TDATA;
  output [1:0]\UFC_RX_REM_Buffer_reg[0] ;
  output [63:0]M_AXI_UFC_RX_TDATA;
  input RESET;
  input neqOp;
  input user_clk;
  input \stage_1_lane_mask_r_reg[3] ;
  input \stage_1_lane_mask_r_reg[1] ;
  input \stage_1_lane_mask_r_reg[2] ;
  input std_bool26_out;
  input std_bool26_out_0;
  input std_bool26_out_1;
  input std_bool26_out_2;
  input RX_ECP_Buffer0;
  input RX_ECP_Buffer0_3;
  input RX_ECP_Buffer0_4;
  input RX_ECP_Buffer0_5;
  input [7:0]\stage_1_data_r_reg[0] ;
  input [7:0]\stage_1_data_r_reg[16] ;
  input [7:0]\stage_1_data_r_reg[48] ;
  input [7:0]\stage_1_data_r_reg[32] ;
  input [4:0]\stage_1_data_r_reg[11] ;
  input [4:0]Q;
  input [4:0]\stage_1_data_r_reg[59] ;
  input [4:0]\stage_1_data_r_reg[43] ;
  input [2:0]RX_PE_DATA;
  input \stage_1_data_r_reg[26] ;
  input \stage_1_data_r_reg[58] ;
  input \stage_1_data_r_reg[42] ;
  input \stage_1_data_r_reg[25] ;
  input \stage_1_data_r_reg[57] ;
  input \stage_1_data_r_reg[41] ;
  input \stage_1_data_r_reg[24] ;
  input \stage_1_data_r_reg[56] ;
  input \stage_1_data_r_reg[40] ;
  input start_rx_i;
  input \stage_1_count_value_r_reg[0] ;
  input \stage_1_count_value_r_reg[1] ;
  input \stage_1_count_value_r_reg[2] ;
  input \stage_1_count_value_r_reg[3] ;
  input [3:0]D;
  input [3:0]\rx_scp_r_reg[0] ;
  input [2:0]\rx_suf_r_reg[0] ;
  input [0:0]\rx_suf_r_reg[2] ;

  wire [3:0]D;
  wire FRAME_ERR;
  wire [63:0]M_AXI_RX_TDATA;
  wire M_AXI_RX_TLAST;
  wire M_AXI_RX_TVALID;
  wire [63:0]M_AXI_UFC_RX_TDATA;
  wire M_AXI_UFC_RX_TLAST;
  wire M_AXI_UFC_RX_TVALID;
  wire [4:0]Q;
  wire RESET;
  wire RX_ECP_Buffer0;
  wire RX_ECP_Buffer0_3;
  wire RX_ECP_Buffer0_4;
  wire RX_ECP_Buffer0_5;
  wire RX_EOF_N;
  wire [2:0]RX_PE_DATA;
  wire [2:0]\RX_REM_Buffer_reg[0] ;
  wire UFC_RX_EOF_N;
  wire [1:0]\UFC_RX_REM_Buffer_reg[0] ;
  wire neqOp;
  wire [15:0]p_1_in;
  wire [15:0]p_2_in;
  wire [0:3]pdu_data_v_i;
  wire [0:3]pdu_ecp_i;
  wire [0:3]pdu_pad_i;
  wire [0:3]pdu_scp_i;
  wire rx_ll_ufc_datapath_i_n_0;
  wire rx_ll_ufc_datapath_i_n_1;
  wire rx_ll_ufc_datapath_i_n_10;
  wire rx_ll_ufc_datapath_i_n_11;
  wire rx_ll_ufc_datapath_i_n_12;
  wire rx_ll_ufc_datapath_i_n_13;
  wire rx_ll_ufc_datapath_i_n_14;
  wire rx_ll_ufc_datapath_i_n_15;
  wire rx_ll_ufc_datapath_i_n_2;
  wire rx_ll_ufc_datapath_i_n_3;
  wire rx_ll_ufc_datapath_i_n_4;
  wire rx_ll_ufc_datapath_i_n_48;
  wire rx_ll_ufc_datapath_i_n_49;
  wire rx_ll_ufc_datapath_i_n_5;
  wire rx_ll_ufc_datapath_i_n_50;
  wire rx_ll_ufc_datapath_i_n_51;
  wire rx_ll_ufc_datapath_i_n_52;
  wire rx_ll_ufc_datapath_i_n_53;
  wire rx_ll_ufc_datapath_i_n_54;
  wire rx_ll_ufc_datapath_i_n_55;
  wire rx_ll_ufc_datapath_i_n_56;
  wire rx_ll_ufc_datapath_i_n_57;
  wire rx_ll_ufc_datapath_i_n_58;
  wire rx_ll_ufc_datapath_i_n_59;
  wire rx_ll_ufc_datapath_i_n_6;
  wire rx_ll_ufc_datapath_i_n_60;
  wire rx_ll_ufc_datapath_i_n_61;
  wire rx_ll_ufc_datapath_i_n_62;
  wire rx_ll_ufc_datapath_i_n_63;
  wire rx_ll_ufc_datapath_i_n_7;
  wire rx_ll_ufc_datapath_i_n_8;
  wire rx_ll_ufc_datapath_i_n_9;
  wire [3:0]\rx_scp_r_reg[0] ;
  wire [2:0]\rx_suf_r_reg[0] ;
  wire [0:0]\rx_suf_r_reg[2] ;
  wire \stage_1_count_value_r_reg[0] ;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[2] ;
  wire \stage_1_count_value_r_reg[3] ;
  wire [7:0]\stage_1_data_r_reg[0] ;
  wire [4:0]\stage_1_data_r_reg[11] ;
  wire [7:0]\stage_1_data_r_reg[16] ;
  wire \stage_1_data_r_reg[24] ;
  wire \stage_1_data_r_reg[25] ;
  wire \stage_1_data_r_reg[26] ;
  wire [7:0]\stage_1_data_r_reg[32] ;
  wire \stage_1_data_r_reg[40] ;
  wire \stage_1_data_r_reg[41] ;
  wire \stage_1_data_r_reg[42] ;
  wire [4:0]\stage_1_data_r_reg[43] ;
  wire [7:0]\stage_1_data_r_reg[48] ;
  wire \stage_1_data_r_reg[56] ;
  wire \stage_1_data_r_reg[57] ;
  wire \stage_1_data_r_reg[58] ;
  wire [4:0]\stage_1_data_r_reg[59] ;
  wire \stage_1_lane_mask_r_reg[1] ;
  wire \stage_1_lane_mask_r_reg[2] ;
  wire \stage_1_lane_mask_r_reg[3] ;
  wire \stage_1_rx_ll_deframer_i/S1_in ;
  wire \stage_1_rx_ll_deframer_i/S3_in ;
  wire \stage_1_rx_ll_deframer_i/S5_in ;
  wire start_rx_i;
  wire std_bool26_out;
  wire std_bool26_out_0;
  wire std_bool26_out_1;
  wire std_bool26_out_2;
  wire [0:3]ufc_data_v_i;
  wire ufc_filter_i_n_10;
  wire ufc_filter_i_n_11;
  wire ufc_filter_i_n_12;
  wire ufc_filter_i_n_13;
  wire ufc_filter_i_n_14;
  wire ufc_filter_i_n_15;
  wire ufc_filter_i_n_16;
  wire ufc_filter_i_n_17;
  wire ufc_filter_i_n_18;
  wire ufc_filter_i_n_19;
  wire ufc_filter_i_n_20;
  wire ufc_filter_i_n_21;
  wire ufc_filter_i_n_22;
  wire ufc_filter_i_n_23;
  wire ufc_filter_i_n_24;
  wire ufc_filter_i_n_25;
  wire ufc_filter_i_n_26;
  wire ufc_filter_i_n_27;
  wire ufc_filter_i_n_28;
  wire ufc_filter_i_n_29;
  wire ufc_filter_i_n_30;
  wire ufc_filter_i_n_31;
  wire ufc_filter_i_n_32;
  wire ufc_filter_i_n_33;
  wire ufc_filter_i_n_34;
  wire ufc_filter_i_n_35;
  wire ufc_filter_i_n_36;
  wire ufc_filter_i_n_37;
  wire ufc_filter_i_n_38;
  wire ufc_filter_i_n_39;
  wire ufc_filter_i_n_40;
  wire ufc_filter_i_n_41;
  wire ufc_filter_i_n_42;
  wire ufc_filter_i_n_43;
  wire ufc_filter_i_n_44;
  wire ufc_filter_i_n_45;
  wire ufc_filter_i_n_46;
  wire ufc_filter_i_n_47;
  wire ufc_filter_i_n_48;
  wire ufc_filter_i_n_49;
  wire ufc_filter_i_n_50;
  wire ufc_filter_i_n_51;
  wire ufc_filter_i_n_52;
  wire ufc_filter_i_n_53;
  wire ufc_filter_i_n_54;
  wire ufc_filter_i_n_55;
  wire ufc_filter_i_n_56;
  wire ufc_filter_i_n_57;
  wire ufc_filter_i_n_58;
  wire ufc_filter_i_n_59;
  wire ufc_filter_i_n_60;
  wire ufc_filter_i_n_61;
  wire ufc_filter_i_n_62;
  wire ufc_filter_i_n_63;
  wire ufc_filter_i_n_64;
  wire ufc_filter_i_n_65;
  wire ufc_filter_i_n_66;
  wire ufc_filter_i_n_67;
  wire ufc_filter_i_n_68;
  wire ufc_filter_i_n_69;
  wire ufc_filter_i_n_70;
  wire ufc_filter_i_n_71;
  wire ufc_filter_i_n_72;
  wire ufc_filter_i_n_73;
  wire ufc_filter_i_n_78;
  wire ufc_filter_i_n_79;
  wire ufc_filter_i_n_80;
  wire ufc_filter_i_n_81;
  wire ufc_filter_i_n_82;
  wire ufc_filter_i_n_9;
  wire ufc_filter_i_n_91;
  wire ufc_start_i;
  wire user_clk;

  aurora_rx_4l_64b_RX_LL_PDU_DATAPATH rx_ll_pdu_datapath_i
       (.D({pdu_ecp_i[0],pdu_ecp_i[1],pdu_ecp_i[2],pdu_ecp_i[3]}),
        .\DEFRAMED_DATA_V_Buffer_reg[0] ({pdu_data_v_i[0],pdu_data_v_i[1],pdu_data_v_i[2],pdu_data_v_i[3]}),
        .FRAME_ERR(FRAME_ERR),
        .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
        .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
        .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
        .Q({pdu_scp_i[0],pdu_scp_i[1],pdu_scp_i[2],pdu_scp_i[3]}),
        .RESET(RESET),
        .RX_EOF_N(RX_EOF_N),
        .\RX_REM_Buffer_reg[0]_0 (\RX_REM_Buffer_reg[0] ),
        .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
        .S3_in(\stage_1_rx_ll_deframer_i/S3_in ),
        .S5_in(\stage_1_rx_ll_deframer_i/S5_in ),
        .data_after_start_muxcy_3(ufc_filter_i_n_91),
        .in_frame_muxcy_0(ufc_filter_i_n_80),
        .in_frame_muxcy_1(ufc_filter_i_n_79),
        .in_frame_muxcy_2(ufc_filter_i_n_78),
        .in_frame_muxcy_3(ufc_filter_i_n_73),
        .pdu_pad_i(pdu_pad_i),
        .\stage_2_data_r_reg[0]_0 ({rx_ll_ufc_datapath_i_n_0,rx_ll_ufc_datapath_i_n_1,rx_ll_ufc_datapath_i_n_2,rx_ll_ufc_datapath_i_n_3,rx_ll_ufc_datapath_i_n_4,rx_ll_ufc_datapath_i_n_5,rx_ll_ufc_datapath_i_n_6,rx_ll_ufc_datapath_i_n_7,rx_ll_ufc_datapath_i_n_8,rx_ll_ufc_datapath_i_n_9,rx_ll_ufc_datapath_i_n_10,rx_ll_ufc_datapath_i_n_11,rx_ll_ufc_datapath_i_n_12,rx_ll_ufc_datapath_i_n_13,rx_ll_ufc_datapath_i_n_14,rx_ll_ufc_datapath_i_n_15,p_2_in,p_1_in,rx_ll_ufc_datapath_i_n_48,rx_ll_ufc_datapath_i_n_49,rx_ll_ufc_datapath_i_n_50,rx_ll_ufc_datapath_i_n_51,rx_ll_ufc_datapath_i_n_52,rx_ll_ufc_datapath_i_n_53,rx_ll_ufc_datapath_i_n_54,rx_ll_ufc_datapath_i_n_55,rx_ll_ufc_datapath_i_n_56,rx_ll_ufc_datapath_i_n_57,rx_ll_ufc_datapath_i_n_58,rx_ll_ufc_datapath_i_n_59,rx_ll_ufc_datapath_i_n_60,rx_ll_ufc_datapath_i_n_61,rx_ll_ufc_datapath_i_n_62,rx_ll_ufc_datapath_i_n_63}),
        .start_rx_i(start_rx_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_RX_LL_UFC_DATAPATH rx_ll_ufc_datapath_i
       (.\BARREL_SHIFTER_CONTROL_Buffer_reg[1] (ufc_filter_i_n_81),
        .\BARREL_SHIFTER_CONTROL_Buffer_reg[2] (ufc_filter_i_n_82),
        .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
        .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
        .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
        .Q({ufc_data_v_i[0],ufc_data_v_i[1],ufc_data_v_i[2],ufc_data_v_i[3]}),
        .RESET(RESET),
        .UFC_RX_EOF_N(UFC_RX_EOF_N),
        .\UFC_RX_REM_Buffer_reg[0]_0 (\UFC_RX_REM_Buffer_reg[0] ),
        .\stage_1_data_r_reg[0]_0 ({rx_ll_ufc_datapath_i_n_0,rx_ll_ufc_datapath_i_n_1,rx_ll_ufc_datapath_i_n_2,rx_ll_ufc_datapath_i_n_3,rx_ll_ufc_datapath_i_n_4,rx_ll_ufc_datapath_i_n_5,rx_ll_ufc_datapath_i_n_6,rx_ll_ufc_datapath_i_n_7,rx_ll_ufc_datapath_i_n_8,rx_ll_ufc_datapath_i_n_9,rx_ll_ufc_datapath_i_n_10,rx_ll_ufc_datapath_i_n_11,rx_ll_ufc_datapath_i_n_12,rx_ll_ufc_datapath_i_n_13,rx_ll_ufc_datapath_i_n_14,rx_ll_ufc_datapath_i_n_15,p_2_in,p_1_in,rx_ll_ufc_datapath_i_n_48,rx_ll_ufc_datapath_i_n_49,rx_ll_ufc_datapath_i_n_50,rx_ll_ufc_datapath_i_n_51,rx_ll_ufc_datapath_i_n_52,rx_ll_ufc_datapath_i_n_53,rx_ll_ufc_datapath_i_n_54,rx_ll_ufc_datapath_i_n_55,rx_ll_ufc_datapath_i_n_56,rx_ll_ufc_datapath_i_n_57,rx_ll_ufc_datapath_i_n_58,rx_ll_ufc_datapath_i_n_59,rx_ll_ufc_datapath_i_n_60,rx_ll_ufc_datapath_i_n_61,rx_ll_ufc_datapath_i_n_62,rx_ll_ufc_datapath_i_n_63}),
        .\stage_1_data_r_reg[0]_1 (ufc_filter_i_n_37),
        .\stage_1_data_r_reg[10]_0 (ufc_filter_i_n_61),
        .\stage_1_data_r_reg[11]_0 (ufc_filter_i_n_57),
        .\stage_1_data_r_reg[12]_0 (ufc_filter_i_n_53),
        .\stage_1_data_r_reg[13]_0 (ufc_filter_i_n_49),
        .\stage_1_data_r_reg[14]_0 (ufc_filter_i_n_45),
        .\stage_1_data_r_reg[15]_0 (ufc_filter_i_n_41),
        .\stage_1_data_r_reg[16]_0 (ufc_filter_i_n_38),
        .\stage_1_data_r_reg[17]_0 (ufc_filter_i_n_34),
        .\stage_1_data_r_reg[18]_0 (ufc_filter_i_n_30),
        .\stage_1_data_r_reg[19]_0 (ufc_filter_i_n_26),
        .\stage_1_data_r_reg[1]_0 (ufc_filter_i_n_33),
        .\stage_1_data_r_reg[20]_0 (ufc_filter_i_n_22),
        .\stage_1_data_r_reg[21]_0 (ufc_filter_i_n_18),
        .\stage_1_data_r_reg[22]_0 (ufc_filter_i_n_14),
        .\stage_1_data_r_reg[23]_0 (ufc_filter_i_n_10),
        .\stage_1_data_r_reg[24]_0 (ufc_filter_i_n_70),
        .\stage_1_data_r_reg[25]_0 (ufc_filter_i_n_66),
        .\stage_1_data_r_reg[26]_0 (ufc_filter_i_n_62),
        .\stage_1_data_r_reg[27]_0 (ufc_filter_i_n_58),
        .\stage_1_data_r_reg[28]_0 (ufc_filter_i_n_54),
        .\stage_1_data_r_reg[29]_0 (ufc_filter_i_n_50),
        .\stage_1_data_r_reg[2]_0 (ufc_filter_i_n_29),
        .\stage_1_data_r_reg[30]_0 (ufc_filter_i_n_46),
        .\stage_1_data_r_reg[31]_0 (ufc_filter_i_n_42),
        .\stage_1_data_r_reg[32]_0 (ufc_filter_i_n_40),
        .\stage_1_data_r_reg[33]_0 (ufc_filter_i_n_36),
        .\stage_1_data_r_reg[34]_0 (ufc_filter_i_n_32),
        .\stage_1_data_r_reg[35]_0 (ufc_filter_i_n_28),
        .\stage_1_data_r_reg[36]_0 (ufc_filter_i_n_24),
        .\stage_1_data_r_reg[37]_0 (ufc_filter_i_n_20),
        .\stage_1_data_r_reg[38]_0 (ufc_filter_i_n_16),
        .\stage_1_data_r_reg[39]_0 (ufc_filter_i_n_12),
        .\stage_1_data_r_reg[3]_0 (ufc_filter_i_n_25),
        .\stage_1_data_r_reg[40]_0 (ufc_filter_i_n_72),
        .\stage_1_data_r_reg[41]_0 (ufc_filter_i_n_68),
        .\stage_1_data_r_reg[42]_0 (ufc_filter_i_n_64),
        .\stage_1_data_r_reg[43]_0 (ufc_filter_i_n_60),
        .\stage_1_data_r_reg[44]_0 (ufc_filter_i_n_56),
        .\stage_1_data_r_reg[45]_0 (ufc_filter_i_n_52),
        .\stage_1_data_r_reg[46]_0 (ufc_filter_i_n_48),
        .\stage_1_data_r_reg[47]_0 (ufc_filter_i_n_44),
        .\stage_1_data_r_reg[48]_0 (ufc_filter_i_n_39),
        .\stage_1_data_r_reg[49]_0 (ufc_filter_i_n_35),
        .\stage_1_data_r_reg[4]_0 (ufc_filter_i_n_21),
        .\stage_1_data_r_reg[50]_0 (ufc_filter_i_n_31),
        .\stage_1_data_r_reg[51]_0 (ufc_filter_i_n_27),
        .\stage_1_data_r_reg[52]_0 (ufc_filter_i_n_23),
        .\stage_1_data_r_reg[53]_0 (ufc_filter_i_n_19),
        .\stage_1_data_r_reg[54]_0 (ufc_filter_i_n_15),
        .\stage_1_data_r_reg[55]_0 (ufc_filter_i_n_11),
        .\stage_1_data_r_reg[56]_0 (ufc_filter_i_n_71),
        .\stage_1_data_r_reg[57]_0 (ufc_filter_i_n_67),
        .\stage_1_data_r_reg[58]_0 (ufc_filter_i_n_63),
        .\stage_1_data_r_reg[59]_0 (ufc_filter_i_n_59),
        .\stage_1_data_r_reg[5]_0 (ufc_filter_i_n_17),
        .\stage_1_data_r_reg[60]_0 (ufc_filter_i_n_55),
        .\stage_1_data_r_reg[61]_0 (ufc_filter_i_n_51),
        .\stage_1_data_r_reg[62]_0 (ufc_filter_i_n_47),
        .\stage_1_data_r_reg[63]_0 (ufc_filter_i_n_43),
        .\stage_1_data_r_reg[6]_0 (ufc_filter_i_n_13),
        .\stage_1_data_r_reg[7]_0 (ufc_filter_i_n_9),
        .\stage_1_data_r_reg[8]_0 (ufc_filter_i_n_69),
        .\stage_1_data_r_reg[9]_0 (ufc_filter_i_n_65),
        .ufc_start_i(ufc_start_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_FILTER ufc_filter_i
       (.D({pdu_ecp_i[0],pdu_ecp_i[1],pdu_ecp_i[2],pdu_ecp_i[3]}),
        .\PDU_DATA_V_Buffer_reg[0]_0 ({pdu_data_v_i[0],pdu_data_v_i[1],pdu_data_v_i[2],pdu_data_v_i[3]}),
        .\PDU_ECP_Buffer_reg[0]_0 (ufc_filter_i_n_80),
        .\PDU_ECP_Buffer_reg[1]_0 (ufc_filter_i_n_79),
        .\PDU_ECP_Buffer_reg[2]_0 (ufc_filter_i_n_78),
        .\PDU_ECP_Buffer_reg[3]_0 (ufc_filter_i_n_73),
        .\PDU_SCP_Buffer_reg[0]_0 ({pdu_scp_i[0],pdu_scp_i[1],pdu_scp_i[2],pdu_scp_i[3]}),
        .\PDU_SCP_Buffer_reg[3]_0 (ufc_filter_i_n_91),
        .Q(Q),
        .RESET(RESET),
        .RX_ECP_Buffer0(RX_ECP_Buffer0),
        .RX_ECP_Buffer0_3(RX_ECP_Buffer0_3),
        .RX_ECP_Buffer0_4(RX_ECP_Buffer0_4),
        .RX_ECP_Buffer0_5(RX_ECP_Buffer0_5),
        .RX_PE_DATA(RX_PE_DATA),
        .\RX_PE_DATA_Buffer_reg[10] (ufc_filter_i_n_61),
        .\RX_PE_DATA_Buffer_reg[10]_0 (ufc_filter_i_n_62),
        .\RX_PE_DATA_Buffer_reg[10]_1 (ufc_filter_i_n_63),
        .\RX_PE_DATA_Buffer_reg[10]_2 (ufc_filter_i_n_64),
        .\RX_PE_DATA_Buffer_reg[8] (ufc_filter_i_n_69),
        .\RX_PE_DATA_Buffer_reg[8]_0 (ufc_filter_i_n_70),
        .\RX_PE_DATA_Buffer_reg[8]_1 (ufc_filter_i_n_71),
        .\RX_PE_DATA_Buffer_reg[8]_2 (ufc_filter_i_n_72),
        .\RX_PE_DATA_Buffer_reg[9] (ufc_filter_i_n_65),
        .\RX_PE_DATA_Buffer_reg[9]_0 (ufc_filter_i_n_66),
        .\RX_PE_DATA_Buffer_reg[9]_1 (ufc_filter_i_n_67),
        .\RX_PE_DATA_Buffer_reg[9]_2 (ufc_filter_i_n_68),
        .S1_in(\stage_1_rx_ll_deframer_i/S1_in ),
        .S3_in(\stage_1_rx_ll_deframer_i/S3_in ),
        .S5_in(\stage_1_rx_ll_deframer_i/S5_in ),
        .\UFC_DATA_V_Buffer_reg[0]_0 ({ufc_data_v_i[0],ufc_data_v_i[1],ufc_data_v_i[2],ufc_data_v_i[3]}),
        .\UFC_MESSAGE_START_Buffer_reg[1]_0 (ufc_filter_i_n_81),
        .\UFC_MESSAGE_START_Buffer_reg[1]_1 (ufc_filter_i_n_82),
        .neqOp(neqOp),
        .pdu_pad_i(pdu_pad_i),
        .\rx_data_v_r_reg[0]_0 (D),
        .\rx_scp_r_reg[0]_0 (\rx_scp_r_reg[0] ),
        .\rx_suf_r_reg[0]_0 ({\rx_suf_r_reg[0] [2:1],\rx_suf_r_reg[2] ,\rx_suf_r_reg[0] [0]}),
        .\stage_1_count_value_r_reg[0]_0 (\stage_1_count_value_r_reg[0] ),
        .\stage_1_count_value_r_reg[1]_0 (\stage_1_count_value_r_reg[1] ),
        .\stage_1_count_value_r_reg[2]_0 (\stage_1_count_value_r_reg[2] ),
        .\stage_1_count_value_r_reg[3]_0 (\stage_1_count_value_r_reg[3] ),
        .\stage_1_data_r_reg[0] (\stage_1_data_r_reg[0] ),
        .\stage_1_data_r_reg[11] (\stage_1_data_r_reg[11] ),
        .\stage_1_data_r_reg[16] (\stage_1_data_r_reg[16] ),
        .\stage_1_data_r_reg[24] (\stage_1_data_r_reg[24] ),
        .\stage_1_data_r_reg[25] (\stage_1_data_r_reg[25] ),
        .\stage_1_data_r_reg[26] (\stage_1_data_r_reg[26] ),
        .\stage_1_data_r_reg[32] (\stage_1_data_r_reg[32] ),
        .\stage_1_data_r_reg[40] (\stage_1_data_r_reg[40] ),
        .\stage_1_data_r_reg[41] (\stage_1_data_r_reg[41] ),
        .\stage_1_data_r_reg[42] (\stage_1_data_r_reg[42] ),
        .\stage_1_data_r_reg[43] (\stage_1_data_r_reg[43] ),
        .\stage_1_data_r_reg[48] (\stage_1_data_r_reg[48] ),
        .\stage_1_data_r_reg[56] (\stage_1_data_r_reg[56] ),
        .\stage_1_data_r_reg[57] (\stage_1_data_r_reg[57] ),
        .\stage_1_data_r_reg[58] (\stage_1_data_r_reg[58] ),
        .\stage_1_data_r_reg[59] (\stage_1_data_r_reg[59] ),
        .\stage_1_lane_mask_r_reg[1]_0 (\stage_1_lane_mask_r_reg[1] ),
        .\stage_1_lane_mask_r_reg[2]_0 (\stage_1_lane_mask_r_reg[2] ),
        .\stage_1_lane_mask_r_reg[3]_0 (\stage_1_lane_mask_r_reg[3] ),
        .std_bool26_out(std_bool26_out),
        .std_bool26_out_0(std_bool26_out_0),
        .std_bool26_out_1(std_bool26_out_1),
        .std_bool26_out_2(std_bool26_out_2),
        .ufc_start_i(ufc_start_i),
        .user_clk(user_clk),
        .\word_aligned_data_r_reg[0] (ufc_filter_i_n_37),
        .\word_aligned_data_r_reg[0]_0 (ufc_filter_i_n_38),
        .\word_aligned_data_r_reg[0]_1 (ufc_filter_i_n_39),
        .\word_aligned_data_r_reg[0]_2 (ufc_filter_i_n_40),
        .\word_aligned_data_r_reg[11] (ufc_filter_i_n_57),
        .\word_aligned_data_r_reg[11]_0 (ufc_filter_i_n_58),
        .\word_aligned_data_r_reg[11]_1 (ufc_filter_i_n_59),
        .\word_aligned_data_r_reg[11]_2 (ufc_filter_i_n_60),
        .\word_aligned_data_r_reg[12] (ufc_filter_i_n_53),
        .\word_aligned_data_r_reg[12]_0 (ufc_filter_i_n_54),
        .\word_aligned_data_r_reg[12]_1 (ufc_filter_i_n_55),
        .\word_aligned_data_r_reg[12]_2 (ufc_filter_i_n_56),
        .\word_aligned_data_r_reg[13] (ufc_filter_i_n_49),
        .\word_aligned_data_r_reg[13]_0 (ufc_filter_i_n_50),
        .\word_aligned_data_r_reg[13]_1 (ufc_filter_i_n_51),
        .\word_aligned_data_r_reg[13]_2 (ufc_filter_i_n_52),
        .\word_aligned_data_r_reg[14] (ufc_filter_i_n_45),
        .\word_aligned_data_r_reg[14]_0 (ufc_filter_i_n_46),
        .\word_aligned_data_r_reg[14]_1 (ufc_filter_i_n_47),
        .\word_aligned_data_r_reg[14]_2 (ufc_filter_i_n_48),
        .\word_aligned_data_r_reg[15] (ufc_filter_i_n_41),
        .\word_aligned_data_r_reg[15]_0 (ufc_filter_i_n_42),
        .\word_aligned_data_r_reg[15]_1 (ufc_filter_i_n_43),
        .\word_aligned_data_r_reg[15]_2 (ufc_filter_i_n_44),
        .\word_aligned_data_r_reg[1] (ufc_filter_i_n_33),
        .\word_aligned_data_r_reg[1]_0 (ufc_filter_i_n_34),
        .\word_aligned_data_r_reg[1]_1 (ufc_filter_i_n_35),
        .\word_aligned_data_r_reg[1]_2 (ufc_filter_i_n_36),
        .\word_aligned_data_r_reg[2] (ufc_filter_i_n_29),
        .\word_aligned_data_r_reg[2]_0 (ufc_filter_i_n_30),
        .\word_aligned_data_r_reg[2]_1 (ufc_filter_i_n_31),
        .\word_aligned_data_r_reg[2]_2 (ufc_filter_i_n_32),
        .\word_aligned_data_r_reg[3] (ufc_filter_i_n_25),
        .\word_aligned_data_r_reg[3]_0 (ufc_filter_i_n_26),
        .\word_aligned_data_r_reg[3]_1 (ufc_filter_i_n_27),
        .\word_aligned_data_r_reg[3]_2 (ufc_filter_i_n_28),
        .\word_aligned_data_r_reg[4] (ufc_filter_i_n_21),
        .\word_aligned_data_r_reg[4]_0 (ufc_filter_i_n_22),
        .\word_aligned_data_r_reg[4]_1 (ufc_filter_i_n_23),
        .\word_aligned_data_r_reg[4]_2 (ufc_filter_i_n_24),
        .\word_aligned_data_r_reg[5] (ufc_filter_i_n_17),
        .\word_aligned_data_r_reg[5]_0 (ufc_filter_i_n_18),
        .\word_aligned_data_r_reg[5]_1 (ufc_filter_i_n_19),
        .\word_aligned_data_r_reg[5]_2 (ufc_filter_i_n_20),
        .\word_aligned_data_r_reg[6] (ufc_filter_i_n_13),
        .\word_aligned_data_r_reg[6]_0 (ufc_filter_i_n_14),
        .\word_aligned_data_r_reg[6]_1 (ufc_filter_i_n_15),
        .\word_aligned_data_r_reg[6]_2 (ufc_filter_i_n_16),
        .\word_aligned_data_r_reg[7] (ufc_filter_i_n_9),
        .\word_aligned_data_r_reg[7]_0 (ufc_filter_i_n_10),
        .\word_aligned_data_r_reg[7]_1 (ufc_filter_i_n_11),
        .\word_aligned_data_r_reg[7]_2 (ufc_filter_i_n_12));
endmodule

module aurora_rx_4l_64b_RX_LL_DEFRAMER
   (D,
    \DEFRAMED_DATA_V_Buffer_reg[2]_0 ,
    \AFTER_SCP_Buffer_reg[3]_0 ,
    std_bool,
    \AFTER_SCP_Buffer_reg[3]_1 ,
    \stage_1_ecp_r_reg[3] ,
    in_frame_muxcy_0_0,
    Q,
    in_frame_muxcy_1_0,
    in_frame_muxcy_2_0,
    in_frame_muxcy_3_0,
    S5_in,
    S3_in,
    S1_in,
    data_after_start_muxcy_3_0,
    RESET,
    user_clk,
    stage_2_frame_err_r_reg,
    stage_2_frame_err_r_reg_0,
    \DEFRAMED_DATA_V_Buffer_reg[0]_0 );
  output [2:0]D;
  output [4:0]\DEFRAMED_DATA_V_Buffer_reg[2]_0 ;
  output \AFTER_SCP_Buffer_reg[3]_0 ;
  output std_bool;
  output \AFTER_SCP_Buffer_reg[3]_1 ;
  output \stage_1_ecp_r_reg[3] ;
  input in_frame_muxcy_0_0;
  input [3:0]Q;
  input in_frame_muxcy_1_0;
  input in_frame_muxcy_2_0;
  input in_frame_muxcy_3_0;
  input S5_in;
  input S3_in;
  input S1_in;
  input data_after_start_muxcy_3_0;
  input RESET;
  input user_clk;
  input [3:0]stage_2_frame_err_r_reg;
  input [3:0]stage_2_frame_err_r_reg_0;
  input [3:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;

  wire \AFTER_SCP_Buffer_reg[3]_0 ;
  wire \AFTER_SCP_Buffer_reg[3]_1 ;
  wire CI;
  wire [2:0]D;
  wire \DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ;
  wire \DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ;
  wire \DEFRAMED_DATA_V_Buffer[2]_i_1_n_0 ;
  wire \DEFRAMED_DATA_V_Buffer[3]_i_1_n_0 ;
  wire [3:0]\DEFRAMED_DATA_V_Buffer_reg[0]_0 ;
  wire [4:0]\DEFRAMED_DATA_V_Buffer_reg[2]_0 ;
  wire [3:0]Q;
  wire RESET;
  wire S1_in;
  wire S3_in;
  wire S5_in;
  wire after_scp_c_1;
  wire after_scp_c_2;
  wire after_scp_c_3;
  wire data_after_start_muxcy_3_0;
  wire data_after_start_muxcy_3_n_0;
  wire in_frame_c_0;
  wire in_frame_c_1;
  wire in_frame_c_2;
  wire in_frame_c_3;
  wire in_frame_muxcy_0_0;
  wire in_frame_muxcy_1_0;
  wire in_frame_muxcy_2_0;
  wire in_frame_muxcy_3_0;
  wire [0:3]stage_1_after_scp_r;
  wire [0:3]stage_1_data_v_r;
  wire \stage_1_ecp_r_reg[3] ;
  wire [0:3]stage_1_in_frame_r;
  wire stage_2_end_after_start_r_i_2_n_0;
  wire stage_2_end_before_start_r_i_2_n_0;
  wire stage_2_frame_err_r_i_2_n_0;
  wire stage_2_frame_err_r_i_3_n_0;
  wire [3:0]stage_2_frame_err_r_reg;
  wire [3:0]stage_2_frame_err_r_reg_0;
  wire stage_2_start_with_data_r_i_2_n_0;
  wire std_bool;
  wire user_clk;
  wire [3:0]NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED;
  wire [3:0]NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED;

  FDRE \AFTER_SCP_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(after_scp_c_3),
        .Q(stage_1_after_scp_r[0]),
        .R(RESET));
  FDRE \AFTER_SCP_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(after_scp_c_2),
        .Q(stage_1_after_scp_r[1]),
        .R(RESET));
  FDRE \AFTER_SCP_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(after_scp_c_1),
        .Q(stage_1_after_scp_r[2]),
        .R(RESET));
  FDRE \AFTER_SCP_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(data_after_start_muxcy_3_n_0),
        .Q(stage_1_after_scp_r[3]),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \COUNT_Buffer[0]_i_1 
       (.I0(stage_1_data_v_r[3]),
        .I1(stage_1_data_v_r[1]),
        .I2(stage_1_data_v_r[2]),
        .I3(stage_1_data_v_r[0]),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'h7EE8)) 
    \COUNT_Buffer[1]_i_1 
       (.I0(stage_1_data_v_r[3]),
        .I1(stage_1_data_v_r[1]),
        .I2(stage_1_data_v_r[2]),
        .I3(stage_1_data_v_r[0]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \COUNT_Buffer[2]_i_1 
       (.I0(stage_1_data_v_r[0]),
        .I1(stage_1_data_v_r[2]),
        .I2(stage_1_data_v_r[1]),
        .I3(stage_1_data_v_r[3]),
        .O(D[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \DEFRAMED_DATA_V_Buffer[0]_i_1 
       (.I0(in_frame_c_3),
        .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [3]),
        .O(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \DEFRAMED_DATA_V_Buffer[1]_i_1 
       (.I0(in_frame_c_2),
        .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [2]),
        .O(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \DEFRAMED_DATA_V_Buffer[2]_i_1 
       (.I0(in_frame_c_1),
        .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [1]),
        .O(\DEFRAMED_DATA_V_Buffer[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \DEFRAMED_DATA_V_Buffer[3]_i_1 
       (.I0(in_frame_c_0),
        .I1(\DEFRAMED_DATA_V_Buffer_reg[0]_0 [0]),
        .O(\DEFRAMED_DATA_V_Buffer[3]_i_1_n_0 ));
  FDRE \DEFRAMED_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\DEFRAMED_DATA_V_Buffer[0]_i_1_n_0 ),
        .Q(stage_1_data_v_r[0]),
        .R(RESET));
  FDRE \DEFRAMED_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\DEFRAMED_DATA_V_Buffer[1]_i_1_n_0 ),
        .Q(stage_1_data_v_r[1]),
        .R(RESET));
  FDRE \DEFRAMED_DATA_V_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\DEFRAMED_DATA_V_Buffer[2]_i_1_n_0 ),
        .Q(stage_1_data_v_r[2]),
        .R(RESET));
  FDRE \DEFRAMED_DATA_V_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\DEFRAMED_DATA_V_Buffer[3]_i_1_n_0 ),
        .Q(stage_1_data_v_r[3]),
        .R(RESET));
  FDRE \IN_FRAME_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(CI),
        .Q(stage_1_in_frame_r[0]),
        .R(RESET));
  FDRE \IN_FRAME_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(in_frame_c_3),
        .Q(stage_1_in_frame_r[1]),
        .R(RESET));
  FDRE \IN_FRAME_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(in_frame_c_2),
        .Q(stage_1_in_frame_r[2]),
        .R(RESET));
  FDRE \IN_FRAME_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(in_frame_c_1),
        .Q(stage_1_in_frame_r[3]),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT4 #(
    .INIT(16'h000E)) 
    \MUX_SELECT_Buffer[1]_i_1 
       (.I0(stage_1_data_v_r[2]),
        .I1(stage_1_data_v_r[3]),
        .I2(stage_1_data_v_r[0]),
        .I3(stage_1_data_v_r[1]),
        .O(\DEFRAMED_DATA_V_Buffer_reg[2]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT4 #(
    .INIT(16'h5504)) 
    \MUX_SELECT_Buffer[2]_i_1 
       (.I0(stage_1_data_v_r[0]),
        .I1(stage_1_data_v_r[3]),
        .I2(stage_1_data_v_r[2]),
        .I3(stage_1_data_v_r[1]),
        .O(\DEFRAMED_DATA_V_Buffer_reg[2]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT4 #(
    .INIT(16'h1060)) 
    \MUX_SELECT_Buffer[4]_i_1 
       (.I0(stage_1_data_v_r[1]),
        .I1(stage_1_data_v_r[0]),
        .I2(stage_1_data_v_r[3]),
        .I3(stage_1_data_v_r[2]),
        .O(\DEFRAMED_DATA_V_Buffer_reg[2]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \MUX_SELECT_Buffer[5]_i_1 
       (.I0(stage_1_data_v_r[0]),
        .I1(stage_1_data_v_r[1]),
        .I2(stage_1_data_v_r[2]),
        .O(\DEFRAMED_DATA_V_Buffer_reg[2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT4 #(
    .INIT(16'h6800)) 
    \MUX_SELECT_Buffer[8]_i_1 
       (.I0(stage_1_data_v_r[0]),
        .I1(stage_1_data_v_r[1]),
        .I2(stage_1_data_v_r[2]),
        .I3(stage_1_data_v_r[3]),
        .O(\DEFRAMED_DATA_V_Buffer_reg[2]_0 [0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  CARRY4 data_after_start_muxcy_0_CARRY4
       (.CI(1'b0),
        .CO({data_after_start_muxcy_3_n_0,after_scp_c_1,after_scp_c_2,after_scp_c_3}),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O(NLW_data_after_start_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
        .S({data_after_start_muxcy_3_0,S1_in,S3_in,S5_in}));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  CARRY4 in_frame_muxcy_0_CARRY4
       (.CI(1'b0),
        .CO({in_frame_c_0,in_frame_c_1,in_frame_c_2,in_frame_c_3}),
        .CYINIT(CI),
        .DI({Q[0],Q[1],Q[2],Q[3]}),
        .O(NLW_in_frame_muxcy_0_CARRY4_O_UNCONNECTED[3:0]),
        .S({in_frame_muxcy_3_0,in_frame_muxcy_2_0,in_frame_muxcy_1_0,in_frame_muxcy_0_0}));
  FDRE in_frame_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(in_frame_c_0),
        .Q(CI),
        .R(RESET));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    stage_2_end_after_start_r_i_1
       (.I0(stage_1_after_scp_r[3]),
        .I1(stage_2_frame_err_r_reg_0[0]),
        .I2(stage_1_after_scp_r[2]),
        .I3(stage_2_frame_err_r_reg_0[1]),
        .I4(stage_2_end_after_start_r_i_2_n_0),
        .O(\AFTER_SCP_Buffer_reg[3]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    stage_2_end_after_start_r_i_2
       (.I0(stage_2_frame_err_r_reg_0[2]),
        .I1(stage_1_after_scp_r[1]),
        .I2(stage_2_frame_err_r_reg_0[3]),
        .I3(stage_1_after_scp_r[0]),
        .O(stage_2_end_after_start_r_i_2_n_0));
  LUT5 #(
    .INIT(32'hFFFF22F2)) 
    stage_2_end_before_start_r_i_1
       (.I0(stage_2_frame_err_r_reg_0[0]),
        .I1(stage_1_after_scp_r[3]),
        .I2(stage_2_frame_err_r_reg_0[1]),
        .I3(stage_1_after_scp_r[2]),
        .I4(stage_2_end_before_start_r_i_2_n_0),
        .O(std_bool));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'h4F44)) 
    stage_2_end_before_start_r_i_2
       (.I0(stage_1_after_scp_r[1]),
        .I1(stage_2_frame_err_r_reg_0[2]),
        .I2(stage_1_after_scp_r[0]),
        .I3(stage_2_frame_err_r_reg_0[3]),
        .O(stage_2_end_before_start_r_i_2_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    stage_2_frame_err_r_i_1
       (.I0(stage_2_frame_err_r_i_2_n_0),
        .I1(stage_2_frame_err_r_i_3_n_0),
        .O(\stage_1_ecp_r_reg[3] ));
  LUT6 #(
    .INIT(64'hFFFFFFE2E2E2FFE2)) 
    stage_2_frame_err_r_i_2
       (.I0(stage_2_frame_err_r_reg_0[0]),
        .I1(stage_1_in_frame_r[3]),
        .I2(stage_2_frame_err_r_reg[0]),
        .I3(stage_2_frame_err_r_reg_0[1]),
        .I4(stage_1_in_frame_r[2]),
        .I5(stage_2_frame_err_r_reg[1]),
        .O(stage_2_frame_err_r_i_2_n_0));
  LUT6 #(
    .INIT(64'hEEFAEEFAFFFFCCF0)) 
    stage_2_frame_err_r_i_3
       (.I0(stage_2_frame_err_r_reg[3]),
        .I1(stage_2_frame_err_r_reg[2]),
        .I2(stage_2_frame_err_r_reg_0[2]),
        .I3(stage_1_in_frame_r[1]),
        .I4(stage_2_frame_err_r_reg_0[3]),
        .I5(stage_1_in_frame_r[0]),
        .O(stage_2_frame_err_r_i_3_n_0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    stage_2_start_with_data_r_i_1
       (.I0(stage_1_after_scp_r[3]),
        .I1(stage_1_data_v_r[3]),
        .I2(stage_1_after_scp_r[2]),
        .I3(stage_1_data_v_r[2]),
        .I4(stage_2_start_with_data_r_i_2_n_0),
        .O(\AFTER_SCP_Buffer_reg[3]_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    stage_2_start_with_data_r_i_2
       (.I0(stage_1_data_v_r[0]),
        .I1(stage_1_after_scp_r[0]),
        .I2(stage_1_data_v_r[1]),
        .I3(stage_1_after_scp_r[1]),
        .O(stage_2_start_with_data_r_i_2_n_0));
endmodule

module aurora_rx_4l_64b_RX_LL_PDU_DATAPATH
   (RX_EOF_N,
    FRAME_ERR,
    M_AXI_RX_TLAST,
    M_AXI_RX_TVALID,
    \RX_REM_Buffer_reg[0]_0 ,
    M_AXI_RX_TDATA,
    in_frame_muxcy_0,
    Q,
    in_frame_muxcy_1,
    in_frame_muxcy_2,
    in_frame_muxcy_3,
    S5_in,
    S3_in,
    S1_in,
    data_after_start_muxcy_3,
    RESET,
    user_clk,
    pdu_pad_i,
    start_rx_i,
    \DEFRAMED_DATA_V_Buffer_reg[0] ,
    D,
    \stage_2_data_r_reg[0]_0 );
  output RX_EOF_N;
  output FRAME_ERR;
  output M_AXI_RX_TLAST;
  output M_AXI_RX_TVALID;
  output [2:0]\RX_REM_Buffer_reg[0]_0 ;
  output [63:0]M_AXI_RX_TDATA;
  input in_frame_muxcy_0;
  input [3:0]Q;
  input in_frame_muxcy_1;
  input in_frame_muxcy_2;
  input in_frame_muxcy_3;
  input S5_in;
  input S3_in;
  input S1_in;
  input data_after_start_muxcy_3;
  input RESET;
  input user_clk;
  input [0:3]pdu_pad_i;
  input start_rx_i;
  input [3:0]\DEFRAMED_DATA_V_Buffer_reg[0] ;
  input [3:0]D;
  input [63:0]\stage_2_data_r_reg[0]_0 ;

  wire [3:0]D;
  wire [3:0]\DEFRAMED_DATA_V_Buffer_reg[0] ;
  wire EOF_N_Buffer;
  wire FRAME_ERR;
  wire FRAME_ERR_RESULT_Buffer;
  wire FRAME_ERR_RESULT_Buffer0;
  wire [1:3]L__0;
  wire [63:0]M_AXI_RX_TDATA;
  wire M_AXI_RX_TLAST;
  wire M_AXI_RX_TVALID;
  wire [13:19]OUTPUT_SELECT_Buffer;
  wire [3:0]Q;
  wire RESET;
  wire RX_EOF_N;
  wire [0:2]RX_REM_Buffer;
  wire [2:0]\RX_REM_Buffer_reg[0]_0 ;
  wire S1_in;
  wire S3_in;
  wire S5_in;
  wire SRC_RDY_N_Buffer;
  wire [0:63]STORAGE_DATA;
  wire \STORAGE_DATA_Buffer[0]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[10]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[11]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[12]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[13]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[14]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[15]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[16]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[17]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[18]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[19]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[1]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[20]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[21]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[22]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[23]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[24]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[25]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[26]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[27]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[28]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[29]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[2]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[30]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[31]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[32]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[33]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[34]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[35]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[36]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[37]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[38]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[39]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[3]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[40]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[41]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[42]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[43]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[44]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[45]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[46]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[47]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[48]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[49]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[4]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[50]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[51]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[52]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[53]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[54]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[55]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[56]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[57]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[58]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[59]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[5]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[60]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[61]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[62]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[63]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[6]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[7]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[8]_i_1_n_0 ;
  wire \STORAGE_DATA_Buffer[9]_i_1_n_0 ;
  wire [3:19]STORAGE_SELECT_Buffer;
  wire [0:2]ce_command_c;
  wire data_after_start_muxcy_3;
  wire end_storage_r0;
  wire in_frame_muxcy_0;
  wire in_frame_muxcy_1;
  wire in_frame_muxcy_2;
  wire in_frame_muxcy_3;
  wire [1:4]mux_select_c;
  wire \neqOp_inferred__0/i__n_0 ;
  wire [13:18]output_select_c;
  wire p_0_in0;
  wire [15:0]p_1_in;
  wire [15:0]p_3_in;
  wire [15:0]p_5_in;
  wire [0:3]pdu_pad_i;
  wire [2:1]plusOp;
  wire [2:2]rx_rem_c;
  wire rx_src_rdy;
  wire sideband_output_i_n_1;
  wire [0:3]stage_1_ecp_r;
  wire stage_1_pad_r;
  wire stage_1_rx_ll_deframer_i_n_10;
  wire stage_1_rx_ll_deframer_i_n_11;
  wire stage_1_rx_ll_deframer_i_n_2;
  wire stage_1_rx_ll_deframer_i_n_4;
  wire stage_1_rx_ll_deframer_i_n_6;
  wire stage_1_rx_ll_deframer_i_n_7;
  wire stage_1_rx_ll_deframer_i_n_8;
  wire [0:3]stage_1_scp_r;
  wire [63:0]\stage_2_data_r_reg[0]_0 ;
  wire \stage_2_data_r_reg_n_0_[0] ;
  wire \stage_2_data_r_reg_n_0_[10] ;
  wire \stage_2_data_r_reg_n_0_[11] ;
  wire \stage_2_data_r_reg_n_0_[12] ;
  wire \stage_2_data_r_reg_n_0_[13] ;
  wire \stage_2_data_r_reg_n_0_[14] ;
  wire \stage_2_data_r_reg_n_0_[15] ;
  wire \stage_2_data_r_reg_n_0_[1] ;
  wire \stage_2_data_r_reg_n_0_[2] ;
  wire \stage_2_data_r_reg_n_0_[3] ;
  wire \stage_2_data_r_reg_n_0_[48] ;
  wire \stage_2_data_r_reg_n_0_[49] ;
  wire \stage_2_data_r_reg_n_0_[4] ;
  wire \stage_2_data_r_reg_n_0_[50] ;
  wire \stage_2_data_r_reg_n_0_[51] ;
  wire \stage_2_data_r_reg_n_0_[52] ;
  wire \stage_2_data_r_reg_n_0_[53] ;
  wire \stage_2_data_r_reg_n_0_[54] ;
  wire \stage_2_data_r_reg_n_0_[55] ;
  wire \stage_2_data_r_reg_n_0_[56] ;
  wire \stage_2_data_r_reg_n_0_[57] ;
  wire \stage_2_data_r_reg_n_0_[58] ;
  wire \stage_2_data_r_reg_n_0_[59] ;
  wire \stage_2_data_r_reg_n_0_[5] ;
  wire \stage_2_data_r_reg_n_0_[60] ;
  wire \stage_2_data_r_reg_n_0_[61] ;
  wire \stage_2_data_r_reg_n_0_[62] ;
  wire \stage_2_data_r_reg_n_0_[63] ;
  wire \stage_2_data_r_reg_n_0_[6] ;
  wire \stage_2_data_r_reg_n_0_[7] ;
  wire \stage_2_data_r_reg_n_0_[8] ;
  wire \stage_2_data_r_reg_n_0_[9] ;
  wire stage_2_end_after_start_r;
  wire stage_2_end_before_start_r;
  wire stage_2_frame_err_r;
  wire stage_2_left_align_control_i_n_0;
  wire stage_2_left_align_control_i_n_1;
  wire stage_2_left_align_control_i_n_2;
  wire stage_2_left_align_control_i_n_3;
  wire stage_2_left_align_control_i_n_4;
  wire stage_2_pad_r;
  wire stage_2_start_with_data_r;
  wire stage_3_end_storage_r;
  wire stage_3_left_align_datapath_mux_i_n_0;
  wire stage_3_left_align_datapath_mux_i_n_1;
  wire stage_3_left_align_datapath_mux_i_n_10;
  wire stage_3_left_align_datapath_mux_i_n_11;
  wire stage_3_left_align_datapath_mux_i_n_12;
  wire stage_3_left_align_datapath_mux_i_n_13;
  wire stage_3_left_align_datapath_mux_i_n_14;
  wire stage_3_left_align_datapath_mux_i_n_15;
  wire stage_3_left_align_datapath_mux_i_n_16;
  wire stage_3_left_align_datapath_mux_i_n_17;
  wire stage_3_left_align_datapath_mux_i_n_18;
  wire stage_3_left_align_datapath_mux_i_n_19;
  wire stage_3_left_align_datapath_mux_i_n_2;
  wire stage_3_left_align_datapath_mux_i_n_20;
  wire stage_3_left_align_datapath_mux_i_n_21;
  wire stage_3_left_align_datapath_mux_i_n_22;
  wire stage_3_left_align_datapath_mux_i_n_23;
  wire stage_3_left_align_datapath_mux_i_n_24;
  wire stage_3_left_align_datapath_mux_i_n_25;
  wire stage_3_left_align_datapath_mux_i_n_26;
  wire stage_3_left_align_datapath_mux_i_n_27;
  wire stage_3_left_align_datapath_mux_i_n_28;
  wire stage_3_left_align_datapath_mux_i_n_29;
  wire stage_3_left_align_datapath_mux_i_n_3;
  wire stage_3_left_align_datapath_mux_i_n_30;
  wire stage_3_left_align_datapath_mux_i_n_31;
  wire stage_3_left_align_datapath_mux_i_n_4;
  wire stage_3_left_align_datapath_mux_i_n_48;
  wire stage_3_left_align_datapath_mux_i_n_49;
  wire stage_3_left_align_datapath_mux_i_n_5;
  wire stage_3_left_align_datapath_mux_i_n_50;
  wire stage_3_left_align_datapath_mux_i_n_51;
  wire stage_3_left_align_datapath_mux_i_n_52;
  wire stage_3_left_align_datapath_mux_i_n_53;
  wire stage_3_left_align_datapath_mux_i_n_54;
  wire stage_3_left_align_datapath_mux_i_n_55;
  wire stage_3_left_align_datapath_mux_i_n_56;
  wire stage_3_left_align_datapath_mux_i_n_57;
  wire stage_3_left_align_datapath_mux_i_n_58;
  wire stage_3_left_align_datapath_mux_i_n_59;
  wire stage_3_left_align_datapath_mux_i_n_6;
  wire stage_3_left_align_datapath_mux_i_n_60;
  wire stage_3_left_align_datapath_mux_i_n_61;
  wire stage_3_left_align_datapath_mux_i_n_62;
  wire stage_3_left_align_datapath_mux_i_n_63;
  wire stage_3_left_align_datapath_mux_i_n_7;
  wire stage_3_left_align_datapath_mux_i_n_8;
  wire stage_3_left_align_datapath_mux_i_n_9;
  wire stage_3_storage_ce_control_i_n_0;
  wire stage_3_storage_ce_control_i_n_1;
  wire stage_3_storage_ce_control_i_n_3;
  wire stage_3_storage_count_control_i_n_1;
  wire stage_3_storage_count_control_i_n_10;
  wire stage_3_storage_count_control_i_n_11;
  wire stage_3_storage_count_control_i_n_12;
  wire stage_3_storage_count_control_i_n_13;
  wire stage_3_storage_count_control_i_n_14;
  wire stage_3_storage_count_control_i_n_3;
  wire stage_3_storage_count_control_i_n_6;
  wire [1:2]stage_3_storage_count_r;
  wire start_rx_i;
  wire std_bool;
  wire [1:2]storage_count_c;
  wire take_storage_c;
  wire user_clk;

  FDRE FRAME_ERR_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(FRAME_ERR_RESULT_Buffer),
        .Q(FRAME_ERR),
        .R(RESET));
  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_RX_TLAST_INST_0
       (.I0(RX_EOF_N),
        .O(M_AXI_RX_TLAST));
  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_RX_TVALID_INST_0
       (.I0(rx_src_rdy),
        .O(M_AXI_RX_TVALID));
  FDRE RX_EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(EOF_N_Buffer),
        .Q(RX_EOF_N),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_REM_Buffer[0]),
        .Q(\RX_REM_Buffer_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_REM_Buffer[1]),
        .Q(\RX_REM_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_REM_Buffer[2]),
        .Q(\RX_REM_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDSE RX_SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(SRC_RDY_N_Buffer),
        .Q(rx_src_rdy),
        .S(RESET));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[0]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_16),
        .I1(stage_3_left_align_datapath_mux_i_n_0),
        .I2(stage_3_left_align_datapath_mux_i_n_48),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[15]),
        .O(\STORAGE_DATA_Buffer[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[10]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_26),
        .I1(stage_3_left_align_datapath_mux_i_n_10),
        .I2(stage_3_left_align_datapath_mux_i_n_58),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[5]),
        .O(\STORAGE_DATA_Buffer[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[11]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_27),
        .I1(stage_3_left_align_datapath_mux_i_n_11),
        .I2(stage_3_left_align_datapath_mux_i_n_59),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[4]),
        .O(\STORAGE_DATA_Buffer[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[12]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_28),
        .I1(stage_3_left_align_datapath_mux_i_n_12),
        .I2(stage_3_left_align_datapath_mux_i_n_60),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[3]),
        .O(\STORAGE_DATA_Buffer[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[13]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_29),
        .I1(stage_3_left_align_datapath_mux_i_n_13),
        .I2(stage_3_left_align_datapath_mux_i_n_61),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[2]),
        .O(\STORAGE_DATA_Buffer[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[14]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_30),
        .I1(stage_3_left_align_datapath_mux_i_n_14),
        .I2(stage_3_left_align_datapath_mux_i_n_62),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[1]),
        .O(\STORAGE_DATA_Buffer[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[15]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_31),
        .I1(stage_3_left_align_datapath_mux_i_n_15),
        .I2(stage_3_left_align_datapath_mux_i_n_63),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[0]),
        .O(\STORAGE_DATA_Buffer[15]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[16]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_16),
        .I1(stage_3_left_align_datapath_mux_i_n_0),
        .I2(stage_3_left_align_datapath_mux_i_n_48),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[15]),
        .O(\STORAGE_DATA_Buffer[16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[17]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_17),
        .I1(stage_3_left_align_datapath_mux_i_n_1),
        .I2(stage_3_left_align_datapath_mux_i_n_49),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[14]),
        .O(\STORAGE_DATA_Buffer[17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[18]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_18),
        .I1(stage_3_left_align_datapath_mux_i_n_2),
        .I2(stage_3_left_align_datapath_mux_i_n_50),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[13]),
        .O(\STORAGE_DATA_Buffer[18]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[19]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_19),
        .I1(stage_3_left_align_datapath_mux_i_n_3),
        .I2(stage_3_left_align_datapath_mux_i_n_51),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[12]),
        .O(\STORAGE_DATA_Buffer[19]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[1]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_17),
        .I1(stage_3_left_align_datapath_mux_i_n_1),
        .I2(stage_3_left_align_datapath_mux_i_n_49),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[14]),
        .O(\STORAGE_DATA_Buffer[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[20]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_20),
        .I1(stage_3_left_align_datapath_mux_i_n_4),
        .I2(stage_3_left_align_datapath_mux_i_n_52),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[11]),
        .O(\STORAGE_DATA_Buffer[20]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[21]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_21),
        .I1(stage_3_left_align_datapath_mux_i_n_5),
        .I2(stage_3_left_align_datapath_mux_i_n_53),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[10]),
        .O(\STORAGE_DATA_Buffer[21]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[22]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_22),
        .I1(stage_3_left_align_datapath_mux_i_n_6),
        .I2(stage_3_left_align_datapath_mux_i_n_54),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[9]),
        .O(\STORAGE_DATA_Buffer[22]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[23]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_23),
        .I1(stage_3_left_align_datapath_mux_i_n_7),
        .I2(stage_3_left_align_datapath_mux_i_n_55),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[8]),
        .O(\STORAGE_DATA_Buffer[23]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[24]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_24),
        .I1(stage_3_left_align_datapath_mux_i_n_8),
        .I2(stage_3_left_align_datapath_mux_i_n_56),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[7]),
        .O(\STORAGE_DATA_Buffer[24]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[25]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_25),
        .I1(stage_3_left_align_datapath_mux_i_n_9),
        .I2(stage_3_left_align_datapath_mux_i_n_57),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[6]),
        .O(\STORAGE_DATA_Buffer[25]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[26]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_26),
        .I1(stage_3_left_align_datapath_mux_i_n_10),
        .I2(stage_3_left_align_datapath_mux_i_n_58),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[5]),
        .O(\STORAGE_DATA_Buffer[26]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[27]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_27),
        .I1(stage_3_left_align_datapath_mux_i_n_11),
        .I2(stage_3_left_align_datapath_mux_i_n_59),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[4]),
        .O(\STORAGE_DATA_Buffer[27]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[28]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_28),
        .I1(stage_3_left_align_datapath_mux_i_n_12),
        .I2(stage_3_left_align_datapath_mux_i_n_60),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[3]),
        .O(\STORAGE_DATA_Buffer[28]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[29]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_29),
        .I1(stage_3_left_align_datapath_mux_i_n_13),
        .I2(stage_3_left_align_datapath_mux_i_n_61),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[2]),
        .O(\STORAGE_DATA_Buffer[29]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[2]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_18),
        .I1(stage_3_left_align_datapath_mux_i_n_2),
        .I2(stage_3_left_align_datapath_mux_i_n_50),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[13]),
        .O(\STORAGE_DATA_Buffer[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[30]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_30),
        .I1(stage_3_left_align_datapath_mux_i_n_14),
        .I2(stage_3_left_align_datapath_mux_i_n_62),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[1]),
        .O(\STORAGE_DATA_Buffer[30]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[31]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_31),
        .I1(stage_3_left_align_datapath_mux_i_n_15),
        .I2(stage_3_left_align_datapath_mux_i_n_63),
        .I3(STORAGE_SELECT_Buffer[8]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[0]),
        .O(\STORAGE_DATA_Buffer[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[32]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_16),
        .I1(stage_3_left_align_datapath_mux_i_n_0),
        .I2(stage_3_left_align_datapath_mux_i_n_48),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[15]),
        .O(\STORAGE_DATA_Buffer[32]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[33]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_17),
        .I1(stage_3_left_align_datapath_mux_i_n_1),
        .I2(stage_3_left_align_datapath_mux_i_n_49),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[14]),
        .O(\STORAGE_DATA_Buffer[33]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[34]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_18),
        .I1(stage_3_left_align_datapath_mux_i_n_2),
        .I2(stage_3_left_align_datapath_mux_i_n_50),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[13]),
        .O(\STORAGE_DATA_Buffer[34]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[35]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_19),
        .I1(stage_3_left_align_datapath_mux_i_n_3),
        .I2(stage_3_left_align_datapath_mux_i_n_51),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[12]),
        .O(\STORAGE_DATA_Buffer[35]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[36]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_20),
        .I1(stage_3_left_align_datapath_mux_i_n_4),
        .I2(stage_3_left_align_datapath_mux_i_n_52),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[11]),
        .O(\STORAGE_DATA_Buffer[36]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[37]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_21),
        .I1(stage_3_left_align_datapath_mux_i_n_5),
        .I2(stage_3_left_align_datapath_mux_i_n_53),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[10]),
        .O(\STORAGE_DATA_Buffer[37]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[38]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_22),
        .I1(stage_3_left_align_datapath_mux_i_n_6),
        .I2(stage_3_left_align_datapath_mux_i_n_54),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[9]),
        .O(\STORAGE_DATA_Buffer[38]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[39]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_23),
        .I1(stage_3_left_align_datapath_mux_i_n_7),
        .I2(stage_3_left_align_datapath_mux_i_n_55),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[8]),
        .O(\STORAGE_DATA_Buffer[39]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[3]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_19),
        .I1(stage_3_left_align_datapath_mux_i_n_3),
        .I2(stage_3_left_align_datapath_mux_i_n_51),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[12]),
        .O(\STORAGE_DATA_Buffer[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[40]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_24),
        .I1(stage_3_left_align_datapath_mux_i_n_8),
        .I2(stage_3_left_align_datapath_mux_i_n_56),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[7]),
        .O(\STORAGE_DATA_Buffer[40]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[41]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_25),
        .I1(stage_3_left_align_datapath_mux_i_n_9),
        .I2(stage_3_left_align_datapath_mux_i_n_57),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[6]),
        .O(\STORAGE_DATA_Buffer[41]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[42]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_26),
        .I1(stage_3_left_align_datapath_mux_i_n_10),
        .I2(stage_3_left_align_datapath_mux_i_n_58),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[5]),
        .O(\STORAGE_DATA_Buffer[42]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[43]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_27),
        .I1(stage_3_left_align_datapath_mux_i_n_11),
        .I2(stage_3_left_align_datapath_mux_i_n_59),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[4]),
        .O(\STORAGE_DATA_Buffer[43]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[44]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_28),
        .I1(stage_3_left_align_datapath_mux_i_n_12),
        .I2(stage_3_left_align_datapath_mux_i_n_60),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[3]),
        .O(\STORAGE_DATA_Buffer[44]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[45]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_29),
        .I1(stage_3_left_align_datapath_mux_i_n_13),
        .I2(stage_3_left_align_datapath_mux_i_n_61),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[2]),
        .O(\STORAGE_DATA_Buffer[45]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[46]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_30),
        .I1(stage_3_left_align_datapath_mux_i_n_14),
        .I2(stage_3_left_align_datapath_mux_i_n_62),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[1]),
        .O(\STORAGE_DATA_Buffer[46]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[47]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_31),
        .I1(stage_3_left_align_datapath_mux_i_n_15),
        .I2(stage_3_left_align_datapath_mux_i_n_63),
        .I3(STORAGE_SELECT_Buffer[13]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[0]),
        .O(\STORAGE_DATA_Buffer[47]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[48]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_16),
        .I1(stage_3_left_align_datapath_mux_i_n_0),
        .I2(stage_3_left_align_datapath_mux_i_n_48),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[15]),
        .O(\STORAGE_DATA_Buffer[48]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[49]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_17),
        .I1(stage_3_left_align_datapath_mux_i_n_1),
        .I2(stage_3_left_align_datapath_mux_i_n_49),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[14]),
        .O(\STORAGE_DATA_Buffer[49]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[4]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_20),
        .I1(stage_3_left_align_datapath_mux_i_n_4),
        .I2(stage_3_left_align_datapath_mux_i_n_52),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[11]),
        .O(\STORAGE_DATA_Buffer[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[50]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_18),
        .I1(stage_3_left_align_datapath_mux_i_n_2),
        .I2(stage_3_left_align_datapath_mux_i_n_50),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[13]),
        .O(\STORAGE_DATA_Buffer[50]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[51]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_19),
        .I1(stage_3_left_align_datapath_mux_i_n_3),
        .I2(stage_3_left_align_datapath_mux_i_n_51),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[12]),
        .O(\STORAGE_DATA_Buffer[51]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[52]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_20),
        .I1(stage_3_left_align_datapath_mux_i_n_4),
        .I2(stage_3_left_align_datapath_mux_i_n_52),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[11]),
        .O(\STORAGE_DATA_Buffer[52]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[53]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_21),
        .I1(stage_3_left_align_datapath_mux_i_n_5),
        .I2(stage_3_left_align_datapath_mux_i_n_53),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[10]),
        .O(\STORAGE_DATA_Buffer[53]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[54]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_22),
        .I1(stage_3_left_align_datapath_mux_i_n_6),
        .I2(stage_3_left_align_datapath_mux_i_n_54),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[9]),
        .O(\STORAGE_DATA_Buffer[54]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[55]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_23),
        .I1(stage_3_left_align_datapath_mux_i_n_7),
        .I2(stage_3_left_align_datapath_mux_i_n_55),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[8]),
        .O(\STORAGE_DATA_Buffer[55]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[56]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_24),
        .I1(stage_3_left_align_datapath_mux_i_n_8),
        .I2(stage_3_left_align_datapath_mux_i_n_56),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[7]),
        .O(\STORAGE_DATA_Buffer[56]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[57]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_25),
        .I1(stage_3_left_align_datapath_mux_i_n_9),
        .I2(stage_3_left_align_datapath_mux_i_n_57),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[6]),
        .O(\STORAGE_DATA_Buffer[57]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[58]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_26),
        .I1(stage_3_left_align_datapath_mux_i_n_10),
        .I2(stage_3_left_align_datapath_mux_i_n_58),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[5]),
        .O(\STORAGE_DATA_Buffer[58]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[59]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_27),
        .I1(stage_3_left_align_datapath_mux_i_n_11),
        .I2(stage_3_left_align_datapath_mux_i_n_59),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[4]),
        .O(\STORAGE_DATA_Buffer[59]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[5]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_21),
        .I1(stage_3_left_align_datapath_mux_i_n_5),
        .I2(stage_3_left_align_datapath_mux_i_n_53),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[10]),
        .O(\STORAGE_DATA_Buffer[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[60]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_28),
        .I1(stage_3_left_align_datapath_mux_i_n_12),
        .I2(stage_3_left_align_datapath_mux_i_n_60),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[3]),
        .O(\STORAGE_DATA_Buffer[60]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[61]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_29),
        .I1(stage_3_left_align_datapath_mux_i_n_13),
        .I2(stage_3_left_align_datapath_mux_i_n_61),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[2]),
        .O(\STORAGE_DATA_Buffer[61]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[62]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_30),
        .I1(stage_3_left_align_datapath_mux_i_n_14),
        .I2(stage_3_left_align_datapath_mux_i_n_62),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[1]),
        .O(\STORAGE_DATA_Buffer[62]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[63]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_31),
        .I1(stage_3_left_align_datapath_mux_i_n_15),
        .I2(stage_3_left_align_datapath_mux_i_n_63),
        .I3(STORAGE_SELECT_Buffer[18]),
        .I4(STORAGE_SELECT_Buffer[19]),
        .I5(p_1_in[0]),
        .O(\STORAGE_DATA_Buffer[63]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[6]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_22),
        .I1(stage_3_left_align_datapath_mux_i_n_6),
        .I2(stage_3_left_align_datapath_mux_i_n_54),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[9]),
        .O(\STORAGE_DATA_Buffer[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[7]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_23),
        .I1(stage_3_left_align_datapath_mux_i_n_7),
        .I2(stage_3_left_align_datapath_mux_i_n_55),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[8]),
        .O(\STORAGE_DATA_Buffer[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[8]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_24),
        .I1(stage_3_left_align_datapath_mux_i_n_8),
        .I2(stage_3_left_align_datapath_mux_i_n_56),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[7]),
        .O(\STORAGE_DATA_Buffer[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \STORAGE_DATA_Buffer[9]_i_1 
       (.I0(stage_3_left_align_datapath_mux_i_n_25),
        .I1(stage_3_left_align_datapath_mux_i_n_9),
        .I2(stage_3_left_align_datapath_mux_i_n_57),
        .I3(STORAGE_SELECT_Buffer[3]),
        .I4(OUTPUT_SELECT_Buffer[19]),
        .I5(p_1_in[6]),
        .O(\STORAGE_DATA_Buffer[9]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \neqOp_inferred__0/i_ 
       (.I0(pdu_pad_i[2]),
        .I1(pdu_pad_i[3]),
        .I2(pdu_pad_i[1]),
        .I3(pdu_pad_i[0]),
        .O(\neqOp_inferred__0/i__n_0 ));
  aurora_rx_4l_64b_OUTPUT_MUX output_mux_i
       (.M_AXI_RX_TDATA(M_AXI_RX_TDATA),
        .\OUTPUT_DATA_Buffer_reg[48]_0 ({stage_3_left_align_datapath_mux_i_n_0,stage_3_left_align_datapath_mux_i_n_1,stage_3_left_align_datapath_mux_i_n_2,stage_3_left_align_datapath_mux_i_n_3,stage_3_left_align_datapath_mux_i_n_4,stage_3_left_align_datapath_mux_i_n_5,stage_3_left_align_datapath_mux_i_n_6,stage_3_left_align_datapath_mux_i_n_7,stage_3_left_align_datapath_mux_i_n_8,stage_3_left_align_datapath_mux_i_n_9,stage_3_left_align_datapath_mux_i_n_10,stage_3_left_align_datapath_mux_i_n_11,stage_3_left_align_datapath_mux_i_n_12,stage_3_left_align_datapath_mux_i_n_13,stage_3_left_align_datapath_mux_i_n_14,stage_3_left_align_datapath_mux_i_n_15,stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,p_1_in}),
        .OUTPUT_SELECT_Buffer({OUTPUT_SELECT_Buffer[13],OUTPUT_SELECT_Buffer[14],OUTPUT_SELECT_Buffer[18],OUTPUT_SELECT_Buffer[19]}),
        .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31],STORAGE_DATA[32],STORAGE_DATA[33],STORAGE_DATA[34],STORAGE_DATA[35],STORAGE_DATA[36],STORAGE_DATA[37],STORAGE_DATA[38],STORAGE_DATA[39],STORAGE_DATA[40],STORAGE_DATA[41],STORAGE_DATA[42],STORAGE_DATA[43],STORAGE_DATA[44],STORAGE_DATA[45],STORAGE_DATA[46],STORAGE_DATA[47],STORAGE_DATA[48],STORAGE_DATA[49],STORAGE_DATA[50],STORAGE_DATA[51],STORAGE_DATA[52],STORAGE_DATA[53],STORAGE_DATA[54],STORAGE_DATA[55],STORAGE_DATA[56],STORAGE_DATA[57],STORAGE_DATA[58],STORAGE_DATA[59],STORAGE_DATA[60],STORAGE_DATA[61],STORAGE_DATA[62],STORAGE_DATA[63]}),
        .user_clk(user_clk));
  aurora_rx_4l_64b_SIDEBAND_OUTPUT sideband_output_i
       (.D(rx_rem_c),
        .EOF_N_Buffer(EOF_N_Buffer),
        .EOF_N_Buffer_reg_0(stage_3_storage_count_control_i_n_14),
        .FRAME_ERR_RESULT_Buffer(FRAME_ERR_RESULT_Buffer),
        .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
        .Q(L__0[3]),
        .\RX_REM_Buffer_reg[0]_0 ({RX_REM_Buffer[0],RX_REM_Buffer[1],RX_REM_Buffer[2]}),
        .\RX_REM_Buffer_reg[1]_0 (stage_3_storage_count_r[2]),
        .SR(take_storage_c),
        .SRC_RDY_N_Buffer(SRC_RDY_N_Buffer),
        .end_storage_r0(end_storage_r0),
        .pad_storage_r_reg_0(stage_3_storage_count_control_i_n_6),
        .stage_2_end_before_start_r(stage_2_end_before_start_r),
        .stage_2_frame_err_r(stage_2_frame_err_r),
        .stage_2_frame_err_r_reg(sideband_output_i_n_1),
        .stage_2_pad_r(stage_2_pad_r),
        .stage_2_start_with_data_r(stage_2_start_with_data_r),
        .stage_2_start_with_data_r_reg(storage_count_c[2]),
        .stage_3_end_storage_r(stage_3_end_storage_r),
        .start_rx_i(start_rx_i),
        .user_clk(user_clk));
  FDRE \stage_1_ecp_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(stage_1_ecp_r[0]),
        .R(1'b0));
  FDRE \stage_1_ecp_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(stage_1_ecp_r[1]),
        .R(1'b0));
  FDRE \stage_1_ecp_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(stage_1_ecp_r[2]),
        .R(1'b0));
  FDRE \stage_1_ecp_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(stage_1_ecp_r[3]),
        .R(1'b0));
  FDRE stage_1_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\neqOp_inferred__0/i__n_0 ),
        .Q(stage_1_pad_r),
        .R(1'b0));
  aurora_rx_4l_64b_RX_LL_DEFRAMER stage_1_rx_ll_deframer_i
       (.\AFTER_SCP_Buffer_reg[3]_0 (stage_1_rx_ll_deframer_i_n_8),
        .\AFTER_SCP_Buffer_reg[3]_1 (stage_1_rx_ll_deframer_i_n_10),
        .D({plusOp,stage_1_rx_ll_deframer_i_n_2}),
        .\DEFRAMED_DATA_V_Buffer_reg[0]_0 (\DEFRAMED_DATA_V_Buffer_reg[0] ),
        .\DEFRAMED_DATA_V_Buffer_reg[2]_0 ({mux_select_c[1],stage_1_rx_ll_deframer_i_n_4,mux_select_c[4],stage_1_rx_ll_deframer_i_n_6,stage_1_rx_ll_deframer_i_n_7}),
        .Q(Q),
        .RESET(RESET),
        .S1_in(S1_in),
        .S3_in(S3_in),
        .S5_in(S5_in),
        .data_after_start_muxcy_3_0(data_after_start_muxcy_3),
        .in_frame_muxcy_0_0(in_frame_muxcy_0),
        .in_frame_muxcy_1_0(in_frame_muxcy_1),
        .in_frame_muxcy_2_0(in_frame_muxcy_2),
        .in_frame_muxcy_3_0(in_frame_muxcy_3),
        .\stage_1_ecp_r_reg[3] (stage_1_rx_ll_deframer_i_n_11),
        .stage_2_frame_err_r_reg({stage_1_scp_r[0],stage_1_scp_r[1],stage_1_scp_r[2],stage_1_scp_r[3]}),
        .stage_2_frame_err_r_reg_0({stage_1_ecp_r[0],stage_1_ecp_r[1],stage_1_ecp_r[2],stage_1_ecp_r[3]}),
        .std_bool(std_bool),
        .user_clk(user_clk));
  FDRE \stage_1_scp_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[3]),
        .Q(stage_1_scp_r[0]),
        .R(1'b0));
  FDRE \stage_1_scp_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[2]),
        .Q(stage_1_scp_r[1]),
        .R(1'b0));
  FDRE \stage_1_scp_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[1]),
        .Q(stage_1_scp_r[2]),
        .R(1'b0));
  FDRE \stage_1_scp_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(Q[0]),
        .Q(stage_1_scp_r[3]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [63]),
        .Q(\stage_2_data_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [53]),
        .Q(\stage_2_data_r_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [52]),
        .Q(\stage_2_data_r_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [51]),
        .Q(\stage_2_data_r_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [50]),
        .Q(\stage_2_data_r_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [49]),
        .Q(\stage_2_data_r_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [48]),
        .Q(\stage_2_data_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [47]),
        .Q(p_5_in[15]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [46]),
        .Q(p_5_in[14]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [45]),
        .Q(p_5_in[13]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [44]),
        .Q(p_5_in[12]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [62]),
        .Q(\stage_2_data_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [43]),
        .Q(p_5_in[11]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [42]),
        .Q(p_5_in[10]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [41]),
        .Q(p_5_in[9]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [40]),
        .Q(p_5_in[8]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [39]),
        .Q(p_5_in[7]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [38]),
        .Q(p_5_in[6]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [37]),
        .Q(p_5_in[5]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [36]),
        .Q(p_5_in[4]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [35]),
        .Q(p_5_in[3]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [34]),
        .Q(p_5_in[2]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [61]),
        .Q(\stage_2_data_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [33]),
        .Q(p_5_in[1]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [32]),
        .Q(p_5_in[0]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [31]),
        .Q(p_3_in[15]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [30]),
        .Q(p_3_in[14]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [29]),
        .Q(p_3_in[13]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [28]),
        .Q(p_3_in[12]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [27]),
        .Q(p_3_in[11]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [26]),
        .Q(p_3_in[10]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [25]),
        .Q(p_3_in[9]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [24]),
        .Q(p_3_in[8]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [60]),
        .Q(\stage_2_data_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [23]),
        .Q(p_3_in[7]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [22]),
        .Q(p_3_in[6]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [21]),
        .Q(p_3_in[5]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [20]),
        .Q(p_3_in[4]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [19]),
        .Q(p_3_in[3]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [18]),
        .Q(p_3_in[2]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [17]),
        .Q(p_3_in[1]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [16]),
        .Q(p_3_in[0]),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [15]),
        .Q(\stage_2_data_r_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [14]),
        .Q(\stage_2_data_r_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [59]),
        .Q(\stage_2_data_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [13]),
        .Q(\stage_2_data_r_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [12]),
        .Q(\stage_2_data_r_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [11]),
        .Q(\stage_2_data_r_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [10]),
        .Q(\stage_2_data_r_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [9]),
        .Q(\stage_2_data_r_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [8]),
        .Q(\stage_2_data_r_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [7]),
        .Q(\stage_2_data_r_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [6]),
        .Q(\stage_2_data_r_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [5]),
        .Q(\stage_2_data_r_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [4]),
        .Q(\stage_2_data_r_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [58]),
        .Q(\stage_2_data_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [3]),
        .Q(\stage_2_data_r_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [2]),
        .Q(\stage_2_data_r_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [1]),
        .Q(\stage_2_data_r_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [0]),
        .Q(\stage_2_data_r_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [57]),
        .Q(\stage_2_data_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [56]),
        .Q(\stage_2_data_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [55]),
        .Q(\stage_2_data_r_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \stage_2_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_data_r_reg[0]_0 [54]),
        .Q(\stage_2_data_r_reg_n_0_[9] ),
        .R(1'b0));
  FDRE stage_2_end_after_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_rx_ll_deframer_i_n_10),
        .Q(stage_2_end_after_start_r),
        .R(RESET));
  FDRE stage_2_end_before_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool),
        .Q(stage_2_end_before_start_r),
        .R(RESET));
  FDRE stage_2_frame_err_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_rx_ll_deframer_i_n_11),
        .Q(stage_2_frame_err_r),
        .R(RESET));
  aurora_rx_4l_64b_LEFT_ALIGN_CONTROL stage_2_left_align_control_i
       (.D({mux_select_c[1],stage_1_rx_ll_deframer_i_n_4,mux_select_c[4],stage_1_rx_ll_deframer_i_n_6,stage_1_rx_ll_deframer_i_n_7}),
        .Q({stage_2_left_align_control_i_n_0,stage_2_left_align_control_i_n_1,stage_2_left_align_control_i_n_2,stage_2_left_align_control_i_n_3,stage_2_left_align_control_i_n_4}),
        .user_clk(user_clk));
  FDRE stage_2_pad_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_pad_r),
        .Q(stage_2_pad_r),
        .R(1'b0));
  FDRE stage_2_start_with_data_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_1_rx_ll_deframer_i_n_8),
        .Q(stage_2_start_with_data_r),
        .R(RESET));
  aurora_rx_4l_64b_VALID_DATA_COUNTER_5 stage_2_valid_data_counter_i
       (.\COUNT_Buffer_reg[0]_0 ({plusOp,stage_1_rx_ll_deframer_i_n_2}),
        .D(storage_count_c[1]),
        .Q({L__0[1],L__0[2],L__0[3]}),
        .RESET(RESET),
        .stage_2_start_with_data_r(stage_2_start_with_data_r),
        .stage_3_end_storage_r(stage_3_end_storage_r),
        .\storage_count_r_reg[1] ({stage_3_storage_count_r[1],stage_3_storage_count_r[2]}),
        .user_clk(user_clk));
  aurora_rx_4l_64b_LEFT_ALIGN_MUX stage_3_left_align_datapath_mux_i
       (.\MUXED_DATA_Buffer_reg[0]_0 ({stage_3_left_align_datapath_mux_i_n_0,stage_3_left_align_datapath_mux_i_n_1,stage_3_left_align_datapath_mux_i_n_2,stage_3_left_align_datapath_mux_i_n_3,stage_3_left_align_datapath_mux_i_n_4,stage_3_left_align_datapath_mux_i_n_5,stage_3_left_align_datapath_mux_i_n_6,stage_3_left_align_datapath_mux_i_n_7,stage_3_left_align_datapath_mux_i_n_8,stage_3_left_align_datapath_mux_i_n_9,stage_3_left_align_datapath_mux_i_n_10,stage_3_left_align_datapath_mux_i_n_11,stage_3_left_align_datapath_mux_i_n_12,stage_3_left_align_datapath_mux_i_n_13,stage_3_left_align_datapath_mux_i_n_14,stage_3_left_align_datapath_mux_i_n_15,stage_3_left_align_datapath_mux_i_n_16,stage_3_left_align_datapath_mux_i_n_17,stage_3_left_align_datapath_mux_i_n_18,stage_3_left_align_datapath_mux_i_n_19,stage_3_left_align_datapath_mux_i_n_20,stage_3_left_align_datapath_mux_i_n_21,stage_3_left_align_datapath_mux_i_n_22,stage_3_left_align_datapath_mux_i_n_23,stage_3_left_align_datapath_mux_i_n_24,stage_3_left_align_datapath_mux_i_n_25,stage_3_left_align_datapath_mux_i_n_26,stage_3_left_align_datapath_mux_i_n_27,stage_3_left_align_datapath_mux_i_n_28,stage_3_left_align_datapath_mux_i_n_29,stage_3_left_align_datapath_mux_i_n_30,stage_3_left_align_datapath_mux_i_n_31,p_1_in,stage_3_left_align_datapath_mux_i_n_48,stage_3_left_align_datapath_mux_i_n_49,stage_3_left_align_datapath_mux_i_n_50,stage_3_left_align_datapath_mux_i_n_51,stage_3_left_align_datapath_mux_i_n_52,stage_3_left_align_datapath_mux_i_n_53,stage_3_left_align_datapath_mux_i_n_54,stage_3_left_align_datapath_mux_i_n_55,stage_3_left_align_datapath_mux_i_n_56,stage_3_left_align_datapath_mux_i_n_57,stage_3_left_align_datapath_mux_i_n_58,stage_3_left_align_datapath_mux_i_n_59,stage_3_left_align_datapath_mux_i_n_60,stage_3_left_align_datapath_mux_i_n_61,stage_3_left_align_datapath_mux_i_n_62,stage_3_left_align_datapath_mux_i_n_63}),
        .\MUXED_DATA_Buffer_reg[0]_1 ({stage_2_left_align_control_i_n_0,stage_2_left_align_control_i_n_1,stage_2_left_align_control_i_n_2,stage_2_left_align_control_i_n_3,stage_2_left_align_control_i_n_4}),
        .Q({\stage_2_data_r_reg_n_0_[0] ,\stage_2_data_r_reg_n_0_[1] ,\stage_2_data_r_reg_n_0_[2] ,\stage_2_data_r_reg_n_0_[3] ,\stage_2_data_r_reg_n_0_[4] ,\stage_2_data_r_reg_n_0_[5] ,\stage_2_data_r_reg_n_0_[6] ,\stage_2_data_r_reg_n_0_[7] ,\stage_2_data_r_reg_n_0_[8] ,\stage_2_data_r_reg_n_0_[9] ,\stage_2_data_r_reg_n_0_[10] ,\stage_2_data_r_reg_n_0_[11] ,\stage_2_data_r_reg_n_0_[12] ,\stage_2_data_r_reg_n_0_[13] ,\stage_2_data_r_reg_n_0_[14] ,\stage_2_data_r_reg_n_0_[15] ,p_5_in,p_3_in,\stage_2_data_r_reg_n_0_[48] ,\stage_2_data_r_reg_n_0_[49] ,\stage_2_data_r_reg_n_0_[50] ,\stage_2_data_r_reg_n_0_[51] ,\stage_2_data_r_reg_n_0_[52] ,\stage_2_data_r_reg_n_0_[53] ,\stage_2_data_r_reg_n_0_[54] ,\stage_2_data_r_reg_n_0_[55] ,\stage_2_data_r_reg_n_0_[56] ,\stage_2_data_r_reg_n_0_[57] ,\stage_2_data_r_reg_n_0_[58] ,\stage_2_data_r_reg_n_0_[59] ,\stage_2_data_r_reg_n_0_[60] ,\stage_2_data_r_reg_n_0_[61] ,\stage_2_data_r_reg_n_0_[62] ,\stage_2_data_r_reg_n_0_[63] }),
        .user_clk(user_clk));
  aurora_rx_4l_64b_OUTPUT_SWITCH_CONTROL stage_3_output_switch_control_i
       (.D({output_select_c[13],output_select_c[14],output_select_c[18]}),
        .OUTPUT_SELECT_Buffer({OUTPUT_SELECT_Buffer[13],OUTPUT_SELECT_Buffer[14],OUTPUT_SELECT_Buffer[18],OUTPUT_SELECT_Buffer[19]}),
        .Q(stage_3_storage_count_r[2]),
        .SR(take_storage_c),
        .user_clk(user_clk));
  aurora_rx_4l_64b_STORAGE_CE_CONTROL stage_3_storage_ce_control_i
       (.D({ce_command_c[0],stage_3_storage_count_control_i_n_1,ce_command_c[2],stage_3_storage_count_control_i_n_3}),
        .Q({stage_3_storage_ce_control_i_n_0,stage_3_storage_ce_control_i_n_1,p_0_in0,stage_3_storage_ce_control_i_n_3}),
        .RESET(RESET),
        .user_clk(user_clk));
  aurora_rx_4l_64b_STORAGE_COUNT_CONTROL stage_3_storage_count_control_i
       (.D({ce_command_c[0],stage_3_storage_count_control_i_n_1,ce_command_c[2],stage_3_storage_count_control_i_n_3}),
        .FRAME_ERR_RESULT_Buffer0(FRAME_ERR_RESULT_Buffer0),
        .Q({stage_3_storage_count_r[1],stage_3_storage_count_r[2]}),
        .SR(sideband_output_i_n_1),
        .end_storage_r0(end_storage_r0),
        .end_storage_r_reg(stage_3_storage_count_control_i_n_6),
        .stage_2_end_after_start_r(stage_2_end_after_start_r),
        .stage_2_end_before_start_r(stage_2_end_before_start_r),
        .stage_2_frame_err_r(stage_2_frame_err_r),
        .stage_2_start_with_data_r(stage_2_start_with_data_r),
        .stage_2_start_with_data_r_reg(rx_rem_c),
        .stage_3_end_storage_r(stage_3_end_storage_r),
        .\storage_count_r_reg[0]_0 ({output_select_c[13],output_select_c[14],output_select_c[18]}),
        .\storage_count_r_reg[0]_1 ({L__0[1],L__0[2],L__0[3]}),
        .\storage_count_r_reg[1]_0 ({stage_3_storage_count_control_i_n_10,stage_3_storage_count_control_i_n_11,stage_3_storage_count_control_i_n_12,stage_3_storage_count_control_i_n_13}),
        .\storage_count_r_reg[1]_1 ({storage_count_c[1],storage_count_c[2]}),
        .\storage_count_r_reg[2]_0 (stage_3_storage_count_control_i_n_14),
        .user_clk(user_clk));
  aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL stage_3_storage_switch_control_i
       (.D({stage_3_storage_count_control_i_n_10,stage_3_storage_count_r[1],stage_3_storage_count_control_i_n_11,stage_3_storage_count_control_i_n_12,stage_3_storage_count_control_i_n_13}),
        .Q({STORAGE_SELECT_Buffer[3],STORAGE_SELECT_Buffer[8],STORAGE_SELECT_Buffer[13],STORAGE_SELECT_Buffer[18],STORAGE_SELECT_Buffer[19]}),
        .SR(take_storage_c),
        .user_clk(user_clk));
  aurora_rx_4l_64b_STORAGE_MUX stage_4_storage_mux_i
       (.D({\STORAGE_DATA_Buffer[0]_i_1_n_0 ,\STORAGE_DATA_Buffer[1]_i_1_n_0 ,\STORAGE_DATA_Buffer[2]_i_1_n_0 ,\STORAGE_DATA_Buffer[3]_i_1_n_0 ,\STORAGE_DATA_Buffer[4]_i_1_n_0 ,\STORAGE_DATA_Buffer[5]_i_1_n_0 ,\STORAGE_DATA_Buffer[6]_i_1_n_0 ,\STORAGE_DATA_Buffer[7]_i_1_n_0 ,\STORAGE_DATA_Buffer[8]_i_1_n_0 ,\STORAGE_DATA_Buffer[9]_i_1_n_0 ,\STORAGE_DATA_Buffer[10]_i_1_n_0 ,\STORAGE_DATA_Buffer[11]_i_1_n_0 ,\STORAGE_DATA_Buffer[12]_i_1_n_0 ,\STORAGE_DATA_Buffer[13]_i_1_n_0 ,\STORAGE_DATA_Buffer[14]_i_1_n_0 ,\STORAGE_DATA_Buffer[15]_i_1_n_0 ,\STORAGE_DATA_Buffer[16]_i_1_n_0 ,\STORAGE_DATA_Buffer[17]_i_1_n_0 ,\STORAGE_DATA_Buffer[18]_i_1_n_0 ,\STORAGE_DATA_Buffer[19]_i_1_n_0 ,\STORAGE_DATA_Buffer[20]_i_1_n_0 ,\STORAGE_DATA_Buffer[21]_i_1_n_0 ,\STORAGE_DATA_Buffer[22]_i_1_n_0 ,\STORAGE_DATA_Buffer[23]_i_1_n_0 ,\STORAGE_DATA_Buffer[24]_i_1_n_0 ,\STORAGE_DATA_Buffer[25]_i_1_n_0 ,\STORAGE_DATA_Buffer[26]_i_1_n_0 ,\STORAGE_DATA_Buffer[27]_i_1_n_0 ,\STORAGE_DATA_Buffer[28]_i_1_n_0 ,\STORAGE_DATA_Buffer[29]_i_1_n_0 ,\STORAGE_DATA_Buffer[30]_i_1_n_0 ,\STORAGE_DATA_Buffer[31]_i_1_n_0 ,\STORAGE_DATA_Buffer[32]_i_1_n_0 ,\STORAGE_DATA_Buffer[33]_i_1_n_0 ,\STORAGE_DATA_Buffer[34]_i_1_n_0 ,\STORAGE_DATA_Buffer[35]_i_1_n_0 ,\STORAGE_DATA_Buffer[36]_i_1_n_0 ,\STORAGE_DATA_Buffer[37]_i_1_n_0 ,\STORAGE_DATA_Buffer[38]_i_1_n_0 ,\STORAGE_DATA_Buffer[39]_i_1_n_0 ,\STORAGE_DATA_Buffer[40]_i_1_n_0 ,\STORAGE_DATA_Buffer[41]_i_1_n_0 ,\STORAGE_DATA_Buffer[42]_i_1_n_0 ,\STORAGE_DATA_Buffer[43]_i_1_n_0 ,\STORAGE_DATA_Buffer[44]_i_1_n_0 ,\STORAGE_DATA_Buffer[45]_i_1_n_0 ,\STORAGE_DATA_Buffer[46]_i_1_n_0 ,\STORAGE_DATA_Buffer[47]_i_1_n_0 ,\STORAGE_DATA_Buffer[48]_i_1_n_0 ,\STORAGE_DATA_Buffer[49]_i_1_n_0 ,\STORAGE_DATA_Buffer[50]_i_1_n_0 ,\STORAGE_DATA_Buffer[51]_i_1_n_0 ,\STORAGE_DATA_Buffer[52]_i_1_n_0 ,\STORAGE_DATA_Buffer[53]_i_1_n_0 ,\STORAGE_DATA_Buffer[54]_i_1_n_0 ,\STORAGE_DATA_Buffer[55]_i_1_n_0 ,\STORAGE_DATA_Buffer[56]_i_1_n_0 ,\STORAGE_DATA_Buffer[57]_i_1_n_0 ,\STORAGE_DATA_Buffer[58]_i_1_n_0 ,\STORAGE_DATA_Buffer[59]_i_1_n_0 ,\STORAGE_DATA_Buffer[60]_i_1_n_0 ,\STORAGE_DATA_Buffer[61]_i_1_n_0 ,\STORAGE_DATA_Buffer[62]_i_1_n_0 ,\STORAGE_DATA_Buffer[63]_i_1_n_0 }),
        .E({stage_3_storage_ce_control_i_n_0,stage_3_storage_ce_control_i_n_1,p_0_in0,stage_3_storage_ce_control_i_n_3}),
        .Q({STORAGE_DATA[0],STORAGE_DATA[1],STORAGE_DATA[2],STORAGE_DATA[3],STORAGE_DATA[4],STORAGE_DATA[5],STORAGE_DATA[6],STORAGE_DATA[7],STORAGE_DATA[8],STORAGE_DATA[9],STORAGE_DATA[10],STORAGE_DATA[11],STORAGE_DATA[12],STORAGE_DATA[13],STORAGE_DATA[14],STORAGE_DATA[15],STORAGE_DATA[16],STORAGE_DATA[17],STORAGE_DATA[18],STORAGE_DATA[19],STORAGE_DATA[20],STORAGE_DATA[21],STORAGE_DATA[22],STORAGE_DATA[23],STORAGE_DATA[24],STORAGE_DATA[25],STORAGE_DATA[26],STORAGE_DATA[27],STORAGE_DATA[28],STORAGE_DATA[29],STORAGE_DATA[30],STORAGE_DATA[31],STORAGE_DATA[32],STORAGE_DATA[33],STORAGE_DATA[34],STORAGE_DATA[35],STORAGE_DATA[36],STORAGE_DATA[37],STORAGE_DATA[38],STORAGE_DATA[39],STORAGE_DATA[40],STORAGE_DATA[41],STORAGE_DATA[42],STORAGE_DATA[43],STORAGE_DATA[44],STORAGE_DATA[45],STORAGE_DATA[46],STORAGE_DATA[47],STORAGE_DATA[48],STORAGE_DATA[49],STORAGE_DATA[50],STORAGE_DATA[51],STORAGE_DATA[52],STORAGE_DATA[53],STORAGE_DATA[54],STORAGE_DATA[55],STORAGE_DATA[56],STORAGE_DATA[57],STORAGE_DATA[58],STORAGE_DATA[59],STORAGE_DATA[60],STORAGE_DATA[61],STORAGE_DATA[62],STORAGE_DATA[63]}),
        .user_clk(user_clk));
endmodule

module aurora_rx_4l_64b_RX_LL_UFC_DATAPATH
   (\stage_1_data_r_reg[0]_0 ,
    UFC_RX_EOF_N,
    M_AXI_UFC_RX_TLAST,
    M_AXI_UFC_RX_TVALID,
    \UFC_RX_REM_Buffer_reg[0]_0 ,
    M_AXI_UFC_RX_TDATA,
    \stage_1_data_r_reg[7]_0 ,
    user_clk,
    \stage_1_data_r_reg[23]_0 ,
    \stage_1_data_r_reg[55]_0 ,
    \stage_1_data_r_reg[39]_0 ,
    \stage_1_data_r_reg[6]_0 ,
    \stage_1_data_r_reg[22]_0 ,
    \stage_1_data_r_reg[54]_0 ,
    \stage_1_data_r_reg[38]_0 ,
    \stage_1_data_r_reg[5]_0 ,
    \stage_1_data_r_reg[21]_0 ,
    \stage_1_data_r_reg[53]_0 ,
    \stage_1_data_r_reg[37]_0 ,
    \stage_1_data_r_reg[4]_0 ,
    \stage_1_data_r_reg[20]_0 ,
    \stage_1_data_r_reg[52]_0 ,
    \stage_1_data_r_reg[36]_0 ,
    \stage_1_data_r_reg[3]_0 ,
    \stage_1_data_r_reg[19]_0 ,
    \stage_1_data_r_reg[51]_0 ,
    \stage_1_data_r_reg[35]_0 ,
    \stage_1_data_r_reg[2]_0 ,
    \stage_1_data_r_reg[18]_0 ,
    \stage_1_data_r_reg[50]_0 ,
    \stage_1_data_r_reg[34]_0 ,
    \stage_1_data_r_reg[1]_0 ,
    \stage_1_data_r_reg[17]_0 ,
    \stage_1_data_r_reg[49]_0 ,
    \stage_1_data_r_reg[33]_0 ,
    \stage_1_data_r_reg[0]_1 ,
    \stage_1_data_r_reg[16]_0 ,
    \stage_1_data_r_reg[48]_0 ,
    \stage_1_data_r_reg[32]_0 ,
    \stage_1_data_r_reg[15]_0 ,
    \stage_1_data_r_reg[31]_0 ,
    \stage_1_data_r_reg[63]_0 ,
    \stage_1_data_r_reg[47]_0 ,
    \stage_1_data_r_reg[14]_0 ,
    \stage_1_data_r_reg[30]_0 ,
    \stage_1_data_r_reg[62]_0 ,
    \stage_1_data_r_reg[46]_0 ,
    \stage_1_data_r_reg[13]_0 ,
    \stage_1_data_r_reg[29]_0 ,
    \stage_1_data_r_reg[61]_0 ,
    \stage_1_data_r_reg[45]_0 ,
    \stage_1_data_r_reg[12]_0 ,
    \stage_1_data_r_reg[28]_0 ,
    \stage_1_data_r_reg[60]_0 ,
    \stage_1_data_r_reg[44]_0 ,
    \stage_1_data_r_reg[11]_0 ,
    \stage_1_data_r_reg[27]_0 ,
    \stage_1_data_r_reg[59]_0 ,
    \stage_1_data_r_reg[43]_0 ,
    \stage_1_data_r_reg[10]_0 ,
    \stage_1_data_r_reg[26]_0 ,
    \stage_1_data_r_reg[58]_0 ,
    \stage_1_data_r_reg[42]_0 ,
    \stage_1_data_r_reg[9]_0 ,
    \stage_1_data_r_reg[25]_0 ,
    \stage_1_data_r_reg[57]_0 ,
    \stage_1_data_r_reg[41]_0 ,
    \stage_1_data_r_reg[8]_0 ,
    \stage_1_data_r_reg[24]_0 ,
    \stage_1_data_r_reg[56]_0 ,
    \stage_1_data_r_reg[40]_0 ,
    RESET,
    ufc_start_i,
    \BARREL_SHIFTER_CONTROL_Buffer_reg[1] ,
    \BARREL_SHIFTER_CONTROL_Buffer_reg[2] ,
    Q);
  output [63:0]\stage_1_data_r_reg[0]_0 ;
  output UFC_RX_EOF_N;
  output M_AXI_UFC_RX_TLAST;
  output M_AXI_UFC_RX_TVALID;
  output [1:0]\UFC_RX_REM_Buffer_reg[0]_0 ;
  output [63:0]M_AXI_UFC_RX_TDATA;
  input \stage_1_data_r_reg[7]_0 ;
  input user_clk;
  input \stage_1_data_r_reg[23]_0 ;
  input \stage_1_data_r_reg[55]_0 ;
  input \stage_1_data_r_reg[39]_0 ;
  input \stage_1_data_r_reg[6]_0 ;
  input \stage_1_data_r_reg[22]_0 ;
  input \stage_1_data_r_reg[54]_0 ;
  input \stage_1_data_r_reg[38]_0 ;
  input \stage_1_data_r_reg[5]_0 ;
  input \stage_1_data_r_reg[21]_0 ;
  input \stage_1_data_r_reg[53]_0 ;
  input \stage_1_data_r_reg[37]_0 ;
  input \stage_1_data_r_reg[4]_0 ;
  input \stage_1_data_r_reg[20]_0 ;
  input \stage_1_data_r_reg[52]_0 ;
  input \stage_1_data_r_reg[36]_0 ;
  input \stage_1_data_r_reg[3]_0 ;
  input \stage_1_data_r_reg[19]_0 ;
  input \stage_1_data_r_reg[51]_0 ;
  input \stage_1_data_r_reg[35]_0 ;
  input \stage_1_data_r_reg[2]_0 ;
  input \stage_1_data_r_reg[18]_0 ;
  input \stage_1_data_r_reg[50]_0 ;
  input \stage_1_data_r_reg[34]_0 ;
  input \stage_1_data_r_reg[1]_0 ;
  input \stage_1_data_r_reg[17]_0 ;
  input \stage_1_data_r_reg[49]_0 ;
  input \stage_1_data_r_reg[33]_0 ;
  input \stage_1_data_r_reg[0]_1 ;
  input \stage_1_data_r_reg[16]_0 ;
  input \stage_1_data_r_reg[48]_0 ;
  input \stage_1_data_r_reg[32]_0 ;
  input \stage_1_data_r_reg[15]_0 ;
  input \stage_1_data_r_reg[31]_0 ;
  input \stage_1_data_r_reg[63]_0 ;
  input \stage_1_data_r_reg[47]_0 ;
  input \stage_1_data_r_reg[14]_0 ;
  input \stage_1_data_r_reg[30]_0 ;
  input \stage_1_data_r_reg[62]_0 ;
  input \stage_1_data_r_reg[46]_0 ;
  input \stage_1_data_r_reg[13]_0 ;
  input \stage_1_data_r_reg[29]_0 ;
  input \stage_1_data_r_reg[61]_0 ;
  input \stage_1_data_r_reg[45]_0 ;
  input \stage_1_data_r_reg[12]_0 ;
  input \stage_1_data_r_reg[28]_0 ;
  input \stage_1_data_r_reg[60]_0 ;
  input \stage_1_data_r_reg[44]_0 ;
  input \stage_1_data_r_reg[11]_0 ;
  input \stage_1_data_r_reg[27]_0 ;
  input \stage_1_data_r_reg[59]_0 ;
  input \stage_1_data_r_reg[43]_0 ;
  input \stage_1_data_r_reg[10]_0 ;
  input \stage_1_data_r_reg[26]_0 ;
  input \stage_1_data_r_reg[58]_0 ;
  input \stage_1_data_r_reg[42]_0 ;
  input \stage_1_data_r_reg[9]_0 ;
  input \stage_1_data_r_reg[25]_0 ;
  input \stage_1_data_r_reg[57]_0 ;
  input \stage_1_data_r_reg[41]_0 ;
  input \stage_1_data_r_reg[8]_0 ;
  input \stage_1_data_r_reg[24]_0 ;
  input \stage_1_data_r_reg[56]_0 ;
  input \stage_1_data_r_reg[40]_0 ;
  input RESET;
  input ufc_start_i;
  input \BARREL_SHIFTER_CONTROL_Buffer_reg[1] ;
  input \BARREL_SHIFTER_CONTROL_Buffer_reg[2] ;
  input [3:0]Q;

  wire \BARREL_SHIFTER_CONTROL_Buffer_reg[1] ;
  wire \BARREL_SHIFTER_CONTROL_Buffer_reg[2] ;
  wire [0:63]MUXED_DATA_Buffer;
  wire [63:0]M_AXI_UFC_RX_TDATA;
  wire M_AXI_UFC_RX_TLAST;
  wire M_AXI_UFC_RX_TVALID;
  wire [3:0]Q;
  wire RESET;
  wire [0:15]SHIFTED_DATA_Buffer;
  wire UFC_EOF_N_Buffer;
  wire [4:0]UFC_OUTPUT_SELECT_Buffer;
  wire UFC_RX_EOF_N;
  wire [1:0]\UFC_RX_REM_Buffer_reg[0]_0 ;
  wire UFC_SRC_RDY_N_Buffer;
  wire [0:11]UFC_STORAGE_SELECT_Buffer;
  wire [0:2]barrel_shifted_count_r;
  wire [31:16]p_8_out;
  wire rx_ufc_src_rdy;
  wire [63:0]\stage_1_data_r_reg[0]_0 ;
  wire \stage_1_data_r_reg[0]_1 ;
  wire \stage_1_data_r_reg[10]_0 ;
  wire \stage_1_data_r_reg[11]_0 ;
  wire \stage_1_data_r_reg[12]_0 ;
  wire \stage_1_data_r_reg[13]_0 ;
  wire \stage_1_data_r_reg[14]_0 ;
  wire \stage_1_data_r_reg[15]_0 ;
  wire \stage_1_data_r_reg[16]_0 ;
  wire \stage_1_data_r_reg[17]_0 ;
  wire \stage_1_data_r_reg[18]_0 ;
  wire \stage_1_data_r_reg[19]_0 ;
  wire \stage_1_data_r_reg[1]_0 ;
  wire \stage_1_data_r_reg[20]_0 ;
  wire \stage_1_data_r_reg[21]_0 ;
  wire \stage_1_data_r_reg[22]_0 ;
  wire \stage_1_data_r_reg[23]_0 ;
  wire \stage_1_data_r_reg[24]_0 ;
  wire \stage_1_data_r_reg[25]_0 ;
  wire \stage_1_data_r_reg[26]_0 ;
  wire \stage_1_data_r_reg[27]_0 ;
  wire \stage_1_data_r_reg[28]_0 ;
  wire \stage_1_data_r_reg[29]_0 ;
  wire \stage_1_data_r_reg[2]_0 ;
  wire \stage_1_data_r_reg[30]_0 ;
  wire \stage_1_data_r_reg[31]_0 ;
  wire \stage_1_data_r_reg[32]_0 ;
  wire \stage_1_data_r_reg[33]_0 ;
  wire \stage_1_data_r_reg[34]_0 ;
  wire \stage_1_data_r_reg[35]_0 ;
  wire \stage_1_data_r_reg[36]_0 ;
  wire \stage_1_data_r_reg[37]_0 ;
  wire \stage_1_data_r_reg[38]_0 ;
  wire \stage_1_data_r_reg[39]_0 ;
  wire \stage_1_data_r_reg[3]_0 ;
  wire \stage_1_data_r_reg[40]_0 ;
  wire \stage_1_data_r_reg[41]_0 ;
  wire \stage_1_data_r_reg[42]_0 ;
  wire \stage_1_data_r_reg[43]_0 ;
  wire \stage_1_data_r_reg[44]_0 ;
  wire \stage_1_data_r_reg[45]_0 ;
  wire \stage_1_data_r_reg[46]_0 ;
  wire \stage_1_data_r_reg[47]_0 ;
  wire \stage_1_data_r_reg[48]_0 ;
  wire \stage_1_data_r_reg[49]_0 ;
  wire \stage_1_data_r_reg[4]_0 ;
  wire \stage_1_data_r_reg[50]_0 ;
  wire \stage_1_data_r_reg[51]_0 ;
  wire \stage_1_data_r_reg[52]_0 ;
  wire \stage_1_data_r_reg[53]_0 ;
  wire \stage_1_data_r_reg[54]_0 ;
  wire \stage_1_data_r_reg[55]_0 ;
  wire \stage_1_data_r_reg[56]_0 ;
  wire \stage_1_data_r_reg[57]_0 ;
  wire \stage_1_data_r_reg[58]_0 ;
  wire \stage_1_data_r_reg[59]_0 ;
  wire \stage_1_data_r_reg[5]_0 ;
  wire \stage_1_data_r_reg[60]_0 ;
  wire \stage_1_data_r_reg[61]_0 ;
  wire \stage_1_data_r_reg[62]_0 ;
  wire \stage_1_data_r_reg[63]_0 ;
  wire \stage_1_data_r_reg[6]_0 ;
  wire \stage_1_data_r_reg[7]_0 ;
  wire \stage_1_data_r_reg[8]_0 ;
  wire \stage_1_data_r_reg[9]_0 ;
  wire stage_1_ufc_start_r;
  wire [2:1]storage_count_2x_c;
  wire ufc_barrel_shifter_control_i_n_0;
  wire ufc_barrel_shifter_control_i_n_1;
  wire ufc_barrel_shifter_i_n_0;
  wire ufc_barrel_shifter_i_n_100;
  wire ufc_barrel_shifter_i_n_101;
  wire ufc_barrel_shifter_i_n_102;
  wire ufc_barrel_shifter_i_n_103;
  wire ufc_barrel_shifter_i_n_104;
  wire ufc_barrel_shifter_i_n_105;
  wire ufc_barrel_shifter_i_n_106;
  wire ufc_barrel_shifter_i_n_107;
  wire ufc_barrel_shifter_i_n_108;
  wire ufc_barrel_shifter_i_n_109;
  wire ufc_barrel_shifter_i_n_110;
  wire ufc_barrel_shifter_i_n_111;
  wire ufc_barrel_shifter_i_n_17;
  wire ufc_barrel_shifter_i_n_18;
  wire ufc_barrel_shifter_i_n_19;
  wire ufc_barrel_shifter_i_n_20;
  wire ufc_barrel_shifter_i_n_21;
  wire ufc_barrel_shifter_i_n_22;
  wire ufc_barrel_shifter_i_n_23;
  wire ufc_barrel_shifter_i_n_24;
  wire ufc_barrel_shifter_i_n_25;
  wire ufc_barrel_shifter_i_n_26;
  wire ufc_barrel_shifter_i_n_27;
  wire ufc_barrel_shifter_i_n_28;
  wire ufc_barrel_shifter_i_n_29;
  wire ufc_barrel_shifter_i_n_30;
  wire ufc_barrel_shifter_i_n_31;
  wire ufc_barrel_shifter_i_n_32;
  wire ufc_barrel_shifter_i_n_33;
  wire ufc_barrel_shifter_i_n_34;
  wire ufc_barrel_shifter_i_n_35;
  wire ufc_barrel_shifter_i_n_36;
  wire ufc_barrel_shifter_i_n_37;
  wire ufc_barrel_shifter_i_n_38;
  wire ufc_barrel_shifter_i_n_39;
  wire ufc_barrel_shifter_i_n_40;
  wire ufc_barrel_shifter_i_n_41;
  wire ufc_barrel_shifter_i_n_42;
  wire ufc_barrel_shifter_i_n_43;
  wire ufc_barrel_shifter_i_n_44;
  wire ufc_barrel_shifter_i_n_45;
  wire ufc_barrel_shifter_i_n_46;
  wire ufc_barrel_shifter_i_n_47;
  wire ufc_barrel_shifter_i_n_48;
  wire ufc_barrel_shifter_i_n_49;
  wire ufc_barrel_shifter_i_n_50;
  wire ufc_barrel_shifter_i_n_51;
  wire ufc_barrel_shifter_i_n_52;
  wire ufc_barrel_shifter_i_n_53;
  wire ufc_barrel_shifter_i_n_54;
  wire ufc_barrel_shifter_i_n_55;
  wire ufc_barrel_shifter_i_n_56;
  wire ufc_barrel_shifter_i_n_57;
  wire ufc_barrel_shifter_i_n_58;
  wire ufc_barrel_shifter_i_n_59;
  wire ufc_barrel_shifter_i_n_60;
  wire ufc_barrel_shifter_i_n_61;
  wire ufc_barrel_shifter_i_n_62;
  wire ufc_barrel_shifter_i_n_63;
  wire ufc_barrel_shifter_i_n_64;
  wire ufc_barrel_shifter_i_n_65;
  wire ufc_barrel_shifter_i_n_66;
  wire ufc_barrel_shifter_i_n_67;
  wire ufc_barrel_shifter_i_n_68;
  wire ufc_barrel_shifter_i_n_69;
  wire ufc_barrel_shifter_i_n_70;
  wire ufc_barrel_shifter_i_n_71;
  wire ufc_barrel_shifter_i_n_72;
  wire ufc_barrel_shifter_i_n_73;
  wire ufc_barrel_shifter_i_n_74;
  wire ufc_barrel_shifter_i_n_75;
  wire ufc_barrel_shifter_i_n_76;
  wire ufc_barrel_shifter_i_n_77;
  wire ufc_barrel_shifter_i_n_78;
  wire ufc_barrel_shifter_i_n_79;
  wire ufc_barrel_shifter_i_n_96;
  wire ufc_barrel_shifter_i_n_97;
  wire ufc_barrel_shifter_i_n_98;
  wire ufc_barrel_shifter_i_n_99;
  wire [9:9]ufc_output_select_c0_in;
  wire ufc_output_switch_control_i_n_0;
  wire ufc_output_switch_control_i_n_10;
  wire ufc_output_switch_control_i_n_11;
  wire ufc_output_switch_control_i_n_12;
  wire ufc_output_switch_control_i_n_13;
  wire ufc_output_switch_control_i_n_14;
  wire ufc_output_switch_control_i_n_15;
  wire ufc_output_switch_control_i_n_16;
  wire ufc_output_switch_control_i_n_17;
  wire ufc_output_switch_control_i_n_18;
  wire ufc_output_switch_control_i_n_19;
  wire ufc_output_switch_control_i_n_20;
  wire ufc_output_switch_control_i_n_6;
  wire ufc_output_switch_control_i_n_7;
  wire ufc_output_switch_control_i_n_8;
  wire ufc_output_switch_control_i_n_9;
  wire ufc_sideband_output_i_n_2;
  wire ufc_sideband_output_i_n_3;
  wire ufc_start_i;
  wire ufc_storage_count_control_i_n_0;
  wire ufc_storage_count_control_i_n_1;
  wire ufc_storage_count_control_i_n_15;
  wire ufc_storage_count_control_i_n_16;
  wire ufc_storage_count_control_i_n_17;
  wire ufc_storage_count_control_i_n_4;
  wire ufc_storage_count_control_i_n_6;
  wire ufc_storage_count_control_i_n_7;
  wire ufc_storage_count_control_i_n_8;
  wire [3:11]ufc_storage_select_c;
  wire user_clk;

  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_UFC_RX_TLAST_INST_0
       (.I0(UFC_RX_EOF_N),
        .O(M_AXI_UFC_RX_TLAST));
  LUT1 #(
    .INIT(2'h1)) 
    M_AXI_UFC_RX_TVALID_INST_0
       (.I0(rx_ufc_src_rdy),
        .O(M_AXI_UFC_RX_TVALID));
  FDRE UFC_RX_EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_EOF_N_Buffer),
        .Q(UFC_RX_EOF_N),
        .R(1'b0));
  FDRE \UFC_RX_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ufc_sideband_output_i_n_2),
        .Q(\UFC_RX_REM_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \UFC_RX_REM_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ufc_sideband_output_i_n_3),
        .Q(\UFC_RX_REM_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  FDSE UFC_RX_SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_SRC_RDY_N_Buffer),
        .Q(rx_ufc_src_rdy),
        .S(RESET));
  FDRE \stage_1_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[0]_1 ),
        .Q(\stage_1_data_r_reg[0]_0 [63]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[10]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [53]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[11]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [52]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[12]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [51]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[13]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [50]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[14]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [49]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[15]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [48]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[16]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [47]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[17]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [46]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[18]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [45]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[19]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [44]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[1]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [62]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[20]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [43]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[21]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [42]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[22]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [41]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[23]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [40]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[24]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [39]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[25]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [38]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[26]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [37]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[27]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [36]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[28]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [35]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[29]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [34]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[2]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [61]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[30]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [33]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[31]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [32]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[32]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [31]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[33]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [30]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[34]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [29]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[35]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [28]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[36]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [27]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[37]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [26]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[38]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [25]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[39]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [24]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[3]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [60]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[40]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [23]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[41]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [22]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[42]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [21]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[43]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [20]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[44]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [19]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[45]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [18]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[46]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [17]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[47]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [16]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[48]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [15]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[49]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [14]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[4]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [59]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[50]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [13]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[51]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [12]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[52]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [11]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[53]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [10]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[54]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [9]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[55]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [8]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[56]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[57]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[58]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[59]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[5]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [58]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[60]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[61]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[62]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[63]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[6]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [57]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[7]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [56]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[8]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [55]),
        .R(1'b0));
  FDRE \stage_1_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_data_r_reg[9]_0 ),
        .Q(\stage_1_data_r_reg[0]_0 [54]),
        .R(1'b0));
  FDRE stage_1_ufc_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ufc_start_i),
        .Q(stage_1_ufc_start_r),
        .R(RESET));
  aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL ufc_barrel_shifter_control_i
       (.\BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0 (ufc_barrel_shifter_control_i_n_0),
        .\BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1 (\BARREL_SHIFTER_CONTROL_Buffer_reg[1] ),
        .\BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0 (ufc_barrel_shifter_control_i_n_1),
        .\BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1 (\BARREL_SHIFTER_CONTROL_Buffer_reg[2] ),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_BARREL_SHIFTER ufc_barrel_shifter_i
       (.D(p_8_out),
        .MUXED_DATA_Buffer({MUXED_DATA_Buffer[32],MUXED_DATA_Buffer[33],MUXED_DATA_Buffer[34],MUXED_DATA_Buffer[35],MUXED_DATA_Buffer[36],MUXED_DATA_Buffer[37],MUXED_DATA_Buffer[38],MUXED_DATA_Buffer[39],MUXED_DATA_Buffer[40],MUXED_DATA_Buffer[41],MUXED_DATA_Buffer[42],MUXED_DATA_Buffer[43],MUXED_DATA_Buffer[44],MUXED_DATA_Buffer[45],MUXED_DATA_Buffer[46],MUXED_DATA_Buffer[47],MUXED_DATA_Buffer[48],MUXED_DATA_Buffer[49],MUXED_DATA_Buffer[50],MUXED_DATA_Buffer[51],MUXED_DATA_Buffer[52],MUXED_DATA_Buffer[53],MUXED_DATA_Buffer[54],MUXED_DATA_Buffer[55],MUXED_DATA_Buffer[56],MUXED_DATA_Buffer[57],MUXED_DATA_Buffer[58],MUXED_DATA_Buffer[59],MUXED_DATA_Buffer[60],MUXED_DATA_Buffer[61],MUXED_DATA_Buffer[62],MUXED_DATA_Buffer[63]}),
        .Q({SHIFTED_DATA_Buffer[0],SHIFTED_DATA_Buffer[1],SHIFTED_DATA_Buffer[2],SHIFTED_DATA_Buffer[3],SHIFTED_DATA_Buffer[4],SHIFTED_DATA_Buffer[5],SHIFTED_DATA_Buffer[6],SHIFTED_DATA_Buffer[7],SHIFTED_DATA_Buffer[8],SHIFTED_DATA_Buffer[9],SHIFTED_DATA_Buffer[10],SHIFTED_DATA_Buffer[11],SHIFTED_DATA_Buffer[12],SHIFTED_DATA_Buffer[13],SHIFTED_DATA_Buffer[14],SHIFTED_DATA_Buffer[15]}),
        .\SHIFTED_DATA_Buffer_reg[0]_0 (\stage_1_data_r_reg[0]_0 [31]),
        .\SHIFTED_DATA_Buffer_reg[0]_1 (\stage_1_data_r_reg[0]_0 [63:32]),
        .\SHIFTED_DATA_Buffer_reg[10]_0 (\stage_1_data_r_reg[0]_0 [21]),
        .\SHIFTED_DATA_Buffer_reg[11]_0 (\stage_1_data_r_reg[0]_0 [20]),
        .\SHIFTED_DATA_Buffer_reg[12]_0 (\stage_1_data_r_reg[0]_0 [19]),
        .\SHIFTED_DATA_Buffer_reg[13]_0 (\stage_1_data_r_reg[0]_0 [18]),
        .\SHIFTED_DATA_Buffer_reg[14]_0 (\stage_1_data_r_reg[0]_0 [17]),
        .\SHIFTED_DATA_Buffer_reg[15]_0 (\stage_1_data_r_reg[0]_0 [16]),
        .\SHIFTED_DATA_Buffer_reg[1]_0 (\stage_1_data_r_reg[0]_0 [30]),
        .\SHIFTED_DATA_Buffer_reg[2]_0 (\stage_1_data_r_reg[0]_0 [29]),
        .\SHIFTED_DATA_Buffer_reg[32]_0 (ufc_barrel_shifter_i_n_96),
        .\SHIFTED_DATA_Buffer_reg[32]_1 (ufc_barrel_shifter_control_i_n_0),
        .\SHIFTED_DATA_Buffer_reg[33]_0 (ufc_barrel_shifter_i_n_97),
        .\SHIFTED_DATA_Buffer_reg[34]_0 (ufc_barrel_shifter_i_n_98),
        .\SHIFTED_DATA_Buffer_reg[35]_0 (ufc_barrel_shifter_i_n_99),
        .\SHIFTED_DATA_Buffer_reg[36]_0 (ufc_barrel_shifter_i_n_100),
        .\SHIFTED_DATA_Buffer_reg[37]_0 (ufc_barrel_shifter_i_n_101),
        .\SHIFTED_DATA_Buffer_reg[38]_0 (ufc_barrel_shifter_i_n_102),
        .\SHIFTED_DATA_Buffer_reg[39]_0 (ufc_barrel_shifter_i_n_103),
        .\SHIFTED_DATA_Buffer_reg[3]_0 (\stage_1_data_r_reg[0]_0 [28]),
        .\SHIFTED_DATA_Buffer_reg[40]_0 (ufc_barrel_shifter_i_n_104),
        .\SHIFTED_DATA_Buffer_reg[41]_0 (ufc_barrel_shifter_i_n_105),
        .\SHIFTED_DATA_Buffer_reg[42]_0 (ufc_barrel_shifter_i_n_106),
        .\SHIFTED_DATA_Buffer_reg[43]_0 (ufc_barrel_shifter_i_n_107),
        .\SHIFTED_DATA_Buffer_reg[44]_0 (ufc_barrel_shifter_i_n_108),
        .\SHIFTED_DATA_Buffer_reg[45]_0 (ufc_barrel_shifter_i_n_109),
        .\SHIFTED_DATA_Buffer_reg[46]_0 (ufc_barrel_shifter_i_n_110),
        .\SHIFTED_DATA_Buffer_reg[47]_0 (ufc_barrel_shifter_i_n_111),
        .\SHIFTED_DATA_Buffer_reg[47]_1 (ufc_barrel_shifter_control_i_n_1),
        .\SHIFTED_DATA_Buffer_reg[48]_0 (ufc_barrel_shifter_i_n_0),
        .\SHIFTED_DATA_Buffer_reg[48]_1 (ufc_barrel_shifter_i_n_17),
        .\SHIFTED_DATA_Buffer_reg[48]_2 (ufc_barrel_shifter_i_n_48),
        .\SHIFTED_DATA_Buffer_reg[48]_3 (ufc_barrel_shifter_i_n_49),
        .\SHIFTED_DATA_Buffer_reg[48]_4 (\stage_1_data_r_reg[0]_0 [15]),
        .\SHIFTED_DATA_Buffer_reg[49]_0 (ufc_barrel_shifter_i_n_18),
        .\SHIFTED_DATA_Buffer_reg[49]_1 (ufc_barrel_shifter_i_n_19),
        .\SHIFTED_DATA_Buffer_reg[49]_2 (ufc_barrel_shifter_i_n_50),
        .\SHIFTED_DATA_Buffer_reg[49]_3 (ufc_barrel_shifter_i_n_51),
        .\SHIFTED_DATA_Buffer_reg[49]_4 (\stage_1_data_r_reg[0]_0 [14]),
        .\SHIFTED_DATA_Buffer_reg[4]_0 (\stage_1_data_r_reg[0]_0 [27]),
        .\SHIFTED_DATA_Buffer_reg[50]_0 (ufc_barrel_shifter_i_n_20),
        .\SHIFTED_DATA_Buffer_reg[50]_1 (ufc_barrel_shifter_i_n_21),
        .\SHIFTED_DATA_Buffer_reg[50]_2 (ufc_barrel_shifter_i_n_52),
        .\SHIFTED_DATA_Buffer_reg[50]_3 (ufc_barrel_shifter_i_n_53),
        .\SHIFTED_DATA_Buffer_reg[50]_4 (\stage_1_data_r_reg[0]_0 [13]),
        .\SHIFTED_DATA_Buffer_reg[51]_0 (ufc_barrel_shifter_i_n_22),
        .\SHIFTED_DATA_Buffer_reg[51]_1 (ufc_barrel_shifter_i_n_23),
        .\SHIFTED_DATA_Buffer_reg[51]_2 (ufc_barrel_shifter_i_n_54),
        .\SHIFTED_DATA_Buffer_reg[51]_3 (ufc_barrel_shifter_i_n_55),
        .\SHIFTED_DATA_Buffer_reg[51]_4 (\stage_1_data_r_reg[0]_0 [12]),
        .\SHIFTED_DATA_Buffer_reg[52]_0 (ufc_barrel_shifter_i_n_24),
        .\SHIFTED_DATA_Buffer_reg[52]_1 (ufc_barrel_shifter_i_n_25),
        .\SHIFTED_DATA_Buffer_reg[52]_2 (ufc_barrel_shifter_i_n_56),
        .\SHIFTED_DATA_Buffer_reg[52]_3 (ufc_barrel_shifter_i_n_57),
        .\SHIFTED_DATA_Buffer_reg[52]_4 (\stage_1_data_r_reg[0]_0 [11]),
        .\SHIFTED_DATA_Buffer_reg[53]_0 (ufc_barrel_shifter_i_n_26),
        .\SHIFTED_DATA_Buffer_reg[53]_1 (ufc_barrel_shifter_i_n_27),
        .\SHIFTED_DATA_Buffer_reg[53]_2 (ufc_barrel_shifter_i_n_58),
        .\SHIFTED_DATA_Buffer_reg[53]_3 (ufc_barrel_shifter_i_n_59),
        .\SHIFTED_DATA_Buffer_reg[53]_4 (\stage_1_data_r_reg[0]_0 [10]),
        .\SHIFTED_DATA_Buffer_reg[54]_0 (ufc_barrel_shifter_i_n_28),
        .\SHIFTED_DATA_Buffer_reg[54]_1 (ufc_barrel_shifter_i_n_29),
        .\SHIFTED_DATA_Buffer_reg[54]_2 (ufc_barrel_shifter_i_n_60),
        .\SHIFTED_DATA_Buffer_reg[54]_3 (ufc_barrel_shifter_i_n_61),
        .\SHIFTED_DATA_Buffer_reg[54]_4 (\stage_1_data_r_reg[0]_0 [9]),
        .\SHIFTED_DATA_Buffer_reg[55]_0 (ufc_barrel_shifter_i_n_30),
        .\SHIFTED_DATA_Buffer_reg[55]_1 (ufc_barrel_shifter_i_n_31),
        .\SHIFTED_DATA_Buffer_reg[55]_2 (ufc_barrel_shifter_i_n_62),
        .\SHIFTED_DATA_Buffer_reg[55]_3 (ufc_barrel_shifter_i_n_63),
        .\SHIFTED_DATA_Buffer_reg[55]_4 (\stage_1_data_r_reg[0]_0 [8]),
        .\SHIFTED_DATA_Buffer_reg[56]_0 (ufc_barrel_shifter_i_n_32),
        .\SHIFTED_DATA_Buffer_reg[56]_1 (ufc_barrel_shifter_i_n_33),
        .\SHIFTED_DATA_Buffer_reg[56]_2 (ufc_barrel_shifter_i_n_64),
        .\SHIFTED_DATA_Buffer_reg[56]_3 (ufc_barrel_shifter_i_n_65),
        .\SHIFTED_DATA_Buffer_reg[56]_4 (\stage_1_data_r_reg[0]_0 [7]),
        .\SHIFTED_DATA_Buffer_reg[57]_0 (ufc_barrel_shifter_i_n_34),
        .\SHIFTED_DATA_Buffer_reg[57]_1 (ufc_barrel_shifter_i_n_35),
        .\SHIFTED_DATA_Buffer_reg[57]_2 (ufc_barrel_shifter_i_n_66),
        .\SHIFTED_DATA_Buffer_reg[57]_3 (ufc_barrel_shifter_i_n_67),
        .\SHIFTED_DATA_Buffer_reg[57]_4 (\stage_1_data_r_reg[0]_0 [6]),
        .\SHIFTED_DATA_Buffer_reg[58]_0 (ufc_barrel_shifter_i_n_36),
        .\SHIFTED_DATA_Buffer_reg[58]_1 (ufc_barrel_shifter_i_n_37),
        .\SHIFTED_DATA_Buffer_reg[58]_2 (ufc_barrel_shifter_i_n_68),
        .\SHIFTED_DATA_Buffer_reg[58]_3 (ufc_barrel_shifter_i_n_69),
        .\SHIFTED_DATA_Buffer_reg[58]_4 (\stage_1_data_r_reg[0]_0 [5]),
        .\SHIFTED_DATA_Buffer_reg[59]_0 (ufc_barrel_shifter_i_n_38),
        .\SHIFTED_DATA_Buffer_reg[59]_1 (ufc_barrel_shifter_i_n_39),
        .\SHIFTED_DATA_Buffer_reg[59]_2 (ufc_barrel_shifter_i_n_70),
        .\SHIFTED_DATA_Buffer_reg[59]_3 (ufc_barrel_shifter_i_n_71),
        .\SHIFTED_DATA_Buffer_reg[59]_4 (\stage_1_data_r_reg[0]_0 [4]),
        .\SHIFTED_DATA_Buffer_reg[5]_0 (\stage_1_data_r_reg[0]_0 [26]),
        .\SHIFTED_DATA_Buffer_reg[60]_0 (ufc_barrel_shifter_i_n_40),
        .\SHIFTED_DATA_Buffer_reg[60]_1 (ufc_barrel_shifter_i_n_41),
        .\SHIFTED_DATA_Buffer_reg[60]_2 (ufc_barrel_shifter_i_n_72),
        .\SHIFTED_DATA_Buffer_reg[60]_3 (ufc_barrel_shifter_i_n_73),
        .\SHIFTED_DATA_Buffer_reg[60]_4 (\stage_1_data_r_reg[0]_0 [3]),
        .\SHIFTED_DATA_Buffer_reg[61]_0 (ufc_barrel_shifter_i_n_42),
        .\SHIFTED_DATA_Buffer_reg[61]_1 (ufc_barrel_shifter_i_n_43),
        .\SHIFTED_DATA_Buffer_reg[61]_2 (ufc_barrel_shifter_i_n_74),
        .\SHIFTED_DATA_Buffer_reg[61]_3 (ufc_barrel_shifter_i_n_75),
        .\SHIFTED_DATA_Buffer_reg[61]_4 (\stage_1_data_r_reg[0]_0 [2]),
        .\SHIFTED_DATA_Buffer_reg[62]_0 (ufc_barrel_shifter_i_n_44),
        .\SHIFTED_DATA_Buffer_reg[62]_1 (ufc_barrel_shifter_i_n_45),
        .\SHIFTED_DATA_Buffer_reg[62]_2 (ufc_barrel_shifter_i_n_76),
        .\SHIFTED_DATA_Buffer_reg[62]_3 (ufc_barrel_shifter_i_n_77),
        .\SHIFTED_DATA_Buffer_reg[62]_4 (\stage_1_data_r_reg[0]_0 [1]),
        .\SHIFTED_DATA_Buffer_reg[63]_0 (ufc_barrel_shifter_i_n_46),
        .\SHIFTED_DATA_Buffer_reg[63]_1 (ufc_barrel_shifter_i_n_47),
        .\SHIFTED_DATA_Buffer_reg[63]_2 (ufc_barrel_shifter_i_n_78),
        .\SHIFTED_DATA_Buffer_reg[63]_3 (ufc_barrel_shifter_i_n_79),
        .\SHIFTED_DATA_Buffer_reg[63]_4 (\stage_1_data_r_reg[0]_0 [0]),
        .\SHIFTED_DATA_Buffer_reg[6]_0 (\stage_1_data_r_reg[0]_0 [25]),
        .\SHIFTED_DATA_Buffer_reg[7]_0 (\stage_1_data_r_reg[0]_0 [24]),
        .\SHIFTED_DATA_Buffer_reg[8]_0 (\stage_1_data_r_reg[0]_0 [23]),
        .\SHIFTED_DATA_Buffer_reg[9]_0 (\stage_1_data_r_reg[0]_0 [22]),
        .UFC_OUTPUT_SELECT_Buffer({UFC_OUTPUT_SELECT_Buffer[4:3],UFC_OUTPUT_SELECT_Buffer[1:0]}),
        .UFC_STORAGE_SELECT_Buffer({UFC_STORAGE_SELECT_Buffer[1],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[7],UFC_STORAGE_SELECT_Buffer[8],UFC_STORAGE_SELECT_Buffer[10],UFC_STORAGE_SELECT_Buffer[11]}),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_OUTPUT_MUX ufc_output_mux_i
       (.D({MUXED_DATA_Buffer[0],MUXED_DATA_Buffer[1],MUXED_DATA_Buffer[2],MUXED_DATA_Buffer[3],MUXED_DATA_Buffer[4],MUXED_DATA_Buffer[5],MUXED_DATA_Buffer[6],MUXED_DATA_Buffer[7],MUXED_DATA_Buffer[8],MUXED_DATA_Buffer[9],MUXED_DATA_Buffer[10],MUXED_DATA_Buffer[11],MUXED_DATA_Buffer[12],MUXED_DATA_Buffer[13],MUXED_DATA_Buffer[14],MUXED_DATA_Buffer[15],p_8_out}),
        .\MUXED_DATA_Buffer_reg[16]_0 (ufc_output_switch_control_i_n_0),
        .\MUXED_DATA_Buffer_reg[17]_0 (ufc_output_switch_control_i_n_6),
        .\MUXED_DATA_Buffer_reg[18]_0 (ufc_output_switch_control_i_n_7),
        .\MUXED_DATA_Buffer_reg[19]_0 (ufc_output_switch_control_i_n_8),
        .\MUXED_DATA_Buffer_reg[20]_0 (ufc_output_switch_control_i_n_9),
        .\MUXED_DATA_Buffer_reg[21]_0 (ufc_output_switch_control_i_n_10),
        .\MUXED_DATA_Buffer_reg[22]_0 (ufc_output_switch_control_i_n_11),
        .\MUXED_DATA_Buffer_reg[23]_0 (ufc_output_switch_control_i_n_12),
        .\MUXED_DATA_Buffer_reg[24]_0 (ufc_output_switch_control_i_n_13),
        .\MUXED_DATA_Buffer_reg[25]_0 (ufc_output_switch_control_i_n_14),
        .\MUXED_DATA_Buffer_reg[26]_0 (ufc_output_switch_control_i_n_15),
        .\MUXED_DATA_Buffer_reg[27]_0 (ufc_output_switch_control_i_n_16),
        .\MUXED_DATA_Buffer_reg[28]_0 (ufc_output_switch_control_i_n_17),
        .\MUXED_DATA_Buffer_reg[29]_0 (ufc_output_switch_control_i_n_18),
        .\MUXED_DATA_Buffer_reg[30]_0 (ufc_output_switch_control_i_n_19),
        .\MUXED_DATA_Buffer_reg[31]_0 (ufc_output_switch_control_i_n_20),
        .\MUXED_DATA_Buffer_reg[48]_0 (ufc_barrel_shifter_i_n_96),
        .\MUXED_DATA_Buffer_reg[49]_0 (ufc_barrel_shifter_i_n_97),
        .\MUXED_DATA_Buffer_reg[50]_0 (ufc_barrel_shifter_i_n_98),
        .\MUXED_DATA_Buffer_reg[51]_0 (ufc_barrel_shifter_i_n_99),
        .\MUXED_DATA_Buffer_reg[52]_0 (ufc_barrel_shifter_i_n_100),
        .\MUXED_DATA_Buffer_reg[53]_0 (ufc_barrel_shifter_i_n_101),
        .\MUXED_DATA_Buffer_reg[54]_0 (ufc_barrel_shifter_i_n_102),
        .\MUXED_DATA_Buffer_reg[55]_0 (ufc_barrel_shifter_i_n_103),
        .\MUXED_DATA_Buffer_reg[56]_0 (ufc_barrel_shifter_i_n_104),
        .\MUXED_DATA_Buffer_reg[57]_0 (ufc_barrel_shifter_i_n_105),
        .\MUXED_DATA_Buffer_reg[58]_0 (ufc_barrel_shifter_i_n_106),
        .\MUXED_DATA_Buffer_reg[59]_0 (ufc_barrel_shifter_i_n_107),
        .\MUXED_DATA_Buffer_reg[60]_0 (ufc_barrel_shifter_i_n_108),
        .\MUXED_DATA_Buffer_reg[61]_0 (ufc_barrel_shifter_i_n_109),
        .\MUXED_DATA_Buffer_reg[62]_0 (ufc_barrel_shifter_i_n_110),
        .\MUXED_DATA_Buffer_reg[63]_0 (ufc_barrel_shifter_i_n_111),
        .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
        .UFC_OUTPUT_SELECT_Buffer(UFC_OUTPUT_SELECT_Buffer[2]),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_OUTPUT_SWITCH_CONTROL ufc_output_switch_control_i
       (.MUXED_DATA_Buffer({MUXED_DATA_Buffer[16],MUXED_DATA_Buffer[17],MUXED_DATA_Buffer[18],MUXED_DATA_Buffer[19],MUXED_DATA_Buffer[20],MUXED_DATA_Buffer[21],MUXED_DATA_Buffer[22],MUXED_DATA_Buffer[23],MUXED_DATA_Buffer[24],MUXED_DATA_Buffer[25],MUXED_DATA_Buffer[26],MUXED_DATA_Buffer[27],MUXED_DATA_Buffer[28],MUXED_DATA_Buffer[29],MUXED_DATA_Buffer[30],MUXED_DATA_Buffer[31]}),
        .\MUXED_DATA_Buffer_reg[16] (ufc_output_switch_control_i_n_0),
        .\MUXED_DATA_Buffer_reg[17] (ufc_output_switch_control_i_n_6),
        .\MUXED_DATA_Buffer_reg[18] (ufc_output_switch_control_i_n_7),
        .\MUXED_DATA_Buffer_reg[19] (ufc_output_switch_control_i_n_8),
        .\MUXED_DATA_Buffer_reg[20] (ufc_output_switch_control_i_n_9),
        .\MUXED_DATA_Buffer_reg[21] (ufc_output_switch_control_i_n_10),
        .\MUXED_DATA_Buffer_reg[22] (ufc_output_switch_control_i_n_11),
        .\MUXED_DATA_Buffer_reg[23] (ufc_output_switch_control_i_n_12),
        .\MUXED_DATA_Buffer_reg[24] (ufc_output_switch_control_i_n_13),
        .\MUXED_DATA_Buffer_reg[25] (ufc_output_switch_control_i_n_14),
        .\MUXED_DATA_Buffer_reg[26] (ufc_output_switch_control_i_n_15),
        .\MUXED_DATA_Buffer_reg[27] (ufc_output_switch_control_i_n_16),
        .\MUXED_DATA_Buffer_reg[28] (ufc_output_switch_control_i_n_17),
        .\MUXED_DATA_Buffer_reg[29] (ufc_output_switch_control_i_n_18),
        .\MUXED_DATA_Buffer_reg[30] (ufc_output_switch_control_i_n_19),
        .\MUXED_DATA_Buffer_reg[31] (ufc_output_switch_control_i_n_20),
        .Q({SHIFTED_DATA_Buffer[0],SHIFTED_DATA_Buffer[1],SHIFTED_DATA_Buffer[2],SHIFTED_DATA_Buffer[3],SHIFTED_DATA_Buffer[4],SHIFTED_DATA_Buffer[5],SHIFTED_DATA_Buffer[6],SHIFTED_DATA_Buffer[7],SHIFTED_DATA_Buffer[8],SHIFTED_DATA_Buffer[9],SHIFTED_DATA_Buffer[10],SHIFTED_DATA_Buffer[11],SHIFTED_DATA_Buffer[12],SHIFTED_DATA_Buffer[13],SHIFTED_DATA_Buffer[14],SHIFTED_DATA_Buffer[15]}),
        .\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 (UFC_OUTPUT_SELECT_Buffer),
        .\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 ({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
        .\UFC_OUTPUT_SELECT_Buffer_reg[9]_0 (ufc_storage_count_control_i_n_4),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT ufc_sideband_output_i
       (.D({ufc_storage_count_control_i_n_6,ufc_storage_count_control_i_n_7}),
        .Q({ufc_sideband_output_i_n_2,ufc_sideband_output_i_n_3}),
        .RESET(RESET),
        .UFC_EOF_N_Buffer(UFC_EOF_N_Buffer),
        .UFC_EOF_N_Buffer_reg_0(ufc_storage_count_control_i_n_15),
        .UFC_SRC_RDY_N_Buffer(UFC_SRC_RDY_N_Buffer),
        .UFC_SRC_RDY_N_Buffer_reg_0(ufc_storage_count_control_i_n_4),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL ufc_storage_count_control_i
       (.D({ufc_storage_count_control_i_n_6,ufc_storage_count_control_i_n_7}),
        .Q({ufc_storage_count_control_i_n_1,storage_count_2x_c}),
        .RESET(RESET),
        .stage_1_ufc_start_r(stage_1_ufc_start_r),
        .\storage_count_r_reg[0]_0 (ufc_storage_count_control_i_n_4),
        .\storage_count_r_reg[0]_1 (ufc_storage_count_control_i_n_8),
        .\storage_count_r_reg[0]_2 ({ufc_storage_select_c[3],ufc_storage_select_c[4],ufc_storage_select_c[7],ufc_storage_select_c[8],ufc_storage_select_c[10],ufc_storage_select_c[11]}),
        .\storage_count_r_reg[0]_3 (ufc_storage_count_control_i_n_15),
        .\storage_count_r_reg[0]_4 (ufc_storage_count_control_i_n_16),
        .\storage_count_r_reg[0]_5 (ufc_storage_count_control_i_n_17),
        .\storage_count_r_reg[0]_6 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1],barrel_shifted_count_r[2]}),
        .\storage_count_r_reg[1]_0 (ufc_storage_count_control_i_n_0),
        .ufc_output_select_c0_in(ufc_output_select_c0_in),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_STORAGE_MUX ufc_storage_mux_i
       (.MUXED_DATA_Buffer(MUXED_DATA_Buffer),
        .\MUXED_DATA_Buffer_reg[0]_0 (ufc_barrel_shifter_i_n_17),
        .\MUXED_DATA_Buffer_reg[10]_0 (ufc_barrel_shifter_i_n_37),
        .\MUXED_DATA_Buffer_reg[11]_0 (ufc_barrel_shifter_i_n_39),
        .\MUXED_DATA_Buffer_reg[12]_0 (ufc_barrel_shifter_i_n_41),
        .\MUXED_DATA_Buffer_reg[13]_0 (ufc_barrel_shifter_i_n_43),
        .\MUXED_DATA_Buffer_reg[14]_0 (ufc_barrel_shifter_i_n_45),
        .\MUXED_DATA_Buffer_reg[15]_0 (ufc_barrel_shifter_i_n_47),
        .\MUXED_DATA_Buffer_reg[16]_0 (ufc_barrel_shifter_i_n_49),
        .\MUXED_DATA_Buffer_reg[17]_0 (ufc_barrel_shifter_i_n_51),
        .\MUXED_DATA_Buffer_reg[18]_0 (ufc_barrel_shifter_i_n_53),
        .\MUXED_DATA_Buffer_reg[19]_0 (ufc_barrel_shifter_i_n_55),
        .\MUXED_DATA_Buffer_reg[1]_0 (ufc_barrel_shifter_i_n_19),
        .\MUXED_DATA_Buffer_reg[20]_0 (ufc_barrel_shifter_i_n_57),
        .\MUXED_DATA_Buffer_reg[21]_0 (ufc_barrel_shifter_i_n_59),
        .\MUXED_DATA_Buffer_reg[22]_0 (ufc_barrel_shifter_i_n_61),
        .\MUXED_DATA_Buffer_reg[23]_0 (ufc_barrel_shifter_i_n_63),
        .\MUXED_DATA_Buffer_reg[24]_0 (ufc_barrel_shifter_i_n_65),
        .\MUXED_DATA_Buffer_reg[25]_0 (ufc_barrel_shifter_i_n_67),
        .\MUXED_DATA_Buffer_reg[26]_0 (ufc_barrel_shifter_i_n_69),
        .\MUXED_DATA_Buffer_reg[27]_0 (ufc_barrel_shifter_i_n_71),
        .\MUXED_DATA_Buffer_reg[28]_0 (ufc_barrel_shifter_i_n_73),
        .\MUXED_DATA_Buffer_reg[29]_0 (ufc_barrel_shifter_i_n_75),
        .\MUXED_DATA_Buffer_reg[2]_0 (ufc_barrel_shifter_i_n_21),
        .\MUXED_DATA_Buffer_reg[30]_0 (ufc_barrel_shifter_i_n_77),
        .\MUXED_DATA_Buffer_reg[31]_0 (ufc_barrel_shifter_i_n_79),
        .\MUXED_DATA_Buffer_reg[32]_0 (ufc_barrel_shifter_i_n_0),
        .\MUXED_DATA_Buffer_reg[33]_0 (ufc_barrel_shifter_i_n_18),
        .\MUXED_DATA_Buffer_reg[34]_0 (ufc_barrel_shifter_i_n_20),
        .\MUXED_DATA_Buffer_reg[35]_0 (ufc_barrel_shifter_i_n_22),
        .\MUXED_DATA_Buffer_reg[36]_0 (ufc_barrel_shifter_i_n_24),
        .\MUXED_DATA_Buffer_reg[37]_0 (ufc_barrel_shifter_i_n_26),
        .\MUXED_DATA_Buffer_reg[38]_0 (ufc_barrel_shifter_i_n_28),
        .\MUXED_DATA_Buffer_reg[39]_0 (ufc_barrel_shifter_i_n_30),
        .\MUXED_DATA_Buffer_reg[3]_0 (ufc_barrel_shifter_i_n_23),
        .\MUXED_DATA_Buffer_reg[40]_0 (ufc_barrel_shifter_i_n_32),
        .\MUXED_DATA_Buffer_reg[41]_0 (ufc_barrel_shifter_i_n_34),
        .\MUXED_DATA_Buffer_reg[42]_0 (ufc_barrel_shifter_i_n_36),
        .\MUXED_DATA_Buffer_reg[43]_0 (ufc_barrel_shifter_i_n_38),
        .\MUXED_DATA_Buffer_reg[44]_0 (ufc_barrel_shifter_i_n_40),
        .\MUXED_DATA_Buffer_reg[45]_0 (ufc_barrel_shifter_i_n_42),
        .\MUXED_DATA_Buffer_reg[46]_0 (ufc_barrel_shifter_i_n_44),
        .\MUXED_DATA_Buffer_reg[47]_0 (ufc_barrel_shifter_i_n_46),
        .\MUXED_DATA_Buffer_reg[48]_0 (ufc_barrel_shifter_i_n_48),
        .\MUXED_DATA_Buffer_reg[49]_0 (ufc_barrel_shifter_i_n_50),
        .\MUXED_DATA_Buffer_reg[4]_0 (ufc_barrel_shifter_i_n_25),
        .\MUXED_DATA_Buffer_reg[50]_0 (ufc_barrel_shifter_i_n_52),
        .\MUXED_DATA_Buffer_reg[51]_0 (ufc_barrel_shifter_i_n_54),
        .\MUXED_DATA_Buffer_reg[52]_0 (ufc_barrel_shifter_i_n_56),
        .\MUXED_DATA_Buffer_reg[53]_0 (ufc_barrel_shifter_i_n_58),
        .\MUXED_DATA_Buffer_reg[54]_0 (ufc_barrel_shifter_i_n_60),
        .\MUXED_DATA_Buffer_reg[55]_0 (ufc_barrel_shifter_i_n_62),
        .\MUXED_DATA_Buffer_reg[56]_0 (ufc_barrel_shifter_i_n_64),
        .\MUXED_DATA_Buffer_reg[57]_0 (ufc_barrel_shifter_i_n_66),
        .\MUXED_DATA_Buffer_reg[58]_0 (ufc_barrel_shifter_i_n_68),
        .\MUXED_DATA_Buffer_reg[59]_0 (ufc_barrel_shifter_i_n_70),
        .\MUXED_DATA_Buffer_reg[5]_0 (ufc_barrel_shifter_i_n_27),
        .\MUXED_DATA_Buffer_reg[60]_0 (ufc_barrel_shifter_i_n_72),
        .\MUXED_DATA_Buffer_reg[61]_0 (ufc_barrel_shifter_i_n_74),
        .\MUXED_DATA_Buffer_reg[62]_0 (ufc_barrel_shifter_i_n_76),
        .\MUXED_DATA_Buffer_reg[63]_0 (ufc_barrel_shifter_i_n_78),
        .\MUXED_DATA_Buffer_reg[6]_0 (ufc_barrel_shifter_i_n_29),
        .\MUXED_DATA_Buffer_reg[7]_0 (ufc_barrel_shifter_i_n_31),
        .\MUXED_DATA_Buffer_reg[8]_0 (ufc_barrel_shifter_i_n_33),
        .\MUXED_DATA_Buffer_reg[9]_0 (ufc_barrel_shifter_i_n_35),
        .UFC_STORAGE_SELECT_Buffer({UFC_STORAGE_SELECT_Buffer[0],UFC_STORAGE_SELECT_Buffer[3],UFC_STORAGE_SELECT_Buffer[6],UFC_STORAGE_SELECT_Buffer[9]}),
        .user_clk(user_clk));
  aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL ufc_storage_switch_control_i
       (.D({ufc_storage_select_c[3],ufc_storage_select_c[4],ufc_storage_select_c[7],ufc_storage_select_c[8],ufc_storage_select_c[10],ufc_storage_select_c[11]}),
        .UFC_STORAGE_SELECT_Buffer({UFC_STORAGE_SELECT_Buffer[0],UFC_STORAGE_SELECT_Buffer[1],UFC_STORAGE_SELECT_Buffer[3],UFC_STORAGE_SELECT_Buffer[4],UFC_STORAGE_SELECT_Buffer[6],UFC_STORAGE_SELECT_Buffer[7],UFC_STORAGE_SELECT_Buffer[8],UFC_STORAGE_SELECT_Buffer[9],UFC_STORAGE_SELECT_Buffer[10],UFC_STORAGE_SELECT_Buffer[11]}),
        .\UFC_STORAGE_SELECT_Buffer_reg[1]_0 (ufc_storage_count_control_i_n_0),
        .\UFC_STORAGE_SELECT_Buffer_reg[6]_0 (ufc_storage_count_control_i_n_16),
        .\UFC_STORAGE_SELECT_Buffer_reg[9]_0 (ufc_storage_count_control_i_n_17),
        .\UFC_STORAGE_SELECT_Buffer_reg[9]_1 (ufc_storage_count_control_i_n_8),
        .ufc_output_select_c0_in(ufc_output_select_c0_in),
        .user_clk(user_clk));
  aurora_rx_4l_64b_VALID_DATA_COUNTER ufc_valid_data_counter
       (.\COUNT_Buffer_reg[0]_0 ({barrel_shifted_count_r[0],barrel_shifted_count_r[1],barrel_shifted_count_r[2]}),
        .Q(Q),
        .RESET(RESET),
        .user_clk(user_clk));
endmodule

module aurora_rx_4l_64b_SIDEBAND_OUTPUT
   (stage_3_end_storage_r,
    stage_2_frame_err_r_reg,
    SRC_RDY_N_Buffer,
    EOF_N_Buffer,
    FRAME_ERR_RESULT_Buffer,
    stage_2_start_with_data_r_reg,
    SR,
    \RX_REM_Buffer_reg[0]_0 ,
    end_storage_r0,
    user_clk,
    EOF_N_Buffer_reg_0,
    FRAME_ERR_RESULT_Buffer0,
    stage_2_end_before_start_r,
    stage_2_start_with_data_r,
    pad_storage_r_reg_0,
    D,
    Q,
    \RX_REM_Buffer_reg[1]_0 ,
    stage_2_pad_r,
    stage_2_frame_err_r,
    start_rx_i);
  output stage_3_end_storage_r;
  output stage_2_frame_err_r_reg;
  output SRC_RDY_N_Buffer;
  output EOF_N_Buffer;
  output FRAME_ERR_RESULT_Buffer;
  output [0:0]stage_2_start_with_data_r_reg;
  output [0:0]SR;
  output [2:0]\RX_REM_Buffer_reg[0]_0 ;
  input end_storage_r0;
  input user_clk;
  input EOF_N_Buffer_reg_0;
  input FRAME_ERR_RESULT_Buffer0;
  input stage_2_end_before_start_r;
  input stage_2_start_with_data_r;
  input pad_storage_r_reg_0;
  input [0:0]D;
  input [0:0]Q;
  input [0:0]\RX_REM_Buffer_reg[1]_0 ;
  input stage_2_pad_r;
  input stage_2_frame_err_r;
  input start_rx_i;

  wire [0:0]D;
  wire EOF_N_Buffer;
  wire EOF_N_Buffer_reg_0;
  wire FRAME_ERR_RESULT_Buffer;
  wire FRAME_ERR_RESULT_Buffer0;
  wire [0:0]Q;
  wire [2:0]\RX_REM_Buffer_reg[0]_0 ;
  wire [0:0]\RX_REM_Buffer_reg[1]_0 ;
  wire [0:0]SR;
  wire SRC_RDY_N_Buffer;
  wire SRC_RDY_N_Buffer_i_1_n_0;
  wire end_storage_r0;
  wire pad_storage_r;
  wire pad_storage_r_i_1_n_0;
  wire pad_storage_r_reg_0;
  wire [1:0]rx_rem_c;
  wire stage_2_end_before_start_r;
  wire stage_2_frame_err_r;
  wire stage_2_frame_err_r_reg;
  wire stage_2_pad_r;
  wire stage_2_start_with_data_r;
  wire [0:0]stage_2_start_with_data_r_reg;
  wire stage_3_end_storage_r;
  wire start_rx_i;
  wire user_clk;

  FDRE EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(EOF_N_Buffer_reg_0),
        .Q(EOF_N_Buffer),
        .R(1'b0));
  FDRE FRAME_ERR_RESULT_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(FRAME_ERR_RESULT_Buffer0),
        .Q(FRAME_ERR_RESULT_Buffer),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \OUTPUT_SELECT_Buffer[13]_i_1 
       (.I0(stage_2_start_with_data_r),
        .I1(stage_3_end_storage_r),
        .O(SR));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT4 #(
    .INIT(16'h10EF)) 
    \RX_REM_Buffer[1]_i_1 
       (.I0(stage_2_start_with_data_r),
        .I1(stage_3_end_storage_r),
        .I2(Q),
        .I3(\RX_REM_Buffer_reg[1]_0 ),
        .O(rx_rem_c[1]));
  LUT4 #(
    .INIT(16'h00FD)) 
    \RX_REM_Buffer[2]_i_1 
       (.I0(stage_2_pad_r),
        .I1(stage_2_start_with_data_r),
        .I2(stage_3_end_storage_r),
        .I3(pad_storage_r),
        .O(rx_rem_c[0]));
  FDRE \RX_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(\RX_REM_Buffer_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_rem_c[1]),
        .Q(\RX_REM_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \RX_REM_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_rem_c[0]),
        .Q(\RX_REM_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h04FF)) 
    SRC_RDY_N_Buffer_i_1
       (.I0(stage_2_end_before_start_r),
        .I1(stage_2_start_with_data_r),
        .I2(stage_3_end_storage_r),
        .I3(pad_storage_r_reg_0),
        .O(SRC_RDY_N_Buffer_i_1_n_0));
  FDSE SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(SRC_RDY_N_Buffer_i_1_n_0),
        .Q(SRC_RDY_N_Buffer),
        .S(stage_2_frame_err_r_reg));
  FDRE end_storage_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(end_storage_r0),
        .Q(stage_3_end_storage_r),
        .R(stage_2_frame_err_r_reg));
  LUT6 #(
    .INIT(64'hBBBBBFBBAAAAAAAA)) 
    pad_storage_r_i_1
       (.I0(stage_2_pad_r),
        .I1(pad_storage_r_reg_0),
        .I2(stage_3_end_storage_r),
        .I3(stage_2_start_with_data_r),
        .I4(stage_2_end_before_start_r),
        .I5(pad_storage_r),
        .O(pad_storage_r_i_1_n_0));
  FDRE pad_storage_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(pad_storage_r_i_1_n_0),
        .Q(pad_storage_r),
        .R(stage_2_frame_err_r_reg));
  LUT2 #(
    .INIT(4'hB)) 
    \storage_count_r[0]_i_1__0 
       (.I0(stage_2_frame_err_r),
        .I1(start_rx_i),
        .O(stage_2_frame_err_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT4 #(
    .INIT(16'hEF10)) 
    \storage_count_r[2]_i_1__0 
       (.I0(stage_2_start_with_data_r),
        .I1(stage_3_end_storage_r),
        .I2(\RX_REM_Buffer_reg[1]_0 ),
        .I3(Q),
        .O(stage_2_start_with_data_r_reg));
endmodule

module aurora_rx_4l_64b_STORAGE_CE_CONTROL
   (Q,
    RESET,
    D,
    user_clk);
  output [3:0]Q;
  input RESET;
  input [3:0]D;
  input user_clk;

  wire [3:0]D;
  wire [3:0]Q;
  wire RESET;
  wire user_clk;

  FDRE \STORAGE_CE_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(RESET));
  FDRE \STORAGE_CE_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .R(RESET));
  FDRE \STORAGE_CE_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(RESET));
  FDRE \STORAGE_CE_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(RESET));
endmodule

module aurora_rx_4l_64b_STORAGE_COUNT_CONTROL
   (D,
    Q,
    end_storage_r_reg,
    stage_2_start_with_data_r_reg,
    FRAME_ERR_RESULT_Buffer0,
    end_storage_r0,
    \storage_count_r_reg[1]_0 ,
    \storage_count_r_reg[2]_0 ,
    \storage_count_r_reg[0]_0 ,
    \storage_count_r_reg[1]_1 ,
    \storage_count_r_reg[0]_1 ,
    stage_3_end_storage_r,
    stage_2_start_with_data_r,
    stage_2_frame_err_r,
    stage_2_end_after_start_r,
    stage_2_end_before_start_r,
    SR,
    user_clk);
  output [3:0]D;
  output [1:0]Q;
  output end_storage_r_reg;
  output [0:0]stage_2_start_with_data_r_reg;
  output FRAME_ERR_RESULT_Buffer0;
  output end_storage_r0;
  output [3:0]\storage_count_r_reg[1]_0 ;
  output \storage_count_r_reg[2]_0 ;
  output [2:0]\storage_count_r_reg[0]_0 ;
  input [1:0]\storage_count_r_reg[1]_1 ;
  input [2:0]\storage_count_r_reg[0]_1 ;
  input stage_3_end_storage_r;
  input stage_2_start_with_data_r;
  input stage_2_frame_err_r;
  input stage_2_end_after_start_r;
  input stage_2_end_before_start_r;
  input [0:0]SR;
  input user_clk;

  wire [3:0]D;
  wire FRAME_ERR_RESULT_Buffer0;
  wire FRAME_ERR_RESULT_Buffer_i_2_n_0;
  wire [1:0]Q;
  wire [0:0]SR;
  wire end_storage_r0;
  wire end_storage_r_i_2_n_0;
  wire end_storage_r_reg;
  wire stage_2_end_after_start_r;
  wire stage_2_end_before_start_r;
  wire stage_2_frame_err_r;
  wire stage_2_start_with_data_r;
  wire [0:0]stage_2_start_with_data_r_reg;
  wire stage_3_end_storage_r;
  wire [0:0]stage_3_storage_count_r;
  wire [0:0]storage_count_c;
  wire \storage_count_r[0]_i_4__0_n_0 ;
  wire \storage_count_r[0]_i_5_n_0 ;
  wire [2:0]\storage_count_r_reg[0]_0 ;
  wire [2:0]\storage_count_r_reg[0]_1 ;
  wire [3:0]\storage_count_r_reg[1]_0 ;
  wire [1:0]\storage_count_r_reg[1]_1 ;
  wire \storage_count_r_reg[2]_0 ;
  wire user_clk;

  LUT6 #(
    .INIT(64'h0000000001FFFFFF)) 
    EOF_N_Buffer_i_1
       (.I0(Q[0]),
        .I1(stage_3_storage_count_r),
        .I2(Q[1]),
        .I3(stage_2_start_with_data_r),
        .I4(stage_2_end_before_start_r),
        .I5(stage_3_end_storage_r),
        .O(\storage_count_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hCFCECFCCFFFECFCC)) 
    FRAME_ERR_RESULT_Buffer_i_1
       (.I0(end_storage_r_i_2_n_0),
        .I1(stage_2_frame_err_r),
        .I2(stage_2_start_with_data_r),
        .I3(stage_2_end_after_start_r),
        .I4(stage_2_end_before_start_r),
        .I5(FRAME_ERR_RESULT_Buffer_i_2_n_0),
        .O(FRAME_ERR_RESULT_Buffer0));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    FRAME_ERR_RESULT_Buffer_i_2
       (.I0(Q[0]),
        .I1(stage_3_storage_count_r),
        .I2(Q[1]),
        .O(FRAME_ERR_RESULT_Buffer_i_2_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    \OUTPUT_SELECT_Buffer[13]_i_2 
       (.I0(stage_3_storage_count_r),
        .I1(Q[1]),
        .O(\storage_count_r_reg[0]_0 [2]));
  LUT2 #(
    .INIT(4'h1)) 
    \OUTPUT_SELECT_Buffer[14]_i_1 
       (.I0(Q[0]),
        .I1(stage_3_storage_count_r),
        .O(\storage_count_r_reg[0]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'h13)) 
    \OUTPUT_SELECT_Buffer[18]_i_1 
       (.I0(Q[0]),
        .I1(stage_3_storage_count_r),
        .I2(Q[1]),
        .O(\storage_count_r_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'hE1F00F1EE1F01E0F)) 
    \RX_REM_Buffer[0]_i_1 
       (.I0(stage_2_start_with_data_r),
        .I1(stage_3_end_storage_r),
        .I2(Q[1]),
        .I3(\storage_count_r_reg[0]_1 [1]),
        .I4(Q[0]),
        .I5(\storage_count_r_reg[0]_1 [0]),
        .O(stage_2_start_with_data_r_reg));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \STORAGE_CE_Buffer[0]_i_1 
       (.I0(end_storage_r_reg),
        .I1(Q[1]),
        .I2(stage_3_storage_count_r),
        .I3(Q[0]),
        .O(D[3]));
  LUT3 #(
    .INIT(8'hAB)) 
    \STORAGE_CE_Buffer[1]_i_1 
       (.I0(end_storage_r_reg),
        .I1(stage_3_storage_count_r),
        .I2(Q[1]),
        .O(D[2]));
  LUT4 #(
    .INIT(16'hFF07)) 
    \STORAGE_CE_Buffer[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(stage_3_storage_count_r),
        .I3(end_storage_r_reg),
        .O(D[1]));
  LUT2 #(
    .INIT(4'hB)) 
    \STORAGE_CE_Buffer[3]_i_1 
       (.I0(end_storage_r_reg),
        .I1(stage_3_storage_count_r),
        .O(D[0]));
  LUT2 #(
    .INIT(4'h9)) 
    \STORAGE_SELECT_Buffer[13]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\storage_count_r_reg[1]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \STORAGE_SELECT_Buffer[18]_i_1 
       (.I0(Q[1]),
        .O(\storage_count_r_reg[1]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \STORAGE_SELECT_Buffer[19]_i_1 
       (.I0(Q[0]),
        .O(\storage_count_r_reg[1]_0 [0]));
  LUT2 #(
    .INIT(4'h6)) 
    \STORAGE_SELECT_Buffer[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\storage_count_r_reg[1]_0 [3]));
  LUT4 #(
    .INIT(16'h88B8)) 
    end_storage_r_i_1
       (.I0(stage_2_end_after_start_r),
        .I1(stage_2_start_with_data_r),
        .I2(stage_2_end_before_start_r),
        .I3(end_storage_r_i_2_n_0),
        .O(end_storage_r0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    end_storage_r_i_2
       (.I0(Q[1]),
        .I1(\storage_count_r_reg[0]_1 [1]),
        .I2(Q[0]),
        .I3(\storage_count_r_reg[0]_1 [0]),
        .I4(stage_3_storage_count_r),
        .I5(\storage_count_r_reg[0]_1 [2]),
        .O(end_storage_r_i_2_n_0));
  LUT6 #(
    .INIT(64'hF4F1F4F1F4F1D771)) 
    \storage_count_r[0]_i_2__0 
       (.I0(end_storage_r_reg),
        .I1(\storage_count_r[0]_i_4__0_n_0 ),
        .I2(\storage_count_r_reg[0]_1 [2]),
        .I3(stage_3_storage_count_r),
        .I4(stage_3_end_storage_r),
        .I5(stage_2_start_with_data_r),
        .O(storage_count_c));
  LUT6 #(
    .INIT(64'hFEEEFFFEFFFEFFFF)) 
    \storage_count_r[0]_i_3__0 
       (.I0(stage_3_end_storage_r),
        .I1(stage_2_start_with_data_r),
        .I2(stage_3_storage_count_r),
        .I3(\storage_count_r_reg[0]_1 [2]),
        .I4(\storage_count_r[0]_i_4__0_n_0 ),
        .I5(\storage_count_r[0]_i_5_n_0 ),
        .O(end_storage_r_reg));
  LUT4 #(
    .INIT(16'h1777)) 
    \storage_count_r[0]_i_4__0 
       (.I0(Q[1]),
        .I1(\storage_count_r_reg[0]_1 [1]),
        .I2(Q[0]),
        .I3(\storage_count_r_reg[0]_1 [0]),
        .O(\storage_count_r[0]_i_4__0_n_0 ));
  LUT4 #(
    .INIT(16'h6009)) 
    \storage_count_r[0]_i_5 
       (.I0(Q[1]),
        .I1(\storage_count_r_reg[0]_1 [1]),
        .I2(Q[0]),
        .I3(\storage_count_r_reg[0]_1 [0]),
        .O(\storage_count_r[0]_i_5_n_0 ));
  FDRE \storage_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(storage_count_c),
        .Q(stage_3_storage_count_r),
        .R(SR));
  FDRE \storage_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\storage_count_r_reg[1]_1 [1]),
        .Q(Q[1]),
        .R(SR));
  FDRE \storage_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\storage_count_r_reg[1]_1 [0]),
        .Q(Q[0]),
        .R(SR));
endmodule

module aurora_rx_4l_64b_STORAGE_MUX
   (Q,
    E,
    D,
    user_clk);
  output [63:0]Q;
  input [3:0]E;
  input [63:0]D;
  input user_clk;

  wire [63:0]D;
  wire [3:0]E;
  wire [63:0]Q;
  wire user_clk;

  FDRE \STORAGE_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[63]),
        .Q(Q[63]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[53]),
        .Q(Q[53]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[52]),
        .Q(Q[52]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[51]),
        .Q(Q[51]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[50]),
        .Q(Q[50]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[49]),
        .Q(Q[49]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[48]),
        .Q(Q[48]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[47]),
        .Q(Q[47]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[46]),
        .Q(Q[46]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[45]),
        .Q(Q[45]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[44]),
        .Q(Q[44]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[62]),
        .Q(Q[62]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[43]),
        .Q(Q[43]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[42]),
        .Q(Q[42]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[41]),
        .Q(Q[41]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[40]),
        .Q(Q[40]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[39]),
        .Q(Q[39]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[38]),
        .Q(Q[38]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[37]),
        .Q(Q[37]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[36]),
        .Q(Q[36]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[35]),
        .Q(Q[35]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[34]),
        .Q(Q[34]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[61]),
        .Q(Q[61]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[33]),
        .Q(Q[33]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(E[2]),
        .D(D[32]),
        .Q(Q[32]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[32] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[31]),
        .Q(Q[31]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[33] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[30]),
        .Q(Q[30]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[34] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[29]),
        .Q(Q[29]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[35] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[28]),
        .Q(Q[28]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[36] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[27]),
        .Q(Q[27]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[37] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[26]),
        .Q(Q[26]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[38] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[25]),
        .Q(Q[25]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[39] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[24]),
        .Q(Q[24]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[60]),
        .Q(Q[60]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[40] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[23]),
        .Q(Q[23]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[41] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[22]),
        .Q(Q[22]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[42] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[21]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[43] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[20]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[44] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[19]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[45] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[18]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[46] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[17]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[47] 
       (.C(user_clk),
        .CE(E[1]),
        .D(D[16]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[48] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[15]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[49] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[14]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[59]),
        .Q(Q[59]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[50] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[13]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[51] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[12]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[52] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[11]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[53] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[54] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[55] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[56] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[57] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[58] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[59] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[58]),
        .Q(Q[58]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[60] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[61] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[62] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[63] 
       (.C(user_clk),
        .CE(E[0]),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[57]),
        .Q(Q[57]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[56]),
        .Q(Q[56]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[55]),
        .Q(Q[55]),
        .R(1'b0));
  FDRE \STORAGE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(E[3]),
        .D(D[54]),
        .Q(Q[54]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_STORAGE_SWITCH_CONTROL
   (Q,
    SR,
    D,
    user_clk);
  output [4:0]Q;
  input [0:0]SR;
  input [4:0]D;
  input user_clk;

  wire [4:0]D;
  wire [4:0]Q;
  wire [0:0]SR;
  wire user_clk;

  FDSE \STORAGE_SELECT_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .S(SR));
  FDSE \STORAGE_SELECT_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .S(SR));
  FDSE \STORAGE_SELECT_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .S(SR));
  FDRE \STORAGE_SELECT_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[4]),
        .R(SR));
  FDRE \STORAGE_SELECT_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(SR));
endmodule

module aurora_rx_4l_64b_SYM_DEC
   (RX_NEG_Buffer,
    rx_sp_i,
    GOT_V_Buffer_reg_0,
    D,
    \RX_PE_DATA_Buffer_reg[9]_0 ,
    \RX_PE_DATA_Buffer_reg[8]_0 ,
    \RX_PE_DATA_Buffer_reg[10]_0 ,
    RX_SCP_Buffer_reg_0,
    RX_SUF_Buffer_reg_0,
    left_aligned_r_reg_0,
    RX_PE_DATA_V_Buffer_reg_0,
    RX_SUF_Buffer_reg_1,
    \RX_PE_DATA_Buffer_reg[9]_1 ,
    bad_as_r0,
    \GOT_A_Buffer_reg[0]_0 ,
    Q,
    \RX_PE_DATA_Buffer_reg[9]_2 ,
    \word_aligned_data_r_reg[11]_0 ,
    \word_aligned_data_r_reg[0]_0 ,
    first_v_received_r,
    std_bool26_out,
    RX_ECP_Buffer0,
    user_clk,
    \word_aligned_control_bits_r_reg[1]_0 ,
    \word_aligned_control_bits_r_reg[0]_0 ,
    SR,
    left_aligned_r_reg_1,
    \stage_1_count_value_r_reg[1] ,
    \stage_1_count_value_r_reg[1]_0 ,
    \stage_1_count_value_r_reg[2] ,
    RX_PE_DATA,
    \stage_1_count_value_r_reg[2]_0 ,
    GOT_A,
    bad_as_r_reg,
    bad_as_r_reg_0,
    bad_as_r_reg_1,
    bad_as_r_reg_2,
    \word_aligned_data_r_reg[8]_0 ,
    \word_aligned_data_r_reg[0]_1 );
  output RX_NEG_Buffer;
  output rx_sp_i;
  output GOT_V_Buffer_reg_0;
  output [0:0]D;
  output \RX_PE_DATA_Buffer_reg[9]_0 ;
  output \RX_PE_DATA_Buffer_reg[8]_0 ;
  output \RX_PE_DATA_Buffer_reg[10]_0 ;
  output [0:0]RX_SCP_Buffer_reg_0;
  output RX_SUF_Buffer_reg_0;
  output left_aligned_r_reg_0;
  output [0:0]RX_PE_DATA_V_Buffer_reg_0;
  output RX_SUF_Buffer_reg_1;
  output \RX_PE_DATA_Buffer_reg[9]_1 ;
  output bad_as_r0;
  output \GOT_A_Buffer_reg[0]_0 ;
  output [0:0]Q;
  output \RX_PE_DATA_Buffer_reg[9]_2 ;
  output [4:0]\word_aligned_data_r_reg[11]_0 ;
  output [7:0]\word_aligned_data_r_reg[0]_0 ;
  output first_v_received_r;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1]_0 ;
  input \word_aligned_control_bits_r_reg[0]_0 ;
  input [0:0]SR;
  input left_aligned_r_reg_1;
  input \stage_1_count_value_r_reg[1] ;
  input \stage_1_count_value_r_reg[1]_0 ;
  input \stage_1_count_value_r_reg[2] ;
  input [0:0]RX_PE_DATA;
  input \stage_1_count_value_r_reg[2]_0 ;
  input [0:1]GOT_A;
  input bad_as_r_reg;
  input bad_as_r_reg_0;
  input [0:0]bad_as_r_reg_1;
  input [0:0]bad_as_r_reg_2;
  input [7:0]\word_aligned_data_r_reg[8]_0 ;
  input [7:0]\word_aligned_data_r_reg[0]_1 ;

  wire [0:0]D;
  wire \EXP_IN_inferred__0/i__n_0 ;
  wire \EXP_IN_inferred__1/i__n_0 ;
  wire \EXP_IN_inferred__14/i__n_0 ;
  wire \EXP_IN_inferred__15/i__n_0 ;
  wire \EXP_IN_inferred__16/i__n_0 ;
  wire \EXP_IN_inferred__17/i__n_0 ;
  wire \EXP_IN_inferred__18/i__n_0 ;
  wire \EXP_IN_inferred__19/i__n_0 ;
  wire \EXP_IN_inferred__20/i__n_0 ;
  wire \EXP_IN_inferred__24/i__n_0 ;
  wire \EXP_IN_inferred__25/i__n_0 ;
  wire \EXP_IN_inferred__26/i__n_0 ;
  wire \EXP_IN_inferred__27/i__n_0 ;
  wire \EXP_IN_inferred__28/i__n_0 ;
  wire \EXP_IN_inferred__29/i__n_0 ;
  wire \EXP_IN_inferred__4/i__n_0 ;
  wire \EXP_IN_inferred__6/i__n_0 ;
  wire \EXP_IN_inferred__7/i__n_0 ;
  wire EXP_IN_n_0;
  wire [0:1]GOT_A;
  wire \GOT_A_Buffer[0]_i_1__2_n_0 ;
  wire \GOT_A_Buffer_reg[0]_0 ;
  wire GOT_V_Buffer_reg_0;
  wire [0:0]Q;
  wire RX_CC_Buffer_i_1__2_n_0;
  wire RX_ECP_Buffer0;
  wire RX_NEG_Buffer;
  wire RX_NEG_Buffer0;
  wire [0:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[10]_0 ;
  wire \RX_PE_DATA_Buffer_reg[8]_0 ;
  wire \RX_PE_DATA_Buffer_reg[9]_0 ;
  wire \RX_PE_DATA_Buffer_reg[9]_1 ;
  wire \RX_PE_DATA_Buffer_reg[9]_2 ;
  wire RX_PE_DATA_V_Buffer_i_1__2_n_0;
  wire [0:0]RX_PE_DATA_V_Buffer_reg_0;
  wire RX_SCP_Buffer_i_1__2_n_0;
  wire [0:0]RX_SCP_Buffer_reg_0;
  wire RX_SP_Buffer_i_2__2_n_0;
  wire RX_SUF_Buffer_reg_0;
  wire RX_SUF_Buffer_reg_1;
  wire [0:0]SR;
  wire bad_as_r0;
  wire bad_as_r_i_2_n_0;
  wire bad_as_r_reg;
  wire bad_as_r_reg_0;
  wire [0:0]bad_as_r_reg_1;
  wire [0:0]bad_as_r_reg_2;
  wire first_v_received_r;
  wire first_v_received_r_i_1__2_n_0;
  wire first_v_received_r_i_2__2_n_0;
  wire [0:3]got_a_d_r;
  wire got_v_c;
  wire left_aligned_r_reg_0;
  wire left_aligned_r_reg_1;
  wire [3:1]p_0_in;
  wire p_15_in;
  wire p_18_in;
  wire p_1_in;
  wire p_2_in;
  wire [0:0]p_3_out;
  wire [3:2]p_4_out;
  wire [0:0]prev_beat_sp_d_r;
  wire prev_beat_sp_r;
  wire prev_beat_sp_r_i_1__2_n_0;
  wire prev_beat_v_r;
  wire prev_beat_v_r_i_1__2_n_0;
  wire [1:3]rx_cc_r;
  wire \rx_ecp_d_r_reg_n_0_[3] ;
  wire [0:0]rx_pad_d_r;
  wire \rx_pe_control_r_reg_n_0_[1] ;
  wire [8:10]rx_pe_data_r;
  wire \rx_scp_d_r_reg_n_0_[2] ;
  wire \rx_scp_d_r_reg_n_0_[3] ;
  wire rx_sp_c;
  wire [0:3]rx_sp_d_r;
  wire rx_sp_i;
  wire [0:1]rx_sp_neg_d_r;
  wire [0:1]rx_spa_neg_d_r;
  wire \rx_suf_d_r_reg_n_0_[0] ;
  wire [0:3]rx_v_d_r;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[1]_0 ;
  wire \stage_1_count_value_r_reg[2] ;
  wire \stage_1_count_value_r_reg[2]_0 ;
  wire std_bool;
  wire std_bool10_in;
  wire std_bool12_out;
  wire std_bool26_out;
  wire std_bool4_in;
  wire std_bool7_in;
  wire std_bool9_out;
  wire user_clk;
  wire [0:1]word_aligned_control_bits_r;
  wire \word_aligned_control_bits_r_reg[0]_0 ;
  wire \word_aligned_control_bits_r_reg[1]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_1 ;
  wire [4:0]\word_aligned_data_r_reg[11]_0 ;
  wire [7:0]\word_aligned_data_r_reg[8]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    EXP_IN
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [1]),
        .I2(\word_aligned_data_r_reg[11]_0 [3]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(EXP_IN_n_0));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__0/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [4]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(p_0_in[1]),
        .O(\EXP_IN_inferred__0/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \EXP_IN_inferred__1/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [1]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__1/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \EXP_IN_inferred__10/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [0]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [3]),
        .O(std_bool9_out));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__11/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[3]),
        .I2(p_0_in[1]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(std_bool10_in));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \EXP_IN_inferred__12/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [4]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(p_0_in[2]),
        .O(std_bool12_out));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__14/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [3]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__14/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__15/i_ 
       (.I0(p_0_in[1]),
        .I1(\word_aligned_data_r_reg[11]_0 [4]),
        .I2(p_0_in[2]),
        .I3(p_0_in[3]),
        .O(\EXP_IN_inferred__15/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__16/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__16/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__17/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [0]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [3]),
        .I3(\word_aligned_data_r_reg[11]_0 [1]),
        .O(\EXP_IN_inferred__17/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__18/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__18/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__19/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [5]),
        .I1(\word_aligned_data_r_reg[0]_0 [4]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [7]),
        .O(\EXP_IN_inferred__19/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__2/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [5]),
        .O(std_bool));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__20/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__20/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__24/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [3]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__24/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__25/i_ 
       (.I0(p_0_in[1]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__25/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__26/i_ 
       (.I0(p_0_in[3]),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__26/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__27/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__27/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__28/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [3]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__28/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__29/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [3]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__29/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__3/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [7]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(std_bool4_in));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__4/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [2]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(\EXP_IN_inferred__4/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__6/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [1]),
        .I1(\word_aligned_data_r_reg[11]_0 [0]),
        .I2(\word_aligned_data_r_reg[11]_0 [2]),
        .I3(\word_aligned_data_r_reg[11]_0 [3]),
        .O(\EXP_IN_inferred__6/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__7/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__7/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__9/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [3]),
        .I1(\word_aligned_data_r_reg[11]_0 [1]),
        .I2(\word_aligned_data_r_reg[11]_0 [2]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(std_bool7_in));
  LUT2 #(
    .INIT(4'h7)) 
    \GOT_A_Buffer[0]_i_1__2 
       (.I0(got_a_d_r[1]),
        .I1(p_2_in),
        .O(\GOT_A_Buffer[0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \GOT_A_Buffer[1]_i_1__2 
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(got_a_d_r[3]),
        .I2(got_a_d_r[2]),
        .O(p_3_out));
  FDRE \GOT_A_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(got_a_d_r[0]),
        .Q(\GOT_A_Buffer_reg[0]_0 ),
        .R(\GOT_A_Buffer[0]_i_1__2_n_0 ));
  FDRE \GOT_A_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_3_out),
        .Q(Q),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h01)) 
    GOT_V_Buffer_i_1__2
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(first_v_received_r_i_2__2_n_0),
        .O(got_v_c));
  FDRE GOT_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(got_v_c),
        .Q(GOT_V_Buffer_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    RX_CC_Buffer_i_1__2
       (.I0(rx_cc_r[1]),
        .I1(p_15_in),
        .I2(rx_cc_r[3]),
        .I3(\rx_scp_d_r_reg_n_0_[2] ),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_CC_Buffer_i_1__2_n_0));
  FDRE RX_CC_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_CC_Buffer_i_1__2_n_0),
        .Q(D),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0F080808)) 
    RX_NEG_Buffer_i_1__2
       (.I0(rx_sp_neg_d_r[1]),
        .I1(rx_sp_neg_d_r[0]),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(rx_spa_neg_d_r[1]),
        .I4(rx_spa_neg_d_r[0]),
        .O(RX_NEG_Buffer0));
  FDRE RX_NEG_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_NEG_Buffer0),
        .Q(RX_NEG_Buffer),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[10]),
        .Q(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[8]),
        .Q(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[9]),
        .Q(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0F08)) 
    RX_PE_DATA_V_Buffer_i_1__2
       (.I0(RX_SP_Buffer_i_2__2_n_0),
        .I1(first_v_received_r_i_2__2_n_0),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_PE_DATA_V_Buffer_i_1__2_n_0));
  FDRE RX_PE_DATA_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_PE_DATA_V_Buffer_i_1__2_n_0),
        .Q(RX_PE_DATA_V_Buffer_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    RX_SCP_Buffer_i_1__2
       (.I0(\rx_scp_d_r_reg_n_0_[3] ),
        .I1(\rx_scp_d_r_reg_n_0_[2] ),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(p_18_in),
        .O(RX_SCP_Buffer_i_1__2_n_0));
  FDRE RX_SCP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_SCP_Buffer_i_1__2_n_0),
        .Q(RX_SCP_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    RX_SP_Buffer_i_1__2
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(RX_SP_Buffer_i_2__2_n_0),
        .O(rx_sp_c));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    RX_SP_Buffer_i_2__2
       (.I0(prev_beat_sp_r),
        .I1(rx_sp_d_r[3]),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[0]),
        .I4(rx_sp_d_r[1]),
        .O(RX_SP_Buffer_i_2__2_n_0));
  FDRE RX_SP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_sp_c),
        .Q(rx_sp_i),
        .R(1'b0));
  FDRE RX_SUF_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_d_r_reg_n_0_[0] ),
        .Q(RX_SUF_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFE)) 
    bad_as_r_i_1
       (.I0(GOT_A[0]),
        .I1(bad_as_r_reg),
        .I2(bad_as_r_reg_0),
        .I3(\GOT_A_Buffer_reg[0]_0 ),
        .I4(bad_as_r_i_2_n_0),
        .O(bad_as_r0));
  LUT4 #(
    .INIT(16'h7FFE)) 
    bad_as_r_i_2
       (.I0(Q),
        .I1(bad_as_r_reg_1),
        .I2(bad_as_r_reg_2),
        .I3(GOT_A[1]),
        .O(bad_as_r_i_2_n_0));
  LUT4 #(
    .INIT(16'hFF01)) 
    first_v_received_r_i_1__2
       (.I0(first_v_received_r_i_2__2_n_0),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(p_2_in),
        .I3(first_v_received_r),
        .O(first_v_received_r_i_1__2_n_0));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    first_v_received_r_i_2__2
       (.I0(prev_beat_v_r),
        .I1(rx_v_d_r[3]),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[0]),
        .I4(rx_v_d_r[1]),
        .O(first_v_received_r_i_2__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    first_v_received_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(first_v_received_r_i_1__2_n_0),
        .Q(first_v_received_r),
        .R(SR));
  FDRE \got_a_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__27/i__n_0 ),
        .Q(got_a_d_r[0]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__4/i__n_0 ),
        .Q(got_a_d_r[1]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__26/i__n_0 ),
        .Q(got_a_d_r[2]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__6/i__n_0 ),
        .Q(got_a_d_r[3]),
        .R(1'b0));
  FDRE left_aligned_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(left_aligned_r_reg_1),
        .Q(left_aligned_r_reg_0),
        .R(SR));
  FDRE \prev_beat_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool4_in),
        .Q(prev_beat_sp_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_sp_r_i_1__2
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[3]),
        .O(prev_beat_sp_r_i_1__2_n_0));
  FDRE prev_beat_sp_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_sp_r_i_1__2_n_0),
        .Q(prev_beat_sp_r),
        .R(\GOT_A_Buffer[0]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_v_r_i_1__2
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[3]),
        .O(prev_beat_v_r_i_1__2_n_0));
  FDRE prev_beat_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_v_r_i_1__2_n_0),
        .Q(prev_beat_v_r),
        .R(\GOT_A_Buffer[0]_i_1__2_n_0 ));
  FDRE \rx_cc_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__29/i__n_0 ),
        .Q(rx_cc_r[1]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__28/i__n_0 ),
        .Q(rx_cc_r[3]),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__19/i__n_0 ),
        .Q(p_15_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__18/i__n_0 ),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__17/i__n_0 ),
        .Q(\rx_ecp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_ecp_r_reg[3]_srl2_i_1 
       (.I0(\rx_scp_d_r_reg_n_0_[2] ),
        .I1(p_15_in),
        .I2(\rx_ecp_d_r_reg_n_0_[3] ),
        .I3(p_1_in),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_ECP_Buffer0));
  FDRE \rx_pad_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__7/i__n_0 ),
        .Q(rx_pad_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0800)) 
    \rx_pad_r_reg[3]_srl2_i_1 
       (.I0(rx_pad_d_r),
        .I1(got_a_d_r[3]),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(std_bool26_out));
  FDRE \rx_pe_control_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[0]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \rx_pe_control_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[1]),
        .Q(\rx_pe_control_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(rx_pe_data_r[10]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(rx_pe_data_r[8]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(rx_pe_data_r[9]),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__16/i__n_0 ),
        .Q(p_18_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__15/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__14/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \rx_sp_d_r[0]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [6]),
        .O(p_4_out[3]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \rx_sp_d_r[1]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(p_4_out[2]));
  FDRE \rx_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[3]),
        .Q(rx_sp_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[2]),
        .Q(rx_sp_d_r[1]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool12_out),
        .Q(rx_sp_d_r[2]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool9_out),
        .Q(rx_sp_d_r[3]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool10_in),
        .Q(rx_sp_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool7_in),
        .Q(rx_sp_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__25/i__n_0 ),
        .Q(rx_spa_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__24/i__n_0 ),
        .Q(rx_spa_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_suf_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__20/i__n_0 ),
        .Q(\rx_suf_d_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool),
        .Q(rx_v_d_r[0]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__1/i__n_0 ),
        .Q(rx_v_d_r[1]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__0/i__n_0 ),
        .Q(rx_v_d_r[2]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(EXP_IN_n_0),
        .Q(rx_v_d_r[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    \stage_1_count_value_r[0]_i_1 
       (.I0(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I1(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I2(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I3(RX_SUF_Buffer_reg_0),
        .O(\RX_PE_DATA_Buffer_reg[9]_2 ));
  LUT6 #(
    .INIT(64'h0BFBFBFBFB0B0B0B)) 
    \stage_1_count_value_r[1]_i_1 
       (.I0(\stage_1_count_value_r_reg[1] ),
        .I1(\stage_1_count_value_r_reg[1]_0 ),
        .I2(RX_SUF_Buffer_reg_0),
        .I3(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I4(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I5(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .O(RX_SUF_Buffer_reg_1));
  LUT6 #(
    .INIT(64'h00ABFFABFFAB00AB)) 
    \stage_1_count_value_r[2]_i_1 
       (.I0(\stage_1_count_value_r_reg[2] ),
        .I1(RX_PE_DATA),
        .I2(\stage_1_count_value_r_reg[2]_0 ),
        .I3(RX_SUF_Buffer_reg_0),
        .I4(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I5(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .O(\RX_PE_DATA_Buffer_reg[9]_1 ));
  FDRE \word_aligned_control_bits_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[0]_0 ),
        .Q(word_aligned_control_bits_r[0]),
        .R(1'b0));
  FDRE \word_aligned_control_bits_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[1]_0 ),
        .Q(word_aligned_control_bits_r[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [7]),
        .Q(\word_aligned_data_r_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [5]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [4]),
        .Q(\word_aligned_data_r_reg[11]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [3]),
        .Q(\word_aligned_data_r_reg[11]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [2]),
        .Q(\word_aligned_data_r_reg[11]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [1]),
        .Q(\word_aligned_data_r_reg[11]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [0]),
        .Q(\word_aligned_data_r_reg[11]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [6]),
        .Q(\word_aligned_data_r_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [5]),
        .Q(\word_aligned_data_r_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [4]),
        .Q(\word_aligned_data_r_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [3]),
        .Q(\word_aligned_data_r_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [2]),
        .Q(\word_aligned_data_r_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [1]),
        .Q(\word_aligned_data_r_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [0]),
        .Q(\word_aligned_data_r_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [7]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [6]),
        .Q(p_0_in[2]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_SYM_DEC" *) 
module aurora_rx_4l_64b_SYM_DEC_14
   (RX_NEG_Buffer,
    rx_sp_i,
    GOT_V_Buffer_reg_0,
    D,
    \RX_PE_DATA_Buffer_reg[9]_0 ,
    \RX_PE_DATA_Buffer_reg[8]_0 ,
    \RX_PE_DATA_Buffer_reg[10]_0 ,
    RX_SCP_Buffer_reg_0,
    RX_SUF_Buffer_reg_0,
    left_aligned_r_reg_0,
    RX_PE_DATA_V_Buffer_reg_0,
    \RX_PE_DATA_Buffer_reg[10]_1 ,
    RX_SUF_Buffer_reg_1,
    \RX_PE_DATA_Buffer_reg[10]_2 ,
    \RX_PE_DATA_Buffer_reg[10]_3 ,
    Q,
    \word_aligned_data_r_reg[0]_0 ,
    first_v_received_r,
    \GOT_A_Buffer_reg[1]_0 ,
    \GOT_A_Buffer_reg[0]_0 ,
    std_bool26_out,
    RX_ECP_Buffer0,
    user_clk,
    \word_aligned_control_bits_r_reg[1]_0 ,
    \word_aligned_control_bits_r_reg[0]_0 ,
    SR,
    left_aligned_r_reg_1,
    \stage_1_count_value_r_reg[1] ,
    RX_SUF,
    \stage_1_count_value_r_reg[2] ,
    \word_aligned_data_r_reg[8]_0 ,
    \word_aligned_data_r_reg[0]_1 );
  output RX_NEG_Buffer;
  output rx_sp_i;
  output GOT_V_Buffer_reg_0;
  output [0:0]D;
  output \RX_PE_DATA_Buffer_reg[9]_0 ;
  output \RX_PE_DATA_Buffer_reg[8]_0 ;
  output \RX_PE_DATA_Buffer_reg[10]_0 ;
  output [0:0]RX_SCP_Buffer_reg_0;
  output RX_SUF_Buffer_reg_0;
  output left_aligned_r_reg_0;
  output [0:0]RX_PE_DATA_V_Buffer_reg_0;
  output \RX_PE_DATA_Buffer_reg[10]_1 ;
  output RX_SUF_Buffer_reg_1;
  output \RX_PE_DATA_Buffer_reg[10]_2 ;
  output \RX_PE_DATA_Buffer_reg[10]_3 ;
  output [4:0]Q;
  output [7:0]\word_aligned_data_r_reg[0]_0 ;
  output first_v_received_r;
  output [0:0]\GOT_A_Buffer_reg[1]_0 ;
  output \GOT_A_Buffer_reg[0]_0 ;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1]_0 ;
  input \word_aligned_control_bits_r_reg[0]_0 ;
  input [0:0]SR;
  input left_aligned_r_reg_1;
  input \stage_1_count_value_r_reg[1] ;
  input RX_SUF;
  input \stage_1_count_value_r_reg[2] ;
  input [7:0]\word_aligned_data_r_reg[8]_0 ;
  input [7:0]\word_aligned_data_r_reg[0]_1 ;

  wire [0:0]D;
  wire \EXP_IN_inferred__0/i__n_0 ;
  wire \EXP_IN_inferred__1/i__n_0 ;
  wire \EXP_IN_inferred__14/i__n_0 ;
  wire \EXP_IN_inferred__15/i__n_0 ;
  wire \EXP_IN_inferred__16/i__n_0 ;
  wire \EXP_IN_inferred__17/i__n_0 ;
  wire \EXP_IN_inferred__18/i__n_0 ;
  wire \EXP_IN_inferred__19/i__n_0 ;
  wire \EXP_IN_inferred__20/i__n_0 ;
  wire \EXP_IN_inferred__24/i__n_0 ;
  wire \EXP_IN_inferred__25/i__n_0 ;
  wire \EXP_IN_inferred__26/i__n_0 ;
  wire \EXP_IN_inferred__27/i__n_0 ;
  wire \EXP_IN_inferred__28/i__n_0 ;
  wire \EXP_IN_inferred__29/i__n_0 ;
  wire \EXP_IN_inferred__4/i__n_0 ;
  wire \EXP_IN_inferred__6/i__n_0 ;
  wire \EXP_IN_inferred__7/i__n_0 ;
  wire EXP_IN_n_0;
  wire \GOT_A_Buffer[0]_i_1__0_n_0 ;
  wire \GOT_A_Buffer_reg[0]_0 ;
  wire [0:0]\GOT_A_Buffer_reg[1]_0 ;
  wire GOT_V_Buffer_reg_0;
  wire [4:0]Q;
  wire RX_CC_Buffer_i_1__0_n_0;
  wire RX_ECP_Buffer0;
  wire RX_NEG_Buffer;
  wire RX_NEG_Buffer0;
  wire \RX_PE_DATA_Buffer_reg[10]_0 ;
  wire \RX_PE_DATA_Buffer_reg[10]_1 ;
  wire \RX_PE_DATA_Buffer_reg[10]_2 ;
  wire \RX_PE_DATA_Buffer_reg[10]_3 ;
  wire \RX_PE_DATA_Buffer_reg[8]_0 ;
  wire \RX_PE_DATA_Buffer_reg[9]_0 ;
  wire RX_PE_DATA_V_Buffer_i_1__0_n_0;
  wire [0:0]RX_PE_DATA_V_Buffer_reg_0;
  wire RX_SCP_Buffer_i_1__0_n_0;
  wire [0:0]RX_SCP_Buffer_reg_0;
  wire RX_SP_Buffer_i_2__0_n_0;
  wire RX_SUF;
  wire RX_SUF_Buffer_reg_0;
  wire RX_SUF_Buffer_reg_1;
  wire [0:0]SR;
  wire first_v_received_r;
  wire first_v_received_r_i_1__0_n_0;
  wire first_v_received_r_i_2__0_n_0;
  wire [0:3]got_a_d_r;
  wire got_v_c;
  wire left_aligned_r_reg_0;
  wire left_aligned_r_reg_1;
  wire [3:1]p_0_in;
  wire p_15_in;
  wire p_18_in;
  wire p_1_in;
  wire p_2_in;
  wire [0:0]p_3_out;
  wire [3:2]p_4_out;
  wire [0:0]prev_beat_sp_d_r;
  wire prev_beat_sp_r;
  wire prev_beat_sp_r_i_1__0_n_0;
  wire prev_beat_v_r;
  wire prev_beat_v_r_i_1__0_n_0;
  wire [1:3]rx_cc_r;
  wire \rx_ecp_d_r_reg_n_0_[3] ;
  wire [0:0]rx_pad_d_r;
  wire \rx_pe_control_r_reg_n_0_[1] ;
  wire [8:10]rx_pe_data_r;
  wire \rx_scp_d_r_reg_n_0_[2] ;
  wire \rx_scp_d_r_reg_n_0_[3] ;
  wire rx_sp_c;
  wire [0:3]rx_sp_d_r;
  wire rx_sp_i;
  wire [0:1]rx_sp_neg_d_r;
  wire [0:1]rx_spa_neg_d_r;
  wire \rx_suf_d_r_reg_n_0_[0] ;
  wire [0:3]rx_v_d_r;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[2] ;
  wire std_bool;
  wire std_bool10_in;
  wire std_bool12_out;
  wire std_bool26_out;
  wire std_bool4_in;
  wire std_bool7_in;
  wire std_bool9_out;
  wire user_clk;
  wire [0:1]word_aligned_control_bits_r;
  wire \word_aligned_control_bits_r_reg[0]_0 ;
  wire \word_aligned_control_bits_r_reg[1]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_1 ;
  wire [7:0]\word_aligned_data_r_reg[8]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    EXP_IN
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[3]),
        .I3(Q[0]),
        .O(EXP_IN_n_0));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__0/i_ 
       (.I0(Q[4]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(p_0_in[1]),
        .O(\EXP_IN_inferred__0/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \EXP_IN_inferred__1/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [1]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__1/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \EXP_IN_inferred__10/i_ 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[3]),
        .O(std_bool9_out));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__11/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[3]),
        .I2(p_0_in[1]),
        .I3(Q[4]),
        .O(std_bool10_in));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \EXP_IN_inferred__12/i_ 
       (.I0(Q[4]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(p_0_in[2]),
        .O(std_bool12_out));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__14/i_ 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\EXP_IN_inferred__14/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__15/i_ 
       (.I0(p_0_in[1]),
        .I1(Q[4]),
        .I2(p_0_in[2]),
        .I3(p_0_in[3]),
        .O(\EXP_IN_inferred__15/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__16/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__16/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__17/i_ 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(Q[1]),
        .O(\EXP_IN_inferred__17/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__18/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__18/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__19/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [5]),
        .I1(\word_aligned_data_r_reg[0]_0 [4]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [7]),
        .O(\EXP_IN_inferred__19/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__2/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [5]),
        .O(std_bool));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__20/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__20/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__24/i_ 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\EXP_IN_inferred__24/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__25/i_ 
       (.I0(p_0_in[1]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(Q[4]),
        .O(\EXP_IN_inferred__25/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__26/i_ 
       (.I0(p_0_in[3]),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(Q[4]),
        .O(\EXP_IN_inferred__26/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__27/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__27/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__28/i_ 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\EXP_IN_inferred__28/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__29/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [3]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__29/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__3/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [7]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(std_bool4_in));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__4/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [2]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(\EXP_IN_inferred__4/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__6/i_ 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\EXP_IN_inferred__6/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__7/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(Q[4]),
        .O(\EXP_IN_inferred__7/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__9/i_ 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[0]),
        .O(std_bool7_in));
  LUT2 #(
    .INIT(4'h7)) 
    \GOT_A_Buffer[0]_i_1__0 
       (.I0(got_a_d_r[1]),
        .I1(p_2_in),
        .O(\GOT_A_Buffer[0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \GOT_A_Buffer[1]_i_1__0 
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(got_a_d_r[3]),
        .I2(got_a_d_r[2]),
        .O(p_3_out));
  FDRE \GOT_A_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(got_a_d_r[0]),
        .Q(\GOT_A_Buffer_reg[0]_0 ),
        .R(\GOT_A_Buffer[0]_i_1__0_n_0 ));
  FDRE \GOT_A_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_3_out),
        .Q(\GOT_A_Buffer_reg[1]_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h01)) 
    GOT_V_Buffer_i_1__0
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(first_v_received_r_i_2__0_n_0),
        .O(got_v_c));
  FDRE GOT_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(got_v_c),
        .Q(GOT_V_Buffer_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    RX_CC_Buffer_i_1__0
       (.I0(rx_cc_r[1]),
        .I1(p_15_in),
        .I2(rx_cc_r[3]),
        .I3(\rx_scp_d_r_reg_n_0_[2] ),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_CC_Buffer_i_1__0_n_0));
  FDRE RX_CC_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_CC_Buffer_i_1__0_n_0),
        .Q(D),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0F080808)) 
    RX_NEG_Buffer_i_1__0
       (.I0(rx_sp_neg_d_r[1]),
        .I1(rx_sp_neg_d_r[0]),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(rx_spa_neg_d_r[1]),
        .I4(rx_spa_neg_d_r[0]),
        .O(RX_NEG_Buffer0));
  FDRE RX_NEG_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_NEG_Buffer0),
        .Q(RX_NEG_Buffer),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[10]),
        .Q(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[8]),
        .Q(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[9]),
        .Q(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0F08)) 
    RX_PE_DATA_V_Buffer_i_1__0
       (.I0(RX_SP_Buffer_i_2__0_n_0),
        .I1(first_v_received_r_i_2__0_n_0),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_PE_DATA_V_Buffer_i_1__0_n_0));
  FDRE RX_PE_DATA_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_PE_DATA_V_Buffer_i_1__0_n_0),
        .Q(RX_PE_DATA_V_Buffer_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    RX_SCP_Buffer_i_1__0
       (.I0(\rx_scp_d_r_reg_n_0_[3] ),
        .I1(\rx_scp_d_r_reg_n_0_[2] ),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(p_18_in),
        .O(RX_SCP_Buffer_i_1__0_n_0));
  FDRE RX_SCP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_SCP_Buffer_i_1__0_n_0),
        .Q(RX_SCP_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    RX_SP_Buffer_i_1__0
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(RX_SP_Buffer_i_2__0_n_0),
        .O(rx_sp_c));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    RX_SP_Buffer_i_2__0
       (.I0(prev_beat_sp_r),
        .I1(rx_sp_d_r[3]),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[0]),
        .I4(rx_sp_d_r[1]),
        .O(RX_SP_Buffer_i_2__0_n_0));
  FDRE RX_SP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_sp_c),
        .Q(rx_sp_i),
        .R(1'b0));
  FDRE RX_SUF_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_d_r_reg_n_0_[0] ),
        .Q(RX_SUF_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFF01)) 
    first_v_received_r_i_1__0
       (.I0(first_v_received_r_i_2__0_n_0),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(p_2_in),
        .I3(first_v_received_r),
        .O(first_v_received_r_i_1__0_n_0));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    first_v_received_r_i_2__0
       (.I0(prev_beat_v_r),
        .I1(rx_v_d_r[3]),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[0]),
        .I4(rx_v_d_r[1]),
        .O(first_v_received_r_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    first_v_received_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(first_v_received_r_i_1__0_n_0),
        .Q(first_v_received_r),
        .R(SR));
  FDRE \got_a_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__27/i__n_0 ),
        .Q(got_a_d_r[0]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__4/i__n_0 ),
        .Q(got_a_d_r[1]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__26/i__n_0 ),
        .Q(got_a_d_r[2]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__6/i__n_0 ),
        .Q(got_a_d_r[3]),
        .R(1'b0));
  FDRE left_aligned_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(left_aligned_r_reg_1),
        .Q(left_aligned_r_reg_0),
        .R(SR));
  FDRE \prev_beat_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool4_in),
        .Q(prev_beat_sp_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_sp_r_i_1__0
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[3]),
        .O(prev_beat_sp_r_i_1__0_n_0));
  FDRE prev_beat_sp_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_sp_r_i_1__0_n_0),
        .Q(prev_beat_sp_r),
        .R(\GOT_A_Buffer[0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_v_r_i_1__0
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[3]),
        .O(prev_beat_v_r_i_1__0_n_0));
  FDRE prev_beat_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_v_r_i_1__0_n_0),
        .Q(prev_beat_v_r),
        .R(\GOT_A_Buffer[0]_i_1__0_n_0 ));
  FDRE \rx_cc_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__29/i__n_0 ),
        .Q(rx_cc_r[1]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__28/i__n_0 ),
        .Q(rx_cc_r[3]),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__19/i__n_0 ),
        .Q(p_15_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__18/i__n_0 ),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__17/i__n_0 ),
        .Q(\rx_ecp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_ecp_r_reg[1]_srl2_i_1 
       (.I0(\rx_scp_d_r_reg_n_0_[2] ),
        .I1(p_15_in),
        .I2(\rx_ecp_d_r_reg_n_0_[3] ),
        .I3(p_1_in),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_ECP_Buffer0));
  FDRE \rx_pad_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__7/i__n_0 ),
        .Q(rx_pad_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0800)) 
    \rx_pad_r_reg[1]_srl2_i_1 
       (.I0(rx_pad_d_r),
        .I1(got_a_d_r[3]),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(std_bool26_out));
  FDRE \rx_pe_control_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[0]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \rx_pe_control_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[1]),
        .Q(\rx_pe_control_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(rx_pe_data_r[10]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(rx_pe_data_r[8]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(rx_pe_data_r[9]),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__16/i__n_0 ),
        .Q(p_18_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__15/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__14/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \rx_sp_d_r[0]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [6]),
        .O(p_4_out[3]));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \rx_sp_d_r[1]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(p_4_out[2]));
  FDRE \rx_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[3]),
        .Q(rx_sp_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[2]),
        .Q(rx_sp_d_r[1]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool12_out),
        .Q(rx_sp_d_r[2]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool9_out),
        .Q(rx_sp_d_r[3]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool10_in),
        .Q(rx_sp_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool7_in),
        .Q(rx_sp_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__25/i__n_0 ),
        .Q(rx_spa_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__24/i__n_0 ),
        .Q(rx_spa_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_suf_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__20/i__n_0 ),
        .Q(\rx_suf_d_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool),
        .Q(rx_v_d_r[0]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__1/i__n_0 ),
        .Q(rx_v_d_r[1]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__0/i__n_0 ),
        .Q(rx_v_d_r[2]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(EXP_IN_n_0),
        .Q(rx_v_d_r[3]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF1FFF)) 
    \stage_1_count_value_r[1]_i_3 
       (.I0(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I1(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I2(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I3(RX_SUF_Buffer_reg_0),
        .I4(\stage_1_count_value_r_reg[1] ),
        .O(\RX_PE_DATA_Buffer_reg[10]_2 ));
  LUT6 #(
    .INIT(64'hFFFF000088208820)) 
    \stage_1_count_value_r[2]_i_2 
       (.I0(RX_SUF_Buffer_reg_0),
        .I1(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I2(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I3(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I4(\stage_1_count_value_r_reg[2] ),
        .I5(\stage_1_count_value_r_reg[1] ),
        .O(RX_SUF_Buffer_reg_1));
  LUT5 #(
    .INIT(32'h00540000)) 
    \stage_1_count_value_r[3]_i_3 
       (.I0(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I1(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I2(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I3(\stage_1_count_value_r_reg[1] ),
        .I4(RX_SUF_Buffer_reg_0),
        .O(\RX_PE_DATA_Buffer_reg[10]_3 ));
  LUT6 #(
    .INIT(64'h00000000FEFFFE00)) 
    \stage_1_lane_mask_r[3]_i_2 
       (.I0(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I1(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I2(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I3(RX_SUF_Buffer_reg_0),
        .I4(\stage_1_count_value_r_reg[1] ),
        .I5(RX_SUF),
        .O(\RX_PE_DATA_Buffer_reg[10]_1 ));
  FDRE \word_aligned_control_bits_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[0]_0 ),
        .Q(word_aligned_control_bits_r[0]),
        .R(1'b0));
  FDRE \word_aligned_control_bits_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[1]_0 ),
        .Q(word_aligned_control_bits_r[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [7]),
        .Q(\word_aligned_data_r_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [5]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [6]),
        .Q(\word_aligned_data_r_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [5]),
        .Q(\word_aligned_data_r_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [4]),
        .Q(\word_aligned_data_r_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [3]),
        .Q(\word_aligned_data_r_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [2]),
        .Q(\word_aligned_data_r_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [1]),
        .Q(\word_aligned_data_r_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [0]),
        .Q(\word_aligned_data_r_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [7]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [6]),
        .Q(p_0_in[2]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_SYM_DEC" *) 
module aurora_rx_4l_64b_SYM_DEC_19
   (RX_NEG_Buffer,
    rx_sp_i,
    GOT_V,
    D,
    \RX_PE_DATA_Buffer_reg[9]_0 ,
    \RX_PE_DATA_Buffer_reg[8]_0 ,
    RX_PE_DATA,
    RX_SCP_Buffer_reg_0,
    RX_SUF_Buffer_reg_0,
    left_aligned_r_reg_0,
    RX_PE_DATA_V_Buffer_reg_0,
    \RX_PE_DATA_Buffer_reg[10]_0 ,
    RX_SUF_Buffer_reg_1,
    \RX_PE_DATA_Buffer_reg[8]_1 ,
    \RX_PE_DATA_Buffer_reg[8]_2 ,
    RX_SUF_Buffer_reg_2,
    good_as_r0,
    GOT_A,
    \word_aligned_data_r_reg[11]_0 ,
    \word_aligned_data_r_reg[0]_0 ,
    first_v_received_r,
    std_bool26_out,
    RX_ECP_Buffer0,
    user_clk,
    \word_aligned_control_bits_r_reg[1]_0 ,
    \word_aligned_control_bits_r_reg[0]_0 ,
    SR,
    left_aligned_r_reg_1,
    start_rx_i,
    \stage_1_lane_mask_r_reg[2] ,
    \stage_1_count_value_r_reg[1] ,
    \stage_1_count_value_r_reg[2] ,
    \stage_1_lane_mask_r_reg[3] ,
    good_as_r_reg,
    good_as_r_reg_0,
    good_as_r_reg_1,
    Q,
    good_as_r_reg_2,
    good_as_r_reg_3,
    \word_aligned_data_r_reg[8]_0 ,
    \word_aligned_data_r_reg[0]_1 );
  output RX_NEG_Buffer;
  output rx_sp_i;
  output GOT_V;
  output [0:0]D;
  output \RX_PE_DATA_Buffer_reg[9]_0 ;
  output \RX_PE_DATA_Buffer_reg[8]_0 ;
  output [0:0]RX_PE_DATA;
  output [0:0]RX_SCP_Buffer_reg_0;
  output RX_SUF_Buffer_reg_0;
  output left_aligned_r_reg_0;
  output [0:0]RX_PE_DATA_V_Buffer_reg_0;
  output \RX_PE_DATA_Buffer_reg[10]_0 ;
  output RX_SUF_Buffer_reg_1;
  output \RX_PE_DATA_Buffer_reg[8]_1 ;
  output \RX_PE_DATA_Buffer_reg[8]_2 ;
  output RX_SUF_Buffer_reg_2;
  output good_as_r0;
  output [0:1]GOT_A;
  output [4:0]\word_aligned_data_r_reg[11]_0 ;
  output [7:0]\word_aligned_data_r_reg[0]_0 ;
  output first_v_received_r;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1]_0 ;
  input \word_aligned_control_bits_r_reg[0]_0 ;
  input [0:0]SR;
  input left_aligned_r_reg_1;
  input start_rx_i;
  input \stage_1_lane_mask_r_reg[2] ;
  input \stage_1_count_value_r_reg[1] ;
  input \stage_1_count_value_r_reg[2] ;
  input \stage_1_lane_mask_r_reg[3] ;
  input good_as_r_reg;
  input good_as_r_reg_0;
  input good_as_r_reg_1;
  input [0:0]Q;
  input [0:0]good_as_r_reg_2;
  input [0:0]good_as_r_reg_3;
  input [7:0]\word_aligned_data_r_reg[8]_0 ;
  input [7:0]\word_aligned_data_r_reg[0]_1 ;

  wire [0:0]D;
  wire \EXP_IN_inferred__0/i__n_0 ;
  wire \EXP_IN_inferred__1/i__n_0 ;
  wire \EXP_IN_inferred__14/i__n_0 ;
  wire \EXP_IN_inferred__15/i__n_0 ;
  wire \EXP_IN_inferred__16/i__n_0 ;
  wire \EXP_IN_inferred__17/i__n_0 ;
  wire \EXP_IN_inferred__18/i__n_0 ;
  wire \EXP_IN_inferred__19/i__n_0 ;
  wire \EXP_IN_inferred__20/i__n_0 ;
  wire \EXP_IN_inferred__24/i__n_0 ;
  wire \EXP_IN_inferred__25/i__n_0 ;
  wire \EXP_IN_inferred__26/i__n_0 ;
  wire \EXP_IN_inferred__27/i__n_0 ;
  wire \EXP_IN_inferred__28/i__n_0 ;
  wire \EXP_IN_inferred__29/i__n_0 ;
  wire \EXP_IN_inferred__4/i__n_0 ;
  wire \EXP_IN_inferred__6/i__n_0 ;
  wire \EXP_IN_inferred__7/i__n_0 ;
  wire EXP_IN_n_0;
  wire [0:1]GOT_A;
  wire \GOT_A_Buffer[0]_i_1_n_0 ;
  wire GOT_V;
  wire [0:0]Q;
  wire RX_CC_Buffer_i_1_n_0;
  wire RX_ECP_Buffer0;
  wire RX_NEG_Buffer;
  wire RX_NEG_Buffer0;
  wire [0:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[10]_0 ;
  wire \RX_PE_DATA_Buffer_reg[8]_0 ;
  wire \RX_PE_DATA_Buffer_reg[8]_1 ;
  wire \RX_PE_DATA_Buffer_reg[8]_2 ;
  wire \RX_PE_DATA_Buffer_reg[9]_0 ;
  wire RX_PE_DATA_V_Buffer_i_1_n_0;
  wire [0:0]RX_PE_DATA_V_Buffer_reg_0;
  wire RX_SCP_Buffer_i_1_n_0;
  wire [0:0]RX_SCP_Buffer_reg_0;
  wire RX_SP_Buffer_i_2_n_0;
  wire RX_SUF_Buffer_reg_0;
  wire RX_SUF_Buffer_reg_1;
  wire RX_SUF_Buffer_reg_2;
  wire [0:0]SR;
  wire first_v_received_r;
  wire first_v_received_r_i_1_n_0;
  wire first_v_received_r_i_2_n_0;
  wire good_as_r0;
  wire good_as_r_reg;
  wire good_as_r_reg_0;
  wire good_as_r_reg_1;
  wire [0:0]good_as_r_reg_2;
  wire [0:0]good_as_r_reg_3;
  wire [0:3]got_a_d_r;
  wire got_v_c;
  wire left_aligned_r_reg_0;
  wire left_aligned_r_reg_1;
  wire [3:1]p_0_in;
  wire p_15_in;
  wire p_18_in;
  wire p_1_in;
  wire p_2_in;
  wire [0:0]p_3_out;
  wire [3:2]p_4_out;
  wire [0:0]prev_beat_sp_d_r;
  wire prev_beat_sp_r;
  wire prev_beat_sp_r_i_1_n_0;
  wire prev_beat_v_r;
  wire prev_beat_v_r_i_1_n_0;
  wire [1:3]rx_cc_r;
  wire \rx_ecp_d_r_reg_n_0_[3] ;
  wire \rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/all_as_c_2__2 ;
  wire [0:0]rx_pad_d_r;
  wire \rx_pe_control_r_reg_n_0_[1] ;
  wire [8:10]rx_pe_data_r;
  wire \rx_scp_d_r_reg_n_0_[2] ;
  wire \rx_scp_d_r_reg_n_0_[3] ;
  wire rx_sp_c;
  wire [0:3]rx_sp_d_r;
  wire rx_sp_i;
  wire [0:1]rx_sp_neg_d_r;
  wire [0:1]rx_spa_neg_d_r;
  wire \rx_suf_d_r_reg_n_0_[0] ;
  wire [0:3]rx_v_d_r;
  wire \stage_1_count_value_r_reg[1] ;
  wire \stage_1_count_value_r_reg[2] ;
  wire \stage_1_lane_mask_r_reg[2] ;
  wire \stage_1_lane_mask_r_reg[3] ;
  wire start_rx_i;
  wire std_bool;
  wire std_bool10_in;
  wire std_bool12_out;
  wire std_bool26_out;
  wire std_bool4_in;
  wire std_bool7_in;
  wire std_bool9_out;
  wire user_clk;
  wire [0:1]word_aligned_control_bits_r;
  wire \word_aligned_control_bits_r_reg[0]_0 ;
  wire \word_aligned_control_bits_r_reg[1]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_1 ;
  wire [4:0]\word_aligned_data_r_reg[11]_0 ;
  wire [7:0]\word_aligned_data_r_reg[8]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    EXP_IN
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [1]),
        .I2(\word_aligned_data_r_reg[11]_0 [3]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(EXP_IN_n_0));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__0/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [4]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(p_0_in[1]),
        .O(\EXP_IN_inferred__0/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \EXP_IN_inferred__1/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [1]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__1/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \EXP_IN_inferred__10/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [0]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [3]),
        .O(std_bool9_out));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__11/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[3]),
        .I2(p_0_in[1]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(std_bool10_in));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \EXP_IN_inferred__12/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [4]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(p_0_in[2]),
        .O(std_bool12_out));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__14/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [3]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__14/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__15/i_ 
       (.I0(p_0_in[1]),
        .I1(\word_aligned_data_r_reg[11]_0 [4]),
        .I2(p_0_in[2]),
        .I3(p_0_in[3]),
        .O(\EXP_IN_inferred__15/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__16/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__16/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__17/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [0]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [3]),
        .I3(\word_aligned_data_r_reg[11]_0 [1]),
        .O(\EXP_IN_inferred__17/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__18/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__18/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__19/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [5]),
        .I1(\word_aligned_data_r_reg[0]_0 [4]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [7]),
        .O(\EXP_IN_inferred__19/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__2/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [5]),
        .O(std_bool));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__20/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__20/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__24/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [2]),
        .I1(\word_aligned_data_r_reg[11]_0 [3]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__24/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__25/i_ 
       (.I0(p_0_in[1]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__25/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__26/i_ 
       (.I0(p_0_in[3]),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__26/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__27/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__27/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__28/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [3]),
        .I1(\word_aligned_data_r_reg[11]_0 [2]),
        .I2(\word_aligned_data_r_reg[11]_0 [1]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(\EXP_IN_inferred__28/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__29/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [3]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__29/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__3/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [7]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(std_bool4_in));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__4/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [2]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(\EXP_IN_inferred__4/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__6/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [1]),
        .I1(\word_aligned_data_r_reg[11]_0 [0]),
        .I2(\word_aligned_data_r_reg[11]_0 [2]),
        .I3(\word_aligned_data_r_reg[11]_0 [3]),
        .O(\EXP_IN_inferred__6/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__7/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(\word_aligned_data_r_reg[11]_0 [4]),
        .O(\EXP_IN_inferred__7/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__9/i_ 
       (.I0(\word_aligned_data_r_reg[11]_0 [3]),
        .I1(\word_aligned_data_r_reg[11]_0 [1]),
        .I2(\word_aligned_data_r_reg[11]_0 [2]),
        .I3(\word_aligned_data_r_reg[11]_0 [0]),
        .O(std_bool7_in));
  LUT2 #(
    .INIT(4'h7)) 
    \GOT_A_Buffer[0]_i_1 
       (.I0(got_a_d_r[1]),
        .I1(p_2_in),
        .O(\GOT_A_Buffer[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \GOT_A_Buffer[1]_i_1 
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(got_a_d_r[3]),
        .I2(got_a_d_r[2]),
        .O(p_3_out));
  FDRE \GOT_A_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(got_a_d_r[0]),
        .Q(GOT_A[0]),
        .R(\GOT_A_Buffer[0]_i_1_n_0 ));
  FDRE \GOT_A_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_3_out),
        .Q(GOT_A[1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h01)) 
    GOT_V_Buffer_i_1
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(first_v_received_r_i_2_n_0),
        .O(got_v_c));
  FDRE GOT_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(got_v_c),
        .Q(GOT_V),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    RX_CC_Buffer_i_1
       (.I0(rx_cc_r[1]),
        .I1(p_15_in),
        .I2(rx_cc_r[3]),
        .I3(\rx_scp_d_r_reg_n_0_[2] ),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_CC_Buffer_i_1_n_0));
  FDRE RX_CC_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_CC_Buffer_i_1_n_0),
        .Q(D),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0F080808)) 
    RX_NEG_Buffer_i_1
       (.I0(rx_sp_neg_d_r[1]),
        .I1(rx_sp_neg_d_r[0]),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(rx_spa_neg_d_r[1]),
        .I4(rx_spa_neg_d_r[0]),
        .O(RX_NEG_Buffer0));
  FDRE RX_NEG_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_NEG_Buffer0),
        .Q(RX_NEG_Buffer),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[10]),
        .Q(RX_PE_DATA),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[8]),
        .Q(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[9]),
        .Q(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0F08)) 
    RX_PE_DATA_V_Buffer_i_1
       (.I0(RX_SP_Buffer_i_2_n_0),
        .I1(first_v_received_r_i_2_n_0),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_PE_DATA_V_Buffer_i_1_n_0));
  FDRE RX_PE_DATA_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_PE_DATA_V_Buffer_i_1_n_0),
        .Q(RX_PE_DATA_V_Buffer_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    RX_SCP_Buffer_i_1
       (.I0(\rx_scp_d_r_reg_n_0_[3] ),
        .I1(\rx_scp_d_r_reg_n_0_[2] ),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(p_18_in),
        .O(RX_SCP_Buffer_i_1_n_0));
  FDRE RX_SCP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_SCP_Buffer_i_1_n_0),
        .Q(RX_SCP_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    RX_SP_Buffer_i_1
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(RX_SP_Buffer_i_2_n_0),
        .O(rx_sp_c));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    RX_SP_Buffer_i_2
       (.I0(prev_beat_sp_r),
        .I1(rx_sp_d_r[3]),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[0]),
        .I4(rx_sp_d_r[1]),
        .O(RX_SP_Buffer_i_2_n_0));
  FDRE RX_SP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_sp_c),
        .Q(rx_sp_i),
        .R(1'b0));
  FDRE RX_SUF_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_d_r_reg_n_0_[0] ),
        .Q(RX_SUF_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF01)) 
    first_v_received_r_i_1
       (.I0(first_v_received_r_i_2_n_0),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(p_2_in),
        .I3(first_v_received_r),
        .O(first_v_received_r_i_1_n_0));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    first_v_received_r_i_2
       (.I0(prev_beat_v_r),
        .I1(rx_v_d_r[3]),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[0]),
        .I4(rx_v_d_r[1]),
        .O(first_v_received_r_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    first_v_received_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(first_v_received_r_i_1_n_0),
        .Q(first_v_received_r),
        .R(SR));
  LUT5 #(
    .INIT(32'hFFFF8000)) 
    good_as_r_i_1
       (.I0(good_as_r_reg),
        .I1(good_as_r_reg_0),
        .I2(good_as_r_reg_1),
        .I3(GOT_A[0]),
        .I4(\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/all_as_c_2__2 ),
        .O(good_as_r0));
  LUT4 #(
    .INIT(16'h8000)) 
    good_as_r_i_2
       (.I0(GOT_A[1]),
        .I1(Q),
        .I2(good_as_r_reg_2),
        .I3(good_as_r_reg_3),
        .O(\rx_global_logic_simplex_i/rx_channel_init_sm_simplex_i/all_as_c_2__2 ));
  FDRE \got_a_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__27/i__n_0 ),
        .Q(got_a_d_r[0]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__4/i__n_0 ),
        .Q(got_a_d_r[1]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__26/i__n_0 ),
        .Q(got_a_d_r[2]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__6/i__n_0 ),
        .Q(got_a_d_r[3]),
        .R(1'b0));
  FDRE left_aligned_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(left_aligned_r_reg_1),
        .Q(left_aligned_r_reg_0),
        .R(SR));
  FDRE \prev_beat_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool4_in),
        .Q(prev_beat_sp_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_sp_r_i_1
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[3]),
        .O(prev_beat_sp_r_i_1_n_0));
  FDRE prev_beat_sp_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_sp_r_i_1_n_0),
        .Q(prev_beat_sp_r),
        .R(\GOT_A_Buffer[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_v_r_i_1
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[3]),
        .O(prev_beat_v_r_i_1_n_0));
  FDRE prev_beat_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_v_r_i_1_n_0),
        .Q(prev_beat_v_r),
        .R(\GOT_A_Buffer[0]_i_1_n_0 ));
  FDRE \rx_cc_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__29/i__n_0 ),
        .Q(rx_cc_r[1]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__28/i__n_0 ),
        .Q(rx_cc_r[3]),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__19/i__n_0 ),
        .Q(p_15_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__18/i__n_0 ),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__17/i__n_0 ),
        .Q(\rx_ecp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_ecp_r_reg[0]_srl2_i_1 
       (.I0(\rx_scp_d_r_reg_n_0_[2] ),
        .I1(p_15_in),
        .I2(\rx_ecp_d_r_reg_n_0_[3] ),
        .I3(p_1_in),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_ECP_Buffer0));
  FDRE \rx_pad_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__7/i__n_0 ),
        .Q(rx_pad_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0800)) 
    \rx_pad_r_reg[0]_srl2_i_1 
       (.I0(rx_pad_d_r),
        .I1(got_a_d_r[3]),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(std_bool26_out));
  FDRE \rx_pe_control_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[0]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \rx_pe_control_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[1]),
        .Q(\rx_pe_control_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(rx_pe_data_r[10]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(rx_pe_data_r[8]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(rx_pe_data_r[9]),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__16/i__n_0 ),
        .Q(p_18_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__15/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__14/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \rx_sp_d_r[0]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [6]),
        .O(p_4_out[3]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \rx_sp_d_r[1]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(p_4_out[2]));
  FDRE \rx_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[3]),
        .Q(rx_sp_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[2]),
        .Q(rx_sp_d_r[1]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool12_out),
        .Q(rx_sp_d_r[2]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool9_out),
        .Q(rx_sp_d_r[3]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool10_in),
        .Q(rx_sp_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool7_in),
        .Q(rx_sp_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__25/i__n_0 ),
        .Q(rx_spa_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__24/i__n_0 ),
        .Q(rx_spa_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_suf_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__20/i__n_0 ),
        .Q(\rx_suf_d_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool),
        .Q(rx_v_d_r[0]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__1/i__n_0 ),
        .Q(rx_v_d_r[1]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__0/i__n_0 ),
        .Q(rx_v_d_r[2]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(EXP_IN_n_0),
        .Q(rx_v_d_r[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFF000008000800)) 
    \stage_1_count_value_r[1]_i_2 
       (.I0(RX_SUF_Buffer_reg_0),
        .I1(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I2(\stage_1_lane_mask_r_reg[2] ),
        .I3(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I4(\stage_1_count_value_r_reg[1] ),
        .I5(\stage_1_count_value_r_reg[2] ),
        .O(RX_SUF_Buffer_reg_1));
  LUT4 #(
    .INIT(16'hFFF7)) 
    \stage_1_count_value_r[2]_i_3 
       (.I0(RX_SUF_Buffer_reg_0),
        .I1(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I2(\stage_1_count_value_r_reg[2] ),
        .I3(\stage_1_lane_mask_r_reg[2] ),
        .O(RX_SUF_Buffer_reg_2));
  LUT6 #(
    .INIT(64'h000000000000E000)) 
    \stage_1_count_value_r[3]_i_2 
       (.I0(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I1(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I2(RX_SUF_Buffer_reg_0),
        .I3(RX_PE_DATA),
        .I4(\stage_1_lane_mask_r_reg[2] ),
        .I5(\stage_1_count_value_r_reg[2] ),
        .O(\RX_PE_DATA_Buffer_reg[8]_2 ));
  LUT6 #(
    .INIT(64'hFE00FF00FE000000)) 
    \stage_1_lane_mask_r[2]_i_1 
       (.I0(RX_PE_DATA),
        .I1(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I2(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I3(start_rx_i),
        .I4(RX_SUF_Buffer_reg_0),
        .I5(\stage_1_lane_mask_r_reg[2] ),
        .O(\RX_PE_DATA_Buffer_reg[10]_0 ));
  LUT4 #(
    .INIT(16'hFFE0)) 
    \stage_1_lane_mask_r[3]_i_1 
       (.I0(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .I1(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .I2(RX_SUF_Buffer_reg_0),
        .I3(\stage_1_lane_mask_r_reg[3] ),
        .O(\RX_PE_DATA_Buffer_reg[8]_1 ));
  FDRE \word_aligned_control_bits_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[0]_0 ),
        .Q(word_aligned_control_bits_r[0]),
        .R(1'b0));
  FDRE \word_aligned_control_bits_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[1]_0 ),
        .Q(word_aligned_control_bits_r[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [7]),
        .Q(\word_aligned_data_r_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [5]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [4]),
        .Q(\word_aligned_data_r_reg[11]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [3]),
        .Q(\word_aligned_data_r_reg[11]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [2]),
        .Q(\word_aligned_data_r_reg[11]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [1]),
        .Q(\word_aligned_data_r_reg[11]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [0]),
        .Q(\word_aligned_data_r_reg[11]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [6]),
        .Q(\word_aligned_data_r_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [5]),
        .Q(\word_aligned_data_r_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [4]),
        .Q(\word_aligned_data_r_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [3]),
        .Q(\word_aligned_data_r_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [2]),
        .Q(\word_aligned_data_r_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [1]),
        .Q(\word_aligned_data_r_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [0]),
        .Q(\word_aligned_data_r_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [7]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [6]),
        .Q(p_0_in[2]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_SYM_DEC" *) 
module aurora_rx_4l_64b_SYM_DEC_9
   (RX_NEG_Buffer,
    rx_sp_i,
    GOT_V_Buffer_reg_0,
    D,
    \RX_PE_DATA_Buffer_reg[8]_0 ,
    \RX_PE_DATA_Buffer_reg[10]_0 ,
    \RX_PE_DATA_Buffer_reg[9]_0 ,
    RX_SCP_Buffer_reg_0,
    RX_SUF_Buffer_reg_0,
    left_aligned_r_reg_0,
    RX_PE_DATA_V_Buffer_reg_0,
    neqOp,
    RX_SUF_Buffer_reg_1,
    Q,
    \word_aligned_data_r_reg[0]_0 ,
    first_v_received_r,
    \GOT_A_Buffer_reg[1]_0 ,
    \GOT_A_Buffer_reg[0]_0 ,
    std_bool26_out,
    RX_ECP_Buffer0,
    user_clk,
    \word_aligned_control_bits_r_reg[1]_0 ,
    \word_aligned_control_bits_r_reg[0]_0 ,
    SR,
    left_aligned_r_reg_1,
    load_ufc_control_code_r_reg,
    \stage_1_count_value_r_reg[3] ,
    \stage_1_count_value_r_reg[3]_0 ,
    \stage_1_count_value_r_reg[3]_1 ,
    \word_aligned_data_r_reg[8]_0 ,
    \word_aligned_data_r_reg[0]_1 );
  output RX_NEG_Buffer;
  output rx_sp_i;
  output GOT_V_Buffer_reg_0;
  output [0:0]D;
  output \RX_PE_DATA_Buffer_reg[8]_0 ;
  output \RX_PE_DATA_Buffer_reg[10]_0 ;
  output \RX_PE_DATA_Buffer_reg[9]_0 ;
  output [0:0]RX_SCP_Buffer_reg_0;
  output RX_SUF_Buffer_reg_0;
  output left_aligned_r_reg_0;
  output [0:0]RX_PE_DATA_V_Buffer_reg_0;
  output neqOp;
  output RX_SUF_Buffer_reg_1;
  output [4:0]Q;
  output [7:0]\word_aligned_data_r_reg[0]_0 ;
  output first_v_received_r;
  output [0:0]\GOT_A_Buffer_reg[1]_0 ;
  output \GOT_A_Buffer_reg[0]_0 ;
  output std_bool26_out;
  output RX_ECP_Buffer0;
  input user_clk;
  input \word_aligned_control_bits_r_reg[1]_0 ;
  input \word_aligned_control_bits_r_reg[0]_0 ;
  input [0:0]SR;
  input left_aligned_r_reg_1;
  input [2:0]load_ufc_control_code_r_reg;
  input \stage_1_count_value_r_reg[3] ;
  input \stage_1_count_value_r_reg[3]_0 ;
  input \stage_1_count_value_r_reg[3]_1 ;
  input [7:0]\word_aligned_data_r_reg[8]_0 ;
  input [7:0]\word_aligned_data_r_reg[0]_1 ;

  wire [0:0]D;
  wire \EXP_IN_inferred__0/i__n_0 ;
  wire \EXP_IN_inferred__1/i__n_0 ;
  wire \EXP_IN_inferred__14/i__n_0 ;
  wire \EXP_IN_inferred__15/i__n_0 ;
  wire \EXP_IN_inferred__16/i__n_0 ;
  wire \EXP_IN_inferred__17/i__n_0 ;
  wire \EXP_IN_inferred__18/i__n_0 ;
  wire \EXP_IN_inferred__19/i__n_0 ;
  wire \EXP_IN_inferred__20/i__n_0 ;
  wire \EXP_IN_inferred__24/i__n_0 ;
  wire \EXP_IN_inferred__25/i__n_0 ;
  wire \EXP_IN_inferred__26/i__n_0 ;
  wire \EXP_IN_inferred__27/i__n_0 ;
  wire \EXP_IN_inferred__28/i__n_0 ;
  wire \EXP_IN_inferred__29/i__n_0 ;
  wire \EXP_IN_inferred__4/i__n_0 ;
  wire \EXP_IN_inferred__6/i__n_0 ;
  wire \EXP_IN_inferred__7/i__n_0 ;
  wire EXP_IN_n_0;
  wire \GOT_A_Buffer[0]_i_1__1_n_0 ;
  wire \GOT_A_Buffer_reg[0]_0 ;
  wire [0:0]\GOT_A_Buffer_reg[1]_0 ;
  wire GOT_V_Buffer_reg_0;
  wire [4:0]Q;
  wire RX_CC_Buffer_i_1__1_n_0;
  wire RX_ECP_Buffer0;
  wire RX_NEG_Buffer;
  wire RX_NEG_Buffer0;
  wire \RX_PE_DATA_Buffer_reg[10]_0 ;
  wire \RX_PE_DATA_Buffer_reg[8]_0 ;
  wire \RX_PE_DATA_Buffer_reg[9]_0 ;
  wire RX_PE_DATA_V_Buffer_i_1__1_n_0;
  wire [0:0]RX_PE_DATA_V_Buffer_reg_0;
  wire RX_SCP_Buffer_i_1__1_n_0;
  wire [0:0]RX_SCP_Buffer_reg_0;
  wire RX_SP_Buffer_i_2__1_n_0;
  wire RX_SUF_Buffer_reg_0;
  wire RX_SUF_Buffer_reg_1;
  wire [0:0]SR;
  wire first_v_received_r;
  wire first_v_received_r_i_1__1_n_0;
  wire first_v_received_r_i_2__1_n_0;
  wire [0:3]got_a_d_r;
  wire got_v_c;
  wire left_aligned_r_reg_0;
  wire left_aligned_r_reg_1;
  wire [2:0]load_ufc_control_code_r_reg;
  wire neqOp;
  wire [3:1]p_0_in;
  wire p_15_in;
  wire p_18_in;
  wire p_1_in;
  wire p_2_in;
  wire [0:0]p_3_out;
  wire [3:2]p_4_out;
  wire [0:0]prev_beat_sp_d_r;
  wire prev_beat_sp_r;
  wire prev_beat_sp_r_i_1__1_n_0;
  wire prev_beat_v_r;
  wire prev_beat_v_r_i_1__1_n_0;
  wire [1:3]rx_cc_r;
  wire \rx_ecp_d_r_reg_n_0_[3] ;
  wire [0:0]rx_pad_d_r;
  wire \rx_pe_control_r_reg_n_0_[1] ;
  wire [8:10]rx_pe_data_r;
  wire \rx_scp_d_r_reg_n_0_[2] ;
  wire \rx_scp_d_r_reg_n_0_[3] ;
  wire rx_sp_c;
  wire [0:3]rx_sp_d_r;
  wire rx_sp_i;
  wire [0:1]rx_sp_neg_d_r;
  wire [0:1]rx_spa_neg_d_r;
  wire \rx_suf_d_r_reg_n_0_[0] ;
  wire [0:3]rx_v_d_r;
  wire \stage_1_count_value_r_reg[3] ;
  wire \stage_1_count_value_r_reg[3]_0 ;
  wire \stage_1_count_value_r_reg[3]_1 ;
  wire std_bool;
  wire std_bool10_in;
  wire std_bool12_out;
  wire std_bool26_out;
  wire std_bool4_in;
  wire std_bool7_in;
  wire std_bool9_out;
  wire user_clk;
  wire [0:1]word_aligned_control_bits_r;
  wire \word_aligned_control_bits_r_reg[0]_0 ;
  wire \word_aligned_control_bits_r_reg[1]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_0 ;
  wire [7:0]\word_aligned_data_r_reg[0]_1 ;
  wire [7:0]\word_aligned_data_r_reg[8]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    EXP_IN
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[3]),
        .I3(Q[0]),
        .O(EXP_IN_n_0));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__0/i_ 
       (.I0(Q[4]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(p_0_in[1]),
        .O(\EXP_IN_inferred__0/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \EXP_IN_inferred__1/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [1]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__1/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \EXP_IN_inferred__10/i_ 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[3]),
        .O(std_bool9_out));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__11/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[3]),
        .I2(p_0_in[1]),
        .I3(Q[4]),
        .O(std_bool10_in));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \EXP_IN_inferred__12/i_ 
       (.I0(Q[4]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(p_0_in[2]),
        .O(std_bool12_out));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__14/i_ 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\EXP_IN_inferred__14/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__15/i_ 
       (.I0(p_0_in[1]),
        .I1(Q[4]),
        .I2(p_0_in[2]),
        .I3(p_0_in[3]),
        .O(\EXP_IN_inferred__15/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__16/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__16/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__17/i_ 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(Q[1]),
        .O(\EXP_IN_inferred__17/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__18/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [3]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__18/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \EXP_IN_inferred__19/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [5]),
        .I1(\word_aligned_data_r_reg[0]_0 [4]),
        .I2(\word_aligned_data_r_reg[0]_0 [6]),
        .I3(\word_aligned_data_r_reg[0]_0 [7]),
        .O(\EXP_IN_inferred__19/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__2/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [5]),
        .O(std_bool));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__20/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__20/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__24/i_ 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\EXP_IN_inferred__24/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__25/i_ 
       (.I0(p_0_in[1]),
        .I1(p_0_in[2]),
        .I2(p_0_in[3]),
        .I3(Q[4]),
        .O(\EXP_IN_inferred__25/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__26/i_ 
       (.I0(p_0_in[3]),
        .I1(p_0_in[2]),
        .I2(p_0_in[1]),
        .I3(Q[4]),
        .O(\EXP_IN_inferred__26/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__27/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [7]),
        .I1(\word_aligned_data_r_reg[0]_0 [6]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(\EXP_IN_inferred__27/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__28/i_ 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\EXP_IN_inferred__28/i__n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__29/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [3]),
        .I1(\word_aligned_data_r_reg[0]_0 [2]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [0]),
        .O(\EXP_IN_inferred__29/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \EXP_IN_inferred__3/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [6]),
        .I1(\word_aligned_data_r_reg[0]_0 [7]),
        .I2(\word_aligned_data_r_reg[0]_0 [5]),
        .I3(\word_aligned_data_r_reg[0]_0 [4]),
        .O(std_bool4_in));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__4/i_ 
       (.I0(\word_aligned_data_r_reg[0]_0 [1]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [2]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(\EXP_IN_inferred__4/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__6/i_ 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\EXP_IN_inferred__6/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__7/i_ 
       (.I0(p_0_in[2]),
        .I1(p_0_in[1]),
        .I2(p_0_in[3]),
        .I3(Q[4]),
        .O(\EXP_IN_inferred__7/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \EXP_IN_inferred__9/i_ 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[0]),
        .O(std_bool7_in));
  LUT2 #(
    .INIT(4'h7)) 
    \GOT_A_Buffer[0]_i_1__1 
       (.I0(got_a_d_r[1]),
        .I1(p_2_in),
        .O(\GOT_A_Buffer[0]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \GOT_A_Buffer[1]_i_1__1 
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(got_a_d_r[3]),
        .I2(got_a_d_r[2]),
        .O(p_3_out));
  FDRE \GOT_A_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(got_a_d_r[0]),
        .Q(\GOT_A_Buffer_reg[0]_0 ),
        .R(\GOT_A_Buffer[0]_i_1__1_n_0 ));
  FDRE \GOT_A_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_3_out),
        .Q(\GOT_A_Buffer_reg[1]_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h01)) 
    GOT_V_Buffer_i_1__1
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(first_v_received_r_i_2__1_n_0),
        .O(got_v_c));
  FDRE GOT_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(got_v_c),
        .Q(GOT_V_Buffer_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    RX_CC_Buffer_i_1__1
       (.I0(rx_cc_r[1]),
        .I1(p_15_in),
        .I2(rx_cc_r[3]),
        .I3(\rx_scp_d_r_reg_n_0_[2] ),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_CC_Buffer_i_1__1_n_0));
  FDRE RX_CC_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_CC_Buffer_i_1__1_n_0),
        .Q(D),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0F080808)) 
    RX_NEG_Buffer_i_1__1
       (.I0(rx_sp_neg_d_r[1]),
        .I1(rx_sp_neg_d_r[0]),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(rx_spa_neg_d_r[1]),
        .I4(rx_spa_neg_d_r[0]),
        .O(RX_NEG_Buffer0));
  FDRE RX_NEG_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_NEG_Buffer0),
        .Q(RX_NEG_Buffer),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[10]),
        .Q(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[8]),
        .Q(\RX_PE_DATA_Buffer_reg[8]_0 ),
        .R(1'b0));
  FDRE \RX_PE_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_pe_data_r[9]),
        .Q(\RX_PE_DATA_Buffer_reg[9]_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0F08)) 
    RX_PE_DATA_V_Buffer_i_1__1
       (.I0(RX_SP_Buffer_i_2__1_n_0),
        .I1(first_v_received_r_i_2__1_n_0),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_PE_DATA_V_Buffer_i_1__1_n_0));
  FDRE RX_PE_DATA_V_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_PE_DATA_V_Buffer_i_1__1_n_0),
        .Q(RX_PE_DATA_V_Buffer_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    RX_SCP_Buffer_i_1__1
       (.I0(\rx_scp_d_r_reg_n_0_[3] ),
        .I1(\rx_scp_d_r_reg_n_0_[2] ),
        .I2(\rx_pe_control_r_reg_n_0_[1] ),
        .I3(p_18_in),
        .O(RX_SCP_Buffer_i_1__1_n_0));
  FDRE RX_SCP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(RX_SCP_Buffer_i_1__1_n_0),
        .Q(RX_SCP_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    RX_SP_Buffer_i_1__1
       (.I0(p_2_in),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(RX_SP_Buffer_i_2__1_n_0),
        .O(rx_sp_c));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    RX_SP_Buffer_i_2__1
       (.I0(prev_beat_sp_r),
        .I1(rx_sp_d_r[3]),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[0]),
        .I4(rx_sp_d_r[1]),
        .O(RX_SP_Buffer_i_2__1_n_0));
  FDRE RX_SP_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_sp_c),
        .Q(rx_sp_i),
        .R(1'b0));
  FDRE RX_SUF_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_d_r_reg_n_0_[0] ),
        .Q(RX_SUF_Buffer_reg_0),
        .R(\GOT_A_Buffer[0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFF01)) 
    first_v_received_r_i_1__1
       (.I0(first_v_received_r_i_2__1_n_0),
        .I1(\rx_pe_control_r_reg_n_0_[1] ),
        .I2(p_2_in),
        .I3(first_v_received_r),
        .O(first_v_received_r_i_1__1_n_0));
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    first_v_received_r_i_2__1
       (.I0(prev_beat_v_r),
        .I1(rx_v_d_r[3]),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[0]),
        .I4(rx_v_d_r[1]),
        .O(first_v_received_r_i_2__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    first_v_received_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(first_v_received_r_i_1__1_n_0),
        .Q(first_v_received_r),
        .R(SR));
  FDRE \got_a_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__27/i__n_0 ),
        .Q(got_a_d_r[0]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__4/i__n_0 ),
        .Q(got_a_d_r[1]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__26/i__n_0 ),
        .Q(got_a_d_r[2]),
        .R(1'b0));
  FDRE \got_a_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__6/i__n_0 ),
        .Q(got_a_d_r[3]),
        .R(1'b0));
  FDRE left_aligned_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(left_aligned_r_reg_1),
        .Q(left_aligned_r_reg_0),
        .R(SR));
  LUT4 #(
    .INIT(16'hFFFE)) 
    load_ufc_control_code_r_i_1
       (.I0(RX_SUF_Buffer_reg_0),
        .I1(load_ufc_control_code_r_reg[1]),
        .I2(load_ufc_control_code_r_reg[2]),
        .I3(load_ufc_control_code_r_reg[0]),
        .O(neqOp));
  FDRE \prev_beat_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool4_in),
        .Q(prev_beat_sp_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_sp_r_i_1__1
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_sp_d_r[2]),
        .I3(rx_sp_d_r[3]),
        .O(prev_beat_sp_r_i_1__1_n_0));
  FDRE prev_beat_sp_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_sp_r_i_1__1_n_0),
        .Q(prev_beat_sp_r),
        .R(\GOT_A_Buffer[0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    prev_beat_v_r_i_1__1
       (.I0(\rx_pe_control_r_reg_n_0_[1] ),
        .I1(prev_beat_sp_d_r),
        .I2(rx_v_d_r[2]),
        .I3(rx_v_d_r[3]),
        .O(prev_beat_v_r_i_1__1_n_0));
  FDRE prev_beat_v_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(prev_beat_v_r_i_1__1_n_0),
        .Q(prev_beat_v_r),
        .R(\GOT_A_Buffer[0]_i_1__1_n_0 ));
  FDRE \rx_cc_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__29/i__n_0 ),
        .Q(rx_cc_r[1]),
        .R(1'b0));
  FDRE \rx_cc_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__28/i__n_0 ),
        .Q(rx_cc_r[3]),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__19/i__n_0 ),
        .Q(p_15_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__18/i__n_0 ),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \rx_ecp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__17/i__n_0 ),
        .Q(\rx_ecp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \rx_ecp_r_reg[2]_srl2_i_1 
       (.I0(\rx_scp_d_r_reg_n_0_[2] ),
        .I1(p_15_in),
        .I2(\rx_ecp_d_r_reg_n_0_[3] ),
        .I3(p_1_in),
        .I4(p_2_in),
        .I5(\rx_pe_control_r_reg_n_0_[1] ),
        .O(RX_ECP_Buffer0));
  FDRE \rx_pad_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__7/i__n_0 ),
        .Q(rx_pad_d_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0800)) 
    \rx_pad_r_reg[2]_srl2_i_1 
       (.I0(rx_pad_d_r),
        .I1(got_a_d_r[3]),
        .I2(p_2_in),
        .I3(\rx_pe_control_r_reg_n_0_[1] ),
        .O(std_bool26_out));
  FDRE \rx_pe_control_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[0]),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \rx_pe_control_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(word_aligned_control_bits_r[1]),
        .Q(\rx_pe_control_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(rx_pe_data_r[10]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(rx_pe_data_r[8]),
        .R(1'b0));
  FDRE \rx_pe_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(rx_pe_data_r[9]),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__16/i__n_0 ),
        .Q(p_18_in),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__15/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \rx_scp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__14/i__n_0 ),
        .Q(\rx_scp_d_r_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT4 #(
    .INIT(16'h0180)) 
    \rx_sp_d_r[0]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [4]),
        .I1(\word_aligned_data_r_reg[0]_0 [5]),
        .I2(\word_aligned_data_r_reg[0]_0 [7]),
        .I3(\word_aligned_data_r_reg[0]_0 [6]),
        .O(p_4_out[3]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT4 #(
    .INIT(16'h1008)) 
    \rx_sp_d_r[1]_i_1 
       (.I0(\word_aligned_data_r_reg[0]_0 [2]),
        .I1(\word_aligned_data_r_reg[0]_0 [0]),
        .I2(\word_aligned_data_r_reg[0]_0 [1]),
        .I3(\word_aligned_data_r_reg[0]_0 [3]),
        .O(p_4_out[2]));
  FDRE \rx_sp_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[3]),
        .Q(rx_sp_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_4_out[2]),
        .Q(rx_sp_d_r[1]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool12_out),
        .Q(rx_sp_d_r[2]),
        .R(1'b0));
  FDRE \rx_sp_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool9_out),
        .Q(rx_sp_d_r[3]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool10_in),
        .Q(rx_sp_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_sp_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool7_in),
        .Q(rx_sp_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__25/i__n_0 ),
        .Q(rx_spa_neg_d_r[0]),
        .R(1'b0));
  FDRE \rx_spa_neg_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__24/i__n_0 ),
        .Q(rx_spa_neg_d_r[1]),
        .R(1'b0));
  FDRE \rx_suf_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__20/i__n_0 ),
        .Q(\rx_suf_d_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(std_bool),
        .Q(rx_v_d_r[0]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__1/i__n_0 ),
        .Q(rx_v_d_r[1]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\EXP_IN_inferred__0/i__n_0 ),
        .Q(rx_v_d_r[2]),
        .R(1'b0));
  FDRE \rx_v_d_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(EXP_IN_n_0),
        .Q(rx_v_d_r[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000FFF8FFFFFFF8)) 
    \stage_1_count_value_r[3]_i_1 
       (.I0(RX_SUF_Buffer_reg_0),
        .I1(\RX_PE_DATA_Buffer_reg[10]_0 ),
        .I2(\stage_1_count_value_r_reg[3] ),
        .I3(\stage_1_count_value_r_reg[3]_0 ),
        .I4(load_ufc_control_code_r_reg[0]),
        .I5(\stage_1_count_value_r_reg[3]_1 ),
        .O(RX_SUF_Buffer_reg_1));
  FDRE \word_aligned_control_bits_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[0]_0 ),
        .Q(word_aligned_control_bits_r[0]),
        .R(1'b0));
  FDRE \word_aligned_control_bits_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_control_bits_r_reg[1]_0 ),
        .Q(word_aligned_control_bits_r[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [7]),
        .Q(\word_aligned_data_r_reg[0]_0 [7]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [5]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [6]),
        .Q(\word_aligned_data_r_reg[0]_0 [6]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [5]),
        .Q(\word_aligned_data_r_reg[0]_0 [5]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [4]),
        .Q(\word_aligned_data_r_reg[0]_0 [4]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [3]),
        .Q(\word_aligned_data_r_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [2]),
        .Q(\word_aligned_data_r_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [1]),
        .Q(\word_aligned_data_r_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[0]_1 [0]),
        .Q(\word_aligned_data_r_reg[0]_0 [0]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [7]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \word_aligned_data_r_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\word_aligned_data_r_reg[8]_0 [6]),
        .Q(p_0_in[2]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_UFC_BARREL_SHIFTER
   (\SHIFTED_DATA_Buffer_reg[48]_0 ,
    Q,
    \SHIFTED_DATA_Buffer_reg[48]_1 ,
    \SHIFTED_DATA_Buffer_reg[49]_0 ,
    \SHIFTED_DATA_Buffer_reg[49]_1 ,
    \SHIFTED_DATA_Buffer_reg[50]_0 ,
    \SHIFTED_DATA_Buffer_reg[50]_1 ,
    \SHIFTED_DATA_Buffer_reg[51]_0 ,
    \SHIFTED_DATA_Buffer_reg[51]_1 ,
    \SHIFTED_DATA_Buffer_reg[52]_0 ,
    \SHIFTED_DATA_Buffer_reg[52]_1 ,
    \SHIFTED_DATA_Buffer_reg[53]_0 ,
    \SHIFTED_DATA_Buffer_reg[53]_1 ,
    \SHIFTED_DATA_Buffer_reg[54]_0 ,
    \SHIFTED_DATA_Buffer_reg[54]_1 ,
    \SHIFTED_DATA_Buffer_reg[55]_0 ,
    \SHIFTED_DATA_Buffer_reg[55]_1 ,
    \SHIFTED_DATA_Buffer_reg[56]_0 ,
    \SHIFTED_DATA_Buffer_reg[56]_1 ,
    \SHIFTED_DATA_Buffer_reg[57]_0 ,
    \SHIFTED_DATA_Buffer_reg[57]_1 ,
    \SHIFTED_DATA_Buffer_reg[58]_0 ,
    \SHIFTED_DATA_Buffer_reg[58]_1 ,
    \SHIFTED_DATA_Buffer_reg[59]_0 ,
    \SHIFTED_DATA_Buffer_reg[59]_1 ,
    \SHIFTED_DATA_Buffer_reg[60]_0 ,
    \SHIFTED_DATA_Buffer_reg[60]_1 ,
    \SHIFTED_DATA_Buffer_reg[61]_0 ,
    \SHIFTED_DATA_Buffer_reg[61]_1 ,
    \SHIFTED_DATA_Buffer_reg[62]_0 ,
    \SHIFTED_DATA_Buffer_reg[62]_1 ,
    \SHIFTED_DATA_Buffer_reg[63]_0 ,
    \SHIFTED_DATA_Buffer_reg[63]_1 ,
    \SHIFTED_DATA_Buffer_reg[48]_2 ,
    \SHIFTED_DATA_Buffer_reg[48]_3 ,
    \SHIFTED_DATA_Buffer_reg[49]_2 ,
    \SHIFTED_DATA_Buffer_reg[49]_3 ,
    \SHIFTED_DATA_Buffer_reg[50]_2 ,
    \SHIFTED_DATA_Buffer_reg[50]_3 ,
    \SHIFTED_DATA_Buffer_reg[51]_2 ,
    \SHIFTED_DATA_Buffer_reg[51]_3 ,
    \SHIFTED_DATA_Buffer_reg[52]_2 ,
    \SHIFTED_DATA_Buffer_reg[52]_3 ,
    \SHIFTED_DATA_Buffer_reg[53]_2 ,
    \SHIFTED_DATA_Buffer_reg[53]_3 ,
    \SHIFTED_DATA_Buffer_reg[54]_2 ,
    \SHIFTED_DATA_Buffer_reg[54]_3 ,
    \SHIFTED_DATA_Buffer_reg[55]_2 ,
    \SHIFTED_DATA_Buffer_reg[55]_3 ,
    \SHIFTED_DATA_Buffer_reg[56]_2 ,
    \SHIFTED_DATA_Buffer_reg[56]_3 ,
    \SHIFTED_DATA_Buffer_reg[57]_2 ,
    \SHIFTED_DATA_Buffer_reg[57]_3 ,
    \SHIFTED_DATA_Buffer_reg[58]_2 ,
    \SHIFTED_DATA_Buffer_reg[58]_3 ,
    \SHIFTED_DATA_Buffer_reg[59]_2 ,
    \SHIFTED_DATA_Buffer_reg[59]_3 ,
    \SHIFTED_DATA_Buffer_reg[60]_2 ,
    \SHIFTED_DATA_Buffer_reg[60]_3 ,
    \SHIFTED_DATA_Buffer_reg[61]_2 ,
    \SHIFTED_DATA_Buffer_reg[61]_3 ,
    \SHIFTED_DATA_Buffer_reg[62]_2 ,
    \SHIFTED_DATA_Buffer_reg[62]_3 ,
    \SHIFTED_DATA_Buffer_reg[63]_2 ,
    \SHIFTED_DATA_Buffer_reg[63]_3 ,
    D,
    \SHIFTED_DATA_Buffer_reg[32]_0 ,
    \SHIFTED_DATA_Buffer_reg[33]_0 ,
    \SHIFTED_DATA_Buffer_reg[34]_0 ,
    \SHIFTED_DATA_Buffer_reg[35]_0 ,
    \SHIFTED_DATA_Buffer_reg[36]_0 ,
    \SHIFTED_DATA_Buffer_reg[37]_0 ,
    \SHIFTED_DATA_Buffer_reg[38]_0 ,
    \SHIFTED_DATA_Buffer_reg[39]_0 ,
    \SHIFTED_DATA_Buffer_reg[40]_0 ,
    \SHIFTED_DATA_Buffer_reg[41]_0 ,
    \SHIFTED_DATA_Buffer_reg[42]_0 ,
    \SHIFTED_DATA_Buffer_reg[43]_0 ,
    \SHIFTED_DATA_Buffer_reg[44]_0 ,
    \SHIFTED_DATA_Buffer_reg[45]_0 ,
    \SHIFTED_DATA_Buffer_reg[46]_0 ,
    \SHIFTED_DATA_Buffer_reg[47]_0 ,
    UFC_STORAGE_SELECT_Buffer,
    UFC_OUTPUT_SELECT_Buffer,
    MUXED_DATA_Buffer,
    \SHIFTED_DATA_Buffer_reg[63]_4 ,
    \SHIFTED_DATA_Buffer_reg[47]_1 ,
    \SHIFTED_DATA_Buffer_reg[15]_0 ,
    \SHIFTED_DATA_Buffer_reg[62]_4 ,
    \SHIFTED_DATA_Buffer_reg[14]_0 ,
    \SHIFTED_DATA_Buffer_reg[61]_4 ,
    \SHIFTED_DATA_Buffer_reg[13]_0 ,
    \SHIFTED_DATA_Buffer_reg[60]_4 ,
    \SHIFTED_DATA_Buffer_reg[12]_0 ,
    \SHIFTED_DATA_Buffer_reg[59]_4 ,
    \SHIFTED_DATA_Buffer_reg[11]_0 ,
    \SHIFTED_DATA_Buffer_reg[58]_4 ,
    \SHIFTED_DATA_Buffer_reg[10]_0 ,
    \SHIFTED_DATA_Buffer_reg[57]_4 ,
    \SHIFTED_DATA_Buffer_reg[9]_0 ,
    \SHIFTED_DATA_Buffer_reg[56]_4 ,
    \SHIFTED_DATA_Buffer_reg[8]_0 ,
    \SHIFTED_DATA_Buffer_reg[55]_4 ,
    \SHIFTED_DATA_Buffer_reg[7]_0 ,
    \SHIFTED_DATA_Buffer_reg[54]_4 ,
    \SHIFTED_DATA_Buffer_reg[6]_0 ,
    \SHIFTED_DATA_Buffer_reg[53]_4 ,
    \SHIFTED_DATA_Buffer_reg[5]_0 ,
    \SHIFTED_DATA_Buffer_reg[52]_4 ,
    \SHIFTED_DATA_Buffer_reg[4]_0 ,
    \SHIFTED_DATA_Buffer_reg[51]_4 ,
    \SHIFTED_DATA_Buffer_reg[3]_0 ,
    \SHIFTED_DATA_Buffer_reg[50]_4 ,
    \SHIFTED_DATA_Buffer_reg[2]_0 ,
    \SHIFTED_DATA_Buffer_reg[49]_4 ,
    \SHIFTED_DATA_Buffer_reg[1]_0 ,
    \SHIFTED_DATA_Buffer_reg[48]_4 ,
    \SHIFTED_DATA_Buffer_reg[0]_0 ,
    \SHIFTED_DATA_Buffer_reg[32]_1 ,
    \SHIFTED_DATA_Buffer_reg[0]_1 ,
    user_clk);
  output \SHIFTED_DATA_Buffer_reg[48]_0 ;
  output [15:0]Q;
  output \SHIFTED_DATA_Buffer_reg[48]_1 ;
  output \SHIFTED_DATA_Buffer_reg[49]_0 ;
  output \SHIFTED_DATA_Buffer_reg[49]_1 ;
  output \SHIFTED_DATA_Buffer_reg[50]_0 ;
  output \SHIFTED_DATA_Buffer_reg[50]_1 ;
  output \SHIFTED_DATA_Buffer_reg[51]_0 ;
  output \SHIFTED_DATA_Buffer_reg[51]_1 ;
  output \SHIFTED_DATA_Buffer_reg[52]_0 ;
  output \SHIFTED_DATA_Buffer_reg[52]_1 ;
  output \SHIFTED_DATA_Buffer_reg[53]_0 ;
  output \SHIFTED_DATA_Buffer_reg[53]_1 ;
  output \SHIFTED_DATA_Buffer_reg[54]_0 ;
  output \SHIFTED_DATA_Buffer_reg[54]_1 ;
  output \SHIFTED_DATA_Buffer_reg[55]_0 ;
  output \SHIFTED_DATA_Buffer_reg[55]_1 ;
  output \SHIFTED_DATA_Buffer_reg[56]_0 ;
  output \SHIFTED_DATA_Buffer_reg[56]_1 ;
  output \SHIFTED_DATA_Buffer_reg[57]_0 ;
  output \SHIFTED_DATA_Buffer_reg[57]_1 ;
  output \SHIFTED_DATA_Buffer_reg[58]_0 ;
  output \SHIFTED_DATA_Buffer_reg[58]_1 ;
  output \SHIFTED_DATA_Buffer_reg[59]_0 ;
  output \SHIFTED_DATA_Buffer_reg[59]_1 ;
  output \SHIFTED_DATA_Buffer_reg[60]_0 ;
  output \SHIFTED_DATA_Buffer_reg[60]_1 ;
  output \SHIFTED_DATA_Buffer_reg[61]_0 ;
  output \SHIFTED_DATA_Buffer_reg[61]_1 ;
  output \SHIFTED_DATA_Buffer_reg[62]_0 ;
  output \SHIFTED_DATA_Buffer_reg[62]_1 ;
  output \SHIFTED_DATA_Buffer_reg[63]_0 ;
  output \SHIFTED_DATA_Buffer_reg[63]_1 ;
  output \SHIFTED_DATA_Buffer_reg[48]_2 ;
  output \SHIFTED_DATA_Buffer_reg[48]_3 ;
  output \SHIFTED_DATA_Buffer_reg[49]_2 ;
  output \SHIFTED_DATA_Buffer_reg[49]_3 ;
  output \SHIFTED_DATA_Buffer_reg[50]_2 ;
  output \SHIFTED_DATA_Buffer_reg[50]_3 ;
  output \SHIFTED_DATA_Buffer_reg[51]_2 ;
  output \SHIFTED_DATA_Buffer_reg[51]_3 ;
  output \SHIFTED_DATA_Buffer_reg[52]_2 ;
  output \SHIFTED_DATA_Buffer_reg[52]_3 ;
  output \SHIFTED_DATA_Buffer_reg[53]_2 ;
  output \SHIFTED_DATA_Buffer_reg[53]_3 ;
  output \SHIFTED_DATA_Buffer_reg[54]_2 ;
  output \SHIFTED_DATA_Buffer_reg[54]_3 ;
  output \SHIFTED_DATA_Buffer_reg[55]_2 ;
  output \SHIFTED_DATA_Buffer_reg[55]_3 ;
  output \SHIFTED_DATA_Buffer_reg[56]_2 ;
  output \SHIFTED_DATA_Buffer_reg[56]_3 ;
  output \SHIFTED_DATA_Buffer_reg[57]_2 ;
  output \SHIFTED_DATA_Buffer_reg[57]_3 ;
  output \SHIFTED_DATA_Buffer_reg[58]_2 ;
  output \SHIFTED_DATA_Buffer_reg[58]_3 ;
  output \SHIFTED_DATA_Buffer_reg[59]_2 ;
  output \SHIFTED_DATA_Buffer_reg[59]_3 ;
  output \SHIFTED_DATA_Buffer_reg[60]_2 ;
  output \SHIFTED_DATA_Buffer_reg[60]_3 ;
  output \SHIFTED_DATA_Buffer_reg[61]_2 ;
  output \SHIFTED_DATA_Buffer_reg[61]_3 ;
  output \SHIFTED_DATA_Buffer_reg[62]_2 ;
  output \SHIFTED_DATA_Buffer_reg[62]_3 ;
  output \SHIFTED_DATA_Buffer_reg[63]_2 ;
  output \SHIFTED_DATA_Buffer_reg[63]_3 ;
  output [15:0]D;
  output \SHIFTED_DATA_Buffer_reg[32]_0 ;
  output \SHIFTED_DATA_Buffer_reg[33]_0 ;
  output \SHIFTED_DATA_Buffer_reg[34]_0 ;
  output \SHIFTED_DATA_Buffer_reg[35]_0 ;
  output \SHIFTED_DATA_Buffer_reg[36]_0 ;
  output \SHIFTED_DATA_Buffer_reg[37]_0 ;
  output \SHIFTED_DATA_Buffer_reg[38]_0 ;
  output \SHIFTED_DATA_Buffer_reg[39]_0 ;
  output \SHIFTED_DATA_Buffer_reg[40]_0 ;
  output \SHIFTED_DATA_Buffer_reg[41]_0 ;
  output \SHIFTED_DATA_Buffer_reg[42]_0 ;
  output \SHIFTED_DATA_Buffer_reg[43]_0 ;
  output \SHIFTED_DATA_Buffer_reg[44]_0 ;
  output \SHIFTED_DATA_Buffer_reg[45]_0 ;
  output \SHIFTED_DATA_Buffer_reg[46]_0 ;
  output \SHIFTED_DATA_Buffer_reg[47]_0 ;
  input [5:0]UFC_STORAGE_SELECT_Buffer;
  input [3:0]UFC_OUTPUT_SELECT_Buffer;
  input [31:0]MUXED_DATA_Buffer;
  input \SHIFTED_DATA_Buffer_reg[63]_4 ;
  input \SHIFTED_DATA_Buffer_reg[47]_1 ;
  input \SHIFTED_DATA_Buffer_reg[15]_0 ;
  input \SHIFTED_DATA_Buffer_reg[62]_4 ;
  input \SHIFTED_DATA_Buffer_reg[14]_0 ;
  input \SHIFTED_DATA_Buffer_reg[61]_4 ;
  input \SHIFTED_DATA_Buffer_reg[13]_0 ;
  input \SHIFTED_DATA_Buffer_reg[60]_4 ;
  input \SHIFTED_DATA_Buffer_reg[12]_0 ;
  input \SHIFTED_DATA_Buffer_reg[59]_4 ;
  input \SHIFTED_DATA_Buffer_reg[11]_0 ;
  input \SHIFTED_DATA_Buffer_reg[58]_4 ;
  input \SHIFTED_DATA_Buffer_reg[10]_0 ;
  input \SHIFTED_DATA_Buffer_reg[57]_4 ;
  input \SHIFTED_DATA_Buffer_reg[9]_0 ;
  input \SHIFTED_DATA_Buffer_reg[56]_4 ;
  input \SHIFTED_DATA_Buffer_reg[8]_0 ;
  input \SHIFTED_DATA_Buffer_reg[55]_4 ;
  input \SHIFTED_DATA_Buffer_reg[7]_0 ;
  input \SHIFTED_DATA_Buffer_reg[54]_4 ;
  input \SHIFTED_DATA_Buffer_reg[6]_0 ;
  input \SHIFTED_DATA_Buffer_reg[53]_4 ;
  input \SHIFTED_DATA_Buffer_reg[5]_0 ;
  input \SHIFTED_DATA_Buffer_reg[52]_4 ;
  input \SHIFTED_DATA_Buffer_reg[4]_0 ;
  input \SHIFTED_DATA_Buffer_reg[51]_4 ;
  input \SHIFTED_DATA_Buffer_reg[3]_0 ;
  input \SHIFTED_DATA_Buffer_reg[50]_4 ;
  input \SHIFTED_DATA_Buffer_reg[2]_0 ;
  input \SHIFTED_DATA_Buffer_reg[49]_4 ;
  input \SHIFTED_DATA_Buffer_reg[1]_0 ;
  input \SHIFTED_DATA_Buffer_reg[48]_4 ;
  input \SHIFTED_DATA_Buffer_reg[0]_0 ;
  input \SHIFTED_DATA_Buffer_reg[32]_1 ;
  input [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
  input user_clk;

  wire [15:0]D;
  wire [31:0]MUXED_DATA_Buffer;
  wire [15:0]Q;
  wire [16:63]SHIFTED_DATA_Buffer;
  wire \SHIFTED_DATA_Buffer[32]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[33]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[34]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[35]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[36]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[37]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[38]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[39]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[40]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[41]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[42]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[43]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[44]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[45]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[46]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[47]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer[48]_i_1_n_0 ;
  wire \SHIFTED_DATA_Buffer_reg[0]_0 ;
  wire [31:0]\SHIFTED_DATA_Buffer_reg[0]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[10]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[11]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[12]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[13]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[14]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[15]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[1]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[2]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[32]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[32]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[33]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[34]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[35]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[36]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[37]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[38]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[39]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[3]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[40]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[41]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[42]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[43]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[44]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[45]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[46]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[47]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[47]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[48]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[48]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[48]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[48]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[48]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[49]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[49]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[49]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[49]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[49]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[4]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[50]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[50]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[50]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[50]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[50]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[51]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[51]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[51]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[51]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[51]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[52]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[52]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[52]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[52]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[52]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[53]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[53]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[53]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[53]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[53]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[54]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[54]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[54]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[54]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[54]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[55]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[55]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[55]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[55]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[55]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[56]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[56]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[56]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[56]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[56]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[57]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[57]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[57]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[57]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[57]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[58]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[58]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[58]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[58]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[58]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[59]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[59]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[59]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[59]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[59]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[5]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[60]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[60]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[60]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[60]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[60]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[61]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[61]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[61]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[61]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[61]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[62]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[62]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[62]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[62]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[62]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[63]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[63]_1 ;
  wire \SHIFTED_DATA_Buffer_reg[63]_2 ;
  wire \SHIFTED_DATA_Buffer_reg[63]_3 ;
  wire \SHIFTED_DATA_Buffer_reg[63]_4 ;
  wire \SHIFTED_DATA_Buffer_reg[6]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[7]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[8]_0 ;
  wire \SHIFTED_DATA_Buffer_reg[9]_0 ;
  wire [3:0]UFC_OUTPUT_SELECT_Buffer;
  wire [5:0]UFC_STORAGE_SELECT_Buffer;
  wire [0:31]shifted_data_c;
  wire user_clk;

  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[0]_i_1 
       (.I0(SHIFTED_DATA_Buffer[48]),
        .I1(SHIFTED_DATA_Buffer[32]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[16]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[15]),
        .O(\SHIFTED_DATA_Buffer_reg[48]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[10]_i_1 
       (.I0(SHIFTED_DATA_Buffer[58]),
        .I1(SHIFTED_DATA_Buffer[42]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[26]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[5]),
        .O(\SHIFTED_DATA_Buffer_reg[58]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[11]_i_1 
       (.I0(SHIFTED_DATA_Buffer[59]),
        .I1(SHIFTED_DATA_Buffer[43]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[27]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[4]),
        .O(\SHIFTED_DATA_Buffer_reg[59]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[12]_i_1 
       (.I0(SHIFTED_DATA_Buffer[60]),
        .I1(SHIFTED_DATA_Buffer[44]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[28]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[3]),
        .O(\SHIFTED_DATA_Buffer_reg[60]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[13]_i_1 
       (.I0(SHIFTED_DATA_Buffer[61]),
        .I1(SHIFTED_DATA_Buffer[45]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[29]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[2]),
        .O(\SHIFTED_DATA_Buffer_reg[61]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[14]_i_1 
       (.I0(SHIFTED_DATA_Buffer[62]),
        .I1(SHIFTED_DATA_Buffer[46]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[30]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[1]),
        .O(\SHIFTED_DATA_Buffer_reg[62]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[15]_i_1 
       (.I0(SHIFTED_DATA_Buffer[63]),
        .I1(SHIFTED_DATA_Buffer[47]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[31]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[0]),
        .O(\SHIFTED_DATA_Buffer_reg[63]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[16]_i_1 
       (.I0(SHIFTED_DATA_Buffer[48]),
        .I1(SHIFTED_DATA_Buffer[32]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[16]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[15]),
        .O(\SHIFTED_DATA_Buffer_reg[48]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[17]_i_1 
       (.I0(SHIFTED_DATA_Buffer[49]),
        .I1(SHIFTED_DATA_Buffer[33]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[17]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[14]),
        .O(\SHIFTED_DATA_Buffer_reg[49]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[18]_i_1 
       (.I0(SHIFTED_DATA_Buffer[50]),
        .I1(SHIFTED_DATA_Buffer[34]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[18]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[13]),
        .O(\SHIFTED_DATA_Buffer_reg[50]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[19]_i_1 
       (.I0(SHIFTED_DATA_Buffer[51]),
        .I1(SHIFTED_DATA_Buffer[35]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[19]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[12]),
        .O(\SHIFTED_DATA_Buffer_reg[51]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[1]_i_1 
       (.I0(SHIFTED_DATA_Buffer[49]),
        .I1(SHIFTED_DATA_Buffer[33]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[17]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[14]),
        .O(\SHIFTED_DATA_Buffer_reg[49]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[20]_i_1 
       (.I0(SHIFTED_DATA_Buffer[52]),
        .I1(SHIFTED_DATA_Buffer[36]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[20]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[11]),
        .O(\SHIFTED_DATA_Buffer_reg[52]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[21]_i_1 
       (.I0(SHIFTED_DATA_Buffer[53]),
        .I1(SHIFTED_DATA_Buffer[37]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[21]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[10]),
        .O(\SHIFTED_DATA_Buffer_reg[53]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[22]_i_1 
       (.I0(SHIFTED_DATA_Buffer[54]),
        .I1(SHIFTED_DATA_Buffer[38]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[22]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[9]),
        .O(\SHIFTED_DATA_Buffer_reg[54]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[23]_i_1 
       (.I0(SHIFTED_DATA_Buffer[55]),
        .I1(SHIFTED_DATA_Buffer[39]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[23]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[8]),
        .O(\SHIFTED_DATA_Buffer_reg[55]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[24]_i_1 
       (.I0(SHIFTED_DATA_Buffer[56]),
        .I1(SHIFTED_DATA_Buffer[40]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[24]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[7]),
        .O(\SHIFTED_DATA_Buffer_reg[56]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[25]_i_1 
       (.I0(SHIFTED_DATA_Buffer[57]),
        .I1(SHIFTED_DATA_Buffer[41]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[25]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[6]),
        .O(\SHIFTED_DATA_Buffer_reg[57]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[26]_i_1 
       (.I0(SHIFTED_DATA_Buffer[58]),
        .I1(SHIFTED_DATA_Buffer[42]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[26]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[5]),
        .O(\SHIFTED_DATA_Buffer_reg[58]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[27]_i_1 
       (.I0(SHIFTED_DATA_Buffer[59]),
        .I1(SHIFTED_DATA_Buffer[43]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[27]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[4]),
        .O(\SHIFTED_DATA_Buffer_reg[59]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[28]_i_1 
       (.I0(SHIFTED_DATA_Buffer[60]),
        .I1(SHIFTED_DATA_Buffer[44]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[28]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[3]),
        .O(\SHIFTED_DATA_Buffer_reg[60]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[29]_i_1 
       (.I0(SHIFTED_DATA_Buffer[61]),
        .I1(SHIFTED_DATA_Buffer[45]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[29]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[2]),
        .O(\SHIFTED_DATA_Buffer_reg[61]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[2]_i_1 
       (.I0(SHIFTED_DATA_Buffer[50]),
        .I1(SHIFTED_DATA_Buffer[34]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[18]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[13]),
        .O(\SHIFTED_DATA_Buffer_reg[50]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[30]_i_1 
       (.I0(SHIFTED_DATA_Buffer[62]),
        .I1(SHIFTED_DATA_Buffer[46]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[30]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[1]),
        .O(\SHIFTED_DATA_Buffer_reg[62]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[31]_i_1 
       (.I0(SHIFTED_DATA_Buffer[63]),
        .I1(SHIFTED_DATA_Buffer[47]),
        .I2(UFC_STORAGE_SELECT_Buffer[4]),
        .I3(SHIFTED_DATA_Buffer[31]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[0]),
        .O(\SHIFTED_DATA_Buffer_reg[63]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[32]_i_1 
       (.I0(SHIFTED_DATA_Buffer[48]),
        .I1(SHIFTED_DATA_Buffer[32]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[16]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[15]),
        .O(\SHIFTED_DATA_Buffer_reg[48]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[32]_i_1__0 
       (.I0(Q[15]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[16]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[31]),
        .O(D[15]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[33]_i_1 
       (.I0(SHIFTED_DATA_Buffer[49]),
        .I1(SHIFTED_DATA_Buffer[33]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[17]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[14]),
        .O(\SHIFTED_DATA_Buffer_reg[49]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[33]_i_1__0 
       (.I0(Q[14]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[17]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[30]),
        .O(D[14]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[34]_i_1 
       (.I0(SHIFTED_DATA_Buffer[50]),
        .I1(SHIFTED_DATA_Buffer[34]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[18]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[13]),
        .O(\SHIFTED_DATA_Buffer_reg[50]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[34]_i_1__0 
       (.I0(Q[13]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[18]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[29]),
        .O(D[13]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[35]_i_1 
       (.I0(SHIFTED_DATA_Buffer[51]),
        .I1(SHIFTED_DATA_Buffer[35]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[19]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[12]),
        .O(\SHIFTED_DATA_Buffer_reg[51]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[35]_i_1__0 
       (.I0(Q[12]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[19]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[28]),
        .O(D[12]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[36]_i_1 
       (.I0(SHIFTED_DATA_Buffer[52]),
        .I1(SHIFTED_DATA_Buffer[36]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[20]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[11]),
        .O(\SHIFTED_DATA_Buffer_reg[52]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[36]_i_1__0 
       (.I0(Q[11]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[20]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[27]),
        .O(D[11]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[37]_i_1 
       (.I0(SHIFTED_DATA_Buffer[53]),
        .I1(SHIFTED_DATA_Buffer[37]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[21]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[10]),
        .O(\SHIFTED_DATA_Buffer_reg[53]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[37]_i_1__0 
       (.I0(Q[10]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[21]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[26]),
        .O(D[10]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[38]_i_1 
       (.I0(SHIFTED_DATA_Buffer[54]),
        .I1(SHIFTED_DATA_Buffer[38]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[22]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[9]),
        .O(\SHIFTED_DATA_Buffer_reg[54]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[38]_i_1__0 
       (.I0(Q[9]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[22]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[25]),
        .O(D[9]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[39]_i_1 
       (.I0(SHIFTED_DATA_Buffer[55]),
        .I1(SHIFTED_DATA_Buffer[39]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[23]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[8]),
        .O(\SHIFTED_DATA_Buffer_reg[55]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[39]_i_1__0 
       (.I0(Q[8]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[23]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[24]),
        .O(D[8]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[3]_i_1 
       (.I0(SHIFTED_DATA_Buffer[51]),
        .I1(SHIFTED_DATA_Buffer[35]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[19]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[12]),
        .O(\SHIFTED_DATA_Buffer_reg[51]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[40]_i_1 
       (.I0(SHIFTED_DATA_Buffer[56]),
        .I1(SHIFTED_DATA_Buffer[40]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[24]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[7]),
        .O(\SHIFTED_DATA_Buffer_reg[56]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[40]_i_1__0 
       (.I0(Q[7]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[24]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[23]),
        .O(D[7]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[41]_i_1 
       (.I0(SHIFTED_DATA_Buffer[57]),
        .I1(SHIFTED_DATA_Buffer[41]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[25]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[6]),
        .O(\SHIFTED_DATA_Buffer_reg[57]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[41]_i_1__0 
       (.I0(Q[6]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[25]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[22]),
        .O(D[6]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[42]_i_1 
       (.I0(SHIFTED_DATA_Buffer[58]),
        .I1(SHIFTED_DATA_Buffer[42]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[26]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[5]),
        .O(\SHIFTED_DATA_Buffer_reg[58]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[42]_i_1__0 
       (.I0(Q[5]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[26]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[21]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[43]_i_1 
       (.I0(SHIFTED_DATA_Buffer[59]),
        .I1(SHIFTED_DATA_Buffer[43]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[27]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[4]),
        .O(\SHIFTED_DATA_Buffer_reg[59]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[43]_i_1__0 
       (.I0(Q[4]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[27]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[20]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[44]_i_1 
       (.I0(SHIFTED_DATA_Buffer[60]),
        .I1(SHIFTED_DATA_Buffer[44]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[28]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[3]),
        .O(\SHIFTED_DATA_Buffer_reg[60]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[44]_i_1__0 
       (.I0(Q[3]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[28]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[19]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[45]_i_1 
       (.I0(SHIFTED_DATA_Buffer[61]),
        .I1(SHIFTED_DATA_Buffer[45]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[29]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[2]),
        .O(\SHIFTED_DATA_Buffer_reg[61]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[45]_i_1__0 
       (.I0(Q[2]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[29]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[18]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[46]_i_1 
       (.I0(SHIFTED_DATA_Buffer[62]),
        .I1(SHIFTED_DATA_Buffer[46]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[30]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[1]),
        .O(\SHIFTED_DATA_Buffer_reg[62]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[46]_i_1__0 
       (.I0(Q[1]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[30]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[17]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[47]_i_1 
       (.I0(SHIFTED_DATA_Buffer[63]),
        .I1(SHIFTED_DATA_Buffer[47]),
        .I2(UFC_STORAGE_SELECT_Buffer[3]),
        .I3(SHIFTED_DATA_Buffer[31]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[0]),
        .O(\SHIFTED_DATA_Buffer_reg[63]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \MUXED_DATA_Buffer[47]_i_1__0 
       (.I0(Q[0]),
        .I1(UFC_OUTPUT_SELECT_Buffer[2]),
        .I2(SHIFTED_DATA_Buffer[31]),
        .I3(UFC_OUTPUT_SELECT_Buffer[3]),
        .I4(MUXED_DATA_Buffer[16]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[48]_i_1 
       (.I0(SHIFTED_DATA_Buffer[48]),
        .I1(SHIFTED_DATA_Buffer[32]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[16]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[15]),
        .O(\SHIFTED_DATA_Buffer_reg[48]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[48]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[32]),
        .I1(SHIFTED_DATA_Buffer[16]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[15]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[15]),
        .O(\SHIFTED_DATA_Buffer_reg[32]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[49]_i_1 
       (.I0(SHIFTED_DATA_Buffer[49]),
        .I1(SHIFTED_DATA_Buffer[33]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[17]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[14]),
        .O(\SHIFTED_DATA_Buffer_reg[49]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[49]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[33]),
        .I1(SHIFTED_DATA_Buffer[17]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[14]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[14]),
        .O(\SHIFTED_DATA_Buffer_reg[33]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[4]_i_1 
       (.I0(SHIFTED_DATA_Buffer[52]),
        .I1(SHIFTED_DATA_Buffer[36]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[20]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[11]),
        .O(\SHIFTED_DATA_Buffer_reg[52]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[50]_i_1 
       (.I0(SHIFTED_DATA_Buffer[50]),
        .I1(SHIFTED_DATA_Buffer[34]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[18]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[13]),
        .O(\SHIFTED_DATA_Buffer_reg[50]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[50]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[34]),
        .I1(SHIFTED_DATA_Buffer[18]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[13]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[13]),
        .O(\SHIFTED_DATA_Buffer_reg[34]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[51]_i_1 
       (.I0(SHIFTED_DATA_Buffer[51]),
        .I1(SHIFTED_DATA_Buffer[35]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[19]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[12]),
        .O(\SHIFTED_DATA_Buffer_reg[51]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[51]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[35]),
        .I1(SHIFTED_DATA_Buffer[19]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[12]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[12]),
        .O(\SHIFTED_DATA_Buffer_reg[35]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[52]_i_1 
       (.I0(SHIFTED_DATA_Buffer[52]),
        .I1(SHIFTED_DATA_Buffer[36]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[20]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[11]),
        .O(\SHIFTED_DATA_Buffer_reg[52]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[52]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[36]),
        .I1(SHIFTED_DATA_Buffer[20]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[11]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[11]),
        .O(\SHIFTED_DATA_Buffer_reg[36]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[53]_i_1 
       (.I0(SHIFTED_DATA_Buffer[53]),
        .I1(SHIFTED_DATA_Buffer[37]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[21]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[10]),
        .O(\SHIFTED_DATA_Buffer_reg[53]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[53]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[37]),
        .I1(SHIFTED_DATA_Buffer[21]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[10]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[10]),
        .O(\SHIFTED_DATA_Buffer_reg[37]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[54]_i_1 
       (.I0(SHIFTED_DATA_Buffer[54]),
        .I1(SHIFTED_DATA_Buffer[38]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[22]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[9]),
        .O(\SHIFTED_DATA_Buffer_reg[54]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[54]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[38]),
        .I1(SHIFTED_DATA_Buffer[22]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[9]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[9]),
        .O(\SHIFTED_DATA_Buffer_reg[38]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[55]_i_1 
       (.I0(SHIFTED_DATA_Buffer[55]),
        .I1(SHIFTED_DATA_Buffer[39]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[23]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[8]),
        .O(\SHIFTED_DATA_Buffer_reg[55]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[55]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[39]),
        .I1(SHIFTED_DATA_Buffer[23]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[8]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[8]),
        .O(\SHIFTED_DATA_Buffer_reg[39]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[56]_i_1 
       (.I0(SHIFTED_DATA_Buffer[56]),
        .I1(SHIFTED_DATA_Buffer[40]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[24]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[7]),
        .O(\SHIFTED_DATA_Buffer_reg[56]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[56]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[40]),
        .I1(SHIFTED_DATA_Buffer[24]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[7]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[7]),
        .O(\SHIFTED_DATA_Buffer_reg[40]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[57]_i_1 
       (.I0(SHIFTED_DATA_Buffer[57]),
        .I1(SHIFTED_DATA_Buffer[41]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[25]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[6]),
        .O(\SHIFTED_DATA_Buffer_reg[57]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[57]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[41]),
        .I1(SHIFTED_DATA_Buffer[25]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[6]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[6]),
        .O(\SHIFTED_DATA_Buffer_reg[41]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[58]_i_1 
       (.I0(SHIFTED_DATA_Buffer[58]),
        .I1(SHIFTED_DATA_Buffer[42]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[26]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[5]),
        .O(\SHIFTED_DATA_Buffer_reg[58]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[58]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[42]),
        .I1(SHIFTED_DATA_Buffer[26]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[5]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[5]),
        .O(\SHIFTED_DATA_Buffer_reg[42]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[59]_i_1 
       (.I0(SHIFTED_DATA_Buffer[59]),
        .I1(SHIFTED_DATA_Buffer[43]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[27]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[4]),
        .O(\SHIFTED_DATA_Buffer_reg[59]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[59]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[43]),
        .I1(SHIFTED_DATA_Buffer[27]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[4]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[4]),
        .O(\SHIFTED_DATA_Buffer_reg[43]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[5]_i_1 
       (.I0(SHIFTED_DATA_Buffer[53]),
        .I1(SHIFTED_DATA_Buffer[37]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[21]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[10]),
        .O(\SHIFTED_DATA_Buffer_reg[53]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[60]_i_1 
       (.I0(SHIFTED_DATA_Buffer[60]),
        .I1(SHIFTED_DATA_Buffer[44]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[28]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[3]),
        .O(\SHIFTED_DATA_Buffer_reg[60]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[60]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[44]),
        .I1(SHIFTED_DATA_Buffer[28]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[3]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[3]),
        .O(\SHIFTED_DATA_Buffer_reg[44]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[61]_i_1 
       (.I0(SHIFTED_DATA_Buffer[61]),
        .I1(SHIFTED_DATA_Buffer[45]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[29]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[2]),
        .O(\SHIFTED_DATA_Buffer_reg[61]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[61]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[45]),
        .I1(SHIFTED_DATA_Buffer[29]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[2]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[2]),
        .O(\SHIFTED_DATA_Buffer_reg[45]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[62]_i_1 
       (.I0(SHIFTED_DATA_Buffer[62]),
        .I1(SHIFTED_DATA_Buffer[46]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[30]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[1]),
        .O(\SHIFTED_DATA_Buffer_reg[62]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[62]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[46]),
        .I1(SHIFTED_DATA_Buffer[30]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[1]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[1]),
        .O(\SHIFTED_DATA_Buffer_reg[46]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[63]_i_1 
       (.I0(SHIFTED_DATA_Buffer[63]),
        .I1(SHIFTED_DATA_Buffer[47]),
        .I2(UFC_STORAGE_SELECT_Buffer[1]),
        .I3(SHIFTED_DATA_Buffer[31]),
        .I4(UFC_STORAGE_SELECT_Buffer[0]),
        .I5(Q[0]),
        .O(\SHIFTED_DATA_Buffer_reg[63]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[63]_i_1__0 
       (.I0(SHIFTED_DATA_Buffer[47]),
        .I1(SHIFTED_DATA_Buffer[31]),
        .I2(UFC_OUTPUT_SELECT_Buffer[1]),
        .I3(Q[0]),
        .I4(UFC_OUTPUT_SELECT_Buffer[0]),
        .I5(MUXED_DATA_Buffer[0]),
        .O(\SHIFTED_DATA_Buffer_reg[47]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[6]_i_1 
       (.I0(SHIFTED_DATA_Buffer[54]),
        .I1(SHIFTED_DATA_Buffer[38]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[22]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[9]),
        .O(\SHIFTED_DATA_Buffer_reg[54]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[7]_i_1 
       (.I0(SHIFTED_DATA_Buffer[55]),
        .I1(SHIFTED_DATA_Buffer[39]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[23]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[8]),
        .O(\SHIFTED_DATA_Buffer_reg[55]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[8]_i_1 
       (.I0(SHIFTED_DATA_Buffer[56]),
        .I1(SHIFTED_DATA_Buffer[40]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[24]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[7]),
        .O(\SHIFTED_DATA_Buffer_reg[56]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \MUXED_DATA_Buffer[9]_i_1 
       (.I0(SHIFTED_DATA_Buffer[57]),
        .I1(SHIFTED_DATA_Buffer[41]),
        .I2(UFC_STORAGE_SELECT_Buffer[5]),
        .I3(SHIFTED_DATA_Buffer[25]),
        .I4(UFC_STORAGE_SELECT_Buffer[2]),
        .I5(Q[6]),
        .O(\SHIFTED_DATA_Buffer_reg[57]_1 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[0]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [31]),
        .I2(\SHIFTED_DATA_Buffer_reg[48]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[0]_0 ),
        .O(shifted_data_c[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[10]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [21]),
        .I2(\SHIFTED_DATA_Buffer_reg[58]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[10]_0 ),
        .O(shifted_data_c[10]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[11]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [20]),
        .I2(\SHIFTED_DATA_Buffer_reg[59]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[11]_0 ),
        .O(shifted_data_c[11]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[12]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [19]),
        .I2(\SHIFTED_DATA_Buffer_reg[60]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[12]_0 ),
        .O(shifted_data_c[12]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[13]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [18]),
        .I2(\SHIFTED_DATA_Buffer_reg[61]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[13]_0 ),
        .O(shifted_data_c[13]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[14]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [17]),
        .I2(\SHIFTED_DATA_Buffer_reg[62]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[14]_0 ),
        .O(shifted_data_c[14]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[15]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [16]),
        .I2(\SHIFTED_DATA_Buffer_reg[63]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[15]_0 ),
        .O(shifted_data_c[15]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[16]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[48]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [15]),
        .O(shifted_data_c[16]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[17]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[1]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[49]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
        .O(shifted_data_c[17]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[18]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[2]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[50]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
        .O(shifted_data_c[18]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[19]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[3]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[51]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
        .O(shifted_data_c[19]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[1]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [14]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [30]),
        .I2(\SHIFTED_DATA_Buffer_reg[49]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[1]_0 ),
        .O(shifted_data_c[1]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[20]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[4]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[52]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
        .O(shifted_data_c[20]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[21]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[5]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[53]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
        .O(shifted_data_c[21]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[22]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[6]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[54]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
        .O(shifted_data_c[22]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[23]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[7]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[55]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
        .O(shifted_data_c[23]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[24]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[8]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[56]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
        .O(shifted_data_c[24]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[25]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[9]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[57]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
        .O(shifted_data_c[25]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[26]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[10]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[58]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [5]),
        .O(shifted_data_c[26]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[27]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[11]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[59]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [4]),
        .O(shifted_data_c[27]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[28]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[12]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[60]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [3]),
        .O(shifted_data_c[28]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[29]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[13]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[61]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [2]),
        .O(shifted_data_c[29]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[2]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [13]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [29]),
        .I2(\SHIFTED_DATA_Buffer_reg[50]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[2]_0 ),
        .O(shifted_data_c[2]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[30]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[14]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[62]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [1]),
        .O(shifted_data_c[30]));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \SHIFTED_DATA_Buffer[31]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[15]_0 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[63]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[0]_1 [0]),
        .O(shifted_data_c[31]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[32]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[48]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[0]_0 ),
        .O(\SHIFTED_DATA_Buffer[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[33]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[49]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[1]_0 ),
        .O(\SHIFTED_DATA_Buffer[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[34]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[50]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[2]_0 ),
        .O(\SHIFTED_DATA_Buffer[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[35]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[51]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[3]_0 ),
        .O(\SHIFTED_DATA_Buffer[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[36]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[52]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[4]_0 ),
        .O(\SHIFTED_DATA_Buffer[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[37]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[53]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[5]_0 ),
        .O(\SHIFTED_DATA_Buffer[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[38]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[54]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[6]_0 ),
        .O(\SHIFTED_DATA_Buffer[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[39]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[55]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[7]_0 ),
        .O(\SHIFTED_DATA_Buffer[39]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[3]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [12]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [28]),
        .I2(\SHIFTED_DATA_Buffer_reg[51]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[3]_0 ),
        .O(shifted_data_c[3]));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[40]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[56]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[8]_0 ),
        .O(\SHIFTED_DATA_Buffer[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[41]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[57]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[9]_0 ),
        .O(\SHIFTED_DATA_Buffer[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[42]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[58]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[10]_0 ),
        .O(\SHIFTED_DATA_Buffer[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[43]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[59]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[11]_0 ),
        .O(\SHIFTED_DATA_Buffer[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[44]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[60]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[12]_0 ),
        .O(\SHIFTED_DATA_Buffer[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[45]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[61]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[13]_0 ),
        .O(\SHIFTED_DATA_Buffer[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[46]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[62]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[14]_0 ),
        .O(\SHIFTED_DATA_Buffer[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \SHIFTED_DATA_Buffer[47]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[63]_4 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I2(\SHIFTED_DATA_Buffer_reg[15]_0 ),
        .O(\SHIFTED_DATA_Buffer[47]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \SHIFTED_DATA_Buffer[48]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I1(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .O(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[4]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [11]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [27]),
        .I2(\SHIFTED_DATA_Buffer_reg[52]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[4]_0 ),
        .O(shifted_data_c[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[5]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [10]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [26]),
        .I2(\SHIFTED_DATA_Buffer_reg[53]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[5]_0 ),
        .O(shifted_data_c[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[6]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [9]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [25]),
        .I2(\SHIFTED_DATA_Buffer_reg[54]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[6]_0 ),
        .O(shifted_data_c[6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[7]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [8]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [24]),
        .I2(\SHIFTED_DATA_Buffer_reg[55]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[7]_0 ),
        .O(shifted_data_c[7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[8]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [7]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [23]),
        .I2(\SHIFTED_DATA_Buffer_reg[56]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[8]_0 ),
        .O(shifted_data_c[8]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \SHIFTED_DATA_Buffer[9]_i_1 
       (.I0(\SHIFTED_DATA_Buffer_reg[0]_1 [6]),
        .I1(\SHIFTED_DATA_Buffer_reg[0]_1 [22]),
        .I2(\SHIFTED_DATA_Buffer_reg[57]_4 ),
        .I3(\SHIFTED_DATA_Buffer_reg[32]_1 ),
        .I4(\SHIFTED_DATA_Buffer_reg[47]_1 ),
        .I5(\SHIFTED_DATA_Buffer_reg[9]_0 ),
        .O(shifted_data_c[9]));
  FDRE \SHIFTED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[0]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[10]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[11]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[12]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[13]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[14]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[15]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[16]),
        .Q(SHIFTED_DATA_Buffer[16]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[17]),
        .Q(SHIFTED_DATA_Buffer[17]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[18]),
        .Q(SHIFTED_DATA_Buffer[18]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[19]),
        .Q(SHIFTED_DATA_Buffer[19]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[1]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[20]),
        .Q(SHIFTED_DATA_Buffer[20]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[21]),
        .Q(SHIFTED_DATA_Buffer[21]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[22]),
        .Q(SHIFTED_DATA_Buffer[22]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[23]),
        .Q(SHIFTED_DATA_Buffer[23]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[24]),
        .Q(SHIFTED_DATA_Buffer[24]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[25]),
        .Q(SHIFTED_DATA_Buffer[25]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[26]),
        .Q(SHIFTED_DATA_Buffer[26]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[27]),
        .Q(SHIFTED_DATA_Buffer[27]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[28]),
        .Q(SHIFTED_DATA_Buffer[28]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[29]),
        .Q(SHIFTED_DATA_Buffer[29]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[2]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[30]),
        .Q(SHIFTED_DATA_Buffer[30]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[31]),
        .Q(SHIFTED_DATA_Buffer[31]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[32]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[32]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[33]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[33]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[34]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[34]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[35]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[35]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[36]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[36]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[37]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[37]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[38]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[38]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[39]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[39]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[3]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[40]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[40]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[41]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[41]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[42]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[42]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[43]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[43]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[44]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[44]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[45]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[45]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[46]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[46]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer[47]_i_1_n_0 ),
        .Q(SHIFTED_DATA_Buffer[47]),
        .R(\SHIFTED_DATA_Buffer_reg[32]_1 ));
  FDRE \SHIFTED_DATA_Buffer_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[48]_4 ),
        .Q(SHIFTED_DATA_Buffer[48]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[49]_4 ),
        .Q(SHIFTED_DATA_Buffer[49]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[4]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[50]_4 ),
        .Q(SHIFTED_DATA_Buffer[50]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[51]_4 ),
        .Q(SHIFTED_DATA_Buffer[51]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[52]_4 ),
        .Q(SHIFTED_DATA_Buffer[52]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[53]_4 ),
        .Q(SHIFTED_DATA_Buffer[53]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[54]_4 ),
        .Q(SHIFTED_DATA_Buffer[54]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[55]_4 ),
        .Q(SHIFTED_DATA_Buffer[55]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[56]_4 ),
        .Q(SHIFTED_DATA_Buffer[56]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[57]_4 ),
        .Q(SHIFTED_DATA_Buffer[57]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[58]_4 ),
        .Q(SHIFTED_DATA_Buffer[58]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[59]_4 ),
        .Q(SHIFTED_DATA_Buffer[59]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[5]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[60]_4 ),
        .Q(SHIFTED_DATA_Buffer[60]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[61]_4 ),
        .Q(SHIFTED_DATA_Buffer[61]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[62]_4 ),
        .Q(SHIFTED_DATA_Buffer[62]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\SHIFTED_DATA_Buffer_reg[63]_4 ),
        .Q(SHIFTED_DATA_Buffer[63]),
        .R(\SHIFTED_DATA_Buffer[48]_i_1_n_0 ));
  FDRE \SHIFTED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[6]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[7]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[8]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \SHIFTED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(shifted_data_c[9]),
        .Q(Q[6]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_UFC_BARREL_SHIFTER_CONTROL
   (\BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0 ,
    \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0 ,
    \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1 ,
    user_clk,
    \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1 );
  output \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0 ;
  output \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0 ;
  input \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1 ;
  input user_clk;
  input \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1 ;

  wire \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0 ;
  wire \BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1 ;
  wire \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0 ;
  wire \BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1 ;
  wire user_clk;

  FDRE \BARREL_SHIFTER_CONTROL_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\BARREL_SHIFTER_CONTROL_Buffer_reg[1]_1 ),
        .Q(\BARREL_SHIFTER_CONTROL_Buffer_reg[1]_0 ),
        .R(1'b0));
  FDRE \BARREL_SHIFTER_CONTROL_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\BARREL_SHIFTER_CONTROL_Buffer_reg[2]_1 ),
        .Q(\BARREL_SHIFTER_CONTROL_Buffer_reg[2]_0 ),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_UFC_FILTER
   (ufc_start_i,
    pdu_pad_i,
    D,
    \word_aligned_data_r_reg[7] ,
    \word_aligned_data_r_reg[7]_0 ,
    \word_aligned_data_r_reg[7]_1 ,
    \word_aligned_data_r_reg[7]_2 ,
    \word_aligned_data_r_reg[6] ,
    \word_aligned_data_r_reg[6]_0 ,
    \word_aligned_data_r_reg[6]_1 ,
    \word_aligned_data_r_reg[6]_2 ,
    \word_aligned_data_r_reg[5] ,
    \word_aligned_data_r_reg[5]_0 ,
    \word_aligned_data_r_reg[5]_1 ,
    \word_aligned_data_r_reg[5]_2 ,
    \word_aligned_data_r_reg[4] ,
    \word_aligned_data_r_reg[4]_0 ,
    \word_aligned_data_r_reg[4]_1 ,
    \word_aligned_data_r_reg[4]_2 ,
    \word_aligned_data_r_reg[3] ,
    \word_aligned_data_r_reg[3]_0 ,
    \word_aligned_data_r_reg[3]_1 ,
    \word_aligned_data_r_reg[3]_2 ,
    \word_aligned_data_r_reg[2] ,
    \word_aligned_data_r_reg[2]_0 ,
    \word_aligned_data_r_reg[2]_1 ,
    \word_aligned_data_r_reg[2]_2 ,
    \word_aligned_data_r_reg[1] ,
    \word_aligned_data_r_reg[1]_0 ,
    \word_aligned_data_r_reg[1]_1 ,
    \word_aligned_data_r_reg[1]_2 ,
    \word_aligned_data_r_reg[0] ,
    \word_aligned_data_r_reg[0]_0 ,
    \word_aligned_data_r_reg[0]_1 ,
    \word_aligned_data_r_reg[0]_2 ,
    \word_aligned_data_r_reg[15] ,
    \word_aligned_data_r_reg[15]_0 ,
    \word_aligned_data_r_reg[15]_1 ,
    \word_aligned_data_r_reg[15]_2 ,
    \word_aligned_data_r_reg[14] ,
    \word_aligned_data_r_reg[14]_0 ,
    \word_aligned_data_r_reg[14]_1 ,
    \word_aligned_data_r_reg[14]_2 ,
    \word_aligned_data_r_reg[13] ,
    \word_aligned_data_r_reg[13]_0 ,
    \word_aligned_data_r_reg[13]_1 ,
    \word_aligned_data_r_reg[13]_2 ,
    \word_aligned_data_r_reg[12] ,
    \word_aligned_data_r_reg[12]_0 ,
    \word_aligned_data_r_reg[12]_1 ,
    \word_aligned_data_r_reg[12]_2 ,
    \word_aligned_data_r_reg[11] ,
    \word_aligned_data_r_reg[11]_0 ,
    \word_aligned_data_r_reg[11]_1 ,
    \word_aligned_data_r_reg[11]_2 ,
    \RX_PE_DATA_Buffer_reg[10] ,
    \RX_PE_DATA_Buffer_reg[10]_0 ,
    \RX_PE_DATA_Buffer_reg[10]_1 ,
    \RX_PE_DATA_Buffer_reg[10]_2 ,
    \RX_PE_DATA_Buffer_reg[9] ,
    \RX_PE_DATA_Buffer_reg[9]_0 ,
    \RX_PE_DATA_Buffer_reg[9]_1 ,
    \RX_PE_DATA_Buffer_reg[9]_2 ,
    \RX_PE_DATA_Buffer_reg[8] ,
    \RX_PE_DATA_Buffer_reg[8]_0 ,
    \RX_PE_DATA_Buffer_reg[8]_1 ,
    \RX_PE_DATA_Buffer_reg[8]_2 ,
    \PDU_ECP_Buffer_reg[3]_0 ,
    \PDU_SCP_Buffer_reg[0]_0 ,
    \PDU_ECP_Buffer_reg[2]_0 ,
    \PDU_ECP_Buffer_reg[1]_0 ,
    \PDU_ECP_Buffer_reg[0]_0 ,
    \UFC_MESSAGE_START_Buffer_reg[1]_0 ,
    \UFC_MESSAGE_START_Buffer_reg[1]_1 ,
    \PDU_DATA_V_Buffer_reg[0]_0 ,
    \UFC_DATA_V_Buffer_reg[0]_0 ,
    \PDU_SCP_Buffer_reg[3]_0 ,
    S1_in,
    S3_in,
    S5_in,
    RESET,
    neqOp,
    user_clk,
    \stage_1_lane_mask_r_reg[3]_0 ,
    \stage_1_lane_mask_r_reg[1]_0 ,
    \stage_1_lane_mask_r_reg[2]_0 ,
    std_bool26_out,
    std_bool26_out_0,
    std_bool26_out_1,
    std_bool26_out_2,
    RX_ECP_Buffer0,
    RX_ECP_Buffer0_3,
    RX_ECP_Buffer0_4,
    RX_ECP_Buffer0_5,
    \stage_1_data_r_reg[0] ,
    \stage_1_data_r_reg[16] ,
    \stage_1_data_r_reg[48] ,
    \stage_1_data_r_reg[32] ,
    \stage_1_data_r_reg[11] ,
    Q,
    \stage_1_data_r_reg[59] ,
    \stage_1_data_r_reg[43] ,
    RX_PE_DATA,
    \stage_1_data_r_reg[26] ,
    \stage_1_data_r_reg[58] ,
    \stage_1_data_r_reg[42] ,
    \stage_1_data_r_reg[25] ,
    \stage_1_data_r_reg[57] ,
    \stage_1_data_r_reg[41] ,
    \stage_1_data_r_reg[24] ,
    \stage_1_data_r_reg[56] ,
    \stage_1_data_r_reg[40] ,
    \stage_1_count_value_r_reg[0]_0 ,
    \stage_1_count_value_r_reg[1]_0 ,
    \stage_1_count_value_r_reg[2]_0 ,
    \stage_1_count_value_r_reg[3]_0 ,
    \rx_data_v_r_reg[0]_0 ,
    \rx_scp_r_reg[0]_0 ,
    \rx_suf_r_reg[0]_0 );
  output ufc_start_i;
  output [0:3]pdu_pad_i;
  output [3:0]D;
  output \word_aligned_data_r_reg[7] ;
  output \word_aligned_data_r_reg[7]_0 ;
  output \word_aligned_data_r_reg[7]_1 ;
  output \word_aligned_data_r_reg[7]_2 ;
  output \word_aligned_data_r_reg[6] ;
  output \word_aligned_data_r_reg[6]_0 ;
  output \word_aligned_data_r_reg[6]_1 ;
  output \word_aligned_data_r_reg[6]_2 ;
  output \word_aligned_data_r_reg[5] ;
  output \word_aligned_data_r_reg[5]_0 ;
  output \word_aligned_data_r_reg[5]_1 ;
  output \word_aligned_data_r_reg[5]_2 ;
  output \word_aligned_data_r_reg[4] ;
  output \word_aligned_data_r_reg[4]_0 ;
  output \word_aligned_data_r_reg[4]_1 ;
  output \word_aligned_data_r_reg[4]_2 ;
  output \word_aligned_data_r_reg[3] ;
  output \word_aligned_data_r_reg[3]_0 ;
  output \word_aligned_data_r_reg[3]_1 ;
  output \word_aligned_data_r_reg[3]_2 ;
  output \word_aligned_data_r_reg[2] ;
  output \word_aligned_data_r_reg[2]_0 ;
  output \word_aligned_data_r_reg[2]_1 ;
  output \word_aligned_data_r_reg[2]_2 ;
  output \word_aligned_data_r_reg[1] ;
  output \word_aligned_data_r_reg[1]_0 ;
  output \word_aligned_data_r_reg[1]_1 ;
  output \word_aligned_data_r_reg[1]_2 ;
  output \word_aligned_data_r_reg[0] ;
  output \word_aligned_data_r_reg[0]_0 ;
  output \word_aligned_data_r_reg[0]_1 ;
  output \word_aligned_data_r_reg[0]_2 ;
  output \word_aligned_data_r_reg[15] ;
  output \word_aligned_data_r_reg[15]_0 ;
  output \word_aligned_data_r_reg[15]_1 ;
  output \word_aligned_data_r_reg[15]_2 ;
  output \word_aligned_data_r_reg[14] ;
  output \word_aligned_data_r_reg[14]_0 ;
  output \word_aligned_data_r_reg[14]_1 ;
  output \word_aligned_data_r_reg[14]_2 ;
  output \word_aligned_data_r_reg[13] ;
  output \word_aligned_data_r_reg[13]_0 ;
  output \word_aligned_data_r_reg[13]_1 ;
  output \word_aligned_data_r_reg[13]_2 ;
  output \word_aligned_data_r_reg[12] ;
  output \word_aligned_data_r_reg[12]_0 ;
  output \word_aligned_data_r_reg[12]_1 ;
  output \word_aligned_data_r_reg[12]_2 ;
  output \word_aligned_data_r_reg[11] ;
  output \word_aligned_data_r_reg[11]_0 ;
  output \word_aligned_data_r_reg[11]_1 ;
  output \word_aligned_data_r_reg[11]_2 ;
  output \RX_PE_DATA_Buffer_reg[10] ;
  output \RX_PE_DATA_Buffer_reg[10]_0 ;
  output \RX_PE_DATA_Buffer_reg[10]_1 ;
  output \RX_PE_DATA_Buffer_reg[10]_2 ;
  output \RX_PE_DATA_Buffer_reg[9] ;
  output \RX_PE_DATA_Buffer_reg[9]_0 ;
  output \RX_PE_DATA_Buffer_reg[9]_1 ;
  output \RX_PE_DATA_Buffer_reg[9]_2 ;
  output \RX_PE_DATA_Buffer_reg[8] ;
  output \RX_PE_DATA_Buffer_reg[8]_0 ;
  output \RX_PE_DATA_Buffer_reg[8]_1 ;
  output \RX_PE_DATA_Buffer_reg[8]_2 ;
  output \PDU_ECP_Buffer_reg[3]_0 ;
  output [3:0]\PDU_SCP_Buffer_reg[0]_0 ;
  output \PDU_ECP_Buffer_reg[2]_0 ;
  output \PDU_ECP_Buffer_reg[1]_0 ;
  output \PDU_ECP_Buffer_reg[0]_0 ;
  output \UFC_MESSAGE_START_Buffer_reg[1]_0 ;
  output \UFC_MESSAGE_START_Buffer_reg[1]_1 ;
  output [3:0]\PDU_DATA_V_Buffer_reg[0]_0 ;
  output [3:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
  output \PDU_SCP_Buffer_reg[3]_0 ;
  output S1_in;
  output S3_in;
  output S5_in;
  input RESET;
  input neqOp;
  input user_clk;
  input \stage_1_lane_mask_r_reg[3]_0 ;
  input \stage_1_lane_mask_r_reg[1]_0 ;
  input \stage_1_lane_mask_r_reg[2]_0 ;
  input std_bool26_out;
  input std_bool26_out_0;
  input std_bool26_out_1;
  input std_bool26_out_2;
  input RX_ECP_Buffer0;
  input RX_ECP_Buffer0_3;
  input RX_ECP_Buffer0_4;
  input RX_ECP_Buffer0_5;
  input [7:0]\stage_1_data_r_reg[0] ;
  input [7:0]\stage_1_data_r_reg[16] ;
  input [7:0]\stage_1_data_r_reg[48] ;
  input [7:0]\stage_1_data_r_reg[32] ;
  input [4:0]\stage_1_data_r_reg[11] ;
  input [4:0]Q;
  input [4:0]\stage_1_data_r_reg[59] ;
  input [4:0]\stage_1_data_r_reg[43] ;
  input [2:0]RX_PE_DATA;
  input \stage_1_data_r_reg[26] ;
  input \stage_1_data_r_reg[58] ;
  input \stage_1_data_r_reg[42] ;
  input \stage_1_data_r_reg[25] ;
  input \stage_1_data_r_reg[57] ;
  input \stage_1_data_r_reg[41] ;
  input \stage_1_data_r_reg[24] ;
  input \stage_1_data_r_reg[56] ;
  input \stage_1_data_r_reg[40] ;
  input \stage_1_count_value_r_reg[0]_0 ;
  input \stage_1_count_value_r_reg[1]_0 ;
  input \stage_1_count_value_r_reg[2]_0 ;
  input \stage_1_count_value_r_reg[3]_0 ;
  input [3:0]\rx_data_v_r_reg[0]_0 ;
  input [3:0]\rx_scp_r_reg[0]_0 ;
  input [3:0]\rx_suf_r_reg[0]_0 ;

  wire [3:0]D;
  wire \PDU_DATA_V_Buffer[0]_i_1_n_0 ;
  wire \PDU_DATA_V_Buffer[1]_i_1_n_0 ;
  wire \PDU_DATA_V_Buffer[2]_i_1_n_0 ;
  wire \PDU_DATA_V_Buffer[3]_i_1_n_0 ;
  wire [3:0]\PDU_DATA_V_Buffer_reg[0]_0 ;
  wire \PDU_ECP_Buffer_reg[0]_0 ;
  wire \PDU_ECP_Buffer_reg[1]_0 ;
  wire \PDU_ECP_Buffer_reg[2]_0 ;
  wire \PDU_ECP_Buffer_reg[3]_0 ;
  wire [3:0]\PDU_SCP_Buffer_reg[0]_0 ;
  wire \PDU_SCP_Buffer_reg[3]_0 ;
  wire [4:0]Q;
  wire RESET;
  wire RX_ECP_Buffer0;
  wire RX_ECP_Buffer0_3;
  wire RX_ECP_Buffer0_4;
  wire RX_ECP_Buffer0_5;
  wire [2:0]RX_PE_DATA;
  wire \RX_PE_DATA_Buffer_reg[10] ;
  wire \RX_PE_DATA_Buffer_reg[10]_0 ;
  wire \RX_PE_DATA_Buffer_reg[10]_1 ;
  wire \RX_PE_DATA_Buffer_reg[10]_2 ;
  wire \RX_PE_DATA_Buffer_reg[8] ;
  wire \RX_PE_DATA_Buffer_reg[8]_0 ;
  wire \RX_PE_DATA_Buffer_reg[8]_1 ;
  wire \RX_PE_DATA_Buffer_reg[8]_2 ;
  wire \RX_PE_DATA_Buffer_reg[9] ;
  wire \RX_PE_DATA_Buffer_reg[9]_0 ;
  wire \RX_PE_DATA_Buffer_reg[9]_1 ;
  wire \RX_PE_DATA_Buffer_reg[9]_2 ;
  wire S1_in;
  wire S3_in;
  wire S5_in;
  wire \UFC_DATA_V_Buffer[1]_i_1_n_0 ;
  wire \UFC_DATA_V_Buffer[2]_i_1_n_0 ;
  wire \UFC_DATA_V_Buffer[3]_i_1_n_0 ;
  wire [3:0]\UFC_DATA_V_Buffer_reg[0]_0 ;
  wire \UFC_MESSAGE_START_Buffer_reg[1]_0 ;
  wire \UFC_MESSAGE_START_Buffer_reg[1]_1 ;
  wire load_ufc_control_code_r;
  wire neqOp;
  wire \neqOp_inferred__0/i__n_0 ;
  wire [0:3]pdu_pad_i;
  wire [0:3]rx_data_v_r;
  wire [3:0]\rx_data_v_r_reg[0]_0 ;
  wire \rx_ecp_r_reg[0]_srl2_n_0 ;
  wire \rx_ecp_r_reg[1]_srl2_n_0 ;
  wire \rx_ecp_r_reg[2]_srl2_n_0 ;
  wire \rx_ecp_r_reg[3]_srl2_n_0 ;
  wire \rx_pad_r_reg[0]_srl2_n_0 ;
  wire \rx_pad_r_reg[1]_srl2_n_0 ;
  wire \rx_pad_r_reg[2]_srl2_n_0 ;
  wire \rx_pad_r_reg[3]_srl2_n_0 ;
  wire [0:3]rx_scp_r;
  wire [3:0]\rx_scp_r_reg[0]_0 ;
  wire [3:0]\rx_suf_r_reg[0]_0 ;
  wire \rx_suf_r_reg_n_0_[0] ;
  wire \rx_suf_r_reg_n_0_[1] ;
  wire \rx_suf_r_reg_n_0_[2] ;
  wire \rx_suf_r_reg_n_0_[3] ;
  wire save_start_r;
  wire [0:3]stage_1_count_value_r;
  wire \stage_1_count_value_r_reg[0]_0 ;
  wire \stage_1_count_value_r_reg[1]_0 ;
  wire \stage_1_count_value_r_reg[2]_0 ;
  wire \stage_1_count_value_r_reg[3]_0 ;
  wire [7:0]\stage_1_data_r_reg[0] ;
  wire [4:0]\stage_1_data_r_reg[11] ;
  wire [7:0]\stage_1_data_r_reg[16] ;
  wire \stage_1_data_r_reg[24] ;
  wire \stage_1_data_r_reg[25] ;
  wire \stage_1_data_r_reg[26] ;
  wire [7:0]\stage_1_data_r_reg[32] ;
  wire \stage_1_data_r_reg[40] ;
  wire \stage_1_data_r_reg[41] ;
  wire \stage_1_data_r_reg[42] ;
  wire [4:0]\stage_1_data_r_reg[43] ;
  wire [7:0]\stage_1_data_r_reg[48] ;
  wire \stage_1_data_r_reg[56] ;
  wire \stage_1_data_r_reg[57] ;
  wire \stage_1_data_r_reg[58] ;
  wire [4:0]\stage_1_data_r_reg[59] ;
  wire \stage_1_lane_mask_r_reg[1]_0 ;
  wire \stage_1_lane_mask_r_reg[2]_0 ;
  wire \stage_1_lane_mask_r_reg[3]_0 ;
  wire \stage_1_lane_mask_r_reg_n_0_[1] ;
  wire \stage_1_lane_mask_r_reg_n_0_[2] ;
  wire \stage_1_lane_mask_r_reg_n_0_[3] ;
  wire [0:3]stage_2_count_value_r;
  wire \stage_2_count_value_r[0]_i_1_n_0 ;
  wire \stage_2_count_value_r[1]_i_1_n_0 ;
  wire \stage_2_count_value_r[2]_i_1_n_0 ;
  wire \stage_2_count_value_r[3]_i_1_n_0 ;
  wire [0:0]stage_2_lane_mask_c__0;
  wire std_bool26_out;
  wire std_bool26_out_0;
  wire std_bool26_out_1;
  wire std_bool26_out_2;
  wire [0:2]ufc_message_start_i;
  wire ufc_start_i;
  wire user_clk;
  wire \word_aligned_data_r_reg[0] ;
  wire \word_aligned_data_r_reg[0]_0 ;
  wire \word_aligned_data_r_reg[0]_1 ;
  wire \word_aligned_data_r_reg[0]_2 ;
  wire \word_aligned_data_r_reg[11] ;
  wire \word_aligned_data_r_reg[11]_0 ;
  wire \word_aligned_data_r_reg[11]_1 ;
  wire \word_aligned_data_r_reg[11]_2 ;
  wire \word_aligned_data_r_reg[12] ;
  wire \word_aligned_data_r_reg[12]_0 ;
  wire \word_aligned_data_r_reg[12]_1 ;
  wire \word_aligned_data_r_reg[12]_2 ;
  wire \word_aligned_data_r_reg[13] ;
  wire \word_aligned_data_r_reg[13]_0 ;
  wire \word_aligned_data_r_reg[13]_1 ;
  wire \word_aligned_data_r_reg[13]_2 ;
  wire \word_aligned_data_r_reg[14] ;
  wire \word_aligned_data_r_reg[14]_0 ;
  wire \word_aligned_data_r_reg[14]_1 ;
  wire \word_aligned_data_r_reg[14]_2 ;
  wire \word_aligned_data_r_reg[15] ;
  wire \word_aligned_data_r_reg[15]_0 ;
  wire \word_aligned_data_r_reg[15]_1 ;
  wire \word_aligned_data_r_reg[15]_2 ;
  wire \word_aligned_data_r_reg[1] ;
  wire \word_aligned_data_r_reg[1]_0 ;
  wire \word_aligned_data_r_reg[1]_1 ;
  wire \word_aligned_data_r_reg[1]_2 ;
  wire \word_aligned_data_r_reg[2] ;
  wire \word_aligned_data_r_reg[2]_0 ;
  wire \word_aligned_data_r_reg[2]_1 ;
  wire \word_aligned_data_r_reg[2]_2 ;
  wire \word_aligned_data_r_reg[3] ;
  wire \word_aligned_data_r_reg[3]_0 ;
  wire \word_aligned_data_r_reg[3]_1 ;
  wire \word_aligned_data_r_reg[3]_2 ;
  wire \word_aligned_data_r_reg[4] ;
  wire \word_aligned_data_r_reg[4]_0 ;
  wire \word_aligned_data_r_reg[4]_1 ;
  wire \word_aligned_data_r_reg[4]_2 ;
  wire \word_aligned_data_r_reg[5] ;
  wire \word_aligned_data_r_reg[5]_0 ;
  wire \word_aligned_data_r_reg[5]_1 ;
  wire \word_aligned_data_r_reg[5]_2 ;
  wire \word_aligned_data_r_reg[6] ;
  wire \word_aligned_data_r_reg[6]_0 ;
  wire \word_aligned_data_r_reg[6]_1 ;
  wire \word_aligned_data_r_reg[6]_2 ;
  wire \word_aligned_data_r_reg[7] ;
  wire \word_aligned_data_r_reg[7]_0 ;
  wire \word_aligned_data_r_reg[7]_1 ;
  wire \word_aligned_data_r_reg[7]_2 ;

  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[0]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[0]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [7]),
        .Q(\word_aligned_data_r_reg[0] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[10]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[10]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[0]),
        .Q(\RX_PE_DATA_Buffer_reg[10] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[11]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[11]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [4]),
        .Q(\word_aligned_data_r_reg[11] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[12]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[12]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [3]),
        .Q(\word_aligned_data_r_reg[12] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[13]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[13]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [2]),
        .Q(\word_aligned_data_r_reg[13] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[14]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[14]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [1]),
        .Q(\word_aligned_data_r_reg[14] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[15]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[15]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[11] [0]),
        .Q(\word_aligned_data_r_reg[15] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[16]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[16]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [7]),
        .Q(\word_aligned_data_r_reg[0]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[17]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[17]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [6]),
        .Q(\word_aligned_data_r_reg[1]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[18]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[18]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [5]),
        .Q(\word_aligned_data_r_reg[2]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[19]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[19]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [4]),
        .Q(\word_aligned_data_r_reg[3]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[1]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[1]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [6]),
        .Q(\word_aligned_data_r_reg[1] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[20]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[20]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [3]),
        .Q(\word_aligned_data_r_reg[4]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[21]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[21]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [2]),
        .Q(\word_aligned_data_r_reg[5]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[22]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[22]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [1]),
        .Q(\word_aligned_data_r_reg[6]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[23]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[23]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[16] [0]),
        .Q(\word_aligned_data_r_reg[7]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[24]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[24]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[24] ),
        .Q(\RX_PE_DATA_Buffer_reg[8]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[25]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[25]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[25] ),
        .Q(\RX_PE_DATA_Buffer_reg[9]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[26]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[26]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[26] ),
        .Q(\RX_PE_DATA_Buffer_reg[10]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[27]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[27]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(Q[4]),
        .Q(\word_aligned_data_r_reg[11]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[28]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[28]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(Q[3]),
        .Q(\word_aligned_data_r_reg[12]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[29]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[29]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(Q[2]),
        .Q(\word_aligned_data_r_reg[13]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[2]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[2]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [5]),
        .Q(\word_aligned_data_r_reg[2] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[30]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[30]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(Q[1]),
        .Q(\word_aligned_data_r_reg[14]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[31]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[31]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(Q[0]),
        .Q(\word_aligned_data_r_reg[15]_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[32]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[32]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [7]),
        .Q(\word_aligned_data_r_reg[0]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[33]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[33]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [6]),
        .Q(\word_aligned_data_r_reg[1]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[34]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[34]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [5]),
        .Q(\word_aligned_data_r_reg[2]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[35]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[35]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [4]),
        .Q(\word_aligned_data_r_reg[3]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[36]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[36]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [3]),
        .Q(\word_aligned_data_r_reg[4]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[37]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[37]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [2]),
        .Q(\word_aligned_data_r_reg[5]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[38]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[38]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [1]),
        .Q(\word_aligned_data_r_reg[6]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[39]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[39]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[32] [0]),
        .Q(\word_aligned_data_r_reg[7]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[3]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[3]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [4]),
        .Q(\word_aligned_data_r_reg[3] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[40]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[40]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[40] ),
        .Q(\RX_PE_DATA_Buffer_reg[8]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[41]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[41]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[41] ),
        .Q(\RX_PE_DATA_Buffer_reg[9]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[42]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[42]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[42] ),
        .Q(\RX_PE_DATA_Buffer_reg[10]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[43]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[43]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[43] [4]),
        .Q(\word_aligned_data_r_reg[11]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[44]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[44]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[43] [3]),
        .Q(\word_aligned_data_r_reg[12]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[45]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[45]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[43] [2]),
        .Q(\word_aligned_data_r_reg[13]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[46]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[46]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[43] [1]),
        .Q(\word_aligned_data_r_reg[14]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[47]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[47]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[43] [0]),
        .Q(\word_aligned_data_r_reg[15]_2 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[48]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[48]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [7]),
        .Q(\word_aligned_data_r_reg[0]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[49]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[49]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [6]),
        .Q(\word_aligned_data_r_reg[1]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[4]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[4]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [3]),
        .Q(\word_aligned_data_r_reg[4] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[50]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[50]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [5]),
        .Q(\word_aligned_data_r_reg[2]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[51]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[51]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [4]),
        .Q(\word_aligned_data_r_reg[3]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[52]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[52]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [3]),
        .Q(\word_aligned_data_r_reg[4]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[53]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[53]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [2]),
        .Q(\word_aligned_data_r_reg[5]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[54]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[54]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [1]),
        .Q(\word_aligned_data_r_reg[6]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[55]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[55]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[48] [0]),
        .Q(\word_aligned_data_r_reg[7]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[56]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[56]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[56] ),
        .Q(\RX_PE_DATA_Buffer_reg[8]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[57]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[57]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[57] ),
        .Q(\RX_PE_DATA_Buffer_reg[9]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[58]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[58]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[58] ),
        .Q(\RX_PE_DATA_Buffer_reg[10]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[59]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[59]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[59] [4]),
        .Q(\word_aligned_data_r_reg[11]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[5]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[5]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [2]),
        .Q(\word_aligned_data_r_reg[5] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[60]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[60]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[59] [3]),
        .Q(\word_aligned_data_r_reg[12]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[61]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[61]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[59] [2]),
        .Q(\word_aligned_data_r_reg[13]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[62]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[62]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[59] [1]),
        .Q(\word_aligned_data_r_reg[14]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[63]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[63]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[59] [0]),
        .Q(\word_aligned_data_r_reg[15]_1 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[6]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[6]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [1]),
        .Q(\word_aligned_data_r_reg[6] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[7]_srl4 " *) 
  SRL16E \PDU_DATA_Buffer_reg[7]_srl4 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(\stage_1_data_r_reg[0] [0]),
        .Q(\word_aligned_data_r_reg[7] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[8]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[8]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[2]),
        .Q(\RX_PE_DATA_Buffer_reg[8] ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/PDU_DATA_Buffer_reg[9]_srl2 " *) 
  SRL16E \PDU_DATA_Buffer_reg[9]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_PE_DATA[1]),
        .Q(\RX_PE_DATA_Buffer_reg[9] ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT5 #(
    .INIT(32'h88888882)) 
    \PDU_DATA_V_Buffer[0]_i_1 
       (.I0(rx_data_v_r[0]),
        .I1(stage_2_count_value_r[0]),
        .I2(stage_2_count_value_r[1]),
        .I3(stage_2_count_value_r[2]),
        .I4(stage_2_count_value_r[3]),
        .O(\PDU_DATA_V_Buffer[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AA02A802)) 
    \PDU_DATA_V_Buffer[1]_i_1 
       (.I0(rx_data_v_r[1]),
        .I1(stage_2_count_value_r[2]),
        .I2(stage_2_count_value_r[1]),
        .I3(stage_2_count_value_r[0]),
        .I4(stage_2_count_value_r[3]),
        .I5(\stage_1_lane_mask_r_reg_n_0_[1] ),
        .O(\PDU_DATA_V_Buffer[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000888A8A82)) 
    \PDU_DATA_V_Buffer[2]_i_1 
       (.I0(rx_data_v_r[2]),
        .I1(stage_2_count_value_r[0]),
        .I2(stage_2_count_value_r[1]),
        .I3(stage_2_count_value_r[2]),
        .I4(stage_2_count_value_r[3]),
        .I5(\stage_1_lane_mask_r_reg_n_0_[2] ),
        .O(\PDU_DATA_V_Buffer[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000A2A2A282)) 
    \PDU_DATA_V_Buffer[3]_i_1 
       (.I0(rx_data_v_r[3]),
        .I1(stage_2_count_value_r[1]),
        .I2(stage_2_count_value_r[0]),
        .I3(stage_2_count_value_r[3]),
        .I4(stage_2_count_value_r[2]),
        .I5(\stage_1_lane_mask_r_reg_n_0_[3] ),
        .O(\PDU_DATA_V_Buffer[3]_i_1_n_0 ));
  FDRE \PDU_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\PDU_DATA_V_Buffer[0]_i_1_n_0 ),
        .Q(\PDU_DATA_V_Buffer_reg[0]_0 [3]),
        .R(RESET));
  FDRE \PDU_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\PDU_DATA_V_Buffer[1]_i_1_n_0 ),
        .Q(\PDU_DATA_V_Buffer_reg[0]_0 [2]),
        .R(RESET));
  FDRE \PDU_DATA_V_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\PDU_DATA_V_Buffer[2]_i_1_n_0 ),
        .Q(\PDU_DATA_V_Buffer_reg[0]_0 [1]),
        .R(RESET));
  FDRE \PDU_DATA_V_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\PDU_DATA_V_Buffer[3]_i_1_n_0 ),
        .Q(\PDU_DATA_V_Buffer_reg[0]_0 [0]),
        .R(RESET));
  FDRE \PDU_ECP_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_ecp_r_reg[0]_srl2_n_0 ),
        .Q(D[3]),
        .R(1'b0));
  FDRE \PDU_ECP_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_ecp_r_reg[1]_srl2_n_0 ),
        .Q(D[2]),
        .R(1'b0));
  FDRE \PDU_ECP_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_ecp_r_reg[2]_srl2_n_0 ),
        .Q(D[1]),
        .R(1'b0));
  FDRE \PDU_ECP_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_ecp_r_reg[3]_srl2_n_0 ),
        .Q(D[0]),
        .R(1'b0));
  FDRE \PDU_PAD_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_pad_r_reg[0]_srl2_n_0 ),
        .Q(pdu_pad_i[0]),
        .R(1'b0));
  FDRE \PDU_PAD_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_pad_r_reg[1]_srl2_n_0 ),
        .Q(pdu_pad_i[1]),
        .R(1'b0));
  FDRE \PDU_PAD_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_pad_r_reg[2]_srl2_n_0 ),
        .Q(pdu_pad_i[2]),
        .R(1'b0));
  FDRE \PDU_PAD_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_pad_r_reg[3]_srl2_n_0 ),
        .Q(pdu_pad_i[3]),
        .R(1'b0));
  FDRE \PDU_SCP_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_scp_r[0]),
        .Q(\PDU_SCP_Buffer_reg[0]_0 [3]),
        .R(1'b0));
  FDRE \PDU_SCP_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_scp_r[1]),
        .Q(\PDU_SCP_Buffer_reg[0]_0 [2]),
        .R(1'b0));
  FDRE \PDU_SCP_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_scp_r[2]),
        .Q(\PDU_SCP_Buffer_reg[0]_0 [1]),
        .R(1'b0));
  FDRE \PDU_SCP_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_scp_r[3]),
        .Q(\PDU_SCP_Buffer_reg[0]_0 [0]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAFAFAFBA)) 
    \UFC_DATA_V_Buffer[1]_i_1 
       (.I0(\stage_1_lane_mask_r_reg_n_0_[1] ),
        .I1(stage_2_count_value_r[3]),
        .I2(stage_2_count_value_r[0]),
        .I3(stage_2_count_value_r[1]),
        .I4(stage_2_count_value_r[2]),
        .O(\UFC_DATA_V_Buffer[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAABFFEA)) 
    \UFC_DATA_V_Buffer[2]_i_1 
       (.I0(\stage_1_lane_mask_r_reg_n_0_[2] ),
        .I1(stage_2_count_value_r[3]),
        .I2(stage_2_count_value_r[2]),
        .I3(stage_2_count_value_r[1]),
        .I4(stage_2_count_value_r[0]),
        .O(\UFC_DATA_V_Buffer[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAFFABAA)) 
    \UFC_DATA_V_Buffer[3]_i_1 
       (.I0(\stage_1_lane_mask_r_reg_n_0_[3] ),
        .I1(stage_2_count_value_r[2]),
        .I2(stage_2_count_value_r[3]),
        .I3(stage_2_count_value_r[0]),
        .I4(stage_2_count_value_r[1]),
        .O(\UFC_DATA_V_Buffer[3]_i_1_n_0 ));
  FDRE \UFC_DATA_V_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(stage_2_lane_mask_c__0),
        .Q(\UFC_DATA_V_Buffer_reg[0]_0 [3]),
        .R(RESET));
  FDRE \UFC_DATA_V_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_DATA_V_Buffer[1]_i_1_n_0 ),
        .Q(\UFC_DATA_V_Buffer_reg[0]_0 [2]),
        .R(RESET));
  FDRE \UFC_DATA_V_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_DATA_V_Buffer[2]_i_1_n_0 ),
        .Q(\UFC_DATA_V_Buffer_reg[0]_0 [1]),
        .R(RESET));
  FDRE \UFC_DATA_V_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_DATA_V_Buffer[3]_i_1_n_0 ),
        .Q(\UFC_DATA_V_Buffer_reg[0]_0 [0]),
        .R(RESET));
  FDRE \UFC_MESSAGE_START_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg_n_0_[0] ),
        .Q(ufc_message_start_i[0]),
        .R(RESET));
  FDRE \UFC_MESSAGE_START_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg_n_0_[1] ),
        .Q(ufc_message_start_i[1]),
        .R(RESET));
  FDRE \UFC_MESSAGE_START_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg_n_0_[2] ),
        .Q(ufc_message_start_i[2]),
        .R(RESET));
  FDRE UFC_START_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\neqOp_inferred__0/i__n_0 ),
        .Q(ufc_start_i),
        .R(RESET));
  LUT1 #(
    .INIT(2'h1)) 
    data_after_start_muxcy_0_i_1
       (.I0(\PDU_SCP_Buffer_reg[0]_0 [3]),
        .O(S5_in));
  LUT1 #(
    .INIT(2'h1)) 
    data_after_start_muxcy_1_i_1
       (.I0(\PDU_SCP_Buffer_reg[0]_0 [2]),
        .O(S3_in));
  LUT1 #(
    .INIT(2'h1)) 
    data_after_start_muxcy_2_i_1
       (.I0(\PDU_SCP_Buffer_reg[0]_0 [1]),
        .O(S1_in));
  LUT1 #(
    .INIT(2'h1)) 
    data_after_start_muxcy_3_i_1
       (.I0(\PDU_SCP_Buffer_reg[0]_0 [0]),
        .O(\PDU_SCP_Buffer_reg[3]_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    in_frame_muxcy_0_i_1
       (.I0(D[3]),
        .I1(\PDU_SCP_Buffer_reg[0]_0 [3]),
        .O(\PDU_ECP_Buffer_reg[0]_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    in_frame_muxcy_1_i_1
       (.I0(D[2]),
        .I1(\PDU_SCP_Buffer_reg[0]_0 [2]),
        .O(\PDU_ECP_Buffer_reg[1]_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    in_frame_muxcy_2_i_1
       (.I0(D[1]),
        .I1(\PDU_SCP_Buffer_reg[0]_0 [1]),
        .O(\PDU_ECP_Buffer_reg[2]_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    in_frame_muxcy_3_i_1
       (.I0(D[0]),
        .I1(\PDU_SCP_Buffer_reg[0]_0 [0]),
        .O(\PDU_ECP_Buffer_reg[3]_0 ));
  FDRE load_ufc_control_code_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(neqOp),
        .Q(load_ufc_control_code_r),
        .R(RESET));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \neqOp_inferred__0/i_ 
       (.I0(\rx_suf_r_reg_n_0_[2] ),
        .I1(save_start_r),
        .I2(\rx_suf_r_reg_n_0_[1] ),
        .I3(\rx_suf_r_reg_n_0_[0] ),
        .O(\neqOp_inferred__0/i__n_0 ));
  FDRE \rx_data_v_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_data_v_r_reg[0]_0 [3]),
        .Q(rx_data_v_r[0]),
        .R(RESET));
  FDRE \rx_data_v_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_data_v_r_reg[0]_0 [2]),
        .Q(rx_data_v_r[1]),
        .R(RESET));
  FDRE \rx_data_v_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_data_v_r_reg[0]_0 [1]),
        .Q(rx_data_v_r[2]),
        .R(RESET));
  FDRE \rx_data_v_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_data_v_r_reg[0]_0 [0]),
        .Q(rx_data_v_r[3]),
        .R(RESET));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[0]_srl2 " *) 
  SRL16E \rx_ecp_r_reg[0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_ECP_Buffer0),
        .Q(\rx_ecp_r_reg[0]_srl2_n_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[1]_srl2 " *) 
  SRL16E \rx_ecp_r_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_ECP_Buffer0_3),
        .Q(\rx_ecp_r_reg[1]_srl2_n_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[2]_srl2 " *) 
  SRL16E \rx_ecp_r_reg[2]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_ECP_Buffer0_4),
        .Q(\rx_ecp_r_reg[2]_srl2_n_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_ecp_r_reg[3]_srl2 " *) 
  SRL16E \rx_ecp_r_reg[3]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(RX_ECP_Buffer0_5),
        .Q(\rx_ecp_r_reg[3]_srl2_n_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[0]_srl2 " *) 
  SRL16E \rx_pad_r_reg[0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(std_bool26_out),
        .Q(\rx_pad_r_reg[0]_srl2_n_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[1]_srl2 " *) 
  SRL16E \rx_pad_r_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(std_bool26_out_0),
        .Q(\rx_pad_r_reg[1]_srl2_n_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[2]_srl2 " *) 
  SRL16E \rx_pad_r_reg[2]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(std_bool26_out_1),
        .Q(\rx_pad_r_reg[2]_srl2_n_0 ));
  (* srl_bus_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg " *) 
  (* srl_name = "U0/\rx_ll_i/ufc_filter_i/rx_pad_r_reg[3]_srl2 " *) 
  SRL16E \rx_pad_r_reg[3]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(user_clk),
        .D(std_bool26_out_2),
        .Q(\rx_pad_r_reg[3]_srl2_n_0 ));
  FDRE \rx_scp_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_scp_r_reg[0]_0 [3]),
        .Q(rx_scp_r[0]),
        .R(1'b0));
  FDRE \rx_scp_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_scp_r_reg[0]_0 [2]),
        .Q(rx_scp_r[1]),
        .R(1'b0));
  FDRE \rx_scp_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_scp_r_reg[0]_0 [1]),
        .Q(rx_scp_r[2]),
        .R(1'b0));
  FDRE \rx_scp_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_scp_r_reg[0]_0 [0]),
        .Q(rx_scp_r[3]),
        .R(1'b0));
  FDRE \rx_suf_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg[0]_0 [3]),
        .Q(\rx_suf_r_reg_n_0_[0] ),
        .R(RESET));
  FDRE \rx_suf_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg[0]_0 [2]),
        .Q(\rx_suf_r_reg_n_0_[1] ),
        .R(RESET));
  FDRE \rx_suf_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg[0]_0 [1]),
        .Q(\rx_suf_r_reg_n_0_[2] ),
        .R(RESET));
  FDRE \rx_suf_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg[0]_0 [0]),
        .Q(\rx_suf_r_reg_n_0_[3] ),
        .R(RESET));
  FDRE save_start_r_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_suf_r_reg_n_0_[3] ),
        .Q(save_start_r),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[0]_0 ),
        .Q(stage_1_count_value_r[0]),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[1]_0 ),
        .Q(stage_1_count_value_r[1]),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[2]_0 ),
        .Q(stage_1_count_value_r[2]),
        .R(RESET));
  FDRE \stage_1_count_value_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_count_value_r_reg[3]_0 ),
        .Q(stage_1_count_value_r[3]),
        .R(RESET));
  FDRE \stage_1_lane_mask_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_lane_mask_r_reg[1]_0 ),
        .Q(\stage_1_lane_mask_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \stage_1_lane_mask_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_lane_mask_r_reg[2]_0 ),
        .Q(\stage_1_lane_mask_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \stage_1_lane_mask_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_1_lane_mask_r_reg[3]_0 ),
        .Q(\stage_1_lane_mask_r_reg_n_0_[3] ),
        .R(RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \stage_2_count_value_r[0]_i_1 
       (.I0(load_ufc_control_code_r),
        .I1(stage_1_count_value_r[0]),
        .O(\stage_2_count_value_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888888B8888)) 
    \stage_2_count_value_r[1]_i_1 
       (.I0(stage_1_count_value_r[1]),
        .I1(load_ufc_control_code_r),
        .I2(stage_2_count_value_r[3]),
        .I3(stage_2_count_value_r[1]),
        .I4(stage_2_count_value_r[0]),
        .I5(stage_2_count_value_r[2]),
        .O(\stage_2_count_value_r[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8B888888)) 
    \stage_2_count_value_r[2]_i_1 
       (.I0(stage_1_count_value_r[2]),
        .I1(load_ufc_control_code_r),
        .I2(stage_2_count_value_r[0]),
        .I3(stage_2_count_value_r[2]),
        .I4(stage_2_count_value_r[1]),
        .O(\stage_2_count_value_r[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8B888888)) 
    \stage_2_count_value_r[3]_i_1 
       (.I0(stage_1_count_value_r[3]),
        .I1(load_ufc_control_code_r),
        .I2(stage_2_count_value_r[0]),
        .I3(stage_2_count_value_r[3]),
        .I4(stage_2_count_value_r[1]),
        .O(\stage_2_count_value_r[3]_i_1_n_0 ));
  FDRE \stage_2_count_value_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[0]_i_1_n_0 ),
        .Q(stage_2_count_value_r[0]),
        .R(RESET));
  FDRE \stage_2_count_value_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[1]_i_1_n_0 ),
        .Q(stage_2_count_value_r[1]),
        .R(RESET));
  FDRE \stage_2_count_value_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[2]_i_1_n_0 ),
        .Q(stage_2_count_value_r[2]),
        .R(RESET));
  FDRE \stage_2_count_value_r_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\stage_2_count_value_r[3]_i_1_n_0 ),
        .Q(stage_2_count_value_r[3]),
        .R(RESET));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'h01FE)) 
    stage_2_lane_mask_c
       (.I0(stage_2_count_value_r[3]),
        .I1(stage_2_count_value_r[2]),
        .I2(stage_2_count_value_r[1]),
        .I3(stage_2_count_value_r[0]),
        .O(stage_2_lane_mask_c__0));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \ufc_barrel_shifter_control_i/BARREL_SHIFTER_CONTROL_Buffer[1]_i_1 
       (.I0(ufc_message_start_i[1]),
        .I1(ufc_message_start_i[2]),
        .I2(ufc_message_start_i[0]),
        .O(\UFC_MESSAGE_START_Buffer_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \ufc_barrel_shifter_control_i/BARREL_SHIFTER_CONTROL_Buffer[2]_i_1 
       (.I0(ufc_message_start_i[1]),
        .I1(ufc_message_start_i[2]),
        .I2(ufc_message_start_i[0]),
        .O(\UFC_MESSAGE_START_Buffer_reg[1]_1 ));
endmodule

module aurora_rx_4l_64b_UFC_OUTPUT_MUX
   (M_AXI_UFC_RX_TDATA,
    D,
    user_clk,
    UFC_OUTPUT_SELECT_Buffer,
    \MUXED_DATA_Buffer_reg[48]_0 ,
    \MUXED_DATA_Buffer_reg[49]_0 ,
    \MUXED_DATA_Buffer_reg[50]_0 ,
    \MUXED_DATA_Buffer_reg[51]_0 ,
    \MUXED_DATA_Buffer_reg[52]_0 ,
    \MUXED_DATA_Buffer_reg[53]_0 ,
    \MUXED_DATA_Buffer_reg[54]_0 ,
    \MUXED_DATA_Buffer_reg[55]_0 ,
    \MUXED_DATA_Buffer_reg[56]_0 ,
    \MUXED_DATA_Buffer_reg[57]_0 ,
    \MUXED_DATA_Buffer_reg[58]_0 ,
    \MUXED_DATA_Buffer_reg[59]_0 ,
    \MUXED_DATA_Buffer_reg[60]_0 ,
    \MUXED_DATA_Buffer_reg[61]_0 ,
    \MUXED_DATA_Buffer_reg[62]_0 ,
    \MUXED_DATA_Buffer_reg[63]_0 ,
    \MUXED_DATA_Buffer_reg[16]_0 ,
    \MUXED_DATA_Buffer_reg[17]_0 ,
    \MUXED_DATA_Buffer_reg[18]_0 ,
    \MUXED_DATA_Buffer_reg[19]_0 ,
    \MUXED_DATA_Buffer_reg[20]_0 ,
    \MUXED_DATA_Buffer_reg[21]_0 ,
    \MUXED_DATA_Buffer_reg[22]_0 ,
    \MUXED_DATA_Buffer_reg[23]_0 ,
    \MUXED_DATA_Buffer_reg[24]_0 ,
    \MUXED_DATA_Buffer_reg[25]_0 ,
    \MUXED_DATA_Buffer_reg[26]_0 ,
    \MUXED_DATA_Buffer_reg[27]_0 ,
    \MUXED_DATA_Buffer_reg[28]_0 ,
    \MUXED_DATA_Buffer_reg[29]_0 ,
    \MUXED_DATA_Buffer_reg[30]_0 ,
    \MUXED_DATA_Buffer_reg[31]_0 );
  output [63:0]M_AXI_UFC_RX_TDATA;
  input [31:0]D;
  input user_clk;
  input [0:0]UFC_OUTPUT_SELECT_Buffer;
  input \MUXED_DATA_Buffer_reg[48]_0 ;
  input \MUXED_DATA_Buffer_reg[49]_0 ;
  input \MUXED_DATA_Buffer_reg[50]_0 ;
  input \MUXED_DATA_Buffer_reg[51]_0 ;
  input \MUXED_DATA_Buffer_reg[52]_0 ;
  input \MUXED_DATA_Buffer_reg[53]_0 ;
  input \MUXED_DATA_Buffer_reg[54]_0 ;
  input \MUXED_DATA_Buffer_reg[55]_0 ;
  input \MUXED_DATA_Buffer_reg[56]_0 ;
  input \MUXED_DATA_Buffer_reg[57]_0 ;
  input \MUXED_DATA_Buffer_reg[58]_0 ;
  input \MUXED_DATA_Buffer_reg[59]_0 ;
  input \MUXED_DATA_Buffer_reg[60]_0 ;
  input \MUXED_DATA_Buffer_reg[61]_0 ;
  input \MUXED_DATA_Buffer_reg[62]_0 ;
  input \MUXED_DATA_Buffer_reg[63]_0 ;
  input \MUXED_DATA_Buffer_reg[16]_0 ;
  input \MUXED_DATA_Buffer_reg[17]_0 ;
  input \MUXED_DATA_Buffer_reg[18]_0 ;
  input \MUXED_DATA_Buffer_reg[19]_0 ;
  input \MUXED_DATA_Buffer_reg[20]_0 ;
  input \MUXED_DATA_Buffer_reg[21]_0 ;
  input \MUXED_DATA_Buffer_reg[22]_0 ;
  input \MUXED_DATA_Buffer_reg[23]_0 ;
  input \MUXED_DATA_Buffer_reg[24]_0 ;
  input \MUXED_DATA_Buffer_reg[25]_0 ;
  input \MUXED_DATA_Buffer_reg[26]_0 ;
  input \MUXED_DATA_Buffer_reg[27]_0 ;
  input \MUXED_DATA_Buffer_reg[28]_0 ;
  input \MUXED_DATA_Buffer_reg[29]_0 ;
  input \MUXED_DATA_Buffer_reg[30]_0 ;
  input \MUXED_DATA_Buffer_reg[31]_0 ;

  wire [31:0]D;
  wire \MUXED_DATA_Buffer_reg[16]_0 ;
  wire \MUXED_DATA_Buffer_reg[17]_0 ;
  wire \MUXED_DATA_Buffer_reg[18]_0 ;
  wire \MUXED_DATA_Buffer_reg[19]_0 ;
  wire \MUXED_DATA_Buffer_reg[20]_0 ;
  wire \MUXED_DATA_Buffer_reg[21]_0 ;
  wire \MUXED_DATA_Buffer_reg[22]_0 ;
  wire \MUXED_DATA_Buffer_reg[23]_0 ;
  wire \MUXED_DATA_Buffer_reg[24]_0 ;
  wire \MUXED_DATA_Buffer_reg[25]_0 ;
  wire \MUXED_DATA_Buffer_reg[26]_0 ;
  wire \MUXED_DATA_Buffer_reg[27]_0 ;
  wire \MUXED_DATA_Buffer_reg[28]_0 ;
  wire \MUXED_DATA_Buffer_reg[29]_0 ;
  wire \MUXED_DATA_Buffer_reg[30]_0 ;
  wire \MUXED_DATA_Buffer_reg[31]_0 ;
  wire \MUXED_DATA_Buffer_reg[48]_0 ;
  wire \MUXED_DATA_Buffer_reg[49]_0 ;
  wire \MUXED_DATA_Buffer_reg[50]_0 ;
  wire \MUXED_DATA_Buffer_reg[51]_0 ;
  wire \MUXED_DATA_Buffer_reg[52]_0 ;
  wire \MUXED_DATA_Buffer_reg[53]_0 ;
  wire \MUXED_DATA_Buffer_reg[54]_0 ;
  wire \MUXED_DATA_Buffer_reg[55]_0 ;
  wire \MUXED_DATA_Buffer_reg[56]_0 ;
  wire \MUXED_DATA_Buffer_reg[57]_0 ;
  wire \MUXED_DATA_Buffer_reg[58]_0 ;
  wire \MUXED_DATA_Buffer_reg[59]_0 ;
  wire \MUXED_DATA_Buffer_reg[60]_0 ;
  wire \MUXED_DATA_Buffer_reg[61]_0 ;
  wire \MUXED_DATA_Buffer_reg[62]_0 ;
  wire \MUXED_DATA_Buffer_reg[63]_0 ;
  wire [63:0]M_AXI_UFC_RX_TDATA;
  wire [0:0]UFC_OUTPUT_SELECT_Buffer;
  wire user_clk;

  FDRE \MUXED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[31]),
        .Q(M_AXI_UFC_RX_TDATA[7]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[21]),
        .Q(M_AXI_UFC_RX_TDATA[13]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[20]),
        .Q(M_AXI_UFC_RX_TDATA[12]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[19]),
        .Q(M_AXI_UFC_RX_TDATA[11]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[18]),
        .Q(M_AXI_UFC_RX_TDATA[10]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[17]),
        .Q(M_AXI_UFC_RX_TDATA[9]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[16]),
        .Q(M_AXI_UFC_RX_TDATA[8]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[16]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[23]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[17]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[22]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[18]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[21]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[19]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[20]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[30]),
        .Q(M_AXI_UFC_RX_TDATA[6]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[20]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[19]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[21]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[18]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[22]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[17]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[23]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[16]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[24]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[31]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[25]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[30]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[26]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[29]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[27]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[28]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[28]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[27]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[29]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[26]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[29]),
        .Q(M_AXI_UFC_RX_TDATA[5]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[30]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[25]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[31]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[24]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[15]),
        .Q(M_AXI_UFC_RX_TDATA[39]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[14]),
        .Q(M_AXI_UFC_RX_TDATA[38]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[13]),
        .Q(M_AXI_UFC_RX_TDATA[37]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[12]),
        .Q(M_AXI_UFC_RX_TDATA[36]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[11]),
        .Q(M_AXI_UFC_RX_TDATA[35]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[10]),
        .Q(M_AXI_UFC_RX_TDATA[34]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[9]),
        .Q(M_AXI_UFC_RX_TDATA[33]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[8]),
        .Q(M_AXI_UFC_RX_TDATA[32]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[28]),
        .Q(M_AXI_UFC_RX_TDATA[4]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[7]),
        .Q(M_AXI_UFC_RX_TDATA[47]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[6]),
        .Q(M_AXI_UFC_RX_TDATA[46]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[5]),
        .Q(M_AXI_UFC_RX_TDATA[45]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[4]),
        .Q(M_AXI_UFC_RX_TDATA[44]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(M_AXI_UFC_RX_TDATA[43]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(M_AXI_UFC_RX_TDATA[42]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(M_AXI_UFC_RX_TDATA[41]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(M_AXI_UFC_RX_TDATA[40]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[48]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[55]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[49]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[54]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[27]),
        .Q(M_AXI_UFC_RX_TDATA[3]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[50]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[53]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[51]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[52]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[52]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[51]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[53]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[50]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[54]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[49]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[55]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[48]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[56]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[63]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[57]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[62]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[58]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[61]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[59]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[60]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[26]),
        .Q(M_AXI_UFC_RX_TDATA[2]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[60]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[59]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[61]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[58]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[62]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[57]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[63]_0 ),
        .Q(M_AXI_UFC_RX_TDATA[56]),
        .R(UFC_OUTPUT_SELECT_Buffer));
  FDRE \MUXED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[25]),
        .Q(M_AXI_UFC_RX_TDATA[1]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[24]),
        .Q(M_AXI_UFC_RX_TDATA[0]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[23]),
        .Q(M_AXI_UFC_RX_TDATA[15]),
        .R(1'b0));
  FDRE \MUXED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[22]),
        .Q(M_AXI_UFC_RX_TDATA[14]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_UFC_OUTPUT_SWITCH_CONTROL
   (\MUXED_DATA_Buffer_reg[16] ,
    \UFC_OUTPUT_SELECT_Buffer_reg[7]_0 ,
    \MUXED_DATA_Buffer_reg[17] ,
    \MUXED_DATA_Buffer_reg[18] ,
    \MUXED_DATA_Buffer_reg[19] ,
    \MUXED_DATA_Buffer_reg[20] ,
    \MUXED_DATA_Buffer_reg[21] ,
    \MUXED_DATA_Buffer_reg[22] ,
    \MUXED_DATA_Buffer_reg[23] ,
    \MUXED_DATA_Buffer_reg[24] ,
    \MUXED_DATA_Buffer_reg[25] ,
    \MUXED_DATA_Buffer_reg[26] ,
    \MUXED_DATA_Buffer_reg[27] ,
    \MUXED_DATA_Buffer_reg[28] ,
    \MUXED_DATA_Buffer_reg[29] ,
    \MUXED_DATA_Buffer_reg[30] ,
    \MUXED_DATA_Buffer_reg[31] ,
    MUXED_DATA_Buffer,
    Q,
    \UFC_OUTPUT_SELECT_Buffer_reg[7]_1 ,
    user_clk,
    \UFC_OUTPUT_SELECT_Buffer_reg[9]_0 );
  output \MUXED_DATA_Buffer_reg[16] ;
  output [4:0]\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 ;
  output \MUXED_DATA_Buffer_reg[17] ;
  output \MUXED_DATA_Buffer_reg[18] ;
  output \MUXED_DATA_Buffer_reg[19] ;
  output \MUXED_DATA_Buffer_reg[20] ;
  output \MUXED_DATA_Buffer_reg[21] ;
  output \MUXED_DATA_Buffer_reg[22] ;
  output \MUXED_DATA_Buffer_reg[23] ;
  output \MUXED_DATA_Buffer_reg[24] ;
  output \MUXED_DATA_Buffer_reg[25] ;
  output \MUXED_DATA_Buffer_reg[26] ;
  output \MUXED_DATA_Buffer_reg[27] ;
  output \MUXED_DATA_Buffer_reg[28] ;
  output \MUXED_DATA_Buffer_reg[29] ;
  output \MUXED_DATA_Buffer_reg[30] ;
  output \MUXED_DATA_Buffer_reg[31] ;
  input [15:0]MUXED_DATA_Buffer;
  input [15:0]Q;
  input [2:0]\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 ;
  input user_clk;
  input \UFC_OUTPUT_SELECT_Buffer_reg[9]_0 ;

  wire [15:0]MUXED_DATA_Buffer;
  wire \MUXED_DATA_Buffer_reg[16] ;
  wire \MUXED_DATA_Buffer_reg[17] ;
  wire \MUXED_DATA_Buffer_reg[18] ;
  wire \MUXED_DATA_Buffer_reg[19] ;
  wire \MUXED_DATA_Buffer_reg[20] ;
  wire \MUXED_DATA_Buffer_reg[21] ;
  wire \MUXED_DATA_Buffer_reg[22] ;
  wire \MUXED_DATA_Buffer_reg[23] ;
  wire \MUXED_DATA_Buffer_reg[24] ;
  wire \MUXED_DATA_Buffer_reg[25] ;
  wire \MUXED_DATA_Buffer_reg[26] ;
  wire \MUXED_DATA_Buffer_reg[27] ;
  wire \MUXED_DATA_Buffer_reg[28] ;
  wire \MUXED_DATA_Buffer_reg[29] ;
  wire \MUXED_DATA_Buffer_reg[30] ;
  wire \MUXED_DATA_Buffer_reg[31] ;
  wire [15:0]Q;
  wire [7:6]UFC_OUTPUT_SELECT_Buffer;
  wire \UFC_OUTPUT_SELECT_Buffer[10]_i_1_n_0 ;
  wire \UFC_OUTPUT_SELECT_Buffer[11]_i_1_n_0 ;
  wire \UFC_OUTPUT_SELECT_Buffer[4]_i_1_n_0 ;
  wire \UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ;
  wire \UFC_OUTPUT_SELECT_Buffer[7]_i_1_n_0 ;
  wire \UFC_OUTPUT_SELECT_Buffer[8]_i_1_n_0 ;
  wire [4:0]\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 ;
  wire [2:0]\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 ;
  wire \UFC_OUTPUT_SELECT_Buffer_reg[9]_0 ;
  wire user_clk;

  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[16]_i_1__0 
       (.I0(MUXED_DATA_Buffer[15]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[15]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[16] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[17]_i_1__0 
       (.I0(MUXED_DATA_Buffer[14]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[14]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[17] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[18]_i_1__0 
       (.I0(MUXED_DATA_Buffer[13]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[13]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[18] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[19]_i_1__0 
       (.I0(MUXED_DATA_Buffer[12]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[12]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[19] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[20]_i_1__0 
       (.I0(MUXED_DATA_Buffer[11]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[11]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[20] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[21]_i_1__0 
       (.I0(MUXED_DATA_Buffer[10]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[10]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[21] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[22]_i_1__0 
       (.I0(MUXED_DATA_Buffer[9]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[9]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[22] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[23]_i_1__0 
       (.I0(MUXED_DATA_Buffer[8]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[8]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[23] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[24]_i_1__0 
       (.I0(MUXED_DATA_Buffer[7]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[7]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[24] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[25]_i_1__0 
       (.I0(MUXED_DATA_Buffer[6]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[6]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[25] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[26]_i_1__0 
       (.I0(MUXED_DATA_Buffer[5]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[5]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[26] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[27]_i_1__0 
       (.I0(MUXED_DATA_Buffer[4]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[4]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[27] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[28]_i_1__0 
       (.I0(MUXED_DATA_Buffer[3]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[3]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[28] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[29]_i_1__0 
       (.I0(MUXED_DATA_Buffer[2]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[2]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[29] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[30]_i_1__0 
       (.I0(MUXED_DATA_Buffer[1]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[1]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[30] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \MUXED_DATA_Buffer[31]_i_1__0 
       (.I0(MUXED_DATA_Buffer[0]),
        .I1(UFC_OUTPUT_SELECT_Buffer[6]),
        .I2(Q[0]),
        .I3(UFC_OUTPUT_SELECT_Buffer[7]),
        .O(\MUXED_DATA_Buffer_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT3 #(
    .INIT(8'h14)) 
    \UFC_OUTPUT_SELECT_Buffer[10]_i_1 
       (.I0(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [2]),
        .I1(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [1]),
        .I2(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [0]),
        .O(\UFC_OUTPUT_SELECT_Buffer[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \UFC_OUTPUT_SELECT_Buffer[11]_i_1 
       (.I0(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [2]),
        .I1(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [0]),
        .O(\UFC_OUTPUT_SELECT_Buffer[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \UFC_OUTPUT_SELECT_Buffer[4]_i_1 
       (.I0(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [1]),
        .I1(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [0]),
        .I2(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [2]),
        .O(\UFC_OUTPUT_SELECT_Buffer[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \UFC_OUTPUT_SELECT_Buffer[5]_i_1 
       (.I0(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [1]),
        .I1(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [0]),
        .I2(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [2]),
        .O(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \UFC_OUTPUT_SELECT_Buffer[7]_i_1 
       (.I0(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [1]),
        .I1(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [2]),
        .O(\UFC_OUTPUT_SELECT_Buffer[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \UFC_OUTPUT_SELECT_Buffer[8]_i_1 
       (.I0(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [0]),
        .I1(\UFC_OUTPUT_SELECT_Buffer_reg[7]_1 [2]),
        .O(\UFC_OUTPUT_SELECT_Buffer[8]_i_1_n_0 ));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer[10]_i_1_n_0 ),
        .Q(\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 [1]),
        .R(1'b0));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer[11]_i_1_n_0 ),
        .Q(\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer[4]_i_1_n_0 ),
        .Q(UFC_OUTPUT_SELECT_Buffer[7]),
        .R(1'b0));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer[5]_i_1_n_0 ),
        .Q(UFC_OUTPUT_SELECT_Buffer[6]),
        .R(1'b0));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer[7]_i_1_n_0 ),
        .Q(\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 [4]),
        .R(1'b0));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer[8]_i_1_n_0 ),
        .Q(\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 [3]),
        .R(1'b0));
  FDRE \UFC_OUTPUT_SELECT_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_OUTPUT_SELECT_Buffer_reg[9]_0 ),
        .Q(\UFC_OUTPUT_SELECT_Buffer_reg[7]_0 [2]),
        .R(1'b0));
endmodule

module aurora_rx_4l_64b_UFC_SIDEBAND_OUTPUT
   (UFC_SRC_RDY_N_Buffer,
    UFC_EOF_N_Buffer,
    Q,
    RESET,
    UFC_SRC_RDY_N_Buffer_reg_0,
    user_clk,
    UFC_EOF_N_Buffer_reg_0,
    D);
  output UFC_SRC_RDY_N_Buffer;
  output UFC_EOF_N_Buffer;
  output [1:0]Q;
  input RESET;
  input UFC_SRC_RDY_N_Buffer_reg_0;
  input user_clk;
  input UFC_EOF_N_Buffer_reg_0;
  input [1:0]D;

  wire [1:0]D;
  wire [1:0]Q;
  wire RESET;
  wire UFC_EOF_N_Buffer;
  wire UFC_EOF_N_Buffer_reg_0;
  wire UFC_SRC_RDY_N_Buffer;
  wire UFC_SRC_RDY_N_Buffer_reg_0;
  wire user_clk;

  FDRE UFC_EOF_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_EOF_N_Buffer_reg_0),
        .Q(UFC_EOF_N_Buffer),
        .R(1'b0));
  FDRE \UFC_REM_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \UFC_REM_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDSE UFC_SRC_RDY_N_Buffer_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(UFC_SRC_RDY_N_Buffer_reg_0),
        .Q(UFC_SRC_RDY_N_Buffer),
        .S(RESET));
endmodule

module aurora_rx_4l_64b_UFC_STORAGE_COUNT_CONTROL
   (\storage_count_r_reg[1]_0 ,
    Q,
    \storage_count_r_reg[0]_0 ,
    ufc_output_select_c0_in,
    D,
    \storage_count_r_reg[0]_1 ,
    \storage_count_r_reg[0]_2 ,
    \storage_count_r_reg[0]_3 ,
    \storage_count_r_reg[0]_4 ,
    \storage_count_r_reg[0]_5 ,
    RESET,
    user_clk,
    \storage_count_r_reg[0]_6 ,
    stage_1_ufc_start_r);
  output \storage_count_r_reg[1]_0 ;
  output [2:0]Q;
  output \storage_count_r_reg[0]_0 ;
  output [0:0]ufc_output_select_c0_in;
  output [1:0]D;
  output \storage_count_r_reg[0]_1 ;
  output [5:0]\storage_count_r_reg[0]_2 ;
  output \storage_count_r_reg[0]_3 ;
  output \storage_count_r_reg[0]_4 ;
  output \storage_count_r_reg[0]_5 ;
  input RESET;
  input user_clk;
  input [2:0]\storage_count_r_reg[0]_6 ;
  input stage_1_ufc_start_r;

  wire [1:0]D;
  wire [2:0]Q;
  wire RESET;
  wire stage_1_ufc_start_r;
  wire [0:2]storage_count_c;
  wire \storage_count_r[0]_i_2_n_0 ;
  wire \storage_count_r[0]_i_4_n_0 ;
  wire \storage_count_r_reg[0]_0 ;
  wire \storage_count_r_reg[0]_1 ;
  wire [5:0]\storage_count_r_reg[0]_2 ;
  wire \storage_count_r_reg[0]_3 ;
  wire \storage_count_r_reg[0]_4 ;
  wire \storage_count_r_reg[0]_5 ;
  wire [2:0]\storage_count_r_reg[0]_6 ;
  wire \storage_count_r_reg[1]_0 ;
  wire [0:0]ufc_output_select_c0_in;
  wire user_clk;

  LUT4 #(
    .INIT(16'hAAAB)) 
    UFC_EOF_N_Buffer_i_1
       (.I0(\storage_count_r_reg[0]_1 ),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\storage_count_r_reg[0]_3 ));
  LUT6 #(
    .INIT(64'hC3C35A69C2C15A69)) 
    \UFC_REM_Buffer[0]_i_1 
       (.I0(\storage_count_r_reg[0]_6 [1]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\storage_count_r_reg[0]_6 [0]),
        .I4(stage_1_ufc_start_r),
        .I5(Q[2]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'h0EF00F0F)) 
    \UFC_REM_Buffer[1]_i_1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(stage_1_ufc_start_r),
        .I4(\storage_count_r_reg[0]_6 [0]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT3 #(
    .INIT(8'h01)) 
    UFC_SRC_RDY_N_Buffer_i_1
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\storage_count_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \UFC_STORAGE_SELECT_Buffer[0]_i_2 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(ufc_output_select_c0_in));
  LUT2 #(
    .INIT(4'h7)) 
    \UFC_STORAGE_SELECT_Buffer[10]_i_1 
       (.I0(\storage_count_r_reg[0]_1 ),
        .I1(Q[1]),
        .O(\storage_count_r_reg[0]_2 [1]));
  LUT2 #(
    .INIT(4'h7)) 
    \UFC_STORAGE_SELECT_Buffer[11]_i_1 
       (.I0(\storage_count_r_reg[0]_1 ),
        .I1(Q[0]),
        .O(\storage_count_r_reg[0]_2 [0]));
  LUT2 #(
    .INIT(4'h6)) 
    \UFC_STORAGE_SELECT_Buffer[1]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\storage_count_r_reg[1]_0 ));
  LUT3 #(
    .INIT(8'h82)) 
    \UFC_STORAGE_SELECT_Buffer[3]_i_1 
       (.I0(\storage_count_r_reg[0]_1 ),
        .I1(Q[2]),
        .I2(Q[1]),
        .O(\storage_count_r_reg[0]_2 [5]));
  LUT2 #(
    .INIT(4'h8)) 
    \UFC_STORAGE_SELECT_Buffer[4]_i_1 
       (.I0(Q[1]),
        .I1(\storage_count_r_reg[0]_1 ),
        .O(\storage_count_r_reg[0]_2 [4]));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \UFC_STORAGE_SELECT_Buffer[6]_i_1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\storage_count_r_reg[0]_4 ));
  LUT3 #(
    .INIT(8'h9F)) 
    \UFC_STORAGE_SELECT_Buffer[7]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\storage_count_r_reg[0]_1 ),
        .O(\storage_count_r_reg[0]_2 [3]));
  LUT2 #(
    .INIT(4'h8)) 
    \UFC_STORAGE_SELECT_Buffer[8]_i_1 
       (.I0(Q[0]),
        .I1(\storage_count_r_reg[0]_1 ),
        .O(\storage_count_r_reg[0]_2 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \UFC_STORAGE_SELECT_Buffer[9]_i_1 
       (.I0(Q[2]),
        .O(\storage_count_r_reg[0]_5 ));
  LUT5 #(
    .INIT(32'hBEC3AA00)) 
    \storage_count_r[0]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(\storage_count_r[0]_i_2_n_0 ),
        .I2(Q[2]),
        .I3(\storage_count_r_reg[0]_6 [2]),
        .I4(\storage_count_r_reg[0]_1 ),
        .O(storage_count_c[0]));
  LUT4 #(
    .INIT(16'hEA80)) 
    \storage_count_r[0]_i_2 
       (.I0(Q[1]),
        .I1(\storage_count_r_reg[0]_6 [0]),
        .I2(Q[0]),
        .I3(\storage_count_r_reg[0]_6 [1]),
        .O(\storage_count_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000FEE8)) 
    \storage_count_r[0]_i_3 
       (.I0(\storage_count_r[0]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(\storage_count_r_reg[0]_6 [2]),
        .I3(\storage_count_r[0]_i_4_n_0 ),
        .I4(stage_1_ufc_start_r),
        .O(\storage_count_r_reg[0]_1 ));
  LUT4 #(
    .INIT(16'h9FF6)) 
    \storage_count_r[0]_i_4 
       (.I0(Q[1]),
        .I1(\storage_count_r_reg[0]_6 [1]),
        .I2(Q[0]),
        .I3(\storage_count_r_reg[0]_6 [0]),
        .O(\storage_count_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hCBBCBBCC88888888)) 
    \storage_count_r[1]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(\storage_count_r_reg[0]_6 [1]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\storage_count_r_reg[0]_6 [0]),
        .I5(\storage_count_r_reg[0]_1 ),
        .O(storage_count_c[1]));
  LUT4 #(
    .INIT(16'hBC88)) 
    \storage_count_r[2]_i_1 
       (.I0(stage_1_ufc_start_r),
        .I1(\storage_count_r_reg[0]_6 [0]),
        .I2(Q[0]),
        .I3(\storage_count_r_reg[0]_1 ),
        .O(storage_count_c[2]));
  FDRE \storage_count_r_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(storage_count_c[0]),
        .Q(Q[2]),
        .R(RESET));
  FDRE \storage_count_r_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(storage_count_c[1]),
        .Q(Q[1]),
        .R(RESET));
  FDRE \storage_count_r_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(storage_count_c[2]),
        .Q(Q[0]),
        .R(RESET));
endmodule

module aurora_rx_4l_64b_UFC_STORAGE_MUX
   (MUXED_DATA_Buffer,
    UFC_STORAGE_SELECT_Buffer,
    \MUXED_DATA_Buffer_reg[0]_0 ,
    user_clk,
    \MUXED_DATA_Buffer_reg[1]_0 ,
    \MUXED_DATA_Buffer_reg[2]_0 ,
    \MUXED_DATA_Buffer_reg[3]_0 ,
    \MUXED_DATA_Buffer_reg[4]_0 ,
    \MUXED_DATA_Buffer_reg[5]_0 ,
    \MUXED_DATA_Buffer_reg[6]_0 ,
    \MUXED_DATA_Buffer_reg[7]_0 ,
    \MUXED_DATA_Buffer_reg[8]_0 ,
    \MUXED_DATA_Buffer_reg[9]_0 ,
    \MUXED_DATA_Buffer_reg[10]_0 ,
    \MUXED_DATA_Buffer_reg[11]_0 ,
    \MUXED_DATA_Buffer_reg[12]_0 ,
    \MUXED_DATA_Buffer_reg[13]_0 ,
    \MUXED_DATA_Buffer_reg[14]_0 ,
    \MUXED_DATA_Buffer_reg[15]_0 ,
    \MUXED_DATA_Buffer_reg[16]_0 ,
    \MUXED_DATA_Buffer_reg[17]_0 ,
    \MUXED_DATA_Buffer_reg[18]_0 ,
    \MUXED_DATA_Buffer_reg[19]_0 ,
    \MUXED_DATA_Buffer_reg[20]_0 ,
    \MUXED_DATA_Buffer_reg[21]_0 ,
    \MUXED_DATA_Buffer_reg[22]_0 ,
    \MUXED_DATA_Buffer_reg[23]_0 ,
    \MUXED_DATA_Buffer_reg[24]_0 ,
    \MUXED_DATA_Buffer_reg[25]_0 ,
    \MUXED_DATA_Buffer_reg[26]_0 ,
    \MUXED_DATA_Buffer_reg[27]_0 ,
    \MUXED_DATA_Buffer_reg[28]_0 ,
    \MUXED_DATA_Buffer_reg[29]_0 ,
    \MUXED_DATA_Buffer_reg[30]_0 ,
    \MUXED_DATA_Buffer_reg[31]_0 ,
    \MUXED_DATA_Buffer_reg[32]_0 ,
    \MUXED_DATA_Buffer_reg[33]_0 ,
    \MUXED_DATA_Buffer_reg[34]_0 ,
    \MUXED_DATA_Buffer_reg[35]_0 ,
    \MUXED_DATA_Buffer_reg[36]_0 ,
    \MUXED_DATA_Buffer_reg[37]_0 ,
    \MUXED_DATA_Buffer_reg[38]_0 ,
    \MUXED_DATA_Buffer_reg[39]_0 ,
    \MUXED_DATA_Buffer_reg[40]_0 ,
    \MUXED_DATA_Buffer_reg[41]_0 ,
    \MUXED_DATA_Buffer_reg[42]_0 ,
    \MUXED_DATA_Buffer_reg[43]_0 ,
    \MUXED_DATA_Buffer_reg[44]_0 ,
    \MUXED_DATA_Buffer_reg[45]_0 ,
    \MUXED_DATA_Buffer_reg[46]_0 ,
    \MUXED_DATA_Buffer_reg[47]_0 ,
    \MUXED_DATA_Buffer_reg[48]_0 ,
    \MUXED_DATA_Buffer_reg[49]_0 ,
    \MUXED_DATA_Buffer_reg[50]_0 ,
    \MUXED_DATA_Buffer_reg[51]_0 ,
    \MUXED_DATA_Buffer_reg[52]_0 ,
    \MUXED_DATA_Buffer_reg[53]_0 ,
    \MUXED_DATA_Buffer_reg[54]_0 ,
    \MUXED_DATA_Buffer_reg[55]_0 ,
    \MUXED_DATA_Buffer_reg[56]_0 ,
    \MUXED_DATA_Buffer_reg[57]_0 ,
    \MUXED_DATA_Buffer_reg[58]_0 ,
    \MUXED_DATA_Buffer_reg[59]_0 ,
    \MUXED_DATA_Buffer_reg[60]_0 ,
    \MUXED_DATA_Buffer_reg[61]_0 ,
    \MUXED_DATA_Buffer_reg[62]_0 ,
    \MUXED_DATA_Buffer_reg[63]_0 );
  output [0:63]MUXED_DATA_Buffer;
  input [3:0]UFC_STORAGE_SELECT_Buffer;
  input \MUXED_DATA_Buffer_reg[0]_0 ;
  input user_clk;
  input \MUXED_DATA_Buffer_reg[1]_0 ;
  input \MUXED_DATA_Buffer_reg[2]_0 ;
  input \MUXED_DATA_Buffer_reg[3]_0 ;
  input \MUXED_DATA_Buffer_reg[4]_0 ;
  input \MUXED_DATA_Buffer_reg[5]_0 ;
  input \MUXED_DATA_Buffer_reg[6]_0 ;
  input \MUXED_DATA_Buffer_reg[7]_0 ;
  input \MUXED_DATA_Buffer_reg[8]_0 ;
  input \MUXED_DATA_Buffer_reg[9]_0 ;
  input \MUXED_DATA_Buffer_reg[10]_0 ;
  input \MUXED_DATA_Buffer_reg[11]_0 ;
  input \MUXED_DATA_Buffer_reg[12]_0 ;
  input \MUXED_DATA_Buffer_reg[13]_0 ;
  input \MUXED_DATA_Buffer_reg[14]_0 ;
  input \MUXED_DATA_Buffer_reg[15]_0 ;
  input \MUXED_DATA_Buffer_reg[16]_0 ;
  input \MUXED_DATA_Buffer_reg[17]_0 ;
  input \MUXED_DATA_Buffer_reg[18]_0 ;
  input \MUXED_DATA_Buffer_reg[19]_0 ;
  input \MUXED_DATA_Buffer_reg[20]_0 ;
  input \MUXED_DATA_Buffer_reg[21]_0 ;
  input \MUXED_DATA_Buffer_reg[22]_0 ;
  input \MUXED_DATA_Buffer_reg[23]_0 ;
  input \MUXED_DATA_Buffer_reg[24]_0 ;
  input \MUXED_DATA_Buffer_reg[25]_0 ;
  input \MUXED_DATA_Buffer_reg[26]_0 ;
  input \MUXED_DATA_Buffer_reg[27]_0 ;
  input \MUXED_DATA_Buffer_reg[28]_0 ;
  input \MUXED_DATA_Buffer_reg[29]_0 ;
  input \MUXED_DATA_Buffer_reg[30]_0 ;
  input \MUXED_DATA_Buffer_reg[31]_0 ;
  input \MUXED_DATA_Buffer_reg[32]_0 ;
  input \MUXED_DATA_Buffer_reg[33]_0 ;
  input \MUXED_DATA_Buffer_reg[34]_0 ;
  input \MUXED_DATA_Buffer_reg[35]_0 ;
  input \MUXED_DATA_Buffer_reg[36]_0 ;
  input \MUXED_DATA_Buffer_reg[37]_0 ;
  input \MUXED_DATA_Buffer_reg[38]_0 ;
  input \MUXED_DATA_Buffer_reg[39]_0 ;
  input \MUXED_DATA_Buffer_reg[40]_0 ;
  input \MUXED_DATA_Buffer_reg[41]_0 ;
  input \MUXED_DATA_Buffer_reg[42]_0 ;
  input \MUXED_DATA_Buffer_reg[43]_0 ;
  input \MUXED_DATA_Buffer_reg[44]_0 ;
  input \MUXED_DATA_Buffer_reg[45]_0 ;
  input \MUXED_DATA_Buffer_reg[46]_0 ;
  input \MUXED_DATA_Buffer_reg[47]_0 ;
  input \MUXED_DATA_Buffer_reg[48]_0 ;
  input \MUXED_DATA_Buffer_reg[49]_0 ;
  input \MUXED_DATA_Buffer_reg[50]_0 ;
  input \MUXED_DATA_Buffer_reg[51]_0 ;
  input \MUXED_DATA_Buffer_reg[52]_0 ;
  input \MUXED_DATA_Buffer_reg[53]_0 ;
  input \MUXED_DATA_Buffer_reg[54]_0 ;
  input \MUXED_DATA_Buffer_reg[55]_0 ;
  input \MUXED_DATA_Buffer_reg[56]_0 ;
  input \MUXED_DATA_Buffer_reg[57]_0 ;
  input \MUXED_DATA_Buffer_reg[58]_0 ;
  input \MUXED_DATA_Buffer_reg[59]_0 ;
  input \MUXED_DATA_Buffer_reg[60]_0 ;
  input \MUXED_DATA_Buffer_reg[61]_0 ;
  input \MUXED_DATA_Buffer_reg[62]_0 ;
  input \MUXED_DATA_Buffer_reg[63]_0 ;

  wire [0:63]MUXED_DATA_Buffer;
  wire \MUXED_DATA_Buffer_reg[0]_0 ;
  wire \MUXED_DATA_Buffer_reg[10]_0 ;
  wire \MUXED_DATA_Buffer_reg[11]_0 ;
  wire \MUXED_DATA_Buffer_reg[12]_0 ;
  wire \MUXED_DATA_Buffer_reg[13]_0 ;
  wire \MUXED_DATA_Buffer_reg[14]_0 ;
  wire \MUXED_DATA_Buffer_reg[15]_0 ;
  wire \MUXED_DATA_Buffer_reg[16]_0 ;
  wire \MUXED_DATA_Buffer_reg[17]_0 ;
  wire \MUXED_DATA_Buffer_reg[18]_0 ;
  wire \MUXED_DATA_Buffer_reg[19]_0 ;
  wire \MUXED_DATA_Buffer_reg[1]_0 ;
  wire \MUXED_DATA_Buffer_reg[20]_0 ;
  wire \MUXED_DATA_Buffer_reg[21]_0 ;
  wire \MUXED_DATA_Buffer_reg[22]_0 ;
  wire \MUXED_DATA_Buffer_reg[23]_0 ;
  wire \MUXED_DATA_Buffer_reg[24]_0 ;
  wire \MUXED_DATA_Buffer_reg[25]_0 ;
  wire \MUXED_DATA_Buffer_reg[26]_0 ;
  wire \MUXED_DATA_Buffer_reg[27]_0 ;
  wire \MUXED_DATA_Buffer_reg[28]_0 ;
  wire \MUXED_DATA_Buffer_reg[29]_0 ;
  wire \MUXED_DATA_Buffer_reg[2]_0 ;
  wire \MUXED_DATA_Buffer_reg[30]_0 ;
  wire \MUXED_DATA_Buffer_reg[31]_0 ;
  wire \MUXED_DATA_Buffer_reg[32]_0 ;
  wire \MUXED_DATA_Buffer_reg[33]_0 ;
  wire \MUXED_DATA_Buffer_reg[34]_0 ;
  wire \MUXED_DATA_Buffer_reg[35]_0 ;
  wire \MUXED_DATA_Buffer_reg[36]_0 ;
  wire \MUXED_DATA_Buffer_reg[37]_0 ;
  wire \MUXED_DATA_Buffer_reg[38]_0 ;
  wire \MUXED_DATA_Buffer_reg[39]_0 ;
  wire \MUXED_DATA_Buffer_reg[3]_0 ;
  wire \MUXED_DATA_Buffer_reg[40]_0 ;
  wire \MUXED_DATA_Buffer_reg[41]_0 ;
  wire \MUXED_DATA_Buffer_reg[42]_0 ;
  wire \MUXED_DATA_Buffer_reg[43]_0 ;
  wire \MUXED_DATA_Buffer_reg[44]_0 ;
  wire \MUXED_DATA_Buffer_reg[45]_0 ;
  wire \MUXED_DATA_Buffer_reg[46]_0 ;
  wire \MUXED_DATA_Buffer_reg[47]_0 ;
  wire \MUXED_DATA_Buffer_reg[48]_0 ;
  wire \MUXED_DATA_Buffer_reg[49]_0 ;
  wire \MUXED_DATA_Buffer_reg[4]_0 ;
  wire \MUXED_DATA_Buffer_reg[50]_0 ;
  wire \MUXED_DATA_Buffer_reg[51]_0 ;
  wire \MUXED_DATA_Buffer_reg[52]_0 ;
  wire \MUXED_DATA_Buffer_reg[53]_0 ;
  wire \MUXED_DATA_Buffer_reg[54]_0 ;
  wire \MUXED_DATA_Buffer_reg[55]_0 ;
  wire \MUXED_DATA_Buffer_reg[56]_0 ;
  wire \MUXED_DATA_Buffer_reg[57]_0 ;
  wire \MUXED_DATA_Buffer_reg[58]_0 ;
  wire \MUXED_DATA_Buffer_reg[59]_0 ;
  wire \MUXED_DATA_Buffer_reg[5]_0 ;
  wire \MUXED_DATA_Buffer_reg[60]_0 ;
  wire \MUXED_DATA_Buffer_reg[61]_0 ;
  wire \MUXED_DATA_Buffer_reg[62]_0 ;
  wire \MUXED_DATA_Buffer_reg[63]_0 ;
  wire \MUXED_DATA_Buffer_reg[6]_0 ;
  wire \MUXED_DATA_Buffer_reg[7]_0 ;
  wire \MUXED_DATA_Buffer_reg[8]_0 ;
  wire \MUXED_DATA_Buffer_reg[9]_0 ;
  wire [3:0]UFC_STORAGE_SELECT_Buffer;
  wire user_clk;

  FDRE \MUXED_DATA_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[0]_0 ),
        .Q(MUXED_DATA_Buffer[0]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[10]_0 ),
        .Q(MUXED_DATA_Buffer[10]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[11]_0 ),
        .Q(MUXED_DATA_Buffer[11]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[12]_0 ),
        .Q(MUXED_DATA_Buffer[12]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[13]_0 ),
        .Q(MUXED_DATA_Buffer[13]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[14]_0 ),
        .Q(MUXED_DATA_Buffer[14]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[15]_0 ),
        .Q(MUXED_DATA_Buffer[15]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[16]_0 ),
        .Q(MUXED_DATA_Buffer[16]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[17]_0 ),
        .Q(MUXED_DATA_Buffer[17]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[18]_0 ),
        .Q(MUXED_DATA_Buffer[18]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[19]_0 ),
        .Q(MUXED_DATA_Buffer[19]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[1]_0 ),
        .Q(MUXED_DATA_Buffer[1]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[20]_0 ),
        .Q(MUXED_DATA_Buffer[20]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[21]_0 ),
        .Q(MUXED_DATA_Buffer[21]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[22]_0 ),
        .Q(MUXED_DATA_Buffer[22]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[23]_0 ),
        .Q(MUXED_DATA_Buffer[23]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[24]_0 ),
        .Q(MUXED_DATA_Buffer[24]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[25]_0 ),
        .Q(MUXED_DATA_Buffer[25]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[26]_0 ),
        .Q(MUXED_DATA_Buffer[26]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[27]_0 ),
        .Q(MUXED_DATA_Buffer[27]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[28]_0 ),
        .Q(MUXED_DATA_Buffer[28]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[29]_0 ),
        .Q(MUXED_DATA_Buffer[29]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[2]_0 ),
        .Q(MUXED_DATA_Buffer[2]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[30]_0 ),
        .Q(MUXED_DATA_Buffer[30]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[31]_0 ),
        .Q(MUXED_DATA_Buffer[31]),
        .R(UFC_STORAGE_SELECT_Buffer[2]));
  FDRE \MUXED_DATA_Buffer_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[32]_0 ),
        .Q(MUXED_DATA_Buffer[32]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[33]_0 ),
        .Q(MUXED_DATA_Buffer[33]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[34]_0 ),
        .Q(MUXED_DATA_Buffer[34]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[35]_0 ),
        .Q(MUXED_DATA_Buffer[35]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[36]_0 ),
        .Q(MUXED_DATA_Buffer[36]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[37]_0 ),
        .Q(MUXED_DATA_Buffer[37]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[38]_0 ),
        .Q(MUXED_DATA_Buffer[38]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[39]_0 ),
        .Q(MUXED_DATA_Buffer[39]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[3]_0 ),
        .Q(MUXED_DATA_Buffer[3]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[40]_0 ),
        .Q(MUXED_DATA_Buffer[40]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[41]_0 ),
        .Q(MUXED_DATA_Buffer[41]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[42]_0 ),
        .Q(MUXED_DATA_Buffer[42]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[43]_0 ),
        .Q(MUXED_DATA_Buffer[43]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[44]_0 ),
        .Q(MUXED_DATA_Buffer[44]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[45]_0 ),
        .Q(MUXED_DATA_Buffer[45]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[46]_0 ),
        .Q(MUXED_DATA_Buffer[46]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[47]_0 ),
        .Q(MUXED_DATA_Buffer[47]),
        .R(UFC_STORAGE_SELECT_Buffer[1]));
  FDRE \MUXED_DATA_Buffer_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[48]_0 ),
        .Q(MUXED_DATA_Buffer[48]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[49]_0 ),
        .Q(MUXED_DATA_Buffer[49]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[4]_0 ),
        .Q(MUXED_DATA_Buffer[4]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[50]_0 ),
        .Q(MUXED_DATA_Buffer[50]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[51]_0 ),
        .Q(MUXED_DATA_Buffer[51]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[52]_0 ),
        .Q(MUXED_DATA_Buffer[52]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[53]_0 ),
        .Q(MUXED_DATA_Buffer[53]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[54]_0 ),
        .Q(MUXED_DATA_Buffer[54]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[55]_0 ),
        .Q(MUXED_DATA_Buffer[55]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[56]_0 ),
        .Q(MUXED_DATA_Buffer[56]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[57]_0 ),
        .Q(MUXED_DATA_Buffer[57]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[58]_0 ),
        .Q(MUXED_DATA_Buffer[58]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[59]_0 ),
        .Q(MUXED_DATA_Buffer[59]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[5]_0 ),
        .Q(MUXED_DATA_Buffer[5]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[60]_0 ),
        .Q(MUXED_DATA_Buffer[60]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[61]_0 ),
        .Q(MUXED_DATA_Buffer[61]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[62]_0 ),
        .Q(MUXED_DATA_Buffer[62]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[63]_0 ),
        .Q(MUXED_DATA_Buffer[63]),
        .R(UFC_STORAGE_SELECT_Buffer[0]));
  FDRE \MUXED_DATA_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[6]_0 ),
        .Q(MUXED_DATA_Buffer[6]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[7]_0 ),
        .Q(MUXED_DATA_Buffer[7]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[8]_0 ),
        .Q(MUXED_DATA_Buffer[8]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
  FDRE \MUXED_DATA_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\MUXED_DATA_Buffer_reg[9]_0 ),
        .Q(MUXED_DATA_Buffer[9]),
        .R(UFC_STORAGE_SELECT_Buffer[3]));
endmodule

module aurora_rx_4l_64b_UFC_STORAGE_SWITCH_CONTROL
   (UFC_STORAGE_SELECT_Buffer,
    D,
    user_clk,
    ufc_output_select_c0_in,
    \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ,
    \UFC_STORAGE_SELECT_Buffer_reg[6]_0 ,
    \UFC_STORAGE_SELECT_Buffer_reg[9]_0 ,
    \UFC_STORAGE_SELECT_Buffer_reg[9]_1 );
  output [9:0]UFC_STORAGE_SELECT_Buffer;
  input [5:0]D;
  input user_clk;
  input [0:0]ufc_output_select_c0_in;
  input \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
  input \UFC_STORAGE_SELECT_Buffer_reg[6]_0 ;
  input \UFC_STORAGE_SELECT_Buffer_reg[9]_0 ;
  input \UFC_STORAGE_SELECT_Buffer_reg[9]_1 ;

  wire [5:0]D;
  wire [9:0]UFC_STORAGE_SELECT_Buffer;
  wire \UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[1]_0 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[6]_0 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[9]_0 ;
  wire \UFC_STORAGE_SELECT_Buffer_reg[9]_1 ;
  wire [0:0]ufc_output_select_c0_in;
  wire user_clk;

  LUT1 #(
    .INIT(2'h1)) 
    \UFC_STORAGE_SELECT_Buffer[0]_i_1 
       (.I0(\UFC_STORAGE_SELECT_Buffer_reg[9]_1 ),
        .O(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ufc_output_select_c0_in),
        .Q(UFC_STORAGE_SELECT_Buffer[9]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(UFC_STORAGE_SELECT_Buffer[1]),
        .R(1'b0));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(UFC_STORAGE_SELECT_Buffer[0]),
        .R(1'b0));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_STORAGE_SELECT_Buffer_reg[1]_0 ),
        .Q(UFC_STORAGE_SELECT_Buffer[8]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[5]),
        .Q(UFC_STORAGE_SELECT_Buffer[7]),
        .R(1'b0));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[4]),
        .Q(UFC_STORAGE_SELECT_Buffer[6]),
        .R(1'b0));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_STORAGE_SELECT_Buffer_reg[6]_0 ),
        .Q(UFC_STORAGE_SELECT_Buffer[5]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(UFC_STORAGE_SELECT_Buffer[4]),
        .R(1'b0));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(UFC_STORAGE_SELECT_Buffer[3]),
        .R(1'b0));
  FDRE \UFC_STORAGE_SELECT_Buffer_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\UFC_STORAGE_SELECT_Buffer_reg[9]_0 ),
        .Q(UFC_STORAGE_SELECT_Buffer[2]),
        .R(\UFC_STORAGE_SELECT_Buffer[0]_i_1_n_0 ));
endmodule

module aurora_rx_4l_64b_VALID_DATA_COUNTER
   (\COUNT_Buffer_reg[0]_0 ,
    Q,
    RESET,
    user_clk);
  output [2:0]\COUNT_Buffer_reg[0]_0 ;
  input [3:0]Q;
  input RESET;
  input user_clk;

  wire [2:0]\COUNT_Buffer_reg[0]_0 ;
  wire [3:0]Q;
  wire RESET;
  wire [2:0]plusOp;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \COUNT_Buffer[0]_i_1 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[3]),
        .O(plusOp[2]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'h7EE8)) 
    \COUNT_Buffer[1]_i_1 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .O(plusOp[1]));
  LUT4 #(
    .INIT(16'h6996)) 
    \COUNT_Buffer[2]_i_1 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(plusOp[0]));
  FDRE \COUNT_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(plusOp[2]),
        .Q(\COUNT_Buffer_reg[0]_0 [2]),
        .R(RESET));
  FDRE \COUNT_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(plusOp[1]),
        .Q(\COUNT_Buffer_reg[0]_0 [1]),
        .R(RESET));
  FDRE \COUNT_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(plusOp[0]),
        .Q(\COUNT_Buffer_reg[0]_0 [0]),
        .R(RESET));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_VALID_DATA_COUNTER" *) 
module aurora_rx_4l_64b_VALID_DATA_COUNTER_5
   (D,
    Q,
    stage_2_start_with_data_r,
    stage_3_end_storage_r,
    \storage_count_r_reg[1] ,
    RESET,
    \COUNT_Buffer_reg[0]_0 ,
    user_clk);
  output [0:0]D;
  output [2:0]Q;
  input stage_2_start_with_data_r;
  input stage_3_end_storage_r;
  input [1:0]\storage_count_r_reg[1] ;
  input RESET;
  input [2:0]\COUNT_Buffer_reg[0]_0 ;
  input user_clk;

  wire [2:0]\COUNT_Buffer_reg[0]_0 ;
  wire [0:0]D;
  wire [2:0]Q;
  wire RESET;
  wire stage_2_start_with_data_r;
  wire stage_3_end_storage_r;
  wire [1:0]\storage_count_r_reg[1] ;
  wire user_clk;

  FDRE \COUNT_Buffer_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\COUNT_Buffer_reg[0]_0 [2]),
        .Q(Q[2]),
        .R(RESET));
  FDRE \COUNT_Buffer_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\COUNT_Buffer_reg[0]_0 [1]),
        .Q(Q[1]),
        .R(RESET));
  FDRE \COUNT_Buffer_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\COUNT_Buffer_reg[0]_0 [0]),
        .Q(Q[0]),
        .R(RESET));
  LUT6 #(
    .INIT(64'hFEEE0111EFFF1000)) 
    \storage_count_r[1]_i_1__0 
       (.I0(stage_2_start_with_data_r),
        .I1(stage_3_end_storage_r),
        .I2(Q[0]),
        .I3(\storage_count_r_reg[1] [0]),
        .I4(Q[1]),
        .I5(\storage_count_r_reg[1] [1]),
        .O(D));
endmodule

module aurora_rx_4l_64b_cdc_sync
   (out,
    HPCNT_RESET,
    GT_RESET,
    init_clk_in,
    \hotplug_count_synth.count_for_reset_r_reg[0] );
  output out;
  output HPCNT_RESET;
  input GT_RESET;
  input init_clk_in;
  input \hotplug_count_synth.count_for_reset_r_reg[0] ;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire HPCNT_RESET;
  wire \hotplug_count_synth.count_for_reset_r_reg[0] ;
  wire init_clk_in;

  assign \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int  = GT_RESET;
  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_2__2 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .I1(\hotplug_count_synth.count_for_reset_r_reg[0] ),
        .O(HPCNT_RESET));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync_0
   (out,
    RX_SYSTEM_RESET,
    init_clk_in);
  output out;
  input RX_SYSTEM_RESET;
  input init_clk_in;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;

  assign \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int  = RX_SYSTEM_RESET;
  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync_1
   (out,
    RX_SYSTEM_RESET,
    user_clk);
  output out;
  input RX_SYSTEM_RESET;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire user_clk;

  assign \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int  = RX_SYSTEM_RESET;
  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync_23
   (E,
    \FSM_sequential_rx_state_reg[1] ,
    in0,
    init_clk_in,
    reset_time_out_reg,
    Q,
    \FSM_sequential_rx_state_reg[0] ,
    reset_time_out_reg_0,
    \FSM_sequential_rx_state_reg[0]_0 ,
    \FSM_sequential_rx_state_reg[0]_1 ,
    \FSM_sequential_rx_state_reg[0]_2 ,
    \FSM_sequential_rx_state_reg[0]_3 ,
    \FSM_sequential_rx_state_reg[0]_4 ,
    rxresetdone_s3,
    reset_time_out_reg_1);
  output [0:0]E;
  output \FSM_sequential_rx_state_reg[1] ;
  input in0;
  input init_clk_in;
  input reset_time_out_reg;
  input [3:0]Q;
  input \FSM_sequential_rx_state_reg[0] ;
  input reset_time_out_reg_0;
  input \FSM_sequential_rx_state_reg[0]_0 ;
  input \FSM_sequential_rx_state_reg[0]_1 ;
  input \FSM_sequential_rx_state_reg[0]_2 ;
  input \FSM_sequential_rx_state_reg[0]_3 ;
  input \FSM_sequential_rx_state_reg[0]_4 ;
  input rxresetdone_s3;
  input reset_time_out_reg_1;

  wire [0:0]E;
  wire \FSM_sequential_rx_state[3]_i_4_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_7_n_0 ;
  wire \FSM_sequential_rx_state_reg[0] ;
  wire \FSM_sequential_rx_state_reg[0]_0 ;
  wire \FSM_sequential_rx_state_reg[0]_1 ;
  wire \FSM_sequential_rx_state_reg[0]_2 ;
  wire \FSM_sequential_rx_state_reg[0]_3 ;
  wire \FSM_sequential_rx_state_reg[0]_4 ;
  wire \FSM_sequential_rx_state_reg[1] ;
  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire [3:0]Q;
  wire init_clk_in;
  wire reset_time_out_i_2_n_0;
  wire reset_time_out_i_3_n_0;
  wire reset_time_out_i_4_n_0;
  wire reset_time_out_i_5_n_0;
  wire reset_time_out_reg;
  wire reset_time_out_reg_0;
  wire reset_time_out_reg_1;
  wire rxresetdone_s3;

  assign \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int  = in0;
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_sequential_rx_state[3]_i_1 
       (.I0(\FSM_sequential_rx_state_reg[0] ),
        .I1(\FSM_sequential_rx_state[3]_i_4_n_0 ),
        .I2(reset_time_out_reg_0),
        .I3(\FSM_sequential_rx_state_reg[0]_0 ),
        .I4(\FSM_sequential_rx_state[3]_i_7_n_0 ),
        .O(E));
  LUT6 #(
    .INIT(64'h2222000003000000)) 
    \FSM_sequential_rx_state[3]_i_4 
       (.I0(\FSM_sequential_rx_state_reg[0]_1 ),
        .I1(\FSM_sequential_rx_state_reg[0]_2 ),
        .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .I3(\FSM_sequential_rx_state_reg[0]_3 ),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(\FSM_sequential_rx_state[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h88880300)) 
    \FSM_sequential_rx_state[3]_i_7 
       (.I0(reset_time_out_i_3_n_0),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(\FSM_sequential_rx_state_reg[0]_4 ),
        .I4(Q[0]),
        .O(\FSM_sequential_rx_state[3]_i_7_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ));
  LUT6 #(
    .INIT(64'hFEEEFFFFFEEE0000)) 
    reset_time_out_i_1
       (.I0(reset_time_out_reg_0),
        .I1(reset_time_out_i_2_n_0),
        .I2(Q[1]),
        .I3(reset_time_out_i_3_n_0),
        .I4(reset_time_out_i_4_n_0),
        .I5(reset_time_out_reg_1),
        .O(\FSM_sequential_rx_state_reg[1] ));
  LUT5 #(
    .INIT(32'h00000004)) 
    reset_time_out_i_2
       (.I0(Q[1]),
        .I1(\FSM_sequential_rx_state_reg[0]_3 ),
        .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .I3(Q[3]),
        .I4(Q[2]),
        .O(reset_time_out_i_2_n_0));
  LUT4 #(
    .INIT(16'h0B08)) 
    reset_time_out_i_3
       (.I0(rxresetdone_s3),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(reset_time_out_i_3_n_0));
  LUT6 #(
    .INIT(64'h00333333FF00FC88)) 
    reset_time_out_i_4
       (.I0(reset_time_out_reg),
        .I1(Q[2]),
        .I2(reset_time_out_i_5_n_0),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[3]),
        .O(reset_time_out_i_4_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    reset_time_out_i_5
       (.I0(\FSM_sequential_rx_state_reg[0]_3 ),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(reset_time_out_i_5_n_0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync_24
   (init_clk_in);
  input init_clk_in;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync_26
   (out,
    SR,
    init_clk_in);
  output out;
  output [0:0]SR;
  input init_clk_in;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire [0:0]SR;
  wire init_clk_in;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ));
  LUT1 #(
    .INIT(2'h1)) 
    \mmcm_lock_count[9]_i_1 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(SR));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync_31
   (out,
    user_clk);
  output out;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2
   (O,
    \hotplug_count_synth.count_for_reset_r_reg[7] ,
    \hotplug_count_synth.count_for_reset_r_reg[11] ,
    \hotplug_count_synth.count_for_reset_r_reg[15] ,
    \hotplug_count_synth.count_for_reset_r_reg[19] ,
    \hotplug_count_synth.count_for_reset_r_reg[23] ,
    \hotplug_count_synth.count_for_reset_r_reg[25] ,
    rx_cc_extend_r2,
    user_clk,
    init_clk_in,
    \hotplug_count_synth.count_for_reset_r_reg );
  output [3:0]O;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  output [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  input rx_cc_extend_r2;
  input user_clk;
  input init_clk_in;
  input [25:0]\hotplug_count_synth.count_for_reset_r_reg ;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire [3:0]O;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_2__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_3__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_4__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_5__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_6__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_2__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_3__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_4__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_5__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_2__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_3__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_4__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_5__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_2__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_3__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_4__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_5__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_2__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_3__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_2__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_3__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_4__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_5__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_2__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_3__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_4__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_5__2_n_0 ;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_n_3 ;
  wire [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_3 ;
  wire init_clk_in;
  wire rx_cc_extend_r2;
  wire user_clk;
  wire [3:1]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_CO_UNCONNECTED ;
  wire [3:2]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_O_UNCONNECTED ;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_2__1 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_3__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_4__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_5__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_5__2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_6__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_6__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_2__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_3__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_4__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_5__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_5__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_2__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_3__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_4__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_5__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_5__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_2__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_3__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_4__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_5__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_5__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_2__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_3__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_2__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_3__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_4__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_5__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_5__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_2__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_3__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_4__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_5__2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_5__2_n_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2 
       (.CI(1'b0),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[0]_i_2__1_n_0 }),
        .O(O),
        .S({\hotplug_count_synth.count_for_reset_r[0]_i_3__2_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_4__2_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_5__2_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_6__2_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[15] ),
        .S({\hotplug_count_synth.count_for_reset_r[12]_i_2__2_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_3__2_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_4__2_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_5__2_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__2_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[19] ),
        .S({\hotplug_count_synth.count_for_reset_r[16]_i_2__2_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_3__2_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_4__2_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_5__2_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__2_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[23] ),
        .S({\hotplug_count_synth.count_for_reset_r[20]_i_2__2_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_3__2_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_4__2_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_5__2_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__2_n_0 ),
        .CO({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_CO_UNCONNECTED [3:1],\hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__2_O_UNCONNECTED [3:2],\hotplug_count_synth.count_for_reset_r_reg[25] }),
        .S({1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[24]_i_2__2_n_0 ,\hotplug_count_synth.count_for_reset_r[24]_i_3__2_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__2_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[7] ),
        .S({\hotplug_count_synth.count_for_reset_r[4]_i_2__2_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_3__2_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_4__2_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_5__2_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__2_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[11] ),
        .S({\hotplug_count_synth.count_for_reset_r[8]_i_2__2_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_3__2_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_4__2_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_5__2_n_0 }));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_10
   (O,
    \hotplug_count_synth.count_for_reset_r_reg[7] ,
    \hotplug_count_synth.count_for_reset_r_reg[11] ,
    \hotplug_count_synth.count_for_reset_r_reg[15] ,
    \hotplug_count_synth.count_for_reset_r_reg[19] ,
    \hotplug_count_synth.count_for_reset_r_reg[23] ,
    \hotplug_count_synth.count_for_reset_r_reg[25] ,
    rx_cc_extend_r2,
    user_clk,
    init_clk_in,
    \hotplug_count_synth.count_for_reset_r_reg );
  output [3:0]O;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  output [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  input rx_cc_extend_r2;
  input user_clk;
  input init_clk_in;
  input [25:0]\hotplug_count_synth.count_for_reset_r_reg ;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire [3:0]O;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_2__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_3__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_4__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_5__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_6__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_2__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_3__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_4__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_5__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_2__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_3__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_4__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_5__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_2__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_3__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_4__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_5__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_2__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_3__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_2__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_3__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_4__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_5__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_2__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_3__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_4__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_5__1_n_0 ;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_n_3 ;
  wire [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_3 ;
  wire init_clk_in;
  wire rx_cc_extend_r2;
  wire user_clk;
  wire [3:1]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_CO_UNCONNECTED ;
  wire [3:2]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_O_UNCONNECTED ;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_2__0 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_3__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_4__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_5__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_5__1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_6__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_6__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_2__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_3__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_4__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_5__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_5__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_2__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_3__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_4__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_5__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_5__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_2__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_3__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_4__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_5__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_5__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_2__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_3__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_2__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_3__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_4__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_5__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_5__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_2__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_3__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_4__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_5__1 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_5__1_n_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1 
       (.CI(1'b0),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[0]_i_2__0_n_0 }),
        .O(O),
        .S({\hotplug_count_synth.count_for_reset_r[0]_i_3__1_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_4__1_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_5__1_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_6__1_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[15] ),
        .S({\hotplug_count_synth.count_for_reset_r[12]_i_2__1_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_3__1_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_4__1_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_5__1_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[19] ),
        .S({\hotplug_count_synth.count_for_reset_r[16]_i_2__1_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_3__1_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_4__1_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_5__1_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[23] ),
        .S({\hotplug_count_synth.count_for_reset_r[20]_i_2__1_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_3__1_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_4__1_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_5__1_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__1_n_0 ),
        .CO({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_CO_UNCONNECTED [3:1],\hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__1_O_UNCONNECTED [3:2],\hotplug_count_synth.count_for_reset_r_reg[25] }),
        .S({1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[24]_i_2__1_n_0 ,\hotplug_count_synth.count_for_reset_r[24]_i_3__1_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[7] ),
        .S({\hotplug_count_synth.count_for_reset_r[4]_i_2__1_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_3__1_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_4__1_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_5__1_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[11] ),
        .S({\hotplug_count_synth.count_for_reset_r[8]_i_2__1_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_3__1_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_4__1_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_5__1_n_0 }));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_15
   (O,
    \hotplug_count_synth.count_for_reset_r_reg[7] ,
    \hotplug_count_synth.count_for_reset_r_reg[11] ,
    \hotplug_count_synth.count_for_reset_r_reg[15] ,
    \hotplug_count_synth.count_for_reset_r_reg[19] ,
    \hotplug_count_synth.count_for_reset_r_reg[23] ,
    \hotplug_count_synth.count_for_reset_r_reg[25] ,
    rx_cc_extend_r2,
    user_clk,
    init_clk_in,
    \hotplug_count_synth.count_for_reset_r_reg );
  output [3:0]O;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  output [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  input rx_cc_extend_r2;
  input user_clk;
  input init_clk_in;
  input [25:0]\hotplug_count_synth.count_for_reset_r_reg ;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire [3:0]O;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_3__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_4__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_5__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_6__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_2__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_3__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_4__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_5__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_2__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_3__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_4__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_5__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_2__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_3__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_4__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_5__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_2__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_3__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_2__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_3__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_4__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_5__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_2__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_3__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_4__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_5__0_n_0 ;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_n_3 ;
  wire [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_3 ;
  wire init_clk_in;
  wire rx_cc_extend_r2;
  wire user_clk;
  wire [3:1]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_CO_UNCONNECTED ;
  wire [3:2]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_O_UNCONNECTED ;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_2 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_3__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_4__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_4__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_5__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_5__0_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_6__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_6__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_2__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_3__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_4__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_4__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_5__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_5__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_2__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_3__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_4__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_4__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_5__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_5__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_2__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_3__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_4__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_4__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_5__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_5__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_2__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_3__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_2__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_3__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_4__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_4__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_5__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_5__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_2__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_3__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_4__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_4__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_5__0 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_5__0_n_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0 
       (.CI(1'b0),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[0]_i_2_n_0 }),
        .O(O),
        .S({\hotplug_count_synth.count_for_reset_r[0]_i_3__0_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_4__0_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_5__0_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_6__0_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[15] ),
        .S({\hotplug_count_synth.count_for_reset_r[12]_i_2__0_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_3__0_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_4__0_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_5__0_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[12]_i_1__0_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[19] ),
        .S({\hotplug_count_synth.count_for_reset_r[16]_i_2__0_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_3__0_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_4__0_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_5__0_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[16]_i_1__0_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[23] ),
        .S({\hotplug_count_synth.count_for_reset_r[20]_i_2__0_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_3__0_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_4__0_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_5__0_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[20]_i_1__0_n_0 ),
        .CO({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_CO_UNCONNECTED [3:1],\hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1__0_O_UNCONNECTED [3:2],\hotplug_count_synth.count_for_reset_r_reg[25] }),
        .S({1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[24]_i_2__0_n_0 ,\hotplug_count_synth.count_for_reset_r[24]_i_3__0_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[0]_i_1__0_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[7] ),
        .S({\hotplug_count_synth.count_for_reset_r[4]_i_2__0_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_3__0_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_4__0_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_5__0_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[4]_i_1__0_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[11] ),
        .S({\hotplug_count_synth.count_for_reset_r[8]_i_2__0_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_3__0_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_4__0_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_5__0_n_0 }));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_20
   (O,
    \hotplug_count_synth.count_for_reset_r_reg[7] ,
    \hotplug_count_synth.count_for_reset_r_reg[11] ,
    \hotplug_count_synth.count_for_reset_r_reg[15] ,
    \hotplug_count_synth.count_for_reset_r_reg[19] ,
    \hotplug_count_synth.count_for_reset_r_reg[23] ,
    \hotplug_count_synth.count_for_reset_r_reg[25] ,
    rx_cc_extend_r2,
    user_clk,
    init_clk_in,
    \hotplug_count_synth.count_for_reset_r_reg );
  output [3:0]O;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  output [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  output [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  input rx_cc_extend_r2;
  input user_clk;
  input init_clk_in;
  input [25:0]\hotplug_count_synth.count_for_reset_r_reg ;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire [3:0]O;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[20]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[24]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ;
  wire [25:0]\hotplug_count_synth.count_for_reset_r_reg ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[11] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[15] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[19] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[23] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3 ;
  wire [1:0]\hotplug_count_synth.count_for_reset_r_reg[25] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 ;
  wire [3:0]\hotplug_count_synth.count_for_reset_r_reg[7] ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ;
  wire \hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 ;
  wire init_clk_in;
  wire rx_cc_extend_r2;
  wire user_clk;
  wire [3:1]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED ;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_cc_extend_r2),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_3 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [3]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [2]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_6 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [1]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \hotplug_count_synth.count_for_reset_r[0]_i_7 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [0]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [15]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [14]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [13]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[12]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [12]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [19]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [18]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [17]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[16]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [16]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [23]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [22]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [21]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[20]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [20]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[20]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [25]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[24]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [24]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [7]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [6]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [5]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[4]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [4]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_2 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [11]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_3 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [10]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_4 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [9]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \hotplug_count_synth.count_for_reset_r[8]_i_5 
       (.I0(\hotplug_count_synth.count_for_reset_r_reg [8]),
        .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .O(\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[0]_i_3_n_0 }),
        .O(O),
        .S({\hotplug_count_synth.count_for_reset_r[0]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_5_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_6_n_0 ,\hotplug_count_synth.count_for_reset_r[0]_i_7_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[12]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[15] ),
        .S({\hotplug_count_synth.count_for_reset_r[12]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[12]_i_5_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[16]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[12]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[19] ),
        .S({\hotplug_count_synth.count_for_reset_r[16]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[16]_i_5_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[20]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[16]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[23] ),
        .S({\hotplug_count_synth.count_for_reset_r[20]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[20]_i_5_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[24]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[20]_i_1_n_0 ),
        .CO({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_CO_UNCONNECTED [3:1],\hotplug_count_synth.count_for_reset_r_reg[24]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_hotplug_count_synth.count_for_reset_r_reg[24]_i_1_O_UNCONNECTED [3:2],\hotplug_count_synth.count_for_reset_r_reg[25] }),
        .S({1'b0,1'b0,\hotplug_count_synth.count_for_reset_r[24]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[24]_i_3_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[4]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[0]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[7] ),
        .S({\hotplug_count_synth.count_for_reset_r[4]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[4]_i_5_n_0 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \hotplug_count_synth.count_for_reset_r_reg[8]_i_1 
       (.CI(\hotplug_count_synth.count_for_reset_r_reg[4]_i_1_n_0 ),
        .CO({\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_0 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_1 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_2 ,\hotplug_count_synth.count_for_reset_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\hotplug_count_synth.count_for_reset_r_reg[11] ),
        .S({\hotplug_count_synth.count_for_reset_r[8]_i_2_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_3_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_4_n_0 ,\hotplug_count_synth.count_for_reset_r[8]_i_5_n_0 }));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_21
   (out,
    gtrxreset_i,
    user_clk,
    init_clk_in);
  output out;
  input gtrxreset_i;
  input user_clk;
  input init_clk_in;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire gtrxreset_i;
  wire init_clk_in;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(gtrxreset_i),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_22
   (out,
    fsm_gt_rx_reset_t,
    init_clk_in,
    user_clk);
  output out;
  input fsm_gt_rx_reset_t;
  input init_clk_in;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire fsm_gt_rx_reset_t;
  wire init_clk_in;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(fsm_gt_rx_reset_t),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_25
   (out,
    rxfsm_rxresetdone_r,
    user_clk,
    init_clk_in);
  output out;
  input rxfsm_rxresetdone_r;
  input user_clk;
  input init_clk_in;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire rxfsm_rxresetdone_r;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rxfsm_rxresetdone_r),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_27
   (init_clk_in,
    user_clk);
  input init_clk_in;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire user_clk;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(1'b0),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_28
   (out,
    run_phase_alignment_int,
    init_clk_in,
    user_clk);
  output out;
  input run_phase_alignment_int;
  input init_clk_in;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire run_phase_alignment_int;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(run_phase_alignment_int),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_29
   (out,
    rx_fsm_reset_done_int,
    init_clk_in,
    user_clk);
  output out;
  input rx_fsm_reset_done_int;
  input init_clk_in;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire rx_fsm_reset_done_int;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_fsm_reset_done_int),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_30
   (rxpmaresetdone_i,
    user_clk,
    init_clk_in);
  input rxpmaresetdone_i;
  input user_clk;
  input init_clk_in;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire rxpmaresetdone_i;
  wire user_clk;

  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(rxpmaresetdone_i),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_32
   (out,
    time_out_wait_bypass,
    user_clk,
    init_clk_in);
  output out;
  input time_out_wait_bypass;
  input user_clk;
  input init_clk_in;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire time_out_wait_bypass;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(time_out_wait_bypass),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_36
   (out,
    link_reset_r,
    init_clk_in,
    user_clk);
  output out;
  input link_reset_r;
  input init_clk_in;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire link_reset_r;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(link_reset_r),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_cdc_sync" *) 
module aurora_rx_4l_64b_cdc_sync__parameterized2_37
   (out,
    tx_lock_comb_r,
    init_clk_in,
    user_clk);
  output out;
  input tx_lock_comb_r;
  input init_clk_in;
  input user_clk;

  (* RTL_KEEP = "true" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ;
  (* async_reg = "true" *) (* shift_extract = "no" *) wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ;
  wire init_clk_in;
  wire tx_lock_comb_r;
  wire user_clk;

  assign out = \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.p_level_in_d1_cdc_from_reg 
       (.C(init_clk_in),
        .CE(1'b1),
        .D(tx_lock_comb_r),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from_inst 
       (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_d1_cdc_from ),
        .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.p_level_in_int ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d1_aurora_rx_4l_64b_cdc_to ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d4 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* shift_extract = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d5 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d6 ),
        .R(1'b0));
endmodule

(* EXAMPLE_SIMULATION = "0" *) (* SIM_GTRESET_SPEEDUP = "FALSE" *) 
module aurora_rx_4l_64b_core
   (M_AXI_RX_TDATA,
    M_AXI_RX_TKEEP,
    M_AXI_RX_TVALID,
    M_AXI_RX_TLAST,
    M_AXI_UFC_RX_TDATA,
    M_AXI_UFC_RX_TKEEP,
    M_AXI_UFC_RX_TVALID,
    M_AXI_UFC_RX_TLAST,
    RXP,
    RXN,
    gt_refclk1,
    RX_HARD_ERR,
    SOFT_ERR,
    FRAME_ERR,
    RX_CHANNEL_UP,
    RX_LANE_UP,
    user_clk,
    sync_clk,
    RX_SYSTEM_RESET,
    RX_RESETDONE_OUT,
    LINK_RESET_OUT,
    POWER_DOWN,
    GT_RESET,
    TX_LOCK,
    init_clk_in,
    PLL_NOT_LOCKED,
    drpclk_in,
    DRPADDR_IN,
    DRPDI_IN,
    DRPDO_OUT,
    DRPEN_IN,
    DRPRDY_OUT,
    DRPWE_IN,
    DRPADDR_IN_LANE1,
    DRPDI_IN_LANE1,
    DRPDO_OUT_LANE1,
    DRPEN_IN_LANE1,
    DRPRDY_OUT_LANE1,
    DRPWE_IN_LANE1,
    DRPADDR_IN_LANE2,
    DRPDI_IN_LANE2,
    DRPDO_OUT_LANE2,
    DRPEN_IN_LANE2,
    DRPRDY_OUT_LANE2,
    DRPWE_IN_LANE2,
    DRPADDR_IN_LANE3,
    DRPDI_IN_LANE3,
    DRPDO_OUT_LANE3,
    DRPEN_IN_LANE3,
    DRPRDY_OUT_LANE3,
    DRPWE_IN_LANE3,
    TX_OUT_CLK,
    gt0_qplllock_in,
    gt0_qpllrefclklost_in,
    gt0_qpllreset_out,
    gt1_qplllock_in,
    gt1_qpllrefclklost_in,
    gt1_qpllreset_out,
    gt_qpllclk_quad2_in,
    gt_qpllrefclk_quad2_in,
    gt_qpllclk_quad3_in,
    gt_qpllrefclk_quad3_in,
    gt0_cplllock_out,
    gt0_rxlpmen_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxmonitorout_out,
    gt0_rxmonitorsel_in,
    gt0_rxcdrhold_in,
    gt0_eyescanreset_in,
    gt0_eyescandataerror_out,
    gt0_eyescantrigger_in,
    gt0_rxbyteisaligned_out,
    gt0_rxcommadet_out,
    gt0_rxprbserr_out,
    gt0_rxprbssel_in,
    gt0_rxprbscntreset_in,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    gt0_rxpmaresetdone_out,
    gt0_dmonitorout_out,
    gt0_rxbufreset_in,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    gt0_rx_realign_out,
    gt0_rx_buf_err_out,
    gt0_rxresetdone_out,
    gt0_rxbufstatus_out,
    gt1_cplllock_out,
    gt1_rxlpmen_in,
    gt1_rxcdrovrden_in,
    gt1_rxdfelpmreset_in,
    gt1_rxmonitorout_out,
    gt1_rxmonitorsel_in,
    gt1_rxcdrhold_in,
    gt1_eyescanreset_in,
    gt1_eyescandataerror_out,
    gt1_eyescantrigger_in,
    gt1_rxbyteisaligned_out,
    gt1_rxcommadet_out,
    gt1_rxprbserr_out,
    gt1_rxprbssel_in,
    gt1_rxprbscntreset_in,
    gt1_rxpcsreset_in,
    gt1_rxpmareset_in,
    gt1_rxpmaresetdone_out,
    gt1_dmonitorout_out,
    gt1_rxbufreset_in,
    gt1_rx_disp_err_out,
    gt1_rx_not_in_table_out,
    gt1_rx_realign_out,
    gt1_rx_buf_err_out,
    gt1_rxresetdone_out,
    gt1_rxbufstatus_out,
    gt2_cplllock_out,
    gt2_rxlpmen_in,
    gt2_rxcdrovrden_in,
    gt2_rxdfelpmreset_in,
    gt2_rxmonitorout_out,
    gt2_rxmonitorsel_in,
    gt2_rxcdrhold_in,
    gt2_eyescanreset_in,
    gt2_eyescandataerror_out,
    gt2_eyescantrigger_in,
    gt2_rxbyteisaligned_out,
    gt2_rxcommadet_out,
    gt2_rxprbserr_out,
    gt2_rxprbssel_in,
    gt2_rxprbscntreset_in,
    gt2_rxpcsreset_in,
    gt2_rxpmareset_in,
    gt2_rxpmaresetdone_out,
    gt2_dmonitorout_out,
    gt2_rxbufreset_in,
    gt2_rx_disp_err_out,
    gt2_rx_not_in_table_out,
    gt2_rx_realign_out,
    gt2_rx_buf_err_out,
    gt2_rxresetdone_out,
    gt2_rxbufstatus_out,
    gt3_cplllock_out,
    gt3_rxlpmen_in,
    gt3_rxcdrovrden_in,
    gt3_rxdfelpmreset_in,
    gt3_rxmonitorout_out,
    gt3_rxmonitorsel_in,
    gt3_rxcdrhold_in,
    gt3_eyescanreset_in,
    gt3_eyescandataerror_out,
    gt3_eyescantrigger_in,
    gt3_rxbyteisaligned_out,
    gt3_rxcommadet_out,
    gt3_rxprbserr_out,
    gt3_rxprbssel_in,
    gt3_rxprbscntreset_in,
    gt3_rxpcsreset_in,
    gt3_rxpmareset_in,
    gt3_rxpmaresetdone_out,
    gt3_dmonitorout_out,
    gt3_rxbufreset_in,
    gt3_rx_disp_err_out,
    gt3_rx_not_in_table_out,
    gt3_rx_realign_out,
    gt3_rx_buf_err_out,
    gt3_rxresetdone_out,
    gt3_rxbufstatus_out,
    sys_reset_out,
    LOOPBACK);
  output [63:0]M_AXI_RX_TDATA;
  output [7:0]M_AXI_RX_TKEEP;
  output M_AXI_RX_TVALID;
  output M_AXI_RX_TLAST;
  output [63:0]M_AXI_UFC_RX_TDATA;
  output [7:0]M_AXI_UFC_RX_TKEEP;
  output M_AXI_UFC_RX_TVALID;
  output M_AXI_UFC_RX_TLAST;
  input [0:3]RXP;
  input [0:3]RXN;
  input gt_refclk1;
  output RX_HARD_ERR;
  output SOFT_ERR;
  output FRAME_ERR;
  output RX_CHANNEL_UP;
  output [0:3]RX_LANE_UP;
  input user_clk;
  input sync_clk;
  input RX_SYSTEM_RESET;
  output RX_RESETDONE_OUT;
  output LINK_RESET_OUT;
  input POWER_DOWN;
  input GT_RESET;
  output TX_LOCK;
  input init_clk_in;
  input PLL_NOT_LOCKED;
  input drpclk_in;
  input [8:0]DRPADDR_IN;
  input [15:0]DRPDI_IN;
  output [15:0]DRPDO_OUT;
  input DRPEN_IN;
  output DRPRDY_OUT;
  input DRPWE_IN;
  input [8:0]DRPADDR_IN_LANE1;
  input [15:0]DRPDI_IN_LANE1;
  output [15:0]DRPDO_OUT_LANE1;
  input DRPEN_IN_LANE1;
  output DRPRDY_OUT_LANE1;
  input DRPWE_IN_LANE1;
  input [8:0]DRPADDR_IN_LANE2;
  input [15:0]DRPDI_IN_LANE2;
  output [15:0]DRPDO_OUT_LANE2;
  input DRPEN_IN_LANE2;
  output DRPRDY_OUT_LANE2;
  input DRPWE_IN_LANE2;
  input [8:0]DRPADDR_IN_LANE3;
  input [15:0]DRPDI_IN_LANE3;
  output [15:0]DRPDO_OUT_LANE3;
  input DRPEN_IN_LANE3;
  output DRPRDY_OUT_LANE3;
  input DRPWE_IN_LANE3;
  output TX_OUT_CLK;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt1_qplllock_in;
  input gt1_qpllrefclklost_in;
  output gt1_qpllreset_out;
  input gt_qpllclk_quad2_in;
  input gt_qpllrefclk_quad2_in;
  input gt_qpllclk_quad3_in;
  input gt_qpllrefclk_quad3_in;
  output gt0_cplllock_out;
  input gt0_rxlpmen_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  output [6:0]gt0_rxmonitorout_out;
  input [1:0]gt0_rxmonitorsel_in;
  input gt0_rxcdrhold_in;
  input gt0_eyescanreset_in;
  output gt0_eyescandataerror_out;
  input gt0_eyescantrigger_in;
  output gt0_rxbyteisaligned_out;
  output gt0_rxcommadet_out;
  output gt0_rxprbserr_out;
  input [2:0]gt0_rxprbssel_in;
  input gt0_rxprbscntreset_in;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  output gt0_rxpmaresetdone_out;
  output [14:0]gt0_dmonitorout_out;
  input gt0_rxbufreset_in;
  output [1:0]gt0_rx_disp_err_out;
  output [1:0]gt0_rx_not_in_table_out;
  output gt0_rx_realign_out;
  output gt0_rx_buf_err_out;
  output gt0_rxresetdone_out;
  output [2:0]gt0_rxbufstatus_out;
  output gt1_cplllock_out;
  input gt1_rxlpmen_in;
  input gt1_rxcdrovrden_in;
  input gt1_rxdfelpmreset_in;
  output [6:0]gt1_rxmonitorout_out;
  input [1:0]gt1_rxmonitorsel_in;
  input gt1_rxcdrhold_in;
  input gt1_eyescanreset_in;
  output gt1_eyescandataerror_out;
  input gt1_eyescantrigger_in;
  output gt1_rxbyteisaligned_out;
  output gt1_rxcommadet_out;
  output gt1_rxprbserr_out;
  input [2:0]gt1_rxprbssel_in;
  input gt1_rxprbscntreset_in;
  input gt1_rxpcsreset_in;
  input gt1_rxpmareset_in;
  output gt1_rxpmaresetdone_out;
  output [14:0]gt1_dmonitorout_out;
  input gt1_rxbufreset_in;
  output [1:0]gt1_rx_disp_err_out;
  output [1:0]gt1_rx_not_in_table_out;
  output gt1_rx_realign_out;
  output gt1_rx_buf_err_out;
  output gt1_rxresetdone_out;
  output [2:0]gt1_rxbufstatus_out;
  output gt2_cplllock_out;
  input gt2_rxlpmen_in;
  input gt2_rxcdrovrden_in;
  input gt2_rxdfelpmreset_in;
  output [6:0]gt2_rxmonitorout_out;
  input [1:0]gt2_rxmonitorsel_in;
  input gt2_rxcdrhold_in;
  input gt2_eyescanreset_in;
  output gt2_eyescandataerror_out;
  input gt2_eyescantrigger_in;
  output gt2_rxbyteisaligned_out;
  output gt2_rxcommadet_out;
  output gt2_rxprbserr_out;
  input [2:0]gt2_rxprbssel_in;
  input gt2_rxprbscntreset_in;
  input gt2_rxpcsreset_in;
  input gt2_rxpmareset_in;
  output gt2_rxpmaresetdone_out;
  output [14:0]gt2_dmonitorout_out;
  input gt2_rxbufreset_in;
  output [1:0]gt2_rx_disp_err_out;
  output [1:0]gt2_rx_not_in_table_out;
  output gt2_rx_realign_out;
  output gt2_rx_buf_err_out;
  output gt2_rxresetdone_out;
  output [2:0]gt2_rxbufstatus_out;
  output gt3_cplllock_out;
  input gt3_rxlpmen_in;
  input gt3_rxcdrovrden_in;
  input gt3_rxdfelpmreset_in;
  output [6:0]gt3_rxmonitorout_out;
  input [1:0]gt3_rxmonitorsel_in;
  input gt3_rxcdrhold_in;
  input gt3_eyescanreset_in;
  output gt3_eyescandataerror_out;
  input gt3_eyescantrigger_in;
  output gt3_rxbyteisaligned_out;
  output gt3_rxcommadet_out;
  output gt3_rxprbserr_out;
  input [2:0]gt3_rxprbssel_in;
  input gt3_rxprbscntreset_in;
  input gt3_rxpcsreset_in;
  input gt3_rxpmareset_in;
  output gt3_rxpmaresetdone_out;
  output [14:0]gt3_dmonitorout_out;
  input gt3_rxbufreset_in;
  output [1:0]gt3_rx_disp_err_out;
  output [1:0]gt3_rx_not_in_table_out;
  output gt3_rx_realign_out;
  output gt3_rx_buf_err_out;
  output gt3_rxresetdone_out;
  output [2:0]gt3_rxbufstatus_out;
  output sys_reset_out;
  input [2:0]LOOPBACK;

  wire \<const0> ;
  wire CHBONDDONE_OUT;
  wire CHBONDDONE_OUT_LANE1;
  wire CHBONDDONE_OUT_LANE2;
  wire CHBONDDONE_OUT_LANE3;
  wire [8:0]DRPADDR_IN;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT;
  wire [15:0]DRPDO_OUT_LANE1;
  wire [15:0]DRPDO_OUT_LANE2;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN;
  wire DRPEN_IN_LANE1;
  wire DRPEN_IN_LANE2;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT;
  wire DRPRDY_OUT_LANE1;
  wire DRPRDY_OUT_LANE2;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN;
  wire DRPWE_IN_LANE1;
  wire DRPWE_IN_LANE2;
  wire DRPWE_IN_LANE3;
  wire FRAME_ERR;
  wire [0:1]GOT_A;
  wire GOT_V;
  wire GT_RESET;
  wire HARD_ERR;
  wire HPCNT_RESET;
  wire LINK_RESET_OUT;
  wire [2:0]LOOPBACK;
  wire [63:0]M_AXI_RX_TDATA;
  wire [7:1]\^M_AXI_RX_TKEEP ;
  wire M_AXI_RX_TLAST;
  wire M_AXI_RX_TVALID;
  wire [63:0]M_AXI_UFC_RX_TDATA;
  wire [7:3]\^M_AXI_UFC_RX_TKEEP ;
  wire M_AXI_UFC_RX_TLAST;
  wire M_AXI_UFC_RX_TVALID;
  wire POWER_DOWN;
  wire RESET;
  wire RESET_24;
  wire [0:3]RXN;
  wire [0:3]RXP;
  wire RX_CHANNEL_UP;
  wire RX_HARD_ERR;
  wire [0:3]RX_LANE_UP;
  wire [8:10]RX_PE_DATA;
  wire RX_PE_DATA_V;
  wire RX_RESETDONE_OUT;
  wire RX_SCP;
  wire RX_SUF;
  wire RX_SYSTEM_RESET;
  wire SOFT_ERR;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire [0:3]ch_bond_done_dly_i;
  wire [3:0]ch_bond_done_r2;
  wire ch_bond_load_pulse_i;
  wire \ch_bond_load_pulse_i[0]_i_1_n_0 ;
  wire \ch_bond_load_pulse_i[1]_i_1_n_0 ;
  wire \ch_bond_load_pulse_i[2]_i_1_n_0 ;
  wire \ch_bond_load_pulse_i[3]_i_1_n_0 ;
  wire \ch_bond_load_pulse_i_reg_n_0_[0] ;
  wire \ch_bond_load_pulse_i_reg_n_0_[1] ;
  wire \ch_bond_load_pulse_i_reg_n_0_[2] ;
  wire \ch_bond_load_pulse_i_reg_n_0_[3] ;
  wire drpclk_in;
  wire en_chan_sync_i;
  wire ena_comma_align_i_0;
  wire ena_comma_align_i_1;
  wire ena_comma_align_i_2;
  wire ena_comma_align_i_3;
  wire gt0_cplllock_out;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire gt0_rx_buf_err_out;
  wire [1:0]gt0_rx_disp_err_out;
  wire [1:0]gt0_rx_not_in_table_out;
  wire gt0_rx_realign_out;
  wire gt0_rxbufreset_in;
  wire [1:0]\^gt0_rxbufstatus_out ;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt1_cplllock_out;
  wire [14:0]gt1_dmonitorout_out;
  wire gt1_eyescandataerror_out;
  wire gt1_eyescanreset_in;
  wire gt1_eyescantrigger_in;
  wire gt1_rx_buf_err_out;
  wire [1:0]gt1_rx_disp_err_out;
  wire [1:0]gt1_rx_not_in_table_out;
  wire gt1_rx_realign_out;
  wire gt1_rxbufreset_in;
  wire [1:0]\^gt1_rxbufstatus_out ;
  wire gt1_rxbyteisaligned_out;
  wire gt1_rxcdrhold_in;
  wire gt1_rxcdrovrden_in;
  wire gt1_rxcommadet_out;
  wire gt1_rxdfelpmreset_in;
  wire gt1_rxlpmen_in;
  wire [6:0]gt1_rxmonitorout_out;
  wire [1:0]gt1_rxmonitorsel_in;
  wire gt1_rxpcsreset_in;
  wire gt1_rxpmareset_in;
  wire gt1_rxpmaresetdone_out;
  wire gt1_rxprbscntreset_in;
  wire gt1_rxprbserr_out;
  wire [2:0]gt1_rxprbssel_in;
  wire gt1_rxresetdone_out;
  wire gt2_cplllock_out;
  wire [14:0]gt2_dmonitorout_out;
  wire gt2_eyescandataerror_out;
  wire gt2_eyescanreset_in;
  wire gt2_eyescantrigger_in;
  wire gt2_rx_buf_err_out;
  wire [1:0]gt2_rx_disp_err_out;
  wire [1:0]gt2_rx_not_in_table_out;
  wire gt2_rx_realign_out;
  wire gt2_rxbufreset_in;
  wire [1:0]\^gt2_rxbufstatus_out ;
  wire gt2_rxbyteisaligned_out;
  wire gt2_rxcdrhold_in;
  wire gt2_rxcdrovrden_in;
  wire gt2_rxcommadet_out;
  wire gt2_rxdfelpmreset_in;
  wire gt2_rxlpmen_in;
  wire [6:0]gt2_rxmonitorout_out;
  wire [1:0]gt2_rxmonitorsel_in;
  wire gt2_rxpcsreset_in;
  wire gt2_rxpmareset_in;
  wire gt2_rxpmaresetdone_out;
  wire gt2_rxprbscntreset_in;
  wire gt2_rxprbserr_out;
  wire [2:0]gt2_rxprbssel_in;
  wire gt2_rxresetdone_out;
  wire gt3_cplllock_out;
  wire [14:0]gt3_dmonitorout_out;
  wire gt3_eyescandataerror_out;
  wire gt3_eyescanreset_in;
  wire gt3_eyescantrigger_in;
  wire gt3_rx_buf_err_out;
  wire [1:0]gt3_rx_disp_err_out;
  wire [1:0]gt3_rx_not_in_table_out;
  wire gt3_rx_realign_out;
  wire gt3_rxbufreset_in;
  wire [1:0]\^gt3_rxbufstatus_out ;
  wire gt3_rxbyteisaligned_out;
  wire gt3_rxcdrhold_in;
  wire gt3_rxcdrovrden_in;
  wire gt3_rxcommadet_out;
  wire gt3_rxdfelpmreset_in;
  wire gt3_rxlpmen_in;
  wire [6:0]gt3_rxmonitorout_out;
  wire [1:0]gt3_rxmonitorsel_in;
  wire gt3_rxpcsreset_in;
  wire gt3_rxpmareset_in;
  wire gt3_rxpmaresetdone_out;
  wire gt3_rxprbscntreset_in;
  wire gt3_rxprbserr_out;
  wire [2:0]gt3_rxprbssel_in;
  wire gt3_rxresetdone_out;
  wire gt_qpllclk_quad2_in;
  wire gt_qpllclk_quad3_in;
  wire gt_qpllrefclk_quad2_in;
  wire gt_qpllrefclk_quad3_in;
  wire gt_refclk1;
  wire gt_reset_sync_init_clk;
  wire gt_wrapper_i_n_231;
  wire gt_wrapper_i_n_232;
  wire gt_wrapper_i_n_233;
  wire gt_wrapper_i_n_234;
  wire gt_wrapper_i_n_235;
  wire gt_wrapper_i_n_236;
  wire gt_wrapper_i_n_237;
  wire gt_wrapper_i_n_238;
  wire gt_wrapper_i_n_239;
  wire gt_wrapper_i_n_242;
  wire gt_wrapper_i_n_244;
  wire gt_wrapper_i_n_245;
  wire gt_wrapper_i_n_246;
  wire gt_wrapper_i_n_247;
  wire gt_wrapper_i_n_248;
  wire gt_wrapper_i_n_249;
  wire gt_wrapper_i_n_250;
  wire gt_wrapper_i_n_251;
  wire gt_wrapper_i_n_252;
  wire gt_wrapper_i_n_253;
  wire gt_wrapper_i_n_254;
  wire gt_wrapper_i_n_255;
  wire gt_wrapper_i_n_256;
  wire gt_wrapper_i_n_257;
  wire gt_wrapper_i_n_258;
  wire gt_wrapper_i_n_259;
  wire gt_wrapper_i_n_260;
  wire gt_wrapper_i_n_263;
  wire gt_wrapper_i_n_265;
  wire gt_wrapper_i_n_266;
  wire gt_wrapper_i_n_267;
  wire gt_wrapper_i_n_268;
  wire gt_wrapper_i_n_269;
  wire gt_wrapper_i_n_270;
  wire gt_wrapper_i_n_271;
  wire gt_wrapper_i_n_272;
  wire gt_wrapper_i_n_273;
  wire gt_wrapper_i_n_274;
  wire gt_wrapper_i_n_275;
  wire gt_wrapper_i_n_276;
  wire gt_wrapper_i_n_277;
  wire gt_wrapper_i_n_278;
  wire gt_wrapper_i_n_279;
  wire gt_wrapper_i_n_280;
  wire gt_wrapper_i_n_281;
  wire gt_wrapper_i_n_284;
  wire gt_wrapper_i_n_286;
  wire gt_wrapper_i_n_287;
  wire gt_wrapper_i_n_288;
  wire gt_wrapper_i_n_289;
  wire gt_wrapper_i_n_290;
  wire gt_wrapper_i_n_291;
  wire gt_wrapper_i_n_292;
  wire gt_wrapper_i_n_293;
  wire gt_wrapper_i_n_294;
  wire gt_wrapper_i_n_295;
  wire gt_wrapper_i_n_296;
  wire gt_wrapper_i_n_297;
  wire gt_wrapper_i_n_298;
  wire gt_wrapper_i_n_299;
  wire gt_wrapper_i_n_300;
  wire gt_wrapper_i_n_301;
  wire gt_wrapper_i_n_302;
  wire gt_wrapper_i_n_305;
  wire gt_wrapper_i_n_307;
  wire gt_wrapper_i_n_308;
  wire gt_wrapper_i_n_309;
  wire gt_wrapper_i_n_310;
  wire gt_wrapper_i_n_311;
  wire gt_wrapper_i_n_312;
  wire gt_wrapper_i_n_313;
  wire gt_wrapper_i_n_314;
  wire gt_wrapper_i_n_315;
  wire gt_wrapper_i_n_316;
  wire gt_wrapper_i_n_317;
  wire gt_wrapper_i_n_318;
  wire gt_wrapper_i_n_319;
  wire gt_wrapper_i_n_320;
  wire gt_wrapper_i_n_321;
  wire gt_wrapper_i_n_322;
  wire gt_wrapper_i_n_323;
  wire gtp_rx_reset_i_0;
  wire gtp_rx_reset_i_1;
  wire gtp_rx_reset_i_2;
  wire gtp_rx_reset_i_3;
  wire gtrxreset_i;
  wire init_clk_in;
  wire link_reset_lane0_i;
  wire link_reset_lane1_i;
  wire link_reset_lane2_i;
  wire link_reset_r;
  wire reset_sync_init_clk;
  wire reset_sync_user_clk;
  wire rx_aurora_lane_simplex_v5_0_i_n_14;
  wire rx_aurora_lane_simplex_v5_0_i_n_16;
  wire rx_aurora_lane_simplex_v5_0_i_n_17;
  wire rx_aurora_lane_simplex_v5_0_i_n_18;
  wire rx_aurora_lane_simplex_v5_0_i_n_19;
  wire rx_aurora_lane_simplex_v5_0_i_n_20;
  wire rx_aurora_lane_simplex_v5_0_i_n_21;
  wire rx_aurora_lane_simplex_v5_0_i_n_26;
  wire rx_aurora_lane_simplex_v5_0_i_n_27;
  wire rx_aurora_lane_simplex_v5_0_i_n_28;
  wire rx_aurora_lane_simplex_v5_0_i_n_29;
  wire rx_aurora_lane_simplex_v5_0_i_n_30;
  wire rx_aurora_lane_simplex_v5_0_i_n_31;
  wire rx_aurora_lane_simplex_v5_0_i_n_32;
  wire rx_aurora_lane_simplex_v5_0_i_n_33;
  wire rx_aurora_lane_simplex_v5_0_i_n_34;
  wire rx_aurora_lane_simplex_v5_0_i_n_35;
  wire rx_aurora_lane_simplex_v5_0_i_n_36;
  wire rx_aurora_lane_simplex_v5_0_i_n_37;
  wire rx_aurora_lane_simplex_v5_1_i_n_10;
  wire rx_aurora_lane_simplex_v5_1_i_n_11;
  wire rx_aurora_lane_simplex_v5_1_i_n_12;
  wire rx_aurora_lane_simplex_v5_1_i_n_14;
  wire rx_aurora_lane_simplex_v5_1_i_n_15;
  wire rx_aurora_lane_simplex_v5_1_i_n_16;
  wire rx_aurora_lane_simplex_v5_1_i_n_17;
  wire rx_aurora_lane_simplex_v5_1_i_n_18;
  wire rx_aurora_lane_simplex_v5_1_i_n_19;
  wire rx_aurora_lane_simplex_v5_1_i_n_20;
  wire rx_aurora_lane_simplex_v5_1_i_n_22;
  wire rx_aurora_lane_simplex_v5_1_i_n_23;
  wire rx_aurora_lane_simplex_v5_1_i_n_24;
  wire rx_aurora_lane_simplex_v5_1_i_n_25;
  wire rx_aurora_lane_simplex_v5_1_i_n_26;
  wire rx_aurora_lane_simplex_v5_1_i_n_27;
  wire rx_aurora_lane_simplex_v5_1_i_n_28;
  wire rx_aurora_lane_simplex_v5_1_i_n_29;
  wire rx_aurora_lane_simplex_v5_1_i_n_30;
  wire rx_aurora_lane_simplex_v5_1_i_n_31;
  wire rx_aurora_lane_simplex_v5_1_i_n_32;
  wire rx_aurora_lane_simplex_v5_1_i_n_33;
  wire rx_aurora_lane_simplex_v5_1_i_n_35;
  wire rx_aurora_lane_simplex_v5_1_i_n_36;
  wire rx_aurora_lane_simplex_v5_1_i_n_4;
  wire rx_aurora_lane_simplex_v5_1_i_n_6;
  wire rx_aurora_lane_simplex_v5_1_i_n_8;
  wire rx_aurora_lane_simplex_v5_1_i_n_9;
  wire rx_aurora_lane_simplex_v5_2_i_n_10;
  wire rx_aurora_lane_simplex_v5_2_i_n_11;
  wire rx_aurora_lane_simplex_v5_2_i_n_12;
  wire rx_aurora_lane_simplex_v5_2_i_n_14;
  wire rx_aurora_lane_simplex_v5_2_i_n_15;
  wire rx_aurora_lane_simplex_v5_2_i_n_16;
  wire rx_aurora_lane_simplex_v5_2_i_n_18;
  wire rx_aurora_lane_simplex_v5_2_i_n_20;
  wire rx_aurora_lane_simplex_v5_2_i_n_21;
  wire rx_aurora_lane_simplex_v5_2_i_n_22;
  wire rx_aurora_lane_simplex_v5_2_i_n_23;
  wire rx_aurora_lane_simplex_v5_2_i_n_24;
  wire rx_aurora_lane_simplex_v5_2_i_n_25;
  wire rx_aurora_lane_simplex_v5_2_i_n_26;
  wire rx_aurora_lane_simplex_v5_2_i_n_27;
  wire rx_aurora_lane_simplex_v5_2_i_n_28;
  wire rx_aurora_lane_simplex_v5_2_i_n_29;
  wire rx_aurora_lane_simplex_v5_2_i_n_30;
  wire rx_aurora_lane_simplex_v5_2_i_n_31;
  wire rx_aurora_lane_simplex_v5_2_i_n_33;
  wire rx_aurora_lane_simplex_v5_2_i_n_34;
  wire rx_aurora_lane_simplex_v5_2_i_n_4;
  wire rx_aurora_lane_simplex_v5_2_i_n_6;
  wire rx_aurora_lane_simplex_v5_2_i_n_8;
  wire rx_aurora_lane_simplex_v5_2_i_n_9;
  wire rx_aurora_lane_simplex_v5_3_i_n_10;
  wire rx_aurora_lane_simplex_v5_3_i_n_11;
  wire rx_aurora_lane_simplex_v5_3_i_n_13;
  wire rx_aurora_lane_simplex_v5_3_i_n_14;
  wire rx_aurora_lane_simplex_v5_3_i_n_15;
  wire rx_aurora_lane_simplex_v5_3_i_n_16;
  wire rx_aurora_lane_simplex_v5_3_i_n_17;
  wire rx_aurora_lane_simplex_v5_3_i_n_20;
  wire rx_aurora_lane_simplex_v5_3_i_n_21;
  wire rx_aurora_lane_simplex_v5_3_i_n_22;
  wire rx_aurora_lane_simplex_v5_3_i_n_24;
  wire rx_aurora_lane_simplex_v5_3_i_n_25;
  wire rx_aurora_lane_simplex_v5_3_i_n_26;
  wire rx_aurora_lane_simplex_v5_3_i_n_27;
  wire rx_aurora_lane_simplex_v5_3_i_n_28;
  wire rx_aurora_lane_simplex_v5_3_i_n_29;
  wire rx_aurora_lane_simplex_v5_3_i_n_30;
  wire rx_aurora_lane_simplex_v5_3_i_n_31;
  wire rx_aurora_lane_simplex_v5_3_i_n_32;
  wire rx_aurora_lane_simplex_v5_3_i_n_33;
  wire rx_aurora_lane_simplex_v5_3_i_n_34;
  wire rx_aurora_lane_simplex_v5_3_i_n_35;
  wire rx_aurora_lane_simplex_v5_3_i_n_4;
  wire rx_aurora_lane_simplex_v5_3_i_n_6;
  wire rx_aurora_lane_simplex_v5_3_i_n_7;
  wire rx_aurora_lane_simplex_v5_3_i_n_8;
  wire rx_aurora_lane_simplex_v5_3_i_n_9;
  wire \rx_channel_init_sm_simplex_i/bad_as_r0 ;
  wire \rx_channel_init_sm_simplex_i/good_as_r0 ;
  wire \rx_channel_init_sm_simplex_i/p_0_in10_in ;
  wire \rx_channel_init_sm_simplex_i/p_1_in11_in ;
  wire [1:0]rx_char_is_comma_i_0;
  wire [1:0]rx_char_is_comma_i_2;
  wire [1:0]rx_char_is_comma_i_4;
  wire [1:0]rx_char_is_comma_i_6;
  wire rx_eof;
  wire \rx_err_detect_simplex_gtp_i/bucket_full_r ;
  wire \rx_err_detect_simplex_gtp_i/bucket_full_r_10 ;
  wire \rx_err_detect_simplex_gtp_i/bucket_full_r_16 ;
  wire \rx_err_detect_simplex_gtp_i/bucket_full_r_22 ;
  wire \rx_err_detect_simplex_gtp_i/hard_err_flop_r0 ;
  wire \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_0 ;
  wire \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_2 ;
  wire \rx_err_detect_simplex_gtp_i/hard_err_flop_r0_4 ;
  wire [1:0]\rx_err_detect_simplex_gtp_i/p_2_out ;
  wire [1:0]\rx_err_detect_simplex_gtp_i/p_2_out_1 ;
  wire [1:0]\rx_err_detect_simplex_gtp_i/p_2_out_3 ;
  wire [1:0]\rx_err_detect_simplex_gtp_i/p_2_out_5 ;
  wire rx_global_logic_simplex_i_n_1;
  wire rx_global_logic_simplex_i_n_10;
  wire rx_global_logic_simplex_i_n_13;
  wire rx_global_logic_simplex_i_n_14;
  wire rx_global_logic_simplex_i_n_2;
  wire rx_global_logic_simplex_i_n_3;
  wire \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r ;
  wire \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_11 ;
  wire \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_17 ;
  wire \rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_23 ;
  wire rx_polarity_i_0;
  wire rx_polarity_i_1;
  wire rx_polarity_i_2;
  wire rx_polarity_i_3;
  wire [0:2]rx_rem;
  wire rx_ufc_eof;
  wire [0:1]rx_ufc_rem;
  wire start_rx_i;
  wire \sym_dec_i/RX_ECP_Buffer0 ;
  wire \sym_dec_i/RX_ECP_Buffer0_12 ;
  wire \sym_dec_i/RX_ECP_Buffer0_18 ;
  wire \sym_dec_i/RX_ECP_Buffer0_6 ;
  wire \sym_dec_i/first_v_received_r ;
  wire \sym_dec_i/first_v_received_r_14 ;
  wire \sym_dec_i/first_v_received_r_20 ;
  wire \sym_dec_i/first_v_received_r_8 ;
  wire [0:0]\sym_dec_i/p_0_in ;
  wire [0:0]\sym_dec_i/p_0_in_15 ;
  wire [0:0]\sym_dec_i/p_0_in_21 ;
  wire [0:0]\sym_dec_i/p_0_in_9 ;
  wire \sym_dec_i/std_bool26_out ;
  wire \sym_dec_i/std_bool26_out_13 ;
  wire \sym_dec_i/std_bool26_out_19 ;
  wire \sym_dec_i/std_bool26_out_7 ;
  wire sync_clk;
  wire sys_reset_out;
  wire \ufc_filter_i/neqOp ;
  wire user_clk;

  assign M_AXI_RX_TKEEP[7:1] = \^M_AXI_RX_TKEEP [7:1];
  assign M_AXI_RX_TKEEP[0] = \<const0> ;
  assign M_AXI_UFC_RX_TKEEP[7] = \^M_AXI_UFC_RX_TKEEP [7];
  assign M_AXI_UFC_RX_TKEEP[6] = \^M_AXI_UFC_RX_TKEEP [7];
  assign M_AXI_UFC_RX_TKEEP[5] = \^M_AXI_UFC_RX_TKEEP [5];
  assign M_AXI_UFC_RX_TKEEP[4] = \^M_AXI_UFC_RX_TKEEP [5];
  assign M_AXI_UFC_RX_TKEEP[3] = \^M_AXI_UFC_RX_TKEEP [3];
  assign M_AXI_UFC_RX_TKEEP[2] = \^M_AXI_UFC_RX_TKEEP [3];
  assign M_AXI_UFC_RX_TKEEP[1] = \<const0> ;
  assign M_AXI_UFC_RX_TKEEP[0] = \<const0> ;
  assign gt0_qpllreset_out = \<const0> ;
  assign gt0_rxbufstatus_out[2] = gt0_rx_buf_err_out;
  assign gt0_rxbufstatus_out[1:0] = \^gt0_rxbufstatus_out [1:0];
  assign gt1_qpllreset_out = \<const0> ;
  assign gt1_rxbufstatus_out[2] = gt1_rx_buf_err_out;
  assign gt1_rxbufstatus_out[1:0] = \^gt1_rxbufstatus_out [1:0];
  assign gt2_rxbufstatus_out[2] = gt2_rx_buf_err_out;
  assign gt2_rxbufstatus_out[1:0] = \^gt2_rxbufstatus_out [1:0];
  assign gt3_rxbufstatus_out[2] = gt3_rx_buf_err_out;
  assign gt3_rxbufstatus_out[1:0] = \^gt3_rxbufstatus_out [1:0];
  GND GND
       (.G(\<const0> ));
  FDRE \ch_bond_done_dly_i_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ch_bond_done_r2[3]),
        .Q(ch_bond_done_dly_i[0]),
        .R(ch_bond_load_pulse_i));
  FDRE \ch_bond_done_dly_i_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ch_bond_done_r2[2]),
        .Q(ch_bond_done_dly_i[1]),
        .R(ch_bond_load_pulse_i));
  FDRE \ch_bond_done_dly_i_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ch_bond_done_r2[1]),
        .Q(ch_bond_done_dly_i[2]),
        .R(ch_bond_load_pulse_i));
  FDRE \ch_bond_done_dly_i_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(ch_bond_done_r2[0]),
        .Q(ch_bond_done_dly_i[3]),
        .R(ch_bond_load_pulse_i));
  FDRE \ch_bond_done_r2_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_global_logic_simplex_i_n_13),
        .Q(ch_bond_done_r2[0]),
        .R(1'b0));
  FDRE \ch_bond_done_r2_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_channel_init_sm_simplex_i/p_1_in11_in ),
        .Q(ch_bond_done_r2[1]),
        .R(1'b0));
  FDRE \ch_bond_done_r2_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\rx_channel_init_sm_simplex_i/p_0_in10_in ),
        .Q(ch_bond_done_r2[2]),
        .R(1'b0));
  FDRE \ch_bond_done_r2_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(rx_global_logic_simplex_i_n_10),
        .Q(ch_bond_done_r2[3]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \ch_bond_load_pulse_i[0]_i_1 
       (.I0(ch_bond_done_r2[3]),
        .I1(ch_bond_done_dly_i[0]),
        .O(\ch_bond_load_pulse_i[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \ch_bond_load_pulse_i[1]_i_1 
       (.I0(ch_bond_done_r2[2]),
        .I1(ch_bond_done_dly_i[1]),
        .O(\ch_bond_load_pulse_i[1]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \ch_bond_load_pulse_i[2]_i_1 
       (.I0(ch_bond_done_r2[1]),
        .I1(ch_bond_done_dly_i[2]),
        .O(\ch_bond_load_pulse_i[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \ch_bond_load_pulse_i[3]_i_1 
       (.I0(ch_bond_done_r2[0]),
        .I1(ch_bond_done_dly_i[3]),
        .O(\ch_bond_load_pulse_i[3]_i_1_n_0 ));
  FDRE \ch_bond_load_pulse_i_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ch_bond_load_pulse_i[0]_i_1_n_0 ),
        .Q(\ch_bond_load_pulse_i_reg_n_0_[0] ),
        .R(ch_bond_load_pulse_i));
  FDRE \ch_bond_load_pulse_i_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ch_bond_load_pulse_i[1]_i_1_n_0 ),
        .Q(\ch_bond_load_pulse_i_reg_n_0_[1] ),
        .R(ch_bond_load_pulse_i));
  FDRE \ch_bond_load_pulse_i_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ch_bond_load_pulse_i[2]_i_1_n_0 ),
        .Q(\ch_bond_load_pulse_i_reg_n_0_[2] ),
        .R(ch_bond_load_pulse_i));
  FDRE \ch_bond_load_pulse_i_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\ch_bond_load_pulse_i[3]_i_1_n_0 ),
        .Q(\ch_bond_load_pulse_i_reg_n_0_[3] ),
        .R(ch_bond_load_pulse_i));
  aurora_rx_4l_64b_RESET_LOGIC core_reset_logic_i
       (.SR(ch_bond_load_pulse_i),
        .SYSTEM_RESET_reg_0(sys_reset_out),
        .TX_LOCK(TX_LOCK),
        .en_chan_sync_i(en_chan_sync_i),
        .gt_rxresetdone_r2_reg_0(gt_wrapper_i_n_323),
        .init_clk_in(init_clk_in),
        .link_reset_r(link_reset_r),
        .out(reset_sync_user_clk),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync gt_reset_cdc_sync
       (.GT_RESET(GT_RESET),
        .HPCNT_RESET(HPCNT_RESET),
        .\hotplug_count_synth.count_for_reset_r_reg[0] (reset_sync_init_clk),
        .init_clk_in(init_clk_in),
        .out(gt_reset_sync_init_clk));
  aurora_rx_4l_64b_GT_WRAPPER gt_wrapper_i
       (.CHBONDDONE_OUT(CHBONDDONE_OUT),
        .CHBONDDONE_OUT_LANE1(CHBONDDONE_OUT_LANE1),
        .CHBONDDONE_OUT_LANE2(CHBONDDONE_OUT_LANE2),
        .CHBONDDONE_OUT_LANE3(CHBONDDONE_OUT_LANE3),
        .D(rx_char_is_comma_i_0),
        .DRPADDR_IN(DRPADDR_IN),
        .DRPADDR_IN_LANE1(DRPADDR_IN_LANE1),
        .DRPADDR_IN_LANE2(DRPADDR_IN_LANE2),
        .DRPADDR_IN_LANE3(DRPADDR_IN_LANE3),
        .DRPDI_IN(DRPDI_IN),
        .DRPDI_IN_LANE1(DRPDI_IN_LANE1),
        .DRPDI_IN_LANE2(DRPDI_IN_LANE2),
        .DRPDI_IN_LANE3(DRPDI_IN_LANE3),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPDO_OUT_LANE1(DRPDO_OUT_LANE1),
        .DRPDO_OUT_LANE2(DRPDO_OUT_LANE2),
        .DRPDO_OUT_LANE3(DRPDO_OUT_LANE3),
        .DRPEN_IN(DRPEN_IN),
        .DRPEN_IN_LANE1(DRPEN_IN_LANE1),
        .DRPEN_IN_LANE2(DRPEN_IN_LANE2),
        .DRPEN_IN_LANE3(DRPEN_IN_LANE3),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPRDY_OUT_LANE1(DRPRDY_OUT_LANE1),
        .DRPRDY_OUT_LANE2(DRPRDY_OUT_LANE2),
        .DRPRDY_OUT_LANE3(DRPRDY_OUT_LANE3),
        .DRPWE_IN(DRPWE_IN),
        .DRPWE_IN_LANE1(DRPWE_IN_LANE1),
        .DRPWE_IN_LANE2(DRPWE_IN_LANE2),
        .DRPWE_IN_LANE3(DRPWE_IN_LANE3),
        .LINK_RESET_OUT(LINK_RESET_OUT),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXN(RXN),
        .RXP(RXP),
        .RX_RESETDONE_OUT(RX_RESETDONE_OUT),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .bucket_full_r(\rx_err_detect_simplex_gtp_i/bucket_full_r ),
        .bucket_full_r_11(\rx_err_detect_simplex_gtp_i/bucket_full_r_22 ),
        .bucket_full_r_5(\rx_err_detect_simplex_gtp_i/bucket_full_r_10 ),
        .bucket_full_r_8(\rx_err_detect_simplex_gtp_i/bucket_full_r_16 ),
        .comma_over_two_cycles_r(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r ),
        .comma_over_two_cycles_r_3(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_11 ),
        .comma_over_two_cycles_r_6(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_17 ),
        .comma_over_two_cycles_r_9(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_23 ),
        .drpclk_in(drpclk_in),
        .en_chan_sync_i(en_chan_sync_i),
        .ena_comma_align_i_0(ena_comma_align_i_0),
        .ena_comma_align_i_1(ena_comma_align_i_1),
        .ena_comma_align_i_2(ena_comma_align_i_2),
        .ena_comma_align_i_3(ena_comma_align_i_3),
        .first_v_received_r(\sym_dec_i/first_v_received_r ),
        .first_v_received_r_10(\sym_dec_i/first_v_received_r_20 ),
        .first_v_received_r_4(\sym_dec_i/first_v_received_r_8 ),
        .first_v_received_r_7(\sym_dec_i/first_v_received_r_14 ),
        .first_v_received_r_reg(gt_wrapper_i_n_242),
        .first_v_received_r_reg_0(gt_wrapper_i_n_263),
        .first_v_received_r_reg_1(gt_wrapper_i_n_284),
        .first_v_received_r_reg_2(gt_wrapper_i_n_305),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out({gt0_rx_buf_err_out,\^gt0_rxbufstatus_out }),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_dmonitorout_out(gt1_dmonitorout_out),
        .gt1_eyescandataerror_out(gt1_eyescandataerror_out),
        .gt1_eyescanreset_in(gt1_eyescanreset_in),
        .gt1_eyescantrigger_in(gt1_eyescantrigger_in),
        .gt1_rx_disp_err_out(gt1_rx_disp_err_out),
        .gt1_rx_not_in_table_out(gt1_rx_not_in_table_out),
        .gt1_rxbufreset_in(gt1_rxbufreset_in),
        .gt1_rxbufstatus_out({gt1_rx_buf_err_out,\^gt1_rxbufstatus_out }),
        .gt1_rxbyteisaligned_out(gt1_rxbyteisaligned_out),
        .gt1_rxcdrhold_in(gt1_rxcdrhold_in),
        .gt1_rxcdrovrden_in(gt1_rxcdrovrden_in),
        .gt1_rxcommadet_out(gt1_rxcommadet_out),
        .gt1_rxdfelpmreset_in(gt1_rxdfelpmreset_in),
        .gt1_rxlpmen_in(gt1_rxlpmen_in),
        .gt1_rxmonitorout_out(gt1_rxmonitorout_out),
        .gt1_rxmonitorsel_in(gt1_rxmonitorsel_in),
        .gt1_rxpcsreset_in(gt1_rxpcsreset_in),
        .gt1_rxpmareset_in(gt1_rxpmareset_in),
        .gt1_rxpmaresetdone_out(gt1_rxpmaresetdone_out),
        .gt1_rxprbscntreset_in(gt1_rxprbscntreset_in),
        .gt1_rxprbserr_out(gt1_rxprbserr_out),
        .gt1_rxprbssel_in(gt1_rxprbssel_in),
        .gt1_rxresetdone_out(gt1_rxresetdone_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_dmonitorout_out(gt2_dmonitorout_out),
        .gt2_eyescandataerror_out(gt2_eyescandataerror_out),
        .gt2_eyescanreset_in(gt2_eyescanreset_in),
        .gt2_eyescantrigger_in(gt2_eyescantrigger_in),
        .gt2_rx_disp_err_out(gt2_rx_disp_err_out),
        .gt2_rx_not_in_table_out(gt2_rx_not_in_table_out),
        .gt2_rxbufreset_in(gt2_rxbufreset_in),
        .gt2_rxbufstatus_out({gt2_rx_buf_err_out,\^gt2_rxbufstatus_out }),
        .gt2_rxbyteisaligned_out(gt2_rxbyteisaligned_out),
        .gt2_rxcdrhold_in(gt2_rxcdrhold_in),
        .gt2_rxcdrovrden_in(gt2_rxcdrovrden_in),
        .gt2_rxcommadet_out(gt2_rxcommadet_out),
        .gt2_rxdfelpmreset_in(gt2_rxdfelpmreset_in),
        .gt2_rxlpmen_in(gt2_rxlpmen_in),
        .gt2_rxmonitorout_out(gt2_rxmonitorout_out),
        .gt2_rxmonitorsel_in(gt2_rxmonitorsel_in),
        .gt2_rxpcsreset_in(gt2_rxpcsreset_in),
        .gt2_rxpmareset_in(gt2_rxpmareset_in),
        .gt2_rxpmaresetdone_out(gt2_rxpmaresetdone_out),
        .gt2_rxprbscntreset_in(gt2_rxprbscntreset_in),
        .gt2_rxprbserr_out(gt2_rxprbserr_out),
        .gt2_rxprbssel_in(gt2_rxprbssel_in),
        .gt2_rxresetdone_out(gt2_rxresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_dmonitorout_out(gt3_dmonitorout_out),
        .gt3_eyescandataerror_out(gt3_eyescandataerror_out),
        .gt3_eyescanreset_in(gt3_eyescanreset_in),
        .gt3_eyescantrigger_in(gt3_eyescantrigger_in),
        .gt3_rx_disp_err_out(gt3_rx_disp_err_out),
        .gt3_rx_not_in_table_out(gt3_rx_not_in_table_out),
        .gt3_rxbufreset_in(gt3_rxbufreset_in),
        .gt3_rxbufstatus_out({gt3_rx_buf_err_out,\^gt3_rxbufstatus_out }),
        .gt3_rxbyteisaligned_out(gt3_rxbyteisaligned_out),
        .gt3_rxcdrhold_in(gt3_rxcdrhold_in),
        .gt3_rxcdrovrden_in(gt3_rxcdrovrden_in),
        .gt3_rxcommadet_out(gt3_rxcommadet_out),
        .gt3_rxdfelpmreset_in(gt3_rxdfelpmreset_in),
        .gt3_rxlpmen_in(gt3_rxlpmen_in),
        .gt3_rxmonitorout_out(gt3_rxmonitorout_out),
        .gt3_rxmonitorsel_in(gt3_rxmonitorsel_in),
        .gt3_rxpcsreset_in(gt3_rxpcsreset_in),
        .gt3_rxpmareset_in(gt3_rxpmareset_in),
        .gt3_rxpmaresetdone_out(gt3_rxpmaresetdone_out),
        .gt3_rxprbscntreset_in(gt3_rxprbscntreset_in),
        .gt3_rxprbserr_out(gt3_rxprbserr_out),
        .gt3_rxprbssel_in(gt3_rxprbssel_in),
        .gt3_rxresetdone_out(gt3_rxresetdone_out),
        .gt_qpllclk_quad2_in(gt_qpllclk_quad2_in),
        .gt_qpllclk_quad3_in(gt_qpllclk_quad3_in),
        .gt_qpllrefclk_quad2_in(gt_qpllrefclk_quad2_in),
        .gt_qpllrefclk_quad3_in(gt_qpllrefclk_quad3_in),
        .gt_refclk1(gt_refclk1),
        .gthe2_i(gt0_rx_realign_out),
        .gthe2_i_0(gt1_rx_realign_out),
        .gthe2_i_1(rx_char_is_comma_i_2),
        .gthe2_i_10(gt_wrapper_i_n_235),
        .gthe2_i_11(gt_wrapper_i_n_236),
        .gthe2_i_12(gt_wrapper_i_n_237),
        .gthe2_i_13(gt_wrapper_i_n_238),
        .gthe2_i_14(gt_wrapper_i_n_239),
        .gthe2_i_15(\rx_err_detect_simplex_gtp_i/p_2_out_5 ),
        .gthe2_i_16({gt_wrapper_i_n_244,gt_wrapper_i_n_245,gt_wrapper_i_n_246,gt_wrapper_i_n_247,gt_wrapper_i_n_248,gt_wrapper_i_n_249,gt_wrapper_i_n_250,gt_wrapper_i_n_251}),
        .gthe2_i_17({gt_wrapper_i_n_252,gt_wrapper_i_n_253,gt_wrapper_i_n_254,gt_wrapper_i_n_255,gt_wrapper_i_n_256,gt_wrapper_i_n_257,gt_wrapper_i_n_258,gt_wrapper_i_n_259}),
        .gthe2_i_18(gt_wrapper_i_n_260),
        .gthe2_i_19(\rx_err_detect_simplex_gtp_i/p_2_out_3 ),
        .gthe2_i_2(gt2_rx_realign_out),
        .gthe2_i_20({gt_wrapper_i_n_265,gt_wrapper_i_n_266,gt_wrapper_i_n_267,gt_wrapper_i_n_268,gt_wrapper_i_n_269,gt_wrapper_i_n_270,gt_wrapper_i_n_271,gt_wrapper_i_n_272}),
        .gthe2_i_21({gt_wrapper_i_n_273,gt_wrapper_i_n_274,gt_wrapper_i_n_275,gt_wrapper_i_n_276,gt_wrapper_i_n_277,gt_wrapper_i_n_278,gt_wrapper_i_n_279,gt_wrapper_i_n_280}),
        .gthe2_i_22(gt_wrapper_i_n_281),
        .gthe2_i_23(\rx_err_detect_simplex_gtp_i/p_2_out_1 ),
        .gthe2_i_24({gt_wrapper_i_n_286,gt_wrapper_i_n_287,gt_wrapper_i_n_288,gt_wrapper_i_n_289,gt_wrapper_i_n_290,gt_wrapper_i_n_291,gt_wrapper_i_n_292,gt_wrapper_i_n_293}),
        .gthe2_i_25({gt_wrapper_i_n_294,gt_wrapper_i_n_295,gt_wrapper_i_n_296,gt_wrapper_i_n_297,gt_wrapper_i_n_298,gt_wrapper_i_n_299,gt_wrapper_i_n_300,gt_wrapper_i_n_301}),
        .gthe2_i_26(gt_wrapper_i_n_302),
        .gthe2_i_27(\rx_err_detect_simplex_gtp_i/p_2_out ),
        .gthe2_i_28({gt_wrapper_i_n_307,gt_wrapper_i_n_308,gt_wrapper_i_n_309,gt_wrapper_i_n_310,gt_wrapper_i_n_311,gt_wrapper_i_n_312,gt_wrapper_i_n_313,gt_wrapper_i_n_314}),
        .gthe2_i_29({gt_wrapper_i_n_315,gt_wrapper_i_n_316,gt_wrapper_i_n_317,gt_wrapper_i_n_318,gt_wrapper_i_n_319,gt_wrapper_i_n_320,gt_wrapper_i_n_321,gt_wrapper_i_n_322}),
        .gthe2_i_3(rx_char_is_comma_i_4),
        .gthe2_i_4(gt3_rx_realign_out),
        .gthe2_i_5(rx_char_is_comma_i_6),
        .gthe2_i_6(gt_wrapper_i_n_231),
        .gthe2_i_7(gt_wrapper_i_n_232),
        .gthe2_i_8(gt_wrapper_i_n_233),
        .gthe2_i_9(gt_wrapper_i_n_234),
        .gtp_rx_reset_i_0(gtp_rx_reset_i_0),
        .gtp_rx_reset_i_1(gtp_rx_reset_i_1),
        .gtp_rx_reset_i_2(gtp_rx_reset_i_2),
        .gtp_rx_reset_i_3(gtp_rx_reset_i_3),
        .gtrxreset_i(gtrxreset_i),
        .hard_err_flop_r0(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0_4 ),
        .hard_err_flop_r0_0(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0_2 ),
        .hard_err_flop_r0_1(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0_0 ),
        .hard_err_flop_r0_2(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0 ),
        .init_clk_in(init_clk_in),
        .link_reset_r(link_reset_r),
        .out(gt_reset_sync_init_clk),
        .rx_polarity_i_0(rx_polarity_i_0),
        .rx_polarity_i_1(rx_polarity_i_1),
        .rx_polarity_i_2(rx_polarity_i_2),
        .rx_polarity_i_3(rx_polarity_i_3),
        .rxfsm_rxresetdone_r3_reg_0(gt_wrapper_i_n_323),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[1] (rx_aurora_lane_simplex_v5_0_i_n_14),
        .\word_aligned_control_bits_r_reg[1]_0 (rx_aurora_lane_simplex_v5_1_i_n_14),
        .\word_aligned_control_bits_r_reg[1]_1 (rx_aurora_lane_simplex_v5_2_i_n_14),
        .\word_aligned_control_bits_r_reg[1]_2 (rx_aurora_lane_simplex_v5_3_i_n_13));
  aurora_rx_4l_64b_cdc_sync_0 hpcnt_reset_cdc_sync
       (.RX_SYSTEM_RESET(RX_SYSTEM_RESET),
        .init_clk_in(init_clk_in),
        .out(reset_sync_init_clk));
  aurora_rx_4l_64b_LL_TO_AXI ll_to_axi_pdu_i
       (.M_AXI_RX_TKEEP(\^M_AXI_RX_TKEEP ),
        .RX_EOF_N(rx_eof),
        .RX_REM(rx_rem));
  aurora_rx_4l_64b_LL_TO_AXI__parameterized1 ll_to_axi_ufc_i
       (.M_AXI_UFC_RX_TKEEP({\^M_AXI_UFC_RX_TKEEP [7],\^M_AXI_UFC_RX_TKEEP [5],\^M_AXI_UFC_RX_TKEEP [3]}),
        .UFC_RX_EOF_N(rx_ufc_eof),
        .UFC_RX_REM({rx_ufc_rem[0],rx_ufc_rem[1]}));
  aurora_rx_4l_64b_cdc_sync_1 reset_sync_user_clk_cdc_sync
       (.RX_SYSTEM_RESET(RX_SYSTEM_RESET),
        .out(reset_sync_user_clk),
        .user_clk(user_clk));
  aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5 rx_aurora_lane_simplex_v5_0_i
       (.D(HARD_ERR),
        .GOT_A(GOT_A),
        .GOT_V(GOT_V),
        .HPCNT_RESET(HPCNT_RESET),
        .Q(rx_aurora_lane_simplex_v5_1_i_n_35),
        .\RX_CHAR_IS_COMMA_R_reg[1] (rx_char_is_comma_i_0),
        .RX_ECP_Buffer0(\sym_dec_i/RX_ECP_Buffer0 ),
        .RX_LANE_UP(RX_LANE_UP[0]),
        .RX_PE_DATA({RX_PE_DATA[8],RX_PE_DATA[9],RX_PE_DATA[10]}),
        .\RX_PE_DATA_Buffer_reg[10] (rx_aurora_lane_simplex_v5_0_i_n_17),
        .\RX_PE_DATA_Buffer_reg[8] (rx_aurora_lane_simplex_v5_0_i_n_19),
        .\RX_PE_DATA_Buffer_reg[8]_0 (rx_aurora_lane_simplex_v5_0_i_n_20),
        .RX_PE_DATA_V_Buffer_reg(RX_PE_DATA_V),
        .RX_SCP_Buffer_reg(RX_SCP),
        .RX_SUF(RX_SUF),
        .RX_SUF_Buffer_reg(rx_aurora_lane_simplex_v5_0_i_n_18),
        .RX_SUF_Buffer_reg_0(rx_aurora_lane_simplex_v5_0_i_n_21),
        .SR(RESET),
        .begin_r_reg(gt0_rx_realign_out),
        .bucket_full_r(\rx_err_detect_simplex_gtp_i/bucket_full_r ),
        .comma_over_two_cycles_r(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r ),
        .\counter2_r_reg[15] (RX_CHANNEL_UP),
        .ena_comma_align_i_0(ena_comma_align_i_0),
        .first_v_received_r(\sym_dec_i/first_v_received_r ),
        .good_as_r0(\rx_channel_init_sm_simplex_i/good_as_r0 ),
        .good_as_r_reg(rx_aurora_lane_simplex_v5_3_i_n_20),
        .good_as_r_reg_0(rx_aurora_lane_simplex_v5_2_i_n_34),
        .good_as_r_reg_1(rx_aurora_lane_simplex_v5_1_i_n_36),
        .good_as_r_reg_2(rx_aurora_lane_simplex_v5_2_i_n_33),
        .good_as_r_reg_3(rx_aurora_lane_simplex_v5_3_i_n_21),
        .gtp_rx_reset_i_0(gtp_rx_reset_i_0),
        .hard_err_flop_r0(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0_4 ),
        .init_clk_in(init_clk_in),
        .left_aligned_r_reg(rx_aurora_lane_simplex_v5_0_i_n_14),
        .left_aligned_r_reg_0(gt_wrapper_i_n_242),
        .link_reset_lane0_i(link_reset_lane0_i),
        .reset_count_r_reg(gt_wrapper_i_n_239),
        .rx_polarity_i_0(rx_polarity_i_0),
        .\soft_err_r_reg[0] (\rx_err_detect_simplex_gtp_i/p_2_out_5 ),
        .\stage_1_count_value_r_reg[1] (rx_aurora_lane_simplex_v5_2_i_n_8),
        .\stage_1_count_value_r_reg[2] (rx_aurora_lane_simplex_v5_2_i_n_12),
        .\stage_1_lane_mask_r_reg[2] (rx_aurora_lane_simplex_v5_1_i_n_12),
        .\stage_1_lane_mask_r_reg[3] (rx_aurora_lane_simplex_v5_1_i_n_17),
        .start_rx_i(start_rx_i),
        .std_bool26_out(\sym_dec_i/std_bool26_out ),
        .user_clk(user_clk),
        .user_clk_0(rx_aurora_lane_simplex_v5_0_i_n_16),
        .\word_aligned_control_bits_r_reg[0] (gt_wrapper_i_n_232),
        .\word_aligned_control_bits_r_reg[1] (gt_wrapper_i_n_231),
        .\word_aligned_data_r_reg[0] ({rx_aurora_lane_simplex_v5_0_i_n_30,rx_aurora_lane_simplex_v5_0_i_n_31,rx_aurora_lane_simplex_v5_0_i_n_32,rx_aurora_lane_simplex_v5_0_i_n_33,rx_aurora_lane_simplex_v5_0_i_n_34,rx_aurora_lane_simplex_v5_0_i_n_35,rx_aurora_lane_simplex_v5_0_i_n_36,rx_aurora_lane_simplex_v5_0_i_n_37}),
        .\word_aligned_data_r_reg[0]_0 ({gt_wrapper_i_n_252,gt_wrapper_i_n_253,gt_wrapper_i_n_254,gt_wrapper_i_n_255,gt_wrapper_i_n_256,gt_wrapper_i_n_257,gt_wrapper_i_n_258,gt_wrapper_i_n_259}),
        .\word_aligned_data_r_reg[11] ({\sym_dec_i/p_0_in ,rx_aurora_lane_simplex_v5_0_i_n_26,rx_aurora_lane_simplex_v5_0_i_n_27,rx_aurora_lane_simplex_v5_0_i_n_28,rx_aurora_lane_simplex_v5_0_i_n_29}),
        .\word_aligned_data_r_reg[8] ({gt_wrapper_i_n_244,gt_wrapper_i_n_245,gt_wrapper_i_n_246,gt_wrapper_i_n_247,gt_wrapper_i_n_248,gt_wrapper_i_n_249,gt_wrapper_i_n_250,gt_wrapper_i_n_251}));
  aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_2 rx_aurora_lane_simplex_v5_1_i
       (.D(rx_aurora_lane_simplex_v5_1_i_n_6),
        .\GOT_A_Buffer_reg[0] (rx_aurora_lane_simplex_v5_1_i_n_36),
        .\GOT_A_Buffer_reg[1] (rx_aurora_lane_simplex_v5_1_i_n_35),
        .GOT_V_Buffer_reg(rx_aurora_lane_simplex_v5_1_i_n_4),
        .HPCNT_RESET(HPCNT_RESET),
        .Q({\sym_dec_i/p_0_in_9 ,rx_aurora_lane_simplex_v5_1_i_n_22,rx_aurora_lane_simplex_v5_1_i_n_23,rx_aurora_lane_simplex_v5_1_i_n_24,rx_aurora_lane_simplex_v5_1_i_n_25}),
        .\RX_CHAR_IS_COMMA_R_reg[1] (rx_char_is_comma_i_2),
        .RX_ECP_Buffer0(\sym_dec_i/RX_ECP_Buffer0_6 ),
        .RX_LANE_UP(RX_LANE_UP[1]),
        .\RX_PE_DATA_Buffer_reg[10] (rx_aurora_lane_simplex_v5_1_i_n_10),
        .\RX_PE_DATA_Buffer_reg[10]_0 (rx_aurora_lane_simplex_v5_1_i_n_17),
        .\RX_PE_DATA_Buffer_reg[10]_1 (rx_aurora_lane_simplex_v5_1_i_n_19),
        .\RX_PE_DATA_Buffer_reg[10]_2 (rx_aurora_lane_simplex_v5_1_i_n_20),
        .\RX_PE_DATA_Buffer_reg[8] (rx_aurora_lane_simplex_v5_1_i_n_9),
        .\RX_PE_DATA_Buffer_reg[9] (rx_aurora_lane_simplex_v5_1_i_n_8),
        .RX_PE_DATA_V_Buffer_reg(rx_aurora_lane_simplex_v5_1_i_n_15),
        .RX_SCP_Buffer_reg(rx_aurora_lane_simplex_v5_1_i_n_11),
        .RX_SUF(RX_SUF),
        .RX_SUF_Buffer_reg(rx_aurora_lane_simplex_v5_1_i_n_12),
        .RX_SUF_Buffer_reg_0(rx_aurora_lane_simplex_v5_1_i_n_18),
        .SR(rx_global_logic_simplex_i_n_1),
        .begin_r_reg(gt1_rx_realign_out),
        .bucket_full_r(\rx_err_detect_simplex_gtp_i/bucket_full_r_10 ),
        .comma_over_two_cycles_r(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_11 ),
        .\counter2_r_reg[15] (RX_CHANNEL_UP),
        .ena_comma_align_i_1(ena_comma_align_i_1),
        .first_v_received_r(\sym_dec_i/first_v_received_r_8 ),
        .gtp_rx_reset_i_1(gtp_rx_reset_i_1),
        .hard_err_flop_r0(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0_2 ),
        .init_clk_in(init_clk_in),
        .left_aligned_r_reg(rx_aurora_lane_simplex_v5_1_i_n_14),
        .left_aligned_r_reg_0(gt_wrapper_i_n_263),
        .link_reset_lane1_i(link_reset_lane1_i),
        .reset_count_r_reg(gt_wrapper_i_n_260),
        .rx_polarity_i_1(rx_polarity_i_1),
        .\soft_err_r_reg[0] (\rx_err_detect_simplex_gtp_i/p_2_out_3 ),
        .\stage_1_count_value_r_reg[1] (rx_aurora_lane_simplex_v5_2_i_n_12),
        .\stage_1_count_value_r_reg[2] (rx_aurora_lane_simplex_v5_2_i_n_10),
        .std_bool26_out(\sym_dec_i/std_bool26_out_7 ),
        .user_clk(user_clk),
        .user_clk_0(rx_aurora_lane_simplex_v5_1_i_n_16),
        .\word_aligned_control_bits_r_reg[0] (gt_wrapper_i_n_234),
        .\word_aligned_control_bits_r_reg[1] (gt_wrapper_i_n_233),
        .\word_aligned_data_r_reg[0] ({rx_aurora_lane_simplex_v5_1_i_n_26,rx_aurora_lane_simplex_v5_1_i_n_27,rx_aurora_lane_simplex_v5_1_i_n_28,rx_aurora_lane_simplex_v5_1_i_n_29,rx_aurora_lane_simplex_v5_1_i_n_30,rx_aurora_lane_simplex_v5_1_i_n_31,rx_aurora_lane_simplex_v5_1_i_n_32,rx_aurora_lane_simplex_v5_1_i_n_33}),
        .\word_aligned_data_r_reg[0]_0 ({gt_wrapper_i_n_273,gt_wrapper_i_n_274,gt_wrapper_i_n_275,gt_wrapper_i_n_276,gt_wrapper_i_n_277,gt_wrapper_i_n_278,gt_wrapper_i_n_279,gt_wrapper_i_n_280}),
        .\word_aligned_data_r_reg[8] ({gt_wrapper_i_n_265,gt_wrapper_i_n_266,gt_wrapper_i_n_267,gt_wrapper_i_n_268,gt_wrapper_i_n_269,gt_wrapper_i_n_270,gt_wrapper_i_n_271,gt_wrapper_i_n_272}));
  aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_3 rx_aurora_lane_simplex_v5_2_i
       (.D(rx_aurora_lane_simplex_v5_2_i_n_6),
        .\GOT_A_Buffer_reg[0] (rx_aurora_lane_simplex_v5_2_i_n_34),
        .\GOT_A_Buffer_reg[1] (rx_aurora_lane_simplex_v5_2_i_n_33),
        .GOT_V_Buffer_reg(rx_aurora_lane_simplex_v5_2_i_n_4),
        .HPCNT_RESET(HPCNT_RESET),
        .Q({\sym_dec_i/p_0_in_15 ,rx_aurora_lane_simplex_v5_2_i_n_20,rx_aurora_lane_simplex_v5_2_i_n_21,rx_aurora_lane_simplex_v5_2_i_n_22,rx_aurora_lane_simplex_v5_2_i_n_23}),
        .\RX_CHAR_IS_COMMA_R_reg[1] (rx_char_is_comma_i_4),
        .RX_ECP_Buffer0(\sym_dec_i/RX_ECP_Buffer0_12 ),
        .RX_LANE_UP(RX_LANE_UP[2]),
        .\RX_PE_DATA_Buffer_reg[10] (rx_aurora_lane_simplex_v5_2_i_n_9),
        .\RX_PE_DATA_Buffer_reg[8] (rx_aurora_lane_simplex_v5_2_i_n_8),
        .\RX_PE_DATA_Buffer_reg[9] (rx_aurora_lane_simplex_v5_2_i_n_10),
        .RX_PE_DATA_V_Buffer_reg(rx_aurora_lane_simplex_v5_2_i_n_15),
        .RX_SCP_Buffer_reg(rx_aurora_lane_simplex_v5_2_i_n_11),
        .RX_SUF_Buffer_reg(rx_aurora_lane_simplex_v5_2_i_n_12),
        .RX_SUF_Buffer_reg_0(rx_aurora_lane_simplex_v5_2_i_n_18),
        .SR(rx_global_logic_simplex_i_n_2),
        .begin_r_reg(gt2_rx_realign_out),
        .bucket_full_r(\rx_err_detect_simplex_gtp_i/bucket_full_r_16 ),
        .comma_over_two_cycles_r(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_17 ),
        .\counter2_r_reg[15] (RX_CHANNEL_UP),
        .ena_comma_align_i_2(ena_comma_align_i_2),
        .first_v_received_r(\sym_dec_i/first_v_received_r_14 ),
        .gtp_rx_reset_i_2(gtp_rx_reset_i_2),
        .hard_err_flop_r0(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0_0 ),
        .init_clk_in(init_clk_in),
        .left_aligned_r_reg(rx_aurora_lane_simplex_v5_2_i_n_14),
        .left_aligned_r_reg_0(gt_wrapper_i_n_284),
        .link_reset_lane2_i(link_reset_lane2_i),
        .load_ufc_control_code_r_reg({RX_SUF,rx_aurora_lane_simplex_v5_1_i_n_12,rx_aurora_lane_simplex_v5_3_i_n_11}),
        .neqOp(\ufc_filter_i/neqOp ),
        .reset_count_r_reg(gt_wrapper_i_n_281),
        .rx_polarity_i_2(rx_polarity_i_2),
        .\soft_err_r_reg[0] (\rx_err_detect_simplex_gtp_i/p_2_out_1 ),
        .\stage_1_count_value_r_reg[3] (rx_aurora_lane_simplex_v5_0_i_n_20),
        .\stage_1_count_value_r_reg[3]_0 (rx_aurora_lane_simplex_v5_1_i_n_20),
        .\stage_1_count_value_r_reg[3]_1 (rx_aurora_lane_simplex_v5_3_i_n_9),
        .std_bool26_out(\sym_dec_i/std_bool26_out_13 ),
        .user_clk(user_clk),
        .user_clk_0(rx_aurora_lane_simplex_v5_2_i_n_16),
        .\word_aligned_control_bits_r_reg[0] (gt_wrapper_i_n_236),
        .\word_aligned_control_bits_r_reg[1] (gt_wrapper_i_n_235),
        .\word_aligned_data_r_reg[0] ({rx_aurora_lane_simplex_v5_2_i_n_24,rx_aurora_lane_simplex_v5_2_i_n_25,rx_aurora_lane_simplex_v5_2_i_n_26,rx_aurora_lane_simplex_v5_2_i_n_27,rx_aurora_lane_simplex_v5_2_i_n_28,rx_aurora_lane_simplex_v5_2_i_n_29,rx_aurora_lane_simplex_v5_2_i_n_30,rx_aurora_lane_simplex_v5_2_i_n_31}),
        .\word_aligned_data_r_reg[0]_0 ({gt_wrapper_i_n_294,gt_wrapper_i_n_295,gt_wrapper_i_n_296,gt_wrapper_i_n_297,gt_wrapper_i_n_298,gt_wrapper_i_n_299,gt_wrapper_i_n_300,gt_wrapper_i_n_301}),
        .\word_aligned_data_r_reg[8] ({gt_wrapper_i_n_286,gt_wrapper_i_n_287,gt_wrapper_i_n_288,gt_wrapper_i_n_289,gt_wrapper_i_n_290,gt_wrapper_i_n_291,gt_wrapper_i_n_292,gt_wrapper_i_n_293}));
  aurora_rx_4l_64b_RX_AURORA_LANE_SIMPLEX_V5_4 rx_aurora_lane_simplex_v5_3_i
       (.D(rx_aurora_lane_simplex_v5_3_i_n_6),
        .GOT_A(GOT_A),
        .\GOT_A_Buffer_reg[0] (rx_aurora_lane_simplex_v5_3_i_n_20),
        .GOT_V_Buffer_reg(rx_aurora_lane_simplex_v5_3_i_n_4),
        .HPCNT_RESET(HPCNT_RESET),
        .LINK_RESET_OUT(LINK_RESET_OUT),
        .Q(rx_aurora_lane_simplex_v5_3_i_n_21),
        .\RX_CHAR_IS_COMMA_R_reg[1] (rx_char_is_comma_i_6),
        .RX_ECP_Buffer0(\sym_dec_i/RX_ECP_Buffer0_18 ),
        .RX_LANE_UP(RX_LANE_UP[3]),
        .RX_PE_DATA(RX_PE_DATA[9]),
        .\RX_PE_DATA_Buffer_reg[10] (rx_aurora_lane_simplex_v5_3_i_n_9),
        .\RX_PE_DATA_Buffer_reg[8] (rx_aurora_lane_simplex_v5_3_i_n_8),
        .\RX_PE_DATA_Buffer_reg[9] (rx_aurora_lane_simplex_v5_3_i_n_7),
        .\RX_PE_DATA_Buffer_reg[9]_0 (rx_aurora_lane_simplex_v5_3_i_n_17),
        .\RX_PE_DATA_Buffer_reg[9]_1 (rx_aurora_lane_simplex_v5_3_i_n_22),
        .RX_PE_DATA_V_Buffer_reg(rx_aurora_lane_simplex_v5_3_i_n_14),
        .RX_SCP_Buffer_reg(rx_aurora_lane_simplex_v5_3_i_n_10),
        .RX_SUF_Buffer_reg(rx_aurora_lane_simplex_v5_3_i_n_11),
        .RX_SUF_Buffer_reg_0(rx_aurora_lane_simplex_v5_3_i_n_16),
        .SR(rx_global_logic_simplex_i_n_3),
        .bad_as_r0(\rx_channel_init_sm_simplex_i/bad_as_r0 ),
        .bad_as_r_reg(rx_aurora_lane_simplex_v5_1_i_n_36),
        .bad_as_r_reg_0(rx_aurora_lane_simplex_v5_2_i_n_34),
        .bad_as_r_reg_1(rx_aurora_lane_simplex_v5_2_i_n_33),
        .bad_as_r_reg_2(rx_aurora_lane_simplex_v5_1_i_n_35),
        .begin_r_reg(gt3_rx_realign_out),
        .bucket_full_r(\rx_err_detect_simplex_gtp_i/bucket_full_r_22 ),
        .comma_over_two_cycles_r(\rx_lane_init_sm_simplex_i/comma_over_two_cycles_r_23 ),
        .\counter2_r_reg[15] (RX_CHANNEL_UP),
        .ena_comma_align_i_3(ena_comma_align_i_3),
        .first_v_received_r(\sym_dec_i/first_v_received_r_20 ),
        .gtp_rx_reset_i_3(gtp_rx_reset_i_3),
        .hard_err_flop_r0(\rx_err_detect_simplex_gtp_i/hard_err_flop_r0 ),
        .init_clk_in(init_clk_in),
        .left_aligned_r_reg(rx_aurora_lane_simplex_v5_3_i_n_13),
        .left_aligned_r_reg_0(gt_wrapper_i_n_305),
        .link_reset_lane0_i(link_reset_lane0_i),
        .link_reset_lane1_i(link_reset_lane1_i),
        .link_reset_lane2_i(link_reset_lane2_i),
        .reset_count_r_reg(gt_wrapper_i_n_302),
        .rx_polarity_i_3(rx_polarity_i_3),
        .\soft_err_r_reg[0] (\rx_err_detect_simplex_gtp_i/p_2_out ),
        .\stage_1_count_value_r_reg[1] (rx_aurora_lane_simplex_v5_0_i_n_18),
        .\stage_1_count_value_r_reg[1]_0 (rx_aurora_lane_simplex_v5_1_i_n_19),
        .\stage_1_count_value_r_reg[2] (rx_aurora_lane_simplex_v5_1_i_n_18),
        .\stage_1_count_value_r_reg[2]_0 (rx_aurora_lane_simplex_v5_0_i_n_21),
        .std_bool26_out(\sym_dec_i/std_bool26_out_19 ),
        .user_clk(user_clk),
        .user_clk_0(rx_aurora_lane_simplex_v5_3_i_n_15),
        .\word_aligned_control_bits_r_reg[0] (gt_wrapper_i_n_238),
        .\word_aligned_control_bits_r_reg[1] (gt_wrapper_i_n_237),
        .\word_aligned_data_r_reg[0] ({rx_aurora_lane_simplex_v5_3_i_n_28,rx_aurora_lane_simplex_v5_3_i_n_29,rx_aurora_lane_simplex_v5_3_i_n_30,rx_aurora_lane_simplex_v5_3_i_n_31,rx_aurora_lane_simplex_v5_3_i_n_32,rx_aurora_lane_simplex_v5_3_i_n_33,rx_aurora_lane_simplex_v5_3_i_n_34,rx_aurora_lane_simplex_v5_3_i_n_35}),
        .\word_aligned_data_r_reg[0]_0 ({gt_wrapper_i_n_315,gt_wrapper_i_n_316,gt_wrapper_i_n_317,gt_wrapper_i_n_318,gt_wrapper_i_n_319,gt_wrapper_i_n_320,gt_wrapper_i_n_321,gt_wrapper_i_n_322}),
        .\word_aligned_data_r_reg[11] ({\sym_dec_i/p_0_in_21 ,rx_aurora_lane_simplex_v5_3_i_n_24,rx_aurora_lane_simplex_v5_3_i_n_25,rx_aurora_lane_simplex_v5_3_i_n_26,rx_aurora_lane_simplex_v5_3_i_n_27}),
        .\word_aligned_data_r_reg[8] ({gt_wrapper_i_n_307,gt_wrapper_i_n_308,gt_wrapper_i_n_309,gt_wrapper_i_n_310,gt_wrapper_i_n_311,gt_wrapper_i_n_312,gt_wrapper_i_n_313,gt_wrapper_i_n_314}));
  aurora_rx_4l_64b_RX_GLOBAL_LOGIC_SIMPLEX rx_global_logic_simplex_i
       (.CHANNEL_UP_Buffer_reg(RX_CHANNEL_UP),
        .CHBONDDONE_OUT(CHBONDDONE_OUT),
        .CHBONDDONE_OUT_LANE1(CHBONDDONE_OUT_LANE1),
        .CHBONDDONE_OUT_LANE2(CHBONDDONE_OUT_LANE2),
        .CHBONDDONE_OUT_LANE3(CHBONDDONE_OUT_LANE3),
        .D({rx_global_logic_simplex_i_n_10,\rx_channel_init_sm_simplex_i/p_0_in10_in ,\rx_channel_init_sm_simplex_i/p_1_in11_in ,rx_global_logic_simplex_i_n_13}),
        .GOT_V(GOT_V),
        .POWER_DOWN(POWER_DOWN),
        .Q({\ch_bond_load_pulse_i_reg_n_0_[0] ,\ch_bond_load_pulse_i_reg_n_0_[1] ,\ch_bond_load_pulse_i_reg_n_0_[2] ,\ch_bond_load_pulse_i_reg_n_0_[3] }),
        .RESET(RESET_24),
        .RX_HARD_ERR(RX_HARD_ERR),
        .RX_LANE_UP(RX_LANE_UP),
        .RX_SUF(RX_SUF),
        .SOFT_ERR(SOFT_ERR),
        .SR(RESET),
        .START_RX_Buffer_reg(rx_global_logic_simplex_i_n_14),
        .START_RX_Buffer_reg_0(sys_reset_out),
        .all_lanes_v_r_reg(rx_aurora_lane_simplex_v5_1_i_n_4),
        .all_lanes_v_r_reg_0(rx_aurora_lane_simplex_v5_2_i_n_4),
        .all_lanes_v_r_reg_1(rx_aurora_lane_simplex_v5_3_i_n_4),
        .bad_as_r0(\rx_channel_init_sm_simplex_i/bad_as_r0 ),
        .en_chan_sync_i(en_chan_sync_i),
        .good_as_r0(\rx_channel_init_sm_simplex_i/good_as_r0 ),
        .gtrxreset_i(gtrxreset_i),
        .\hard_err_r_reg[0] ({HARD_ERR,rx_aurora_lane_simplex_v5_1_i_n_6,rx_aurora_lane_simplex_v5_2_i_n_6,rx_aurora_lane_simplex_v5_3_i_n_6}),
        .reset_lanes_flop_1_i(rx_global_logic_simplex_i_n_1),
        .reset_lanes_flop_2_i(rx_global_logic_simplex_i_n_2),
        .reset_lanes_flop_3_i(rx_global_logic_simplex_i_n_3),
        .\soft_err_r_reg[0] (rx_aurora_lane_simplex_v5_0_i_n_16),
        .\soft_err_r_reg[1] (rx_aurora_lane_simplex_v5_1_i_n_16),
        .\soft_err_r_reg[2] (rx_aurora_lane_simplex_v5_2_i_n_16),
        .\soft_err_r_reg[3] (rx_aurora_lane_simplex_v5_3_i_n_15),
        .start_rx_i(start_rx_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_RX_LL rx_ll_i
       (.D({RX_PE_DATA_V,rx_aurora_lane_simplex_v5_1_i_n_15,rx_aurora_lane_simplex_v5_2_i_n_15,rx_aurora_lane_simplex_v5_3_i_n_14}),
        .FRAME_ERR(FRAME_ERR),
        .M_AXI_RX_TDATA(M_AXI_RX_TDATA),
        .M_AXI_RX_TLAST(M_AXI_RX_TLAST),
        .M_AXI_RX_TVALID(M_AXI_RX_TVALID),
        .M_AXI_UFC_RX_TDATA(M_AXI_UFC_RX_TDATA),
        .M_AXI_UFC_RX_TLAST(M_AXI_UFC_RX_TLAST),
        .M_AXI_UFC_RX_TVALID(M_AXI_UFC_RX_TVALID),
        .Q({\sym_dec_i/p_0_in_9 ,rx_aurora_lane_simplex_v5_1_i_n_22,rx_aurora_lane_simplex_v5_1_i_n_23,rx_aurora_lane_simplex_v5_1_i_n_24,rx_aurora_lane_simplex_v5_1_i_n_25}),
        .RESET(RESET_24),
        .RX_ECP_Buffer0(\sym_dec_i/RX_ECP_Buffer0 ),
        .RX_ECP_Buffer0_3(\sym_dec_i/RX_ECP_Buffer0_6 ),
        .RX_ECP_Buffer0_4(\sym_dec_i/RX_ECP_Buffer0_12 ),
        .RX_ECP_Buffer0_5(\sym_dec_i/RX_ECP_Buffer0_18 ),
        .RX_EOF_N(rx_eof),
        .RX_PE_DATA({RX_PE_DATA[8],RX_PE_DATA[9],RX_PE_DATA[10]}),
        .\RX_REM_Buffer_reg[0] ({rx_rem[0],rx_rem[1],rx_rem[2]}),
        .UFC_RX_EOF_N(rx_ufc_eof),
        .\UFC_RX_REM_Buffer_reg[0] ({rx_ufc_rem[0],rx_ufc_rem[1]}),
        .neqOp(\ufc_filter_i/neqOp ),
        .\rx_scp_r_reg[0] ({RX_SCP,rx_aurora_lane_simplex_v5_1_i_n_11,rx_aurora_lane_simplex_v5_2_i_n_11,rx_aurora_lane_simplex_v5_3_i_n_10}),
        .\rx_suf_r_reg[0] ({RX_SUF,rx_aurora_lane_simplex_v5_1_i_n_12,rx_aurora_lane_simplex_v5_3_i_n_11}),
        .\rx_suf_r_reg[2] (rx_aurora_lane_simplex_v5_2_i_n_12),
        .\stage_1_count_value_r_reg[0] (rx_aurora_lane_simplex_v5_3_i_n_22),
        .\stage_1_count_value_r_reg[1] (rx_aurora_lane_simplex_v5_3_i_n_16),
        .\stage_1_count_value_r_reg[2] (rx_aurora_lane_simplex_v5_3_i_n_17),
        .\stage_1_count_value_r_reg[3] (rx_aurora_lane_simplex_v5_2_i_n_18),
        .\stage_1_data_r_reg[0] ({rx_aurora_lane_simplex_v5_0_i_n_30,rx_aurora_lane_simplex_v5_0_i_n_31,rx_aurora_lane_simplex_v5_0_i_n_32,rx_aurora_lane_simplex_v5_0_i_n_33,rx_aurora_lane_simplex_v5_0_i_n_34,rx_aurora_lane_simplex_v5_0_i_n_35,rx_aurora_lane_simplex_v5_0_i_n_36,rx_aurora_lane_simplex_v5_0_i_n_37}),
        .\stage_1_data_r_reg[11] ({\sym_dec_i/p_0_in ,rx_aurora_lane_simplex_v5_0_i_n_26,rx_aurora_lane_simplex_v5_0_i_n_27,rx_aurora_lane_simplex_v5_0_i_n_28,rx_aurora_lane_simplex_v5_0_i_n_29}),
        .\stage_1_data_r_reg[16] ({rx_aurora_lane_simplex_v5_1_i_n_26,rx_aurora_lane_simplex_v5_1_i_n_27,rx_aurora_lane_simplex_v5_1_i_n_28,rx_aurora_lane_simplex_v5_1_i_n_29,rx_aurora_lane_simplex_v5_1_i_n_30,rx_aurora_lane_simplex_v5_1_i_n_31,rx_aurora_lane_simplex_v5_1_i_n_32,rx_aurora_lane_simplex_v5_1_i_n_33}),
        .\stage_1_data_r_reg[24] (rx_aurora_lane_simplex_v5_1_i_n_9),
        .\stage_1_data_r_reg[25] (rx_aurora_lane_simplex_v5_1_i_n_8),
        .\stage_1_data_r_reg[26] (rx_aurora_lane_simplex_v5_1_i_n_10),
        .\stage_1_data_r_reg[32] ({rx_aurora_lane_simplex_v5_2_i_n_24,rx_aurora_lane_simplex_v5_2_i_n_25,rx_aurora_lane_simplex_v5_2_i_n_26,rx_aurora_lane_simplex_v5_2_i_n_27,rx_aurora_lane_simplex_v5_2_i_n_28,rx_aurora_lane_simplex_v5_2_i_n_29,rx_aurora_lane_simplex_v5_2_i_n_30,rx_aurora_lane_simplex_v5_2_i_n_31}),
        .\stage_1_data_r_reg[40] (rx_aurora_lane_simplex_v5_2_i_n_8),
        .\stage_1_data_r_reg[41] (rx_aurora_lane_simplex_v5_2_i_n_10),
        .\stage_1_data_r_reg[42] (rx_aurora_lane_simplex_v5_2_i_n_9),
        .\stage_1_data_r_reg[43] ({\sym_dec_i/p_0_in_15 ,rx_aurora_lane_simplex_v5_2_i_n_20,rx_aurora_lane_simplex_v5_2_i_n_21,rx_aurora_lane_simplex_v5_2_i_n_22,rx_aurora_lane_simplex_v5_2_i_n_23}),
        .\stage_1_data_r_reg[48] ({rx_aurora_lane_simplex_v5_3_i_n_28,rx_aurora_lane_simplex_v5_3_i_n_29,rx_aurora_lane_simplex_v5_3_i_n_30,rx_aurora_lane_simplex_v5_3_i_n_31,rx_aurora_lane_simplex_v5_3_i_n_32,rx_aurora_lane_simplex_v5_3_i_n_33,rx_aurora_lane_simplex_v5_3_i_n_34,rx_aurora_lane_simplex_v5_3_i_n_35}),
        .\stage_1_data_r_reg[56] (rx_aurora_lane_simplex_v5_3_i_n_8),
        .\stage_1_data_r_reg[57] (rx_aurora_lane_simplex_v5_3_i_n_7),
        .\stage_1_data_r_reg[58] (rx_aurora_lane_simplex_v5_3_i_n_9),
        .\stage_1_data_r_reg[59] ({\sym_dec_i/p_0_in_21 ,rx_aurora_lane_simplex_v5_3_i_n_24,rx_aurora_lane_simplex_v5_3_i_n_25,rx_aurora_lane_simplex_v5_3_i_n_26,rx_aurora_lane_simplex_v5_3_i_n_27}),
        .\stage_1_lane_mask_r_reg[1] (rx_global_logic_simplex_i_n_14),
        .\stage_1_lane_mask_r_reg[2] (rx_aurora_lane_simplex_v5_0_i_n_17),
        .\stage_1_lane_mask_r_reg[3] (rx_aurora_lane_simplex_v5_0_i_n_19),
        .start_rx_i(start_rx_i),
        .std_bool26_out(\sym_dec_i/std_bool26_out ),
        .std_bool26_out_0(\sym_dec_i/std_bool26_out_7 ),
        .std_bool26_out_1(\sym_dec_i/std_bool26_out_13 ),
        .std_bool26_out_2(\sym_dec_i/std_bool26_out_19 ),
        .user_clk(user_clk));
endmodule

module aurora_rx_4l_64b_gt
   (gt0_cplllock_out,
    DRPRDY_OUT,
    gt0_eyescandataerror_out,
    gt0_rxbyteisaligned_out,
    gthe2_i_0,
    CHBONDDONE_OUT,
    gt0_rxcommadet_out,
    gt0_rxpmaresetdone_out,
    gt0_rxprbserr_out,
    gt0_rxresetdone_out,
    gt0_dmonitorout_out,
    DRPDO_OUT,
    gt0_rxbufstatus_out,
    gt0_rxmonitorout_out,
    D,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    gthe2_i_1,
    gthe2_i_2,
    gthe2_i_3,
    gthe2_i_4,
    first_v_received_r_reg,
    hard_err_flop_r0,
    gthe2_i_5,
    gthe2_i_6,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt0_eyescanreset_in,
    gt0_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    SR,
    fsm_gt_rx_reset_t,
    gt_qpllclk_quad2_in,
    gt_qpllrefclk_quad2_in,
    gt0_rxbufreset_in,
    gt0_rxcdrhold_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxlpmen_in,
    ena_comma_align_i_0,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    rx_polarity_i_0,
    gt0_rxprbscntreset_in,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    DRPDI_IN,
    gt0_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt0_rxprbssel_in,
    RXCHBONDO,
    DRPADDR_IN,
    flag2_reg_0,
    \word_aligned_control_bits_r_reg[1] ,
    gtp_rx_reset_i_0,
    comma_over_two_cycles_r,
    first_v_received_r,
    bucket_full_r,
    cpll_reset_i);
  output gt0_cplllock_out;
  output DRPRDY_OUT;
  output gt0_eyescandataerror_out;
  output gt0_rxbyteisaligned_out;
  output gthe2_i_0;
  output CHBONDDONE_OUT;
  output gt0_rxcommadet_out;
  output gt0_rxpmaresetdone_out;
  output gt0_rxprbserr_out;
  output gt0_rxresetdone_out;
  output [14:0]gt0_dmonitorout_out;
  output [15:0]DRPDO_OUT;
  output [2:0]gt0_rxbufstatus_out;
  output [6:0]gt0_rxmonitorout_out;
  output [1:0]D;
  output [1:0]gt0_rx_disp_err_out;
  output [1:0]gt0_rx_not_in_table_out;
  output gthe2_i_1;
  output gthe2_i_2;
  output gthe2_i_3;
  output [1:0]gthe2_i_4;
  output first_v_received_r_reg;
  output hard_err_flop_r0;
  output [7:0]gthe2_i_5;
  output [7:0]gthe2_i_6;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt0_eyescanreset_in;
  input gt0_eyescantrigger_in;
  input [0:0]RXN;
  input [0:0]RXP;
  input gt_refclk1;
  input [0:0]SR;
  input fsm_gt_rx_reset_t;
  input gt_qpllclk_quad2_in;
  input gt_qpllrefclk_quad2_in;
  input gt0_rxbufreset_in;
  input gt0_rxcdrhold_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  input gt0_rxlpmen_in;
  input ena_comma_align_i_0;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  input rx_polarity_i_0;
  input gt0_rxprbscntreset_in;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN;
  input [1:0]gt0_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_rxprbssel_in;
  input [4:0]RXCHBONDO;
  input [8:0]DRPADDR_IN;
  input flag2_reg_0;
  input \word_aligned_control_bits_r_reg[1] ;
  input gtp_rx_reset_i_0;
  input comma_over_two_cycles_r;
  input first_v_received_r;
  input bucket_full_r;
  input cpll_reset_i;

  wire CHBONDDONE_OUT;
  wire CPLLPD;
  wire CPLLRESET;
  wire [1:0]D;
  wire [8:0]DRPADDR_IN;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDO_OUT;
  wire DRPEN_IN;
  wire DRPRDY_OUT;
  wire DRPWE_IN;
  wire D_0;
  wire GT0_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [0:0]RXN;
  wire [0:0]RXP;
  wire [0:0]SR;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire bucket_full_r;
  wire comma_over_two_cycles_r;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire ena_comma_align_i_0;
  wire first_v_received_r;
  wire first_v_received_r_reg;
  wire flag2;
  wire flag2_i_2_n_0;
  wire flag2_reg_0;
  wire flag_i_1_n_0;
  wire fsm_gt_rx_reset_t;
  wire gt0_cplllock_out;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire [1:0]gt0_rx_disp_err_out;
  wire [1:0]gt0_rx_not_in_table_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt_qpllclk_quad2_in;
  wire gt_qpllrefclk_quad2_in;
  wire gt_refclk1;
  wire gt_rxuserrdy_i;
  wire gthe2_i_0;
  wire gthe2_i_1;
  wire gthe2_i_2;
  wire gthe2_i_3;
  wire [1:0]gthe2_i_4;
  wire [7:0]gthe2_i_5;
  wire [7:0]gthe2_i_6;
  wire gthe2_i_n_0;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_112;
  wire gthe2_i_n_113;
  wire gthe2_i_n_12;
  wire gthe2_i_n_120;
  wire gthe2_i_n_121;
  wire gthe2_i_n_122;
  wire gthe2_i_n_123;
  wire gthe2_i_n_124;
  wire gthe2_i_n_13;
  wire gthe2_i_n_15;
  wire gthe2_i_n_29;
  wire gthe2_i_n_45;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_5;
  wire gthe2_i_n_54;
  wire gthe2_i_n_6;
  wire gtp_rx_reset_i_0;
  wire hard_err_flop_r0;
  wire init_clk_in;
  wire [1:0]rx_char_is_k_i_0;
  wire [15:0]rx_data_i_0;
  wire rx_polarity_i_0;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt0_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D_0),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_2
       (.I0(ack_flag),
        .O(flag2_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_2_n_0),
        .Q(flag2),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D_0),
        .O(flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1_n_0),
        .Q(D_0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt0_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT0_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT(gt0_dmonitorout_out),
        .DRPADDR(DRPADDR_IN),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN),
        .DRPDO(DRPDO_OUT),
        .DRPEN(DRPEN_IN),
        .DRPRDY(DRPRDY_OUT),
        .DRPWE(DRPWE_IN),
        .EYESCANDATAERROR(gt0_eyescandataerror_out),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(gt0_eyescanreset_in),
        .EYESCANTRIGGER(gt0_eyescantrigger_in),
        .GTGREFCLK(1'b0),
        .GTHRXN(RXN),
        .GTHRXP(RXP),
        .GTHTXN(gthe2_i_n_5),
        .GTHTXP(gthe2_i_n_6),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(SR),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(fsm_gt_rx_reset_t),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad2_in),
        .QPLLREFCLK(gt_qpllrefclk_quad2_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(gt0_rxbufreset_in),
        .RXBUFSTATUS(gt0_rxbufstatus_out),
        .RXBYTEISALIGNED(gt0_rxbyteisaligned_out),
        .RXBYTEREALIGN(gthe2_i_0),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(gt0_rxcdrhold_in),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(gt0_rxcdrovrden_in),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(CHBONDDONE_OUT),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],D}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],rx_char_is_k_i_0}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b1}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({gthe2_i_n_120,gthe2_i_n_121,gthe2_i_n_122,gthe2_i_n_123,gthe2_i_n_124}),
        .RXCHBONDSLAVE(1'b1),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gt0_rxcommadet_out),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],rx_data_i_0}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(1'b0),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(gt0_rxdfelpmreset_in),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gt0_rx_disp_err_out}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(gt0_rxlpmen_in),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(ena_comma_align_i_0),
        .RXMONITOROUT(gt0_rxmonitorout_out),
        .RXMONITORSEL(gt0_rxmonitorsel_in),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gt0_rx_not_in_table_out}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(ena_comma_align_i_0),
        .RXPCSRESET(gt0_rxpcsreset_in),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(gt0_rxpmareset_in),
        .RXPMARESETDONE(gt0_rxpmaresetdone_out),
        .RXPOLARITY(rx_polarity_i_0),
        .RXPRBSCNTRESET(gt0_rxprbscntreset_in),
        .RXPRBSERR(gt0_rxprbserr_out),
        .RXPRBSSEL(gt0_rxprbssel_in),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gt0_rxresetdone_out),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS({gthe2_i_n_112,gthe2_i_n_113}),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(1'b0),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(1'b0),
        .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(gthe2_i_n_45),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(1'b0),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gthe2_i_n_54),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(1'b1),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT3 #(
    .INIT(8'hFE)) 
    hard_err_flop_r_i_1
       (.I0(gt0_rxbufstatus_out[2]),
        .I1(bucket_full_r),
        .I2(gthe2_i_0),
        .O(hard_err_flop_r0));
  LUT5 #(
    .INIT(32'hFFFBEFFF)) 
    left_aligned_r_i_2
       (.I0(first_v_received_r),
        .I1(D[0]),
        .I2(D[1]),
        .I3(rx_char_is_k_i_0[1]),
        .I4(rx_char_is_k_i_0[0]),
        .O(first_v_received_r_reg));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    reset_count_r_i_2
       (.I0(gt0_rx_not_in_table_out[1]),
        .I1(gt0_rx_disp_err_out[1]),
        .I2(gtp_rx_reset_i_0),
        .I3(comma_over_two_cycles_r),
        .I4(gt0_rx_not_in_table_out[0]),
        .I5(gt0_rx_disp_err_out[0]),
        .O(gthe2_i_3));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[0]_i_2 
       (.I0(gt0_rx_not_in_table_out[0]),
        .I1(gt0_rx_disp_err_out[0]),
        .O(gthe2_i_4[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[1]_i_1 
       (.I0(gt0_rx_not_in_table_out[1]),
        .I1(gt0_rx_disp_err_out[1]),
        .O(gthe2_i_4[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[0]_i_1 
       (.I0(rx_char_is_k_i_0[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_0[1]),
        .O(gthe2_i_2));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[1]_i_1 
       (.I0(rx_char_is_k_i_0[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_0[0]),
        .O(gthe2_i_1));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[0]_i_1 
       (.I0(rx_data_i_0[7]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[15]),
        .O(gthe2_i_6[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[10]_i_1 
       (.I0(rx_data_i_0[13]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[5]),
        .O(gthe2_i_5[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[11]_i_1 
       (.I0(rx_data_i_0[12]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[4]),
        .O(gthe2_i_5[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[12]_i_1 
       (.I0(rx_data_i_0[11]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[3]),
        .O(gthe2_i_5[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[13]_i_1 
       (.I0(rx_data_i_0[10]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[2]),
        .O(gthe2_i_5[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[14]_i_1 
       (.I0(rx_data_i_0[9]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[1]),
        .O(gthe2_i_5[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[15]_i_1 
       (.I0(rx_data_i_0[8]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[0]),
        .O(gthe2_i_5[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[1]_i_1 
       (.I0(rx_data_i_0[6]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[14]),
        .O(gthe2_i_6[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[2]_i_1 
       (.I0(rx_data_i_0[5]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[13]),
        .O(gthe2_i_6[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[3]_i_1 
       (.I0(rx_data_i_0[4]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[12]),
        .O(gthe2_i_6[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[4]_i_1 
       (.I0(rx_data_i_0[3]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[11]),
        .O(gthe2_i_6[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[5]_i_1 
       (.I0(rx_data_i_0[2]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[10]),
        .O(gthe2_i_6[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[6]_i_1 
       (.I0(rx_data_i_0[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[9]),
        .O(gthe2_i_6[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[7]_i_1 
       (.I0(rx_data_i_0[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[8]),
        .O(gthe2_i_6[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[8]_i_1 
       (.I0(rx_data_i_0[15]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[7]),
        .O(gthe2_i_5[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[9]_i_1 
       (.I0(rx_data_i_0[14]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_0[6]),
        .O(gthe2_i_5[6]));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_gt" *) 
module aurora_rx_4l_64b_gt_33
   (gt1_cplllock_out,
    DRPRDY_OUT_LANE1,
    gt1_eyescandataerror_out,
    gt1_rxbyteisaligned_out,
    gthe2_i_0,
    CHBONDDONE_OUT_LANE1,
    gt1_rxcommadet_out,
    gt1_rxpmaresetdone_out,
    gt1_rxprbserr_out,
    gt1_rxresetdone_out,
    gt1_dmonitorout_out,
    DRPDO_OUT_LANE1,
    gt1_rxbufstatus_out,
    RXCHBONDO,
    gt1_rxmonitorout_out,
    gthe2_i_1,
    gt1_rx_disp_err_out,
    gt1_rx_not_in_table_out,
    gthe2_i_2,
    gthe2_i_3,
    gthe2_i_4,
    gthe2_i_5,
    first_v_received_r_reg,
    hard_err_flop_r0_0,
    gthe2_i_6,
    gthe2_i_7,
    init_clk_in,
    drpclk_in,
    DRPEN_IN_LANE1,
    DRPWE_IN_LANE1,
    gt1_eyescanreset_in,
    gt1_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    SR,
    fsm_gt_rx_reset_t,
    gt_qpllclk_quad2_in,
    gt_qpllrefclk_quad2_in,
    gt1_rxbufreset_in,
    gt1_rxcdrhold_in,
    gt1_rxcdrovrden_in,
    en_chan_sync_i,
    gt1_rxdfelpmreset_in,
    gt1_rxlpmen_in,
    ena_comma_align_i_1,
    gt1_rxpcsreset_in,
    gt1_rxpmareset_in,
    rx_polarity_i_1,
    gt1_rxprbscntreset_in,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    DRPDI_IN_LANE1,
    gt1_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt1_rxprbssel_in,
    DRPADDR_IN_LANE1,
    flag2_reg_0,
    \word_aligned_control_bits_r_reg[1] ,
    gtp_rx_reset_i_1,
    comma_over_two_cycles_r_3,
    first_v_received_r_4,
    bucket_full_r_5,
    cpll_reset_i);
  output gt1_cplllock_out;
  output DRPRDY_OUT_LANE1;
  output gt1_eyescandataerror_out;
  output gt1_rxbyteisaligned_out;
  output gthe2_i_0;
  output CHBONDDONE_OUT_LANE1;
  output gt1_rxcommadet_out;
  output gt1_rxpmaresetdone_out;
  output gt1_rxprbserr_out;
  output gt1_rxresetdone_out;
  output [14:0]gt1_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE1;
  output [2:0]gt1_rxbufstatus_out;
  output [4:0]RXCHBONDO;
  output [6:0]gt1_rxmonitorout_out;
  output [1:0]gthe2_i_1;
  output [1:0]gt1_rx_disp_err_out;
  output [1:0]gt1_rx_not_in_table_out;
  output gthe2_i_2;
  output gthe2_i_3;
  output gthe2_i_4;
  output [1:0]gthe2_i_5;
  output first_v_received_r_reg;
  output hard_err_flop_r0_0;
  output [7:0]gthe2_i_6;
  output [7:0]gthe2_i_7;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN_LANE1;
  input DRPWE_IN_LANE1;
  input gt1_eyescanreset_in;
  input gt1_eyescantrigger_in;
  input [0:0]RXN;
  input [0:0]RXP;
  input gt_refclk1;
  input [0:0]SR;
  input fsm_gt_rx_reset_t;
  input gt_qpllclk_quad2_in;
  input gt_qpllrefclk_quad2_in;
  input gt1_rxbufreset_in;
  input gt1_rxcdrhold_in;
  input gt1_rxcdrovrden_in;
  input en_chan_sync_i;
  input gt1_rxdfelpmreset_in;
  input gt1_rxlpmen_in;
  input ena_comma_align_i_1;
  input gt1_rxpcsreset_in;
  input gt1_rxpmareset_in;
  input rx_polarity_i_1;
  input gt1_rxprbscntreset_in;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN_LANE1;
  input [1:0]gt1_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt1_rxprbssel_in;
  input [8:0]DRPADDR_IN_LANE1;
  input flag2_reg_0;
  input \word_aligned_control_bits_r_reg[1] ;
  input gtp_rx_reset_i_1;
  input comma_over_two_cycles_r_3;
  input first_v_received_r_4;
  input bucket_full_r_5;
  input cpll_reset_i;

  wire CHBONDDONE_OUT_LANE1;
  wire CPLLPD;
  wire CPLLRESET;
  wire D;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDO_OUT_LANE1;
  wire DRPEN_IN_LANE1;
  wire DRPRDY_OUT_LANE1;
  wire DRPWE_IN_LANE1;
  wire GT1_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [0:0]RXN;
  wire [0:0]RXP;
  wire [0:0]SR;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire bucket_full_r_5;
  wire comma_over_two_cycles_r_3;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire en_chan_sync_i;
  wire ena_comma_align_i_1;
  wire first_v_received_r_4;
  wire first_v_received_r_reg;
  wire flag2_i_1_n_0;
  wire flag2_reg_0;
  wire flag2_reg_n_0;
  wire flag_i_1__0_n_0;
  wire fsm_gt_rx_reset_t;
  wire gt1_cplllock_out;
  wire [14:0]gt1_dmonitorout_out;
  wire gt1_eyescandataerror_out;
  wire gt1_eyescanreset_in;
  wire gt1_eyescantrigger_in;
  wire [1:0]gt1_rx_disp_err_out;
  wire [1:0]gt1_rx_not_in_table_out;
  wire gt1_rxbufreset_in;
  wire [2:0]gt1_rxbufstatus_out;
  wire gt1_rxbyteisaligned_out;
  wire gt1_rxcdrhold_in;
  wire gt1_rxcdrovrden_in;
  wire gt1_rxcommadet_out;
  wire gt1_rxdfelpmreset_in;
  wire gt1_rxlpmen_in;
  wire [6:0]gt1_rxmonitorout_out;
  wire [1:0]gt1_rxmonitorsel_in;
  wire gt1_rxpcsreset_in;
  wire gt1_rxpmareset_in;
  wire gt1_rxpmaresetdone_out;
  wire gt1_rxprbscntreset_in;
  wire gt1_rxprbserr_out;
  wire [2:0]gt1_rxprbssel_in;
  wire gt1_rxresetdone_out;
  wire gt_qpllclk_quad2_in;
  wire gt_qpllrefclk_quad2_in;
  wire gt_refclk1;
  wire gt_rxuserrdy_i;
  wire gthe2_i_0;
  wire [1:0]gthe2_i_1;
  wire gthe2_i_2;
  wire gthe2_i_3;
  wire gthe2_i_4;
  wire [1:0]gthe2_i_5;
  wire [7:0]gthe2_i_6;
  wire [7:0]gthe2_i_7;
  wire gthe2_i_n_0;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_112;
  wire gthe2_i_n_113;
  wire gthe2_i_n_12;
  wire gthe2_i_n_13;
  wire gthe2_i_n_15;
  wire gthe2_i_n_29;
  wire gthe2_i_n_45;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_5;
  wire gthe2_i_n_54;
  wire gthe2_i_n_6;
  wire gtp_rx_reset_i_1;
  wire hard_err_flop_r0_0;
  wire init_clk_in;
  wire [1:0]rx_char_is_k_i_2;
  wire [15:0]rx_data_i_16;
  wire rx_polarity_i_1;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2_reg_n_0),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt1_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1
       (.I0(ack_flag),
        .O(flag2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_1_n_0),
        .Q(flag2_reg_n_0),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1__0
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D),
        .O(flag_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1__0_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt1_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT1_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT(gt1_dmonitorout_out),
        .DRPADDR(DRPADDR_IN_LANE1),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN_LANE1),
        .DRPDO(DRPDO_OUT_LANE1),
        .DRPEN(DRPEN_IN_LANE1),
        .DRPRDY(DRPRDY_OUT_LANE1),
        .DRPWE(DRPWE_IN_LANE1),
        .EYESCANDATAERROR(gt1_eyescandataerror_out),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(gt1_eyescanreset_in),
        .EYESCANTRIGGER(gt1_eyescantrigger_in),
        .GTGREFCLK(1'b0),
        .GTHRXN(RXN),
        .GTHRXP(RXP),
        .GTHTXN(gthe2_i_n_5),
        .GTHTXP(gthe2_i_n_6),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(SR),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(fsm_gt_rx_reset_t),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad2_in),
        .QPLLREFCLK(gt_qpllrefclk_quad2_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(gt1_rxbufreset_in),
        .RXBUFSTATUS(gt1_rxbufstatus_out),
        .RXBYTEISALIGNED(gt1_rxbyteisaligned_out),
        .RXBYTEREALIGN(gthe2_i_0),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(gt1_rxcdrhold_in),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(gt1_rxcdrovrden_in),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(CHBONDDONE_OUT_LANE1),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],gthe2_i_1}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],rx_char_is_k_i_2}),
        .RXCHBONDEN(en_chan_sync_i),
        .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXCHBONDLEVEL({1'b0,1'b1,1'b0}),
        .RXCHBONDMASTER(1'b1),
        .RXCHBONDO(RXCHBONDO),
        .RXCHBONDSLAVE(1'b0),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gt1_rxcommadet_out),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],rx_data_i_16}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(1'b0),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(gt1_rxdfelpmreset_in),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gt1_rx_disp_err_out}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(gt1_rxlpmen_in),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(ena_comma_align_i_1),
        .RXMONITOROUT(gt1_rxmonitorout_out),
        .RXMONITORSEL(gt1_rxmonitorsel_in),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gt1_rx_not_in_table_out}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(ena_comma_align_i_1),
        .RXPCSRESET(gt1_rxpcsreset_in),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(gt1_rxpmareset_in),
        .RXPMARESETDONE(gt1_rxpmaresetdone_out),
        .RXPOLARITY(rx_polarity_i_1),
        .RXPRBSCNTRESET(gt1_rxprbscntreset_in),
        .RXPRBSERR(gt1_rxprbserr_out),
        .RXPRBSSEL(gt1_rxprbssel_in),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gt1_rxresetdone_out),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS({gthe2_i_n_112,gthe2_i_n_113}),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(1'b0),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(1'b0),
        .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(gthe2_i_n_45),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(1'b0),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gthe2_i_n_54),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(1'b1),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT3 #(
    .INIT(8'hFE)) 
    hard_err_flop_r_i_1__0
       (.I0(gt1_rxbufstatus_out[2]),
        .I1(bucket_full_r_5),
        .I2(gthe2_i_0),
        .O(hard_err_flop_r0_0));
  LUT5 #(
    .INIT(32'hFFFBEFFF)) 
    left_aligned_r_i_2__0
       (.I0(first_v_received_r_4),
        .I1(gthe2_i_1[0]),
        .I2(gthe2_i_1[1]),
        .I3(rx_char_is_k_i_2[1]),
        .I4(rx_char_is_k_i_2[0]),
        .O(first_v_received_r_reg));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    reset_count_r_i_2__0
       (.I0(gt1_rx_not_in_table_out[1]),
        .I1(gt1_rx_disp_err_out[1]),
        .I2(gtp_rx_reset_i_1),
        .I3(comma_over_two_cycles_r_3),
        .I4(gt1_rx_not_in_table_out[0]),
        .I5(gt1_rx_disp_err_out[0]),
        .O(gthe2_i_4));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[0]_i_2__0 
       (.I0(gt1_rx_not_in_table_out[0]),
        .I1(gt1_rx_disp_err_out[0]),
        .O(gthe2_i_5[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[1]_i_1__0 
       (.I0(gt1_rx_not_in_table_out[1]),
        .I1(gt1_rx_disp_err_out[1]),
        .O(gthe2_i_5[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[0]_i_1__0 
       (.I0(rx_char_is_k_i_2[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_2[1]),
        .O(gthe2_i_3));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[1]_i_1__0 
       (.I0(rx_char_is_k_i_2[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_2[0]),
        .O(gthe2_i_2));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[0]_i_1__0 
       (.I0(rx_data_i_16[7]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[15]),
        .O(gthe2_i_7[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[10]_i_1__0 
       (.I0(rx_data_i_16[13]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[5]),
        .O(gthe2_i_6[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[11]_i_1__0 
       (.I0(rx_data_i_16[12]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[4]),
        .O(gthe2_i_6[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[12]_i_1__0 
       (.I0(rx_data_i_16[11]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[3]),
        .O(gthe2_i_6[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[13]_i_1__0 
       (.I0(rx_data_i_16[10]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[2]),
        .O(gthe2_i_6[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[14]_i_1__0 
       (.I0(rx_data_i_16[9]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[1]),
        .O(gthe2_i_6[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[15]_i_1__0 
       (.I0(rx_data_i_16[8]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[0]),
        .O(gthe2_i_6[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[1]_i_1__0 
       (.I0(rx_data_i_16[6]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[14]),
        .O(gthe2_i_7[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[2]_i_1__0 
       (.I0(rx_data_i_16[5]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[13]),
        .O(gthe2_i_7[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[3]_i_1__0 
       (.I0(rx_data_i_16[4]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[12]),
        .O(gthe2_i_7[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[4]_i_1__0 
       (.I0(rx_data_i_16[3]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[11]),
        .O(gthe2_i_7[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[5]_i_1__0 
       (.I0(rx_data_i_16[2]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[10]),
        .O(gthe2_i_7[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[6]_i_1__0 
       (.I0(rx_data_i_16[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[9]),
        .O(gthe2_i_7[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[7]_i_1__0 
       (.I0(rx_data_i_16[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[8]),
        .O(gthe2_i_7[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[8]_i_1__0 
       (.I0(rx_data_i_16[15]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[7]),
        .O(gthe2_i_6[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[9]_i_1__0 
       (.I0(rx_data_i_16[14]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_16[6]),
        .O(gthe2_i_6[6]));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_gt" *) 
module aurora_rx_4l_64b_gt_34
   (gt2_cplllock_out,
    DRPRDY_OUT_LANE2,
    gt2_eyescandataerror_out,
    gt2_rxbyteisaligned_out,
    gthe2_i_0,
    CHBONDDONE_OUT_LANE2,
    gt2_rxcommadet_out,
    gt2_rxpmaresetdone_out,
    gt2_rxprbserr_out,
    gt2_rxresetdone_out,
    TX_OUT_CLK,
    gt2_dmonitorout_out,
    DRPDO_OUT_LANE2,
    gt2_rxbufstatus_out,
    RXCHBONDO,
    gt2_rxmonitorout_out,
    gthe2_i_1,
    gt2_rx_disp_err_out,
    gt2_rx_not_in_table_out,
    gthe2_i_2,
    gthe2_i_3,
    gthe2_i_4,
    gthe2_i_5,
    first_v_received_r_reg,
    hard_err_flop_r0_1,
    gthe2_i_6,
    gthe2_i_7,
    TX_LOCK,
    init_clk_in,
    drpclk_in,
    DRPEN_IN_LANE2,
    DRPWE_IN_LANE2,
    gt2_eyescanreset_in,
    gt2_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    SR,
    fsm_gt_rx_reset_t,
    gt_qpllclk_quad3_in,
    gt_qpllrefclk_quad3_in,
    gt2_rxbufreset_in,
    gt2_rxcdrhold_in,
    gt2_rxcdrovrden_in,
    gt2_rxdfelpmreset_in,
    gt2_rxlpmen_in,
    ena_comma_align_i_2,
    gt2_rxpcsreset_in,
    gt2_rxpmareset_in,
    rx_polarity_i_2,
    gt2_rxprbscntreset_in,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    DRPDI_IN_LANE2,
    gt2_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt2_rxprbssel_in,
    gthe2_i_8,
    DRPADDR_IN_LANE2,
    flag2_reg_0,
    \word_aligned_control_bits_r_reg[1] ,
    gtp_rx_reset_i_2,
    comma_over_two_cycles_r_6,
    first_v_received_r_7,
    bucket_full_r_8,
    cpll_reset_i,
    gt3_cplllock_out,
    gt0_cplllock_out,
    gt1_cplllock_out);
  output gt2_cplllock_out;
  output DRPRDY_OUT_LANE2;
  output gt2_eyescandataerror_out;
  output gt2_rxbyteisaligned_out;
  output gthe2_i_0;
  output CHBONDDONE_OUT_LANE2;
  output gt2_rxcommadet_out;
  output gt2_rxpmaresetdone_out;
  output gt2_rxprbserr_out;
  output gt2_rxresetdone_out;
  output TX_OUT_CLK;
  output [14:0]gt2_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE2;
  output [2:0]gt2_rxbufstatus_out;
  output [4:0]RXCHBONDO;
  output [6:0]gt2_rxmonitorout_out;
  output [1:0]gthe2_i_1;
  output [1:0]gt2_rx_disp_err_out;
  output [1:0]gt2_rx_not_in_table_out;
  output gthe2_i_2;
  output gthe2_i_3;
  output gthe2_i_4;
  output [1:0]gthe2_i_5;
  output first_v_received_r_reg;
  output hard_err_flop_r0_1;
  output [7:0]gthe2_i_6;
  output [7:0]gthe2_i_7;
  output TX_LOCK;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN_LANE2;
  input DRPWE_IN_LANE2;
  input gt2_eyescanreset_in;
  input gt2_eyescantrigger_in;
  input [0:0]RXN;
  input [0:0]RXP;
  input gt_refclk1;
  input [0:0]SR;
  input fsm_gt_rx_reset_t;
  input gt_qpllclk_quad3_in;
  input gt_qpllrefclk_quad3_in;
  input gt2_rxbufreset_in;
  input gt2_rxcdrhold_in;
  input gt2_rxcdrovrden_in;
  input gt2_rxdfelpmreset_in;
  input gt2_rxlpmen_in;
  input ena_comma_align_i_2;
  input gt2_rxpcsreset_in;
  input gt2_rxpmareset_in;
  input rx_polarity_i_2;
  input gt2_rxprbscntreset_in;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN_LANE2;
  input [1:0]gt2_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt2_rxprbssel_in;
  input [4:0]gthe2_i_8;
  input [8:0]DRPADDR_IN_LANE2;
  input flag2_reg_0;
  input \word_aligned_control_bits_r_reg[1] ;
  input gtp_rx_reset_i_2;
  input comma_over_two_cycles_r_6;
  input first_v_received_r_7;
  input bucket_full_r_8;
  input cpll_reset_i;
  input gt3_cplllock_out;
  input gt0_cplllock_out;
  input gt1_cplllock_out;

  wire CHBONDDONE_OUT_LANE2;
  wire CPLLPD;
  wire CPLLRESET;
  wire D;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDO_OUT_LANE2;
  wire DRPEN_IN_LANE2;
  wire DRPRDY_OUT_LANE2;
  wire DRPWE_IN_LANE2;
  wire GT2_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [0:0]RXN;
  wire [0:0]RXP;
  wire [0:0]SR;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire bucket_full_r_8;
  wire comma_over_two_cycles_r_6;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire ena_comma_align_i_2;
  wire first_v_received_r_7;
  wire first_v_received_r_reg;
  wire flag2_i_1__0_n_0;
  wire flag2_reg_0;
  wire flag2_reg_n_0;
  wire flag_i_1__1_n_0;
  wire fsm_gt_rx_reset_t;
  wire gt0_cplllock_out;
  wire gt1_cplllock_out;
  wire gt2_cplllock_out;
  wire [14:0]gt2_dmonitorout_out;
  wire gt2_eyescandataerror_out;
  wire gt2_eyescanreset_in;
  wire gt2_eyescantrigger_in;
  wire [1:0]gt2_rx_disp_err_out;
  wire [1:0]gt2_rx_not_in_table_out;
  wire gt2_rxbufreset_in;
  wire [2:0]gt2_rxbufstatus_out;
  wire gt2_rxbyteisaligned_out;
  wire gt2_rxcdrhold_in;
  wire gt2_rxcdrovrden_in;
  wire gt2_rxcommadet_out;
  wire gt2_rxdfelpmreset_in;
  wire gt2_rxlpmen_in;
  wire [6:0]gt2_rxmonitorout_out;
  wire [1:0]gt2_rxmonitorsel_in;
  wire gt2_rxpcsreset_in;
  wire gt2_rxpmareset_in;
  wire gt2_rxpmaresetdone_out;
  wire gt2_rxprbscntreset_in;
  wire gt2_rxprbserr_out;
  wire [2:0]gt2_rxprbssel_in;
  wire gt2_rxresetdone_out;
  wire gt3_cplllock_out;
  wire gt_qpllclk_quad3_in;
  wire gt_qpllrefclk_quad3_in;
  wire gt_refclk1;
  wire gt_rxuserrdy_i;
  wire gthe2_i_0;
  wire [1:0]gthe2_i_1;
  wire gthe2_i_2;
  wire gthe2_i_3;
  wire gthe2_i_4;
  wire [1:0]gthe2_i_5;
  wire [7:0]gthe2_i_6;
  wire [7:0]gthe2_i_7;
  wire [4:0]gthe2_i_8;
  wire gthe2_i_n_0;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_112;
  wire gthe2_i_n_113;
  wire gthe2_i_n_12;
  wire gthe2_i_n_13;
  wire gthe2_i_n_15;
  wire gthe2_i_n_29;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_5;
  wire gthe2_i_n_54;
  wire gthe2_i_n_6;
  wire gtp_rx_reset_i_2;
  wire hard_err_flop_r0_1;
  wire init_clk_in;
  wire [1:0]rx_char_is_k_i_4;
  wire [15:0]rx_data_i_32;
  wire rx_polarity_i_2;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'h8000)) 
    TX_LOCK_INST_0
       (.I0(gt2_cplllock_out),
        .I1(gt3_cplllock_out),
        .I2(gt0_cplllock_out),
        .I3(gt1_cplllock_out),
        .O(TX_LOCK));
  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2_reg_n_0),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt2_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1__0
       (.I0(ack_flag),
        .O(flag2_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_1__0_n_0),
        .Q(flag2_reg_n_0),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1__1
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D),
        .O(flag_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1__1_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt2_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT2_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT(gt2_dmonitorout_out),
        .DRPADDR(DRPADDR_IN_LANE2),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN_LANE2),
        .DRPDO(DRPDO_OUT_LANE2),
        .DRPEN(DRPEN_IN_LANE2),
        .DRPRDY(DRPRDY_OUT_LANE2),
        .DRPWE(DRPWE_IN_LANE2),
        .EYESCANDATAERROR(gt2_eyescandataerror_out),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(gt2_eyescanreset_in),
        .EYESCANTRIGGER(gt2_eyescantrigger_in),
        .GTGREFCLK(1'b0),
        .GTHRXN(RXN),
        .GTHRXP(RXP),
        .GTHTXN(gthe2_i_n_5),
        .GTHTXP(gthe2_i_n_6),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(SR),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(fsm_gt_rx_reset_t),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad3_in),
        .QPLLREFCLK(gt_qpllrefclk_quad3_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(gt2_rxbufreset_in),
        .RXBUFSTATUS(gt2_rxbufstatus_out),
        .RXBYTEISALIGNED(gt2_rxbyteisaligned_out),
        .RXBYTEREALIGN(gthe2_i_0),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(gt2_rxcdrhold_in),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(gt2_rxcdrovrden_in),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(CHBONDDONE_OUT_LANE2),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],gthe2_i_1}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],rx_char_is_k_i_4}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI(gthe2_i_8),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b1}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO(RXCHBONDO),
        .RXCHBONDSLAVE(1'b1),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gt2_rxcommadet_out),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],rx_data_i_32}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(1'b0),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(gt2_rxdfelpmreset_in),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gt2_rx_disp_err_out}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(gt2_rxlpmen_in),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(ena_comma_align_i_2),
        .RXMONITOROUT(gt2_rxmonitorout_out),
        .RXMONITORSEL(gt2_rxmonitorsel_in),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gt2_rx_not_in_table_out}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(ena_comma_align_i_2),
        .RXPCSRESET(gt2_rxpcsreset_in),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(gt2_rxpmareset_in),
        .RXPMARESETDONE(gt2_rxpmaresetdone_out),
        .RXPOLARITY(rx_polarity_i_2),
        .RXPRBSCNTRESET(gt2_rxprbscntreset_in),
        .RXPRBSERR(gt2_rxprbserr_out),
        .RXPRBSSEL(gt2_rxprbssel_in),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gt2_rxresetdone_out),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS({gthe2_i_n_112,gthe2_i_n_113}),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(1'b0),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(1'b0),
        .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(TX_OUT_CLK),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(1'b0),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gthe2_i_n_54),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(1'b1),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT3 #(
    .INIT(8'hFE)) 
    hard_err_flop_r_i_1__1
       (.I0(gt2_rxbufstatus_out[2]),
        .I1(bucket_full_r_8),
        .I2(gthe2_i_0),
        .O(hard_err_flop_r0_1));
  LUT5 #(
    .INIT(32'hFFFBEFFF)) 
    left_aligned_r_i_2__1
       (.I0(first_v_received_r_7),
        .I1(gthe2_i_1[0]),
        .I2(gthe2_i_1[1]),
        .I3(rx_char_is_k_i_4[1]),
        .I4(rx_char_is_k_i_4[0]),
        .O(first_v_received_r_reg));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    reset_count_r_i_2__1
       (.I0(gt2_rx_not_in_table_out[1]),
        .I1(gt2_rx_disp_err_out[1]),
        .I2(gtp_rx_reset_i_2),
        .I3(comma_over_two_cycles_r_6),
        .I4(gt2_rx_not_in_table_out[0]),
        .I5(gt2_rx_disp_err_out[0]),
        .O(gthe2_i_4));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[0]_i_2__1 
       (.I0(gt2_rx_not_in_table_out[0]),
        .I1(gt2_rx_disp_err_out[0]),
        .O(gthe2_i_5[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[1]_i_1__1 
       (.I0(gt2_rx_not_in_table_out[1]),
        .I1(gt2_rx_disp_err_out[1]),
        .O(gthe2_i_5[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[0]_i_1__1 
       (.I0(rx_char_is_k_i_4[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_4[1]),
        .O(gthe2_i_3));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[1]_i_1__1 
       (.I0(rx_char_is_k_i_4[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_4[0]),
        .O(gthe2_i_2));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[0]_i_1__1 
       (.I0(rx_data_i_32[7]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[15]),
        .O(gthe2_i_7[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[10]_i_1__1 
       (.I0(rx_data_i_32[13]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[5]),
        .O(gthe2_i_6[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[11]_i_1__1 
       (.I0(rx_data_i_32[12]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[4]),
        .O(gthe2_i_6[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[12]_i_1__1 
       (.I0(rx_data_i_32[11]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[3]),
        .O(gthe2_i_6[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[13]_i_1__1 
       (.I0(rx_data_i_32[10]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[2]),
        .O(gthe2_i_6[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[14]_i_1__1 
       (.I0(rx_data_i_32[9]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[1]),
        .O(gthe2_i_6[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[15]_i_1__1 
       (.I0(rx_data_i_32[8]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[0]),
        .O(gthe2_i_6[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[1]_i_1__1 
       (.I0(rx_data_i_32[6]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[14]),
        .O(gthe2_i_7[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[2]_i_1__1 
       (.I0(rx_data_i_32[5]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[13]),
        .O(gthe2_i_7[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[3]_i_1__1 
       (.I0(rx_data_i_32[4]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[12]),
        .O(gthe2_i_7[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[4]_i_1__1 
       (.I0(rx_data_i_32[3]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[11]),
        .O(gthe2_i_7[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[5]_i_1__1 
       (.I0(rx_data_i_32[2]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[10]),
        .O(gthe2_i_7[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[6]_i_1__1 
       (.I0(rx_data_i_32[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[9]),
        .O(gthe2_i_7[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[7]_i_1__1 
       (.I0(rx_data_i_32[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[8]),
        .O(gthe2_i_7[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[8]_i_1__1 
       (.I0(rx_data_i_32[15]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[7]),
        .O(gthe2_i_6[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[9]_i_1__1 
       (.I0(rx_data_i_32[14]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_32[6]),
        .O(gthe2_i_6[6]));
endmodule

(* ORIG_REF_NAME = "aurora_rx_4l_64b_gt" *) 
module aurora_rx_4l_64b_gt_35
   (gt3_cplllock_out,
    DRPRDY_OUT_LANE3,
    gt3_eyescandataerror_out,
    gt3_rxbyteisaligned_out,
    gthe2_i_0,
    CHBONDDONE_OUT_LANE3,
    gt3_rxcommadet_out,
    gt3_rxpmaresetdone_out,
    gt3_rxprbserr_out,
    gt3_rxresetdone_out,
    gt3_dmonitorout_out,
    DRPDO_OUT_LANE3,
    gt3_rxbufstatus_out,
    gt3_rxmonitorout_out,
    gthe2_i_1,
    gt3_rx_disp_err_out,
    gt3_rx_not_in_table_out,
    gthe2_i_2,
    gthe2_i_3,
    gthe2_i_4,
    gthe2_i_5,
    first_v_received_r_reg,
    hard_err_flop_r0_2,
    gthe2_i_6,
    gthe2_i_7,
    init_clk_in,
    drpclk_in,
    DRPEN_IN_LANE3,
    DRPWE_IN_LANE3,
    gt3_eyescanreset_in,
    gt3_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    SR,
    fsm_gt_rx_reset_t,
    gt_qpllclk_quad3_in,
    gt_qpllrefclk_quad3_in,
    gt3_rxbufreset_in,
    gt3_rxcdrhold_in,
    gt3_rxcdrovrden_in,
    gt3_rxdfelpmreset_in,
    gt3_rxlpmen_in,
    ena_comma_align_i_3,
    gt3_rxpcsreset_in,
    gt3_rxpmareset_in,
    rx_polarity_i_3,
    gt3_rxprbscntreset_in,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    DRPDI_IN_LANE3,
    gt3_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt3_rxprbssel_in,
    RXCHBONDO,
    DRPADDR_IN_LANE3,
    flag2_reg_0,
    \word_aligned_control_bits_r_reg[1] ,
    gtp_rx_reset_i_3,
    comma_over_two_cycles_r_9,
    first_v_received_r_10,
    bucket_full_r_11,
    cpll_reset_i);
  output gt3_cplllock_out;
  output DRPRDY_OUT_LANE3;
  output gt3_eyescandataerror_out;
  output gt3_rxbyteisaligned_out;
  output gthe2_i_0;
  output CHBONDDONE_OUT_LANE3;
  output gt3_rxcommadet_out;
  output gt3_rxpmaresetdone_out;
  output gt3_rxprbserr_out;
  output gt3_rxresetdone_out;
  output [14:0]gt3_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE3;
  output [2:0]gt3_rxbufstatus_out;
  output [6:0]gt3_rxmonitorout_out;
  output [1:0]gthe2_i_1;
  output [1:0]gt3_rx_disp_err_out;
  output [1:0]gt3_rx_not_in_table_out;
  output gthe2_i_2;
  output gthe2_i_3;
  output gthe2_i_4;
  output [1:0]gthe2_i_5;
  output first_v_received_r_reg;
  output hard_err_flop_r0_2;
  output [7:0]gthe2_i_6;
  output [7:0]gthe2_i_7;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN_LANE3;
  input DRPWE_IN_LANE3;
  input gt3_eyescanreset_in;
  input gt3_eyescantrigger_in;
  input [0:0]RXN;
  input [0:0]RXP;
  input gt_refclk1;
  input [0:0]SR;
  input fsm_gt_rx_reset_t;
  input gt_qpllclk_quad3_in;
  input gt_qpllrefclk_quad3_in;
  input gt3_rxbufreset_in;
  input gt3_rxcdrhold_in;
  input gt3_rxcdrovrden_in;
  input gt3_rxdfelpmreset_in;
  input gt3_rxlpmen_in;
  input ena_comma_align_i_3;
  input gt3_rxpcsreset_in;
  input gt3_rxpmareset_in;
  input rx_polarity_i_3;
  input gt3_rxprbscntreset_in;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN_LANE3;
  input [1:0]gt3_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt3_rxprbssel_in;
  input [4:0]RXCHBONDO;
  input [8:0]DRPADDR_IN_LANE3;
  input flag2_reg_0;
  input \word_aligned_control_bits_r_reg[1] ;
  input gtp_rx_reset_i_3;
  input comma_over_two_cycles_r_9;
  input first_v_received_r_10;
  input bucket_full_r_11;
  input cpll_reset_i;

  wire CHBONDDONE_OUT_LANE3;
  wire CPLLPD;
  wire CPLLRESET;
  wire D;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN_LANE3;
  wire GT3_CPLLREFCLKLOST_OUT;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [4:0]RXCHBONDO;
  wire [0:0]RXN;
  wire [0:0]RXP;
  wire [0:0]SR;
  wire ack_flag;
  wire ack_flag_i_1_n_0;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;
  wire bucket_full_r_11;
  wire comma_over_two_cycles_r_9;
  wire cpll_reset_i;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire cpllreset_ovrd_i;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire drpclk_in;
  wire ena_comma_align_i_3;
  wire first_v_received_r_10;
  wire first_v_received_r_reg;
  wire flag2_i_1__1_n_0;
  wire flag2_reg_0;
  wire flag2_reg_n_0;
  wire flag_i_1__2_n_0;
  wire fsm_gt_rx_reset_t;
  wire gt3_cplllock_out;
  wire [14:0]gt3_dmonitorout_out;
  wire gt3_eyescandataerror_out;
  wire gt3_eyescanreset_in;
  wire gt3_eyescantrigger_in;
  wire [1:0]gt3_rx_disp_err_out;
  wire [1:0]gt3_rx_not_in_table_out;
  wire gt3_rxbufreset_in;
  wire [2:0]gt3_rxbufstatus_out;
  wire gt3_rxbyteisaligned_out;
  wire gt3_rxcdrhold_in;
  wire gt3_rxcdrovrden_in;
  wire gt3_rxcommadet_out;
  wire gt3_rxdfelpmreset_in;
  wire gt3_rxlpmen_in;
  wire [6:0]gt3_rxmonitorout_out;
  wire [1:0]gt3_rxmonitorsel_in;
  wire gt3_rxpcsreset_in;
  wire gt3_rxpmareset_in;
  wire gt3_rxpmaresetdone_out;
  wire gt3_rxprbscntreset_in;
  wire gt3_rxprbserr_out;
  wire [2:0]gt3_rxprbssel_in;
  wire gt3_rxresetdone_out;
  wire gt_qpllclk_quad3_in;
  wire gt_qpllrefclk_quad3_in;
  wire gt_refclk1;
  wire gt_rxuserrdy_i;
  wire gthe2_i_0;
  wire [1:0]gthe2_i_1;
  wire gthe2_i_2;
  wire gthe2_i_3;
  wire gthe2_i_4;
  wire [1:0]gthe2_i_5;
  wire [7:0]gthe2_i_6;
  wire [7:0]gthe2_i_7;
  wire gthe2_i_n_0;
  wire gthe2_i_n_104;
  wire gthe2_i_n_105;
  wire gthe2_i_n_112;
  wire gthe2_i_n_113;
  wire gthe2_i_n_12;
  wire gthe2_i_n_120;
  wire gthe2_i_n_121;
  wire gthe2_i_n_122;
  wire gthe2_i_n_123;
  wire gthe2_i_n_124;
  wire gthe2_i_n_13;
  wire gthe2_i_n_15;
  wire gthe2_i_n_29;
  wire gthe2_i_n_45;
  wire gthe2_i_n_46;
  wire gthe2_i_n_47;
  wire gthe2_i_n_5;
  wire gthe2_i_n_54;
  wire gthe2_i_n_6;
  wire gtp_rx_reset_i_3;
  wire hard_err_flop_r0_2;
  wire init_clk_in;
  wire [1:0]rx_char_is_k_i_6;
  wire [15:0]rx_data_i_48;
  wire rx_polarity_i_3;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;
  wire NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED;
  wire NLW_gthe2_i_PHYSTATUS_UNCONNECTED;
  wire NLW_gthe2_i_RSOSINTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMINITDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMSASDET_UNCONNECTED;
  wire NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXELECIDLE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED;
  wire NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED;
  wire NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_RXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_RXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_RXSYNCOUT_UNCONNECTED;
  wire NLW_gthe2_i_RXVALID_UNCONNECTED;
  wire NLW_gthe2_i_TXCOMFINISH_UNCONNECTED;
  wire NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED;
  wire NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPHINITDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENN_UNCONNECTED;
  wire NLW_gthe2_i_TXQPISENP_UNCONNECTED;
  wire NLW_gthe2_i_TXRATEDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCDONE_UNCONNECTED;
  wire NLW_gthe2_i_TXSYNCOUT_UNCONNECTED;
  wire [15:0]NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXCHARISK_UNCONNECTED;
  wire [63:16]NLW_gthe2_i_RXDATA_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXDATAVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXDISPERR_UNCONNECTED;
  wire [5:0]NLW_gthe2_i_RXHEADER_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXHEADERVALID_UNCONNECTED;
  wire [7:2]NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHMONITOR_UNCONNECTED;
  wire [4:0]NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED;
  wire [1:0]NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED;
  wire [2:0]NLW_gthe2_i_RXSTATUS_UNCONNECTED;

  LUT4 #(
    .INIT(16'hFF90)) 
    ack_flag_i_1
       (.I0(ack_sync6),
        .I1(ack_sync5),
        .I2(ack_flag),
        .I3(flag2_reg_n_0),
        .O(ack_flag_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ack_flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_flag_i_1_n_0),
        .Q(ack_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg1
       (.C(init_clk_in),
        .CE(1'b1),
        .D(data_sync6),
        .Q(ack_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg2
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync1),
        .Q(ack_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg3
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync2),
        .Q(ack_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg4
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync3),
        .Q(ack_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg5
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync4),
        .Q(ack_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    ack_sync_reg6
       (.C(init_clk_in),
        .CE(1'b1),
        .D(ack_sync5),
        .Q(ack_sync6),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF6)) 
    cpll_reset_i__0
       (.I0(data_sync6),
        .I1(data_sync5),
        .I2(cpllreset_ovrd_i),
        .O(CPLLRESET));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(CPLLPD),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllreset_ovrd_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\gt_wrapper_i/aurora_rx_4l_64b_multi_gt_i/gt3_aurora_rx_4l_64b_i/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_refclk1),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg1
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(D),
        .Q(data_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg2
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync1),
        .Q(data_sync2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg3
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync2),
        .Q(data_sync3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg4
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync3),
        .Q(data_sync4),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg5
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync4),
        .Q(data_sync5),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* SHREG_EXTRACT = "no" *) 
  (* XILINX_LEGACY_PRIM = "FD" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *) 
  FDRE #(
    .INIT(1'b0)) 
    data_sync_reg6
       (.C(gt_refclk1),
        .CE(1'b1),
        .D(data_sync5),
        .Q(data_sync6),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1__1
       (.I0(ack_flag),
        .O(flag2_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag2_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag2_i_1__1_n_0),
        .Q(flag2_reg_n_0),
        .R(flag2_reg_0));
  LUT3 #(
    .INIT(8'hB4)) 
    flag_i_1__2
       (.I0(ack_flag),
        .I1(cpll_reset_i),
        .I2(D),
        .O(flag_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    flag_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(flag_i_1__2_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  GTHE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'h00C10),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(2),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .A_RXOSCALRESET(1'b0),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(42'h24800040E80),
    .CFOK_CFG2(6'b100000),
    .CFOK_CFG3(6'b100000),
    .CHAN_BOND_KEEP_ALIGN("FALSE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0101111100),
    .CHAN_BOND_SEQ_1_2(10'b0000000000),
    .CHAN_BOND_SEQ_1_3(10'b0000000000),
    .CHAN_BOND_SEQ_1_4(10'b0000000000),
    .CHAN_BOND_SEQ_1_ENABLE(4'b0001),
    .CHAN_BOND_SEQ_2_1(10'b0000000000),
    .CHAN_BOND_SEQ_2_2(10'b0000000000),
    .CHAN_BOND_SEQ_2_3(10'b0000000000),
    .CHAN_BOND_SEQ_2_4(10'b0000000000),
    .CHAN_BOND_SEQ_2_ENABLE(4'b0000),
    .CHAN_BOND_SEQ_2_USE("FALSE"),
    .CHAN_BOND_SEQ_LEN(1),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("FALSE"),
    .CLK_COR_MAX_LAT(21),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0111110111),
    .CLK_COR_SEQ_1_2(10'b0111110111),
    .CLK_COR_SEQ_1_3(10'b0100000000),
    .CLK_COR_SEQ_1_4(10'b0100000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0100000000),
    .CLK_COR_SEQ_2_2(10'b0100000000),
    .CLK_COR_SEQ_2_3(10'b0100000000),
    .CLK_COR_SEQ_2_4(10'b0100000000),
    .CLK_COR_SEQ_2_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(2),
    .CPLL_CFG(29'h00BC07DC),
    .CPLL_FBDIV(4),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000A00),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("TRUE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("FALSE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("FALSE"),
    .PCS_RSVD_ATTR(48'h000000000000),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h19),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'b00000000000000000000000010000000),
    .PMA_RSV2(32'b00011100000000000000000000001010),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(15'b000000000001000),
    .PMA_RSV5(4'b0000),
    .RESET_POWERSAVE_DISABLE(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b1000),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("FALSE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0002007FE2000C2080018),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b0),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00001000000000),
    .RXLPM_LF_CFG(18'b001001000000000000),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("PMA"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(1),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h084020),
    .RXPH_CFG(24'hC00002),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(2'b00),
    .RXPI_CFG1(2'b00),
    .RXPI_CFG2(2'b00),
    .RXPI_CFG3(2'b00),
    .RXPI_CFG4(1'b0),
    .RXPI_CFG5(1'b0),
    .RXPI_CFG6(3'b100),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("OFF"),
    .RXSYNC_MULTILANE(1'b0),
    .RXSYNC_OVRD(1'b0),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(24'b000011000000000000010000),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(7),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFELPM_CFG0(4'b0110),
    .RX_DFELPM_CFG1(1'b0),
    .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1),
    .RX_DFE_AGC_CFG0(2'b00),
    .RX_DFE_AGC_CFG1(3'b100),
    .RX_DFE_AGC_CFG2(4'b0000),
    .RX_DFE_AGC_OVRDEN(1'b1),
    .RX_DFE_GAIN_CFG(23'h0020C0),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011100000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_H6_CFG(11'b00000100000),
    .RX_DFE_H7_CFG(11'b00000100000),
    .RX_DFE_KL_CFG(33'b001000001000000000000001100010000),
    .RX_DFE_KL_LPM_KH_CFG0(2'b01),
    .RX_DFE_KL_LPM_KH_CFG1(3'b010),
    .RX_DFE_KL_LPM_KH_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KH_OVRDEN(1'b1),
    .RX_DFE_KL_LPM_KL_CFG0(2'b10),
    .RX_DFE_KL_LPM_KL_CFG1(3'b010),
    .RX_DFE_KL_LPM_KL_CFG2(4'b0010),
    .RX_DFE_KL_LPM_KL_OVRDEN(1'b1),
    .RX_DFE_LPM_CFG(16'h0080),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0),
    .RX_DFE_ST_CFG(54'h00E100000C003F),
    .RX_DFE_UT_CFG(17'b00011100000000000),
    .RX_DFE_VP_CFG(17'b00011101010100011),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b0101),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("TRUE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("X"),
    .SIM_VERSION("2.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("TRUE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b0),
    .TXOUT_DIV(1),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b100),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00001),
    .TXSYNC_MULTILANE(1'b0),
    .TXSYNC_OVRD(1'b0),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(7),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b000000),
    .TX_DEEMPH1(6'b000000),
    .TX_DRIVE_MODE("DIRECT"),
    .TX_EIDLE_ASSERT_DELAY(3'b110),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001110),
    .TX_MARGIN_FULL_1(7'b1001001),
    .TX_MARGIN_FULL_2(7'b1000101),
    .TX_MARGIN_FULL_3(7'b1000010),
    .TX_MARGIN_FULL_4(7'b1000000),
    .TX_MARGIN_LOW_0(7'b1000110),
    .TX_MARGIN_LOW_1(7'b1000100),
    .TX_MARGIN_LOW_2(7'b1000010),
    .TX_MARGIN_LOW_3(7'b1000000),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h1832),
    .TX_RXDETECT_PRECHARGE_TIME(17'h155CC),
    .TX_RXDETECT_REF(3'b100),
    .TX_XCLK_SEL("TXOUT"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    gthe2_i
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .CPLLFBCLKLOST(gthe2_i_n_0),
        .CPLLLOCK(gt3_cplllock_out),
        .CPLLLOCKDETCLK(init_clk_in),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD),
        .CPLLREFCLKLOST(GT3_CPLLREFCLKLOST_OUT),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT(gt3_dmonitorout_out),
        .DRPADDR(DRPADDR_IN_LANE3),
        .DRPCLK(drpclk_in),
        .DRPDI(DRPDI_IN_LANE3),
        .DRPDO(DRPDO_OUT_LANE3),
        .DRPEN(DRPEN_IN_LANE3),
        .DRPRDY(DRPRDY_OUT_LANE3),
        .DRPWE(DRPWE_IN_LANE3),
        .EYESCANDATAERROR(gt3_eyescandataerror_out),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(gt3_eyescanreset_in),
        .EYESCANTRIGGER(gt3_eyescantrigger_in),
        .GTGREFCLK(1'b0),
        .GTHRXN(RXN),
        .GTHRXP(RXP),
        .GTHTXN(gthe2_i_n_5),
        .GTHTXP(gthe2_i_n_6),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(gt_refclk1),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(NLW_gthe2_i_GTREFCLKMONITOR_UNCONNECTED),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(SR),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(fsm_gt_rx_reset_t),
        .LOOPBACK(LOOPBACK),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(NLW_gthe2_i_PCSRSVDOUT_UNCONNECTED[15:0]),
        .PHYSTATUS(NLW_gthe2_i_PHYSTATUS_UNCONNECTED),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(gt_qpllclk_quad3_in),
        .QPLLREFCLK(gt_qpllrefclk_quad3_in),
        .RESETOVRD(1'b0),
        .RSOSINTDONE(NLW_gthe2_i_RSOSINTDONE_UNCONNECTED),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(gt3_rxbufreset_in),
        .RXBUFSTATUS(gt3_rxbufstatus_out),
        .RXBYTEISALIGNED(gt3_rxbyteisaligned_out),
        .RXBYTEREALIGN(gthe2_i_0),
        .RXCDRFREQRESET(1'b0),
        .RXCDRHOLD(gt3_rxcdrhold_in),
        .RXCDRLOCK(gthe2_i_n_12),
        .RXCDROVRDEN(gt3_rxcdrovrden_in),
        .RXCDRRESET(1'b0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(gthe2_i_n_13),
        .RXCHANISALIGNED(CHBONDDONE_OUT_LANE3),
        .RXCHANREALIGN(gthe2_i_n_15),
        .RXCHARISCOMMA({NLW_gthe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],gthe2_i_1}),
        .RXCHARISK({NLW_gthe2_i_RXCHARISK_UNCONNECTED[7:2],rx_char_is_k_i_6}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({gthe2_i_n_120,gthe2_i_n_121,gthe2_i_n_122,gthe2_i_n_123,gthe2_i_n_124}),
        .RXCHBONDSLAVE(1'b1),
        .RXCLKCORCNT({gthe2_i_n_104,gthe2_i_n_105}),
        .RXCOMINITDET(NLW_gthe2_i_RXCOMINITDET_UNCONNECTED),
        .RXCOMMADET(gt3_rxcommadet_out),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(NLW_gthe2_i_RXCOMSASDET_UNCONNECTED),
        .RXCOMWAKEDET(NLW_gthe2_i_RXCOMWAKEDET_UNCONNECTED),
        .RXDATA({NLW_gthe2_i_RXDATA_UNCONNECTED[63:16],rx_data_i_48}),
        .RXDATAVALID(NLW_gthe2_i_RXDATAVALID_UNCONNECTED[1:0]),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(1'b0),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFEAGCTRL({1'b1,1'b0,1'b0,1'b0,1'b0}),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b0),
        .RXDFELPMRESET(gt3_rxdfelpmreset_in),
        .RXDFESLIDETAP({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPADAPTEN(1'b0),
        .RXDFESLIDETAPHOLD(1'b0),
        .RXDFESLIDETAPID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXDFESLIDETAPINITOVRDEN(1'b0),
        .RXDFESLIDETAPONLYADAPTEN(1'b0),
        .RXDFESLIDETAPOVRDEN(1'b0),
        .RXDFESLIDETAPSTARTED(NLW_gthe2_i_RXDFESLIDETAPSTARTED_UNCONNECTED),
        .RXDFESLIDETAPSTROBE(1'b0),
        .RXDFESLIDETAPSTROBEDONE(NLW_gthe2_i_RXDFESLIDETAPSTROBEDONE_UNCONNECTED),
        .RXDFESLIDETAPSTROBESTARTED(NLW_gthe2_i_RXDFESLIDETAPSTROBESTARTED_UNCONNECTED),
        .RXDFESTADAPTDONE(NLW_gthe2_i_RXDFESTADAPTDONE_UNCONNECTED),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFETAP6HOLD(1'b0),
        .RXDFETAP6OVRDEN(1'b0),
        .RXDFETAP7HOLD(1'b0),
        .RXDFETAP7OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b1),
        .RXDISPERR({NLW_gthe2_i_RXDISPERR_UNCONNECTED[7:2],gt3_rx_disp_err_out}),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(NLW_gthe2_i_RXDLYSRESETDONE_UNCONNECTED),
        .RXELECIDLE(NLW_gthe2_i_RXELECIDLE_UNCONNECTED),
        .RXELECIDLEMODE({1'b1,1'b1}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(NLW_gthe2_i_RXHEADER_UNCONNECTED[5:0]),
        .RXHEADERVALID(NLW_gthe2_i_RXHEADERVALID_UNCONNECTED[1:0]),
        .RXLPMEN(gt3_rxlpmen_in),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(ena_comma_align_i_3),
        .RXMONITOROUT(gt3_rxmonitorout_out),
        .RXMONITORSEL(gt3_rxmonitorsel_in),
        .RXNOTINTABLE({NLW_gthe2_i_RXNOTINTABLE_UNCONNECTED[7:2],gt3_rx_not_in_table_out}),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b1,1'b1,1'b0}),
        .RXOSINTEN(1'b0),
        .RXOSINTHOLD(1'b1),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTSTARTED(NLW_gthe2_i_RXOSINTSTARTED_UNCONNECTED),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(NLW_gthe2_i_RXOSINTSTROBEDONE_UNCONNECTED),
        .RXOSINTSTROBESTARTED(NLW_gthe2_i_RXOSINTSTROBESTARTED_UNCONNECTED),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(gthe2_i_n_29),
        .RXOUTCLKFABRIC(NLW_gthe2_i_RXOUTCLKFABRIC_UNCONNECTED),
        .RXOUTCLKPCS(NLW_gthe2_i_RXOUTCLKPCS_UNCONNECTED),
        .RXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .RXPCOMMAALIGNEN(ena_comma_align_i_3),
        .RXPCSRESET(gt3_rxpcsreset_in),
        .RXPD({POWER_DOWN,POWER_DOWN}),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(NLW_gthe2_i_RXPHALIGNDONE_UNCONNECTED),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(NLW_gthe2_i_RXPHMONITOR_UNCONNECTED[4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(NLW_gthe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]),
        .RXPMARESET(gt3_rxpmareset_in),
        .RXPMARESETDONE(gt3_rxpmaresetdone_out),
        .RXPOLARITY(rx_polarity_i_3),
        .RXPRBSCNTRESET(gt3_rxprbscntreset_in),
        .RXPRBSERR(gt3_rxprbserr_out),
        .RXPRBSSEL(gt3_rxprbssel_in),
        .RXQPIEN(1'b0),
        .RXQPISENN(NLW_gthe2_i_RXQPISENN_UNCONNECTED),
        .RXQPISENP(NLW_gthe2_i_RXQPISENP_UNCONNECTED),
        .RXRATE({1'b0,1'b0,1'b0}),
        .RXRATEDONE(NLW_gthe2_i_RXRATEDONE_UNCONNECTED),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gt3_rxresetdone_out),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(NLW_gthe2_i_RXSTARTOFSEQ_UNCONNECTED[1:0]),
        .RXSTATUS(NLW_gthe2_i_RXSTATUS_UNCONNECTED[2:0]),
        .RXSYNCALLIN(1'b0),
        .RXSYNCDONE(NLW_gthe2_i_RXSYNCDONE_UNCONNECTED),
        .RXSYNCIN(1'b0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(NLW_gthe2_i_RXSYNCOUT_UNCONNECTED),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(gt_rxuserrdy_i),
        .RXUSRCLK(sync_clk),
        .RXUSRCLK2(user_clk),
        .RXVALID(NLW_gthe2_i_RXVALID_UNCONNECTED),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS({gthe2_i_n_112,gthe2_i_n_113}),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCOMFINISH(NLW_gthe2_i_TXCOMFINISH_UNCONNECTED),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXDEEMPH(1'b0),
        .TXDETECTRX(1'b0),
        .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b1),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(1'b0),
        .TXDLYSRESETDONE(NLW_gthe2_i_TXDLYSRESETDONE_UNCONNECTED),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(1'b0),
        .TXGEARBOXREADY(NLW_gthe2_i_TXGEARBOXREADY_UNCONNECTED),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(1'b0),
        .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXMARGIN({1'b0,1'b0,1'b0}),
        .TXOUTCLK(gthe2_i_n_45),
        .TXOUTCLKFABRIC(gthe2_i_n_46),
        .TXOUTCLKPCS(gthe2_i_n_47),
        .TXOUTCLKSEL({1'b0,1'b1,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD({POWER_DOWN,POWER_DOWN}),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(1'b0),
        .TXPHALIGNDONE(NLW_gthe2_i_TXPHALIGNDONE_UNCONNECTED),
        .TXPHALIGNEN(1'b0),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(1'b0),
        .TXPHINITDONE(NLW_gthe2_i_TXPHINITDONE_UNCONNECTED),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b1),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(1'b0),
        .TXPMARESETDONE(NLW_gthe2_i_TXPMARESETDONE_UNCONNECTED),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(NLW_gthe2_i_TXQPISENN_UNCONNECTED),
        .TXQPISENP(NLW_gthe2_i_TXQPISENP_UNCONNECTED),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE({1'b0,1'b0,1'b0}),
        .TXRATEDONE(NLW_gthe2_i_TXRATEDONE_UNCONNECTED),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gthe2_i_n_54),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(1'b0),
        .TXSYNCDONE(NLW_gthe2_i_TXSYNCDONE_UNCONNECTED),
        .TXSYNCIN(1'b0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(NLW_gthe2_i_TXSYNCOUT_UNCONNECTED),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(1'b1),
        .TXUSRCLK(sync_clk),
        .TXUSRCLK2(user_clk));
  LUT3 #(
    .INIT(8'hFE)) 
    hard_err_flop_r_i_1__2
       (.I0(gt3_rxbufstatus_out[2]),
        .I1(bucket_full_r_11),
        .I2(gthe2_i_0),
        .O(hard_err_flop_r0_2));
  LUT5 #(
    .INIT(32'hFFFBEFFF)) 
    left_aligned_r_i_2__2
       (.I0(first_v_received_r_10),
        .I1(gthe2_i_1[0]),
        .I2(gthe2_i_1[1]),
        .I3(rx_char_is_k_i_6[1]),
        .I4(rx_char_is_k_i_6[0]),
        .O(first_v_received_r_reg));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    reset_count_r_i_2__2
       (.I0(gt3_rx_not_in_table_out[1]),
        .I1(gt3_rx_disp_err_out[1]),
        .I2(gtp_rx_reset_i_3),
        .I3(comma_over_two_cycles_r_9),
        .I4(gt3_rx_not_in_table_out[0]),
        .I5(gt3_rx_disp_err_out[0]),
        .O(gthe2_i_4));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[0]_i_2__2 
       (.I0(gt3_rx_not_in_table_out[0]),
        .I1(gt3_rx_disp_err_out[0]),
        .O(gthe2_i_5[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \soft_err_r[1]_i_1__2 
       (.I0(gt3_rx_not_in_table_out[1]),
        .I1(gt3_rx_disp_err_out[1]),
        .O(gthe2_i_5[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[0]_i_1__2 
       (.I0(rx_char_is_k_i_6[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_6[1]),
        .O(gthe2_i_3));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_control_bits_r[1]_i_1__2 
       (.I0(rx_char_is_k_i_6[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_char_is_k_i_6[0]),
        .O(gthe2_i_2));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[0]_i_1__2 
       (.I0(rx_data_i_48[7]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[15]),
        .O(gthe2_i_7[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[10]_i_1__2 
       (.I0(rx_data_i_48[13]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[5]),
        .O(gthe2_i_6[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[11]_i_1__2 
       (.I0(rx_data_i_48[12]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[4]),
        .O(gthe2_i_6[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[12]_i_1__2 
       (.I0(rx_data_i_48[11]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[3]),
        .O(gthe2_i_6[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[13]_i_1__2 
       (.I0(rx_data_i_48[10]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[2]),
        .O(gthe2_i_6[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[14]_i_1__2 
       (.I0(rx_data_i_48[9]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[1]),
        .O(gthe2_i_6[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[15]_i_1__2 
       (.I0(rx_data_i_48[8]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[0]),
        .O(gthe2_i_6[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[1]_i_1__2 
       (.I0(rx_data_i_48[6]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[14]),
        .O(gthe2_i_7[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[2]_i_1__2 
       (.I0(rx_data_i_48[5]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[13]),
        .O(gthe2_i_7[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[3]_i_1__2 
       (.I0(rx_data_i_48[4]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[12]),
        .O(gthe2_i_7[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[4]_i_1__2 
       (.I0(rx_data_i_48[3]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[11]),
        .O(gthe2_i_7[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[5]_i_1__2 
       (.I0(rx_data_i_48[2]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[10]),
        .O(gthe2_i_7[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[6]_i_1__2 
       (.I0(rx_data_i_48[1]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[9]),
        .O(gthe2_i_7[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[7]_i_1__2 
       (.I0(rx_data_i_48[0]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[8]),
        .O(gthe2_i_7[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[8]_i_1__2 
       (.I0(rx_data_i_48[15]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[7]),
        .O(gthe2_i_6[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \word_aligned_data_r[9]_i_1__2 
       (.I0(rx_data_i_48[14]),
        .I1(\word_aligned_control_bits_r_reg[1] ),
        .I2(rx_data_i_48[6]),
        .O(gthe2_i_6[6]));
endmodule

module aurora_rx_4l_64b_multi_gt
   (gt0_cplllock_out,
    DRPRDY_OUT,
    gt0_eyescandataerror_out,
    gt0_rxbyteisaligned_out,
    gthe2_i,
    CHBONDDONE_OUT,
    gt0_rxcommadet_out,
    gt0_rxpmaresetdone_out,
    gt0_rxprbserr_out,
    gt0_rxresetdone_out,
    gt0_dmonitorout_out,
    DRPDO_OUT,
    gt0_rxbufstatus_out,
    gt0_rxmonitorout_out,
    D,
    gt0_rx_disp_err_out,
    gt0_rx_not_in_table_out,
    gt1_cplllock_out,
    DRPRDY_OUT_LANE1,
    gt1_eyescandataerror_out,
    gt1_rxbyteisaligned_out,
    gthe2_i_0,
    CHBONDDONE_OUT_LANE1,
    gt1_rxcommadet_out,
    gt1_rxpmaresetdone_out,
    gt1_rxprbserr_out,
    gt1_rxresetdone_out,
    gt1_dmonitorout_out,
    DRPDO_OUT_LANE1,
    gt1_rxbufstatus_out,
    gt1_rxmonitorout_out,
    gthe2_i_1,
    gt1_rx_disp_err_out,
    gt1_rx_not_in_table_out,
    gt2_cplllock_out,
    DRPRDY_OUT_LANE2,
    gt2_eyescandataerror_out,
    gt2_rxbyteisaligned_out,
    gthe2_i_2,
    CHBONDDONE_OUT_LANE2,
    gt2_rxcommadet_out,
    gt2_rxpmaresetdone_out,
    gt2_rxprbserr_out,
    gt2_rxresetdone_out,
    TX_OUT_CLK,
    gt2_dmonitorout_out,
    DRPDO_OUT_LANE2,
    gt2_rxbufstatus_out,
    gt2_rxmonitorout_out,
    gthe2_i_3,
    gt2_rx_disp_err_out,
    gt2_rx_not_in_table_out,
    gt3_cplllock_out,
    DRPRDY_OUT_LANE3,
    gt3_eyescandataerror_out,
    gt3_rxbyteisaligned_out,
    gthe2_i_4,
    CHBONDDONE_OUT_LANE3,
    gt3_rxcommadet_out,
    gt3_rxpmaresetdone_out,
    gt3_rxprbserr_out,
    gt3_rxresetdone_out,
    gt3_dmonitorout_out,
    DRPDO_OUT_LANE3,
    gt3_rxbufstatus_out,
    gt3_rxmonitorout_out,
    gthe2_i_5,
    gt3_rx_disp_err_out,
    gt3_rx_not_in_table_out,
    gthe2_i_6,
    gthe2_i_7,
    gthe2_i_8,
    gthe2_i_9,
    gthe2_i_10,
    gthe2_i_11,
    gthe2_i_12,
    gthe2_i_13,
    gthe2_i_14,
    gthe2_i_15,
    first_v_received_r_reg,
    hard_err_flop_r0,
    gthe2_i_16,
    gthe2_i_17,
    gthe2_i_18,
    gthe2_i_19,
    first_v_received_r_reg_0,
    hard_err_flop_r0_0,
    gthe2_i_20,
    gthe2_i_21,
    gthe2_i_22,
    gthe2_i_23,
    first_v_received_r_reg_1,
    hard_err_flop_r0_1,
    gthe2_i_24,
    gthe2_i_25,
    gthe2_i_26,
    gthe2_i_27,
    first_v_received_r_reg_2,
    hard_err_flop_r0_2,
    gthe2_i_28,
    gthe2_i_29,
    TX_LOCK,
    init_clk_in,
    drpclk_in,
    DRPEN_IN,
    DRPWE_IN,
    gt0_eyescanreset_in,
    gt0_eyescantrigger_in,
    RXN,
    RXP,
    gt_refclk1,
    SR,
    fsm_gt_rx_reset_t,
    gt_qpllclk_quad2_in,
    gt_qpllrefclk_quad2_in,
    gt0_rxbufreset_in,
    gt0_rxcdrhold_in,
    gt0_rxcdrovrden_in,
    gt0_rxdfelpmreset_in,
    gt0_rxlpmen_in,
    ena_comma_align_i_0,
    gt0_rxpcsreset_in,
    gt0_rxpmareset_in,
    rx_polarity_i_0,
    gt0_rxprbscntreset_in,
    gt_rxuserrdy_i,
    sync_clk,
    user_clk,
    DRPDI_IN,
    gt0_rxmonitorsel_in,
    POWER_DOWN,
    LOOPBACK,
    gt0_rxprbssel_in,
    DRPADDR_IN,
    DRPEN_IN_LANE1,
    DRPWE_IN_LANE1,
    gt1_eyescanreset_in,
    gt1_eyescantrigger_in,
    gt1_rxbufreset_in,
    gt1_rxcdrhold_in,
    gt1_rxcdrovrden_in,
    en_chan_sync_i,
    gt1_rxdfelpmreset_in,
    gt1_rxlpmen_in,
    ena_comma_align_i_1,
    gt1_rxpcsreset_in,
    gt1_rxpmareset_in,
    rx_polarity_i_1,
    gt1_rxprbscntreset_in,
    DRPDI_IN_LANE1,
    gt1_rxmonitorsel_in,
    gt1_rxprbssel_in,
    DRPADDR_IN_LANE1,
    DRPEN_IN_LANE2,
    DRPWE_IN_LANE2,
    gt2_eyescanreset_in,
    gt2_eyescantrigger_in,
    gt_qpllclk_quad3_in,
    gt_qpllrefclk_quad3_in,
    gt2_rxbufreset_in,
    gt2_rxcdrhold_in,
    gt2_rxcdrovrden_in,
    gt2_rxdfelpmreset_in,
    gt2_rxlpmen_in,
    ena_comma_align_i_2,
    gt2_rxpcsreset_in,
    gt2_rxpmareset_in,
    rx_polarity_i_2,
    gt2_rxprbscntreset_in,
    DRPDI_IN_LANE2,
    gt2_rxmonitorsel_in,
    gt2_rxprbssel_in,
    DRPADDR_IN_LANE2,
    DRPEN_IN_LANE3,
    DRPWE_IN_LANE3,
    gt3_eyescanreset_in,
    gt3_eyescantrigger_in,
    gt3_rxbufreset_in,
    gt3_rxcdrhold_in,
    gt3_rxcdrovrden_in,
    gt3_rxdfelpmreset_in,
    gt3_rxlpmen_in,
    ena_comma_align_i_3,
    gt3_rxpcsreset_in,
    gt3_rxpmareset_in,
    rx_polarity_i_3,
    gt3_rxprbscntreset_in,
    DRPDI_IN_LANE3,
    gt3_rxmonitorsel_in,
    gt3_rxprbssel_in,
    DRPADDR_IN_LANE3,
    flag2_reg,
    \word_aligned_control_bits_r_reg[1] ,
    \word_aligned_control_bits_r_reg[1]_0 ,
    \word_aligned_control_bits_r_reg[1]_1 ,
    \word_aligned_control_bits_r_reg[1]_2 ,
    gtp_rx_reset_i_0,
    comma_over_two_cycles_r,
    first_v_received_r,
    bucket_full_r,
    gtp_rx_reset_i_1,
    comma_over_two_cycles_r_3,
    first_v_received_r_4,
    bucket_full_r_5,
    gtp_rx_reset_i_2,
    comma_over_two_cycles_r_6,
    first_v_received_r_7,
    bucket_full_r_8,
    gtp_rx_reset_i_3,
    comma_over_two_cycles_r_9,
    first_v_received_r_10,
    bucket_full_r_11,
    cpll_reset_i);
  output gt0_cplllock_out;
  output DRPRDY_OUT;
  output gt0_eyescandataerror_out;
  output gt0_rxbyteisaligned_out;
  output gthe2_i;
  output CHBONDDONE_OUT;
  output gt0_rxcommadet_out;
  output gt0_rxpmaresetdone_out;
  output gt0_rxprbserr_out;
  output gt0_rxresetdone_out;
  output [14:0]gt0_dmonitorout_out;
  output [15:0]DRPDO_OUT;
  output [2:0]gt0_rxbufstatus_out;
  output [6:0]gt0_rxmonitorout_out;
  output [1:0]D;
  output [1:0]gt0_rx_disp_err_out;
  output [1:0]gt0_rx_not_in_table_out;
  output gt1_cplllock_out;
  output DRPRDY_OUT_LANE1;
  output gt1_eyescandataerror_out;
  output gt1_rxbyteisaligned_out;
  output gthe2_i_0;
  output CHBONDDONE_OUT_LANE1;
  output gt1_rxcommadet_out;
  output gt1_rxpmaresetdone_out;
  output gt1_rxprbserr_out;
  output gt1_rxresetdone_out;
  output [14:0]gt1_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE1;
  output [2:0]gt1_rxbufstatus_out;
  output [6:0]gt1_rxmonitorout_out;
  output [1:0]gthe2_i_1;
  output [1:0]gt1_rx_disp_err_out;
  output [1:0]gt1_rx_not_in_table_out;
  output gt2_cplllock_out;
  output DRPRDY_OUT_LANE2;
  output gt2_eyescandataerror_out;
  output gt2_rxbyteisaligned_out;
  output gthe2_i_2;
  output CHBONDDONE_OUT_LANE2;
  output gt2_rxcommadet_out;
  output gt2_rxpmaresetdone_out;
  output gt2_rxprbserr_out;
  output gt2_rxresetdone_out;
  output TX_OUT_CLK;
  output [14:0]gt2_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE2;
  output [2:0]gt2_rxbufstatus_out;
  output [6:0]gt2_rxmonitorout_out;
  output [1:0]gthe2_i_3;
  output [1:0]gt2_rx_disp_err_out;
  output [1:0]gt2_rx_not_in_table_out;
  output gt3_cplllock_out;
  output DRPRDY_OUT_LANE3;
  output gt3_eyescandataerror_out;
  output gt3_rxbyteisaligned_out;
  output gthe2_i_4;
  output CHBONDDONE_OUT_LANE3;
  output gt3_rxcommadet_out;
  output gt3_rxpmaresetdone_out;
  output gt3_rxprbserr_out;
  output gt3_rxresetdone_out;
  output [14:0]gt3_dmonitorout_out;
  output [15:0]DRPDO_OUT_LANE3;
  output [2:0]gt3_rxbufstatus_out;
  output [6:0]gt3_rxmonitorout_out;
  output [1:0]gthe2_i_5;
  output [1:0]gt3_rx_disp_err_out;
  output [1:0]gt3_rx_not_in_table_out;
  output gthe2_i_6;
  output gthe2_i_7;
  output gthe2_i_8;
  output gthe2_i_9;
  output gthe2_i_10;
  output gthe2_i_11;
  output gthe2_i_12;
  output gthe2_i_13;
  output gthe2_i_14;
  output [1:0]gthe2_i_15;
  output first_v_received_r_reg;
  output hard_err_flop_r0;
  output [7:0]gthe2_i_16;
  output [7:0]gthe2_i_17;
  output gthe2_i_18;
  output [1:0]gthe2_i_19;
  output first_v_received_r_reg_0;
  output hard_err_flop_r0_0;
  output [7:0]gthe2_i_20;
  output [7:0]gthe2_i_21;
  output gthe2_i_22;
  output [1:0]gthe2_i_23;
  output first_v_received_r_reg_1;
  output hard_err_flop_r0_1;
  output [7:0]gthe2_i_24;
  output [7:0]gthe2_i_25;
  output gthe2_i_26;
  output [1:0]gthe2_i_27;
  output first_v_received_r_reg_2;
  output hard_err_flop_r0_2;
  output [7:0]gthe2_i_28;
  output [7:0]gthe2_i_29;
  output TX_LOCK;
  input init_clk_in;
  input drpclk_in;
  input DRPEN_IN;
  input DRPWE_IN;
  input gt0_eyescanreset_in;
  input gt0_eyescantrigger_in;
  input [0:3]RXN;
  input [0:3]RXP;
  input gt_refclk1;
  input [0:0]SR;
  input fsm_gt_rx_reset_t;
  input gt_qpllclk_quad2_in;
  input gt_qpllrefclk_quad2_in;
  input gt0_rxbufreset_in;
  input gt0_rxcdrhold_in;
  input gt0_rxcdrovrden_in;
  input gt0_rxdfelpmreset_in;
  input gt0_rxlpmen_in;
  input ena_comma_align_i_0;
  input gt0_rxpcsreset_in;
  input gt0_rxpmareset_in;
  input rx_polarity_i_0;
  input gt0_rxprbscntreset_in;
  input gt_rxuserrdy_i;
  input sync_clk;
  input user_clk;
  input [15:0]DRPDI_IN;
  input [1:0]gt0_rxmonitorsel_in;
  input POWER_DOWN;
  input [2:0]LOOPBACK;
  input [2:0]gt0_rxprbssel_in;
  input [8:0]DRPADDR_IN;
  input DRPEN_IN_LANE1;
  input DRPWE_IN_LANE1;
  input gt1_eyescanreset_in;
  input gt1_eyescantrigger_in;
  input gt1_rxbufreset_in;
  input gt1_rxcdrhold_in;
  input gt1_rxcdrovrden_in;
  input en_chan_sync_i;
  input gt1_rxdfelpmreset_in;
  input gt1_rxlpmen_in;
  input ena_comma_align_i_1;
  input gt1_rxpcsreset_in;
  input gt1_rxpmareset_in;
  input rx_polarity_i_1;
  input gt1_rxprbscntreset_in;
  input [15:0]DRPDI_IN_LANE1;
  input [1:0]gt1_rxmonitorsel_in;
  input [2:0]gt1_rxprbssel_in;
  input [8:0]DRPADDR_IN_LANE1;
  input DRPEN_IN_LANE2;
  input DRPWE_IN_LANE2;
  input gt2_eyescanreset_in;
  input gt2_eyescantrigger_in;
  input gt_qpllclk_quad3_in;
  input gt_qpllrefclk_quad3_in;
  input gt2_rxbufreset_in;
  input gt2_rxcdrhold_in;
  input gt2_rxcdrovrden_in;
  input gt2_rxdfelpmreset_in;
  input gt2_rxlpmen_in;
  input ena_comma_align_i_2;
  input gt2_rxpcsreset_in;
  input gt2_rxpmareset_in;
  input rx_polarity_i_2;
  input gt2_rxprbscntreset_in;
  input [15:0]DRPDI_IN_LANE2;
  input [1:0]gt2_rxmonitorsel_in;
  input [2:0]gt2_rxprbssel_in;
  input [8:0]DRPADDR_IN_LANE2;
  input DRPEN_IN_LANE3;
  input DRPWE_IN_LANE3;
  input gt3_eyescanreset_in;
  input gt3_eyescantrigger_in;
  input gt3_rxbufreset_in;
  input gt3_rxcdrhold_in;
  input gt3_rxcdrovrden_in;
  input gt3_rxdfelpmreset_in;
  input gt3_rxlpmen_in;
  input ena_comma_align_i_3;
  input gt3_rxpcsreset_in;
  input gt3_rxpmareset_in;
  input rx_polarity_i_3;
  input gt3_rxprbscntreset_in;
  input [15:0]DRPDI_IN_LANE3;
  input [1:0]gt3_rxmonitorsel_in;
  input [2:0]gt3_rxprbssel_in;
  input [8:0]DRPADDR_IN_LANE3;
  input flag2_reg;
  input \word_aligned_control_bits_r_reg[1] ;
  input \word_aligned_control_bits_r_reg[1]_0 ;
  input \word_aligned_control_bits_r_reg[1]_1 ;
  input \word_aligned_control_bits_r_reg[1]_2 ;
  input gtp_rx_reset_i_0;
  input comma_over_two_cycles_r;
  input first_v_received_r;
  input bucket_full_r;
  input gtp_rx_reset_i_1;
  input comma_over_two_cycles_r_3;
  input first_v_received_r_4;
  input bucket_full_r_5;
  input gtp_rx_reset_i_2;
  input comma_over_two_cycles_r_6;
  input first_v_received_r_7;
  input bucket_full_r_8;
  input gtp_rx_reset_i_3;
  input comma_over_two_cycles_r_9;
  input first_v_received_r_10;
  input bucket_full_r_11;
  input cpll_reset_i;

  wire CHBONDDONE_OUT;
  wire CHBONDDONE_OUT_LANE1;
  wire CHBONDDONE_OUT_LANE2;
  wire CHBONDDONE_OUT_LANE3;
  wire [1:0]D;
  wire [8:0]DRPADDR_IN;
  wire [8:0]DRPADDR_IN_LANE1;
  wire [8:0]DRPADDR_IN_LANE2;
  wire [8:0]DRPADDR_IN_LANE3;
  wire [15:0]DRPDI_IN;
  wire [15:0]DRPDI_IN_LANE1;
  wire [15:0]DRPDI_IN_LANE2;
  wire [15:0]DRPDI_IN_LANE3;
  wire [15:0]DRPDO_OUT;
  wire [15:0]DRPDO_OUT_LANE1;
  wire [15:0]DRPDO_OUT_LANE2;
  wire [15:0]DRPDO_OUT_LANE3;
  wire DRPEN_IN;
  wire DRPEN_IN_LANE1;
  wire DRPEN_IN_LANE2;
  wire DRPEN_IN_LANE3;
  wire DRPRDY_OUT;
  wire DRPRDY_OUT_LANE1;
  wire DRPRDY_OUT_LANE2;
  wire DRPRDY_OUT_LANE3;
  wire DRPWE_IN;
  wire DRPWE_IN_LANE1;
  wire DRPWE_IN_LANE2;
  wire DRPWE_IN_LANE3;
  wire [2:0]LOOPBACK;
  wire POWER_DOWN;
  wire [0:3]RXN;
  wire [0:3]RXP;
  wire [0:0]SR;
  wire TX_LOCK;
  wire TX_OUT_CLK;
  wire bucket_full_r;
  wire bucket_full_r_11;
  wire bucket_full_r_5;
  wire bucket_full_r_8;
  wire [4:0]chbondo_LANE1;
  wire [4:0]chbondo_LANE2;
  wire comma_over_two_cycles_r;
  wire comma_over_two_cycles_r_3;
  wire comma_over_two_cycles_r_6;
  wire comma_over_two_cycles_r_9;
  wire cpll_reset_i;
  wire drpclk_in;
  wire en_chan_sync_i;
  wire ena_comma_align_i_0;
  wire ena_comma_align_i_1;
  wire ena_comma_align_i_2;
  wire ena_comma_align_i_3;
  wire first_v_received_r;
  wire first_v_received_r_10;
  wire first_v_received_r_4;
  wire first_v_received_r_7;
  wire first_v_received_r_reg;
  wire first_v_received_r_reg_0;
  wire first_v_received_r_reg_1;
  wire first_v_received_r_reg_2;
  wire flag2_reg;
  wire fsm_gt_rx_reset_t;
  wire gt0_cplllock_out;
  wire [14:0]gt0_dmonitorout_out;
  wire gt0_eyescandataerror_out;
  wire gt0_eyescanreset_in;
  wire gt0_eyescantrigger_in;
  wire [1:0]gt0_rx_disp_err_out;
  wire [1:0]gt0_rx_not_in_table_out;
  wire gt0_rxbufreset_in;
  wire [2:0]gt0_rxbufstatus_out;
  wire gt0_rxbyteisaligned_out;
  wire gt0_rxcdrhold_in;
  wire gt0_rxcdrovrden_in;
  wire gt0_rxcommadet_out;
  wire gt0_rxdfelpmreset_in;
  wire gt0_rxlpmen_in;
  wire [6:0]gt0_rxmonitorout_out;
  wire [1:0]gt0_rxmonitorsel_in;
  wire gt0_rxpcsreset_in;
  wire gt0_rxpmareset_in;
  wire gt0_rxpmaresetdone_out;
  wire gt0_rxprbscntreset_in;
  wire gt0_rxprbserr_out;
  wire [2:0]gt0_rxprbssel_in;
  wire gt0_rxresetdone_out;
  wire gt1_cplllock_out;
  wire [14:0]gt1_dmonitorout_out;
  wire gt1_eyescandataerror_out;
  wire gt1_eyescanreset_in;
  wire gt1_eyescantrigger_in;
  wire [1:0]gt1_rx_disp_err_out;
  wire [1:0]gt1_rx_not_in_table_out;
  wire gt1_rxbufreset_in;
  wire [2:0]gt1_rxbufstatus_out;
  wire gt1_rxbyteisaligned_out;
  wire gt1_rxcdrhold_in;
  wire gt1_rxcdrovrden_in;
  wire gt1_rxcommadet_out;
  wire gt1_rxdfelpmreset_in;
  wire gt1_rxlpmen_in;
  wire [6:0]gt1_rxmonitorout_out;
  wire [1:0]gt1_rxmonitorsel_in;
  wire gt1_rxpcsreset_in;
  wire gt1_rxpmareset_in;
  wire gt1_rxpmaresetdone_out;
  wire gt1_rxprbscntreset_in;
  wire gt1_rxprbserr_out;
  wire [2:0]gt1_rxprbssel_in;
  wire gt1_rxresetdone_out;
  wire gt2_cplllock_out;
  wire [14:0]gt2_dmonitorout_out;
  wire gt2_eyescandataerror_out;
  wire gt2_eyescanreset_in;
  wire gt2_eyescantrigger_in;
  wire [1:0]gt2_rx_disp_err_out;
  wire [1:0]gt2_rx_not_in_table_out;
  wire gt2_rxbufreset_in;
  wire [2:0]gt2_rxbufstatus_out;
  wire gt2_rxbyteisaligned_out;
  wire gt2_rxcdrhold_in;
  wire gt2_rxcdrovrden_in;
  wire gt2_rxcommadet_out;
  wire gt2_rxdfelpmreset_in;
  wire gt2_rxlpmen_in;
  wire [6:0]gt2_rxmonitorout_out;
  wire [1:0]gt2_rxmonitorsel_in;
  wire gt2_rxpcsreset_in;
  wire gt2_rxpmareset_in;
  wire gt2_rxpmaresetdone_out;
  wire gt2_rxprbscntreset_in;
  wire gt2_rxprbserr_out;
  wire [2:0]gt2_rxprbssel_in;
  wire gt2_rxresetdone_out;
  wire gt3_cplllock_out;
  wire [14:0]gt3_dmonitorout_out;
  wire gt3_eyescandataerror_out;
  wire gt3_eyescanreset_in;
  wire gt3_eyescantrigger_in;
  wire [1:0]gt3_rx_disp_err_out;
  wire [1:0]gt3_rx_not_in_table_out;
  wire gt3_rxbufreset_in;
  wire [2:0]gt3_rxbufstatus_out;
  wire gt3_rxbyteisaligned_out;
  wire gt3_rxcdrhold_in;
  wire gt3_rxcdrovrden_in;
  wire gt3_rxcommadet_out;
  wire gt3_rxdfelpmreset_in;
  wire gt3_rxlpmen_in;
  wire [6:0]gt3_rxmonitorout_out;
  wire [1:0]gt3_rxmonitorsel_in;
  wire gt3_rxpcsreset_in;
  wire gt3_rxpmareset_in;
  wire gt3_rxpmaresetdone_out;
  wire gt3_rxprbscntreset_in;
  wire gt3_rxprbserr_out;
  wire [2:0]gt3_rxprbssel_in;
  wire gt3_rxresetdone_out;
  wire gt_qpllclk_quad2_in;
  wire gt_qpllclk_quad3_in;
  wire gt_qpllrefclk_quad2_in;
  wire gt_qpllrefclk_quad3_in;
  wire gt_refclk1;
  wire gt_rxuserrdy_i;
  wire gthe2_i;
  wire gthe2_i_0;
  wire [1:0]gthe2_i_1;
  wire gthe2_i_10;
  wire gthe2_i_11;
  wire gthe2_i_12;
  wire gthe2_i_13;
  wire gthe2_i_14;
  wire [1:0]gthe2_i_15;
  wire [7:0]gthe2_i_16;
  wire [7:0]gthe2_i_17;
  wire gthe2_i_18;
  wire [1:0]gthe2_i_19;
  wire gthe2_i_2;
  wire [7:0]gthe2_i_20;
  wire [7:0]gthe2_i_21;
  wire gthe2_i_22;
  wire [1:0]gthe2_i_23;
  wire [7:0]gthe2_i_24;
  wire [7:0]gthe2_i_25;
  wire gthe2_i_26;
  wire [1:0]gthe2_i_27;
  wire [7:0]gthe2_i_28;
  wire [7:0]gthe2_i_29;
  wire [1:0]gthe2_i_3;
  wire gthe2_i_4;
  wire [1:0]gthe2_i_5;
  wire gthe2_i_6;
  wire gthe2_i_7;
  wire gthe2_i_8;
  wire gthe2_i_9;
  wire gtp_rx_reset_i_0;
  wire gtp_rx_reset_i_1;
  wire gtp_rx_reset_i_2;
  wire gtp_rx_reset_i_3;
  wire hard_err_flop_r0;
  wire hard_err_flop_r0_0;
  wire hard_err_flop_r0_1;
  wire hard_err_flop_r0_2;
  wire init_clk_in;
  wire rx_polarity_i_0;
  wire rx_polarity_i_1;
  wire rx_polarity_i_2;
  wire rx_polarity_i_3;
  wire sync_clk;
  wire user_clk;
  wire \word_aligned_control_bits_r_reg[1] ;
  wire \word_aligned_control_bits_r_reg[1]_0 ;
  wire \word_aligned_control_bits_r_reg[1]_1 ;
  wire \word_aligned_control_bits_r_reg[1]_2 ;

  aurora_rx_4l_64b_gt gt0_aurora_rx_4l_64b_i
       (.CHBONDDONE_OUT(CHBONDDONE_OUT),
        .D(D),
        .DRPADDR_IN(DRPADDR_IN),
        .DRPDI_IN(DRPDI_IN),
        .DRPDO_OUT(DRPDO_OUT),
        .DRPEN_IN(DRPEN_IN),
        .DRPRDY_OUT(DRPRDY_OUT),
        .DRPWE_IN(DRPWE_IN),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE1),
        .RXN(RXN[0]),
        .RXP(RXP[0]),
        .SR(SR),
        .bucket_full_r(bucket_full_r),
        .comma_over_two_cycles_r(comma_over_two_cycles_r),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .ena_comma_align_i_0(ena_comma_align_i_0),
        .first_v_received_r(first_v_received_r),
        .first_v_received_r_reg(first_v_received_r_reg),
        .flag2_reg_0(flag2_reg),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt0_dmonitorout_out(gt0_dmonitorout_out),
        .gt0_eyescandataerror_out(gt0_eyescandataerror_out),
        .gt0_eyescanreset_in(gt0_eyescanreset_in),
        .gt0_eyescantrigger_in(gt0_eyescantrigger_in),
        .gt0_rx_disp_err_out(gt0_rx_disp_err_out),
        .gt0_rx_not_in_table_out(gt0_rx_not_in_table_out),
        .gt0_rxbufreset_in(gt0_rxbufreset_in),
        .gt0_rxbufstatus_out(gt0_rxbufstatus_out),
        .gt0_rxbyteisaligned_out(gt0_rxbyteisaligned_out),
        .gt0_rxcdrhold_in(gt0_rxcdrhold_in),
        .gt0_rxcdrovrden_in(gt0_rxcdrovrden_in),
        .gt0_rxcommadet_out(gt0_rxcommadet_out),
        .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in),
        .gt0_rxlpmen_in(gt0_rxlpmen_in),
        .gt0_rxmonitorout_out(gt0_rxmonitorout_out),
        .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in),
        .gt0_rxpcsreset_in(gt0_rxpcsreset_in),
        .gt0_rxpmareset_in(gt0_rxpmareset_in),
        .gt0_rxpmaresetdone_out(gt0_rxpmaresetdone_out),
        .gt0_rxprbscntreset_in(gt0_rxprbscntreset_in),
        .gt0_rxprbserr_out(gt0_rxprbserr_out),
        .gt0_rxprbssel_in(gt0_rxprbssel_in),
        .gt0_rxresetdone_out(gt0_rxresetdone_out),
        .gt_qpllclk_quad2_in(gt_qpllclk_quad2_in),
        .gt_qpllrefclk_quad2_in(gt_qpllrefclk_quad2_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gthe2_i_0(gthe2_i),
        .gthe2_i_1(gthe2_i_6),
        .gthe2_i_2(gthe2_i_7),
        .gthe2_i_3(gthe2_i_14),
        .gthe2_i_4(gthe2_i_15),
        .gthe2_i_5(gthe2_i_16),
        .gthe2_i_6(gthe2_i_17),
        .gtp_rx_reset_i_0(gtp_rx_reset_i_0),
        .hard_err_flop_r0(hard_err_flop_r0),
        .init_clk_in(init_clk_in),
        .rx_polarity_i_0(rx_polarity_i_0),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[1] (\word_aligned_control_bits_r_reg[1] ));
  aurora_rx_4l_64b_gt_33 gt1_aurora_rx_4l_64b_i
       (.CHBONDDONE_OUT_LANE1(CHBONDDONE_OUT_LANE1),
        .DRPADDR_IN_LANE1(DRPADDR_IN_LANE1),
        .DRPDI_IN_LANE1(DRPDI_IN_LANE1),
        .DRPDO_OUT_LANE1(DRPDO_OUT_LANE1),
        .DRPEN_IN_LANE1(DRPEN_IN_LANE1),
        .DRPRDY_OUT_LANE1(DRPRDY_OUT_LANE1),
        .DRPWE_IN_LANE1(DRPWE_IN_LANE1),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE1),
        .RXN(RXN[1]),
        .RXP(RXP[1]),
        .SR(SR),
        .bucket_full_r_5(bucket_full_r_5),
        .comma_over_two_cycles_r_3(comma_over_two_cycles_r_3),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .en_chan_sync_i(en_chan_sync_i),
        .ena_comma_align_i_1(ena_comma_align_i_1),
        .first_v_received_r_4(first_v_received_r_4),
        .first_v_received_r_reg(first_v_received_r_reg_0),
        .flag2_reg_0(flag2_reg),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt1_dmonitorout_out(gt1_dmonitorout_out),
        .gt1_eyescandataerror_out(gt1_eyescandataerror_out),
        .gt1_eyescanreset_in(gt1_eyescanreset_in),
        .gt1_eyescantrigger_in(gt1_eyescantrigger_in),
        .gt1_rx_disp_err_out(gt1_rx_disp_err_out),
        .gt1_rx_not_in_table_out(gt1_rx_not_in_table_out),
        .gt1_rxbufreset_in(gt1_rxbufreset_in),
        .gt1_rxbufstatus_out(gt1_rxbufstatus_out),
        .gt1_rxbyteisaligned_out(gt1_rxbyteisaligned_out),
        .gt1_rxcdrhold_in(gt1_rxcdrhold_in),
        .gt1_rxcdrovrden_in(gt1_rxcdrovrden_in),
        .gt1_rxcommadet_out(gt1_rxcommadet_out),
        .gt1_rxdfelpmreset_in(gt1_rxdfelpmreset_in),
        .gt1_rxlpmen_in(gt1_rxlpmen_in),
        .gt1_rxmonitorout_out(gt1_rxmonitorout_out),
        .gt1_rxmonitorsel_in(gt1_rxmonitorsel_in),
        .gt1_rxpcsreset_in(gt1_rxpcsreset_in),
        .gt1_rxpmareset_in(gt1_rxpmareset_in),
        .gt1_rxpmaresetdone_out(gt1_rxpmaresetdone_out),
        .gt1_rxprbscntreset_in(gt1_rxprbscntreset_in),
        .gt1_rxprbserr_out(gt1_rxprbserr_out),
        .gt1_rxprbssel_in(gt1_rxprbssel_in),
        .gt1_rxresetdone_out(gt1_rxresetdone_out),
        .gt_qpllclk_quad2_in(gt_qpllclk_quad2_in),
        .gt_qpllrefclk_quad2_in(gt_qpllrefclk_quad2_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gthe2_i_0(gthe2_i_0),
        .gthe2_i_1(gthe2_i_1),
        .gthe2_i_2(gthe2_i_8),
        .gthe2_i_3(gthe2_i_9),
        .gthe2_i_4(gthe2_i_18),
        .gthe2_i_5(gthe2_i_19),
        .gthe2_i_6(gthe2_i_20),
        .gthe2_i_7(gthe2_i_21),
        .gtp_rx_reset_i_1(gtp_rx_reset_i_1),
        .hard_err_flop_r0_0(hard_err_flop_r0_0),
        .init_clk_in(init_clk_in),
        .rx_polarity_i_1(rx_polarity_i_1),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[1] (\word_aligned_control_bits_r_reg[1]_0 ));
  aurora_rx_4l_64b_gt_34 gt2_aurora_rx_4l_64b_i
       (.CHBONDDONE_OUT_LANE2(CHBONDDONE_OUT_LANE2),
        .DRPADDR_IN_LANE2(DRPADDR_IN_LANE2),
        .DRPDI_IN_LANE2(DRPDI_IN_LANE2),
        .DRPDO_OUT_LANE2(DRPDO_OUT_LANE2),
        .DRPEN_IN_LANE2(DRPEN_IN_LANE2),
        .DRPRDY_OUT_LANE2(DRPRDY_OUT_LANE2),
        .DRPWE_IN_LANE2(DRPWE_IN_LANE2),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE2),
        .RXN(RXN[2]),
        .RXP(RXP[2]),
        .SR(SR),
        .TX_LOCK(TX_LOCK),
        .TX_OUT_CLK(TX_OUT_CLK),
        .bucket_full_r_8(bucket_full_r_8),
        .comma_over_two_cycles_r_6(comma_over_two_cycles_r_6),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .ena_comma_align_i_2(ena_comma_align_i_2),
        .first_v_received_r_7(first_v_received_r_7),
        .first_v_received_r_reg(first_v_received_r_reg_1),
        .flag2_reg_0(flag2_reg),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt0_cplllock_out(gt0_cplllock_out),
        .gt1_cplllock_out(gt1_cplllock_out),
        .gt2_cplllock_out(gt2_cplllock_out),
        .gt2_dmonitorout_out(gt2_dmonitorout_out),
        .gt2_eyescandataerror_out(gt2_eyescandataerror_out),
        .gt2_eyescanreset_in(gt2_eyescanreset_in),
        .gt2_eyescantrigger_in(gt2_eyescantrigger_in),
        .gt2_rx_disp_err_out(gt2_rx_disp_err_out),
        .gt2_rx_not_in_table_out(gt2_rx_not_in_table_out),
        .gt2_rxbufreset_in(gt2_rxbufreset_in),
        .gt2_rxbufstatus_out(gt2_rxbufstatus_out),
        .gt2_rxbyteisaligned_out(gt2_rxbyteisaligned_out),
        .gt2_rxcdrhold_in(gt2_rxcdrhold_in),
        .gt2_rxcdrovrden_in(gt2_rxcdrovrden_in),
        .gt2_rxcommadet_out(gt2_rxcommadet_out),
        .gt2_rxdfelpmreset_in(gt2_rxdfelpmreset_in),
        .gt2_rxlpmen_in(gt2_rxlpmen_in),
        .gt2_rxmonitorout_out(gt2_rxmonitorout_out),
        .gt2_rxmonitorsel_in(gt2_rxmonitorsel_in),
        .gt2_rxpcsreset_in(gt2_rxpcsreset_in),
        .gt2_rxpmareset_in(gt2_rxpmareset_in),
        .gt2_rxpmaresetdone_out(gt2_rxpmaresetdone_out),
        .gt2_rxprbscntreset_in(gt2_rxprbscntreset_in),
        .gt2_rxprbserr_out(gt2_rxprbserr_out),
        .gt2_rxprbssel_in(gt2_rxprbssel_in),
        .gt2_rxresetdone_out(gt2_rxresetdone_out),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt_qpllclk_quad3_in(gt_qpllclk_quad3_in),
        .gt_qpllrefclk_quad3_in(gt_qpllrefclk_quad3_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gthe2_i_0(gthe2_i_2),
        .gthe2_i_1(gthe2_i_3),
        .gthe2_i_2(gthe2_i_10),
        .gthe2_i_3(gthe2_i_11),
        .gthe2_i_4(gthe2_i_22),
        .gthe2_i_5(gthe2_i_23),
        .gthe2_i_6(gthe2_i_24),
        .gthe2_i_7(gthe2_i_25),
        .gthe2_i_8(chbondo_LANE1),
        .gtp_rx_reset_i_2(gtp_rx_reset_i_2),
        .hard_err_flop_r0_1(hard_err_flop_r0_1),
        .init_clk_in(init_clk_in),
        .rx_polarity_i_2(rx_polarity_i_2),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[1] (\word_aligned_control_bits_r_reg[1]_1 ));
  aurora_rx_4l_64b_gt_35 gt3_aurora_rx_4l_64b_i
       (.CHBONDDONE_OUT_LANE3(CHBONDDONE_OUT_LANE3),
        .DRPADDR_IN_LANE3(DRPADDR_IN_LANE3),
        .DRPDI_IN_LANE3(DRPDI_IN_LANE3),
        .DRPDO_OUT_LANE3(DRPDO_OUT_LANE3),
        .DRPEN_IN_LANE3(DRPEN_IN_LANE3),
        .DRPRDY_OUT_LANE3(DRPRDY_OUT_LANE3),
        .DRPWE_IN_LANE3(DRPWE_IN_LANE3),
        .LOOPBACK(LOOPBACK),
        .POWER_DOWN(POWER_DOWN),
        .RXCHBONDO(chbondo_LANE2),
        .RXN(RXN[3]),
        .RXP(RXP[3]),
        .SR(SR),
        .bucket_full_r_11(bucket_full_r_11),
        .comma_over_two_cycles_r_9(comma_over_two_cycles_r_9),
        .cpll_reset_i(cpll_reset_i),
        .drpclk_in(drpclk_in),
        .ena_comma_align_i_3(ena_comma_align_i_3),
        .first_v_received_r_10(first_v_received_r_10),
        .first_v_received_r_reg(first_v_received_r_reg_2),
        .flag2_reg_0(flag2_reg),
        .fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .gt3_cplllock_out(gt3_cplllock_out),
        .gt3_dmonitorout_out(gt3_dmonitorout_out),
        .gt3_eyescandataerror_out(gt3_eyescandataerror_out),
        .gt3_eyescanreset_in(gt3_eyescanreset_in),
        .gt3_eyescantrigger_in(gt3_eyescantrigger_in),
        .gt3_rx_disp_err_out(gt3_rx_disp_err_out),
        .gt3_rx_not_in_table_out(gt3_rx_not_in_table_out),
        .gt3_rxbufreset_in(gt3_rxbufreset_in),
        .gt3_rxbufstatus_out(gt3_rxbufstatus_out),
        .gt3_rxbyteisaligned_out(gt3_rxbyteisaligned_out),
        .gt3_rxcdrhold_in(gt3_rxcdrhold_in),
        .gt3_rxcdrovrden_in(gt3_rxcdrovrden_in),
        .gt3_rxcommadet_out(gt3_rxcommadet_out),
        .gt3_rxdfelpmreset_in(gt3_rxdfelpmreset_in),
        .gt3_rxlpmen_in(gt3_rxlpmen_in),
        .gt3_rxmonitorout_out(gt3_rxmonitorout_out),
        .gt3_rxmonitorsel_in(gt3_rxmonitorsel_in),
        .gt3_rxpcsreset_in(gt3_rxpcsreset_in),
        .gt3_rxpmareset_in(gt3_rxpmareset_in),
        .gt3_rxpmaresetdone_out(gt3_rxpmaresetdone_out),
        .gt3_rxprbscntreset_in(gt3_rxprbscntreset_in),
        .gt3_rxprbserr_out(gt3_rxprbserr_out),
        .gt3_rxprbssel_in(gt3_rxprbssel_in),
        .gt3_rxresetdone_out(gt3_rxresetdone_out),
        .gt_qpllclk_quad3_in(gt_qpllclk_quad3_in),
        .gt_qpllrefclk_quad3_in(gt_qpllrefclk_quad3_in),
        .gt_refclk1(gt_refclk1),
        .gt_rxuserrdy_i(gt_rxuserrdy_i),
        .gthe2_i_0(gthe2_i_4),
        .gthe2_i_1(gthe2_i_5),
        .gthe2_i_2(gthe2_i_12),
        .gthe2_i_3(gthe2_i_13),
        .gthe2_i_4(gthe2_i_26),
        .gthe2_i_5(gthe2_i_27),
        .gthe2_i_6(gthe2_i_28),
        .gthe2_i_7(gthe2_i_29),
        .gtp_rx_reset_i_3(gtp_rx_reset_i_3),
        .hard_err_flop_r0_2(hard_err_flop_r0_2),
        .init_clk_in(init_clk_in),
        .rx_polarity_i_3(rx_polarity_i_3),
        .sync_clk(sync_clk),
        .user_clk(user_clk),
        .\word_aligned_control_bits_r_reg[1] (\word_aligned_control_bits_r_reg[1]_2 ));
endmodule

module aurora_rx_4l_64b_rx_startup_fsm
   (fsm_gt_rx_reset_t,
    gt_rxuserrdy_i,
    cpll_reset_i,
    CPLL_RESET_reg_0,
    in0,
    init_clk_in,
    user_clk,
    rxfsm_rxresetdone_r,
    AR,
    reset_time_out_reg_0);
  output fsm_gt_rx_reset_t;
  output gt_rxuserrdy_i;
  output cpll_reset_i;
  output CPLL_RESET_reg_0;
  input in0;
  input init_clk_in;
  input user_clk;
  input rxfsm_rxresetdone_r;
  input [0:0]AR;
  input reset_time_out_reg_0;

  wire [0:0]AR;
  wire CPLL_RESET_i_1_n_0;
  wire CPLL_RESET_reg_0;
  wire \FSM_sequential_rx_state[0]_i_2_n_0 ;
  wire \FSM_sequential_rx_state[0]_i_3_n_0 ;
  wire \FSM_sequential_rx_state[1]_i_2_n_0 ;
  wire \FSM_sequential_rx_state[1]_i_3_n_0 ;
  wire \FSM_sequential_rx_state[2]_i_2_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_10_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_11_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_12_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_13_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_3_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_5_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_6_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_8_n_0 ;
  wire \FSM_sequential_rx_state[3]_i_9_n_0 ;
  wire RXUSERRDY_i_1_n_0;
  wire check_tlock_max_i_1_n_0;
  wire check_tlock_max_reg_n_0;
  wire clear;
  wire cpll_reset_i;
  wire fsm_gt_rx_reset_t;
  wire gt_rxuserrdy_i;
  wire gtrxreset_i_i_1_n_0;
  wire in0;
  wire init_clk_in;
  wire init_wait_count;
  wire \init_wait_count[0]_i_1_n_0 ;
  wire \init_wait_count[6]_i_3_n_0 ;
  wire \init_wait_count[6]_i_4_n_0 ;
  wire [6:0]init_wait_count_reg;
  wire init_wait_done_i_1_n_0;
  wire init_wait_done_i_2_n_0;
  wire init_wait_done_reg_n_0;
  wire \mmcm_lock_count[2]_i_1_n_0 ;
  wire \mmcm_lock_count[3]_i_1_n_0 ;
  wire \mmcm_lock_count[4]_i_1_n_0 ;
  wire \mmcm_lock_count[5]_i_1_n_0 ;
  wire \mmcm_lock_count[6]_i_1_n_0 ;
  wire \mmcm_lock_count[7]_i_1_n_0 ;
  wire \mmcm_lock_count[8]_i_1_n_0 ;
  wire \mmcm_lock_count[9]_i_2_n_0 ;
  wire \mmcm_lock_count[9]_i_3_n_0 ;
  wire \mmcm_lock_count[9]_i_4_n_0 ;
  wire [9:0]mmcm_lock_count_reg;
  wire mmcm_lock_i;
  wire mmcm_lock_reclocked;
  wire mmcm_lock_reclocked_i_1_n_0;
  wire [6:1]p_0_in;
  wire p_0_in_0;
  wire [1:0]p_0_in__0;
  wire pll_reset_asserted_i_1_n_0;
  wire pll_reset_asserted_reg_n_0;
  wire reset_time_out_reg_0;
  wire reset_time_out_reg_n_0;
  wire run_phase_alignment_int;
  wire run_phase_alignment_int_i_1_n_0;
  wire run_phase_alignment_int_s2;
  wire run_phase_alignment_int_s3;
  wire rx_fsm_reset_done_int;
  wire rx_fsm_reset_done_int_0;
  wire rx_fsm_reset_done_int_i_1_n_0;
  wire rx_fsm_reset_done_int_i_3_n_0;
  wire rx_fsm_reset_done_int_i_4_n_0;
  wire rx_fsm_reset_done_int_i_5_n_0;
  wire rx_fsm_reset_done_int_s3;
  wire [3:0]rx_state;
  wire [3:0]rx_state__0;
  wire rxfsm_rxresetdone_r;
  wire rxpmaresetdone_i;
  wire rxpmaresetdone_rx_s;
  wire rxresetdone_s2;
  wire rxresetdone_s3;
  wire scndry_out;
  wire sel;
  wire sync_CPLLLOCK_cdc_sync_n_0;
  wire sync_CPLLLOCK_cdc_sync_n_1;
  wire sync_mmcm_lock_reclocked_cdc_sync_n_1;
  wire sync_rx_fsm_reset_done_int_cdc_sync_n_0;
  wire time_out_100us_i_1_n_0;
  wire time_out_100us_i_2_n_0;
  wire time_out_100us_i_3_n_0;
  wire time_out_100us_reg_n_0;
  wire time_out_1us_i_1_n_0;
  wire time_out_1us_i_2_n_0;
  wire time_out_1us_i_3_n_0;
  wire time_out_1us_i_4_n_0;
  wire time_out_1us_reg_n_0;
  wire time_out_2ms_i_1_n_0;
  wire time_out_2ms_i_2_n_0;
  wire time_out_2ms_i_3_n_0;
  wire time_out_2ms_i_4_n_0;
  wire time_out_2ms_i_5_n_0;
  wire time_out_2ms_reg_n_0;
  wire time_out_counter;
  wire \time_out_counter[0]_i_3_n_0 ;
  wire \time_out_counter[0]_i_4_n_0 ;
  wire \time_out_counter[0]_i_5_n_0 ;
  wire [18:0]time_out_counter_reg;
  wire \time_out_counter_reg[0]_i_2_n_0 ;
  wire \time_out_counter_reg[0]_i_2_n_1 ;
  wire \time_out_counter_reg[0]_i_2_n_2 ;
  wire \time_out_counter_reg[0]_i_2_n_3 ;
  wire \time_out_counter_reg[0]_i_2_n_4 ;
  wire \time_out_counter_reg[0]_i_2_n_5 ;
  wire \time_out_counter_reg[0]_i_2_n_6 ;
  wire \time_out_counter_reg[0]_i_2_n_7 ;
  wire \time_out_counter_reg[12]_i_1_n_0 ;
  wire \time_out_counter_reg[12]_i_1_n_1 ;
  wire \time_out_counter_reg[12]_i_1_n_2 ;
  wire \time_out_counter_reg[12]_i_1_n_3 ;
  wire \time_out_counter_reg[12]_i_1_n_4 ;
  wire \time_out_counter_reg[12]_i_1_n_5 ;
  wire \time_out_counter_reg[12]_i_1_n_6 ;
  wire \time_out_counter_reg[12]_i_1_n_7 ;
  wire \time_out_counter_reg[16]_i_1_n_2 ;
  wire \time_out_counter_reg[16]_i_1_n_3 ;
  wire \time_out_counter_reg[16]_i_1_n_5 ;
  wire \time_out_counter_reg[16]_i_1_n_6 ;
  wire \time_out_counter_reg[16]_i_1_n_7 ;
  wire \time_out_counter_reg[4]_i_1_n_0 ;
  wire \time_out_counter_reg[4]_i_1_n_1 ;
  wire \time_out_counter_reg[4]_i_1_n_2 ;
  wire \time_out_counter_reg[4]_i_1_n_3 ;
  wire \time_out_counter_reg[4]_i_1_n_4 ;
  wire \time_out_counter_reg[4]_i_1_n_5 ;
  wire \time_out_counter_reg[4]_i_1_n_6 ;
  wire \time_out_counter_reg[4]_i_1_n_7 ;
  wire \time_out_counter_reg[8]_i_1_n_0 ;
  wire \time_out_counter_reg[8]_i_1_n_1 ;
  wire \time_out_counter_reg[8]_i_1_n_2 ;
  wire \time_out_counter_reg[8]_i_1_n_3 ;
  wire \time_out_counter_reg[8]_i_1_n_4 ;
  wire \time_out_counter_reg[8]_i_1_n_5 ;
  wire \time_out_counter_reg[8]_i_1_n_6 ;
  wire \time_out_counter_reg[8]_i_1_n_7 ;
  wire time_out_wait_bypass;
  wire time_out_wait_bypass_i_1_n_0;
  wire time_out_wait_bypass_i_2_n_0;
  wire time_out_wait_bypass_i_3_n_0;
  wire time_out_wait_bypass_i_4_n_0;
  wire time_out_wait_bypass_s2;
  wire time_out_wait_bypass_s3;
  wire time_tlock_max;
  wire time_tlock_max1;
  wire time_tlock_max1_carry__0_i_1_n_0;
  wire time_tlock_max1_carry__0_i_2_n_0;
  wire time_tlock_max1_carry__0_i_3_n_0;
  wire time_tlock_max1_carry__0_i_4_n_0;
  wire time_tlock_max1_carry__0_i_5_n_0;
  wire time_tlock_max1_carry__0_n_0;
  wire time_tlock_max1_carry__0_n_1;
  wire time_tlock_max1_carry__0_n_2;
  wire time_tlock_max1_carry__0_n_3;
  wire time_tlock_max1_carry__1_i_1_n_0;
  wire time_tlock_max1_carry__1_i_2_n_0;
  wire time_tlock_max1_carry__1_i_3_n_0;
  wire time_tlock_max1_carry__1_n_3;
  wire time_tlock_max1_carry_i_1_n_0;
  wire time_tlock_max1_carry_i_2_n_0;
  wire time_tlock_max1_carry_i_3_n_0;
  wire time_tlock_max1_carry_i_4_n_0;
  wire time_tlock_max1_carry_i_5_n_0;
  wire time_tlock_max1_carry_n_0;
  wire time_tlock_max1_carry_n_1;
  wire time_tlock_max1_carry_n_2;
  wire time_tlock_max1_carry_n_3;
  wire time_tlock_max_i_1_n_0;
  wire user_clk;
  wire \wait_bypass_count[0]_i_2_n_0 ;
  wire \wait_bypass_count[0]_i_4_n_0 ;
  wire [12:0]wait_bypass_count_reg;
  wire \wait_bypass_count_reg[0]_i_3_n_0 ;
  wire \wait_bypass_count_reg[0]_i_3_n_1 ;
  wire \wait_bypass_count_reg[0]_i_3_n_2 ;
  wire \wait_bypass_count_reg[0]_i_3_n_3 ;
  wire \wait_bypass_count_reg[0]_i_3_n_4 ;
  wire \wait_bypass_count_reg[0]_i_3_n_5 ;
  wire \wait_bypass_count_reg[0]_i_3_n_6 ;
  wire \wait_bypass_count_reg[0]_i_3_n_7 ;
  wire \wait_bypass_count_reg[12]_i_1_n_7 ;
  wire \wait_bypass_count_reg[4]_i_1_n_0 ;
  wire \wait_bypass_count_reg[4]_i_1_n_1 ;
  wire \wait_bypass_count_reg[4]_i_1_n_2 ;
  wire \wait_bypass_count_reg[4]_i_1_n_3 ;
  wire \wait_bypass_count_reg[4]_i_1_n_4 ;
  wire \wait_bypass_count_reg[4]_i_1_n_5 ;
  wire \wait_bypass_count_reg[4]_i_1_n_6 ;
  wire \wait_bypass_count_reg[4]_i_1_n_7 ;
  wire \wait_bypass_count_reg[8]_i_1_n_0 ;
  wire \wait_bypass_count_reg[8]_i_1_n_1 ;
  wire \wait_bypass_count_reg[8]_i_1_n_2 ;
  wire \wait_bypass_count_reg[8]_i_1_n_3 ;
  wire \wait_bypass_count_reg[8]_i_1_n_4 ;
  wire \wait_bypass_count_reg[8]_i_1_n_5 ;
  wire \wait_bypass_count_reg[8]_i_1_n_6 ;
  wire \wait_bypass_count_reg[8]_i_1_n_7 ;
  wire [0:0]wait_time_cnt0;
  wire \wait_time_cnt[1]_i_1_n_0 ;
  wire \wait_time_cnt[2]_i_1_n_0 ;
  wire \wait_time_cnt[3]_i_1_n_0 ;
  wire \wait_time_cnt[4]_i_1_n_0 ;
  wire \wait_time_cnt[5]_i_1_n_0 ;
  wire \wait_time_cnt[6]_i_1_n_0 ;
  wire \wait_time_cnt[6]_i_3_n_0 ;
  wire \wait_time_cnt[6]_i_4_n_0 ;
  wire [6:0]wait_time_cnt_reg;
  wire [3:2]\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED ;
  wire [3:0]NLW_time_tlock_max1_carry_O_UNCONNECTED;
  wire [3:0]NLW_time_tlock_max1_carry__0_O_UNCONNECTED;
  wire [3:2]NLW_time_tlock_max1_carry__1_CO_UNCONNECTED;
  wire [3:0]NLW_time_tlock_max1_carry__1_O_UNCONNECTED;
  wire [3:0]\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED ;
  wire [3:1]\NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFFFFFDFF00000100)) 
    CPLL_RESET_i_1
       (.I0(pll_reset_asserted_reg_n_0),
        .I1(rx_state[3]),
        .I2(rx_state[2]),
        .I3(rx_state[0]),
        .I4(rx_state[1]),
        .I5(cpll_reset_i),
        .O(CPLL_RESET_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    CPLL_RESET_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(CPLL_RESET_i_1_n_0),
        .Q(cpll_reset_i),
        .R(AR));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'hFFEFEFEF)) 
    \FSM_sequential_rx_state[0]_i_1 
       (.I0(\FSM_sequential_rx_state[0]_i_2_n_0 ),
        .I1(\FSM_sequential_rx_state[0]_i_3_n_0 ),
        .I2(rx_state[0]),
        .I3(rx_state[1]),
        .I4(rx_state[3]),
        .O(rx_state__0[0]));
  LUT6 #(
    .INIT(64'h2222AAAA00300000)) 
    \FSM_sequential_rx_state[0]_i_2 
       (.I0(time_out_2ms_reg_n_0),
        .I1(reset_time_out_reg_n_0),
        .I2(time_tlock_max),
        .I3(rx_state[3]),
        .I4(rx_state[2]),
        .I5(rx_state[1]),
        .O(\FSM_sequential_rx_state[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT4 #(
    .INIT(16'h0200)) 
    \FSM_sequential_rx_state[0]_i_3 
       (.I0(rx_state[3]),
        .I1(reset_time_out_reg_n_0),
        .I2(gt_rxuserrdy_i),
        .I3(time_out_100us_reg_n_0),
        .O(\FSM_sequential_rx_state[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF24200400)) 
    \FSM_sequential_rx_state[1]_i_1 
       (.I0(rx_state[0]),
        .I1(rx_state[1]),
        .I2(rx_state[3]),
        .I3(rx_state[2]),
        .I4(\FSM_sequential_rx_state[1]_i_2_n_0 ),
        .I5(\FSM_sequential_rx_state[1]_i_3_n_0 ),
        .O(rx_state__0[1]));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_rx_state[1]_i_2 
       (.I0(gt_rxuserrdy_i),
        .I1(time_out_100us_reg_n_0),
        .O(\FSM_sequential_rx_state[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000AABF000F0000)) 
    \FSM_sequential_rx_state[1]_i_3 
       (.I0(reset_time_out_reg_n_0),
        .I1(time_tlock_max),
        .I2(rx_state[2]),
        .I3(rx_state[3]),
        .I4(rx_state[1]),
        .I5(rx_state[0]),
        .O(\FSM_sequential_rx_state[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h010C0C0C01000C0C)) 
    \FSM_sequential_rx_state[2]_i_1 
       (.I0(time_out_2ms_reg_n_0),
        .I1(rx_state[2]),
        .I2(rx_state[3]),
        .I3(rx_state[1]),
        .I4(rx_state[0]),
        .I5(\FSM_sequential_rx_state[2]_i_2_n_0 ),
        .O(rx_state__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_rx_state[2]_i_2 
       (.I0(reset_time_out_reg_n_0),
        .I1(time_tlock_max),
        .O(\FSM_sequential_rx_state[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_rx_state[3]_i_10 
       (.I0(reset_time_out_reg_n_0),
        .I1(time_out_2ms_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_rx_state[3]_i_11 
       (.I0(rx_state[2]),
        .I1(rx_state[3]),
        .O(\FSM_sequential_rx_state[3]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h000000008F888888)) 
    \FSM_sequential_rx_state[3]_i_12 
       (.I0(rx_state[3]),
        .I1(gt_rxuserrdy_i),
        .I2(rx_state[0]),
        .I3(rx_state[2]),
        .I4(reset_time_out_reg_0),
        .I5(rx_state[1]),
        .O(\FSM_sequential_rx_state[3]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_rx_state[3]_i_13 
       (.I0(rx_state[1]),
        .I1(rx_state[0]),
        .O(\FSM_sequential_rx_state[3]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAAAEAEFAAAA)) 
    \FSM_sequential_rx_state[3]_i_2 
       (.I0(\FSM_sequential_rx_state[3]_i_8_n_0 ),
        .I1(\FSM_sequential_rx_state[3]_i_9_n_0 ),
        .I2(rx_state[0]),
        .I3(time_out_wait_bypass_s3),
        .I4(rx_state[3]),
        .I5(rx_state[1]),
        .O(rx_state__0[3]));
  LUT6 #(
    .INIT(64'h000000000F440000)) 
    \FSM_sequential_rx_state[3]_i_3 
       (.I0(\FSM_sequential_rx_state[2]_i_2_n_0 ),
        .I1(rx_state[2]),
        .I2(\FSM_sequential_rx_state[3]_i_10_n_0 ),
        .I3(rx_state[1]),
        .I4(rx_state[0]),
        .I5(rx_state[3]),
        .O(\FSM_sequential_rx_state[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAEAFFAAAAEA)) 
    \FSM_sequential_rx_state[3]_i_5 
       (.I0(\FSM_sequential_rx_state[3]_i_12_n_0 ),
        .I1(mmcm_lock_reclocked),
        .I2(rx_state[2]),
        .I3(rx_state[3]),
        .I4(\FSM_sequential_rx_state[3]_i_13_n_0 ),
        .I5(gt_rxuserrdy_i),
        .O(\FSM_sequential_rx_state[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAAA)) 
    \FSM_sequential_rx_state[3]_i_6 
       (.I0(\FSM_sequential_rx_state[0]_i_3_n_0 ),
        .I1(\wait_time_cnt[6]_i_4_n_0 ),
        .I2(wait_time_cnt_reg[6]),
        .I3(rx_state[3]),
        .I4(rx_state[0]),
        .I5(rx_state[1]),
        .O(\FSM_sequential_rx_state[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'h80800080)) 
    \FSM_sequential_rx_state[3]_i_8 
       (.I0(rx_state[0]),
        .I1(rx_state[1]),
        .I2(rx_state[2]),
        .I3(time_out_2ms_reg_n_0),
        .I4(reset_time_out_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_rx_state[3]_i_9 
       (.I0(time_out_100us_reg_n_0),
        .I1(gt_rxuserrdy_i),
        .I2(reset_time_out_reg_n_0),
        .O(\FSM_sequential_rx_state[3]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[0] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[0]),
        .Q(rx_state[0]),
        .R(AR));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[1] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[1]),
        .Q(rx_state[1]),
        .R(AR));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[2] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[2]),
        .Q(rx_state[2]),
        .R(AR));
  (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_rx_state_reg[3] 
       (.C(init_clk_in),
        .CE(sync_CPLLLOCK_cdc_sync_n_0),
        .D(rx_state__0[3]),
        .Q(rx_state[3]),
        .R(AR));
  LUT5 #(
    .INIT(32'hFFFB4000)) 
    RXUSERRDY_i_1
       (.I0(rx_state[3]),
        .I1(rx_state[0]),
        .I2(rx_state[2]),
        .I3(rx_state[1]),
        .I4(gt_rxuserrdy_i),
        .O(RXUSERRDY_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    RXUSERRDY_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(RXUSERRDY_i_1_n_0),
        .Q(gt_rxuserrdy_i),
        .R(AR));
  LUT5 #(
    .INIT(32'hFFFB0008)) 
    check_tlock_max_i_1
       (.I0(rx_state[2]),
        .I1(rx_state[0]),
        .I2(rx_state[1]),
        .I3(rx_state[3]),
        .I4(check_tlock_max_reg_n_0),
        .O(check_tlock_max_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    check_tlock_max_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(check_tlock_max_i_1_n_0),
        .Q(check_tlock_max_reg_n_0),
        .R(AR));
  LUT1 #(
    .INIT(2'h1)) 
    flag2_i_1__2
       (.I0(cpll_reset_i),
        .O(CPLL_RESET_reg_0));
  aurora_rx_4l_64b_cdc_sync__parameterized2_22 gtrxreset_cdc_sync
       (.fsm_gt_rx_reset_t(fsm_gt_rx_reset_t),
        .init_clk_in(init_clk_in),
        .out(scndry_out),
        .user_clk(user_clk));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'hFFEF0100)) 
    gtrxreset_i_i_1
       (.I0(rx_state[3]),
        .I1(rx_state[1]),
        .I2(rx_state[2]),
        .I3(rx_state[0]),
        .I4(fsm_gt_rx_reset_t),
        .O(gtrxreset_i_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gtrxreset_i_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(gtrxreset_i_i_1_n_0),
        .Q(fsm_gt_rx_reset_t),
        .R(AR));
  LUT1 #(
    .INIT(2'h1)) 
    \init_wait_count[0]_i_1 
       (.I0(init_wait_count_reg[0]),
        .O(\init_wait_count[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \init_wait_count[1]_i_1 
       (.I0(init_wait_count_reg[0]),
        .I1(init_wait_count_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \init_wait_count[2]_i_1 
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \init_wait_count[3]_i_1 
       (.I0(init_wait_count_reg[2]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[1]),
        .I3(init_wait_count_reg[3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \init_wait_count[4]_i_1 
       (.I0(init_wait_count_reg[3]),
        .I1(init_wait_count_reg[1]),
        .I2(init_wait_count_reg[0]),
        .I3(init_wait_count_reg[2]),
        .I4(init_wait_count_reg[4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \init_wait_count[5]_i_1 
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[2]),
        .I3(init_wait_count_reg[3]),
        .I4(init_wait_count_reg[4]),
        .I5(init_wait_count_reg[5]),
        .O(p_0_in[5]));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFFFFFFF)) 
    \init_wait_count[6]_i_1 
       (.I0(\init_wait_count[6]_i_3_n_0 ),
        .I1(init_wait_count_reg[3]),
        .I2(init_wait_count_reg[4]),
        .I3(init_wait_count_reg[5]),
        .I4(init_wait_count_reg[6]),
        .I5(init_wait_count_reg[0]),
        .O(init_wait_count));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \init_wait_count[6]_i_2 
       (.I0(\init_wait_count[6]_i_4_n_0 ),
        .I1(init_wait_count_reg[5]),
        .I2(init_wait_count_reg[4]),
        .I3(init_wait_count_reg[3]),
        .I4(init_wait_count_reg[6]),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \init_wait_count[6]_i_3 
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[2]),
        .O(\init_wait_count[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \init_wait_count[6]_i_4 
       (.I0(init_wait_count_reg[1]),
        .I1(init_wait_count_reg[0]),
        .I2(init_wait_count_reg[2]),
        .O(\init_wait_count[6]_i_4_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[0] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(\init_wait_count[0]_i_1_n_0 ),
        .Q(init_wait_count_reg[0]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[1] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[1]),
        .Q(init_wait_count_reg[1]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[2] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[2]),
        .Q(init_wait_count_reg[2]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[3] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[3]),
        .Q(init_wait_count_reg[3]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[4] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[4]),
        .Q(init_wait_count_reg[4]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[5] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[5]),
        .Q(init_wait_count_reg[5]));
  FDCE #(
    .INIT(1'b0)) 
    \init_wait_count_reg[6] 
       (.C(init_clk_in),
        .CE(init_wait_count),
        .CLR(AR),
        .D(p_0_in[6]),
        .Q(init_wait_count_reg[6]));
  LUT3 #(
    .INIT(8'hF8)) 
    init_wait_done_i_1
       (.I0(init_wait_count_reg[0]),
        .I1(init_wait_done_i_2_n_0),
        .I2(init_wait_done_reg_n_0),
        .O(init_wait_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    init_wait_done_i_2
       (.I0(init_wait_count_reg[4]),
        .I1(init_wait_count_reg[3]),
        .I2(init_wait_count_reg[1]),
        .I3(init_wait_count_reg[2]),
        .I4(init_wait_count_reg[5]),
        .I5(init_wait_count_reg[6]),
        .O(init_wait_done_i_2_n_0));
  FDCE #(
    .INIT(1'b0)) 
    init_wait_done_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .CLR(AR),
        .D(init_wait_done_i_1_n_0),
        .Q(init_wait_done_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \mmcm_lock_count[0]_i_1 
       (.I0(mmcm_lock_count_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \mmcm_lock_count[1]_i_1 
       (.I0(mmcm_lock_count_reg[0]),
        .I1(mmcm_lock_count_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \mmcm_lock_count[2]_i_1 
       (.I0(mmcm_lock_count_reg[1]),
        .I1(mmcm_lock_count_reg[0]),
        .I2(mmcm_lock_count_reg[2]),
        .O(\mmcm_lock_count[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \mmcm_lock_count[3]_i_1 
       (.I0(mmcm_lock_count_reg[2]),
        .I1(mmcm_lock_count_reg[0]),
        .I2(mmcm_lock_count_reg[1]),
        .I3(mmcm_lock_count_reg[3]),
        .O(\mmcm_lock_count[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \mmcm_lock_count[4]_i_1 
       (.I0(mmcm_lock_count_reg[3]),
        .I1(mmcm_lock_count_reg[1]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[2]),
        .I4(mmcm_lock_count_reg[4]),
        .O(\mmcm_lock_count[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \mmcm_lock_count[5]_i_1 
       (.I0(mmcm_lock_count_reg[4]),
        .I1(mmcm_lock_count_reg[2]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[1]),
        .I4(mmcm_lock_count_reg[3]),
        .I5(mmcm_lock_count_reg[5]),
        .O(\mmcm_lock_count[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \mmcm_lock_count[6]_i_1 
       (.I0(\mmcm_lock_count[9]_i_4_n_0 ),
        .I1(mmcm_lock_count_reg[6]),
        .O(\mmcm_lock_count[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \mmcm_lock_count[7]_i_1 
       (.I0(mmcm_lock_count_reg[6]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[7]),
        .O(\mmcm_lock_count[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \mmcm_lock_count[8]_i_1 
       (.I0(mmcm_lock_count_reg[7]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[6]),
        .I3(mmcm_lock_count_reg[8]),
        .O(\mmcm_lock_count[8]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hDFFFFFFF)) 
    \mmcm_lock_count[9]_i_2 
       (.I0(mmcm_lock_count_reg[7]),
        .I1(\mmcm_lock_count[9]_i_4_n_0 ),
        .I2(mmcm_lock_count_reg[6]),
        .I3(mmcm_lock_count_reg[8]),
        .I4(mmcm_lock_count_reg[9]),
        .O(\mmcm_lock_count[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \mmcm_lock_count[9]_i_3 
       (.I0(mmcm_lock_count_reg[8]),
        .I1(mmcm_lock_count_reg[6]),
        .I2(\mmcm_lock_count[9]_i_4_n_0 ),
        .I3(mmcm_lock_count_reg[7]),
        .I4(mmcm_lock_count_reg[9]),
        .O(\mmcm_lock_count[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \mmcm_lock_count[9]_i_4 
       (.I0(mmcm_lock_count_reg[4]),
        .I1(mmcm_lock_count_reg[2]),
        .I2(mmcm_lock_count_reg[0]),
        .I3(mmcm_lock_count_reg[1]),
        .I4(mmcm_lock_count_reg[3]),
        .I5(mmcm_lock_count_reg[5]),
        .O(\mmcm_lock_count[9]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[0] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[0]),
        .Q(mmcm_lock_count_reg[0]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[1] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(p_0_in__0[1]),
        .Q(mmcm_lock_count_reg[1]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[2] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[2]_i_1_n_0 ),
        .Q(mmcm_lock_count_reg[2]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[3] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[3]_i_1_n_0 ),
        .Q(mmcm_lock_count_reg[3]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[4] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[4]_i_1_n_0 ),
        .Q(mmcm_lock_count_reg[4]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[5] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[5]_i_1_n_0 ),
        .Q(mmcm_lock_count_reg[5]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[6] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[6]_i_1_n_0 ),
        .Q(mmcm_lock_count_reg[6]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[7] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[7]_i_1_n_0 ),
        .Q(mmcm_lock_count_reg[7]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[8] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[8]_i_1_n_0 ),
        .Q(mmcm_lock_count_reg[8]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  FDRE #(
    .INIT(1'b0)) 
    \mmcm_lock_count_reg[9] 
       (.C(init_clk_in),
        .CE(\mmcm_lock_count[9]_i_2_n_0 ),
        .D(\mmcm_lock_count[9]_i_3_n_0 ),
        .Q(mmcm_lock_count_reg[9]),
        .R(sync_mmcm_lock_reclocked_cdc_sync_n_1));
  LUT3 #(
    .INIT(8'hE0)) 
    mmcm_lock_reclocked_i_1
       (.I0(mmcm_lock_reclocked),
        .I1(p_0_in_0),
        .I2(mmcm_lock_i),
        .O(mmcm_lock_reclocked_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    mmcm_lock_reclocked_i_2
       (.I0(mmcm_lock_count_reg[9]),
        .I1(mmcm_lock_count_reg[8]),
        .I2(mmcm_lock_count_reg[6]),
        .I3(\mmcm_lock_count[9]_i_4_n_0 ),
        .I4(mmcm_lock_count_reg[7]),
        .O(p_0_in_0));
  FDRE #(
    .INIT(1'b0)) 
    mmcm_lock_reclocked_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(mmcm_lock_reclocked_i_1_n_0),
        .Q(mmcm_lock_reclocked),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFDFF0100)) 
    pll_reset_asserted_i_1
       (.I0(rx_state[1]),
        .I1(rx_state[2]),
        .I2(rx_state[3]),
        .I3(rx_state[0]),
        .I4(pll_reset_asserted_reg_n_0),
        .O(pll_reset_asserted_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pll_reset_asserted_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(pll_reset_asserted_i_1_n_0),
        .Q(pll_reset_asserted_reg_n_0),
        .R(AR));
  FDSE #(
    .INIT(1'b0)) 
    reset_time_out_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(sync_CPLLLOCK_cdc_sync_n_1),
        .Q(reset_time_out_reg_n_0),
        .S(AR));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT5 #(
    .INIT(32'hFEFF0010)) 
    run_phase_alignment_int_i_1
       (.I0(rx_state[2]),
        .I1(rx_state[1]),
        .I2(rx_state[3]),
        .I3(rx_state[0]),
        .I4(run_phase_alignment_int),
        .O(run_phase_alignment_int_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    run_phase_alignment_int_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(run_phase_alignment_int_i_1_n_0),
        .Q(run_phase_alignment_int),
        .R(AR));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    run_phase_alignment_int_s3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(run_phase_alignment_int_s2),
        .Q(run_phase_alignment_int_s3),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hABA8)) 
    rx_fsm_reset_done_int_i_1
       (.I0(rx_fsm_reset_done_int_0),
        .I1(rx_fsm_reset_done_int_i_3_n_0),
        .I2(rx_fsm_reset_done_int_i_4_n_0),
        .I3(rx_fsm_reset_done_int),
        .O(rx_fsm_reset_done_int_i_1_n_0));
  LUT5 #(
    .INIT(32'h00040000)) 
    rx_fsm_reset_done_int_i_2
       (.I0(rx_state[0]),
        .I1(time_out_1us_reg_n_0),
        .I2(rx_state[2]),
        .I3(reset_time_out_reg_n_0),
        .I4(gt_rxuserrdy_i),
        .O(rx_fsm_reset_done_int_0));
  LUT6 #(
    .INIT(64'h0400040004040400)) 
    rx_fsm_reset_done_int_i_3
       (.I0(\FSM_sequential_rx_state[3]_i_13_n_0 ),
        .I1(rx_state[3]),
        .I2(rx_state[2]),
        .I3(gt_rxuserrdy_i),
        .I4(time_out_100us_reg_n_0),
        .I5(reset_time_out_reg_n_0),
        .O(rx_fsm_reset_done_int_i_3_n_0));
  LUT6 #(
    .INIT(64'h0008000808080008)) 
    rx_fsm_reset_done_int_i_4
       (.I0(rx_fsm_reset_done_int_i_5_n_0),
        .I1(rx_state[1]),
        .I2(rx_state[0]),
        .I3(gt_rxuserrdy_i),
        .I4(time_out_1us_reg_n_0),
        .I5(reset_time_out_reg_n_0),
        .O(rx_fsm_reset_done_int_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rx_fsm_reset_done_int_i_5
       (.I0(rx_state[3]),
        .I1(rx_state[2]),
        .O(rx_fsm_reset_done_int_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rx_fsm_reset_done_int_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rx_fsm_reset_done_int_i_1_n_0),
        .Q(rx_fsm_reset_done_int),
        .R(AR));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    rx_fsm_reset_done_int_s3_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
        .Q(rx_fsm_reset_done_int_s3),
        .R(1'b0));
  FDCE #(
    .INIT(1'b0)) 
    rxpmaresetdone_i_reg
       (.C(user_clk),
        .CE(1'b1),
        .CLR(scndry_out),
        .D(rxpmaresetdone_rx_s),
        .Q(rxpmaresetdone_i));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    rxresetdone_s3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(rxresetdone_s2),
        .Q(rxresetdone_s3),
        .R(1'b0));
  aurora_rx_4l_64b_cdc_sync_23 sync_CPLLLOCK_cdc_sync
       (.E(sync_CPLLLOCK_cdc_sync_n_0),
        .\FSM_sequential_rx_state_reg[0] (\FSM_sequential_rx_state[3]_i_3_n_0 ),
        .\FSM_sequential_rx_state_reg[0]_0 (\FSM_sequential_rx_state[3]_i_6_n_0 ),
        .\FSM_sequential_rx_state_reg[0]_1 (time_out_2ms_reg_n_0),
        .\FSM_sequential_rx_state_reg[0]_2 (\FSM_sequential_rx_state[3]_i_11_n_0 ),
        .\FSM_sequential_rx_state_reg[0]_3 (pll_reset_asserted_reg_n_0),
        .\FSM_sequential_rx_state_reg[0]_4 (init_wait_done_reg_n_0),
        .\FSM_sequential_rx_state_reg[1] (sync_CPLLLOCK_cdc_sync_n_1),
        .Q(rx_state),
        .in0(in0),
        .init_clk_in(init_clk_in),
        .reset_time_out_reg(reset_time_out_reg_0),
        .reset_time_out_reg_0(\FSM_sequential_rx_state[3]_i_5_n_0 ),
        .reset_time_out_reg_1(reset_time_out_reg_n_0),
        .rxresetdone_s3(rxresetdone_s3));
  aurora_rx_4l_64b_cdc_sync_24 sync_QPLLLOCK_cdc_sync
       (.init_clk_in(init_clk_in));
  aurora_rx_4l_64b_cdc_sync__parameterized2_25 sync_RXRESETDONE_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(rxresetdone_s2),
        .rxfsm_rxresetdone_r(rxfsm_rxresetdone_r),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync_26 sync_mmcm_lock_reclocked_cdc_sync
       (.SR(sync_mmcm_lock_reclocked_cdc_sync_n_1),
        .init_clk_in(init_clk_in),
        .out(mmcm_lock_i));
  aurora_rx_4l_64b_cdc_sync__parameterized2_27 sync_pmaresetdone_fallingedge_detect_cdc_sync
       (.init_clk_in(init_clk_in),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync__parameterized2_28 sync_run_phase_alignment_int_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(run_phase_alignment_int_s2),
        .run_phase_alignment_int(run_phase_alignment_int),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync__parameterized2_29 sync_rx_fsm_reset_done_int_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(sync_rx_fsm_reset_done_int_cdc_sync_n_0),
        .rx_fsm_reset_done_int(rx_fsm_reset_done_int),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync__parameterized2_30 sync_rxpmaresetdone_cdc_sync
       (.init_clk_in(init_clk_in),
        .rxpmaresetdone_i(rxpmaresetdone_i),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync_31 sync_rxpmaresetdone_rx_s_cdc_sync
       (.out(rxpmaresetdone_rx_s),
        .user_clk(user_clk));
  aurora_rx_4l_64b_cdc_sync__parameterized2_32 sync_time_out_wait_bypass_cdc_sync
       (.init_clk_in(init_clk_in),
        .out(time_out_wait_bypass_s2),
        .time_out_wait_bypass(time_out_wait_bypass),
        .user_clk(user_clk));
  LUT6 #(
    .INIT(64'hFFFFFFFF00020000)) 
    time_out_100us_i_1
       (.I0(time_out_100us_i_2_n_0),
        .I1(time_out_counter_reg[4]),
        .I2(time_out_counter_reg[5]),
        .I3(time_out_2ms_i_3_n_0),
        .I4(time_out_100us_i_3_n_0),
        .I5(time_out_100us_reg_n_0),
        .O(time_out_100us_i_1_n_0));
  LUT5 #(
    .INIT(32'h00008000)) 
    time_out_100us_i_2
       (.I0(time_out_1us_i_4_n_0),
        .I1(time_out_counter_reg[6]),
        .I2(time_out_counter_reg[7]),
        .I3(time_out_counter_reg[2]),
        .I4(time_out_counter_reg[1]),
        .O(time_out_100us_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000200000000000)) 
    time_out_100us_i_3
       (.I0(time_out_counter_reg[12]),
        .I1(time_out_counter_reg[11]),
        .I2(time_out_counter_reg[8]),
        .I3(time_out_counter_reg[10]),
        .I4(time_out_counter_reg[18]),
        .I5(time_out_counter_reg[13]),
        .O(time_out_100us_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_100us_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_100us_i_1_n_0),
        .Q(time_out_100us_reg_n_0),
        .R(reset_time_out_reg_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000200)) 
    time_out_1us_i_1
       (.I0(time_out_1us_i_2_n_0),
        .I1(time_out_1us_i_3_n_0),
        .I2(time_out_counter_reg[0]),
        .I3(time_out_1us_i_4_n_0),
        .I4(time_out_2ms_i_5_n_0),
        .I5(time_out_1us_reg_n_0),
        .O(time_out_1us_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    time_out_1us_i_2
       (.I0(time_out_counter_reg[7]),
        .I1(time_out_counter_reg[9]),
        .I2(time_out_counter_reg[2]),
        .I3(time_out_counter_reg[3]),
        .I4(time_out_counter_reg[18]),
        .I5(time_out_counter_reg[11]),
        .O(time_out_1us_i_2_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    time_out_1us_i_3
       (.I0(time_out_counter_reg[4]),
        .I1(time_out_counter_reg[5]),
        .O(time_out_1us_i_3_n_0));
  LUT4 #(
    .INIT(16'h0001)) 
    time_out_1us_i_4
       (.I0(time_out_counter_reg[17]),
        .I1(time_out_counter_reg[16]),
        .I2(time_out_counter_reg[15]),
        .I3(time_out_counter_reg[14]),
        .O(time_out_1us_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_1us_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_1us_i_1_n_0),
        .Q(time_out_1us_reg_n_0),
        .R(reset_time_out_reg_n_0));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    time_out_2ms_i_1
       (.I0(time_out_2ms_i_2_n_0),
        .I1(time_out_2ms_i_3_n_0),
        .I2(time_out_2ms_i_4_n_0),
        .I3(time_out_2ms_i_5_n_0),
        .I4(time_out_2ms_reg_n_0),
        .O(time_out_2ms_i_1_n_0));
  LUT6 #(
    .INIT(64'h0020000000000000)) 
    time_out_2ms_i_2
       (.I0(time_out_counter_reg[15]),
        .I1(time_out_counter_reg[16]),
        .I2(time_out_counter_reg[11]),
        .I3(time_out_counter_reg[14]),
        .I4(time_out_counter_reg[18]),
        .I5(time_out_counter_reg[17]),
        .O(time_out_2ms_i_2_n_0));
  LUT3 #(
    .INIT(8'h7F)) 
    time_out_2ms_i_3
       (.I0(time_out_counter_reg[9]),
        .I1(time_out_counter_reg[3]),
        .I2(time_out_counter_reg[0]),
        .O(time_out_2ms_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    time_out_2ms_i_4
       (.I0(time_out_counter_reg[2]),
        .I1(time_out_counter_reg[4]),
        .I2(time_out_counter_reg[7]),
        .I3(time_out_counter_reg[5]),
        .O(time_out_2ms_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    time_out_2ms_i_5
       (.I0(time_out_counter_reg[12]),
        .I1(time_out_counter_reg[13]),
        .I2(time_out_counter_reg[8]),
        .I3(time_out_counter_reg[10]),
        .I4(time_out_counter_reg[1]),
        .I5(time_out_counter_reg[6]),
        .O(time_out_2ms_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_2ms_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_2ms_i_1_n_0),
        .Q(time_out_2ms_reg_n_0),
        .R(reset_time_out_reg_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    \time_out_counter[0]_i_1 
       (.I0(time_out_2ms_i_5_n_0),
        .I1(time_out_counter_reg[4]),
        .I2(\time_out_counter[0]_i_3_n_0 ),
        .I3(time_out_counter_reg[2]),
        .I4(time_out_2ms_i_3_n_0),
        .I5(\time_out_counter[0]_i_4_n_0 ),
        .O(time_out_counter));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \time_out_counter[0]_i_3 
       (.I0(time_out_counter_reg[5]),
        .I1(time_out_counter_reg[7]),
        .O(\time_out_counter[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF7FFFFFFFFF)) 
    \time_out_counter[0]_i_4 
       (.I0(time_out_counter_reg[17]),
        .I1(time_out_counter_reg[18]),
        .I2(time_out_counter_reg[15]),
        .I3(time_out_counter_reg[16]),
        .I4(time_out_counter_reg[14]),
        .I5(time_out_counter_reg[11]),
        .O(\time_out_counter[0]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \time_out_counter[0]_i_5 
       (.I0(time_out_counter_reg[0]),
        .O(\time_out_counter[0]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[0] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_7 ),
        .Q(time_out_counter_reg[0]),
        .R(reset_time_out_reg_n_0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[0]_i_2 
       (.CI(1'b0),
        .CO({\time_out_counter_reg[0]_i_2_n_0 ,\time_out_counter_reg[0]_i_2_n_1 ,\time_out_counter_reg[0]_i_2_n_2 ,\time_out_counter_reg[0]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\time_out_counter_reg[0]_i_2_n_4 ,\time_out_counter_reg[0]_i_2_n_5 ,\time_out_counter_reg[0]_i_2_n_6 ,\time_out_counter_reg[0]_i_2_n_7 }),
        .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[10] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_5 ),
        .Q(time_out_counter_reg[10]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[11] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_4 ),
        .Q(time_out_counter_reg[11]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[12] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_7 ),
        .Q(time_out_counter_reg[12]),
        .R(reset_time_out_reg_n_0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[12]_i_1 
       (.CI(\time_out_counter_reg[8]_i_1_n_0 ),
        .CO({\time_out_counter_reg[12]_i_1_n_0 ,\time_out_counter_reg[12]_i_1_n_1 ,\time_out_counter_reg[12]_i_1_n_2 ,\time_out_counter_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[12]_i_1_n_4 ,\time_out_counter_reg[12]_i_1_n_5 ,\time_out_counter_reg[12]_i_1_n_6 ,\time_out_counter_reg[12]_i_1_n_7 }),
        .S(time_out_counter_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[13] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_6 ),
        .Q(time_out_counter_reg[13]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[14] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_5 ),
        .Q(time_out_counter_reg[14]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[15] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[12]_i_1_n_4 ),
        .Q(time_out_counter_reg[15]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[16] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[16]_i_1_n_7 ),
        .Q(time_out_counter_reg[16]),
        .R(reset_time_out_reg_n_0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[16]_i_1 
       (.CI(\time_out_counter_reg[12]_i_1_n_0 ),
        .CO({\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED [3:2],\time_out_counter_reg[16]_i_1_n_2 ,\time_out_counter_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED [3],\time_out_counter_reg[16]_i_1_n_5 ,\time_out_counter_reg[16]_i_1_n_6 ,\time_out_counter_reg[16]_i_1_n_7 }),
        .S({1'b0,time_out_counter_reg[18:16]}));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[17] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[16]_i_1_n_6 ),
        .Q(time_out_counter_reg[17]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[18] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[16]_i_1_n_5 ),
        .Q(time_out_counter_reg[18]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[1] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_6 ),
        .Q(time_out_counter_reg[1]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[2] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_5 ),
        .Q(time_out_counter_reg[2]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[3] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[0]_i_2_n_4 ),
        .Q(time_out_counter_reg[3]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[4] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_7 ),
        .Q(time_out_counter_reg[4]),
        .R(reset_time_out_reg_n_0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[4]_i_1 
       (.CI(\time_out_counter_reg[0]_i_2_n_0 ),
        .CO({\time_out_counter_reg[4]_i_1_n_0 ,\time_out_counter_reg[4]_i_1_n_1 ,\time_out_counter_reg[4]_i_1_n_2 ,\time_out_counter_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[4]_i_1_n_4 ,\time_out_counter_reg[4]_i_1_n_5 ,\time_out_counter_reg[4]_i_1_n_6 ,\time_out_counter_reg[4]_i_1_n_7 }),
        .S(time_out_counter_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[5] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_6 ),
        .Q(time_out_counter_reg[5]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[6] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_5 ),
        .Q(time_out_counter_reg[6]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[7] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[4]_i_1_n_4 ),
        .Q(time_out_counter_reg[7]),
        .R(reset_time_out_reg_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[8] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_7 ),
        .Q(time_out_counter_reg[8]),
        .R(reset_time_out_reg_n_0));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \time_out_counter_reg[8]_i_1 
       (.CI(\time_out_counter_reg[4]_i_1_n_0 ),
        .CO({\time_out_counter_reg[8]_i_1_n_0 ,\time_out_counter_reg[8]_i_1_n_1 ,\time_out_counter_reg[8]_i_1_n_2 ,\time_out_counter_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\time_out_counter_reg[8]_i_1_n_4 ,\time_out_counter_reg[8]_i_1_n_5 ,\time_out_counter_reg[8]_i_1_n_6 ,\time_out_counter_reg[8]_i_1_n_7 }),
        .S(time_out_counter_reg[11:8]));
  FDRE #(
    .INIT(1'b0)) 
    \time_out_counter_reg[9] 
       (.C(init_clk_in),
        .CE(time_out_counter),
        .D(\time_out_counter_reg[8]_i_1_n_6 ),
        .Q(time_out_counter_reg[9]),
        .R(reset_time_out_reg_n_0));
  LUT4 #(
    .INIT(16'hAB00)) 
    time_out_wait_bypass_i_1
       (.I0(time_out_wait_bypass),
        .I1(rx_fsm_reset_done_int_s3),
        .I2(time_out_wait_bypass_i_2_n_0),
        .I3(run_phase_alignment_int_s3),
        .O(time_out_wait_bypass_i_1_n_0));
  LUT5 #(
    .INIT(32'hFBFFFFFF)) 
    time_out_wait_bypass_i_2
       (.I0(time_out_wait_bypass_i_3_n_0),
        .I1(wait_bypass_count_reg[1]),
        .I2(wait_bypass_count_reg[11]),
        .I3(wait_bypass_count_reg[0]),
        .I4(time_out_wait_bypass_i_4_n_0),
        .O(time_out_wait_bypass_i_2_n_0));
  LUT4 #(
    .INIT(16'hDFFF)) 
    time_out_wait_bypass_i_3
       (.I0(wait_bypass_count_reg[9]),
        .I1(wait_bypass_count_reg[4]),
        .I2(wait_bypass_count_reg[12]),
        .I3(wait_bypass_count_reg[2]),
        .O(time_out_wait_bypass_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    time_out_wait_bypass_i_4
       (.I0(wait_bypass_count_reg[5]),
        .I1(wait_bypass_count_reg[7]),
        .I2(wait_bypass_count_reg[3]),
        .I3(wait_bypass_count_reg[6]),
        .I4(wait_bypass_count_reg[10]),
        .I5(wait_bypass_count_reg[8]),
        .O(time_out_wait_bypass_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_out_wait_bypass_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(time_out_wait_bypass_i_1_n_0),
        .Q(time_out_wait_bypass),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    time_out_wait_bypass_s3_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_out_wait_bypass_s2),
        .Q(time_out_wait_bypass_s3),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 time_tlock_max1_carry
       (.CI(1'b0),
        .CO({time_tlock_max1_carry_n_0,time_tlock_max1_carry_n_1,time_tlock_max1_carry_n_2,time_tlock_max1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,time_tlock_max1_carry_i_1_n_0,1'b0,time_out_counter_reg[1]}),
        .O(NLW_time_tlock_max1_carry_O_UNCONNECTED[3:0]),
        .S({time_tlock_max1_carry_i_2_n_0,time_tlock_max1_carry_i_3_n_0,time_tlock_max1_carry_i_4_n_0,time_tlock_max1_carry_i_5_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 time_tlock_max1_carry__0
       (.CI(time_tlock_max1_carry_n_0),
        .CO({time_tlock_max1_carry__0_n_0,time_tlock_max1_carry__0_n_1,time_tlock_max1_carry__0_n_2,time_tlock_max1_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({time_tlock_max1_carry__0_i_1_n_0,1'b0,time_out_counter_reg[11],1'b0}),
        .O(NLW_time_tlock_max1_carry__0_O_UNCONNECTED[3:0]),
        .S({time_tlock_max1_carry__0_i_2_n_0,time_tlock_max1_carry__0_i_3_n_0,time_tlock_max1_carry__0_i_4_n_0,time_tlock_max1_carry__0_i_5_n_0}));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry__0_i_1
       (.I0(time_out_counter_reg[14]),
        .I1(time_out_counter_reg[15]),
        .O(time_tlock_max1_carry__0_i_1_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry__0_i_2
       (.I0(time_out_counter_reg[15]),
        .I1(time_out_counter_reg[14]),
        .O(time_tlock_max1_carry__0_i_2_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    time_tlock_max1_carry__0_i_3
       (.I0(time_out_counter_reg[12]),
        .I1(time_out_counter_reg[13]),
        .O(time_tlock_max1_carry__0_i_3_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    time_tlock_max1_carry__0_i_4
       (.I0(time_out_counter_reg[10]),
        .I1(time_out_counter_reg[11]),
        .O(time_tlock_max1_carry__0_i_4_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    time_tlock_max1_carry__0_i_5
       (.I0(time_out_counter_reg[8]),
        .I1(time_out_counter_reg[9]),
        .O(time_tlock_max1_carry__0_i_5_n_0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 time_tlock_max1_carry__1
       (.CI(time_tlock_max1_carry__0_n_0),
        .CO({NLW_time_tlock_max1_carry__1_CO_UNCONNECTED[3:2],time_tlock_max1,time_tlock_max1_carry__1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,time_out_counter_reg[18],time_tlock_max1_carry__1_i_1_n_0}),
        .O(NLW_time_tlock_max1_carry__1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,time_tlock_max1_carry__1_i_2_n_0,time_tlock_max1_carry__1_i_3_n_0}));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry__1_i_1
       (.I0(time_out_counter_reg[16]),
        .I1(time_out_counter_reg[17]),
        .O(time_tlock_max1_carry__1_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    time_tlock_max1_carry__1_i_2
       (.I0(time_out_counter_reg[18]),
        .O(time_tlock_max1_carry__1_i_2_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry__1_i_3
       (.I0(time_out_counter_reg[17]),
        .I1(time_out_counter_reg[16]),
        .O(time_tlock_max1_carry__1_i_3_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    time_tlock_max1_carry_i_1
       (.I0(time_out_counter_reg[4]),
        .I1(time_out_counter_reg[5]),
        .O(time_tlock_max1_carry_i_1_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    time_tlock_max1_carry_i_2
       (.I0(time_out_counter_reg[6]),
        .I1(time_out_counter_reg[7]),
        .O(time_tlock_max1_carry_i_2_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    time_tlock_max1_carry_i_3
       (.I0(time_out_counter_reg[5]),
        .I1(time_out_counter_reg[4]),
        .O(time_tlock_max1_carry_i_3_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    time_tlock_max1_carry_i_4
       (.I0(time_out_counter_reg[2]),
        .I1(time_out_counter_reg[3]),
        .O(time_tlock_max1_carry_i_4_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    time_tlock_max1_carry_i_5
       (.I0(time_out_counter_reg[0]),
        .I1(time_out_counter_reg[1]),
        .O(time_tlock_max1_carry_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    time_tlock_max_i_1
       (.I0(time_tlock_max1),
        .I1(check_tlock_max_reg_n_0),
        .I2(time_tlock_max),
        .O(time_tlock_max_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    time_tlock_max_reg
       (.C(init_clk_in),
        .CE(1'b1),
        .D(time_tlock_max_i_1_n_0),
        .Q(time_tlock_max),
        .R(reset_time_out_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_bypass_count[0]_i_1 
       (.I0(run_phase_alignment_int_s3),
        .O(clear));
  LUT2 #(
    .INIT(4'h2)) 
    \wait_bypass_count[0]_i_2 
       (.I0(time_out_wait_bypass_i_2_n_0),
        .I1(rx_fsm_reset_done_int_s3),
        .O(\wait_bypass_count[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_bypass_count[0]_i_4 
       (.I0(wait_bypass_count_reg[0]),
        .O(\wait_bypass_count[0]_i_4_n_0 ));
  FDRE \wait_bypass_count_reg[0] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_7 ),
        .Q(wait_bypass_count_reg[0]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[0]_i_3 
       (.CI(1'b0),
        .CO({\wait_bypass_count_reg[0]_i_3_n_0 ,\wait_bypass_count_reg[0]_i_3_n_1 ,\wait_bypass_count_reg[0]_i_3_n_2 ,\wait_bypass_count_reg[0]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\wait_bypass_count_reg[0]_i_3_n_4 ,\wait_bypass_count_reg[0]_i_3_n_5 ,\wait_bypass_count_reg[0]_i_3_n_6 ,\wait_bypass_count_reg[0]_i_3_n_7 }),
        .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_4_n_0 }));
  FDRE \wait_bypass_count_reg[10] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_5 ),
        .Q(wait_bypass_count_reg[10]),
        .R(clear));
  FDRE \wait_bypass_count_reg[11] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_4 ),
        .Q(wait_bypass_count_reg[11]),
        .R(clear));
  FDRE \wait_bypass_count_reg[12] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[12]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[12]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[12]_i_1 
       (.CI(\wait_bypass_count_reg[8]_i_1_n_0 ),
        .CO(\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_wait_bypass_count_reg[12]_i_1_O_UNCONNECTED [3:1],\wait_bypass_count_reg[12]_i_1_n_7 }),
        .S({1'b0,1'b0,1'b0,wait_bypass_count_reg[12]}));
  FDRE \wait_bypass_count_reg[1] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_6 ),
        .Q(wait_bypass_count_reg[1]),
        .R(clear));
  FDRE \wait_bypass_count_reg[2] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_5 ),
        .Q(wait_bypass_count_reg[2]),
        .R(clear));
  FDRE \wait_bypass_count_reg[3] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[0]_i_3_n_4 ),
        .Q(wait_bypass_count_reg[3]),
        .R(clear));
  FDRE \wait_bypass_count_reg[4] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[4]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[4]_i_1 
       (.CI(\wait_bypass_count_reg[0]_i_3_n_0 ),
        .CO({\wait_bypass_count_reg[4]_i_1_n_0 ,\wait_bypass_count_reg[4]_i_1_n_1 ,\wait_bypass_count_reg[4]_i_1_n_2 ,\wait_bypass_count_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\wait_bypass_count_reg[4]_i_1_n_4 ,\wait_bypass_count_reg[4]_i_1_n_5 ,\wait_bypass_count_reg[4]_i_1_n_6 ,\wait_bypass_count_reg[4]_i_1_n_7 }),
        .S(wait_bypass_count_reg[7:4]));
  FDRE \wait_bypass_count_reg[5] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_6 ),
        .Q(wait_bypass_count_reg[5]),
        .R(clear));
  FDRE \wait_bypass_count_reg[6] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_5 ),
        .Q(wait_bypass_count_reg[6]),
        .R(clear));
  FDRE \wait_bypass_count_reg[7] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[4]_i_1_n_4 ),
        .Q(wait_bypass_count_reg[7]),
        .R(clear));
  FDRE \wait_bypass_count_reg[8] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_7 ),
        .Q(wait_bypass_count_reg[8]),
        .R(clear));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \wait_bypass_count_reg[8]_i_1 
       (.CI(\wait_bypass_count_reg[4]_i_1_n_0 ),
        .CO({\wait_bypass_count_reg[8]_i_1_n_0 ,\wait_bypass_count_reg[8]_i_1_n_1 ,\wait_bypass_count_reg[8]_i_1_n_2 ,\wait_bypass_count_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\wait_bypass_count_reg[8]_i_1_n_4 ,\wait_bypass_count_reg[8]_i_1_n_5 ,\wait_bypass_count_reg[8]_i_1_n_6 ,\wait_bypass_count_reg[8]_i_1_n_7 }),
        .S(wait_bypass_count_reg[11:8]));
  FDRE \wait_bypass_count_reg[9] 
       (.C(user_clk),
        .CE(\wait_bypass_count[0]_i_2_n_0 ),
        .D(\wait_bypass_count_reg[8]_i_1_n_6 ),
        .Q(wait_bypass_count_reg[9]),
        .R(clear));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wait_time_cnt[0]_i_1 
       (.I0(wait_time_cnt_reg[0]),
        .O(wait_time_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_time_cnt[1]_i_1 
       (.I0(wait_time_cnt_reg[0]),
        .I1(wait_time_cnt_reg[1]),
        .O(\wait_time_cnt[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hE1)) 
    \wait_time_cnt[2]_i_1 
       (.I0(wait_time_cnt_reg[1]),
        .I1(wait_time_cnt_reg[0]),
        .I2(wait_time_cnt_reg[2]),
        .O(\wait_time_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \wait_time_cnt[3]_i_1 
       (.I0(wait_time_cnt_reg[2]),
        .I1(wait_time_cnt_reg[0]),
        .I2(wait_time_cnt_reg[1]),
        .I3(wait_time_cnt_reg[3]),
        .O(\wait_time_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \wait_time_cnt[4]_i_1 
       (.I0(wait_time_cnt_reg[3]),
        .I1(wait_time_cnt_reg[1]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[2]),
        .I4(wait_time_cnt_reg[4]),
        .O(\wait_time_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \wait_time_cnt[5]_i_1 
       (.I0(wait_time_cnt_reg[4]),
        .I1(wait_time_cnt_reg[2]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[1]),
        .I4(wait_time_cnt_reg[3]),
        .I5(wait_time_cnt_reg[5]),
        .O(\wait_time_cnt[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \wait_time_cnt[6]_i_1 
       (.I0(rx_state[0]),
        .I1(rx_state[1]),
        .I2(rx_state[3]),
        .O(\wait_time_cnt[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \wait_time_cnt[6]_i_2 
       (.I0(\wait_time_cnt[6]_i_4_n_0 ),
        .I1(wait_time_cnt_reg[6]),
        .O(sel));
  LUT2 #(
    .INIT(4'h9)) 
    \wait_time_cnt[6]_i_3 
       (.I0(\wait_time_cnt[6]_i_4_n_0 ),
        .I1(wait_time_cnt_reg[6]),
        .O(\wait_time_cnt[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wait_time_cnt[6]_i_4 
       (.I0(wait_time_cnt_reg[4]),
        .I1(wait_time_cnt_reg[2]),
        .I2(wait_time_cnt_reg[0]),
        .I3(wait_time_cnt_reg[1]),
        .I4(wait_time_cnt_reg[3]),
        .I5(wait_time_cnt_reg[5]),
        .O(\wait_time_cnt[6]_i_4_n_0 ));
  FDRE \wait_time_cnt_reg[0] 
       (.C(init_clk_in),
        .CE(sel),
        .D(wait_time_cnt0),
        .Q(wait_time_cnt_reg[0]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[1] 
       (.C(init_clk_in),
        .CE(sel),
        .D(\wait_time_cnt[1]_i_1_n_0 ),
        .Q(wait_time_cnt_reg[1]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[2] 
       (.C(init_clk_in),
        .CE(sel),
        .D(\wait_time_cnt[2]_i_1_n_0 ),
        .Q(wait_time_cnt_reg[2]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[3] 
       (.C(init_clk_in),
        .CE(sel),
        .D(\wait_time_cnt[3]_i_1_n_0 ),
        .Q(wait_time_cnt_reg[3]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDRE \wait_time_cnt_reg[4] 
       (.C(init_clk_in),
        .CE(sel),
        .D(\wait_time_cnt[4]_i_1_n_0 ),
        .Q(wait_time_cnt_reg[4]),
        .R(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[5] 
       (.C(init_clk_in),
        .CE(sel),
        .D(\wait_time_cnt[5]_i_1_n_0 ),
        .Q(wait_time_cnt_reg[5]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
  FDSE \wait_time_cnt_reg[6] 
       (.C(init_clk_in),
        .CE(sel),
        .D(\wait_time_cnt[6]_i_3_n_0 ),
        .Q(wait_time_cnt_reg[6]),
        .S(\wait_time_cnt[6]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
