// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Tue Sep  8 14:04:23 2020
// Host        : efex-vm2.cern.ch running 64-bit CentOS Linux release 7.8.2003 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/EKk3926z/0/atlas-l1calo-efex/RODFirmware/IP/bkpln_efex/aurora_rx_4l_64b/aurora_rx_4l_64b_stub.v
// Design      : aurora_rx_4l_64b
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module aurora_rx_4l_64b(m_axi_rx_tdata, m_axi_rx_tvalid, 
  m_axi_rx_tkeep, m_axi_rx_tlast, m_axi_ufc_rx_tdata, m_axi_ufc_rx_tkeep, 
  m_axi_ufc_rx_tvalid, m_axi_ufc_rx_tlast, rxp, rxn, gt_refclk1, frame_err, rx_hard_err, 
  soft_err, rx_lane_up, rx_channel_up, user_clk, sync_clk, rx_system_reset, power_down, loopback, 
  gt_reset, tx_lock, sys_reset_out, init_clk_in, rx_resetdone_out, link_reset_out, drpclk_in, 
  drpaddr_in, drpdi_in, drpdo_out, drpen_in, drprdy_out, drpwe_in, drpaddr_in_lane1, 
  drpdi_in_lane1, drpdo_out_lane1, drpen_in_lane1, drprdy_out_lane1, drpwe_in_lane1, 
  drpaddr_in_lane2, drpdi_in_lane2, drpdo_out_lane2, drpen_in_lane2, drprdy_out_lane2, 
  drpwe_in_lane2, drpaddr_in_lane3, drpdi_in_lane3, drpdo_out_lane3, drpen_in_lane3, 
  drprdy_out_lane3, drpwe_in_lane3, gt0_qplllock_in, gt0_qpllrefclklost_in, 
  gt0_qpllreset_out, gt1_qplllock_in, gt1_qpllrefclklost_in, gt1_qpllreset_out, 
  gt_qpllclk_quad2_in, gt_qpllrefclk_quad2_in, gt_qpllclk_quad3_in, 
  gt_qpllrefclk_quad3_in, tx_out_clk, pll_not_locked)
/* synthesis syn_black_box black_box_pad_pin="m_axi_rx_tdata[63:0],m_axi_rx_tvalid,m_axi_rx_tkeep[7:0],m_axi_rx_tlast,m_axi_ufc_rx_tdata[63:0],m_axi_ufc_rx_tkeep[7:0],m_axi_ufc_rx_tvalid,m_axi_ufc_rx_tlast,rxp[0:3],rxn[0:3],gt_refclk1,frame_err,rx_hard_err,soft_err,rx_lane_up[0:3],rx_channel_up,user_clk,sync_clk,rx_system_reset,power_down,loopback[2:0],gt_reset,tx_lock,sys_reset_out,init_clk_in,rx_resetdone_out,link_reset_out,drpclk_in,drpaddr_in[8:0],drpdi_in[15:0],drpdo_out[15:0],drpen_in,drprdy_out,drpwe_in,drpaddr_in_lane1[8:0],drpdi_in_lane1[15:0],drpdo_out_lane1[15:0],drpen_in_lane1,drprdy_out_lane1,drpwe_in_lane1,drpaddr_in_lane2[8:0],drpdi_in_lane2[15:0],drpdo_out_lane2[15:0],drpen_in_lane2,drprdy_out_lane2,drpwe_in_lane2,drpaddr_in_lane3[8:0],drpdi_in_lane3[15:0],drpdo_out_lane3[15:0],drpen_in_lane3,drprdy_out_lane3,drpwe_in_lane3,gt0_qplllock_in,gt0_qpllrefclklost_in,gt0_qpllreset_out,gt1_qplllock_in,gt1_qpllrefclklost_in,gt1_qpllreset_out,gt_qpllclk_quad2_in,gt_qpllrefclk_quad2_in,gt_qpllclk_quad3_in,gt_qpllrefclk_quad3_in,tx_out_clk,pll_not_locked" */;
  output [63:0]m_axi_rx_tdata;
  output m_axi_rx_tvalid;
  output [7:0]m_axi_rx_tkeep;
  output m_axi_rx_tlast;
  output [63:0]m_axi_ufc_rx_tdata;
  output [7:0]m_axi_ufc_rx_tkeep;
  output m_axi_ufc_rx_tvalid;
  output m_axi_ufc_rx_tlast;
  input [0:3]rxp;
  input [0:3]rxn;
  input gt_refclk1;
  output frame_err;
  output rx_hard_err;
  output soft_err;
  output [0:3]rx_lane_up;
  output rx_channel_up;
  input user_clk;
  input sync_clk;
  input rx_system_reset;
  input power_down;
  input [2:0]loopback;
  input gt_reset;
  output tx_lock;
  output sys_reset_out;
  input init_clk_in;
  output rx_resetdone_out;
  output link_reset_out;
  input drpclk_in;
  input [8:0]drpaddr_in;
  input [15:0]drpdi_in;
  output [15:0]drpdo_out;
  input drpen_in;
  output drprdy_out;
  input drpwe_in;
  input [8:0]drpaddr_in_lane1;
  input [15:0]drpdi_in_lane1;
  output [15:0]drpdo_out_lane1;
  input drpen_in_lane1;
  output drprdy_out_lane1;
  input drpwe_in_lane1;
  input [8:0]drpaddr_in_lane2;
  input [15:0]drpdi_in_lane2;
  output [15:0]drpdo_out_lane2;
  input drpen_in_lane2;
  output drprdy_out_lane2;
  input drpwe_in_lane2;
  input [8:0]drpaddr_in_lane3;
  input [15:0]drpdi_in_lane3;
  output [15:0]drpdo_out_lane3;
  input drpen_in_lane3;
  output drprdy_out_lane3;
  input drpwe_in_lane3;
  input gt0_qplllock_in;
  input gt0_qpllrefclklost_in;
  output gt0_qpllreset_out;
  input gt1_qplllock_in;
  input gt1_qpllrefclklost_in;
  output gt1_qpllreset_out;
  input gt_qpllclk_quad2_in;
  input gt_qpllrefclk_quad2_in;
  input gt_qpllclk_quad3_in;
  input gt_qpllrefclk_quad3_in;
  output tx_out_clk;
  input pll_not_locked;
endmodule
