xilinx.com customized_ip bulk_data_fifo 1.0 S_AXIS S_AXIS TDATA s_axis_tdata TDEST s_axis_tdest TID s_axis_tid TKEEP s_axis_tkeep TLAST s_axis_tlast TREADY s_axis_tready TSTRB s_axis_tstrb TUSER s_axis_tuser TVALID s_axis_tvalid TDATA_NUM_BYTES 8 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 2 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl M_AXIS M_AXIS TDATA m_axis_tdata TDEST m_axis_tdest TID m_axis_tid TKEEP m_axis_tkeep TLAST m_axis_tlast TREADY m_axis_tready TSTRB m_axis_tstrb TUSER m_axis_tuser TVALID m_axis_tvalid TDATA_NUM_BYTES 8 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 2 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl S_RSTIF S_RSTIF RST s_axis_aresetn POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl S_CLKIF S_CLKIF CLK s_axis_aclk ASSOCIATED_BUSIF S_AXIS FREQ_HZ s_axis_aclk frequency s_axis_aclk frequency 100000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl M_CLKIF M_CLKIF CLK m_axis_aclk ASSOCIATED_BUSIF M_AXIS FREQ_HZ m_axis_aclk frequency m_axis_aclk frequency 100000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false S_CLKENIF S_CLKENIF CE s_axis_aclken POLARITY ACTIVE_LOW none false M_CLKENIF M_CLKENIF CE m_axis_aclken POLARITY ACTIVE_LOW none false xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog axis_data_fifo_v2_0_2_top xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset xilinx_verilogsynthesis_view_fileset GENtimestamp Mon May 04 20:59:18 UTC 2020 outputProductCRC 9:96f690ed xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints xilinx_synthesisconstraints_view_fileset GENtimestamp Mon May 04 20:59:18 UTC 2020 outputProductCRC 9:96f690ed xilinx_verilogsynthesiswrapper Verilog Synthesis Wrapper verilogSource:vivado.xilinx.com:synthesis.wrapper verilog bulk_data_fifo xilinx_verilogsynthesiswrapper_view_fileset GENtimestamp Mon May 04 20:59:18 UTC 2020 outputProductCRC 9:96f690ed xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Mon May 04 21:18:08 UTC 2020 outputProductCRC 9:96f690ed s_axis_aresetn in wire xilinx_verilogsynthesis 0x0 s_axis_aclk in wire xilinx_verilogsynthesis 0x0 s_axis_aclken in wire xilinx_verilogsynthesis 0x1 false s_axis_tvalid in wire xilinx_verilogsynthesis 0x0 s_axis_tready out wire xilinx_verilogsynthesis true s_axis_tdata in 63 0 wire xilinx_verilogsynthesis 0x0000000000000000 true s_axis_tstrb in 7 0 wire xilinx_verilogsynthesis 0xFF false s_axis_tkeep in 7 0 wire xilinx_verilogsynthesis 0xFF false s_axis_tlast in wire xilinx_verilogsynthesis 0x1 true s_axis_tid in 0 0 wire xilinx_verilogsynthesis 0x0 false s_axis_tdest in 0 0 wire xilinx_verilogsynthesis 0x0 false s_axis_tuser in 1 0 wire xilinx_verilogsynthesis 0x0 true m_axis_aclk in wire xilinx_verilogsynthesis 0x0 false m_axis_aclken in wire xilinx_verilogsynthesis 0x1 false m_axis_tvalid out wire xilinx_verilogsynthesis m_axis_tready in wire xilinx_verilogsynthesis 0x1 true m_axis_tdata out 63 0 wire xilinx_verilogsynthesis true m_axis_tstrb out 7 0 wire xilinx_verilogsynthesis false m_axis_tkeep out 7 0 wire xilinx_verilogsynthesis false m_axis_tlast out wire xilinx_verilogsynthesis true m_axis_tid out 0 0 wire xilinx_verilogsynthesis false m_axis_tdest out 0 0 wire xilinx_verilogsynthesis false m_axis_tuser out 1 0 wire xilinx_verilogsynthesis true axis_wr_data_count out 31 0 wire xilinx_verilogsynthesis true axis_rd_data_count out 31 0 wire xilinx_verilogsynthesis true almost_empty out wire xilinx_verilogsynthesis false prog_empty out wire xilinx_verilogsynthesis false almost_full out wire xilinx_verilogsynthesis false prog_full out wire xilinx_verilogsynthesis false sbiterr out wire xilinx_verilogsynthesis false dbiterr out wire xilinx_verilogsynthesis false injectsbiterr in wire xilinx_verilogsynthesis 0x0 false injectdbiterr in wire xilinx_verilogsynthesis 0x0 false C_FAMILY virtex7 C_AXIS_TDATA_WIDTH 64 C_AXIS_TID_WIDTH 1 C_AXIS_TDEST_WIDTH 1 C_AXIS_TUSER_WIDTH 2 C_AXIS_SIGNAL_SET 0b00000000000000000000000010010011 C_FIFO_DEPTH 1024 C_FIFO_MODE 2 C_IS_ACLK_ASYNC 0 C_SYNCHRONIZER_STAGE 3 C_ACLKEN_CONV_MODE 0 C_ECC_MODE 0 C_FIFO_MEMORY_TYPE auto C_USE_ADV_FEATURES 826486851 C_PROG_EMPTY_THRESH 5 C_PROG_FULL_THRESH 11 choice_list_57592463 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 choice_pairs_0866c675 1 2 choice_pairs_0fb728ab auto block distributed choice_pairs_37189c7b 0 1 choice_pairs_7e3eb5e2 0 1 2 3 xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset hdl/axis_infrastructure_v1_1_0.vh verilogSource true axis_infrastructure_v1_1_0 hdl/axis_infrastructure_v1_1_vl_rfs.v verilogSource axis_infrastructure_v1_1_0 xilinx_verilogsynthesis_view_fileset hdl/axis_data_fifo_v2_0_vl_rfs.v verilogSource axis_data_fifo_v2_0_2 xilinx_synthesisconstraints_view_fileset bulk_data_fifo_ooc.xdc xdc USED_IN_implementation USED_IN_out_of_context USED_IN_synthesis xilinx_verilogsynthesiswrapper_view_fileset synth/bulk_data_fifo.v verilogSource xil_defaultlib xilinx_externalfiles_view_fileset bulk_data_fifo.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib bulk_data_fifo_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib bulk_data_fifo_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib bulk_data_fifo_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib bulk_data_fifo_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib The AXI4-Stream Data FIFO IP provides the infrastructure to insert buffering between a AXI4-Stream master and slave. TDATA_NUM_BYTES TDATA width (bytes) 8 true TID_WIDTH TID width (bits) 0 true TDEST_WIDTH TDEST width (bits) 0 true TUSER_WIDTH TUSER width (bits) 2 true FIFO_DEPTH FIFO depth 1024 true FIFO_MODE Enable packet mode 2 true IS_ACLK_ASYNC Independent clocks 0 true ACLKEN_CONV_MODE ACLKEN conversion mode 0 true HAS_TREADY Enable TREADY 1 false HAS_TSTRB Enable TSTRB 0 true HAS_TKEEP Enable TKEEP 0 true HAS_TLAST Enable TLAST 1 false SYNCHRONIZATION_STAGES CDC sync stages 3 false HAS_WR_DATA_COUNT Enable write data count 1 true HAS_RD_DATA_COUNT Enable read data count 1 true HAS_AEMPTY Enable almost empty 0 false HAS_PROG_EMPTY Enable programmable empty 0 true PROG_EMPTY_THRESH Progammable empty threshold 5 false HAS_AFULL Enable almost full 0 false HAS_PROG_FULL Enable programmable full 0 true PROG_FULL_THRESH Progammable full threshold 11 false ENABLE_ECC Enable ECC 0 false HAS_ECC_ERR_INJECT Include ECC error injection 0 false FIFO_MEMORY_TYPE Memory type auto true Component_Name bulk_data_fifo AXI4-Stream Data FIFO XPM_FIFO XPM_CDC 2 2019.2