xilinx.com customized_ip dwidth_convert 1.0 S_AXIS S_AXIS TVALID s_axis_tvalid TREADY s_axis_tready TDATA s_axis_tdata TSTRB s_axis_tstrb TKEEP s_axis_tkeep TLAST s_axis_tlast TID s_axis_tid TDEST s_axis_tdest TUSER s_axis_tuser TDATA_NUM_BYTES 4 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl M_AXIS M_AXIS TVALID m_axis_tvalid TREADY m_axis_tready TDATA m_axis_tdata TSTRB m_axis_tstrb TKEEP m_axis_tkeep TLAST m_axis_tlast TID m_axis_tid TDEST m_axis_tdest TUSER m_axis_tuser TDATA_NUM_BYTES 8 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 1 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl RSTIF RSTIF RST aresetn POLARITY ACTIVE_LOW none INSERT_VIP 0 simulation.rtl CLKIF CLKIF CLK aclk FREQ_HZ aclk frequency aclk frequency 10000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl CLKENIF CLKENIF CE aclken POLARITY ACTIVE_LOW none false xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog axis_dwidth_converter_v1_1_19_axis_dwidth_converter xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset xilinx_verilogsynthesis_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset xilinx_verilogsynthesis_view_fileset GENtimestamp Mon May 04 20:59:07 UTC 2020 outputProductCRC 9:e3847266 xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints xilinx_synthesisconstraints_view_fileset GENtimestamp Mon May 04 20:59:07 UTC 2020 outputProductCRC 9:e3847266 xilinx_verilogsynthesiswrapper Verilog Synthesis Wrapper verilogSource:vivado.xilinx.com:synthesis.wrapper verilog dwidth_convert xilinx_verilogsynthesiswrapper_view_fileset GENtimestamp Mon May 04 20:59:07 UTC 2020 outputProductCRC 9:e3847266 xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Mon May 04 21:30:25 UTC 2020 outputProductCRC 9:e3847266 aclk in wire xilinx_verilogsynthesis aresetn in wire xilinx_verilogsynthesis aclken in wire xilinx_verilogsynthesis 0x1 false s_axis_tvalid in wire xilinx_verilogsynthesis 0x0 s_axis_tready out wire xilinx_verilogsynthesis true s_axis_tdata in 31 0 wire xilinx_verilogsynthesis 0x00000000 s_axis_tstrb in 3 0 wire xilinx_verilogsynthesis 0xF false s_axis_tkeep in 3 0 wire xilinx_verilogsynthesis 0xF false s_axis_tlast in wire xilinx_verilogsynthesis 0x1 true s_axis_tid in 0 0 wire xilinx_verilogsynthesis 0x0 false s_axis_tdest in 0 0 wire xilinx_verilogsynthesis 0x0 false s_axis_tuser in 0 0 wire xilinx_verilogsynthesis 0x0 false m_axis_tvalid out wire xilinx_verilogsynthesis m_axis_tready in wire xilinx_verilogsynthesis 0x1 true m_axis_tdata out 63 0 wire xilinx_verilogsynthesis m_axis_tstrb out 7 0 wire xilinx_verilogsynthesis false m_axis_tkeep out 7 0 wire xilinx_verilogsynthesis true m_axis_tlast out wire xilinx_verilogsynthesis true m_axis_tid out 0 0 wire xilinx_verilogsynthesis false m_axis_tdest out 0 0 wire xilinx_verilogsynthesis false m_axis_tuser out 0 0 wire xilinx_verilogsynthesis false C_FAMILY virtex7 C_S_AXIS_TDATA_WIDTH 32 C_M_AXIS_TDATA_WIDTH 64 C_AXIS_TID_WIDTH 1 C_AXIS_TDEST_WIDTH 1 C_S_AXIS_TUSER_WIDTH 1 C_M_AXIS_TUSER_WIDTH 1 C_AXIS_SIGNAL_SET 0b00000000000000000000000000010011 choice_pairs_37189c7b 0 1 xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset hdl/axis_infrastructure_v1_1_0.vh verilogSource true axis_infrastructure_v1_1_0 hdl/axis_infrastructure_v1_1_vl_rfs.v verilogSource axis_infrastructure_v1_1_0 xilinx_verilogsynthesis_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset hdl/axis_register_slice_v1_1_vl_rfs.v verilogSource axis_register_slice_v1_1_20 xilinx_verilogsynthesis_view_fileset hdl/axis_dwidth_converter_v1_1_vl_rfs.v verilogSource axis_dwidth_converter_v1_1_19 xilinx_synthesisconstraints_view_fileset dwidth_convert_ooc.xdc xdc USED_IN_implementation USED_IN_out_of_context USED_IN_synthesis xilinx_verilogsynthesiswrapper_view_fileset synth/dwidth_convert.v verilogSource xil_defaultlib xilinx_externalfiles_view_fileset dwidth_convert.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib dwidth_convert_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib dwidth_convert_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib dwidth_convert_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib dwidth_convert_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib The AXI4-Stream Data Widith Converter IP provides the infrastructure to change the data path width between a AXI4-Stream master and slave. S_TDATA_NUM_BYTES Slave Interface TDATA Width (bytes) 4 true M_TDATA_NUM_BYTES Master Interface TDATA Width (bytes) 8 true TID_WIDTH TID Width (bits) 0 true TDEST_WIDTH TDEST Width (bits) 0 true TUSER_BITS_PER_BYTE TUSER bits per byte 0 true HAS_TREADY Enable TREADY 1 true HAS_TLAST Enable TLAST 1 true HAS_TSTRB Enable TSTRB 0 true HAS_TKEEP Enable TKEEP 0 true HAS_ACLKEN Enable ACLKEN 0 true HAS_MI_TKEEP Enable MI TKEEP 1 true Component_Name dwidth_convert AXI4-Stream Data Width Converter XPM_CDC XPM_FIFO 19 2019.2