xilinx.com customized_ip ethernet_mac_rgmii 1.0 gmii gmii GMII COL gmii_col CRS gmii_crs GTX_CLK gmii_tx_clk RX_CLK gmii_rx_clk RX_DV gmii_rx_dv RX_ER gmii_rx_er RXD gmii_rxd TX_CLK mii_tx_clk TX_EN gmii_tx_en TX_ER gmii_tx_er TXD gmii_txd BOARD.ASSOCIATED_PARAM ETHERNET_BOARD_INTERFACE required false mii mii MII COL mii_col CRS mii_crs RX_CLK mii_rx_clk RX_DV mii_rx_dv RX_ER mii_rx_er RXD mii_rxd TX_CLK mii_tx_clk TX_EN mii_tx_en TX_ER mii_tx_er TXD mii_txd BOARD.ASSOCIATED_PARAM ETHERNET_BOARD_INTERFACE required false rgmii rgmii RGMII RD rgmii_rxd RX_CTL rgmii_rx_ctl RXC rgmii_rxc TD rgmii_txd TX_CTL rgmii_tx_ctl TXC rgmii_txc BOARD.ASSOCIATED_PARAM ETHERNET_BOARD_INTERFACE required true rgmii_status rgmii_status RGMII Status duplex_status inband_duplex_status link_speed inband_clock_speed link_status inband_link_status true mdio_internal mdio_internal MDIO MDC mdc MDIO_I mdio_i MDIO_O mdio_o MDIO_T mdio_t BOARD.ASSOCIATED_PARAM MDIO_BOARD_INTERFACE required CAN_DEBUG false none false mdio_external mdio_external MDIO IO mdio MDC mdc BOARD.ASSOCIATED_PARAM MDIO_BOARD_INTERFACE required CAN_DEBUG false none true s_axis_tx s_axis_tx TX data input TDATA tx_axis_mac_tdata TLAST tx_axis_mac_tlast TREADY tx_axis_mac_tready TUSER tx_axis_mac_tuser TVALID tx_axis_mac_tvalid TDATA_NUM_BYTES 1 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 1 none HAS_TREADY 1 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl m_axis_rx m_axis_rx RX data output TDATA rx_axis_mac_tdata TLAST rx_axis_mac_tlast TUSER rx_axis_mac_tuser TVALID rx_axis_mac_tvalid TDATA_NUM_BYTES 1 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 1 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 1 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl m_axis_rx_ts m_axis_rx_ts Rx Timestamp data output TDATA rx_ts_axis_tdata TVALID rx_ts_axis_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_tx_ts m_axis_tx_ts Tx Timestamp data output TDATA tx_ts_axis_tdata TVALID tx_ts_axis_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_av s_axis_tx_av AVB AV data input TDATA tx_axis_av_tdata TLAST tx_axis_av_tlast TREADY tx_axis_av_tready TUSER tx_axis_av_tuser TVALID tx_axis_av_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_av m_axis_rx_av AVB AV data output TDATA rx_axis_av_tdata TLAST rx_axis_av_tlast TUSER rx_axis_av_tuser TVALID rx_axis_av_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false tx_mac_aclk tx_mac_aclk CLK tx_mac_aclk ASSOCIATED_BUSIF s_axis_tx:m_axis_tx_ts:s_axis_tx_av:s_axis_pause:s_axis_tx_pfc0:s_axis_tx_pfc1:s_axis_tx_pfc2:s_axis_tx_pfc3:s_axis_tx_pfc4:s_axis_tx_pfc5:s_axis_tx_pfc6:s_axis_tx_pfc7 ASSOCIATED_ASYNC_RESET tx_axi_rstn:tx_reset FREQ_HZ 125000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl rx_mac_aclk rx_mac_aclk CLK rx_mac_aclk ASSOCIATED_BUSIF m_axis_rx:m_axis_rx_ts:m_axis_rx_av:m_axis_rx_pfc0:m_axis_rx_pfc1:m_axis_rx_pfc2:m_axis_rx_pfc3:m_axis_rx_pfc4:m_axis_rx_pfc5:m_axis_rx_pfc6:m_axis_rx_pfc7 ASSOCIATED_ASYNC_RESET rx_axi_rstn:rx_reset FREQ_HZ 125000000 PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl tx_reset tx_reset reset synchronous to the tx axi clock domain RST tx_reset POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl rx_reset rx_reset reset synchronous to the rx axi clock domain RST rx_reset POLARITY ACTIVE_HIGH INSERT_VIP 0 simulation.rtl gtx_clk gtx_clk Main 125MHz clock input CLK gtx_clk FREQ_HZ 125000000 PHASE 0 CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true rx_usr_clk2 rx_usr_clk2 RX User Clock2 clock input from PHY CLK rx_usr_clk2 FREQ_HZ 125000000 PHASE 0 CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false gtx_clk_out gtx_clk_out Shared 125MHz clock output CLK gtx_clk_out FREQ_HZ 125000000 PHASE 0 CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false gtx_clk90 gtx_clk90 Shared 125MHz 90 degree shifted input Clock required for RGMII transmit offset CLK gtx_clk90 FREQ_HZ 125000000 PHASE 90 CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false gtx_clk90_out gtx_clk90_out Shared 125MHz 90 degree shifted output Clock required for RGMII transmit offset CLK gtx_clk90_out FREQ_HZ 125000000 PHASE 90 CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false ref_clk ref_clk Clock required for IODelay Ctrl CLK refclk FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_BUSIF none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl false glbl_rstn glbl_rstn Asynchronous reset RST glbl_rstn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl rx_axi_rstn rx_axi_rstn reset synchronous to the rx axi clock domain RST rx_axi_rstn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl tx_axi_rstn tx_axi_rstn Reset synchronous to the tx axi clock domain RST tx_axi_rstn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl clk_enable clk_enable CE clk_enable POLARITY ACTIVE_LOW none false clk_enable_rx clk_enable_rx CE clk_enable_rx POLARITY ACTIVE_LOW none false rx_enable rx_enable CE rx_enable POLARITY ACTIVE_LOW none false m_axis_rx_pfc0 m_axis_rx_pfc0 RX Priority 0 Pause interface TREADY rx_pfc_p0_tready TVALID rx_pfc_p0_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_pfc1 m_axis_rx_pfc1 RX Priority 1 Pause interface TREADY rx_pfc_p1_tready TVALID rx_pfc_p1_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_pfc2 m_axis_rx_pfc2 RX Priority 2 Pause interface TREADY rx_pfc_p2_tready TVALID rx_pfc_p2_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_pfc3 m_axis_rx_pfc3 RX Priority 3 Pause interface TREADY rx_pfc_p3_tready TVALID rx_pfc_p3_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_pfc4 m_axis_rx_pfc4 RX Priority 4 Pause interface TREADY rx_pfc_p4_tready TVALID rx_pfc_p4_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_pfc5 m_axis_rx_pfc5 RX Priority 5 Pause interface TREADY rx_pfc_p5_tready TVALID rx_pfc_p5_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_pfc6 m_axis_rx_pfc6 RX Priority 6 Pause interface TREADY rx_pfc_p6_tready TVALID rx_pfc_p6_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false m_axis_rx_pfc7 m_axis_rx_pfc7 RX Priority 7 Pause interface TREADY rx_pfc_p7_tready TVALID rx_pfc_p7_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc0 s_axis_tx_pfc0 TX Priority 0 Pause interface TVALID tx_pfc_p0_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc1 s_axis_tx_pfc1 TX Priority 1 Pause interface TVALID tx_pfc_p1_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc2 s_axis_tx_pfc2 TX Priority 2 Pause interface TVALID tx_pfc_p2_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc3 s_axis_tx_pfc3 TX Priority 3 Pause interface TVALID tx_pfc_p3_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc4 s_axis_tx_pfc4 TX Priority 4 Pause interface TVALID tx_pfc_p4_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc5 s_axis_tx_pfc5 TX Priority 5 Pause interface TVALID tx_pfc_p5_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc6 s_axis_tx_pfc6 TX Priority 6 Pause interface TVALID tx_pfc_p6_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_tx_pfc7 s_axis_tx_pfc7 TX Priority 7 Pause interface TVALID tx_pfc_p7_tvalid TDATA_NUM_BYTES 0 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl false s_axis_pause s_axis_pause TX Legacy Pause interface TDATA pause_val TVALID pause_req TDATA_NUM_BYTES 2 none TDEST_WIDTH 0 none TID_WIDTH 0 none TUSER_WIDTH 0 none HAS_TREADY 0 none HAS_TSTRB 0 none HAS_TKEEP 0 none HAS_TLAST 0 none FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none LAYERED_METADATA undef none INSERT_VIP 0 simulation.rtl s_axi s_axi ARADDR s_axi_araddr ARREADY s_axi_arready ARVALID s_axi_arvalid AWADDR s_axi_awaddr AWREADY s_axi_awready AWVALID s_axi_awvalid BREADY s_axi_bready BRESP s_axi_bresp BVALID s_axi_bvalid RDATA s_axi_rdata RREADY s_axi_rready RRESP s_axi_rresp RVALID s_axi_rvalid WDATA s_axi_wdata WREADY s_axi_wready WVALID s_axi_wvalid DATA_WIDTH 32 none PROTOCOL AXI4LITE none FREQ_HZ 100000000 none ID_WIDTH 0 none ADDR_WIDTH 12 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 1 none HAS_RRESP 1 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl true s_axi_aclk s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none ASSOCIATED_RESET none INSERT_VIP 0 simulation.rtl true s_axi_resetn s_axi_resetn RST s_axi_resetn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl true mac_irq INTERRUPT mac_irq SENSITIVITY EDGE_RISING PortWidth 1 none true interrupt_ptp_timer INTERRUPT interrupt_ptp_timer SENSITIVITY EDGE_RISING PortWidth 1 none false interrupt_ptp_rx INTERRUPT interrupt_ptp_rx SENSITIVITY EDGE_RISING PortWidth 1 none false interrupt_ptp_tx INTERRUPT interrupt_ptp_tx SENSITIVITY EDGE_RISING PortWidth 1 none false tx_statistics tx_statistics Tx Statistics statistics_data tx_statistics_vector statistics_valid tx_statistics_valid rx_statistics rx_statistics Rx Statistics statistics_data rx_statistics_vector statistics_valid rx_statistics_valid ptp_timers ptp_timers PTP Timer Outputs clk8k clk8k ns_field rtc_nanosec_field ns_field_1722 rtc_nanosec_field_1722 s_field rtc_sec_field false xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis ethernet_mac_rgmii_block xilinx_anylanguagesynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset GENtimestamp Mon May 04 20:57:21 UTC 2020 outputProductCRC 9:da97cf1b outputProductLicenses tri_mode_eth_mac@2015.04(BOUGHT);eth_avb_endpoint@2015.04(DESIGN_LINKING) xilinx_synthesisconstraints Synthesis Constraints :vivado.xilinx.com:synthesis.constraints outputProductCRC 9:da97cf1b outputProductLicenses tri_mode_eth_mac@2015.04(BOUGHT);eth_avb_endpoint@2015.04(DESIGN_LINKING) xilinx_vhdlsynthesiswrapper VHDL Synthesis Wrapper vhdlSource:vivado.xilinx.com:synthesis.wrapper vhdl ethernet_mac_rgmii xilinx_vhdlsynthesiswrapper_view_fileset GENtimestamp Mon May 04 20:57:21 UTC 2020 outputProductCRC 9:da97cf1b outputProductLicenses tri_mode_eth_mac@2015.04(BOUGHT);eth_avb_endpoint@2015.04(DESIGN_LINKING) xilinx_implementation Implementation :vivado.xilinx.com:implementation xilinx_implementation_view_fileset GENtimestamp Mon May 04 20:57:21 UTC 2020 outputProductCRC 9:da97cf1b outputProductLicenses tri_mode_eth_mac@2015.04(BOUGHT);eth_avb_endpoint@2015.04(DESIGN_LINKING) xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Mon May 04 21:30:35 UTC 2020 outputProductCRC 9:da97cf1b outputProductLicenses tri_mode_eth_mac@2015.04(BOUGHT);eth_avb_endpoint@2015.04(DESIGN_LINKING) s_axi_aclk in std_logic xilinx_anylanguagesynthesis 0 true s_axi_resetn in std_logic xilinx_anylanguagesynthesis 0 true gtx_clk in std_logic xilinx_anylanguagesynthesis true rx_usr_clk2 in std_logic xilinx_anylanguagesynthesis 0 false gtx_clk90 in std_logic xilinx_anylanguagesynthesis 0 false gtx_clk_out out std_logic xilinx_anylanguagesynthesis false gtx_clk90_out out std_logic xilinx_anylanguagesynthesis 0 false glbl_rstn in std_logic xilinx_anylanguagesynthesis rx_axi_rstn in std_logic xilinx_anylanguagesynthesis tx_axi_rstn in std_logic xilinx_anylanguagesynthesis rx_statistics_vector out 27 0 std_logic_vector xilinx_anylanguagesynthesis rx_statistics_valid out std_logic xilinx_anylanguagesynthesis rx_mac_aclk out std_logic xilinx_anylanguagesynthesis rx_reset out std_logic xilinx_anylanguagesynthesis rx_enable out std_logic xilinx_anylanguagesynthesis false rx_axis_filter_tuser out 0 0 std_logic_vector xilinx_anylanguagesynthesis false rx_axis_mac_tdata out 7 0 std_logic_vector xilinx_anylanguagesynthesis rx_axis_mac_tvalid out std_logic xilinx_anylanguagesynthesis rx_axis_mac_tlast out std_logic xilinx_anylanguagesynthesis rx_axis_mac_tuser out std_logic xilinx_anylanguagesynthesis tx_ifg_delay in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 tx_statistics_vector out 31 0 std_logic_vector xilinx_anylanguagesynthesis tx_statistics_valid out std_logic xilinx_anylanguagesynthesis tx_mac_aclk out std_logic xilinx_anylanguagesynthesis tx_reset out std_logic xilinx_anylanguagesynthesis tx_enable out std_logic xilinx_anylanguagesynthesis false tx_axis_mac_tdata in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 tx_axis_mac_tvalid in std_logic xilinx_anylanguagesynthesis 0 tx_axis_mac_tlast in std_logic xilinx_anylanguagesynthesis 0 tx_axis_mac_tuser in 0 0 std_logic_vector xilinx_anylanguagesynthesis 0 tx_axis_mac_tready out std_logic xilinx_anylanguagesynthesis tx_collision out std_logic xilinx_anylanguagesynthesis false tx_retransmit out std_logic xilinx_anylanguagesynthesis false tx_axis_av_tdata in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 false tx_axis_av_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_axis_av_tlast in std_logic xilinx_anylanguagesynthesis 0 false tx_axis_av_tuser in std_logic xilinx_anylanguagesynthesis 0 false tx_axis_av_tready out std_logic xilinx_anylanguagesynthesis false rx_axis_av_tdata out 7 0 std_logic_vector xilinx_anylanguagesynthesis false rx_axis_av_tvalid out std_logic xilinx_anylanguagesynthesis false rx_axis_av_tlast out std_logic xilinx_anylanguagesynthesis false rx_axis_av_tuser out std_logic xilinx_anylanguagesynthesis false rtc_nanosec_field out 31 0 std_logic_vector xilinx_anylanguagesynthesis false rtc_sec_field out 47 0 std_logic_vector xilinx_anylanguagesynthesis false rtc_nanosec_field_1722 out 31 0 std_logic_vector xilinx_anylanguagesynthesis false clk8k out std_logic xilinx_anylanguagesynthesis false interrupt_ptp_timer out std_logic xilinx_anylanguagesynthesis false interrupt_ptp_rx out std_logic xilinx_anylanguagesynthesis false interrupt_ptp_tx out std_logic xilinx_anylanguagesynthesis false systemtimer_s_field in 47 0 std_logic_vector xilinx_anylanguagesynthesis 0 false systemtimer_ns_field in 31 0 std_logic_vector xilinx_anylanguagesynthesis 0 false correction_timer in 63 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxphy_s_field in 47 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxphy_ns_field in 31 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rxphy_correction_timer in 63 0 std_logic_vector xilinx_anylanguagesynthesis 0 false rx_ts_axis_tdata out 127 0 std_logic_vector xilinx_anylanguagesynthesis false rx_ts_axis_tvalid out std_logic xilinx_anylanguagesynthesis false tx_ts_axis_tdata out 127 0 std_logic_vector xilinx_anylanguagesynthesis false tx_ts_axis_tvalid out std_logic xilinx_anylanguagesynthesis false pause_req in std_logic xilinx_anylanguagesynthesis 0 pause_val in 15 0 std_logic_vector xilinx_anylanguagesynthesis 0 refclk in std_logic xilinx_anylanguagesynthesis 0 false clk_enable in std_logic xilinx_anylanguagesynthesis 1 false clk_enable_rx in std_logic xilinx_anylanguagesynthesis 1 false speedis100 out std_logic xilinx_anylanguagesynthesis speedis10100 out std_logic xilinx_anylanguagesynthesis gmii_txd out 7 0 std_logic_vector xilinx_anylanguagesynthesis false gmii_tx_en out std_logic xilinx_anylanguagesynthesis false gmii_tx_er out std_logic xilinx_anylanguagesynthesis false gmii_tx_clk out std_logic xilinx_anylanguagesynthesis false gmii_rxd in 7 0 std_logic_vector xilinx_anylanguagesynthesis 0 false gmii_rx_dv in std_logic xilinx_anylanguagesynthesis 0 false gmii_rx_er in std_logic xilinx_anylanguagesynthesis 0 false gmii_rx_clk in std_logic xilinx_anylanguagesynthesis 0 false gmii_col in std_logic xilinx_anylanguagesynthesis 0 false gmii_crs in std_logic xilinx_anylanguagesynthesis 0 false mii_tx_clk in std_logic xilinx_anylanguagesynthesis 0 false mii_txd out 3 0 std_logic_vector xilinx_anylanguagesynthesis false mii_tx_en out std_logic xilinx_anylanguagesynthesis false mii_tx_er out std_logic xilinx_anylanguagesynthesis false mii_rxd in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 false mii_rx_dv in std_logic xilinx_anylanguagesynthesis 0 false mii_rx_er in std_logic xilinx_anylanguagesynthesis 0 false mii_rx_clk in std_logic xilinx_anylanguagesynthesis 0 false mii_col in std_logic xilinx_anylanguagesynthesis 0 false mii_crs in std_logic xilinx_anylanguagesynthesis 0 false rgmii_txd out 3 0 std_logic_vector xilinx_anylanguagesynthesis true rgmii_tx_ctl out std_logic xilinx_anylanguagesynthesis true rgmii_txc out std_logic xilinx_anylanguagesynthesis true rgmii_rxd in 3 0 std_logic_vector xilinx_anylanguagesynthesis 0 true rgmii_rx_ctl in std_logic xilinx_anylanguagesynthesis 0 true rgmii_rxc in std_logic xilinx_anylanguagesynthesis 0 true inband_link_status out std_logic xilinx_anylanguagesynthesis true inband_clock_speed out 1 0 std_logic_vector xilinx_anylanguagesynthesis true inband_duplex_status out std_logic xilinx_anylanguagesynthesis true mdio_i in std_logic xilinx_anylanguagesynthesis 0 false mdio_t out std_logic xilinx_anylanguagesynthesis false mdio_o out std_logic xilinx_anylanguagesynthesis false mdio inout std_logic xilinx_anylanguagesynthesis true mdc out std_logic xilinx_anylanguagesynthesis true s_axi_awaddr in 11 0 std_logic_vector xilinx_anylanguagesynthesis 0 true s_axi_awvalid in std_logic xilinx_anylanguagesynthesis 0 true s_axi_awready out std_logic xilinx_anylanguagesynthesis true s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis 0 true s_axi_wvalid in std_logic xilinx_anylanguagesynthesis 0 true s_axi_wready out std_logic xilinx_anylanguagesynthesis true s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis true s_axi_bvalid out std_logic xilinx_anylanguagesynthesis true s_axi_bready in std_logic xilinx_anylanguagesynthesis 0 true s_axi_araddr in 11 0 std_logic_vector xilinx_anylanguagesynthesis 0 true s_axi_arvalid in std_logic xilinx_anylanguagesynthesis 0 true s_axi_arready out std_logic xilinx_anylanguagesynthesis true s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis true s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis true s_axi_rvalid out std_logic xilinx_anylanguagesynthesis true s_axi_rready in std_logic xilinx_anylanguagesynthesis 0 true mac_irq out std_logic xilinx_anylanguagesynthesis true rx_configuration_vector in 79 0 std_logic_vector xilinx_anylanguagesynthesis 0 false tx_configuration_vector in 79 0 std_logic_vector xilinx_anylanguagesynthesis 0 false tx_pfc_p0_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_pfc_p1_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_pfc_p2_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_pfc_p3_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_pfc_p4_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_pfc_p5_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_pfc_p6_tvalid in std_logic xilinx_anylanguagesynthesis 0 false tx_pfc_p7_tvalid in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p0_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p1_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p2_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p3_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p4_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p5_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p6_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p7_tvalid out std_logic xilinx_anylanguagesynthesis false rx_pfc_p0_tready in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p1_tready in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p2_tready in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p3_tready in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p4_tready in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p5_tready in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p6_tready in std_logic xilinx_anylanguagesynthesis 0 false rx_pfc_p7_tready in std_logic xilinx_anylanguagesynthesis 0 false c_component_name ethernet_mac_rgmii c_physical_interface RGMII c_half_duplex false c_has_host true c_has_mdio true c_mdio_external true c_axilite_freq 100.00 c_add_filter false c_at_entries 0 c_family virtex7 c_mac_speed SPEED_1000_MBPS c_int_clk_src User_Clk2 c_int_mode_type BASEX c_has_stats true c_num_stats 34 c_cntr_rst true c_stats_width 64 c_avb false c_1588 0 c_tx_inband_cf_enable false c_rx_inband_ts_enable false c_tx_tuser_width 1 c_rx_vec_width 79 c_tx_vec_width 79 c_addr_width 12 c_pfc false c_mii_io true c_data_rate 1_Gbps choice_list_43f0d29b 32bit 64bit choice_list_699650f8 BASEX SGMII choice_list_75cd4dfc Time_of_day Correction_Field_Format choice_list_aae36830 1_Gbps 2.5_Gbps choice_list_ac75ef1e Custom choice_list_b6ddaaa0 RGMII GMII MII Internal choice_list_db751818 user_clk2 rx_user_clk2 choice_list_f945896b Tri_speed 1000_Mbps choice_pairs_14544bc6 1 0 choice_pairs_912a7802 true false xilinx_anylanguagesynthesis_xilinx_com_ip_xbip_utils_3_0__ref_view_fileset hdl/xbip_utils_v3_0_vh_rfs.vhd vhdlSource xbip_utils_v3_0_10 xilinx_anylanguagesynthesis_xilinx_com_ip_xbip_pipe_3_0__ref_view_fileset hdl/xbip_pipe_v3_0_vh_rfs.vhd vhdlSource xbip_pipe_v3_0_6 xilinx_anylanguagesynthesis_xilinx_com_ip_xbip_bram18k_3_0__ref_view_fileset hdl/xbip_bram18k_v3_0_vh_rfs.vhd vhdlSource xbip_bram18k_v3_0_6 xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset hdl/mult_gen_v12_0_vh_rfs.vhd vhdlSource mult_gen_v12_0_16 xilinx_anylanguagesynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset hdl/axi_lite_ipif_v3_0_vh_rfs.vhd vhdlSource axi_lite_ipif_v3_0_4 xilinx_anylanguagesynthesis_view_fileset synth/ethernet_mac_rgmii.xdc xdc synth/ethernet_mac_rgmii_ooc.xdc xdc USED_IN_implementation USED_IN_out_of_context USED_IN_synthesis synth/ethernet_mac_rgmii_clocks.xdc xdc processing_order late hdl/tri_mode_ethernet_mac_v9_0_rfs.v verilogSource tri_mode_ethernet_mac_v9_0_15 hdl/avb/tx_ptp_pkt_buff_init.mem mem tri_mode_ethernet_mac_v9_0_15 hdl/tri_mode_ethernet_mac_v9_0_rfs.vhd vhdlSource tri_mode_ethernet_mac_v9_0_15 synth/common/ethernet_mac_rgmii_block_sync_block.vhd vhdlSource synth/ethernet_mac_rgmii_axi4_lite_ipif_wrapper.vhd vhdlSource header_files/ethernet_mac_rgmii_axi4_lite_registers.h cSource synth/physical/ethernet_mac_rgmii_rgmii_v2_0_if.vhd vhdlSource synth/statistics/ethernet_mac_rgmii_vector_decode.vhd vhdlSource synth/ethernet_mac_rgmii_block.vhd vhdlSource ethernet_mac_rgmii_block xilinx_vhdlsynthesiswrapper_view_fileset synth/ethernet_mac_rgmii.vhd vhdlSource xilinx_implementation_view_fileset synth/ethernet_mac_rgmii_board.xdc xdc USED_IN_board USED_IN_implementation USED_IN_synthesis xilinx_externalfiles_view_fileset ethernet_mac_rgmii.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib ethernet_mac_rgmii_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib ethernet_mac_rgmii_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib ethernet_mac_rgmii_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib ethernet_mac_rgmii_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib The TEMAC Block LogiCORE(TM) is designed to the IEEE 802.3-2008 standard specification and supports full/half duplex operation at 10/100/1000Mbps speeds and a full duplex only operation at 2.5Gbps. In addition, it provides support for VLAN and JUMBO frames, as well as network management options such as statistics gathering and flow control. The core can be configured and monitored through an AXI interface, providing users with the flexibility to select the processor best suited to their specific application. The standalone core provides either a Gigabit Media Independent Interface (GMII) or a Reduced Gigabit Media Independent Interface (RGMII), both of which can carry Ethernet traffic at all three speeds and are suitable for connection to all industry standard PHYs of all media types. In addition, the core seamlessly interfaces to the Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE which can provide a Serial-GMII (SGMII) or can alternatively extend the functionality of the core to provide a 1000BASE-X PCS/PMA (1Gb/s and 2.5Gb/s Optical PHY Standard) creating a complete Gig/2.5GigE MAC core solution. Component_Name ethernet_mac_rgmii USE_BOARD_FLOW Generate Board based IO Constraints false ETHERNET_BOARD_INTERFACE Custom MDIO_BOARD_INTERFACE Custom Data_Rate Data Rate 1_Gbps Physical_Interface PHY Interface RGMII MAC_Speed MAC Speed 1000_Mbps Int_Clk_Src internal mode clock source user_clk2 Int_Mode_Type internal mode type BASEX Half_Duplex Half Duplex false Management_Interface Management Type true Management_Frequency Frequency (MHz) 100.00 Enable_MDIO Management Data Input/Output Interface (MDIO) true Make_MDIO_External Add IO Buffers for MDIO Interface ports true Frame_Filter Frame Filter false Number_of_Table_Entries Number of Table Entries 0 false Statistics_Counters Statistics Counters true Statistics_Reset Statistics Reset true Statistics_Width Statistics_Width 64bit Enable_AVB Ethernet Audio/Video Bridging (AVB) false Enable_1588 IEEE1588 hardware timestamping false MII_IO IEEE1588 hardware timestamping true false Enable_1588_1step Enable 1-step false false Timer_Format Timer Format Time_of_day false TX_Inband_CF_Enable TX InBand Command Field Enable false false RX_Inband_TS_Enable RX InBand TimeStamp Enable false false SupportLevel Shared Logic 0 Enable_Priority_Flow_Control IEEE802.1Qbb Priority-based Flow Control false Tri Mode Ethernet MAC XPM_MEMORY 15 tri_mode_eth_mac@2015.04 eth_avb_endpoint@2015.04 2019.2