// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 // Date : Mon May 4 23:36:15 2020 // Host : hog-efex2.cern.ch running 64-bit CentOS Linux release 7.7.1908 (Core) // Command : write_verilog -force -mode funcsim // /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_sim_netlist.v // Design : fifo1KB_34bit // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7vx550tffg1927-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "fifo1KB_34bit,fifo_generator_v13_2_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_2_5,Vivado 2019.2" *) (* NotValidForBitStream *) module fifo1KB_34bit (rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count, prog_full); input rst; (* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input wr_clk; (* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input rd_clk; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [33:0]din; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [33:0]dout; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; output [4:0]wr_data_count; output prog_full; wire [33:0]din; wire [33:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire [4:0]wr_data_count; wire wr_en; wire NLW_U0_almost_empty_UNCONNECTED; wire NLW_U0_almost_full_UNCONNECTED; wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; wire NLW_U0_axi_ar_overflow_UNCONNECTED; wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; wire NLW_U0_axi_ar_prog_full_UNCONNECTED; wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; wire NLW_U0_axi_ar_underflow_UNCONNECTED; wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; wire NLW_U0_axi_aw_overflow_UNCONNECTED; wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; wire NLW_U0_axi_aw_prog_full_UNCONNECTED; wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; wire NLW_U0_axi_aw_underflow_UNCONNECTED; wire NLW_U0_axi_b_dbiterr_UNCONNECTED; wire NLW_U0_axi_b_overflow_UNCONNECTED; wire NLW_U0_axi_b_prog_empty_UNCONNECTED; wire NLW_U0_axi_b_prog_full_UNCONNECTED; wire NLW_U0_axi_b_sbiterr_UNCONNECTED; wire NLW_U0_axi_b_underflow_UNCONNECTED; wire NLW_U0_axi_r_dbiterr_UNCONNECTED; wire NLW_U0_axi_r_overflow_UNCONNECTED; wire NLW_U0_axi_r_prog_empty_UNCONNECTED; wire NLW_U0_axi_r_prog_full_UNCONNECTED; wire NLW_U0_axi_r_sbiterr_UNCONNECTED; wire NLW_U0_axi_r_underflow_UNCONNECTED; wire NLW_U0_axi_w_dbiterr_UNCONNECTED; wire NLW_U0_axi_w_overflow_UNCONNECTED; wire NLW_U0_axi_w_prog_empty_UNCONNECTED; wire NLW_U0_axi_w_prog_full_UNCONNECTED; wire NLW_U0_axi_w_sbiterr_UNCONNECTED; wire NLW_U0_axi_w_underflow_UNCONNECTED; wire NLW_U0_axis_dbiterr_UNCONNECTED; wire NLW_U0_axis_overflow_UNCONNECTED; wire NLW_U0_axis_prog_empty_UNCONNECTED; wire NLW_U0_axis_prog_full_UNCONNECTED; wire NLW_U0_axis_sbiterr_UNCONNECTED; wire NLW_U0_axis_underflow_UNCONNECTED; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_m_axi_arvalid_UNCONNECTED; wire NLW_U0_m_axi_awvalid_UNCONNECTED; wire NLW_U0_m_axi_bready_UNCONNECTED; wire NLW_U0_m_axi_rready_UNCONNECTED; wire NLW_U0_m_axi_wlast_UNCONNECTED; wire NLW_U0_m_axi_wvalid_UNCONNECTED; wire NLW_U0_m_axis_tlast_UNCONNECTED; wire NLW_U0_m_axis_tvalid_UNCONNECTED; wire NLW_U0_overflow_UNCONNECTED; wire NLW_U0_prog_empty_UNCONNECTED; wire NLW_U0_rd_rst_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_s_axis_tready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire NLW_U0_underflow_UNCONNECTED; wire NLW_U0_valid_UNCONNECTED; wire NLW_U0_wr_ack_UNCONNECTED; wire NLW_U0_wr_rst_busy_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_data_count_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; wire [4:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "5" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "34" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "34" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "27" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "26" *) (* C_PROG_FULL_TYPE = "1" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "5" *) (* C_RD_DEPTH = "32" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "5" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "5" *) (* C_WR_DEPTH = "32" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "5" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) fifo1KB_34bit_fifo_generator_v13_2_5 U0 (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), .almost_full(NLW_U0_almost_full_UNCONNECTED), .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), .axi_ar_injectdbiterr(1'b0), .axi_ar_injectsbiterr(1'b0), .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), .axi_aw_injectdbiterr(1'b0), .axi_aw_injectsbiterr(1'b0), .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), .axi_b_injectdbiterr(1'b0), .axi_b_injectsbiterr(1'b0), .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), .axi_r_injectdbiterr(1'b0), .axi_r_injectsbiterr(1'b0), .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), .axi_w_injectdbiterr(1'b0), .axi_w_injectsbiterr(1'b0), .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), .axis_injectdbiterr(1'b0), .axis_injectsbiterr(1'b0), .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), .data_count(NLW_U0_data_count_UNCONNECTED[4:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout(dout), .empty(empty), .full(full), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .int_clk(1'b0), .m_aclk(1'b0), .m_aclk_en(1'b0), .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), .m_axi_arready(1'b0), .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), .m_axi_awready(1'b0), .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), .m_axi_bid(1'b0), .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), .m_axi_bresp({1'b0,1'b0}), .m_axi_buser(1'b0), .m_axi_bvalid(1'b0), .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_rid(1'b0), .m_axi_rlast(1'b0), .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), .m_axi_rresp({1'b0,1'b0}), .m_axi_ruser(1'b0), .m_axi_rvalid(1'b0), .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), .m_axi_wready(1'b0), .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]), .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]), .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), .m_axis_tready(1'b0), .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]), .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(NLW_U0_overflow_UNCONNECTED), .prog_empty(NLW_U0_prog_empty_UNCONNECTED), .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full(prog_full), .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[4:0]), .rd_en(rd_en), .rd_rst(1'b0), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), .rst(rst), .s_aclk(1'b0), .s_aclk_en(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_arid(1'b0), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlock(1'b0), .s_axi_arprot({1'b0,1'b0,1'b0}), .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_aruser(1'b0), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awuser(1'b0), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wid(1'b0), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser(1'b0), .s_axi_wvalid(1'b0), .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axis_tdest(1'b0), .s_axis_tid(1'b0), .s_axis_tkeep(1'b0), .s_axis_tlast(1'b0), .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), .s_axis_tstrb(1'b0), .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), .s_axis_tvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .sleep(1'b0), .srst(1'b0), .underflow(NLW_U0_underflow_UNCONNECTED), .valid(NLW_U0_valid_UNCONNECTED), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst(1'b0), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "ASYNC_RST" *) module fifo1KB_34bit_xpm_cdc_async_rst (src_arst, dest_clk, dest_arst); input src_arst; input dest_clk; output dest_arst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff; wire dest_clk; wire src_arst; assign dest_arst = arststages_ff[1]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "ASYNC_RST" *) FDPE #( .INIT(1'b0)) \arststages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(1'b0), .PRE(src_arst), .Q(arststages_ff[0])); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "ASYNC_RST" *) FDPE #( .INIT(1'b0)) \arststages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(arststages_ff[0]), .PRE(src_arst), .Q(arststages_ff[1])); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "ASYNC_RST" *) module fifo1KB_34bit_xpm_cdc_async_rst__1 (src_arst, dest_clk, dest_arst); input src_arst; input dest_clk; output dest_arst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff; wire dest_clk; wire src_arst; assign dest_arst = arststages_ff[1]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "ASYNC_RST" *) FDPE #( .INIT(1'b0)) \arststages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(1'b0), .PRE(src_arst), .Q(arststages_ff[0])); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "ASYNC_RST" *) FDPE #( .INIT(1'b0)) \arststages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(arststages_ff[0]), .PRE(src_arst), .Q(arststages_ff[1])); endmodule (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "1" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "5" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "GRAY" *) module fifo1KB_34bit_xpm_cdc_gray (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [4:0]src_in_bin; input dest_clk; output [4:0]dest_out_bin; wire [4:0]async_path; wire [3:0]binval; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [4:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [4:0]\dest_graysync_ff[1] ; wire [4:0]dest_out_bin; wire [3:0]gray_enc; wire src_clk; wire [4:0]src_in_bin; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin_ff[0]_i_1 (.I0(\dest_graysync_ff[1] [0]), .I1(\dest_graysync_ff[1] [2]), .I2(\dest_graysync_ff[1] [4]), .I3(\dest_graysync_ff[1] [3]), .I4(\dest_graysync_ff[1] [1]), .O(binval[0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin_ff[1]_i_1 (.I0(\dest_graysync_ff[1] [1]), .I1(\dest_graysync_ff[1] [3]), .I2(\dest_graysync_ff[1] [4]), .I3(\dest_graysync_ff[1] [2]), .O(binval[1])); LUT3 #( .INIT(8'h96)) \dest_out_bin_ff[2]_i_1 (.I0(\dest_graysync_ff[1] [2]), .I1(\dest_graysync_ff[1] [4]), .I2(\dest_graysync_ff[1] [3]), .O(binval[2])); LUT2 #( .INIT(4'h6)) \dest_out_bin_ff[3]_i_1 (.I0(\dest_graysync_ff[1] [3]), .I1(\dest_graysync_ff[1] [4]), .O(binval[3])); FDRE \dest_out_bin_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(binval[0]), .Q(dest_out_bin[0]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(binval[1]), .Q(dest_out_bin[1]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(binval[2]), .Q(dest_out_bin[2]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[3] (.C(dest_clk), .CE(1'b1), .D(binval[3]), .Q(dest_out_bin[3]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(dest_out_bin[4]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(src_in_bin[4]), .Q(async_path[4]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "1" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "5" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "GRAY" *) module fifo1KB_34bit_xpm_cdc_gray__2 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [4:0]src_in_bin; input dest_clk; output [4:0]dest_out_bin; wire [4:0]async_path; wire [3:0]binval; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [4:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [4:0]\dest_graysync_ff[1] ; wire [4:0]dest_out_bin; wire [3:0]gray_enc; wire src_clk; wire [4:0]src_in_bin; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin_ff[0]_i_1 (.I0(\dest_graysync_ff[1] [0]), .I1(\dest_graysync_ff[1] [2]), .I2(\dest_graysync_ff[1] [4]), .I3(\dest_graysync_ff[1] [3]), .I4(\dest_graysync_ff[1] [1]), .O(binval[0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin_ff[1]_i_1 (.I0(\dest_graysync_ff[1] [1]), .I1(\dest_graysync_ff[1] [3]), .I2(\dest_graysync_ff[1] [4]), .I3(\dest_graysync_ff[1] [2]), .O(binval[1])); LUT3 #( .INIT(8'h96)) \dest_out_bin_ff[2]_i_1 (.I0(\dest_graysync_ff[1] [2]), .I1(\dest_graysync_ff[1] [4]), .I2(\dest_graysync_ff[1] [3]), .O(binval[2])); LUT2 #( .INIT(4'h6)) \dest_out_bin_ff[3]_i_1 (.I0(\dest_graysync_ff[1] [3]), .I1(\dest_graysync_ff[1] [4]), .O(binval[3])); FDRE \dest_out_bin_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(binval[0]), .Q(dest_out_bin[0]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(binval[1]), .Q(dest_out_bin[1]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(binval[2]), .Q(dest_out_bin[2]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[3] (.C(dest_clk), .CE(1'b1), .D(binval[3]), .Q(dest_out_bin[3]), .R(1'b0)); FDRE \dest_out_bin_ff_reg[4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(dest_out_bin[4]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(src_in_bin[4]), .Q(async_path[4]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "SINGLE" *) module fifo1KB_34bit_xpm_cdc_single (src_clk, src_in, dest_clk, dest_out); input src_clk; input src_in; input dest_clk; output dest_out; wire dest_clk; wire src_in; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [3:0]syncstages_ff; assign dest_out = syncstages_ff[3]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_in), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[3] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[2]), .Q(syncstages_ff[3]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "SINGLE" *) module fifo1KB_34bit_xpm_cdc_single__2 (src_clk, src_in, dest_clk, dest_out); input src_clk; input src_in; input dest_clk; output dest_out; wire dest_clk; wire src_in; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [3:0]syncstages_ff; assign dest_out = syncstages_ff[3]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_in), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SINGLE" *) FDRE \syncstages_ff_reg[3] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[2]), .Q(syncstages_ff[3]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module fifo1KB_34bit_blk_mem_gen_generic_cstr (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, AS, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 , din); output [33:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input [0:0]AS; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; input [33:0]din; wire [0:0]AS; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; wire [0:0]E; wire [33:0]din; wire [33:0]dout; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fifo1KB_34bit_blk_mem_gen_prim_width \ramloop[0].ram.r (.AS(AS), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ), .E(E), .din(din), .dout(dout), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module fifo1KB_34bit_blk_mem_gen_prim_width (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, AS, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 , din); output [33:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input [0:0]AS; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; input [33:0]din; wire [0:0]AS; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; wire [0:0]E; wire [33:0]din; wire [33:0]dout; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fifo1KB_34bit_blk_mem_gen_prim_wrapper \prim_noinit.ram (.AS(AS), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ), .E(E), .din(din), .dout(dout), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module fifo1KB_34bit_blk_mem_gen_prim_wrapper (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, AS, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1 , din); output [33:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input [0:0]AS; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1 ; input [33:0]din; wire [0:0]AS; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ; wire [0:0]E; wire [33:0]din; wire [33:0]dout; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; (* box_type = "PRIMITIVE" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(18'h00000), .INIT_B(18'h00000), .INIT_FILE("NONE"), .IS_CLKARDCLK_INVERTED(1'b0), .IS_CLKBWRCLK_INVERTED(1'b0), .IS_ENARDEN_INVERTED(1'b0), .IS_ENBWREN_INVERTED(1'b0), .IS_RSTRAMARSTRAM_INVERTED(1'b0), .IS_RSTRAMB_INVERTED(1'b0), .IS_RSTREGARSTREG_INVERTED(1'b0), .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (.ADDRARDADDR({1'b0,1'b0,1'b0,1'b0,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ,1'b0,1'b0,1'b0,1'b0,1'b0}), .ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1 ,1'b0,1'b0,1'b0,1'b0,1'b0}), .CLKARDCLK(rd_clk), .CLKBWRCLK(wr_clk), .DIADI({din[16:9],din[7:0]}), .DIBDI({din[33:26],din[24:17]}), .DIPADIP({1'b0,din[8]}), .DIPBDIP({1'b0,din[25]}), .DOADO({dout[16:9],dout[7:0]}), .DOBDO({dout[33:26],dout[24:17]}), .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ,dout[8]}), .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ,dout[25]}), .ENARDEN(tmp_ram_rd_en), .ENBWREN(E), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(AS), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE({E,E,E,E})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module fifo1KB_34bit_blk_mem_gen_top (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, AS, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 , din); output [33:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input [0:0]AS; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; input [33:0]din; wire [0:0]AS; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; wire [0:0]E; wire [33:0]din; wire [33:0]dout; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fifo1KB_34bit_blk_mem_gen_generic_cstr \valid.cstr (.AS(AS), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ), .E(E), .din(din), .dout(dout), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) module fifo1KB_34bit_blk_mem_gen_v8_4_4 (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, AS, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 , din); output [33:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input [0:0]AS; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; input [33:0]din; wire [0:0]AS; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; wire [0:0]E; wire [33:0]din; wire [33:0]dout; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fifo1KB_34bit_blk_mem_gen_v8_4_4_synth inst_blk_mem_gen (.AS(AS), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ), .E(E), .din(din), .dout(dout), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *) module fifo1KB_34bit_blk_mem_gen_v8_4_4_synth (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, AS, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 , din); output [33:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input [0:0]AS; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; input [33:0]din; wire [0:0]AS; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; wire [0:0]E; wire [33:0]din; wire [33:0]dout; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fifo1KB_34bit_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.AS(AS), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ), .E(E), .din(din), .dout(dout), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "clk_x_pntrs" *) module fifo1KB_34bit_clk_x_pntrs (\grstd1.grst_full.grst_f.rst_d3_reg , RD_PNTR_WR, \dest_out_bin_ff_reg[3] , D, \dest_out_bin_ff_reg[3]_0 , WR_PNTR_RD, \dest_out_bin_ff_reg[3]_1 , ram_full_fb_i_reg, E, out, Q, ram_full_fb_i_reg_0, \src_gray_ff_reg[4] , \src_gray_ff_reg[4]_0 , ram_empty_i_reg, wr_clk, rd_clk); output \grstd1.grst_full.grst_f.rst_d3_reg ; output [4:0]RD_PNTR_WR; output \dest_out_bin_ff_reg[3] ; output [2:0]D; output \dest_out_bin_ff_reg[3]_0 ; output [1:0]WR_PNTR_RD; output \dest_out_bin_ff_reg[3]_1 ; input ram_full_fb_i_reg; input [0:0]E; input out; input [4:0]Q; input [1:0]ram_full_fb_i_reg_0; input [4:0]\src_gray_ff_reg[4] ; input [4:0]\src_gray_ff_reg[4]_0 ; input [2:0]ram_empty_i_reg; input wr_clk; input rd_clk; wire [2:0]D; wire [0:0]E; wire [4:0]Q; wire [4:0]RD_PNTR_WR; wire [1:0]WR_PNTR_RD; wire \dest_out_bin_ff_reg[3] ; wire \dest_out_bin_ff_reg[3]_0 ; wire \dest_out_bin_ff_reg[3]_1 ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire out; wire [2:0]ram_empty_i_reg; wire ram_full_fb_i_reg; wire [1:0]ram_full_fb_i_reg_0; wire ram_full_i_i_3_n_0; wire ram_full_i_i_4_n_0; wire ram_full_i_i_5_n_0; wire rd_clk; wire [4:0]\src_gray_ff_reg[4] ; wire [4:0]\src_gray_ff_reg[4]_0 ; wire wr_clk; wire \wr_data_count_i[4]_i_2_n_0 ; wire [4:2]wr_pntr_rd; LUT4 #( .INIT(16'hB44B)) \gdiff.diff_pntr_pad[5]_i_5 (.I0(RD_PNTR_WR[3]), .I1(Q[3]), .I2(RD_PNTR_WR[4]), .I3(Q[4]), .O(\dest_out_bin_ff_reg[3] )); LUT6 #( .INIT(64'h9009000000009009)) ram_empty_i_i_2 (.I0(wr_pntr_rd[3]), .I1(\src_gray_ff_reg[4]_0 [3]), .I2(wr_pntr_rd[2]), .I3(\src_gray_ff_reg[4]_0 [2]), .I4(\src_gray_ff_reg[4]_0 [4]), .I5(wr_pntr_rd[4]), .O(\dest_out_bin_ff_reg[3]_0 )); LUT6 #( .INIT(64'h9009000000009009)) ram_empty_i_i_5 (.I0(wr_pntr_rd[3]), .I1(ram_empty_i_reg[1]), .I2(wr_pntr_rd[2]), .I3(ram_empty_i_reg[0]), .I4(ram_empty_i_reg[2]), .I5(wr_pntr_rd[4]), .O(\dest_out_bin_ff_reg[3]_1 )); LUT6 #( .INIT(64'h00000000FF808080)) ram_full_i_i_1 (.I0(ram_full_fb_i_reg), .I1(ram_full_i_i_3_n_0), .I2(E), .I3(ram_full_i_i_4_n_0), .I4(ram_full_i_i_5_n_0), .I5(out), .O(\grstd1.grst_full.grst_f.rst_d3_reg )); LUT4 #( .INIT(16'h9009)) ram_full_i_i_3 (.I0(RD_PNTR_WR[0]), .I1(ram_full_fb_i_reg_0[0]), .I2(RD_PNTR_WR[1]), .I3(ram_full_fb_i_reg_0[1]), .O(ram_full_i_i_3_n_0)); LUT4 #( .INIT(16'h9009)) ram_full_i_i_4 (.I0(RD_PNTR_WR[0]), .I1(Q[0]), .I2(Q[1]), .I3(RD_PNTR_WR[1]), .O(ram_full_i_i_4_n_0)); LUT6 #( .INIT(64'h9009000000009009)) ram_full_i_i_5 (.I0(RD_PNTR_WR[3]), .I1(Q[3]), .I2(RD_PNTR_WR[2]), .I3(Q[2]), .I4(Q[4]), .I5(RD_PNTR_WR[4]), .O(ram_full_i_i_5_n_0)); (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* REG_OUTPUT = "1" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "5" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) fifo1KB_34bit_xpm_cdc_gray rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(RD_PNTR_WR), .src_clk(rd_clk), .src_in_bin(\src_gray_ff_reg[4]_0 )); LUT4 #( .INIT(16'h2DD2)) \wr_data_count_i[1]_i_1 (.I0(RD_PNTR_WR[0]), .I1(\src_gray_ff_reg[4] [0]), .I2(RD_PNTR_WR[1]), .I3(\src_gray_ff_reg[4] [1]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'h69)) \wr_data_count_i[3]_i_1 (.I0(\wr_data_count_i[4]_i_2_n_0 ), .I1(RD_PNTR_WR[3]), .I2(\src_gray_ff_reg[4] [3]), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT5 #( .INIT(32'h718E8E71)) \wr_data_count_i[4]_i_1 (.I0(\wr_data_count_i[4]_i_2_n_0 ), .I1(\src_gray_ff_reg[4] [3]), .I2(RD_PNTR_WR[3]), .I3(RD_PNTR_WR[4]), .I4(\src_gray_ff_reg[4] [4]), .O(D[2])); LUT6 #( .INIT(64'hD4DD4444DDDDD4DD)) \wr_data_count_i[4]_i_2 (.I0(RD_PNTR_WR[2]), .I1(\src_gray_ff_reg[4] [2]), .I2(\src_gray_ff_reg[4] [0]), .I3(RD_PNTR_WR[0]), .I4(\src_gray_ff_reg[4] [1]), .I5(RD_PNTR_WR[1]), .O(\wr_data_count_i[4]_i_2_n_0 )); (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* REG_OUTPUT = "1" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "5" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) fifo1KB_34bit_xpm_cdc_gray__2 wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin({wr_pntr_rd,WR_PNTR_RD}), .src_clk(wr_clk), .src_in_bin(\src_gray_ff_reg[4] )); endmodule (* ORIG_REF_NAME = "fifo_generator_ramfifo" *) module fifo1KB_34bit_fifo_generator_ramfifo (wr_rst_busy, AR, dout, empty, full, wr_data_count, prog_full, rst, wr_clk, rd_clk, din, wr_en, rd_en); output wr_rst_busy; output [0:0]AR; output [33:0]dout; output empty; output full; output [4:0]wr_data_count; output prog_full; input rst; input wr_clk; input rd_clk; input [33:0]din; input wr_en; input rd_en; wire [0:0]AR; wire [33:0]din; wire [33:0]dout; wire empty; wire full; wire \gntv_or_sync_fifo.gcx.clkx_n_0 ; wire \gntv_or_sync_fifo.gcx.clkx_n_10 ; wire \gntv_or_sync_fifo.gcx.clkx_n_13 ; wire \gntv_or_sync_fifo.gcx.clkx_n_6 ; wire \gntv_or_sync_fifo.gl0.wr_n_15 ; wire [4:1]minusOp; wire prog_full; wire ram_wr_en; wire rd_clk; wire rd_en; wire [4:0]rd_pntr; wire [4:2]rd_pntr_plus1; wire [4:0]rd_pntr_wr; wire rst; wire rst_full_ff_i; wire rst_full_gen_i; wire rstblk_n_0; wire tmp_ram_rd_en; wire wr_clk; wire [4:0]wr_data_count; wire wr_en; wire [4:0]wr_pntr; wire [4:0]wr_pntr_plus1; wire [1:0]wr_pntr_plus2; wire [1:0]wr_pntr_rd; wire wr_rst_busy; fifo1KB_34bit_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx (.D({minusOp[4:3],minusOp[1]}), .E(ram_wr_en), .Q(wr_pntr_plus1), .RD_PNTR_WR(rd_pntr_wr), .WR_PNTR_RD(wr_pntr_rd), .\dest_out_bin_ff_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_6 ), .\dest_out_bin_ff_reg[3]_0 (\gntv_or_sync_fifo.gcx.clkx_n_10 ), .\dest_out_bin_ff_reg[3]_1 (\gntv_or_sync_fifo.gcx.clkx_n_13 ), .\grstd1.grst_full.grst_f.rst_d3_reg (\gntv_or_sync_fifo.gcx.clkx_n_0 ), .out(rst_full_gen_i), .ram_empty_i_reg(rd_pntr_plus1), .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_15 ), .ram_full_fb_i_reg_0(wr_pntr_plus2), .rd_clk(rd_clk), .\src_gray_ff_reg[4] (wr_pntr), .\src_gray_ff_reg[4]_0 (rd_pntr), .wr_clk(wr_clk)); fifo1KB_34bit_rd_logic \gntv_or_sync_fifo.gl0.rd (.AS(AR), .Q(rd_pntr_plus1), .WR_PNTR_RD(wr_pntr_rd), .empty(empty), .\gc0.count_d1_reg[4] (rd_pntr), .ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_10 ), .ram_empty_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_13 ), .rd_clk(rd_clk), .rd_en(rd_en), .tmp_ram_rd_en(tmp_ram_rd_en)); fifo1KB_34bit_wr_logic \gntv_or_sync_fifo.gl0.wr (.AR(rstblk_n_0), .D({minusOp[4:3],minusOp[1]}), .E(ram_wr_en), .Q(wr_pntr_plus1), .RD_PNTR_WR(rd_pntr_wr), .full(full), .\gdiff.diff_pntr_pad_reg[5] (\gntv_or_sync_fifo.gcx.clkx_n_6 ), .\gic0.gc0.count_d2_reg[4] (wr_pntr), .\gic0.gc0.count_reg[1] (wr_pntr_plus2), .\gic0.gc0.count_reg[3] (\gntv_or_sync_fifo.gl0.wr_n_15 ), .\gpf1.prog_full_i_reg (rst_full_gen_i), .out(rst_full_ff_i), .prog_full(prog_full), .ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en)); fifo1KB_34bit_memory \gntv_or_sync_fifo.mem (.AS(AR), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (rd_pntr), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (wr_pntr), .E(ram_wr_en), .din(din), .dout(dout), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); fifo1KB_34bit_reset_blk_ramfifo rstblk (.AR(rstblk_n_0), .AS(AR), .\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_gen_i), .out(rst_full_ff_i), .rd_clk(rd_clk), .rst(rst), .wr_clk(wr_clk), .wr_rst_busy(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "fifo_generator_top" *) module fifo1KB_34bit_fifo_generator_top (wr_rst_busy, AS, dout, empty, full, wr_data_count, prog_full, rst, wr_clk, rd_clk, din, wr_en, rd_en); output wr_rst_busy; output [0:0]AS; output [33:0]dout; output empty; output full; output [4:0]wr_data_count; output prog_full; input rst; input wr_clk; input rd_clk; input [33:0]din; input wr_en; input rd_en; wire [0:0]AS; wire [33:0]din; wire [33:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire [4:0]wr_data_count; wire wr_en; wire wr_rst_busy; fifo1KB_34bit_fifo_generator_ramfifo \grf.rf (.AR(AS), .din(din), .dout(dout), .empty(empty), .full(full), .prog_full(prog_full), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "5" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "34" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "34" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "27" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "26" *) (* C_PROG_FULL_TYPE = "1" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "5" *) (* C_RD_DEPTH = "32" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "5" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "5" *) (* C_WR_DEPTH = "32" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "5" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_2_5" *) module fifo1KB_34bit_fifo_generator_v13_2_5 (backup, backup_marker, clk, rst, srst, wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, prog_empty_thresh, prog_empty_thresh_assert, prog_empty_thresh_negate, prog_full_thresh, prog_full_thresh_assert, prog_full_thresh_negate, int_clk, injectdbiterr, injectsbiterr, sleep, dout, full, almost_full, wr_ack, overflow, empty, almost_empty, valid, underflow, data_count, rd_data_count, wr_data_count, prog_full, prog_empty, sbiterr, dbiterr, wr_rst_busy, rd_rst_busy, m_aclk, s_aclk, s_aresetn, m_aclk_en, s_aclk_en, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awregion, s_axi_awuser, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wuser, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_buser, s_axi_bvalid, s_axi_bready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awregion, m_axi_awuser, m_axi_awvalid, m_axi_awready, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wuser, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_buser, m_axi_bvalid, m_axi_bready, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arregion, s_axi_aruser, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_ruser, s_axi_rvalid, s_axi_rready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arregion, m_axi_aruser, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_ruser, m_axi_rvalid, m_axi_rready, s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tstrb, s_axis_tkeep, s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tstrb, m_axis_tkeep, m_axis_tlast, m_axis_tid, m_axis_tdest, m_axis_tuser, axi_aw_injectsbiterr, axi_aw_injectdbiterr, axi_aw_prog_full_thresh, axi_aw_prog_empty_thresh, axi_aw_data_count, axi_aw_wr_data_count, axi_aw_rd_data_count, axi_aw_sbiterr, axi_aw_dbiterr, axi_aw_overflow, axi_aw_underflow, axi_aw_prog_full, axi_aw_prog_empty, axi_w_injectsbiterr, axi_w_injectdbiterr, axi_w_prog_full_thresh, axi_w_prog_empty_thresh, axi_w_data_count, axi_w_wr_data_count, axi_w_rd_data_count, axi_w_sbiterr, axi_w_dbiterr, axi_w_overflow, axi_w_underflow, axi_w_prog_full, axi_w_prog_empty, axi_b_injectsbiterr, axi_b_injectdbiterr, axi_b_prog_full_thresh, axi_b_prog_empty_thresh, axi_b_data_count, axi_b_wr_data_count, axi_b_rd_data_count, axi_b_sbiterr, axi_b_dbiterr, axi_b_overflow, axi_b_underflow, axi_b_prog_full, axi_b_prog_empty, axi_ar_injectsbiterr, axi_ar_injectdbiterr, axi_ar_prog_full_thresh, axi_ar_prog_empty_thresh, axi_ar_data_count, axi_ar_wr_data_count, axi_ar_rd_data_count, axi_ar_sbiterr, axi_ar_dbiterr, axi_ar_overflow, axi_ar_underflow, axi_ar_prog_full, axi_ar_prog_empty, axi_r_injectsbiterr, axi_r_injectdbiterr, axi_r_prog_full_thresh, axi_r_prog_empty_thresh, axi_r_data_count, axi_r_wr_data_count, axi_r_rd_data_count, axi_r_sbiterr, axi_r_dbiterr, axi_r_overflow, axi_r_underflow, axi_r_prog_full, axi_r_prog_empty, axis_injectsbiterr, axis_injectdbiterr, axis_prog_full_thresh, axis_prog_empty_thresh, axis_data_count, axis_wr_data_count, axis_rd_data_count, axis_sbiterr, axis_dbiterr, axis_overflow, axis_underflow, axis_prog_full, axis_prog_empty); input backup; input backup_marker; input clk; input rst; input srst; input wr_clk; input wr_rst; input rd_clk; input rd_rst; input [33:0]din; input wr_en; input rd_en; input [4:0]prog_empty_thresh; input [4:0]prog_empty_thresh_assert; input [4:0]prog_empty_thresh_negate; input [4:0]prog_full_thresh; input [4:0]prog_full_thresh_assert; input [4:0]prog_full_thresh_negate; input int_clk; input injectdbiterr; input injectsbiterr; input sleep; output [33:0]dout; output full; output almost_full; output wr_ack; output overflow; output empty; output almost_empty; output valid; output underflow; output [4:0]data_count; output [4:0]rd_data_count; output [4:0]wr_data_count; output prog_full; output prog_empty; output sbiterr; output dbiterr; output wr_rst_busy; output rd_rst_busy; input m_aclk; input s_aclk; input s_aresetn; input m_aclk_en; input s_aclk_en; input [0:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; input [3:0]s_axi_awregion; input [0:0]s_axi_awuser; input s_axi_awvalid; output s_axi_awready; input [0:0]s_axi_wid; input [63:0]s_axi_wdata; input [7:0]s_axi_wstrb; input s_axi_wlast; input [0:0]s_axi_wuser; input s_axi_wvalid; output s_axi_wready; output [0:0]s_axi_bid; output [1:0]s_axi_bresp; output [0:0]s_axi_buser; output s_axi_bvalid; input s_axi_bready; output [0:0]m_axi_awid; output [31:0]m_axi_awaddr; output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; output [0:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; output [3:0]m_axi_awqos; output [3:0]m_axi_awregion; output [0:0]m_axi_awuser; output m_axi_awvalid; input m_axi_awready; output [0:0]m_axi_wid; output [63:0]m_axi_wdata; output [7:0]m_axi_wstrb; output m_axi_wlast; output [0:0]m_axi_wuser; output m_axi_wvalid; input m_axi_wready; input [0:0]m_axi_bid; input [1:0]m_axi_bresp; input [0:0]m_axi_buser; input m_axi_bvalid; output m_axi_bready; input [0:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; input [3:0]s_axi_arregion; input [0:0]s_axi_aruser; input s_axi_arvalid; output s_axi_arready; output [0:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output [0:0]s_axi_ruser; output s_axi_rvalid; input s_axi_rready; output [0:0]m_axi_arid; output [31:0]m_axi_araddr; output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arqos; output [3:0]m_axi_arregion; output [0:0]m_axi_aruser; output m_axi_arvalid; input m_axi_arready; input [0:0]m_axi_rid; input [63:0]m_axi_rdata; input [1:0]m_axi_rresp; input m_axi_rlast; input [0:0]m_axi_ruser; input m_axi_rvalid; output m_axi_rready; input s_axis_tvalid; output s_axis_tready; input [7:0]s_axis_tdata; input [0:0]s_axis_tstrb; input [0:0]s_axis_tkeep; input s_axis_tlast; input [0:0]s_axis_tid; input [0:0]s_axis_tdest; input [3:0]s_axis_tuser; output m_axis_tvalid; input m_axis_tready; output [7:0]m_axis_tdata; output [0:0]m_axis_tstrb; output [0:0]m_axis_tkeep; output m_axis_tlast; output [0:0]m_axis_tid; output [0:0]m_axis_tdest; output [3:0]m_axis_tuser; input axi_aw_injectsbiterr; input axi_aw_injectdbiterr; input [3:0]axi_aw_prog_full_thresh; input [3:0]axi_aw_prog_empty_thresh; output [4:0]axi_aw_data_count; output [4:0]axi_aw_wr_data_count; output [4:0]axi_aw_rd_data_count; output axi_aw_sbiterr; output axi_aw_dbiterr; output axi_aw_overflow; output axi_aw_underflow; output axi_aw_prog_full; output axi_aw_prog_empty; input axi_w_injectsbiterr; input axi_w_injectdbiterr; input [9:0]axi_w_prog_full_thresh; input [9:0]axi_w_prog_empty_thresh; output [10:0]axi_w_data_count; output [10:0]axi_w_wr_data_count; output [10:0]axi_w_rd_data_count; output axi_w_sbiterr; output axi_w_dbiterr; output axi_w_overflow; output axi_w_underflow; output axi_w_prog_full; output axi_w_prog_empty; input axi_b_injectsbiterr; input axi_b_injectdbiterr; input [3:0]axi_b_prog_full_thresh; input [3:0]axi_b_prog_empty_thresh; output [4:0]axi_b_data_count; output [4:0]axi_b_wr_data_count; output [4:0]axi_b_rd_data_count; output axi_b_sbiterr; output axi_b_dbiterr; output axi_b_overflow; output axi_b_underflow; output axi_b_prog_full; output axi_b_prog_empty; input axi_ar_injectsbiterr; input axi_ar_injectdbiterr; input [3:0]axi_ar_prog_full_thresh; input [3:0]axi_ar_prog_empty_thresh; output [4:0]axi_ar_data_count; output [4:0]axi_ar_wr_data_count; output [4:0]axi_ar_rd_data_count; output axi_ar_sbiterr; output axi_ar_dbiterr; output axi_ar_overflow; output axi_ar_underflow; output axi_ar_prog_full; output axi_ar_prog_empty; input axi_r_injectsbiterr; input axi_r_injectdbiterr; input [9:0]axi_r_prog_full_thresh; input [9:0]axi_r_prog_empty_thresh; output [10:0]axi_r_data_count; output [10:0]axi_r_wr_data_count; output [10:0]axi_r_rd_data_count; output axi_r_sbiterr; output axi_r_dbiterr; output axi_r_overflow; output axi_r_underflow; output axi_r_prog_full; output axi_r_prog_empty; input axis_injectsbiterr; input axis_injectdbiterr; input [9:0]axis_prog_full_thresh; input [9:0]axis_prog_empty_thresh; output [10:0]axis_data_count; output [10:0]axis_wr_data_count; output [10:0]axis_rd_data_count; output axis_sbiterr; output axis_dbiterr; output axis_overflow; output axis_underflow; output axis_prog_full; output axis_prog_empty; wire \ ; wire \ ; wire [33:0]din; wire [33:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rd_rst_busy; wire rst; wire wr_clk; wire [4:0]wr_data_count; wire wr_en; wire wr_rst_busy; assign almost_empty = \ ; assign almost_full = \ ; assign axi_ar_data_count[4] = \ ; assign axi_ar_data_count[3] = \ ; assign axi_ar_data_count[2] = \ ; assign axi_ar_data_count[1] = \ ; assign axi_ar_data_count[0] = \ ; assign axi_ar_dbiterr = \ ; assign axi_ar_overflow = \ ; assign axi_ar_prog_empty = \ ; assign axi_ar_prog_full = \ ; assign axi_ar_rd_data_count[4] = \ ; assign axi_ar_rd_data_count[3] = \ ; assign axi_ar_rd_data_count[2] = \ ; assign axi_ar_rd_data_count[1] = \ ; assign axi_ar_rd_data_count[0] = \ ; assign axi_ar_sbiterr = \ ; assign axi_ar_underflow = \ ; assign axi_ar_wr_data_count[4] = \ ; assign axi_ar_wr_data_count[3] = \ ; assign axi_ar_wr_data_count[2] = \ ; assign axi_ar_wr_data_count[1] = \ ; assign axi_ar_wr_data_count[0] = \ ; assign axi_aw_data_count[4] = \ ; assign axi_aw_data_count[3] = \ ; assign axi_aw_data_count[2] = \ ; assign axi_aw_data_count[1] = \ ; assign axi_aw_data_count[0] = \ ; assign axi_aw_dbiterr = \ ; assign axi_aw_overflow = \ ; assign axi_aw_prog_empty = \ ; assign axi_aw_prog_full = \ ; assign axi_aw_rd_data_count[4] = \ ; assign axi_aw_rd_data_count[3] = \ ; assign axi_aw_rd_data_count[2] = \ ; assign axi_aw_rd_data_count[1] = \ ; assign axi_aw_rd_data_count[0] = \ ; assign axi_aw_sbiterr = \ ; assign axi_aw_underflow = \ ; assign axi_aw_wr_data_count[4] = \ ; assign axi_aw_wr_data_count[3] = \ ; assign axi_aw_wr_data_count[2] = \ ; assign axi_aw_wr_data_count[1] = \ ; assign axi_aw_wr_data_count[0] = \ ; assign axi_b_data_count[4] = \ ; assign axi_b_data_count[3] = \ ; assign axi_b_data_count[2] = \ ; assign axi_b_data_count[1] = \ ; assign axi_b_data_count[0] = \ ; assign axi_b_dbiterr = \ ; assign axi_b_overflow = \ ; assign axi_b_prog_empty = \ ; assign axi_b_prog_full = \ ; assign axi_b_rd_data_count[4] = \ ; assign axi_b_rd_data_count[3] = \ ; assign axi_b_rd_data_count[2] = \ ; assign axi_b_rd_data_count[1] = \ ; assign axi_b_rd_data_count[0] = \ ; assign axi_b_sbiterr = \ ; assign axi_b_underflow = \ ; assign axi_b_wr_data_count[4] = \ ; assign axi_b_wr_data_count[3] = \ ; assign axi_b_wr_data_count[2] = \ ; assign axi_b_wr_data_count[1] = \ ; assign axi_b_wr_data_count[0] = \ ; assign axi_r_data_count[10] = \ ; assign axi_r_data_count[9] = \ ; assign axi_r_data_count[8] = \ ; assign axi_r_data_count[7] = \ ; assign axi_r_data_count[6] = \ ; assign axi_r_data_count[5] = \ ; assign axi_r_data_count[4] = \ ; assign axi_r_data_count[3] = \ ; assign axi_r_data_count[2] = \ ; assign axi_r_data_count[1] = \ ; assign axi_r_data_count[0] = \ ; assign axi_r_dbiterr = \ ; assign axi_r_overflow = \ ; assign axi_r_prog_empty = \ ; assign axi_r_prog_full = \ ; assign axi_r_rd_data_count[10] = \ ; assign axi_r_rd_data_count[9] = \ ; assign axi_r_rd_data_count[8] = \ ; assign axi_r_rd_data_count[7] = \ ; assign axi_r_rd_data_count[6] = \ ; assign axi_r_rd_data_count[5] = \ ; assign axi_r_rd_data_count[4] = \ ; assign axi_r_rd_data_count[3] = \ ; assign axi_r_rd_data_count[2] = \ ; assign axi_r_rd_data_count[1] = \ ; assign axi_r_rd_data_count[0] = \ ; assign axi_r_sbiterr = \ ; assign axi_r_underflow = \ ; assign axi_r_wr_data_count[10] = \ ; assign axi_r_wr_data_count[9] = \ ; assign axi_r_wr_data_count[8] = \ ; assign axi_r_wr_data_count[7] = \ ; assign axi_r_wr_data_count[6] = \ ; assign axi_r_wr_data_count[5] = \ ; assign axi_r_wr_data_count[4] = \ ; assign axi_r_wr_data_count[3] = \ ; assign axi_r_wr_data_count[2] = \ ; assign axi_r_wr_data_count[1] = \ ; assign axi_r_wr_data_count[0] = \ ; assign axi_w_data_count[10] = \ ; assign axi_w_data_count[9] = \ ; assign axi_w_data_count[8] = \ ; assign axi_w_data_count[7] = \ ; assign axi_w_data_count[6] = \ ; assign axi_w_data_count[5] = \ ; assign axi_w_data_count[4] = \ ; assign axi_w_data_count[3] = \ ; assign axi_w_data_count[2] = \ ; assign axi_w_data_count[1] = \ ; assign axi_w_data_count[0] = \ ; assign axi_w_dbiterr = \ ; assign axi_w_overflow = \ ; assign axi_w_prog_empty = \ ; assign axi_w_prog_full = \ ; assign axi_w_rd_data_count[10] = \ ; assign axi_w_rd_data_count[9] = \ ; assign axi_w_rd_data_count[8] = \ ; assign axi_w_rd_data_count[7] = \ ; assign axi_w_rd_data_count[6] = \ ; assign axi_w_rd_data_count[5] = \ ; assign axi_w_rd_data_count[4] = \ ; assign axi_w_rd_data_count[3] = \ ; assign axi_w_rd_data_count[2] = \ ; assign axi_w_rd_data_count[1] = \ ; assign axi_w_rd_data_count[0] = \ ; assign axi_w_sbiterr = \ ; assign axi_w_underflow = \ ; assign axi_w_wr_data_count[10] = \ ; assign axi_w_wr_data_count[9] = \ ; assign axi_w_wr_data_count[8] = \ ; assign axi_w_wr_data_count[7] = \ ; assign axi_w_wr_data_count[6] = \ ; assign axi_w_wr_data_count[5] = \ ; assign axi_w_wr_data_count[4] = \ ; assign axi_w_wr_data_count[3] = \ ; assign axi_w_wr_data_count[2] = \ ; assign axi_w_wr_data_count[1] = \ ; assign axi_w_wr_data_count[0] = \ ; assign axis_data_count[10] = \ ; assign axis_data_count[9] = \ ; assign axis_data_count[8] = \ ; assign axis_data_count[7] = \ ; assign axis_data_count[6] = \ ; assign axis_data_count[5] = \ ; assign axis_data_count[4] = \ ; assign axis_data_count[3] = \ ; assign axis_data_count[2] = \ ; assign axis_data_count[1] = \ ; assign axis_data_count[0] = \ ; assign axis_dbiterr = \ ; assign axis_overflow = \ ; assign axis_prog_empty = \ ; assign axis_prog_full = \ ; assign axis_rd_data_count[10] = \ ; assign axis_rd_data_count[9] = \ ; assign axis_rd_data_count[8] = \ ; assign axis_rd_data_count[7] = \ ; assign axis_rd_data_count[6] = \ ; assign axis_rd_data_count[5] = \ ; assign axis_rd_data_count[4] = \ ; assign axis_rd_data_count[3] = \ ; assign axis_rd_data_count[2] = \ ; assign axis_rd_data_count[1] = \ ; assign axis_rd_data_count[0] = \ ; assign axis_sbiterr = \ ; assign axis_underflow = \ ; assign axis_wr_data_count[10] = \ ; assign axis_wr_data_count[9] = \ ; assign axis_wr_data_count[8] = \ ; assign axis_wr_data_count[7] = \ ; assign axis_wr_data_count[6] = \ ; assign axis_wr_data_count[5] = \ ; assign axis_wr_data_count[4] = \ ; assign axis_wr_data_count[3] = \ ; assign axis_wr_data_count[2] = \ ; assign axis_wr_data_count[1] = \ ; assign axis_wr_data_count[0] = \ ; assign data_count[4] = \ ; assign data_count[3] = \ ; assign data_count[2] = \ ; assign data_count[1] = \ ; assign data_count[0] = \ ; assign dbiterr = \ ; assign m_axi_araddr[31] = \ ; assign m_axi_araddr[30] = \ ; assign m_axi_araddr[29] = \ ; assign m_axi_araddr[28] = \ ; assign m_axi_araddr[27] = \ ; assign m_axi_araddr[26] = \ ; assign m_axi_araddr[25] = \ ; assign m_axi_araddr[24] = \ ; assign m_axi_araddr[23] = \ ; assign m_axi_araddr[22] = \ ; assign m_axi_araddr[21] = \ ; assign m_axi_araddr[20] = \ ; assign m_axi_araddr[19] = \ ; assign m_axi_araddr[18] = \ ; assign m_axi_araddr[17] = \ ; assign m_axi_araddr[16] = \ ; assign m_axi_araddr[15] = \ ; assign m_axi_araddr[14] = \ ; assign m_axi_araddr[13] = \ ; assign m_axi_araddr[12] = \ ; assign m_axi_araddr[11] = \ ; assign m_axi_araddr[10] = \ ; assign m_axi_araddr[9] = \ ; assign m_axi_araddr[8] = \ ; assign m_axi_araddr[7] = \ ; assign m_axi_araddr[6] = \ ; assign m_axi_araddr[5] = \ ; assign m_axi_araddr[4] = \ ; assign m_axi_araddr[3] = \ ; assign m_axi_araddr[2] = \ ; assign m_axi_araddr[1] = \ ; assign m_axi_araddr[0] = \ ; assign m_axi_arburst[1] = \ ; assign m_axi_arburst[0] = \ ; assign m_axi_arcache[3] = \ ; assign m_axi_arcache[2] = \ ; assign m_axi_arcache[1] = \ ; assign m_axi_arcache[0] = \ ; assign m_axi_arid[0] = \ ; assign m_axi_arlen[7] = \ ; assign m_axi_arlen[6] = \ ; assign m_axi_arlen[5] = \ ; assign m_axi_arlen[4] = \ ; assign m_axi_arlen[3] = \ ; assign m_axi_arlen[2] = \ ; assign m_axi_arlen[1] = \ ; assign m_axi_arlen[0] = \ ; assign m_axi_arlock[0] = \ ; assign m_axi_arprot[2] = \ ; assign m_axi_arprot[1] = \ ; assign m_axi_arprot[0] = \ ; assign m_axi_arqos[3] = \ ; assign m_axi_arqos[2] = \ ; assign m_axi_arqos[1] = \ ; assign m_axi_arqos[0] = \ ; assign m_axi_arregion[3] = \ ; assign m_axi_arregion[2] = \ ; assign m_axi_arregion[1] = \ ; assign m_axi_arregion[0] = \ ; assign m_axi_arsize[2] = \ ; assign m_axi_arsize[1] = \ ; assign m_axi_arsize[0] = \ ; assign m_axi_aruser[0] = \ ; assign m_axi_arvalid = \ ; assign m_axi_awaddr[31] = \ ; assign m_axi_awaddr[30] = \ ; assign m_axi_awaddr[29] = \ ; assign m_axi_awaddr[28] = \ ; assign m_axi_awaddr[27] = \ ; assign m_axi_awaddr[26] = \ ; assign m_axi_awaddr[25] = \ ; assign m_axi_awaddr[24] = \ ; assign m_axi_awaddr[23] = \ ; assign m_axi_awaddr[22] = \ ; assign m_axi_awaddr[21] = \ ; assign m_axi_awaddr[20] = \ ; assign m_axi_awaddr[19] = \ ; assign m_axi_awaddr[18] = \ ; assign m_axi_awaddr[17] = \ ; assign m_axi_awaddr[16] = \ ; assign m_axi_awaddr[15] = \ ; assign m_axi_awaddr[14] = \ ; assign m_axi_awaddr[13] = \ ; assign m_axi_awaddr[12] = \ ; assign m_axi_awaddr[11] = \ ; assign m_axi_awaddr[10] = \ ; assign m_axi_awaddr[9] = \ ; assign m_axi_awaddr[8] = \ ; assign m_axi_awaddr[7] = \ ; assign m_axi_awaddr[6] = \ ; assign m_axi_awaddr[5] = \ ; assign m_axi_awaddr[4] = \ ; assign m_axi_awaddr[3] = \ ; assign m_axi_awaddr[2] = \ ; assign m_axi_awaddr[1] = \ ; assign m_axi_awaddr[0] = \ ; assign m_axi_awburst[1] = \ ; assign m_axi_awburst[0] = \ ; assign m_axi_awcache[3] = \ ; assign m_axi_awcache[2] = \ ; assign m_axi_awcache[1] = \ ; assign m_axi_awcache[0] = \ ; assign m_axi_awid[0] = \ ; assign m_axi_awlen[7] = \ ; assign m_axi_awlen[6] = \ ; assign m_axi_awlen[5] = \ ; assign m_axi_awlen[4] = \ ; assign m_axi_awlen[3] = \ ; assign m_axi_awlen[2] = \ ; assign m_axi_awlen[1] = \ ; assign m_axi_awlen[0] = \ ; assign m_axi_awlock[0] = \ ; assign m_axi_awprot[2] = \ ; assign m_axi_awprot[1] = \ ; assign m_axi_awprot[0] = \ ; assign m_axi_awqos[3] = \ ; assign m_axi_awqos[2] = \ ; assign m_axi_awqos[1] = \ ; assign m_axi_awqos[0] = \ ; assign m_axi_awregion[3] = \ ; assign m_axi_awregion[2] = \ ; assign m_axi_awregion[1] = \ ; assign m_axi_awregion[0] = \ ; assign m_axi_awsize[2] = \ ; assign m_axi_awsize[1] = \ ; assign m_axi_awsize[0] = \ ; assign m_axi_awuser[0] = \ ; assign m_axi_awvalid = \ ; assign m_axi_bready = \ ; assign m_axi_rready = \ ; assign m_axi_wdata[63] = \ ; assign m_axi_wdata[62] = \ ; assign m_axi_wdata[61] = \ ; assign m_axi_wdata[60] = \ ; assign m_axi_wdata[59] = \ ; assign m_axi_wdata[58] = \ ; assign m_axi_wdata[57] = \ ; assign m_axi_wdata[56] = \ ; assign m_axi_wdata[55] = \ ; assign m_axi_wdata[54] = \ ; assign m_axi_wdata[53] = \ ; assign m_axi_wdata[52] = \ ; assign m_axi_wdata[51] = \ ; assign m_axi_wdata[50] = \ ; assign m_axi_wdata[49] = \ ; assign m_axi_wdata[48] = \ ; assign m_axi_wdata[47] = \ ; assign m_axi_wdata[46] = \ ; assign m_axi_wdata[45] = \ ; assign m_axi_wdata[44] = \ ; assign m_axi_wdata[43] = \ ; assign m_axi_wdata[42] = \ ; assign m_axi_wdata[41] = \ ; assign m_axi_wdata[40] = \ ; assign m_axi_wdata[39] = \ ; assign m_axi_wdata[38] = \ ; assign m_axi_wdata[37] = \ ; assign m_axi_wdata[36] = \ ; assign m_axi_wdata[35] = \ ; assign m_axi_wdata[34] = \ ; assign m_axi_wdata[33] = \ ; assign m_axi_wdata[32] = \ ; assign m_axi_wdata[31] = \ ; assign m_axi_wdata[30] = \ ; assign m_axi_wdata[29] = \ ; assign m_axi_wdata[28] = \ ; assign m_axi_wdata[27] = \ ; assign m_axi_wdata[26] = \ ; assign m_axi_wdata[25] = \ ; assign m_axi_wdata[24] = \ ; assign m_axi_wdata[23] = \ ; assign m_axi_wdata[22] = \ ; assign m_axi_wdata[21] = \ ; assign m_axi_wdata[20] = \ ; assign m_axi_wdata[19] = \ ; assign m_axi_wdata[18] = \ ; assign m_axi_wdata[17] = \ ; assign m_axi_wdata[16] = \ ; assign m_axi_wdata[15] = \ ; assign m_axi_wdata[14] = \ ; assign m_axi_wdata[13] = \ ; assign m_axi_wdata[12] = \ ; assign m_axi_wdata[11] = \ ; assign m_axi_wdata[10] = \ ; assign m_axi_wdata[9] = \ ; assign m_axi_wdata[8] = \ ; assign m_axi_wdata[7] = \ ; assign m_axi_wdata[6] = \ ; assign m_axi_wdata[5] = \ ; assign m_axi_wdata[4] = \ ; assign m_axi_wdata[3] = \ ; assign m_axi_wdata[2] = \ ; assign m_axi_wdata[1] = \ ; assign m_axi_wdata[0] = \ ; assign m_axi_wid[0] = \ ; assign m_axi_wlast = \ ; assign m_axi_wstrb[7] = \ ; assign m_axi_wstrb[6] = \ ; assign m_axi_wstrb[5] = \ ; assign m_axi_wstrb[4] = \ ; assign m_axi_wstrb[3] = \ ; assign m_axi_wstrb[2] = \ ; assign m_axi_wstrb[1] = \ ; assign m_axi_wstrb[0] = \ ; assign m_axi_wuser[0] = \ ; assign m_axi_wvalid = \ ; assign m_axis_tdata[7] = \ ; assign m_axis_tdata[6] = \ ; assign m_axis_tdata[5] = \ ; assign m_axis_tdata[4] = \ ; assign m_axis_tdata[3] = \ ; assign m_axis_tdata[2] = \ ; assign m_axis_tdata[1] = \ ; assign m_axis_tdata[0] = \ ; assign m_axis_tdest[0] = \ ; assign m_axis_tid[0] = \ ; assign m_axis_tkeep[0] = \ ; assign m_axis_tlast = \ ; assign m_axis_tstrb[0] = \ ; assign m_axis_tuser[3] = \ ; assign m_axis_tuser[2] = \ ; assign m_axis_tuser[1] = \ ; assign m_axis_tuser[0] = \ ; assign m_axis_tvalid = \ ; assign overflow = \ ; assign prog_empty = \ ; assign rd_data_count[4] = \ ; assign rd_data_count[3] = \ ; assign rd_data_count[2] = \ ; assign rd_data_count[1] = \ ; assign rd_data_count[0] = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_buser[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_rdata[63] = \ ; assign s_axi_rdata[62] = \ ; assign s_axi_rdata[61] = \ ; assign s_axi_rdata[60] = \ ; assign s_axi_rdata[59] = \ ; assign s_axi_rdata[58] = \ ; assign s_axi_rdata[57] = \ ; assign s_axi_rdata[56] = \ ; assign s_axi_rdata[55] = \ ; assign s_axi_rdata[54] = \ ; assign s_axi_rdata[53] = \ ; assign s_axi_rdata[52] = \ ; assign s_axi_rdata[51] = \ ; assign s_axi_rdata[50] = \ ; assign s_axi_rdata[49] = \ ; assign s_axi_rdata[48] = \ ; assign s_axi_rdata[47] = \ ; assign s_axi_rdata[46] = \ ; assign s_axi_rdata[45] = \ ; assign s_axi_rdata[44] = \ ; assign s_axi_rdata[43] = \ ; assign s_axi_rdata[42] = \ ; assign s_axi_rdata[41] = \ ; assign s_axi_rdata[40] = \ ; assign s_axi_rdata[39] = \ ; assign s_axi_rdata[38] = \ ; assign s_axi_rdata[37] = \ ; assign s_axi_rdata[36] = \ ; assign s_axi_rdata[35] = \ ; assign s_axi_rdata[34] = \ ; assign s_axi_rdata[33] = \ ; assign s_axi_rdata[32] = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rid[0] = \ ; assign s_axi_rlast = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_ruser[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_wready = \ ; assign s_axis_tready = \ ; assign sbiterr = \ ; assign underflow = \ ; assign valid = \ ; assign wr_ack = \ ; GND GND (.G(\ )); VCC VCC (.P(\ )); fifo1KB_34bit_fifo_generator_v13_2_5_synth inst_fifo_gen (.AR(rd_rst_busy), .din(din), .dout(dout), .empty(empty), .full(full), .prog_full(prog_full), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "fifo_generator_v13_2_5_synth" *) module fifo1KB_34bit_fifo_generator_v13_2_5_synth (wr_rst_busy, AR, dout, empty, full, wr_data_count, prog_full, rst, wr_clk, rd_clk, din, wr_en, rd_en); output wr_rst_busy; output [0:0]AR; output [33:0]dout; output empty; output full; output [4:0]wr_data_count; output prog_full; input rst; input wr_clk; input rd_clk; input [33:0]din; input wr_en; input rd_en; wire [0:0]AR; wire [33:0]din; wire [33:0]dout; wire empty; wire full; wire prog_full; wire rd_clk; wire rd_en; wire rst; wire wr_clk; wire [4:0]wr_data_count; wire wr_en; wire wr_rst_busy; fifo1KB_34bit_fifo_generator_top \gconvfifo.rf (.AS(AR), .din(din), .dout(dout), .empty(empty), .full(full), .prog_full(prog_full), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "memory" *) module fifo1KB_34bit_memory (dout, rd_clk, wr_clk, tmp_ram_rd_en, E, AS, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 , din); output [33:0]dout; input rd_clk; input wr_clk; input tmp_ram_rd_en; input [0:0]E; input [0:0]AS; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; input [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; input [33:0]din; wire [0:0]AS; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ; wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ; wire [0:0]E; wire [33:0]din; wire [33:0]dout; wire rd_clk; wire tmp_ram_rd_en; wire wr_clk; fifo1KB_34bit_blk_mem_gen_v8_4_4 \gbm.gbmg.gbmga.ngecc.bmg (.AS(AS), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ), .E(E), .din(din), .dout(dout), .rd_clk(rd_clk), .tmp_ram_rd_en(tmp_ram_rd_en), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module fifo1KB_34bit_rd_bin_cntr (rd_en_0, Q, \gc0.count_d1_reg[4]_0 , ram_empty_i_reg, rd_en, out, ram_empty_i_reg_0, WR_PNTR_RD, E, rd_clk, AS); output rd_en_0; output [2:0]Q; output [4:0]\gc0.count_d1_reg[4]_0 ; input ram_empty_i_reg; input rd_en; input out; input ram_empty_i_reg_0; input [1:0]WR_PNTR_RD; input [0:0]E; input rd_clk; input [0:0]AS; wire [0:0]AS; wire [0:0]E; wire [2:0]Q; wire [1:0]WR_PNTR_RD; wire [4:0]\gc0.count_d1_reg[4]_0 ; wire out; wire [4:0]plusOp__1; wire ram_empty_i_i_3_n_0; wire ram_empty_i_i_4_n_0; wire ram_empty_i_reg; wire ram_empty_i_reg_0; wire rd_clk; wire rd_en; wire rd_en_0; wire [1:0]rd_pntr_plus1; LUT1 #( .INIT(2'h1)) \gc0.count[0]_i_1 (.I0(rd_pntr_plus1[0]), .O(plusOp__1[0])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT2 #( .INIT(4'h6)) \gc0.count[1]_i_1 (.I0(rd_pntr_plus1[0]), .I1(rd_pntr_plus1[1]), .O(plusOp__1[1])); LUT3 #( .INIT(8'h78)) \gc0.count[2]_i_1 (.I0(rd_pntr_plus1[0]), .I1(rd_pntr_plus1[1]), .I2(Q[0]), .O(plusOp__1[2])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT4 #( .INIT(16'h7F80)) \gc0.count[3]_i_1 (.I0(rd_pntr_plus1[1]), .I1(rd_pntr_plus1[0]), .I2(Q[0]), .I3(Q[1]), .O(plusOp__1[3])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT5 #( .INIT(32'h7FFF8000)) \gc0.count[4]_i_1 (.I0(Q[0]), .I1(rd_pntr_plus1[0]), .I2(rd_pntr_plus1[1]), .I3(Q[1]), .I4(Q[2]), .O(plusOp__1[4])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[0] (.C(rd_clk), .CE(E), .CLR(AS), .D(rd_pntr_plus1[0]), .Q(\gc0.count_d1_reg[4]_0 [0])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(rd_clk), .CE(E), .CLR(AS), .D(rd_pntr_plus1[1]), .Q(\gc0.count_d1_reg[4]_0 [1])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(rd_clk), .CE(E), .CLR(AS), .D(Q[0]), .Q(\gc0.count_d1_reg[4]_0 [2])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(rd_clk), .CE(E), .CLR(AS), .D(Q[1]), .Q(\gc0.count_d1_reg[4]_0 [3])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[4] (.C(rd_clk), .CE(E), .CLR(AS), .D(Q[2]), .Q(\gc0.count_d1_reg[4]_0 [4])); FDPE #( .INIT(1'b1)) \gc0.count_reg[0] (.C(rd_clk), .CE(E), .D(plusOp__1[0]), .PRE(AS), .Q(rd_pntr_plus1[0])); FDCE #( .INIT(1'b0)) \gc0.count_reg[1] (.C(rd_clk), .CE(E), .CLR(AS), .D(plusOp__1[1]), .Q(rd_pntr_plus1[1])); FDCE #( .INIT(1'b0)) \gc0.count_reg[2] (.C(rd_clk), .CE(E), .CLR(AS), .D(plusOp__1[2]), .Q(Q[0])); FDCE #( .INIT(1'b0)) \gc0.count_reg[3] (.C(rd_clk), .CE(E), .CLR(AS), .D(plusOp__1[3]), .Q(Q[1])); FDCE #( .INIT(1'b0)) \gc0.count_reg[4] (.C(rd_clk), .CE(E), .CLR(AS), .D(plusOp__1[4]), .Q(Q[2])); LUT6 #( .INIT(64'h88F8888888888888)) ram_empty_i_i_1 (.I0(ram_empty_i_reg), .I1(ram_empty_i_i_3_n_0), .I2(rd_en), .I3(out), .I4(ram_empty_i_i_4_n_0), .I5(ram_empty_i_reg_0), .O(rd_en_0)); LUT4 #( .INIT(16'h9009)) ram_empty_i_i_3 (.I0(\gc0.count_d1_reg[4]_0 [0]), .I1(WR_PNTR_RD[0]), .I2(\gc0.count_d1_reg[4]_0 [1]), .I3(WR_PNTR_RD[1]), .O(ram_empty_i_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT4 #( .INIT(16'h9009)) ram_empty_i_i_4 (.I0(rd_pntr_plus1[0]), .I1(WR_PNTR_RD[0]), .I2(rd_pntr_plus1[1]), .I3(WR_PNTR_RD[1]), .O(ram_empty_i_i_4_n_0)); endmodule (* ORIG_REF_NAME = "rd_logic" *) module fifo1KB_34bit_rd_logic (empty, tmp_ram_rd_en, Q, \gc0.count_d1_reg[4] , rd_clk, AS, ram_empty_i_reg, rd_en, ram_empty_i_reg_0, WR_PNTR_RD); output empty; output tmp_ram_rd_en; output [2:0]Q; output [4:0]\gc0.count_d1_reg[4] ; input rd_clk; input [0:0]AS; input ram_empty_i_reg; input rd_en; input ram_empty_i_reg_0; input [1:0]WR_PNTR_RD; wire [0:0]AS; wire [2:0]Q; wire [1:0]WR_PNTR_RD; wire empty; wire empty_fb_i; wire [4:0]\gc0.count_d1_reg[4] ; wire ram_empty_i_reg; wire ram_empty_i_reg_0; wire ram_rd_en; wire rd_clk; wire rd_en; wire rpntr_n_0; wire tmp_ram_rd_en; fifo1KB_34bit_rd_status_flags_as \gras.rsts (.AS(AS), .E(ram_rd_en), .empty(empty), .out(empty_fb_i), .ram_empty_i_reg_0(rpntr_n_0), .rd_clk(rd_clk), .rd_en(rd_en), .tmp_ram_rd_en(tmp_ram_rd_en)); fifo1KB_34bit_rd_bin_cntr rpntr (.AS(AS), .E(ram_rd_en), .Q(Q), .WR_PNTR_RD(WR_PNTR_RD), .\gc0.count_d1_reg[4]_0 (\gc0.count_d1_reg[4] ), .out(empty_fb_i), .ram_empty_i_reg(ram_empty_i_reg), .ram_empty_i_reg_0(ram_empty_i_reg_0), .rd_clk(rd_clk), .rd_en(rd_en), .rd_en_0(rpntr_n_0)); endmodule (* ORIG_REF_NAME = "rd_status_flags_as" *) module fifo1KB_34bit_rd_status_flags_as (empty, out, tmp_ram_rd_en, E, ram_empty_i_reg_0, rd_clk, AS, rd_en); output empty; output out; output tmp_ram_rd_en; output [0:0]E; input ram_empty_i_reg_0; input rd_clk; input [0:0]AS; input rd_en; wire [0:0]AS; wire [0:0]E; (* DONT_TOUCH *) wire ram_empty_fb_i; (* DONT_TOUCH *) wire ram_empty_i; wire ram_empty_i_reg_0; wire rd_clk; wire rd_en; wire tmp_ram_rd_en; assign empty = ram_empty_i; assign out = ram_empty_fb_i; LUT3 #( .INIT(8'hF4)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1 (.I0(ram_empty_fb_i), .I1(rd_en), .I2(AS), .O(tmp_ram_rd_en)); LUT2 #( .INIT(4'h2)) \gc0.count_d1[4]_i_1 (.I0(rd_en), .I1(ram_empty_fb_i), .O(E)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_fb_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i_reg_0), .PRE(AS), .Q(ram_empty_fb_i)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i_reg_0), .PRE(AS), .Q(ram_empty_i)); endmodule (* ORIG_REF_NAME = "reset_blk_ramfifo" *) module fifo1KB_34bit_reset_blk_ramfifo (AR, AS, out, \grstd1.grst_full.grst_f.rst_d3_reg_0 , wr_rst_busy, rst, wr_clk, rd_clk); output [0:0]AR; output [0:0]AS; output out; output \grstd1.grst_full.grst_f.rst_d3_reg_0 ; output wr_rst_busy; input rst; input wr_clk; input rd_clk; wire [0:0]AR; wire [0:0]AS; wire dest_out; wire \grstd1.grst_full.grst_f.rst_d3_i_1_n_0 ; wire \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0 ; wire \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0 ; wire \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0 ; wire rd_clk; (* DONT_TOUCH *) wire [2:0]rd_rst_reg; wire [3:0]rd_rst_wr_ext; wire rst; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d2; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d3; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d4; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d5; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d6; (* async_reg = "true" *) (* msgon = "true" *) wire rst_d7; (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2; (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1; (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2; wire sckt_rd_rst_wr; wire wr_clk; wire wr_rst_busy; wire [1:0]wr_rst_rd_ext; (* DONT_TOUCH *) wire [2:0]wr_rst_reg; assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d3; assign out = rst_d2; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d1_reg (.C(wr_clk), .CE(1'b1), .D(wr_rst_busy), .PRE(rst_wr_reg2), .Q(rst_d1)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d2_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1), .PRE(rst_wr_reg2), .Q(rst_d2)); LUT2 #( .INIT(4'hE)) \grstd1.grst_full.grst_f.rst_d3_i_1 (.I0(rst_d2), .I1(AR), .O(\grstd1.grst_full.grst_f.rst_d3_i_1_n_0 )); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d3_reg (.C(wr_clk), .CE(1'b1), .D(\grstd1.grst_full.grst_f.rst_d3_i_1_n_0 ), .PRE(rst_wr_reg2), .Q(rst_d3)); (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) FDPE #( .INIT(1'b1)) \grstd1.grst_full.grst_f.rst_d4_reg (.C(wr_clk), .CE(1'b1), .D(rst_d3), .PRE(rst_wr_reg2), .Q(rst_d4)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b1), .O(wr_rst_reg[2])); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b1), .O(wr_rst_reg[1])); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b1), .O(rst_d7)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b1), .O(wr_rst_reg[0])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b1), .O(rd_rst_reg[2])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b1), .O(rd_rst_reg[1])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b1), .O(rd_rst_reg[0])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(rst_wr_reg1)); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(rst_rd_reg1)); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b1), .O(rst_d5)); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b1), .O(rst_d6)); FDCE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(rst_wr_reg2), .D(sckt_rd_rst_wr), .Q(rd_rst_wr_ext[0])); FDCE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(rst_wr_reg2), .D(rd_rst_wr_ext[0]), .Q(rd_rst_wr_ext[1])); FDCE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(rst_wr_reg2), .D(rd_rst_wr_ext[1]), .Q(rd_rst_wr_ext[2])); FDCE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(rst_wr_reg2), .D(rd_rst_wr_ext[2]), .Q(rd_rst_wr_ext[3])); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* INV_DEF_VAL = "1'b1" *) (* RST_ACTIVE_HIGH = "1" *) (* VERSION = "0" *) (* XPM_CDC = "ASYNC_RST" *) (* XPM_MODULE = "TRUE" *) fifo1KB_34bit_xpm_cdc_async_rst \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst (.dest_arst(rst_rd_reg2), .dest_clk(rd_clk), .src_arst(rst)); LUT2 #( .INIT(4'h2)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1 (.I0(AS), .I1(wr_rst_rd_ext[1]), .O(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0 )); FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0 ), .PRE(rst_rd_reg2), .Q(AS)); LUT3 #( .INIT(8'h8A)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1 (.I0(AR), .I1(rd_rst_wr_ext[0]), .I2(rd_rst_wr_ext[1]), .O(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0 )); FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0 ), .PRE(rst_wr_reg2), .Q(AR)); LUT5 #( .INIT(32'hAAAA08AA)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1 (.I0(wr_rst_busy), .I1(rd_rst_wr_ext[1]), .I2(rd_rst_wr_ext[0]), .I3(rd_rst_wr_ext[3]), .I4(rd_rst_wr_ext[2]), .O(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0 )); FDPE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg (.C(wr_clk), .CE(1'b1), .D(\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0 ), .PRE(rst_wr_reg2), .Q(wr_rst_busy)); FDCE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] (.C(rd_clk), .CE(1'b1), .CLR(rst_rd_reg2), .D(dest_out), .Q(wr_rst_rd_ext[0])); FDCE #( .INIT(1'b0)) \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1] (.C(rd_clk), .CE(1'b1), .CLR(rst_rd_reg2), .D(wr_rst_rd_ext[0]), .Q(wr_rst_rd_ext[1])); (* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SINGLE" *) (* XPM_MODULE = "TRUE" *) fifo1KB_34bit_xpm_cdc_single \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr (.dest_clk(wr_clk), .dest_out(sckt_rd_rst_wr), .src_clk(rd_clk), .src_in(AS)); (* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SINGLE" *) (* XPM_MODULE = "TRUE" *) fifo1KB_34bit_xpm_cdc_single__2 \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd (.dest_clk(rd_clk), .dest_out(dest_out), .src_clk(wr_clk), .src_in(AR)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* INV_DEF_VAL = "1'b1" *) (* RST_ACTIVE_HIGH = "1" *) (* VERSION = "0" *) (* XPM_CDC = "ASYNC_RST" *) (* XPM_MODULE = "TRUE" *) fifo1KB_34bit_xpm_cdc_async_rst__1 \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst (.dest_arst(rst_wr_reg2), .dest_clk(wr_clk), .src_arst(rst)); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) module fifo1KB_34bit_wr_bin_cntr (Q, D, \gic0.gc0.count_d2_reg[4]_0 , \gic0.gc0.count_d1_reg[2]_0 , \gic0.gc0.count_reg[1]_0 , \gic0.gc0.count_reg[3]_0 , RD_PNTR_WR, \gdiff.diff_pntr_pad_reg[5] , E, wr_en, out, wr_clk, AR); output [4:0]Q; output [1:0]D; output [4:0]\gic0.gc0.count_d2_reg[4]_0 ; output [4:0]\gic0.gc0.count_d1_reg[2]_0 ; output [1:0]\gic0.gc0.count_reg[1]_0 ; output \gic0.gc0.count_reg[3]_0 ; input [4:0]RD_PNTR_WR; input \gdiff.diff_pntr_pad_reg[5] ; input [0:0]E; input wr_en; input out; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [1:0]D; wire [0:0]E; wire [4:0]Q; wire [4:0]RD_PNTR_WR; wire \gdiff.diff_pntr_pad[3]_i_2_n_0 ; wire \gdiff.diff_pntr_pad[5]_i_2_n_0 ; wire \gdiff.diff_pntr_pad[5]_i_3_n_0 ; wire \gdiff.diff_pntr_pad[5]_i_4_n_0 ; wire \gdiff.diff_pntr_pad_reg[5] ; wire [4:0]\gic0.gc0.count_d1_reg[2]_0 ; wire [4:0]\gic0.gc0.count_d2_reg[4]_0 ; wire [1:0]\gic0.gc0.count_reg[1]_0 ; wire \gic0.gc0.count_reg[3]_0 ; wire out; wire [4:0]plusOp__0; wire wr_clk; wire wr_en; wire [4:2]wr_pntr_plus2; (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'h9969)) \gdiff.diff_pntr_pad[1]_i_1 (.I0(Q[0]), .I1(RD_PNTR_WR[0]), .I2(wr_en), .I3(out), .O(\gic0.gc0.count_d1_reg[2]_0 [0])); LUT6 #( .INIT(64'hF75108AE08AEF751)) \gdiff.diff_pntr_pad[2]_i_1 (.I0(Q[0]), .I1(wr_en), .I2(out), .I3(RD_PNTR_WR[0]), .I4(RD_PNTR_WR[1]), .I5(Q[1]), .O(\gic0.gc0.count_d1_reg[2]_0 [1])); LUT6 #( .INIT(64'h2BD4FF0000FF2BD4)) \gdiff.diff_pntr_pad[3]_i_1 (.I0(RD_PNTR_WR[0]), .I1(E), .I2(Q[0]), .I3(\gdiff.diff_pntr_pad[3]_i_2_n_0 ), .I4(Q[1]), .I5(RD_PNTR_WR[1]), .O(\gic0.gc0.count_d1_reg[2]_0 [2])); LUT2 #( .INIT(4'h9)) \gdiff.diff_pntr_pad[3]_i_2 (.I0(Q[2]), .I1(RD_PNTR_WR[2]), .O(\gdiff.diff_pntr_pad[3]_i_2_n_0 )); LUT6 #( .INIT(64'h51AEF70808F751AE)) \gdiff.diff_pntr_pad[4]_i_1 (.I0(\gdiff.diff_pntr_pad[5]_i_3_n_0 ), .I1(Q[1]), .I2(RD_PNTR_WR[1]), .I3(\gdiff.diff_pntr_pad[5]_i_4_n_0 ), .I4(Q[2]), .I5(RD_PNTR_WR[2]), .O(\gic0.gc0.count_d1_reg[2]_0 [3])); LUT6 #( .INIT(64'h1701FF7FE8FE0080)) \gdiff.diff_pntr_pad[5]_i_1 (.I0(\gdiff.diff_pntr_pad[5]_i_2_n_0 ), .I1(\gdiff.diff_pntr_pad[5]_i_3_n_0 ), .I2(Q[2]), .I3(RD_PNTR_WR[2]), .I4(\gdiff.diff_pntr_pad[5]_i_4_n_0 ), .I5(\gdiff.diff_pntr_pad_reg[5] ), .O(\gic0.gc0.count_d1_reg[2]_0 [4])); LUT2 #( .INIT(4'h2)) \gdiff.diff_pntr_pad[5]_i_2 (.I0(Q[1]), .I1(RD_PNTR_WR[1]), .O(\gdiff.diff_pntr_pad[5]_i_2_n_0 )); LUT6 #( .INIT(64'h0000900090909990)) \gdiff.diff_pntr_pad[5]_i_3 (.I0(RD_PNTR_WR[1]), .I1(Q[1]), .I2(Q[0]), .I3(wr_en), .I4(out), .I5(RD_PNTR_WR[0]), .O(\gdiff.diff_pntr_pad[5]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gdiff.diff_pntr_pad[5]_i_4 (.I0(Q[3]), .I1(RD_PNTR_WR[3]), .O(\gdiff.diff_pntr_pad[5]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT1 #( .INIT(2'h1)) \gic0.gc0.count[0]_i_1 (.I0(\gic0.gc0.count_reg[1]_0 [0]), .O(plusOp__0[0])); LUT2 #( .INIT(4'h6)) \gic0.gc0.count[1]_i_1 (.I0(\gic0.gc0.count_reg[1]_0 [0]), .I1(\gic0.gc0.count_reg[1]_0 [1]), .O(plusOp__0[1])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'h78)) \gic0.gc0.count[2]_i_1 (.I0(\gic0.gc0.count_reg[1]_0 [0]), .I1(\gic0.gc0.count_reg[1]_0 [1]), .I2(wr_pntr_plus2[2]), .O(plusOp__0[2])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h7F80)) \gic0.gc0.count[3]_i_1 (.I0(\gic0.gc0.count_reg[1]_0 [1]), .I1(\gic0.gc0.count_reg[1]_0 [0]), .I2(wr_pntr_plus2[2]), .I3(wr_pntr_plus2[3]), .O(plusOp__0[3])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT5 #( .INIT(32'h7FFF8000)) \gic0.gc0.count[4]_i_1 (.I0(wr_pntr_plus2[2]), .I1(\gic0.gc0.count_reg[1]_0 [0]), .I2(\gic0.gc0.count_reg[1]_0 [1]), .I3(wr_pntr_plus2[3]), .I4(wr_pntr_plus2[4]), .O(plusOp__0[4])); FDPE #( .INIT(1'b1)) \gic0.gc0.count_d1_reg[0] (.C(wr_clk), .CE(E), .D(\gic0.gc0.count_reg[1]_0 [0]), .PRE(AR), .Q(Q[0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[1] (.C(wr_clk), .CE(E), .CLR(AR), .D(\gic0.gc0.count_reg[1]_0 [1]), .Q(Q[1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[2]), .Q(Q[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[3]), .Q(Q[3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(wr_pntr_plus2[4]), .Q(Q[4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[0] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[0]), .Q(\gic0.gc0.count_d2_reg[4]_0 [0])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[1] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[1]), .Q(\gic0.gc0.count_d2_reg[4]_0 [1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[2]), .Q(\gic0.gc0.count_d2_reg[4]_0 [2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[3]), .Q(\gic0.gc0.count_d2_reg[4]_0 [3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(Q[4]), .Q(\gic0.gc0.count_d2_reg[4]_0 [4])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[0] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__0[0]), .Q(\gic0.gc0.count_reg[1]_0 [0])); FDPE #( .INIT(1'b1)) \gic0.gc0.count_reg[1] (.C(wr_clk), .CE(E), .D(plusOp__0[1]), .PRE(AR), .Q(\gic0.gc0.count_reg[1]_0 [1])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[2] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__0[2]), .Q(wr_pntr_plus2[2])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[3] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__0[3]), .Q(wr_pntr_plus2[3])); FDCE #( .INIT(1'b0)) \gic0.gc0.count_reg[4] (.C(wr_clk), .CE(E), .CLR(AR), .D(plusOp__0[4]), .Q(wr_pntr_plus2[4])); LUT6 #( .INIT(64'h9009000000009009)) ram_full_i_i_2 (.I0(wr_pntr_plus2[3]), .I1(RD_PNTR_WR[3]), .I2(wr_pntr_plus2[2]), .I3(RD_PNTR_WR[2]), .I4(RD_PNTR_WR[4]), .I5(wr_pntr_plus2[4]), .O(\gic0.gc0.count_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT2 #( .INIT(4'h6)) \wr_data_count_i[0]_i_1 (.I0(\gic0.gc0.count_d2_reg[4]_0 [0]), .I1(RD_PNTR_WR[0]), .O(D[0])); LUT6 #( .INIT(64'h4F04B0FBB0FB4F04)) \wr_data_count_i[2]_i_1 (.I0(\gic0.gc0.count_d2_reg[4]_0 [0]), .I1(RD_PNTR_WR[0]), .I2(\gic0.gc0.count_d2_reg[4]_0 [1]), .I3(RD_PNTR_WR[1]), .I4(RD_PNTR_WR[2]), .I5(\gic0.gc0.count_d2_reg[4]_0 [2]), .O(D[1])); endmodule (* ORIG_REF_NAME = "wr_dc_as" *) module fifo1KB_34bit_wr_dc_as (wr_data_count, D, wr_clk, AR); output [4:0]wr_data_count; input [4:0]D; input wr_clk; input [0:0]AR; wire [0:0]AR; wire [4:0]D; wire wr_clk; wire [4:0]wr_data_count; FDCE #( .INIT(1'b0)) \wr_data_count_i_reg[0] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[0]), .Q(wr_data_count[0])); FDCE #( .INIT(1'b0)) \wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[1]), .Q(wr_data_count[1])); FDCE #( .INIT(1'b0)) \wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[2]), .Q(wr_data_count[2])); FDCE #( .INIT(1'b0)) \wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[3]), .Q(wr_data_count[3])); FDCE #( .INIT(1'b0)) \wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[4]), .Q(wr_data_count[4])); endmodule (* ORIG_REF_NAME = "wr_logic" *) module fifo1KB_34bit_wr_logic (full, prog_full, Q, \gic0.gc0.count_d2_reg[4] , E, \gic0.gc0.count_reg[1] , \gic0.gc0.count_reg[3] , wr_data_count, ram_full_fb_i_reg, wr_clk, out, RD_PNTR_WR, \gdiff.diff_pntr_pad_reg[5] , wr_en, \gpf1.prog_full_i_reg , D, AR); output full; output prog_full; output [4:0]Q; output [4:0]\gic0.gc0.count_d2_reg[4] ; output [0:0]E; output [1:0]\gic0.gc0.count_reg[1] ; output \gic0.gc0.count_reg[3] ; output [4:0]wr_data_count; input ram_full_fb_i_reg; input wr_clk; input out; input [4:0]RD_PNTR_WR; input \gdiff.diff_pntr_pad_reg[5] ; input wr_en; input \gpf1.prog_full_i_reg ; input [2:0]D; input [0:0]AR; wire [0:0]AR; wire [2:0]D; wire [0:0]E; wire [4:0]Q; wire [4:0]RD_PNTR_WR; wire full; wire \gdiff.diff_pntr_pad_reg[5] ; wire [4:0]\gic0.gc0.count_d2_reg[4] ; wire [1:0]\gic0.gc0.count_reg[1] ; wire \gic0.gc0.count_reg[3] ; wire \gpf1.prog_full_i_reg ; wire \gwas.wsts_n_1 ; wire [2:2]minusOp; wire out; wire [5:1]plusOp; wire prog_full; wire ram_full_fb_i_reg; wire wpntr_n_6; wire wr_clk; wire [4:0]wr_data_count; wire wr_en; fifo1KB_34bit_wr_pf_as \gwas.gpf.wrpf (.AR(AR), .D(plusOp), .\gpf1.prog_full_i_reg_0 (\gpf1.prog_full_i_reg ), .\gpf1.prog_full_i_reg_1 (\gwas.wsts_n_1 ), .out(out), .prog_full(prog_full), .wr_clk(wr_clk)); fifo1KB_34bit_wr_dc_as \gwas.gwdc0.wdc (.AR(AR), .D({D[2:1],minusOp,D[0],wpntr_n_6}), .wr_clk(wr_clk), .wr_data_count(wr_data_count)); fifo1KB_34bit_wr_status_flags_as \gwas.wsts (.E(E), .full(full), .out(\gwas.wsts_n_1 ), .ram_full_fb_i_reg_0(ram_full_fb_i_reg), .ram_full_fb_i_reg_1(out), .wr_clk(wr_clk), .wr_en(wr_en)); fifo1KB_34bit_wr_bin_cntr wpntr (.AR(AR), .D({minusOp,wpntr_n_6}), .E(E), .Q(Q), .RD_PNTR_WR(RD_PNTR_WR), .\gdiff.diff_pntr_pad_reg[5] (\gdiff.diff_pntr_pad_reg[5] ), .\gic0.gc0.count_d1_reg[2]_0 (plusOp), .\gic0.gc0.count_d2_reg[4]_0 (\gic0.gc0.count_d2_reg[4] ), .\gic0.gc0.count_reg[1]_0 (\gic0.gc0.count_reg[1] ), .\gic0.gc0.count_reg[3]_0 (\gic0.gc0.count_reg[3] ), .out(\gwas.wsts_n_1 ), .wr_clk(wr_clk), .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "wr_pf_as" *) module fifo1KB_34bit_wr_pf_as (prog_full, wr_clk, out, \gpf1.prog_full_i_reg_0 , \gpf1.prog_full_i_reg_1 , D, AR); output prog_full; input wr_clk; input out; input \gpf1.prog_full_i_reg_0 ; input \gpf1.prog_full_i_reg_1 ; input [4:0]D; input [0:0]AR; wire [0:0]AR; wire [4:0]D; wire [4:0]diff_pntr; wire \gpf1.prog_full_i_i_1_n_0 ; wire \gpf1.prog_full_i_reg_0 ; wire \gpf1.prog_full_i_reg_1 ; wire out; wire prog_full; wire prog_full_i; wire wr_clk; FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[1] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[0]), .Q(diff_pntr[0])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[2] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[1]), .Q(diff_pntr[1])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[3] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[2]), .Q(diff_pntr[2])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[4] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[3]), .Q(diff_pntr[3])); FDCE #( .INIT(1'b0)) \gdiff.diff_pntr_pad_reg[5] (.C(wr_clk), .CE(1'b1), .CLR(AR), .D(D[4]), .Q(diff_pntr[4])); LUT4 #( .INIT(16'hBA8A)) \gpf1.prog_full_i_i_1 (.I0(prog_full_i), .I1(\gpf1.prog_full_i_reg_0 ), .I2(\gpf1.prog_full_i_reg_1 ), .I3(prog_full), .O(\gpf1.prog_full_i_i_1_n_0 )); LUT6 #( .INIT(64'h00000000AA800000)) \gpf1.prog_full_i_i_2 (.I0(diff_pntr[4]), .I1(diff_pntr[1]), .I2(diff_pntr[0]), .I3(diff_pntr[2]), .I4(diff_pntr[3]), .I5(\gpf1.prog_full_i_reg_0 ), .O(prog_full_i)); FDPE #( .INIT(1'b1)) \gpf1.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gpf1.prog_full_i_i_1_n_0 ), .PRE(out), .Q(prog_full)); endmodule (* ORIG_REF_NAME = "wr_status_flags_as" *) module fifo1KB_34bit_wr_status_flags_as (full, out, E, ram_full_fb_i_reg_0, wr_clk, ram_full_fb_i_reg_1, wr_en); output full; output out; output [0:0]E; input ram_full_fb_i_reg_0; input wr_clk; input ram_full_fb_i_reg_1; input wr_en; wire [0:0]E; (* DONT_TOUCH *) wire ram_full_fb_i; wire ram_full_fb_i_reg_0; wire ram_full_fb_i_reg_1; (* DONT_TOUCH *) wire ram_full_i; wire wr_clk; wire wr_en; assign full = ram_full_i; assign out = ram_full_fb_i; LUT2 #( .INIT(4'h2)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2 (.I0(wr_en), .I1(ram_full_fb_i), .O(E)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_fb_i_reg (.C(wr_clk), .CE(1'b1), .D(ram_full_fb_i_reg_0), .PRE(ram_full_fb_i_reg_1), .Q(ram_full_fb_i)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(ram_full_fb_i_reg_0), .PRE(ram_full_fb_i_reg_1), .Q(ram_full_i)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif