-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -- Date : Mon May 4 23:36:15 2020 -- Host : hog-efex2.cern.ch running 64-bit CentOS Linux release 7.7.1908 (Core) -- Command : write_vhdl -force -mode funcsim -- /home/gitlab-runner/builds/Ap-NaJLy/0/atlas-l1calo-efex/RODFirmware/IP/fullmode/fifo1KB_34bit/fifo1KB_34bit_sim_netlist.vhdl -- Design : fifo1KB_34bit -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7vx550tffg1927-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_xpm_cdc_async_rst is port ( src_arst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_arst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of fifo1KB_34bit_xpm_cdc_async_rst : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of fifo1KB_34bit_xpm_cdc_async_rst : entity is 2; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of fifo1KB_34bit_xpm_cdc_async_rst : entity is 0; attribute INV_DEF_VAL : string; attribute INV_DEF_VAL of fifo1KB_34bit_xpm_cdc_async_rst : entity is "1'b1"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_xpm_cdc_async_rst : entity is "xpm_cdc_async_rst"; attribute RST_ACTIVE_HIGH : integer; attribute RST_ACTIVE_HIGH of fifo1KB_34bit_xpm_cdc_async_rst : entity is 1; attribute VERSION : integer; attribute VERSION of fifo1KB_34bit_xpm_cdc_async_rst : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of fifo1KB_34bit_xpm_cdc_async_rst : entity is "TRUE"; attribute xpm_cdc : string; attribute xpm_cdc of fifo1KB_34bit_xpm_cdc_async_rst : entity is "ASYNC_RST"; end fifo1KB_34bit_xpm_cdc_async_rst; architecture STRUCTURE of fifo1KB_34bit_xpm_cdc_async_rst is signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of arststages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of arststages_ff : signal is "true"; attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \arststages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST"; attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \arststages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST"; begin dest_arst <= arststages_ff(1); \arststages_ff_reg[0]\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => '0', PRE => src_arst, Q => arststages_ff(0) ); \arststages_ff_reg[1]\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => arststages_ff(0), PRE => src_arst, Q => arststages_ff(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \fifo1KB_34bit_xpm_cdc_async_rst__1\ is port ( src_arst : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_arst : out STD_LOGIC ); attribute DEF_VAL : string; attribute DEF_VAL of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is 2; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is 0; attribute INV_DEF_VAL : string; attribute INV_DEF_VAL of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is "1'b1"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is "xpm_cdc_async_rst"; attribute RST_ACTIVE_HIGH : integer; attribute RST_ACTIVE_HIGH of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is 1; attribute VERSION : integer; attribute VERSION of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is "TRUE"; attribute xpm_cdc : string; attribute xpm_cdc of \fifo1KB_34bit_xpm_cdc_async_rst__1\ : entity is "ASYNC_RST"; end \fifo1KB_34bit_xpm_cdc_async_rst__1\; architecture STRUCTURE of \fifo1KB_34bit_xpm_cdc_async_rst__1\ is signal arststages_ff : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of arststages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of arststages_ff : signal is "true"; attribute xpm_cdc of arststages_ff : signal is "ASYNC_RST"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \arststages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \arststages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \arststages_ff_reg[0]\ : label is "ASYNC_RST"; attribute ASYNC_REG_boolean of \arststages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \arststages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \arststages_ff_reg[1]\ : label is "ASYNC_RST"; begin dest_arst <= arststages_ff(1); \arststages_ff_reg[0]\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => '0', PRE => src_arst, Q => arststages_ff(0) ); \arststages_ff_reg[1]\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => dest_clk, CE => '1', D => arststages_ff(0), PRE => src_arst, Q => arststages_ff(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_xpm_cdc_gray is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 4 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 4 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of fifo1KB_34bit_xpm_cdc_gray : entity is 2; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of fifo1KB_34bit_xpm_cdc_gray : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_xpm_cdc_gray : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of fifo1KB_34bit_xpm_cdc_gray : entity is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of fifo1KB_34bit_xpm_cdc_gray : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of fifo1KB_34bit_xpm_cdc_gray : entity is 0; attribute VERSION : integer; attribute VERSION of fifo1KB_34bit_xpm_cdc_gray : entity is 0; attribute WIDTH : integer; attribute WIDTH of fifo1KB_34bit_xpm_cdc_gray : entity is 5; attribute XPM_MODULE : string; attribute XPM_MODULE of fifo1KB_34bit_xpm_cdc_gray : entity is "TRUE"; attribute xpm_cdc : string; attribute xpm_cdc of fifo1KB_34bit_xpm_cdc_gray : entity is "GRAY"; end fifo1KB_34bit_xpm_cdc_gray; architecture STRUCTURE of fifo1KB_34bit_xpm_cdc_gray is signal async_path : STD_LOGIC_VECTOR ( 4 downto 0 ); signal binval : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal gray_enc : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair3"; begin \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_out_bin_ff[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[1]\(0), I1 => \dest_graysync_ff[1]\(2), I2 => \dest_graysync_ff[1]\(4), I3 => \dest_graysync_ff[1]\(3), I4 => \dest_graysync_ff[1]\(1), O => binval(0) ); \dest_out_bin_ff[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[1]\(1), I1 => \dest_graysync_ff[1]\(3), I2 => \dest_graysync_ff[1]\(4), I3 => \dest_graysync_ff[1]\(2), O => binval(1) ); \dest_out_bin_ff[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[1]\(2), I1 => \dest_graysync_ff[1]\(4), I2 => \dest_graysync_ff[1]\(3), O => binval(2) ); \dest_out_bin_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[1]\(3), I1 => \dest_graysync_ff[1]\(4), O => binval(3) ); \dest_out_bin_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(0), Q => dest_out_bin(0), R => '0' ); \dest_out_bin_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(1), Q => dest_out_bin(1), R => '0' ); \dest_out_bin_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(2), Q => dest_out_bin(2), R => '0' ); \dest_out_bin_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(3), Q => dest_out_bin(3), R => '0' ); \dest_out_bin_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => dest_out_bin(4), R => '0' ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(4), Q => async_path(4), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \fifo1KB_34bit_xpm_cdc_gray__2\ is port ( src_clk : in STD_LOGIC; src_in_bin : in STD_LOGIC_VECTOR ( 4 downto 0 ); dest_clk : in STD_LOGIC; dest_out_bin : out STD_LOGIC_VECTOR ( 4 downto 0 ) ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is 2; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is "xpm_cdc_gray"; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is 0; attribute VERSION : integer; attribute VERSION of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is 0; attribute WIDTH : integer; attribute WIDTH of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is 5; attribute XPM_MODULE : string; attribute XPM_MODULE of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is "TRUE"; attribute xpm_cdc : string; attribute xpm_cdc of \fifo1KB_34bit_xpm_cdc_gray__2\ : entity is "GRAY"; end \fifo1KB_34bit_xpm_cdc_gray__2\; architecture STRUCTURE of \fifo1KB_34bit_xpm_cdc_gray__2\ is signal async_path : STD_LOGIC_VECTOR ( 4 downto 0 ); signal binval : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true"; attribute async_reg : string; attribute async_reg of \dest_graysync_ff[0]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY"; signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true"; attribute async_reg of \dest_graysync_ff[1]\ : signal is "true"; attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY"; signal gray_enc : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY"; attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true; attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true"; attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair1"; begin \dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(0), Q => \dest_graysync_ff[0]\(0), R => '0' ); \dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(1), Q => \dest_graysync_ff[0]\(1), R => '0' ); \dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(2), Q => \dest_graysync_ff[0]\(2), R => '0' ); \dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(3), Q => \dest_graysync_ff[0]\(3), R => '0' ); \dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => async_path(4), Q => \dest_graysync_ff[0]\(4), R => '0' ); \dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(0), Q => \dest_graysync_ff[1]\(0), R => '0' ); \dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(1), Q => \dest_graysync_ff[1]\(1), R => '0' ); \dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(2), Q => \dest_graysync_ff[1]\(2), R => '0' ); \dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(3), Q => \dest_graysync_ff[1]\(3), R => '0' ); \dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[0]\(4), Q => \dest_graysync_ff[1]\(4), R => '0' ); \dest_out_bin_ff[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \dest_graysync_ff[1]\(0), I1 => \dest_graysync_ff[1]\(2), I2 => \dest_graysync_ff[1]\(4), I3 => \dest_graysync_ff[1]\(3), I4 => \dest_graysync_ff[1]\(1), O => binval(0) ); \dest_out_bin_ff[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \dest_graysync_ff[1]\(1), I1 => \dest_graysync_ff[1]\(3), I2 => \dest_graysync_ff[1]\(4), I3 => \dest_graysync_ff[1]\(2), O => binval(1) ); \dest_out_bin_ff[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \dest_graysync_ff[1]\(2), I1 => \dest_graysync_ff[1]\(4), I2 => \dest_graysync_ff[1]\(3), O => binval(2) ); \dest_out_bin_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \dest_graysync_ff[1]\(3), I1 => \dest_graysync_ff[1]\(4), O => binval(3) ); \dest_out_bin_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(0), Q => dest_out_bin(0), R => '0' ); \dest_out_bin_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(1), Q => dest_out_bin(1), R => '0' ); \dest_out_bin_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(2), Q => dest_out_bin(2), R => '0' ); \dest_out_bin_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => binval(3), Q => dest_out_bin(3), R => '0' ); \dest_out_bin_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => \dest_graysync_ff[1]\(4), Q => dest_out_bin(4), R => '0' ); \src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(1), I1 => src_in_bin(0), O => gray_enc(0) ); \src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(2), I1 => src_in_bin(1), O => gray_enc(1) ); \src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(3), I1 => src_in_bin(2), O => gray_enc(2) ); \src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => src_in_bin(4), I1 => src_in_bin(3), O => gray_enc(3) ); \src_gray_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(0), Q => async_path(0), R => '0' ); \src_gray_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(1), Q => async_path(1), R => '0' ); \src_gray_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(2), Q => async_path(2), R => '0' ); \src_gray_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => gray_enc(3), Q => async_path(3), R => '0' ); \src_gray_ff_reg[4]\: unisim.vcomponents.FDRE port map ( C => src_clk, CE => '1', D => src_in_bin(4), Q => async_path(4), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_xpm_cdc_single is port ( src_clk : in STD_LOGIC; src_in : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_out : out STD_LOGIC ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of fifo1KB_34bit_xpm_cdc_single : entity is 4; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of fifo1KB_34bit_xpm_cdc_single : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_xpm_cdc_single : entity is "xpm_cdc_single"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of fifo1KB_34bit_xpm_cdc_single : entity is 0; attribute SRC_INPUT_REG : integer; attribute SRC_INPUT_REG of fifo1KB_34bit_xpm_cdc_single : entity is 0; attribute VERSION : integer; attribute VERSION of fifo1KB_34bit_xpm_cdc_single : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of fifo1KB_34bit_xpm_cdc_single : entity is "TRUE"; attribute xpm_cdc : string; attribute xpm_cdc of fifo1KB_34bit_xpm_cdc_single : entity is "SINGLE"; end fifo1KB_34bit_xpm_cdc_single; architecture STRUCTURE of fifo1KB_34bit_xpm_cdc_single is signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SINGLE"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[3]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE"; begin dest_out <= syncstages_ff(3); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => src_in, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); \syncstages_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => syncstages_ff(2), Q => syncstages_ff(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \fifo1KB_34bit_xpm_cdc_single__2\ is port ( src_clk : in STD_LOGIC; src_in : in STD_LOGIC; dest_clk : in STD_LOGIC; dest_out : out STD_LOGIC ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is 4; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is "xpm_cdc_single"; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is 0; attribute SRC_INPUT_REG : integer; attribute SRC_INPUT_REG of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is 0; attribute VERSION : integer; attribute VERSION of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is 0; attribute XPM_MODULE : string; attribute XPM_MODULE of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is "TRUE"; attribute xpm_cdc : string; attribute xpm_cdc of \fifo1KB_34bit_xpm_cdc_single__2\ : entity is "SINGLE"; end \fifo1KB_34bit_xpm_cdc_single__2\; architecture STRUCTURE of \fifo1KB_34bit_xpm_cdc_single__2\ is signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of syncstages_ff : signal is "true"; attribute async_reg : string; attribute async_reg of syncstages_ff : signal is "true"; attribute xpm_cdc of syncstages_ff : signal is "SINGLE"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \syncstages_ff_reg[0]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[1]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[2]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE"; attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true; attribute KEEP of \syncstages_ff_reg[3]\ : label is "true"; attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE"; begin dest_out <= syncstages_ff(3); \syncstages_ff_reg[0]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => src_in, Q => syncstages_ff(0), R => '0' ); \syncstages_ff_reg[1]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => syncstages_ff(0), Q => syncstages_ff(1), R => '0' ); \syncstages_ff_reg[2]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => syncstages_ff(1), Q => syncstages_ff(2), R => '0' ); \syncstages_ff_reg[3]\: unisim.vcomponents.FDRE port map ( C => dest_clk, CE => '1', D => syncstages_ff(2), Q => syncstages_ff(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_blk_mem_gen_prim_wrapper is port ( dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; tmp_ram_rd_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); AS : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); din : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; end fifo1KB_34bit_blk_mem_gen_prim_wrapper; architecture STRUCTURE of fifo1KB_34bit_blk_mem_gen_prim_wrapper is signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "SDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 36, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 36 ) port map ( ADDRARDADDR(13 downto 10) => B"0000", ADDRARDADDR(9 downto 5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0), ADDRARDADDR(4 downto 0) => B"00000", ADDRBWRADDR(13 downto 10) => B"0000", ADDRBWRADDR(9 downto 5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1\(4 downto 0), ADDRBWRADDR(4 downto 0) => B"00000", CLKARDCLK => rd_clk, CLKBWRCLK => wr_clk, DIADI(15 downto 8) => din(16 downto 9), DIADI(7 downto 0) => din(7 downto 0), DIBDI(15 downto 8) => din(33 downto 26), DIBDI(7 downto 0) => din(24 downto 17), DIPADIP(1) => '0', DIPADIP(0) => din(8), DIPBDIP(1) => '0', DIPBDIP(0) => din(25), DOADO(15 downto 8) => dout(16 downto 9), DOADO(7 downto 0) => dout(7 downto 0), DOBDO(15 downto 8) => dout(33 downto 26), DOBDO(7 downto 0) => dout(24 downto 17), DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\, DOPADOP(0) => dout(8), DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\, DOPBDOP(0) => dout(25), ENARDEN => tmp_ram_rd_en, ENBWREN => E(0), REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => AS(0), RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1 downto 0) => B"00", WEBWE(3) => E(0), WEBWE(2) => E(0), WEBWE(1) => E(0), WEBWE(0) => E(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_rd_bin_cntr is port ( rd_en_0 : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gc0.count_d1_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); ram_empty_i_reg : in STD_LOGIC; rd_en : in STD_LOGIC; \out\ : in STD_LOGIC; ram_empty_i_reg_0 : in STD_LOGIC; WR_PNTR_RD : in STD_LOGIC_VECTOR ( 1 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC; AS : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_rd_bin_cntr : entity is "rd_bin_cntr"; end fifo1KB_34bit_rd_bin_cntr; architecture STRUCTURE of fifo1KB_34bit_rd_bin_cntr is signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^gc0.count_d1_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal ram_empty_i_i_3_n_0 : STD_LOGIC; signal ram_empty_i_i_4_n_0 : STD_LOGIC; signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of ram_empty_i_i_4 : label is "soft_lutpair6"; begin Q(2 downto 0) <= \^q\(2 downto 0); \gc0.count_d1_reg[4]_0\(4 downto 0) <= \^gc0.count_d1_reg[4]_0\(4 downto 0); \gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rd_pntr_plus1(0), O => \plusOp__1\(0) ); \gc0.count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rd_pntr_plus1(0), I1 => rd_pntr_plus1(1), O => \plusOp__1\(1) ); \gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => rd_pntr_plus1(0), I1 => rd_pntr_plus1(1), I2 => \^q\(0), O => \plusOp__1\(2) ); \gc0.count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => rd_pntr_plus1(1), I1 => rd_pntr_plus1(0), I2 => \^q\(0), I3 => \^q\(1), O => \plusOp__1\(3) ); \gc0.count[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(0), I1 => rd_pntr_plus1(0), I2 => rd_pntr_plus1(1), I3 => \^q\(1), I4 => \^q\(2), O => \plusOp__1\(4) ); \gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => rd_pntr_plus1(0), Q => \^gc0.count_d1_reg[4]_0\(0) ); \gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => rd_pntr_plus1(1), Q => \^gc0.count_d1_reg[4]_0\(1) ); \gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => \^q\(0), Q => \^gc0.count_d1_reg[4]_0\(2) ); \gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => \^q\(1), Q => \^gc0.count_d1_reg[4]_0\(3) ); \gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => \^q\(2), Q => \^gc0.count_d1_reg[4]_0\(4) ); \gc0.count_reg[0]\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rd_clk, CE => E(0), D => \plusOp__1\(0), PRE => AS(0), Q => rd_pntr_plus1(0) ); \gc0.count_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => \plusOp__1\(1), Q => rd_pntr_plus1(1) ); \gc0.count_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => \plusOp__1\(2), Q => \^q\(0) ); \gc0.count_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => \plusOp__1\(3), Q => \^q\(1) ); \gc0.count_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => E(0), CLR => AS(0), D => \plusOp__1\(4), Q => \^q\(2) ); ram_empty_i_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"88F8888888888888" ) port map ( I0 => ram_empty_i_reg, I1 => ram_empty_i_i_3_n_0, I2 => rd_en, I3 => \out\, I4 => ram_empty_i_i_4_n_0, I5 => ram_empty_i_reg_0, O => rd_en_0 ); ram_empty_i_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^gc0.count_d1_reg[4]_0\(0), I1 => WR_PNTR_RD(0), I2 => \^gc0.count_d1_reg[4]_0\(1), I3 => WR_PNTR_RD(1), O => ram_empty_i_i_3_n_0 ); ram_empty_i_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => rd_pntr_plus1(0), I1 => WR_PNTR_RD(0), I2 => rd_pntr_plus1(1), I3 => WR_PNTR_RD(1), O => ram_empty_i_i_4_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_rd_status_flags_as is port ( empty : out STD_LOGIC; \out\ : out STD_LOGIC; tmp_ram_rd_en : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); ram_empty_i_reg_0 : in STD_LOGIC; rd_clk : in STD_LOGIC; AS : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_rd_status_flags_as : entity is "rd_status_flags_as"; end fifo1KB_34bit_rd_status_flags_as; architecture STRUCTURE of fifo1KB_34bit_rd_status_flags_as is signal ram_empty_fb_i : STD_LOGIC; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; signal ram_empty_i : STD_LOGIC; attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of ram_empty_fb_i_reg : label is "yes"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; attribute KEEP of ram_empty_i_reg : label is "yes"; attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; begin empty <= ram_empty_i; \out\ <= ram_empty_fb_i; \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"F4" ) port map ( I0 => ram_empty_fb_i, I1 => rd_en, I2 => AS(0), O => tmp_ram_rd_en ); \gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => rd_en, I1 => ram_empty_fb_i, O => E(0) ); ram_empty_fb_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => ram_empty_i_reg_0, PRE => AS(0), Q => ram_empty_fb_i ); ram_empty_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => rd_clk, CE => '1', D => ram_empty_i_reg_0, PRE => AS(0), Q => ram_empty_i ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_wr_bin_cntr is port ( Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \gic0.gc0.count_d2_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); \gic0.gc0.count_d1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); \gic0.gc0.count_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \gic0.gc0.count_reg[3]_0\ : out STD_LOGIC; RD_PNTR_WR : in STD_LOGIC_VECTOR ( 4 downto 0 ); \gdiff.diff_pntr_pad_reg[5]\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_en : in STD_LOGIC; \out\ : in STD_LOGIC; wr_clk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_wr_bin_cntr : entity is "wr_bin_cntr"; end fifo1KB_34bit_wr_bin_cntr; architecture STRUCTURE of fifo1KB_34bit_wr_bin_cntr is signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \gdiff.diff_pntr_pad[3]_i_2_n_0\ : STD_LOGIC; signal \gdiff.diff_pntr_pad[5]_i_2_n_0\ : STD_LOGIC; signal \gdiff.diff_pntr_pad[5]_i_3_n_0\ : STD_LOGIC; signal \gdiff.diff_pntr_pad[5]_i_4_n_0\ : STD_LOGIC; signal \^gic0.gc0.count_d2_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \^gic0.gc0.count_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 4 downto 2 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gdiff.diff_pntr_pad[1]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \wr_data_count_i[0]_i_1\ : label is "soft_lutpair8"; begin Q(4 downto 0) <= \^q\(4 downto 0); \gic0.gc0.count_d2_reg[4]_0\(4 downto 0) <= \^gic0.gc0.count_d2_reg[4]_0\(4 downto 0); \gic0.gc0.count_reg[1]_0\(1 downto 0) <= \^gic0.gc0.count_reg[1]_0\(1 downto 0); \gdiff.diff_pntr_pad[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9969" ) port map ( I0 => \^q\(0), I1 => RD_PNTR_WR(0), I2 => wr_en, I3 => \out\, O => \gic0.gc0.count_d1_reg[2]_0\(0) ); \gdiff.diff_pntr_pad[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F75108AE08AEF751" ) port map ( I0 => \^q\(0), I1 => wr_en, I2 => \out\, I3 => RD_PNTR_WR(0), I4 => RD_PNTR_WR(1), I5 => \^q\(1), O => \gic0.gc0.count_d1_reg[2]_0\(1) ); \gdiff.diff_pntr_pad[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"2BD4FF0000FF2BD4" ) port map ( I0 => RD_PNTR_WR(0), I1 => E(0), I2 => \^q\(0), I3 => \gdiff.diff_pntr_pad[3]_i_2_n_0\, I4 => \^q\(1), I5 => RD_PNTR_WR(1), O => \gic0.gc0.count_d1_reg[2]_0\(2) ); \gdiff.diff_pntr_pad[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => RD_PNTR_WR(2), O => \gdiff.diff_pntr_pad[3]_i_2_n_0\ ); \gdiff.diff_pntr_pad[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"51AEF70808F751AE" ) port map ( I0 => \gdiff.diff_pntr_pad[5]_i_3_n_0\, I1 => \^q\(1), I2 => RD_PNTR_WR(1), I3 => \gdiff.diff_pntr_pad[5]_i_4_n_0\, I4 => \^q\(2), I5 => RD_PNTR_WR(2), O => \gic0.gc0.count_d1_reg[2]_0\(3) ); \gdiff.diff_pntr_pad[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"1701FF7FE8FE0080" ) port map ( I0 => \gdiff.diff_pntr_pad[5]_i_2_n_0\, I1 => \gdiff.diff_pntr_pad[5]_i_3_n_0\, I2 => \^q\(2), I3 => RD_PNTR_WR(2), I4 => \gdiff.diff_pntr_pad[5]_i_4_n_0\, I5 => \gdiff.diff_pntr_pad_reg[5]\, O => \gic0.gc0.count_d1_reg[2]_0\(4) ); \gdiff.diff_pntr_pad[5]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => RD_PNTR_WR(1), O => \gdiff.diff_pntr_pad[5]_i_2_n_0\ ); \gdiff.diff_pntr_pad[5]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000900090909990" ) port map ( I0 => RD_PNTR_WR(1), I1 => \^q\(1), I2 => \^q\(0), I3 => wr_en, I4 => \out\, I5 => RD_PNTR_WR(0), O => \gdiff.diff_pntr_pad[5]_i_3_n_0\ ); \gdiff.diff_pntr_pad[5]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => RD_PNTR_WR(3), O => \gdiff.diff_pntr_pad[5]_i_4_n_0\ ); \gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gic0.gc0.count_reg[1]_0\(0), O => \plusOp__0\(0) ); \gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^gic0.gc0.count_reg[1]_0\(0), I1 => \^gic0.gc0.count_reg[1]_0\(1), O => \plusOp__0\(1) ); \gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^gic0.gc0.count_reg[1]_0\(0), I1 => \^gic0.gc0.count_reg[1]_0\(1), I2 => wr_pntr_plus2(2), O => \plusOp__0\(2) ); \gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^gic0.gc0.count_reg[1]_0\(1), I1 => \^gic0.gc0.count_reg[1]_0\(0), I2 => wr_pntr_plus2(2), I3 => wr_pntr_plus2(3), O => \plusOp__0\(3) ); \gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => wr_pntr_plus2(2), I1 => \^gic0.gc0.count_reg[1]_0\(0), I2 => \^gic0.gc0.count_reg[1]_0\(1), I3 => wr_pntr_plus2(3), I4 => wr_pntr_plus2(4), O => \plusOp__0\(4) ); \gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => E(0), D => \^gic0.gc0.count_reg[1]_0\(0), PRE => AR(0), Q => \^q\(0) ); \gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \^gic0.gc0.count_reg[1]_0\(1), Q => \^q\(1) ); \gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => wr_pntr_plus2(2), Q => \^q\(2) ); \gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => wr_pntr_plus2(3), Q => \^q\(3) ); \gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => wr_pntr_plus2(4), Q => \^q\(4) ); \gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \^q\(0), Q => \^gic0.gc0.count_d2_reg[4]_0\(0) ); \gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \^q\(1), Q => \^gic0.gc0.count_d2_reg[4]_0\(1) ); \gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \^q\(2), Q => \^gic0.gc0.count_d2_reg[4]_0\(2) ); \gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \^q\(3), Q => \^gic0.gc0.count_d2_reg[4]_0\(3) ); \gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \^q\(4), Q => \^gic0.gc0.count_d2_reg[4]_0\(4) ); \gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \plusOp__0\(0), Q => \^gic0.gc0.count_reg[1]_0\(0) ); \gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => E(0), D => \plusOp__0\(1), PRE => AR(0), Q => \^gic0.gc0.count_reg[1]_0\(1) ); \gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \plusOp__0\(2), Q => wr_pntr_plus2(2) ); \gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \plusOp__0\(3), Q => wr_pntr_plus2(3) ); \gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => E(0), CLR => AR(0), D => \plusOp__0\(4), Q => wr_pntr_plus2(4) ); ram_full_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => wr_pntr_plus2(3), I1 => RD_PNTR_WR(3), I2 => wr_pntr_plus2(2), I3 => RD_PNTR_WR(2), I4 => RD_PNTR_WR(4), I5 => wr_pntr_plus2(4), O => \gic0.gc0.count_reg[3]_0\ ); \wr_data_count_i[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^gic0.gc0.count_d2_reg[4]_0\(0), I1 => RD_PNTR_WR(0), O => D(0) ); \wr_data_count_i[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"4F04B0FBB0FB4F04" ) port map ( I0 => \^gic0.gc0.count_d2_reg[4]_0\(0), I1 => RD_PNTR_WR(0), I2 => \^gic0.gc0.count_d2_reg[4]_0\(1), I3 => RD_PNTR_WR(1), I4 => RD_PNTR_WR(2), I5 => \^gic0.gc0.count_d2_reg[4]_0\(2), O => D(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_wr_dc_as is port ( wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); D : in STD_LOGIC_VECTOR ( 4 downto 0 ); wr_clk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_wr_dc_as : entity is "wr_dc_as"; end fifo1KB_34bit_wr_dc_as; architecture STRUCTURE of fifo1KB_34bit_wr_dc_as is begin \wr_data_count_i_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(0), Q => wr_data_count(0) ); \wr_data_count_i_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(1), Q => wr_data_count(1) ); \wr_data_count_i_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(2), Q => wr_data_count(2) ); \wr_data_count_i_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(3), Q => wr_data_count(3) ); \wr_data_count_i_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(4), Q => wr_data_count(4) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_wr_pf_as is port ( prog_full : out STD_LOGIC; wr_clk : in STD_LOGIC; \out\ : in STD_LOGIC; \gpf1.prog_full_i_reg_0\ : in STD_LOGIC; \gpf1.prog_full_i_reg_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 4 downto 0 ); AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_wr_pf_as : entity is "wr_pf_as"; end fifo1KB_34bit_wr_pf_as; architecture STRUCTURE of fifo1KB_34bit_wr_pf_as is signal diff_pntr : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC; signal \^prog_full\ : STD_LOGIC; signal prog_full_i : STD_LOGIC; begin prog_full <= \^prog_full\; \gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(0), Q => diff_pntr(0) ); \gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(1), Q => diff_pntr(1) ); \gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(2), Q => diff_pntr(2) ); \gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(3), Q => diff_pntr(3) ); \gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => AR(0), D => D(4), Q => diff_pntr(4) ); \gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BA8A" ) port map ( I0 => prog_full_i, I1 => \gpf1.prog_full_i_reg_0\, I2 => \gpf1.prog_full_i_reg_1\, I3 => \^prog_full\, O => \gpf1.prog_full_i_i_1_n_0\ ); \gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AA800000" ) port map ( I0 => diff_pntr(4), I1 => diff_pntr(1), I2 => diff_pntr(0), I3 => diff_pntr(2), I4 => diff_pntr(3), I5 => \gpf1.prog_full_i_reg_0\, O => prog_full_i ); \gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \gpf1.prog_full_i_i_1_n_0\, PRE => \out\, Q => \^prog_full\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_wr_status_flags_as is port ( full : out STD_LOGIC; \out\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); ram_full_fb_i_reg_0 : in STD_LOGIC; wr_clk : in STD_LOGIC; ram_full_fb_i_reg_1 : in STD_LOGIC; wr_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_wr_status_flags_as : entity is "wr_status_flags_as"; end fifo1KB_34bit_wr_status_flags_as; architecture STRUCTURE of fifo1KB_34bit_wr_status_flags_as is signal ram_full_fb_i : STD_LOGIC; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; signal ram_full_i : STD_LOGIC; attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of ram_full_fb_i_reg : label is "yes"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; attribute KEEP of ram_full_i_reg : label is "yes"; attribute equivalent_register_removal of ram_full_i_reg : label is "no"; begin full <= ram_full_i; \out\ <= ram_full_fb_i; \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => wr_en, I1 => ram_full_fb_i, O => E(0) ); ram_full_fb_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => ram_full_fb_i_reg_0, PRE => ram_full_fb_i_reg_1, Q => ram_full_fb_i ); ram_full_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => ram_full_fb_i_reg_0, PRE => ram_full_fb_i_reg_1, Q => ram_full_i ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_blk_mem_gen_prim_width is port ( dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; tmp_ram_rd_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); AS : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); din : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end fifo1KB_34bit_blk_mem_gen_prim_width; architecture STRUCTURE of fifo1KB_34bit_blk_mem_gen_prim_width is begin \prim_noinit.ram\: entity work.fifo1KB_34bit_blk_mem_gen_prim_wrapper port map ( AS(0) => AS(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_1\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0), E(0) => E(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), rd_clk => rd_clk, tmp_ram_rd_en => tmp_ram_rd_en, wr_clk => wr_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_clk_x_pntrs is port ( \grstd1.grst_full.grst_f.rst_d3_reg\ : out STD_LOGIC; RD_PNTR_WR : out STD_LOGIC_VECTOR ( 4 downto 0 ); \dest_out_bin_ff_reg[3]\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 2 downto 0 ); \dest_out_bin_ff_reg[3]_0\ : out STD_LOGIC; WR_PNTR_RD : out STD_LOGIC_VECTOR ( 1 downto 0 ); \dest_out_bin_ff_reg[3]_1\ : out STD_LOGIC; ram_full_fb_i_reg : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); ram_full_fb_i_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); \src_gray_ff_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \src_gray_ff_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); ram_empty_i_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_clk_x_pntrs : entity is "clk_x_pntrs"; end fifo1KB_34bit_clk_x_pntrs; architecture STRUCTURE of fifo1KB_34bit_clk_x_pntrs is signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal ram_full_i_i_3_n_0 : STD_LOGIC; signal ram_full_i_i_4_n_0 : STD_LOGIC; signal ram_full_i_i_5_n_0 : STD_LOGIC; signal \wr_data_count_i[4]_i_2_n_0\ : STD_LOGIC; signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 4 downto 2 ); attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of rd_pntr_cdc_inst : label is 2; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of rd_pntr_cdc_inst : label is 0; attribute REG_OUTPUT : integer; attribute REG_OUTPUT of rd_pntr_cdc_inst : label is 1; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of rd_pntr_cdc_inst : label is 0; attribute SIM_LOSSLESS_GRAY_CHK : integer; attribute SIM_LOSSLESS_GRAY_CHK of rd_pntr_cdc_inst : label is 0; attribute VERSION : integer; attribute VERSION of rd_pntr_cdc_inst : label is 0; attribute WIDTH : integer; attribute WIDTH of rd_pntr_cdc_inst : label is 5; attribute XPM_CDC : string; attribute XPM_CDC of rd_pntr_cdc_inst : label is "GRAY"; attribute XPM_MODULE : string; attribute XPM_MODULE of rd_pntr_cdc_inst : label is "TRUE"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \wr_data_count_i[3]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \wr_data_count_i[4]_i_1\ : label is "soft_lutpair4"; attribute DEST_SYNC_FF of wr_pntr_cdc_inst : label is 2; attribute INIT_SYNC_FF of wr_pntr_cdc_inst : label is 0; attribute REG_OUTPUT of wr_pntr_cdc_inst : label is 1; attribute SIM_ASSERT_CHK of wr_pntr_cdc_inst : label is 0; attribute SIM_LOSSLESS_GRAY_CHK of wr_pntr_cdc_inst : label is 0; attribute VERSION of wr_pntr_cdc_inst : label is 0; attribute WIDTH of wr_pntr_cdc_inst : label is 5; attribute XPM_CDC of wr_pntr_cdc_inst : label is "GRAY"; attribute XPM_MODULE of wr_pntr_cdc_inst : label is "TRUE"; begin RD_PNTR_WR(4 downto 0) <= \^rd_pntr_wr\(4 downto 0); \gdiff.diff_pntr_pad[5]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"B44B" ) port map ( I0 => \^rd_pntr_wr\(3), I1 => Q(3), I2 => \^rd_pntr_wr\(4), I3 => Q(4), O => \dest_out_bin_ff_reg[3]\ ); ram_empty_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^wr_pntr_rd\(3), I1 => \src_gray_ff_reg[4]_0\(3), I2 => \^wr_pntr_rd\(2), I3 => \src_gray_ff_reg[4]_0\(2), I4 => \src_gray_ff_reg[4]_0\(4), I5 => \^wr_pntr_rd\(4), O => \dest_out_bin_ff_reg[3]_0\ ); ram_empty_i_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^wr_pntr_rd\(3), I1 => ram_empty_i_reg(1), I2 => \^wr_pntr_rd\(2), I3 => ram_empty_i_reg(0), I4 => ram_empty_i_reg(2), I5 => \^wr_pntr_rd\(4), O => \dest_out_bin_ff_reg[3]_1\ ); ram_full_i_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FF808080" ) port map ( I0 => ram_full_fb_i_reg, I1 => ram_full_i_i_3_n_0, I2 => E(0), I3 => ram_full_i_i_4_n_0, I4 => ram_full_i_i_5_n_0, I5 => \out\, O => \grstd1.grst_full.grst_f.rst_d3_reg\ ); ram_full_i_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^rd_pntr_wr\(0), I1 => ram_full_fb_i_reg_0(0), I2 => \^rd_pntr_wr\(1), I3 => ram_full_fb_i_reg_0(1), O => ram_full_i_i_3_n_0 ); ram_full_i_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^rd_pntr_wr\(0), I1 => Q(0), I2 => Q(1), I3 => \^rd_pntr_wr\(1), O => ram_full_i_i_4_n_0 ); ram_full_i_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^rd_pntr_wr\(3), I1 => Q(3), I2 => \^rd_pntr_wr\(2), I3 => Q(2), I4 => Q(4), I5 => \^rd_pntr_wr\(4), O => ram_full_i_i_5_n_0 ); rd_pntr_cdc_inst: entity work.fifo1KB_34bit_xpm_cdc_gray port map ( dest_clk => wr_clk, dest_out_bin(4 downto 0) => \^rd_pntr_wr\(4 downto 0), src_clk => rd_clk, src_in_bin(4 downto 0) => \src_gray_ff_reg[4]_0\(4 downto 0) ); \wr_data_count_i[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2DD2" ) port map ( I0 => \^rd_pntr_wr\(0), I1 => \src_gray_ff_reg[4]\(0), I2 => \^rd_pntr_wr\(1), I3 => \src_gray_ff_reg[4]\(1), O => D(0) ); \wr_data_count_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \wr_data_count_i[4]_i_2_n_0\, I1 => \^rd_pntr_wr\(3), I2 => \src_gray_ff_reg[4]\(3), O => D(1) ); \wr_data_count_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"718E8E71" ) port map ( I0 => \wr_data_count_i[4]_i_2_n_0\, I1 => \src_gray_ff_reg[4]\(3), I2 => \^rd_pntr_wr\(3), I3 => \^rd_pntr_wr\(4), I4 => \src_gray_ff_reg[4]\(4), O => D(2) ); \wr_data_count_i[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"D4DD4444DDDDD4DD" ) port map ( I0 => \^rd_pntr_wr\(2), I1 => \src_gray_ff_reg[4]\(2), I2 => \src_gray_ff_reg[4]\(0), I3 => \^rd_pntr_wr\(0), I4 => \src_gray_ff_reg[4]\(1), I5 => \^rd_pntr_wr\(1), O => \wr_data_count_i[4]_i_2_n_0\ ); wr_pntr_cdc_inst: entity work.\fifo1KB_34bit_xpm_cdc_gray__2\ port map ( dest_clk => rd_clk, dest_out_bin(4 downto 2) => \^wr_pntr_rd\(4 downto 2), dest_out_bin(1 downto 0) => WR_PNTR_RD(1 downto 0), src_clk => wr_clk, src_in_bin(4 downto 0) => \src_gray_ff_reg[4]\(4 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_rd_logic is port ( empty : out STD_LOGIC; tmp_ram_rd_en : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gc0.count_d1_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); rd_clk : in STD_LOGIC; AS : in STD_LOGIC_VECTOR ( 0 to 0 ); ram_empty_i_reg : in STD_LOGIC; rd_en : in STD_LOGIC; ram_empty_i_reg_0 : in STD_LOGIC; WR_PNTR_RD : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_rd_logic : entity is "rd_logic"; end fifo1KB_34bit_rd_logic; architecture STRUCTURE of fifo1KB_34bit_rd_logic is signal empty_fb_i : STD_LOGIC; signal ram_rd_en : STD_LOGIC; signal rpntr_n_0 : STD_LOGIC; begin \gras.rsts\: entity work.fifo1KB_34bit_rd_status_flags_as port map ( AS(0) => AS(0), E(0) => ram_rd_en, empty => empty, \out\ => empty_fb_i, ram_empty_i_reg_0 => rpntr_n_0, rd_clk => rd_clk, rd_en => rd_en, tmp_ram_rd_en => tmp_ram_rd_en ); rpntr: entity work.fifo1KB_34bit_rd_bin_cntr port map ( AS(0) => AS(0), E(0) => ram_rd_en, Q(2 downto 0) => Q(2 downto 0), WR_PNTR_RD(1 downto 0) => WR_PNTR_RD(1 downto 0), \gc0.count_d1_reg[4]_0\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), \out\ => empty_fb_i, ram_empty_i_reg => ram_empty_i_reg, ram_empty_i_reg_0 => ram_empty_i_reg_0, rd_clk => rd_clk, rd_en => rd_en, rd_en_0 => rpntr_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_reset_blk_ramfifo is port ( AR : out STD_LOGIC_VECTOR ( 0 to 0 ); AS : out STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : out STD_LOGIC; \grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_reset_blk_ramfifo : entity is "reset_blk_ramfifo"; end fifo1KB_34bit_reset_blk_ramfifo; architecture STRUCTURE of fifo1KB_34bit_reset_blk_ramfifo is signal \^ar\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^as\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal dest_out : STD_LOGIC; signal \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\ : STD_LOGIC; signal \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0\ : STD_LOGIC; signal \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0\ : STD_LOGIC; signal \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0\ : STD_LOGIC; signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true; signal rd_rst_wr_ext : STD_LOGIC_VECTOR ( 3 downto 0 ); signal rst_d1 : STD_LOGIC; attribute async_reg : string; attribute async_reg of rst_d1 : signal is "true"; attribute msgon : string; attribute msgon of rst_d1 : signal is "true"; signal rst_d2 : STD_LOGIC; attribute async_reg of rst_d2 : signal is "true"; attribute msgon of rst_d2 : signal is "true"; signal rst_d3 : STD_LOGIC; attribute async_reg of rst_d3 : signal is "true"; attribute msgon of rst_d3 : signal is "true"; signal rst_d4 : STD_LOGIC; attribute async_reg of rst_d4 : signal is "true"; attribute msgon of rst_d4 : signal is "true"; signal rst_d5 : STD_LOGIC; attribute async_reg of rst_d5 : signal is "true"; attribute msgon of rst_d5 : signal is "true"; signal rst_d6 : STD_LOGIC; attribute async_reg of rst_d6 : signal is "true"; attribute msgon of rst_d6 : signal is "true"; signal rst_d7 : STD_LOGIC; attribute async_reg of rst_d7 : signal is "true"; attribute msgon of rst_d7 : signal is "true"; signal rst_rd_reg1 : STD_LOGIC; attribute async_reg of rst_rd_reg1 : signal is "true"; attribute msgon of rst_rd_reg1 : signal is "true"; signal rst_rd_reg2 : STD_LOGIC; attribute async_reg of rst_rd_reg2 : signal is "true"; attribute msgon of rst_rd_reg2 : signal is "true"; signal rst_wr_reg1 : STD_LOGIC; attribute async_reg of rst_wr_reg1 : signal is "true"; attribute msgon of rst_wr_reg1 : signal is "true"; signal rst_wr_reg2 : STD_LOGIC; attribute async_reg of rst_wr_reg2 : signal is "true"; attribute msgon of rst_wr_reg2 : signal is "true"; signal sckt_rd_rst_wr : STD_LOGIC; signal \^wr_rst_busy\ : STD_LOGIC; signal wr_rst_rd_ext : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes"; attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true"; attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true; attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes"; attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true"; attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true; attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes"; attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true"; attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d4_reg\ : label is std.standard.true; attribute KEEP of \grstd1.grst_full.grst_f.rst_d4_reg\ : label is "yes"; attribute msgon of \grstd1.grst_full.grst_f.rst_d4_reg\ : label is "true"; attribute DEF_VAL : string; attribute DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "1'b0"; attribute DEST_SYNC_FF : integer; attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 2; attribute INIT_SYNC_FF : integer; attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 0; attribute INV_DEF_VAL : string; attribute INV_DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "1'b1"; attribute RST_ACTIVE_HIGH : integer; attribute RST_ACTIVE_HIGH of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 1; attribute VERSION : integer; attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is 0; attribute XPM_CDC : string; attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "ASYNC_RST"; attribute XPM_MODULE : string; attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\ : label is "TRUE"; attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 4; attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; attribute SIM_ASSERT_CHK : integer; attribute SIM_ASSERT_CHK of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; attribute SRC_INPUT_REG : integer; attribute SRC_INPUT_REG of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is 0; attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is "SINGLE"; attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\ : label is "TRUE"; attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 4; attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; attribute SIM_ASSERT_CHK of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; attribute SRC_INPUT_REG of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is 0; attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is "SINGLE"; attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\ : label is "TRUE"; attribute DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "1'b0"; attribute DEST_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 2; attribute INIT_SYNC_FF of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 0; attribute INV_DEF_VAL of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "1'b1"; attribute RST_ACTIVE_HIGH of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 1; attribute VERSION of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is 0; attribute XPM_CDC of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "ASYNC_RST"; attribute XPM_MODULE of \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\ : label is "TRUE"; begin AR(0) <= \^ar\(0); AS(0) <= \^as\(0); \grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d3; \out\ <= rst_d2; wr_rst_busy <= \^wr_rst_busy\; \grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \^wr_rst_busy\, PRE => rst_wr_reg2, Q => rst_d1 ); \grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => rst_d1, PRE => rst_wr_reg2, Q => rst_d2 ); \grstd1.grst_full.grst_f.rst_d3_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rst_d2, I1 => \^ar\(0), O => \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\ ); \grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\, PRE => rst_wr_reg2, Q => rst_d3 ); \grstd1.grst_full.grst_f.rst_d4_reg\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => '1', D => rst_d3, PRE => rst_wr_reg2, Q => rst_d4 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => wr_rst_reg(2) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => wr_rst_reg(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => rst_d7 ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => wr_rst_reg(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => rd_rst_reg(2) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => rd_rst_reg(1) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => rd_rst_reg(0) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => rst_wr_reg1 ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => rst_rd_reg1 ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => rst_d5 ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => rst_d6 ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => rst_wr_reg2, D => sckt_rd_rst_wr, Q => rd_rst_wr_ext(0) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => rst_wr_reg2, D => rd_rst_wr_ext(0), Q => rd_rst_wr_ext(1) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => rst_wr_reg2, D => rd_rst_wr_ext(1), Q => rd_rst_wr_ext(2) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rd_rst_wr_ext_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', CLR => rst_wr_reg2, D => rd_rst_wr_ext(2), Q => rd_rst_wr_ext(3) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst\: entity work.fifo1KB_34bit_xpm_cdc_async_rst port map ( dest_arst => rst_rd_reg2, dest_clk => rd_clk, src_arst => rst ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^as\(0), I1 => wr_rst_rd_ext(1), O => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0\ ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', D => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_i_1_n_0\, PRE => rst_rd_reg2, Q => \^as\(0) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"8A" ) port map ( I0 => \^ar\(0), I1 => rd_rst_wr_ext(0), I2 => rd_rst_wr_ext(1), O => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0\ ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_i_1_n_0\, PRE => rst_wr_reg2, Q => \^ar\(0) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAA08AA" ) port map ( I0 => \^wr_rst_busy\, I1 => rd_rst_wr_ext(1), I2 => rd_rst_wr_ext(0), I3 => rd_rst_wr_ext(3), I4 => rd_rst_wr_ext(2), O => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0\ ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_reg\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => wr_clk, CE => '1', D => \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_busy_i_i_1_n_0\, PRE => rst_wr_reg2, Q => \^wr_rst_busy\ ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', CLR => rst_rd_reg2, D => dest_out, Q => wr_rst_rd_ext(0) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => rd_clk, CE => '1', CLR => rst_rd_reg2, D => wr_rst_rd_ext(0), Q => wr_rst_rd_ext(1) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr\: entity work.fifo1KB_34bit_xpm_cdc_single port map ( dest_clk => wr_clk, dest_out => sckt_rd_rst_wr, src_clk => rd_clk, src_in => \^as\(0) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd\: entity work.\fifo1KB_34bit_xpm_cdc_single__2\ port map ( dest_clk => rd_clk, dest_out => dest_out, src_clk => wr_clk, src_in => \^ar\(0) ); \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst\: entity work.\fifo1KB_34bit_xpm_cdc_async_rst__1\ port map ( dest_arst => rst_wr_reg2, dest_clk => wr_clk, src_arst => rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_wr_logic is port ( full : out STD_LOGIC; prog_full : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); \gic0.gc0.count_d2_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); \gic0.gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \gic0.gc0.count_reg[3]\ : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); ram_full_fb_i_reg : in STD_LOGIC; wr_clk : in STD_LOGIC; \out\ : in STD_LOGIC; RD_PNTR_WR : in STD_LOGIC_VECTOR ( 4 downto 0 ); \gdiff.diff_pntr_pad_reg[5]\ : in STD_LOGIC; wr_en : in STD_LOGIC; \gpf1.prog_full_i_reg\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 2 downto 0 ); AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_wr_logic : entity is "wr_logic"; end fifo1KB_34bit_wr_logic; architecture STRUCTURE of fifo1KB_34bit_wr_logic is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gwas.wsts_n_1\ : STD_LOGIC; signal minusOp : STD_LOGIC_VECTOR ( 2 to 2 ); signal plusOp : STD_LOGIC_VECTOR ( 5 downto 1 ); signal wpntr_n_6 : STD_LOGIC; begin E(0) <= \^e\(0); \gwas.gpf.wrpf\: entity work.fifo1KB_34bit_wr_pf_as port map ( AR(0) => AR(0), D(4 downto 0) => plusOp(5 downto 1), \gpf1.prog_full_i_reg_0\ => \gpf1.prog_full_i_reg\, \gpf1.prog_full_i_reg_1\ => \gwas.wsts_n_1\, \out\ => \out\, prog_full => prog_full, wr_clk => wr_clk ); \gwas.gwdc0.wdc\: entity work.fifo1KB_34bit_wr_dc_as port map ( AR(0) => AR(0), D(4 downto 3) => D(2 downto 1), D(2) => minusOp(2), D(1) => D(0), D(0) => wpntr_n_6, wr_clk => wr_clk, wr_data_count(4 downto 0) => wr_data_count(4 downto 0) ); \gwas.wsts\: entity work.fifo1KB_34bit_wr_status_flags_as port map ( E(0) => \^e\(0), full => full, \out\ => \gwas.wsts_n_1\, ram_full_fb_i_reg_0 => ram_full_fb_i_reg, ram_full_fb_i_reg_1 => \out\, wr_clk => wr_clk, wr_en => wr_en ); wpntr: entity work.fifo1KB_34bit_wr_bin_cntr port map ( AR(0) => AR(0), D(1) => minusOp(2), D(0) => wpntr_n_6, E(0) => \^e\(0), Q(4 downto 0) => Q(4 downto 0), RD_PNTR_WR(4 downto 0) => RD_PNTR_WR(4 downto 0), \gdiff.diff_pntr_pad_reg[5]\ => \gdiff.diff_pntr_pad_reg[5]\, \gic0.gc0.count_d1_reg[2]_0\(4 downto 0) => plusOp(5 downto 1), \gic0.gc0.count_d2_reg[4]_0\(4 downto 0) => \gic0.gc0.count_d2_reg[4]\(4 downto 0), \gic0.gc0.count_reg[1]_0\(1 downto 0) => \gic0.gc0.count_reg[1]\(1 downto 0), \gic0.gc0.count_reg[3]_0\ => \gic0.gc0.count_reg[3]\, \out\ => \gwas.wsts_n_1\, wr_clk => wr_clk, wr_en => wr_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_blk_mem_gen_generic_cstr is port ( dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; tmp_ram_rd_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); AS : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); din : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end fifo1KB_34bit_blk_mem_gen_generic_cstr; architecture STRUCTURE of fifo1KB_34bit_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.fifo1KB_34bit_blk_mem_gen_prim_width port map ( AS(0) => AS(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0), E(0) => E(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), rd_clk => rd_clk, tmp_ram_rd_en => tmp_ram_rd_en, wr_clk => wr_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_blk_mem_gen_top is port ( dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; tmp_ram_rd_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); AS : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); din : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_blk_mem_gen_top : entity is "blk_mem_gen_top"; end fifo1KB_34bit_blk_mem_gen_top; architecture STRUCTURE of fifo1KB_34bit_blk_mem_gen_top is begin \valid.cstr\: entity work.fifo1KB_34bit_blk_mem_gen_generic_cstr port map ( AS(0) => AS(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0), E(0) => E(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), rd_clk => rd_clk, tmp_ram_rd_en => tmp_ram_rd_en, wr_clk => wr_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_blk_mem_gen_v8_4_4_synth is port ( dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; tmp_ram_rd_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); AS : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); din : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth"; end fifo1KB_34bit_blk_mem_gen_v8_4_4_synth; architecture STRUCTURE of fifo1KB_34bit_blk_mem_gen_v8_4_4_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.fifo1KB_34bit_blk_mem_gen_top port map ( AS(0) => AS(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0), E(0) => E(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), rd_clk => rd_clk, tmp_ram_rd_en => tmp_ram_rd_en, wr_clk => wr_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_blk_mem_gen_v8_4_4 is port ( dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; tmp_ram_rd_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); AS : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); din : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4"; end fifo1KB_34bit_blk_mem_gen_v8_4_4; architecture STRUCTURE of fifo1KB_34bit_blk_mem_gen_v8_4_4 is begin inst_blk_mem_gen: entity work.fifo1KB_34bit_blk_mem_gen_v8_4_4_synth port map ( AS(0) => AS(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0), E(0) => E(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), rd_clk => rd_clk, tmp_ram_rd_en => tmp_ram_rd_en, wr_clk => wr_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_memory is port ( dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); rd_clk : in STD_LOGIC; wr_clk : in STD_LOGIC; tmp_ram_rd_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); AS : in STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); din : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_memory : entity is "memory"; end fifo1KB_34bit_memory; architecture STRUCTURE of fifo1KB_34bit_memory is begin \gbm.gbmg.gbmga.ngecc.bmg\: entity work.fifo1KB_34bit_blk_mem_gen_v8_4_4 port map ( AS(0) => AS(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0), E(0) => E(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), rd_clk => rd_clk, tmp_ram_rd_en => tmp_ram_rd_en, wr_clk => wr_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_fifo_generator_ramfifo is port ( wr_rst_busy : out STD_LOGIC; AR : out STD_LOGIC_VECTOR ( 0 to 0 ); dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); empty : out STD_LOGIC; full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full : out STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 33 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo"; end fifo1KB_34bit_fifo_generator_ramfifo; architecture STRUCTURE of fifo1KB_34bit_fifo_generator_ramfifo is signal \^ar\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC; signal \gntv_or_sync_fifo.gcx.clkx_n_10\ : STD_LOGIC; signal \gntv_or_sync_fifo.gcx.clkx_n_13\ : STD_LOGIC; signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_15\ : STD_LOGIC; signal minusOp : STD_LOGIC_VECTOR ( 4 downto 1 ); signal ram_wr_en : STD_LOGIC; signal rd_pntr : STD_LOGIC_VECTOR ( 4 downto 0 ); signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 2 ); signal rd_pntr_wr : STD_LOGIC_VECTOR ( 4 downto 0 ); signal rst_full_ff_i : STD_LOGIC; signal rst_full_gen_i : STD_LOGIC; signal rstblk_n_0 : STD_LOGIC; signal tmp_ram_rd_en : STD_LOGIC; signal wr_pntr : STD_LOGIC_VECTOR ( 4 downto 0 ); signal wr_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wr_pntr_rd : STD_LOGIC_VECTOR ( 1 downto 0 ); begin AR(0) <= \^ar\(0); \gntv_or_sync_fifo.gcx.clkx\: entity work.fifo1KB_34bit_clk_x_pntrs port map ( D(2 downto 1) => minusOp(4 downto 3), D(0) => minusOp(1), E(0) => ram_wr_en, Q(4 downto 0) => wr_pntr_plus1(4 downto 0), RD_PNTR_WR(4 downto 0) => rd_pntr_wr(4 downto 0), WR_PNTR_RD(1 downto 0) => wr_pntr_rd(1 downto 0), \dest_out_bin_ff_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\, \dest_out_bin_ff_reg[3]_0\ => \gntv_or_sync_fifo.gcx.clkx_n_10\, \dest_out_bin_ff_reg[3]_1\ => \gntv_or_sync_fifo.gcx.clkx_n_13\, \grstd1.grst_full.grst_f.rst_d3_reg\ => \gntv_or_sync_fifo.gcx.clkx_n_0\, \out\ => rst_full_gen_i, ram_empty_i_reg(2 downto 0) => rd_pntr_plus1(4 downto 2), ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_15\, ram_full_fb_i_reg_0(1 downto 0) => wr_pntr_plus2(1 downto 0), rd_clk => rd_clk, \src_gray_ff_reg[4]\(4 downto 0) => wr_pntr(4 downto 0), \src_gray_ff_reg[4]_0\(4 downto 0) => rd_pntr(4 downto 0), wr_clk => wr_clk ); \gntv_or_sync_fifo.gl0.rd\: entity work.fifo1KB_34bit_rd_logic port map ( AS(0) => \^ar\(0), Q(2 downto 0) => rd_pntr_plus1(4 downto 2), WR_PNTR_RD(1 downto 0) => wr_pntr_rd(1 downto 0), empty => empty, \gc0.count_d1_reg[4]\(4 downto 0) => rd_pntr(4 downto 0), ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_10\, ram_empty_i_reg_0 => \gntv_or_sync_fifo.gcx.clkx_n_13\, rd_clk => rd_clk, rd_en => rd_en, tmp_ram_rd_en => tmp_ram_rd_en ); \gntv_or_sync_fifo.gl0.wr\: entity work.fifo1KB_34bit_wr_logic port map ( AR(0) => rstblk_n_0, D(2 downto 1) => minusOp(4 downto 3), D(0) => minusOp(1), E(0) => ram_wr_en, Q(4 downto 0) => wr_pntr_plus1(4 downto 0), RD_PNTR_WR(4 downto 0) => rd_pntr_wr(4 downto 0), full => full, \gdiff.diff_pntr_pad_reg[5]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\, \gic0.gc0.count_d2_reg[4]\(4 downto 0) => wr_pntr(4 downto 0), \gic0.gc0.count_reg[1]\(1 downto 0) => wr_pntr_plus2(1 downto 0), \gic0.gc0.count_reg[3]\ => \gntv_or_sync_fifo.gl0.wr_n_15\, \gpf1.prog_full_i_reg\ => rst_full_gen_i, \out\ => rst_full_ff_i, prog_full => prog_full, ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\, wr_clk => wr_clk, wr_data_count(4 downto 0) => wr_data_count(4 downto 0), wr_en => wr_en ); \gntv_or_sync_fifo.mem\: entity work.fifo1KB_34bit_memory port map ( AS(0) => \^ar\(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4 downto 0) => rd_pntr(4 downto 0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => wr_pntr(4 downto 0), E(0) => ram_wr_en, din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), rd_clk => rd_clk, tmp_ram_rd_en => tmp_ram_rd_en, wr_clk => wr_clk ); rstblk: entity work.fifo1KB_34bit_reset_blk_ramfifo port map ( AR(0) => rstblk_n_0, AS(0) => \^ar\(0), \grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_gen_i, \out\ => rst_full_ff_i, rd_clk => rd_clk, rst => rst, wr_clk => wr_clk, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_fifo_generator_top is port ( wr_rst_busy : out STD_LOGIC; AS : out STD_LOGIC_VECTOR ( 0 to 0 ); dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); empty : out STD_LOGIC; full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full : out STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 33 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_fifo_generator_top : entity is "fifo_generator_top"; end fifo1KB_34bit_fifo_generator_top; architecture STRUCTURE of fifo1KB_34bit_fifo_generator_top is begin \grf.rf\: entity work.fifo1KB_34bit_fifo_generator_ramfifo port map ( AR(0) => AS(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), empty => empty, full => full, prog_full => prog_full, rd_clk => rd_clk, rd_en => rd_en, rst => rst, wr_clk => wr_clk, wr_data_count(4 downto 0) => wr_data_count(4 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_fifo_generator_v13_2_5_synth is port ( wr_rst_busy : out STD_LOGIC; AR : out STD_LOGIC_VECTOR ( 0 to 0 ); dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); empty : out STD_LOGIC; full : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full : out STD_LOGIC; rst : in STD_LOGIC; wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 33 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_fifo_generator_v13_2_5_synth : entity is "fifo_generator_v13_2_5_synth"; end fifo1KB_34bit_fifo_generator_v13_2_5_synth; architecture STRUCTURE of fifo1KB_34bit_fifo_generator_v13_2_5_synth is begin \gconvfifo.rf\: entity work.fifo1KB_34bit_fifo_generator_top port map ( AS(0) => AR(0), din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), empty => empty, full => full, prog_full => prog_full, rd_clk => rd_clk, rd_en => rd_en, rst => rst, wr_clk => wr_clk, wr_data_count(4 downto 0) => wr_data_count(4 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit_fifo_generator_v13_2_5 is port ( backup : in STD_LOGIC; backup_marker : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; srst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_rst : in STD_LOGIC; rd_clk : in STD_LOGIC; rd_rst : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 33 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC; prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); int_clk : in STD_LOGIC; injectdbiterr : in STD_LOGIC; injectsbiterr : in STD_LOGIC; sleep : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); full : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; overflow : out STD_LOGIC; empty : out STD_LOGIC; almost_empty : out STD_LOGIC; valid : out STD_LOGIC; underflow : out STD_LOGIC; data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full : out STD_LOGIC; prog_empty : out STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; m_aclk : in STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; m_aclk_en : in STD_LOGIC; s_aclk_en : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC; s_axis_tvalid : in STD_LOGIC; s_axis_tready : out STD_LOGIC; s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tlast : in STD_LOGIC; s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axis_tvalid : out STD_LOGIC; m_axis_tready : in STD_LOGIC; m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tlast : out STD_LOGIC; m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); axi_aw_injectsbiterr : in STD_LOGIC; axi_aw_injectdbiterr : in STD_LOGIC; axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_aw_sbiterr : out STD_LOGIC; axi_aw_dbiterr : out STD_LOGIC; axi_aw_overflow : out STD_LOGIC; axi_aw_underflow : out STD_LOGIC; axi_aw_prog_full : out STD_LOGIC; axi_aw_prog_empty : out STD_LOGIC; axi_w_injectsbiterr : in STD_LOGIC; axi_w_injectdbiterr : in STD_LOGIC; axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_w_sbiterr : out STD_LOGIC; axi_w_dbiterr : out STD_LOGIC; axi_w_overflow : out STD_LOGIC; axi_w_underflow : out STD_LOGIC; axi_w_prog_full : out STD_LOGIC; axi_w_prog_empty : out STD_LOGIC; axi_b_injectsbiterr : in STD_LOGIC; axi_b_injectdbiterr : in STD_LOGIC; axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_b_sbiterr : out STD_LOGIC; axi_b_dbiterr : out STD_LOGIC; axi_b_overflow : out STD_LOGIC; axi_b_underflow : out STD_LOGIC; axi_b_prog_full : out STD_LOGIC; axi_b_prog_empty : out STD_LOGIC; axi_ar_injectsbiterr : in STD_LOGIC; axi_ar_injectdbiterr : in STD_LOGIC; axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_ar_sbiterr : out STD_LOGIC; axi_ar_dbiterr : out STD_LOGIC; axi_ar_overflow : out STD_LOGIC; axi_ar_underflow : out STD_LOGIC; axi_ar_prog_full : out STD_LOGIC; axi_ar_prog_empty : out STD_LOGIC; axi_r_injectsbiterr : in STD_LOGIC; axi_r_injectdbiterr : in STD_LOGIC; axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_r_sbiterr : out STD_LOGIC; axi_r_dbiterr : out STD_LOGIC; axi_r_overflow : out STD_LOGIC; axi_r_underflow : out STD_LOGIC; axi_r_prog_full : out STD_LOGIC; axi_r_prog_empty : out STD_LOGIC; axis_injectsbiterr : in STD_LOGIC; axis_injectdbiterr : in STD_LOGIC; axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axis_sbiterr : out STD_LOGIC; axis_dbiterr : out STD_LOGIC; axis_overflow : out STD_LOGIC; axis_underflow : out STD_LOGIC; axis_prog_full : out STD_LOGIC; axis_prog_empty : out STD_LOGIC ); attribute C_ADD_NGC_CONSTRAINT : integer; attribute C_ADD_NGC_CONSTRAINT of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_APPLICATION_TYPE_AXIS : integer; attribute C_APPLICATION_TYPE_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_APPLICATION_TYPE_RACH : integer; attribute C_APPLICATION_TYPE_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_APPLICATION_TYPE_RDCH : integer; attribute C_APPLICATION_TYPE_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_APPLICATION_TYPE_WACH : integer; attribute C_APPLICATION_TYPE_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_APPLICATION_TYPE_WDCH : integer; attribute C_APPLICATION_TYPE_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_APPLICATION_TYPE_WRCH : integer; attribute C_APPLICATION_TYPE_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_AXIS_TDATA_WIDTH : integer; attribute C_AXIS_TDATA_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 8; attribute C_AXIS_TDEST_WIDTH : integer; attribute C_AXIS_TDEST_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXIS_TID_WIDTH : integer; attribute C_AXIS_TID_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXIS_TKEEP_WIDTH : integer; attribute C_AXIS_TKEEP_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXIS_TSTRB_WIDTH : integer; attribute C_AXIS_TSTRB_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXIS_TUSER_WIDTH : integer; attribute C_AXIS_TUSER_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 4; attribute C_AXIS_TYPE : integer; attribute C_AXIS_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 64; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXI_LEN_WIDTH : integer; attribute C_AXI_LEN_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 8; attribute C_AXI_LOCK_WIDTH : integer; attribute C_AXI_LOCK_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_COMMON_CLOCK : integer; attribute C_COMMON_CLOCK of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_COUNT_TYPE : integer; attribute C_COUNT_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_DATA_COUNT_WIDTH : integer; attribute C_DATA_COUNT_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 5; attribute C_DEFAULT_VALUE : string; attribute C_DEFAULT_VALUE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "BlankString"; attribute C_DIN_WIDTH : integer; attribute C_DIN_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 34; attribute C_DIN_WIDTH_AXIS : integer; attribute C_DIN_WIDTH_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_DIN_WIDTH_RACH : integer; attribute C_DIN_WIDTH_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 32; attribute C_DIN_WIDTH_RDCH : integer; attribute C_DIN_WIDTH_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 64; attribute C_DIN_WIDTH_WACH : integer; attribute C_DIN_WIDTH_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_DIN_WIDTH_WDCH : integer; attribute C_DIN_WIDTH_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 64; attribute C_DIN_WIDTH_WRCH : integer; attribute C_DIN_WIDTH_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 2; attribute C_DOUT_RST_VAL : string; attribute C_DOUT_RST_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "0"; attribute C_DOUT_WIDTH : integer; attribute C_DOUT_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 34; attribute C_ENABLE_RLOCS : integer; attribute C_ENABLE_RLOCS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ENABLE_RST_SYNC : integer; attribute C_ENABLE_RST_SYNC of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ERROR_INJECTION_TYPE : integer; attribute C_ERROR_INJECTION_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ERROR_INJECTION_TYPE_AXIS : integer; attribute C_ERROR_INJECTION_TYPE_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ERROR_INJECTION_TYPE_RACH : integer; attribute C_ERROR_INJECTION_TYPE_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ERROR_INJECTION_TYPE_RDCH : integer; attribute C_ERROR_INJECTION_TYPE_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ERROR_INJECTION_TYPE_WACH : integer; attribute C_ERROR_INJECTION_TYPE_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ERROR_INJECTION_TYPE_WDCH : integer; attribute C_ERROR_INJECTION_TYPE_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_ERROR_INJECTION_TYPE_WRCH : integer; attribute C_ERROR_INJECTION_TYPE_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_FAMILY : string; attribute C_FAMILY of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "virtex7"; attribute C_FULL_FLAGS_RST_VAL : integer; attribute C_FULL_FLAGS_RST_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_ALMOST_EMPTY : integer; attribute C_HAS_ALMOST_EMPTY of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_ALMOST_FULL : integer; attribute C_HAS_ALMOST_FULL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXIS_TDATA : integer; attribute C_HAS_AXIS_TDATA of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_AXIS_TDEST : integer; attribute C_HAS_AXIS_TDEST of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXIS_TID : integer; attribute C_HAS_AXIS_TID of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXIS_TKEEP : integer; attribute C_HAS_AXIS_TKEEP of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXIS_TLAST : integer; attribute C_HAS_AXIS_TLAST of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXIS_TREADY : integer; attribute C_HAS_AXIS_TREADY of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_AXIS_TSTRB : integer; attribute C_HAS_AXIS_TSTRB of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXIS_TUSER : integer; attribute C_HAS_AXIS_TUSER of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_AXI_ARUSER : integer; attribute C_HAS_AXI_ARUSER of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXI_AWUSER : integer; attribute C_HAS_AXI_AWUSER of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXI_BUSER : integer; attribute C_HAS_AXI_BUSER of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXI_RD_CHANNEL : integer; attribute C_HAS_AXI_RD_CHANNEL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_AXI_RUSER : integer; attribute C_HAS_AXI_RUSER of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_AXI_WR_CHANNEL : integer; attribute C_HAS_AXI_WR_CHANNEL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_AXI_WUSER : integer; attribute C_HAS_AXI_WUSER of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_BACKUP : integer; attribute C_HAS_BACKUP of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_DATA_COUNT : integer; attribute C_HAS_DATA_COUNT of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_DATA_COUNTS_AXIS : integer; attribute C_HAS_DATA_COUNTS_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_DATA_COUNTS_RACH : integer; attribute C_HAS_DATA_COUNTS_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_DATA_COUNTS_RDCH : integer; attribute C_HAS_DATA_COUNTS_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_DATA_COUNTS_WACH : integer; attribute C_HAS_DATA_COUNTS_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_DATA_COUNTS_WDCH : integer; attribute C_HAS_DATA_COUNTS_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_DATA_COUNTS_WRCH : integer; attribute C_HAS_DATA_COUNTS_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_INT_CLK : integer; attribute C_HAS_INT_CLK of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_MASTER_CE : integer; attribute C_HAS_MASTER_CE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_MEMINIT_FILE : integer; attribute C_HAS_MEMINIT_FILE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_OVERFLOW : integer; attribute C_HAS_OVERFLOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_PROG_FLAGS_AXIS : integer; attribute C_HAS_PROG_FLAGS_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_PROG_FLAGS_RACH : integer; attribute C_HAS_PROG_FLAGS_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_PROG_FLAGS_RDCH : integer; attribute C_HAS_PROG_FLAGS_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_PROG_FLAGS_WACH : integer; attribute C_HAS_PROG_FLAGS_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_PROG_FLAGS_WDCH : integer; attribute C_HAS_PROG_FLAGS_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_PROG_FLAGS_WRCH : integer; attribute C_HAS_PROG_FLAGS_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_RD_DATA_COUNT : integer; attribute C_HAS_RD_DATA_COUNT of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_RD_RST : integer; attribute C_HAS_RD_RST of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_RST : integer; attribute C_HAS_RST of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_SLAVE_CE : integer; attribute C_HAS_SLAVE_CE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_SRST : integer; attribute C_HAS_SRST of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_UNDERFLOW : integer; attribute C_HAS_UNDERFLOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_VALID : integer; attribute C_HAS_VALID of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_WR_ACK : integer; attribute C_HAS_WR_ACK of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_HAS_WR_DATA_COUNT : integer; attribute C_HAS_WR_DATA_COUNT of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_HAS_WR_RST : integer; attribute C_HAS_WR_RST of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_IMPLEMENTATION_TYPE : integer; attribute C_IMPLEMENTATION_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 2; attribute C_IMPLEMENTATION_TYPE_AXIS : integer; attribute C_IMPLEMENTATION_TYPE_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_IMPLEMENTATION_TYPE_RACH : integer; attribute C_IMPLEMENTATION_TYPE_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_IMPLEMENTATION_TYPE_RDCH : integer; attribute C_IMPLEMENTATION_TYPE_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_IMPLEMENTATION_TYPE_WACH : integer; attribute C_IMPLEMENTATION_TYPE_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_IMPLEMENTATION_TYPE_WDCH : integer; attribute C_IMPLEMENTATION_TYPE_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_IMPLEMENTATION_TYPE_WRCH : integer; attribute C_IMPLEMENTATION_TYPE_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_INIT_WR_PNTR_VAL : integer; attribute C_INIT_WR_PNTR_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_MEMORY_TYPE : integer; attribute C_MEMORY_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_MIF_FILE_NAME : string; attribute C_MIF_FILE_NAME of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "BlankString"; attribute C_MSGON_VAL : integer; attribute C_MSGON_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_OPTIMIZATION_MODE : integer; attribute C_OPTIMIZATION_MODE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_OVERFLOW_LOW : integer; attribute C_OVERFLOW_LOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_POWER_SAVING_MODE : integer; attribute C_POWER_SAVING_MODE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PRELOAD_LATENCY : integer; attribute C_PRELOAD_LATENCY of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_PRELOAD_REGS : integer; attribute C_PRELOAD_REGS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PRIM_FIFO_TYPE : string; attribute C_PRIM_FIFO_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_AXIS : string; attribute C_PRIM_FIFO_TYPE_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "1kx18"; attribute C_PRIM_FIFO_TYPE_RACH : string; attribute C_PRIM_FIFO_TYPE_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_RDCH : string; attribute C_PRIM_FIFO_TYPE_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "1kx36"; attribute C_PRIM_FIFO_TYPE_WACH : string; attribute C_PRIM_FIFO_TYPE_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_WDCH : string; attribute C_PRIM_FIFO_TYPE_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "1kx36"; attribute C_PRIM_FIFO_TYPE_WRCH : string; attribute C_PRIM_FIFO_TYPE_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "512x36"; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 2; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1022; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 3; attribute C_PROG_EMPTY_TYPE : integer; attribute C_PROG_EMPTY_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_EMPTY_TYPE_AXIS : integer; attribute C_PROG_EMPTY_TYPE_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_EMPTY_TYPE_RACH : integer; attribute C_PROG_EMPTY_TYPE_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_EMPTY_TYPE_RDCH : integer; attribute C_PROG_EMPTY_TYPE_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_EMPTY_TYPE_WACH : integer; attribute C_PROG_EMPTY_TYPE_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_EMPTY_TYPE_WDCH : integer; attribute C_PROG_EMPTY_TYPE_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_EMPTY_TYPE_WRCH : integer; attribute C_PROG_EMPTY_TYPE_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 27; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1023; attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 26; attribute C_PROG_FULL_TYPE : integer; attribute C_PROG_FULL_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_PROG_FULL_TYPE_AXIS : integer; attribute C_PROG_FULL_TYPE_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_FULL_TYPE_RACH : integer; attribute C_PROG_FULL_TYPE_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_FULL_TYPE_RDCH : integer; attribute C_PROG_FULL_TYPE_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_FULL_TYPE_WACH : integer; attribute C_PROG_FULL_TYPE_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_FULL_TYPE_WDCH : integer; attribute C_PROG_FULL_TYPE_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_PROG_FULL_TYPE_WRCH : integer; attribute C_PROG_FULL_TYPE_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_RACH_TYPE : integer; attribute C_RACH_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_RDCH_TYPE : integer; attribute C_RDCH_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_RD_DATA_COUNT_WIDTH : integer; attribute C_RD_DATA_COUNT_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 5; attribute C_RD_DEPTH : integer; attribute C_RD_DEPTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 32; attribute C_RD_FREQ : integer; attribute C_RD_FREQ of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_RD_PNTR_WIDTH : integer; attribute C_RD_PNTR_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 5; attribute C_REG_SLICE_MODE_AXIS : integer; attribute C_REG_SLICE_MODE_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_REG_SLICE_MODE_RACH : integer; attribute C_REG_SLICE_MODE_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_REG_SLICE_MODE_RDCH : integer; attribute C_REG_SLICE_MODE_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_REG_SLICE_MODE_WACH : integer; attribute C_REG_SLICE_MODE_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_REG_SLICE_MODE_WDCH : integer; attribute C_REG_SLICE_MODE_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_REG_SLICE_MODE_WRCH : integer; attribute C_REG_SLICE_MODE_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_SYNCHRONIZER_STAGE : integer; attribute C_SYNCHRONIZER_STAGE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 2; attribute C_UNDERFLOW_LOW : integer; attribute C_UNDERFLOW_LOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_COMMON_OVERFLOW : integer; attribute C_USE_COMMON_OVERFLOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_COMMON_UNDERFLOW : integer; attribute C_USE_COMMON_UNDERFLOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_DEFAULT_SETTINGS : integer; attribute C_USE_DEFAULT_SETTINGS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_DOUT_RST : integer; attribute C_USE_DOUT_RST of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_ECC_AXIS : integer; attribute C_USE_ECC_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_ECC_RACH : integer; attribute C_USE_ECC_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_ECC_RDCH : integer; attribute C_USE_ECC_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_ECC_WACH : integer; attribute C_USE_ECC_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_ECC_WDCH : integer; attribute C_USE_ECC_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_ECC_WRCH : integer; attribute C_USE_ECC_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_EMBEDDED_REG : integer; attribute C_USE_EMBEDDED_REG of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_FIFO16_FLAGS : integer; attribute C_USE_FIFO16_FLAGS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_FWFT_DATA_COUNT : integer; attribute C_USE_FWFT_DATA_COUNT of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_USE_PIPELINE_REG : integer; attribute C_USE_PIPELINE_REG of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_VALID_LOW : integer; attribute C_VALID_LOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_WACH_TYPE : integer; attribute C_WACH_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_WDCH_TYPE : integer; attribute C_WDCH_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_WRCH_TYPE : integer; attribute C_WRCH_TYPE of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_WR_ACK_LOW : integer; attribute C_WR_ACK_LOW of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 0; attribute C_WR_DATA_COUNT_WIDTH : integer; attribute C_WR_DATA_COUNT_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 5; attribute C_WR_DEPTH : integer; attribute C_WR_DEPTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 32; attribute C_WR_DEPTH_AXIS : integer; attribute C_WR_DEPTH_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1024; attribute C_WR_DEPTH_RACH : integer; attribute C_WR_DEPTH_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 16; attribute C_WR_DEPTH_RDCH : integer; attribute C_WR_DEPTH_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1024; attribute C_WR_DEPTH_WACH : integer; attribute C_WR_DEPTH_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 16; attribute C_WR_DEPTH_WDCH : integer; attribute C_WR_DEPTH_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1024; attribute C_WR_DEPTH_WRCH : integer; attribute C_WR_DEPTH_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 16; attribute C_WR_FREQ : integer; attribute C_WR_FREQ of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute C_WR_PNTR_WIDTH : integer; attribute C_WR_PNTR_WIDTH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 5; attribute C_WR_PNTR_WIDTH_AXIS : integer; attribute C_WR_PNTR_WIDTH_AXIS of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 10; attribute C_WR_PNTR_WIDTH_RACH : integer; attribute C_WR_PNTR_WIDTH_RACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 4; attribute C_WR_PNTR_WIDTH_RDCH : integer; attribute C_WR_PNTR_WIDTH_RDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 10; attribute C_WR_PNTR_WIDTH_WACH : integer; attribute C_WR_PNTR_WIDTH_WACH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 4; attribute C_WR_PNTR_WIDTH_WDCH : integer; attribute C_WR_PNTR_WIDTH_WDCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 10; attribute C_WR_PNTR_WIDTH_WRCH : integer; attribute C_WR_PNTR_WIDTH_WRCH of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of fifo1KB_34bit_fifo_generator_v13_2_5 : entity is "fifo_generator_v13_2_5"; end fifo1KB_34bit_fifo_generator_v13_2_5; architecture STRUCTURE of fifo1KB_34bit_fifo_generator_v13_2_5 is signal \\ : STD_LOGIC; signal \\ : STD_LOGIC; begin almost_empty <= \\; almost_full <= \\; axi_ar_data_count(4) <= \\; axi_ar_data_count(3) <= \\; axi_ar_data_count(2) <= \\; axi_ar_data_count(1) <= \\; axi_ar_data_count(0) <= \\; axi_ar_dbiterr <= \\; axi_ar_overflow <= \\; axi_ar_prog_empty <= \\; axi_ar_prog_full <= \\; axi_ar_rd_data_count(4) <= \\; axi_ar_rd_data_count(3) <= \\; axi_ar_rd_data_count(2) <= \\; axi_ar_rd_data_count(1) <= \\; axi_ar_rd_data_count(0) <= \\; axi_ar_sbiterr <= \\; axi_ar_underflow <= \\; axi_ar_wr_data_count(4) <= \\; axi_ar_wr_data_count(3) <= \\; axi_ar_wr_data_count(2) <= \\; axi_ar_wr_data_count(1) <= \\; axi_ar_wr_data_count(0) <= \\; axi_aw_data_count(4) <= \\; axi_aw_data_count(3) <= \\; axi_aw_data_count(2) <= \\; axi_aw_data_count(1) <= \\; axi_aw_data_count(0) <= \\; axi_aw_dbiterr <= \\; axi_aw_overflow <= \\; axi_aw_prog_empty <= \\; axi_aw_prog_full <= \\; axi_aw_rd_data_count(4) <= \\; axi_aw_rd_data_count(3) <= \\; axi_aw_rd_data_count(2) <= \\; axi_aw_rd_data_count(1) <= \\; axi_aw_rd_data_count(0) <= \\; axi_aw_sbiterr <= \\; axi_aw_underflow <= \\; axi_aw_wr_data_count(4) <= \\; axi_aw_wr_data_count(3) <= \\; axi_aw_wr_data_count(2) <= \\; axi_aw_wr_data_count(1) <= \\; axi_aw_wr_data_count(0) <= \\; axi_b_data_count(4) <= \\; axi_b_data_count(3) <= \\; axi_b_data_count(2) <= \\; axi_b_data_count(1) <= \\; axi_b_data_count(0) <= \\; axi_b_dbiterr <= \\; axi_b_overflow <= \\; axi_b_prog_empty <= \\; axi_b_prog_full <= \\; axi_b_rd_data_count(4) <= \\; axi_b_rd_data_count(3) <= \\; axi_b_rd_data_count(2) <= \\; axi_b_rd_data_count(1) <= \\; axi_b_rd_data_count(0) <= \\; axi_b_sbiterr <= \\; axi_b_underflow <= \\; axi_b_wr_data_count(4) <= \\; axi_b_wr_data_count(3) <= \\; axi_b_wr_data_count(2) <= \\; axi_b_wr_data_count(1) <= \\; axi_b_wr_data_count(0) <= \\; axi_r_data_count(10) <= \\; axi_r_data_count(9) <= \\; axi_r_data_count(8) <= \\; axi_r_data_count(7) <= \\; axi_r_data_count(6) <= \\; axi_r_data_count(5) <= \\; axi_r_data_count(4) <= \\; axi_r_data_count(3) <= \\; axi_r_data_count(2) <= \\; axi_r_data_count(1) <= \\; axi_r_data_count(0) <= \\; axi_r_dbiterr <= \\; axi_r_overflow <= \\; axi_r_prog_empty <= \\; axi_r_prog_full <= \\; axi_r_rd_data_count(10) <= \\; axi_r_rd_data_count(9) <= \\; axi_r_rd_data_count(8) <= \\; axi_r_rd_data_count(7) <= \\; axi_r_rd_data_count(6) <= \\; axi_r_rd_data_count(5) <= \\; axi_r_rd_data_count(4) <= \\; axi_r_rd_data_count(3) <= \\; axi_r_rd_data_count(2) <= \\; axi_r_rd_data_count(1) <= \\; axi_r_rd_data_count(0) <= \\; axi_r_sbiterr <= \\; axi_r_underflow <= \\; axi_r_wr_data_count(10) <= \\; axi_r_wr_data_count(9) <= \\; axi_r_wr_data_count(8) <= \\; axi_r_wr_data_count(7) <= \\; axi_r_wr_data_count(6) <= \\; axi_r_wr_data_count(5) <= \\; axi_r_wr_data_count(4) <= \\; axi_r_wr_data_count(3) <= \\; axi_r_wr_data_count(2) <= \\; axi_r_wr_data_count(1) <= \\; axi_r_wr_data_count(0) <= \\; axi_w_data_count(10) <= \\; axi_w_data_count(9) <= \\; axi_w_data_count(8) <= \\; axi_w_data_count(7) <= \\; axi_w_data_count(6) <= \\; axi_w_data_count(5) <= \\; axi_w_data_count(4) <= \\; axi_w_data_count(3) <= \\; axi_w_data_count(2) <= \\; axi_w_data_count(1) <= \\; axi_w_data_count(0) <= \\; axi_w_dbiterr <= \\; axi_w_overflow <= \\; axi_w_prog_empty <= \\; axi_w_prog_full <= \\; axi_w_rd_data_count(10) <= \\; axi_w_rd_data_count(9) <= \\; axi_w_rd_data_count(8) <= \\; axi_w_rd_data_count(7) <= \\; axi_w_rd_data_count(6) <= \\; axi_w_rd_data_count(5) <= \\; axi_w_rd_data_count(4) <= \\; axi_w_rd_data_count(3) <= \\; axi_w_rd_data_count(2) <= \\; axi_w_rd_data_count(1) <= \\; axi_w_rd_data_count(0) <= \\; axi_w_sbiterr <= \\; axi_w_underflow <= \\; axi_w_wr_data_count(10) <= \\; axi_w_wr_data_count(9) <= \\; axi_w_wr_data_count(8) <= \\; axi_w_wr_data_count(7) <= \\; axi_w_wr_data_count(6) <= \\; axi_w_wr_data_count(5) <= \\; axi_w_wr_data_count(4) <= \\; axi_w_wr_data_count(3) <= \\; axi_w_wr_data_count(2) <= \\; axi_w_wr_data_count(1) <= \\; axi_w_wr_data_count(0) <= \\; axis_data_count(10) <= \\; axis_data_count(9) <= \\; axis_data_count(8) <= \\; axis_data_count(7) <= \\; axis_data_count(6) <= \\; axis_data_count(5) <= \\; axis_data_count(4) <= \\; axis_data_count(3) <= \\; axis_data_count(2) <= \\; axis_data_count(1) <= \\; axis_data_count(0) <= \\; axis_dbiterr <= \\; axis_overflow <= \\; axis_prog_empty <= \\; axis_prog_full <= \\; axis_rd_data_count(10) <= \\; axis_rd_data_count(9) <= \\; axis_rd_data_count(8) <= \\; axis_rd_data_count(7) <= \\; axis_rd_data_count(6) <= \\; axis_rd_data_count(5) <= \\; axis_rd_data_count(4) <= \\; axis_rd_data_count(3) <= \\; axis_rd_data_count(2) <= \\; axis_rd_data_count(1) <= \\; axis_rd_data_count(0) <= \\; axis_sbiterr <= \\; axis_underflow <= \\; axis_wr_data_count(10) <= \\; axis_wr_data_count(9) <= \\; axis_wr_data_count(8) <= \\; axis_wr_data_count(7) <= \\; axis_wr_data_count(6) <= \\; axis_wr_data_count(5) <= \\; axis_wr_data_count(4) <= \\; axis_wr_data_count(3) <= \\; axis_wr_data_count(2) <= \\; axis_wr_data_count(1) <= \\; axis_wr_data_count(0) <= \\; data_count(4) <= \\; data_count(3) <= \\; data_count(2) <= \\; data_count(1) <= \\; data_count(0) <= \\; dbiterr <= \\; m_axi_araddr(31) <= \\; m_axi_araddr(30) <= \\; m_axi_araddr(29) <= \\; m_axi_araddr(28) <= \\; m_axi_araddr(27) <= \\; m_axi_araddr(26) <= \\; m_axi_araddr(25) <= \\; m_axi_araddr(24) <= \\; m_axi_araddr(23) <= \\; m_axi_araddr(22) <= \\; m_axi_araddr(21) <= \\; m_axi_araddr(20) <= \\; m_axi_araddr(19) <= \\; m_axi_araddr(18) <= \\; m_axi_araddr(17) <= \\; m_axi_araddr(16) <= \\; m_axi_araddr(15) <= \\; m_axi_araddr(14) <= \\; m_axi_araddr(13) <= \\; m_axi_araddr(12) <= \\; m_axi_araddr(11) <= \\; m_axi_araddr(10) <= \\; m_axi_araddr(9) <= \\; m_axi_araddr(8) <= \\; m_axi_araddr(7) <= \\; m_axi_araddr(6) <= \\; m_axi_araddr(5) <= \\; m_axi_araddr(4) <= \\; m_axi_araddr(3) <= \\; m_axi_araddr(2) <= \\; m_axi_araddr(1) <= \\; m_axi_araddr(0) <= \\; m_axi_arburst(1) <= \\; m_axi_arburst(0) <= \\; m_axi_arcache(3) <= \\; m_axi_arcache(2) <= \\; m_axi_arcache(1) <= \\; m_axi_arcache(0) <= \\; m_axi_arid(0) <= \\; m_axi_arlen(7) <= \\; m_axi_arlen(6) <= \\; m_axi_arlen(5) <= \\; m_axi_arlen(4) <= \\; m_axi_arlen(3) <= \\; m_axi_arlen(2) <= \\; m_axi_arlen(1) <= \\; m_axi_arlen(0) <= \\; m_axi_arlock(0) <= \\; m_axi_arprot(2) <= \\; m_axi_arprot(1) <= \\; m_axi_arprot(0) <= \\; m_axi_arqos(3) <= \\; m_axi_arqos(2) <= \\; m_axi_arqos(1) <= \\; m_axi_arqos(0) <= \\; m_axi_arregion(3) <= \\; m_axi_arregion(2) <= \\; m_axi_arregion(1) <= \\; m_axi_arregion(0) <= \\; m_axi_arsize(2) <= \\; m_axi_arsize(1) <= \\; m_axi_arsize(0) <= \\; m_axi_aruser(0) <= \\; m_axi_arvalid <= \\; m_axi_awaddr(31) <= \\; m_axi_awaddr(30) <= \\; m_axi_awaddr(29) <= \\; m_axi_awaddr(28) <= \\; m_axi_awaddr(27) <= \\; m_axi_awaddr(26) <= \\; m_axi_awaddr(25) <= \\; m_axi_awaddr(24) <= \\; m_axi_awaddr(23) <= \\; m_axi_awaddr(22) <= \\; m_axi_awaddr(21) <= \\; m_axi_awaddr(20) <= \\; m_axi_awaddr(19) <= \\; m_axi_awaddr(18) <= \\; m_axi_awaddr(17) <= \\; m_axi_awaddr(16) <= \\; m_axi_awaddr(15) <= \\; m_axi_awaddr(14) <= \\; m_axi_awaddr(13) <= \\; m_axi_awaddr(12) <= \\; m_axi_awaddr(11) <= \\; m_axi_awaddr(10) <= \\; m_axi_awaddr(9) <= \\; m_axi_awaddr(8) <= \\; m_axi_awaddr(7) <= \\; m_axi_awaddr(6) <= \\; m_axi_awaddr(5) <= \\; m_axi_awaddr(4) <= \\; m_axi_awaddr(3) <= \\; m_axi_awaddr(2) <= \\; m_axi_awaddr(1) <= \\; m_axi_awaddr(0) <= \\; m_axi_awburst(1) <= \\; m_axi_awburst(0) <= \\; m_axi_awcache(3) <= \\; m_axi_awcache(2) <= \\; m_axi_awcache(1) <= \\; m_axi_awcache(0) <= \\; m_axi_awid(0) <= \\; m_axi_awlen(7) <= \\; m_axi_awlen(6) <= \\; m_axi_awlen(5) <= \\; m_axi_awlen(4) <= \\; m_axi_awlen(3) <= \\; m_axi_awlen(2) <= \\; m_axi_awlen(1) <= \\; m_axi_awlen(0) <= \\; m_axi_awlock(0) <= \\; m_axi_awprot(2) <= \\; m_axi_awprot(1) <= \\; m_axi_awprot(0) <= \\; m_axi_awqos(3) <= \\; m_axi_awqos(2) <= \\; m_axi_awqos(1) <= \\; m_axi_awqos(0) <= \\; m_axi_awregion(3) <= \\; m_axi_awregion(2) <= \\; m_axi_awregion(1) <= \\; m_axi_awregion(0) <= \\; m_axi_awsize(2) <= \\; m_axi_awsize(1) <= \\; m_axi_awsize(0) <= \\; m_axi_awuser(0) <= \\; m_axi_awvalid <= \\; m_axi_bready <= \\; m_axi_rready <= \\; m_axi_wdata(63) <= \\; m_axi_wdata(62) <= \\; m_axi_wdata(61) <= \\; m_axi_wdata(60) <= \\; m_axi_wdata(59) <= \\; m_axi_wdata(58) <= \\; m_axi_wdata(57) <= \\; m_axi_wdata(56) <= \\; m_axi_wdata(55) <= \\; m_axi_wdata(54) <= \\; m_axi_wdata(53) <= \\; m_axi_wdata(52) <= \\; m_axi_wdata(51) <= \\; m_axi_wdata(50) <= \\; m_axi_wdata(49) <= \\; m_axi_wdata(48) <= \\; m_axi_wdata(47) <= \\; m_axi_wdata(46) <= \\; m_axi_wdata(45) <= \\; m_axi_wdata(44) <= \\; m_axi_wdata(43) <= \\; m_axi_wdata(42) <= \\; m_axi_wdata(41) <= \\; m_axi_wdata(40) <= \\; m_axi_wdata(39) <= \\; m_axi_wdata(38) <= \\; m_axi_wdata(37) <= \\; m_axi_wdata(36) <= \\; m_axi_wdata(35) <= \\; m_axi_wdata(34) <= \\; m_axi_wdata(33) <= \\; m_axi_wdata(32) <= \\; m_axi_wdata(31) <= \\; m_axi_wdata(30) <= \\; m_axi_wdata(29) <= \\; m_axi_wdata(28) <= \\; m_axi_wdata(27) <= \\; m_axi_wdata(26) <= \\; m_axi_wdata(25) <= \\; m_axi_wdata(24) <= \\; m_axi_wdata(23) <= \\; m_axi_wdata(22) <= \\; m_axi_wdata(21) <= \\; m_axi_wdata(20) <= \\; m_axi_wdata(19) <= \\; m_axi_wdata(18) <= \\; m_axi_wdata(17) <= \\; m_axi_wdata(16) <= \\; m_axi_wdata(15) <= \\; m_axi_wdata(14) <= \\; m_axi_wdata(13) <= \\; m_axi_wdata(12) <= \\; m_axi_wdata(11) <= \\; m_axi_wdata(10) <= \\; m_axi_wdata(9) <= \\; m_axi_wdata(8) <= \\; m_axi_wdata(7) <= \\; m_axi_wdata(6) <= \\; m_axi_wdata(5) <= \\; m_axi_wdata(4) <= \\; m_axi_wdata(3) <= \\; m_axi_wdata(2) <= \\; m_axi_wdata(1) <= \\; m_axi_wdata(0) <= \\; m_axi_wid(0) <= \\; m_axi_wlast <= \\; m_axi_wstrb(7) <= \\; m_axi_wstrb(6) <= \\; m_axi_wstrb(5) <= \\; m_axi_wstrb(4) <= \\; m_axi_wstrb(3) <= \\; m_axi_wstrb(2) <= \\; m_axi_wstrb(1) <= \\; m_axi_wstrb(0) <= \\; m_axi_wuser(0) <= \\; m_axi_wvalid <= \\; m_axis_tdata(7) <= \\; m_axis_tdata(6) <= \\; m_axis_tdata(5) <= \\; m_axis_tdata(4) <= \\; m_axis_tdata(3) <= \\; m_axis_tdata(2) <= \\; m_axis_tdata(1) <= \\; m_axis_tdata(0) <= \\; m_axis_tdest(0) <= \\; m_axis_tid(0) <= \\; m_axis_tkeep(0) <= \\; m_axis_tlast <= \\; m_axis_tstrb(0) <= \\; m_axis_tuser(3) <= \\; m_axis_tuser(2) <= \\; m_axis_tuser(1) <= \\; m_axis_tuser(0) <= \\; m_axis_tvalid <= \\; overflow <= \\; prog_empty <= \\; rd_data_count(4) <= \\; rd_data_count(3) <= \\; rd_data_count(2) <= \\; rd_data_count(1) <= \\; rd_data_count(0) <= \\; s_axi_arready <= \\; s_axi_awready <= \\; s_axi_bid(0) <= \\; s_axi_bresp(1) <= \\; s_axi_bresp(0) <= \\; s_axi_buser(0) <= \\; s_axi_bvalid <= \\; s_axi_rdata(63) <= \\; s_axi_rdata(62) <= \\; s_axi_rdata(61) <= \\; s_axi_rdata(60) <= \\; s_axi_rdata(59) <= \\; s_axi_rdata(58) <= \\; s_axi_rdata(57) <= \\; s_axi_rdata(56) <= \\; s_axi_rdata(55) <= \\; s_axi_rdata(54) <= \\; s_axi_rdata(53) <= \\; s_axi_rdata(52) <= \\; s_axi_rdata(51) <= \\; s_axi_rdata(50) <= \\; s_axi_rdata(49) <= \\; s_axi_rdata(48) <= \\; s_axi_rdata(47) <= \\; s_axi_rdata(46) <= \\; s_axi_rdata(45) <= \\; s_axi_rdata(44) <= \\; s_axi_rdata(43) <= \\; s_axi_rdata(42) <= \\; s_axi_rdata(41) <= \\; s_axi_rdata(40) <= \\; s_axi_rdata(39) <= \\; s_axi_rdata(38) <= \\; s_axi_rdata(37) <= \\; s_axi_rdata(36) <= \\; s_axi_rdata(35) <= \\; s_axi_rdata(34) <= \\; s_axi_rdata(33) <= \\; s_axi_rdata(32) <= \\; s_axi_rdata(31) <= \\; s_axi_rdata(30) <= \\; s_axi_rdata(29) <= \\; s_axi_rdata(28) <= \\; s_axi_rdata(27) <= \\; s_axi_rdata(26) <= \\; s_axi_rdata(25) <= \\; s_axi_rdata(24) <= \\; s_axi_rdata(23) <= \\; s_axi_rdata(22) <= \\; s_axi_rdata(21) <= \\; s_axi_rdata(20) <= \\; s_axi_rdata(19) <= \\; s_axi_rdata(18) <= \\; s_axi_rdata(17) <= \\; s_axi_rdata(16) <= \\; s_axi_rdata(15) <= \\; s_axi_rdata(14) <= \\; s_axi_rdata(13) <= \\; s_axi_rdata(12) <= \\; s_axi_rdata(11) <= \\; s_axi_rdata(10) <= \\; s_axi_rdata(9) <= \\; s_axi_rdata(8) <= \\; s_axi_rdata(7) <= \\; s_axi_rdata(6) <= \\; s_axi_rdata(5) <= \\; s_axi_rdata(4) <= \\; s_axi_rdata(3) <= \\; s_axi_rdata(2) <= \\; s_axi_rdata(1) <= \\; s_axi_rdata(0) <= \\; s_axi_rid(0) <= \\; s_axi_rlast <= \\; s_axi_rresp(1) <= \\; s_axi_rresp(0) <= \\; s_axi_ruser(0) <= \\; s_axi_rvalid <= \\; s_axi_wready <= \\; s_axis_tready <= \\; sbiterr <= \\; underflow <= \\; valid <= \\; wr_ack <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); VCC: unisim.vcomponents.VCC port map ( P => \\ ); inst_fifo_gen: entity work.fifo1KB_34bit_fifo_generator_v13_2_5_synth port map ( AR(0) => rd_rst_busy, din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), empty => empty, full => full, prog_full => prog_full, rd_clk => rd_clk, rd_en => rd_en, rst => rst, wr_clk => wr_clk, wr_data_count(4 downto 0) => wr_data_count(4 downto 0), wr_en => wr_en, wr_rst_busy => wr_rst_busy ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity fifo1KB_34bit is port ( rst : in STD_LOGIC; wr_clk : in STD_LOGIC; rd_clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 33 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); full : out STD_LOGIC; empty : out STD_LOGIC; wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); prog_full : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of fifo1KB_34bit : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of fifo1KB_34bit : entity is "fifo1KB_34bit,fifo_generator_v13_2_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of fifo1KB_34bit : entity is "yes"; attribute x_core_info : string; attribute x_core_info of fifo1KB_34bit : entity is "fifo_generator_v13_2_5,Vivado 2019.2"; end fifo1KB_34bit; architecture STRUCTURE of fifo1KB_34bit is signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_valid_UNCONNECTED : STD_LOGIC; signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC; signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_ADD_NGC_CONSTRAINT : integer; attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0; attribute C_APPLICATION_TYPE_AXIS : integer; attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0; attribute C_APPLICATION_TYPE_RACH : integer; attribute C_APPLICATION_TYPE_RACH of U0 : label is 0; attribute C_APPLICATION_TYPE_RDCH : integer; attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0; attribute C_APPLICATION_TYPE_WACH : integer; attribute C_APPLICATION_TYPE_WACH of U0 : label is 0; attribute C_APPLICATION_TYPE_WDCH : integer; attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0; attribute C_APPLICATION_TYPE_WRCH : integer; attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0; attribute C_AXIS_TDATA_WIDTH : integer; attribute C_AXIS_TDATA_WIDTH of U0 : label is 8; attribute C_AXIS_TDEST_WIDTH : integer; attribute C_AXIS_TDEST_WIDTH of U0 : label is 1; attribute C_AXIS_TID_WIDTH : integer; attribute C_AXIS_TID_WIDTH of U0 : label is 1; attribute C_AXIS_TKEEP_WIDTH : integer; attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1; attribute C_AXIS_TSTRB_WIDTH : integer; attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1; attribute C_AXIS_TUSER_WIDTH : integer; attribute C_AXIS_TUSER_WIDTH of U0 : label is 4; attribute C_AXIS_TYPE : integer; attribute C_AXIS_TYPE of U0 : label is 0; attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of U0 : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of U0 : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of U0 : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of U0 : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of U0 : label is 64; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 1; attribute C_AXI_LEN_WIDTH : integer; attribute C_AXI_LEN_WIDTH of U0 : label is 8; attribute C_AXI_LOCK_WIDTH : integer; attribute C_AXI_LOCK_WIDTH of U0 : label is 1; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of U0 : label is 1; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of U0 : label is 1; attribute C_COMMON_CLOCK : integer; attribute C_COMMON_CLOCK of U0 : label is 0; attribute C_COUNT_TYPE : integer; attribute C_COUNT_TYPE of U0 : label is 0; attribute C_DATA_COUNT_WIDTH : integer; attribute C_DATA_COUNT_WIDTH of U0 : label is 5; attribute C_DEFAULT_VALUE : string; attribute C_DEFAULT_VALUE of U0 : label is "BlankString"; attribute C_DIN_WIDTH : integer; attribute C_DIN_WIDTH of U0 : label is 34; attribute C_DIN_WIDTH_AXIS : integer; attribute C_DIN_WIDTH_AXIS of U0 : label is 1; attribute C_DIN_WIDTH_RACH : integer; attribute C_DIN_WIDTH_RACH of U0 : label is 32; attribute C_DIN_WIDTH_RDCH : integer; attribute C_DIN_WIDTH_RDCH of U0 : label is 64; attribute C_DIN_WIDTH_WACH : integer; attribute C_DIN_WIDTH_WACH of U0 : label is 1; attribute C_DIN_WIDTH_WDCH : integer; attribute C_DIN_WIDTH_WDCH of U0 : label is 64; attribute C_DIN_WIDTH_WRCH : integer; attribute C_DIN_WIDTH_WRCH of U0 : label is 2; attribute C_DOUT_RST_VAL : string; attribute C_DOUT_RST_VAL of U0 : label is "0"; attribute C_DOUT_WIDTH : integer; attribute C_DOUT_WIDTH of U0 : label is 34; attribute C_ENABLE_RLOCS : integer; attribute C_ENABLE_RLOCS of U0 : label is 0; attribute C_ENABLE_RST_SYNC : integer; attribute C_ENABLE_RST_SYNC of U0 : label is 1; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE : integer; attribute C_ERROR_INJECTION_TYPE of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_AXIS : integer; attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_RACH : integer; attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_RDCH : integer; attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WACH : integer; attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WDCH : integer; attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WRCH : integer; attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "virtex7"; attribute C_FULL_FLAGS_RST_VAL : integer; attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1; attribute C_HAS_ALMOST_EMPTY : integer; attribute C_HAS_ALMOST_EMPTY of U0 : label is 0; attribute C_HAS_ALMOST_FULL : integer; attribute C_HAS_ALMOST_FULL of U0 : label is 0; attribute C_HAS_AXIS_TDATA : integer; attribute C_HAS_AXIS_TDATA of U0 : label is 1; attribute C_HAS_AXIS_TDEST : integer; attribute C_HAS_AXIS_TDEST of U0 : label is 0; attribute C_HAS_AXIS_TID : integer; attribute C_HAS_AXIS_TID of U0 : label is 0; attribute C_HAS_AXIS_TKEEP : integer; attribute C_HAS_AXIS_TKEEP of U0 : label is 0; attribute C_HAS_AXIS_TLAST : integer; attribute C_HAS_AXIS_TLAST of U0 : label is 0; attribute C_HAS_AXIS_TREADY : integer; attribute C_HAS_AXIS_TREADY of U0 : label is 1; attribute C_HAS_AXIS_TSTRB : integer; attribute C_HAS_AXIS_TSTRB of U0 : label is 0; attribute C_HAS_AXIS_TUSER : integer; attribute C_HAS_AXIS_TUSER of U0 : label is 1; attribute C_HAS_AXI_ARUSER : integer; attribute C_HAS_AXI_ARUSER of U0 : label is 0; attribute C_HAS_AXI_AWUSER : integer; attribute C_HAS_AXI_AWUSER of U0 : label is 0; attribute C_HAS_AXI_BUSER : integer; attribute C_HAS_AXI_BUSER of U0 : label is 0; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_AXI_RD_CHANNEL : integer; attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1; attribute C_HAS_AXI_RUSER : integer; attribute C_HAS_AXI_RUSER of U0 : label is 0; attribute C_HAS_AXI_WR_CHANNEL : integer; attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1; attribute C_HAS_AXI_WUSER : integer; attribute C_HAS_AXI_WUSER of U0 : label is 0; attribute C_HAS_BACKUP : integer; attribute C_HAS_BACKUP of U0 : label is 0; attribute C_HAS_DATA_COUNT : integer; attribute C_HAS_DATA_COUNT of U0 : label is 0; attribute C_HAS_DATA_COUNTS_AXIS : integer; attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0; attribute C_HAS_DATA_COUNTS_RACH : integer; attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_RDCH : integer; attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WACH : integer; attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WDCH : integer; attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WRCH : integer; attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0; attribute C_HAS_INT_CLK : integer; attribute C_HAS_INT_CLK of U0 : label is 0; attribute C_HAS_MASTER_CE : integer; attribute C_HAS_MASTER_CE of U0 : label is 0; attribute C_HAS_MEMINIT_FILE : integer; attribute C_HAS_MEMINIT_FILE of U0 : label is 0; attribute C_HAS_OVERFLOW : integer; attribute C_HAS_OVERFLOW of U0 : label is 0; attribute C_HAS_PROG_FLAGS_AXIS : integer; attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0; attribute C_HAS_PROG_FLAGS_RACH : integer; attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_RDCH : integer; attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WACH : integer; attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WDCH : integer; attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WRCH : integer; attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0; attribute C_HAS_RD_DATA_COUNT : integer; attribute C_HAS_RD_DATA_COUNT of U0 : label is 0; attribute C_HAS_RD_RST : integer; attribute C_HAS_RD_RST of U0 : label is 0; attribute C_HAS_RST : integer; attribute C_HAS_RST of U0 : label is 1; attribute C_HAS_SLAVE_CE : integer; attribute C_HAS_SLAVE_CE of U0 : label is 0; attribute C_HAS_SRST : integer; attribute C_HAS_SRST of U0 : label is 0; attribute C_HAS_UNDERFLOW : integer; attribute C_HAS_UNDERFLOW of U0 : label is 0; attribute C_HAS_VALID : integer; attribute C_HAS_VALID of U0 : label is 0; attribute C_HAS_WR_ACK : integer; attribute C_HAS_WR_ACK of U0 : label is 0; attribute C_HAS_WR_DATA_COUNT : integer; attribute C_HAS_WR_DATA_COUNT of U0 : label is 1; attribute C_HAS_WR_RST : integer; attribute C_HAS_WR_RST of U0 : label is 0; attribute C_IMPLEMENTATION_TYPE : integer; attribute C_IMPLEMENTATION_TYPE of U0 : label is 2; attribute C_IMPLEMENTATION_TYPE_AXIS : integer; attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_RACH : integer; attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_RDCH : integer; attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WACH : integer; attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WDCH : integer; attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WRCH : integer; attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1; attribute C_INIT_WR_PNTR_VAL : integer; attribute C_INIT_WR_PNTR_VAL of U0 : label is 0; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_MEMORY_TYPE : integer; attribute C_MEMORY_TYPE of U0 : label is 1; attribute C_MIF_FILE_NAME : string; attribute C_MIF_FILE_NAME of U0 : label is "BlankString"; attribute C_MSGON_VAL : integer; attribute C_MSGON_VAL of U0 : label is 1; attribute C_OPTIMIZATION_MODE : integer; attribute C_OPTIMIZATION_MODE of U0 : label is 0; attribute C_OVERFLOW_LOW : integer; attribute C_OVERFLOW_LOW of U0 : label is 0; attribute C_POWER_SAVING_MODE : integer; attribute C_POWER_SAVING_MODE of U0 : label is 0; attribute C_PRELOAD_LATENCY : integer; attribute C_PRELOAD_LATENCY of U0 : label is 1; attribute C_PRELOAD_REGS : integer; attribute C_PRELOAD_REGS of U0 : label is 0; attribute C_PRIM_FIFO_TYPE : string; attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36"; attribute C_PRIM_FIFO_TYPE_AXIS : string; attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18"; attribute C_PRIM_FIFO_TYPE_RACH : string; attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36"; attribute C_PRIM_FIFO_TYPE_RDCH : string; attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36"; attribute C_PRIM_FIFO_TYPE_WACH : string; attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36"; attribute C_PRIM_FIFO_TYPE_WDCH : string; attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36"; attribute C_PRIM_FIFO_TYPE_WRCH : string; attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36"; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3; attribute C_PROG_EMPTY_TYPE : integer; attribute C_PROG_EMPTY_TYPE of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_AXIS : integer; attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_RACH : integer; attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_RDCH : integer; attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WACH : integer; attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WDCH : integer; attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WRCH : integer; attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0; attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 27; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 26; attribute C_PROG_FULL_TYPE : integer; attribute C_PROG_FULL_TYPE of U0 : label is 1; attribute C_PROG_FULL_TYPE_AXIS : integer; attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0; attribute C_PROG_FULL_TYPE_RACH : integer; attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0; attribute C_PROG_FULL_TYPE_RDCH : integer; attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WACH : integer; attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WDCH : integer; attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WRCH : integer; attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0; attribute C_RACH_TYPE : integer; attribute C_RACH_TYPE of U0 : label is 0; attribute C_RDCH_TYPE : integer; attribute C_RDCH_TYPE of U0 : label is 0; attribute C_RD_DATA_COUNT_WIDTH : integer; attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 5; attribute C_RD_DEPTH : integer; attribute C_RD_DEPTH of U0 : label is 32; attribute C_RD_FREQ : integer; attribute C_RD_FREQ of U0 : label is 1; attribute C_RD_PNTR_WIDTH : integer; attribute C_RD_PNTR_WIDTH of U0 : label is 5; attribute C_REG_SLICE_MODE_AXIS : integer; attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0; attribute C_REG_SLICE_MODE_RACH : integer; attribute C_REG_SLICE_MODE_RACH of U0 : label is 0; attribute C_REG_SLICE_MODE_RDCH : integer; attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0; attribute C_REG_SLICE_MODE_WACH : integer; attribute C_REG_SLICE_MODE_WACH of U0 : label is 0; attribute C_REG_SLICE_MODE_WDCH : integer; attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0; attribute C_REG_SLICE_MODE_WRCH : integer; attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of U0 : label is 0; attribute C_SYNCHRONIZER_STAGE : integer; attribute C_SYNCHRONIZER_STAGE of U0 : label is 2; attribute C_UNDERFLOW_LOW : integer; attribute C_UNDERFLOW_LOW of U0 : label is 0; attribute C_USE_COMMON_OVERFLOW : integer; attribute C_USE_COMMON_OVERFLOW of U0 : label is 0; attribute C_USE_COMMON_UNDERFLOW : integer; attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0; attribute C_USE_DEFAULT_SETTINGS : integer; attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0; attribute C_USE_DOUT_RST : integer; attribute C_USE_DOUT_RST of U0 : label is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_ECC_AXIS : integer; attribute C_USE_ECC_AXIS of U0 : label is 0; attribute C_USE_ECC_RACH : integer; attribute C_USE_ECC_RACH of U0 : label is 0; attribute C_USE_ECC_RDCH : integer; attribute C_USE_ECC_RDCH of U0 : label is 0; attribute C_USE_ECC_WACH : integer; attribute C_USE_ECC_WACH of U0 : label is 0; attribute C_USE_ECC_WDCH : integer; attribute C_USE_ECC_WDCH of U0 : label is 0; attribute C_USE_ECC_WRCH : integer; attribute C_USE_ECC_WRCH of U0 : label is 0; attribute C_USE_EMBEDDED_REG : integer; attribute C_USE_EMBEDDED_REG of U0 : label is 0; attribute C_USE_FIFO16_FLAGS : integer; attribute C_USE_FIFO16_FLAGS of U0 : label is 0; attribute C_USE_FWFT_DATA_COUNT : integer; attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0; attribute C_USE_PIPELINE_REG : integer; attribute C_USE_PIPELINE_REG of U0 : label is 0; attribute C_VALID_LOW : integer; attribute C_VALID_LOW of U0 : label is 0; attribute C_WACH_TYPE : integer; attribute C_WACH_TYPE of U0 : label is 0; attribute C_WDCH_TYPE : integer; attribute C_WDCH_TYPE of U0 : label is 0; attribute C_WRCH_TYPE : integer; attribute C_WRCH_TYPE of U0 : label is 0; attribute C_WR_ACK_LOW : integer; attribute C_WR_ACK_LOW of U0 : label is 0; attribute C_WR_DATA_COUNT_WIDTH : integer; attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 5; attribute C_WR_DEPTH : integer; attribute C_WR_DEPTH of U0 : label is 32; attribute C_WR_DEPTH_AXIS : integer; attribute C_WR_DEPTH_AXIS of U0 : label is 1024; attribute C_WR_DEPTH_RACH : integer; attribute C_WR_DEPTH_RACH of U0 : label is 16; attribute C_WR_DEPTH_RDCH : integer; attribute C_WR_DEPTH_RDCH of U0 : label is 1024; attribute C_WR_DEPTH_WACH : integer; attribute C_WR_DEPTH_WACH of U0 : label is 16; attribute C_WR_DEPTH_WDCH : integer; attribute C_WR_DEPTH_WDCH of U0 : label is 1024; attribute C_WR_DEPTH_WRCH : integer; attribute C_WR_DEPTH_WRCH of U0 : label is 16; attribute C_WR_FREQ : integer; attribute C_WR_FREQ of U0 : label is 1; attribute C_WR_PNTR_WIDTH : integer; attribute C_WR_PNTR_WIDTH of U0 : label is 5; attribute C_WR_PNTR_WIDTH_AXIS : integer; attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10; attribute C_WR_PNTR_WIDTH_RACH : integer; attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4; attribute C_WR_PNTR_WIDTH_RDCH : integer; attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10; attribute C_WR_PNTR_WIDTH_WACH : integer; attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4; attribute C_WR_PNTR_WIDTH_WDCH : integer; attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10; attribute C_WR_PNTR_WIDTH_WRCH : integer; attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of empty : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; attribute x_interface_info of full : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; attribute x_interface_info of rd_clk : signal is "xilinx.com:signal:clock:1.0 read_clk CLK"; attribute x_interface_parameter : string; attribute x_interface_parameter of rd_clk : signal is "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; attribute x_interface_info of rd_en : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; attribute x_interface_info of wr_clk : signal is "xilinx.com:signal:clock:1.0 write_clk CLK"; attribute x_interface_parameter of wr_clk : signal is "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0"; attribute x_interface_info of wr_en : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; attribute x_interface_info of din : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; attribute x_interface_info of dout : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; begin U0: entity work.fifo1KB_34bit_fifo_generator_v13_2_5 port map ( almost_empty => NLW_U0_almost_empty_UNCONNECTED, almost_full => NLW_U0_almost_full_UNCONNECTED, axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0), axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED, axi_ar_injectdbiterr => '0', axi_ar_injectsbiterr => '0', axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED, axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED, axi_ar_prog_empty_thresh(3 downto 0) => B"0000", axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED, axi_ar_prog_full_thresh(3 downto 0) => B"0000", axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED, axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED, axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0), axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED, axi_aw_injectdbiterr => '0', axi_aw_injectsbiterr => '0', axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED, axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED, axi_aw_prog_empty_thresh(3 downto 0) => B"0000", axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED, axi_aw_prog_full_thresh(3 downto 0) => B"0000", axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED, axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED, axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0), axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED, axi_b_injectdbiterr => '0', axi_b_injectsbiterr => '0', axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED, axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED, axi_b_prog_empty_thresh(3 downto 0) => B"0000", axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED, axi_b_prog_full_thresh(3 downto 0) => B"0000", axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0), axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED, axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED, axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0), axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0), axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED, axi_r_injectdbiterr => '0', axi_r_injectsbiterr => '0', axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED, axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED, axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED, axi_r_prog_full_thresh(9 downto 0) => B"0000000000", axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0), axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED, axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED, axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0), axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0), axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED, axi_w_injectdbiterr => '0', axi_w_injectsbiterr => '0', axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED, axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED, axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED, axi_w_prog_full_thresh(9 downto 0) => B"0000000000", axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0), axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED, axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED, axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0), axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0), axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED, axis_injectdbiterr => '0', axis_injectsbiterr => '0', axis_overflow => NLW_U0_axis_overflow_UNCONNECTED, axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED, axis_prog_empty_thresh(9 downto 0) => B"0000000000", axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED, axis_prog_full_thresh(9 downto 0) => B"0000000000", axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0), axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED, axis_underflow => NLW_U0_axis_underflow_UNCONNECTED, axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0), backup => '0', backup_marker => '0', clk => '0', data_count(4 downto 0) => NLW_U0_data_count_UNCONNECTED(4 downto 0), dbiterr => NLW_U0_dbiterr_UNCONNECTED, din(33 downto 0) => din(33 downto 0), dout(33 downto 0) => dout(33 downto 0), empty => empty, full => full, injectdbiterr => '0', injectsbiterr => '0', int_clk => '0', m_aclk => '0', m_aclk_en => '0', m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0), m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0), m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => '0', m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED, m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0), m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0), m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => '0', m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED, m_axi_bid(0) => '0', m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED, m_axi_bresp(1 downto 0) => B"00", m_axi_buser(0) => '0', m_axi_bvalid => '0', m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", m_axi_rid(0) => '0', m_axi_rlast => '0', m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED, m_axi_rresp(1 downto 0) => B"00", m_axi_ruser(0) => '0', m_axi_rvalid => '0', m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0), m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0), m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED, m_axi_wready => '0', m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0), m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED, m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0), m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0), m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0), m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0), m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED, m_axis_tready => '0', m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0), m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0), m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED, overflow => NLW_U0_overflow_UNCONNECTED, prog_empty => NLW_U0_prog_empty_UNCONNECTED, prog_empty_thresh(4 downto 0) => B"00000", prog_empty_thresh_assert(4 downto 0) => B"00000", prog_empty_thresh_negate(4 downto 0) => B"00000", prog_full => prog_full, prog_full_thresh(4 downto 0) => B"00000", prog_full_thresh_assert(4 downto 0) => B"00000", prog_full_thresh_negate(4 downto 0) => B"00000", rd_clk => rd_clk, rd_data_count(4 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(4 downto 0), rd_en => rd_en, rd_rst => '0', rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED, rst => rst, s_aclk => '0', s_aclk_en => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arcache(3 downto 0) => B"0000", s_axi_arid(0) => '0', s_axi_arlen(7 downto 0) => B"00000000", s_axi_arlock(0) => '0', s_axi_arprot(2 downto 0) => B"000", s_axi_arqos(3 downto 0) => B"0000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => B"000", s_axi_aruser(0) => '0', s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awcache(3 downto 0) => B"0000", s_axi_awid(0) => '0', s_axi_awlen(7 downto 0) => B"00000000", s_axi_awlock(0) => '0', s_axi_awprot(2 downto 0) => B"000", s_axi_awqos(3 downto 0) => B"0000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => B"000", s_axi_awuser(0) => '0', s_axi_awvalid => '0', s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0), s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", s_axi_wid(0) => '0', s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(7 downto 0) => B"00000000", s_axi_wuser(0) => '0', s_axi_wvalid => '0', s_axis_tdata(7 downto 0) => B"00000000", s_axis_tdest(0) => '0', s_axis_tid(0) => '0', s_axis_tkeep(0) => '0', s_axis_tlast => '0', s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED, s_axis_tstrb(0) => '0', s_axis_tuser(3 downto 0) => B"0000", s_axis_tvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, sleep => '0', srst => '0', underflow => NLW_U0_underflow_UNCONNECTED, valid => NLW_U0_valid_UNCONNECTED, wr_ack => NLW_U0_wr_ack_UNCONNECTED, wr_clk => wr_clk, wr_data_count(4 downto 0) => wr_data_count(4 downto 0), wr_en => wr_en, wr_rst => '0', wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED ); end STRUCTURE;