// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
// Date        : Mon May 13 11:50:50 2024
// Host        : atlas-tdaq-firmware-dev.cern.ch running 64-bit CentOS Linux release 7.9.2009 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /home/gitlab-runner/builds/z7w3GeU4/2/atlas-l1calo-efex/RODFirmware/Projects/rod_jfex/rod_jfex.gen/sources_1/ip/ila_ev_builder/ila_ev_builder_stub.v
// Design      : ila_ev_builder
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7vx550tffg1927-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ila,Vivado 2022.1" *)
module ila_ev_builder(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
  probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, 
  probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28, 
  probe29)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[5:0],probe1[4:0],probe2[4:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[0:0],probe14[23:0],probe15[0:0],probe16[11:0],probe17[0:0],probe18[0:0],probe19[15:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[15:0],probe25[63:0],probe26[0:0],probe27[0:0],probe28[15:0],probe29[31:0]" */;
  input clk;
  input [5:0]probe0;
  input [4:0]probe1;
  input [4:0]probe2;
  input [0:0]probe3;
  input [0:0]probe4;
  input [0:0]probe5;
  input [0:0]probe6;
  input [0:0]probe7;
  input [0:0]probe8;
  input [0:0]probe9;
  input [0:0]probe10;
  input [0:0]probe11;
  input [0:0]probe12;
  input [0:0]probe13;
  input [23:0]probe14;
  input [0:0]probe15;
  input [11:0]probe16;
  input [0:0]probe17;
  input [0:0]probe18;
  input [15:0]probe19;
  input [0:0]probe20;
  input [0:0]probe21;
  input [0:0]probe22;
  input [0:0]probe23;
  input [15:0]probe24;
  input [63:0]probe25;
  input [0:0]probe26;
  input [0:0]probe27;
  input [15:0]probe28;
  input [31:0]probe29;
endmodule
